--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_TICKLESS_IDLE 0\r
+#define configCPU_CLOCK_HZ ( SystemCoreClock )\r
+#define configTICK_RATE_HZ ( ( TickType_t ) 200 )\r
+#define configMAX_PRIORITIES 5\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 256 )\r
+#define configMAX_TASK_NAME_LEN 20\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_TASK_NOTIFICATIONS 1\r
+#define configUSE_MUTEXES 1\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */\r
+#define configQUEUE_REGISTRY_SIZE 8\r
+#define configUSE_QUEUE_SETS 0\r
+#define configUSE_TIME_SLICING 0\r
+#define configUSE_NEWLIB_REENTRANT 0\r
+#define configENABLE_BACKWARD_COMPATIBILITY 0\r
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5\r
+\r
+/* Used memory allocation (heap_x.c). */\r
+#define configFRTOS_MEMORY_SCHEME 4\r
+\r
+/* Tasks.c additions (e.g. Thread Aware Debug capability). */\r
+#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1\r
+\r
+/* Memory allocation related definitions. */\r
+#define configSUPPORT_STATIC_ALLOCATION 0\r
+#define configSUPPORT_DYNAMIC_ALLOCATION 1\r
+#define configTOTAL_HEAP_SIZE ( ( size_t )( 10 * 1024 ) )\r
+#define configAPPLICATION_ALLOCATED_HEAP 0\r
+\r
+/* Hook function related definitions. */\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCHECK_FOR_STACK_OVERFLOW 0\r
+#define configUSE_MALLOC_FAILED_HOOK 0\r
+#define configUSE_DAEMON_TASK_STARTUP_HOOK 0\r
+\r
+/* Run time and task stats gathering related definitions. */\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0\r
+\r
+/* Task aware debugging. */\r
+#define configRECORD_STACK_HIGH_ADDRESS 1\r
+\r
+/* Co-routine related definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES 2\r
+\r
+/* Software timer related definitions. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
+#define configTIMER_QUEUE_LENGTH 10\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/* Define to trap errors during development. */\r
+#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);}\r
+\r
+/* Optional functions - most linkers will remove unused functions anyway. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_xTaskGetSchedulerState 1\r
+#define INCLUDE_xTaskGetCurrentTaskHandle 1\r
+#define INCLUDE_uxTaskGetStackHighWaterMark 0\r
+#define INCLUDE_xTaskGetIdleTaskHandle 0\r
+#define INCLUDE_eTaskGetState 0\r
+#define INCLUDE_xTimerPendFunctionCall 1\r
+#define INCLUDE_xTaskAbortDelay 0\r
+#define INCLUDE_xTaskGetHandle 0\r
+#define INCLUDE_xTaskResumeFromISR 1\r
+\r
+#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__)\r
+ /* Clock manager provides in this variable system core clock frequency. */\r
+ #include <stdint.h>\r
+ extern uint32_t SystemCoreClock;\r
+#endif\r
+\r
+/* Interrupt nesting behaviour configuration. Cortex-M specific. */\r
+#ifdef __NVIC_PRIO_BITS\r
+/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */\r
+#define configPRIO_BITS __NVIC_PRIO_BITS\r
+#else\r
+#define configPRIO_BITS 3 /* 8 priority levels */\r
+#endif\r
+\r
+/* The lowest interrupt priority that can be used in a call to a "set priority"\r
+function. */\r
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1)\r
+\r
+/* The highest interrupt priority that can be used by any interrupt service\r
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL\r
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER\r
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */\r
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2\r
+\r
+/* Interrupt priorities used by the kernel port layer itself. These are generic\r
+to all Cortex-M ports, and do not rely on any particular library functions. */\r
+#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))\r
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\r
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))\r
+\r
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\r
+standard names. */\r
+#define vPortSVCHandler SVC_Handler\r
+#define xPortPendSVHandler PendSV_Handler\r
+#define xPortSysTickHandler SysTick_Handler\r
+\r
+/* Ensure that system calls can only be made from kernel code. */\r
+#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 1\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* BSP includes. */\r
+#include "board.h"\r
+#include "pin_mux.h"\r
+\r
+/* Demo includes. */\r
+#include "mpu_demo.h"\r
+\r
+/**\r
+ * @brief Performs board specific initialization.\r
+ */\r
+static void prvInitHardware( void );\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvInitHardware( void )\r
+{\r
+ /* Attach 12 MHz clock to FLEXCOMM0 (debug console). */\r
+ CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);\r
+\r
+ BOARD_InitPins();\r
+ BOARD_BootClockPLL180M();\r
+ BOARD_InitDebugConsole();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ /* Initialize hardware. */\r
+ prvInitHardware();\r
+\r
+ /* Start the MPU demo. */\r
+ vStartMPUDemo();\r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Should not get here. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )\r
+{\r
+ /* If configCHECK_FOR_STACK_OVERFLOW is set to either 1 or 2 then this\r
+ function will automatically get called if a task overflows its stack. */\r
+ ( void ) pxTask;\r
+ ( void ) pcTaskName;\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ /* If configUSE_MALLOC_FAILED_HOOK is set to 1 then this function will\r
+ be called automatically if a call to pvPortMalloc() fails. pvPortMalloc()\r
+ is called automatically when a task, queue or semaphore is created. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an\r
+implementation of vApplicationGetIdleTaskMemory() to provide the memory that is\r
+used by the Idle task. */\r
+void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )\r
+{\r
+/* If the buffers to be provided to the Idle task are declared inside this\r
+function then they must be declared static - otherwise they will be allocated on\r
+the stack and so not exists after this function exits. */\r
+static StaticTask_t xIdleTaskTCB;\r
+static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];\r
+\r
+ /* Pass out a pointer to the StaticTask_t structure in which the Idle task's\r
+ state will be stored. */\r
+ *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;\r
+\r
+ /* Pass out the array that will be used as the Idle task's stack. */\r
+ *ppxIdleTaskStackBuffer = uxIdleTaskStack;\r
+\r
+ /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.\r
+ Note that, as the array is necessarily of type StackType_t,\r
+ configMINIMAL_STACK_SIZE is specified in words, not bytes. */\r
+ *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the\r
+application must provide an implementation of vApplicationGetTimerTaskMemory()\r
+to provide the memory that is used by the Timer service task. */\r
+void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize )\r
+{\r
+/* If the buffers to be provided to the Timer task are declared inside this\r
+function then they must be declared static - otherwise they will be allocated on\r
+the stack and so not exists after this function exits. */\r
+static StaticTask_t xTimerTaskTCB;\r
+static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ];\r
+\r
+ /* Pass out a pointer to the StaticTask_t structure in which the Timer\r
+ task's state will be stored. */\r
+ *ppxTimerTaskTCBBuffer = &xTimerTaskTCB;\r
+\r
+ /* Pass out the array that will be used as the Timer task's stack. */\r
+ *ppxTimerTaskStackBuffer = uxTimerTaskStack;\r
+\r
+ /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.\r
+ Note that, as the array is necessarily of type StackType_t,\r
+ configMINIMAL_STACK_SIZE is specified in words, not bytes. */\r
+ *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/** ARMv7 MPU Details:\r
+ *\r
+ * - ARMv7 MPU requires that the size of a MPU region is a power of 2.\r
+ * - Smallest supported region size is 32 bytes.\r
+ * - Start address of a region must be aligned to an integer multiple of the\r
+ * region size. For example, if the region size is 4 KB(0x1000), the starting\r
+ * address must be N x 0x1000, where N is an integer.\r
+ */\r
+\r
+/**\r
+ * @brief Size of the shared memory region.\r
+ */\r
+#define SHARED_MEMORY_SIZE 32\r
+\r
+/**\r
+ * @brief Memory region shared between two tasks.\r
+ */\r
+static uint8_t ucSharedMemory[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) );\r
+\r
+/**\r
+ * @brief Memory region used to track Memory Fault intentionally caused by the\r
+ * RO Access task.\r
+ *\r
+ * RO Access task sets ucROTaskFaultTracker[ 0 ] to 1 before accessing illegal\r
+ * memory. Illegal memory access causes Memory Fault and the fault handler\r
+ * checks ucROTaskFaultTracker[ 0 ] to see if this is an expected fault. We\r
+ * recover gracefully from an expected fault by jumping to the next instruction.\r
+ *\r
+ * @note We are declaring a region of 32 bytes even though we need only one.\r
+ * The reason is that the smallest supported MPU region size is 32 bytes.\r
+ */\r
+static volatile uint8_t ucROTaskFaultTracker[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ) = { 0 };\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Implements the task which has Read Only access to the memory region\r
+ * ucSharedMemory.\r
+ *\r
+ * @param pvParameters[in] Parameters as passed during task creation.\r
+ */\r
+static void prvROAccessTask( void * pvParameters );\r
+\r
+/**\r
+ * @brief Implements the task which has Read Write access to the memory region\r
+ * ucSharedMemory.\r
+ *\r
+ * @param pvParameters[in] Parameters as passed during task creation.\r
+ */\r
+static void prvRWAccessTask( void * pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvROAccessTask( void * pvParameters )\r
+{\r
+uint8_t ucVal;\r
+\r
+ /* Unused parameters. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ; ; )\r
+ {\r
+ /* This task has RO access to ucSharedMemory and therefore it can read\r
+ * it but cannot modify it. */\r
+ ucVal = ucSharedMemory[ 0 ];\r
+\r
+ /* Silent compiler warnings about unused variables. */\r
+ ( void ) ucVal;\r
+\r
+ /* Since this task has Read Only access to the ucSharedMemory region,\r
+ * writing to it results in Memory Fault. Set ucROTaskFaultTracker[ 0 ]\r
+ * to 1 to tell the Memory Fault Handler that this is an expected fault.\r
+ * The handler will recover from this fault gracefully by jumping to the\r
+ * next instruction. */\r
+ ucROTaskFaultTracker[ 0 ] = 1;\r
+\r
+ /* Illegal access to generate Memory Fault. */\r
+ ucSharedMemory[ 0 ] = 0;\r
+\r
+ /* Ensure that the above line did generate MemFault and the fault\r
+ * handler did clear the ucROTaskFaultTracker[ 0 ]. */\r
+ configASSERT( ucROTaskFaultTracker[ 0 ] == 0 );\r
+\r
+ #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )\r
+ {\r
+ /* Generate an SVC to raise the privilege. Since privilege\r
+ * escalation is only allowed from kernel code, this request must\r
+ * get rejected and the task must remain unprivileged. As a result,\r
+ * trying to write to ucSharedMemory will still result in Memory\r
+ * Fault. */\r
+ portRAISE_PRIVILEGE();\r
+\r
+ /* Set ucROTaskFaultTracker[ 0 ] to 1 to tell the Memory Fault\r
+ * Handler that this is an expected fault. The handler will then be\r
+ * able to recover from this fault gracefully by jumping to the\r
+ * next instruction.*/\r
+ ucROTaskFaultTracker[ 0 ] = 1;\r
+\r
+ /* The following must still result in Memory Fault since the task\r
+ * is still running unprivileged. */\r
+ ucSharedMemory[ 0 ] = 0;\r
+\r
+ /* Ensure that the above line did generate MemFault and the fault\r
+ * handler did clear the ucROTaskFaultTracker[ 0 ]. */\r
+ configASSERT( ucROTaskFaultTracker[ 0 ] == 0 );\r
+ }\r
+ #else\r
+ {\r
+ /* Generate an SVC to raise the privilege. Since\r
+ * configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not enabled, the\r
+ * task will be able to escalate privilege. */\r
+ portRAISE_PRIVILEGE();\r
+\r
+ /* At this point, the task is running privileged. The following\r
+ * access must not result in Memory Fault. If something goes\r
+ * wrong and we do get a fault, the execution will stop in fault\r
+ * handler as ucROTaskFaultTracker[ 0 ] is not set (i.e.\r
+ * un-expected fault). */\r
+ ucSharedMemory[ 0 ] = 0;\r
+\r
+ /* Lower down the privilege. */\r
+ portSWITCH_TO_USER_MODE();\r
+\r
+ /* Now the task is running unprivileged and therefore an attempt to\r
+ * write to ucSharedMemory will result in a Memory Fault. Set\r
+ * ucROTaskFaultTracker[ 0 ] to 1 to tell the Memory Fault Handler\r
+ * that this is an expected fault. The handler will then be able to\r
+ * recover from this fault gracefully by jumping to the next\r
+ * instruction.*/\r
+ ucROTaskFaultTracker[ 0 ] = 1;\r
+\r
+ /* The following must result in Memory Fault since the task is now\r
+ * running unprivileged. */\r
+ ucSharedMemory[ 0 ] = 0;\r
+\r
+ /* Ensure that the above line did generate MemFault and the fault\r
+ * handler did clear the ucROTaskFaultTracker[ 0 ]. */\r
+ configASSERT( ucROTaskFaultTracker[ 0 ] == 0 );\r
+ }\r
+ #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */\r
+\r
+ /* Wait for a second. */\r
+ vTaskDelay( pdMS_TO_TICKS( 1000 ) );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvRWAccessTask( void * pvParameters )\r
+{\r
+ /* Unused parameters. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ; ; )\r
+ {\r
+ /* This task has RW access to ucSharedMemory and therefore can write to\r
+ * it. */\r
+ ucSharedMemory[ 0 ] = 0;\r
+\r
+ /* Wait for a second. */\r
+ vTaskDelay( pdMS_TO_TICKS( 1000 ) );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartMPUDemo( void )\r
+{\r
+/**\r
+ * Since stack of a task is protected using MPU, it must satisfy MPU\r
+ * requirements as mentioned at the top of this file.\r
+ */\r
+static StackType_t xROAccessTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) ) ) );\r
+static StackType_t xRWAccessTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) ) ) );\r
+TaskParameters_t xROAccessTaskParameters =\r
+{\r
+ .pvTaskCode = prvROAccessTask,\r
+ .pcName = "ROAccess",\r
+ .usStackDepth = configMINIMAL_STACK_SIZE,\r
+ .pvParameters = NULL,\r
+ .uxPriority = tskIDLE_PRIORITY,\r
+ .puxStackBuffer = xROAccessTaskStack,\r
+ .xRegions = {\r
+ { ucSharedMemory, SHARED_MEMORY_SIZE, portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY | portMPU_REGION_EXECUTE_NEVER },\r
+ { ( void * ) ucROTaskFaultTracker, SHARED_MEMORY_SIZE, portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER },\r
+ { 0, 0, 0 },\r
+ }\r
+};\r
+TaskParameters_t xRWAccessTaskParameters =\r
+{\r
+ .pvTaskCode = prvRWAccessTask,\r
+ .pcName = "RWAccess",\r
+ .usStackDepth = configMINIMAL_STACK_SIZE,\r
+ .pvParameters = NULL,\r
+ .uxPriority = tskIDLE_PRIORITY,\r
+ .puxStackBuffer = xRWAccessTaskStack,\r
+ .xRegions = {\r
+ { ucSharedMemory, SHARED_MEMORY_SIZE, portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER},\r
+ { 0, 0, 0 },\r
+ { 0, 0, 0 },\r
+ }\r
+};\r
+\r
+ /* Create an unprivileged task with RO access to ucSharedMemory. */\r
+ xTaskCreateRestricted( &( xROAccessTaskParameters ), NULL );\r
+\r
+ /* Create an unprivileged task with RW access to ucSharedMemory. */\r
+ xTaskCreateRestricted( &( xRWAccessTaskParameters ), NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portDONT_DISCARD void vHandleMemoryFault( uint32_t * pulFaultStackAddress )\r
+{\r
+uint32_t ulPC;\r
+uint16_t usOffendingInstruction;\r
+\r
+ /* Is this an expected fault? */\r
+ if( ucROTaskFaultTracker[ 0 ] == 1 )\r
+ {\r
+ /* Read program counter. */\r
+ ulPC = pulFaultStackAddress[ 6 ];\r
+\r
+ /* Read the offending instruction. */\r
+ usOffendingInstruction = *( uint16_t * )ulPC;\r
+\r
+ /* From ARM docs:\r
+ * If the value of bits[15:11] of the halfword being decoded is one of\r
+ * the following, the halfword is the first halfword of a 32-bit\r
+ * instruction:\r
+ * - 0b11101.\r
+ * - 0b11110.\r
+ * - 0b11111.\r
+ * Otherwise, the halfword is a 16-bit instruction.\r
+ */\r
+\r
+ /* Extract bits[15:11] of the offending instruction. */\r
+ usOffendingInstruction = usOffendingInstruction & 0xF800;\r
+ usOffendingInstruction = ( usOffendingInstruction >> 11 );\r
+\r
+ /* Determine if the offending instruction is a 32-bit instruction or\r
+ * a 16-bit instruction. */\r
+ if( usOffendingInstruction == 0x001F ||\r
+ usOffendingInstruction == 0x001E ||\r
+ usOffendingInstruction == 0x001D )\r
+ {\r
+ /* Since the offending instruction is a 32-bit instruction,\r
+ * increment the program counter by 4 to move to the next\r
+ * instruction. */\r
+ ulPC += 4;\r
+ }\r
+ else\r
+ {\r
+ /* Since the offending instruction is a 16-bit instruction,\r
+ * increment the program counter by 2 to move to the next\r
+ * instruction. */\r
+ ulPC += 2;\r
+ }\r
+\r
+ /* Save the new program counter on the stack. */\r
+ pulFaultStackAddress[ 6 ] = ulPC;\r
+\r
+ /* Mark the fault as handled. */\r
+ ucROTaskFaultTracker[ 0 ] = 0;\r
+ }\r
+ else\r
+ {\r
+ /* This is an unexpected fault - loop forever. */\r
+ for( ; ; )\r
+ {\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __MPU_DEMO_H__\r
+#define __MPU_DEMO_H__\r
+\r
+/**\r
+ * @brief Creates all the tasks for MPU demo.\r
+ *\r
+ * The MPU demo creates 2 unprivileged tasks - One of which has Read Only access\r
+ * to a shared memory region while the other has Read Write access. The task\r
+ * with Read Only access then tries to write to the shared memory which results\r
+ * in a Memory fault. The fault handler examines that it is the fault generated\r
+ * by the task with Read Only access and if so, it recovers from the fault\r
+ * greacefully by moving the Program Counter to the next instruction to the one\r
+ * which generated the fault. If any other memory access violation occurs, the\r
+ * fault handler will get stuck in an inifinite loop.\r
+ */\r
+void vStartMPUDemo( void );\r
+\r
+#endif /* __MPU_DEMO_H__ */\r
--- /dev/null
+/* ----------------------------------------------------------------------\r
+ * Project: CMSIS DSP Library\r
+ * Title: arm_common_tables.h\r
+ * Description: Extern declaration for common tables\r
+ *\r
+ * $Date: 27. January 2017\r
+ * $Revision: V.1.5.1\r
+ *\r
+ * Target Processor: Cortex-M cores\r
+ * -------------------------------------------------------------------- */\r
+/*\r
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#ifndef _ARM_COMMON_TABLES_H\r
+#define _ARM_COMMON_TABLES_H\r
+\r
+#include "arm_math.h"\r
+\r
+extern const uint16_t armBitRevTable[1024];\r
+extern const q15_t armRecipTableQ15[64];\r
+extern const q31_t armRecipTableQ31[64];\r
+extern const float32_t twiddleCoef_16[32];\r
+extern const float32_t twiddleCoef_32[64];\r
+extern const float32_t twiddleCoef_64[128];\r
+extern const float32_t twiddleCoef_128[256];\r
+extern const float32_t twiddleCoef_256[512];\r
+extern const float32_t twiddleCoef_512[1024];\r
+extern const float32_t twiddleCoef_1024[2048];\r
+extern const float32_t twiddleCoef_2048[4096];\r
+extern const float32_t twiddleCoef_4096[8192];\r
+#define twiddleCoef twiddleCoef_4096\r
+extern const q31_t twiddleCoef_16_q31[24];\r
+extern const q31_t twiddleCoef_32_q31[48];\r
+extern const q31_t twiddleCoef_64_q31[96];\r
+extern const q31_t twiddleCoef_128_q31[192];\r
+extern const q31_t twiddleCoef_256_q31[384];\r
+extern const q31_t twiddleCoef_512_q31[768];\r
+extern const q31_t twiddleCoef_1024_q31[1536];\r
+extern const q31_t twiddleCoef_2048_q31[3072];\r
+extern const q31_t twiddleCoef_4096_q31[6144];\r
+extern const q15_t twiddleCoef_16_q15[24];\r
+extern const q15_t twiddleCoef_32_q15[48];\r
+extern const q15_t twiddleCoef_64_q15[96];\r
+extern const q15_t twiddleCoef_128_q15[192];\r
+extern const q15_t twiddleCoef_256_q15[384];\r
+extern const q15_t twiddleCoef_512_q15[768];\r
+extern const q15_t twiddleCoef_1024_q15[1536];\r
+extern const q15_t twiddleCoef_2048_q15[3072];\r
+extern const q15_t twiddleCoef_4096_q15[6144];\r
+extern const float32_t twiddleCoef_rfft_32[32];\r
+extern const float32_t twiddleCoef_rfft_64[64];\r
+extern const float32_t twiddleCoef_rfft_128[128];\r
+extern const float32_t twiddleCoef_rfft_256[256];\r
+extern const float32_t twiddleCoef_rfft_512[512];\r
+extern const float32_t twiddleCoef_rfft_1024[1024];\r
+extern const float32_t twiddleCoef_rfft_2048[2048];\r
+extern const float32_t twiddleCoef_rfft_4096[4096];\r
+\r
+/* floating-point bit reversal tables */\r
+#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)\r
+#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)\r
+#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)\r
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)\r
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)\r
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)\r
+#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)\r
+#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)\r
+#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)\r
+\r
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];\r
+\r
+/* fixed-point bit reversal tables */\r
+#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)\r
+#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)\r
+#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)\r
+#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)\r
+#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)\r
+#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)\r
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)\r
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)\r
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)\r
+\r
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];\r
+\r
+/* Tables for Fast Math Sine and Cosine */\r
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];\r
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];\r
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];\r
+\r
+#endif /* ARM_COMMON_TABLES_H */\r
--- /dev/null
+/* ----------------------------------------------------------------------\r
+ * Project: CMSIS DSP Library\r
+ * Title: arm_const_structs.h\r
+ * Description: Constant structs that are initialized for user convenience.\r
+ * For example, some can be given as arguments to the arm_cfft_f32() function.\r
+ *\r
+ * $Date: 27. January 2017\r
+ * $Revision: V.1.5.1\r
+ *\r
+ * Target Processor: Cortex-M cores\r
+ * -------------------------------------------------------------------- */\r
+/*\r
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#ifndef _ARM_CONST_STRUCTS_H\r
+#define _ARM_CONST_STRUCTS_H\r
+\r
+#include "arm_math.h"\r
+#include "arm_common_tables.h"\r
+\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;\r
+\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;\r
+\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;\r
+\r
+#endif\r
--- /dev/null
+/******************************************************************************\r
+ * @file arm_math.h\r
+ * @brief Public header file for CMSIS DSP Library\r
+ * @version V1.6.0\r
+ * @date 18. March 2019\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+/**\r
+ \mainpage CMSIS DSP Software Library\r
+ *\r
+ * Introduction\r
+ * ------------\r
+ *\r
+ * This user manual describes the CMSIS DSP software library,\r
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.\r
+ *\r
+ * The library is divided into a number of functions each covering a specific category:\r
+ * - Basic math functions\r
+ * - Fast math functions\r
+ * - Complex math functions\r
+ * - Filters\r
+ * - Matrix functions\r
+ * - Transform functions\r
+ * - Motor control functions\r
+ * - Statistical functions\r
+ * - Support functions\r
+ * - Interpolation functions\r
+ *\r
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,\r
+ * 32-bit integer and 32-bit floating-point values.\r
+ *\r
+ * Using the Library\r
+ * ------------\r
+ *\r
+ * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.\r
+ * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)\r
+ * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)\r
+ * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)\r
+ * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)\r
+ * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)\r
+ * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)\r
+ * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)\r
+ * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)\r
+ * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)\r
+ * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)\r
+ * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)\r
+ * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)\r
+ * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)\r
+ * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)\r
+ * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian)\r
+ * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian)\r
+ * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit)\r
+ * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions)\r
+ * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)\r
+ *\r
+ * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.\r
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single\r
+ * public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.\r
+ *\r
+ *\r
+ * Examples\r
+ * --------\r
+ *\r
+ * The library ships with a number of examples which demonstrate how to use the library functions.\r
+ *\r
+ * Toolchain Support\r
+ * ------------\r
+ *\r
+ * The library has been developed and tested with MDK version 5.14.0.0\r
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.\r
+ *\r
+ * Building the Library\r
+ * ------------\r
+ *\r
+ * The library installer contains a project file to rebuild libraries on MDK toolchain in the <code>CMSIS\\DSP\\Projects\\ARM</code> folder.\r
+ * - arm_cortexM_math.uvprojx\r
+ *\r
+ *\r
+ * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above.\r
+ *\r
+ * Preprocessor Macros\r
+ * ------------\r
+ *\r
+ * Each library project have different preprocessor macros.\r
+ *\r
+ * - ARM_MATH_BIG_ENDIAN:\r
+ *\r
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.\r
+ *\r
+ * - ARM_MATH_MATRIX_CHECK:\r
+ *\r
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices\r
+ *\r
+ * - ARM_MATH_ROUNDING:\r
+ *\r
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions\r
+ *\r
+ * - ARM_MATH_LOOPUNROLL:\r
+ *\r
+ * Define macro ARM_MATH_LOOPUNROLL to enable manual loop unrolling in DSP functions\r
+ *\r
+ * <hr>\r
+ * CMSIS-DSP in ARM::CMSIS Pack\r
+ * -----------------------------\r
+ *\r
+ * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:\r
+ * |File/Folder |Content |\r
+ * |---------------------------------|------------------------------------------------------------------------|\r
+ * |\b CMSIS\\Documentation\\DSP | This documentation |\r
+ * |\b CMSIS\\DSP\\DSP_Lib_TestSuite | DSP_Lib test suite |\r
+ * |\b CMSIS\\DSP\\Examples | Example projects demonstrating the usage of the library functions |\r
+ * |\b CMSIS\\DSP\\Include | DSP_Lib include files |\r
+ * |\b CMSIS\\DSP\\Lib | DSP_Lib binaries |\r
+ * |\b CMSIS\\DSP\\Projects | Projects to rebuild DSP_Lib binaries |\r
+ * |\b CMSIS\\DSP\\Source | DSP_Lib source files |\r
+ *\r
+ * <hr>\r
+ * Revision History of CMSIS-DSP\r
+ * ------------\r
+ * Please refer to \ref ChangeLog_pg.\r
+ */\r
+\r
+\r
+/**\r
+ * @defgroup groupMath Basic Math Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupFastMath Fast Math Functions\r
+ * This set of functions provides a fast approximation to sine, cosine, and square root.\r
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions\r
+ * operate on individual values and not arrays.\r
+ * There are separate functions for Q15, Q31, and floating-point data.\r
+ *\r
+ */\r
+\r
+/**\r
+ * @defgroup groupCmplxMath Complex Math Functions\r
+ * This set of functions operates on complex data vectors.\r
+ * The data in the complex arrays is stored in an interleaved fashion\r
+ * (real, imag, real, imag, ...).\r
+ * In the API functions, the number of samples in a complex array refers\r
+ * to the number of complex values; the array contains twice this number of\r
+ * real values.\r
+ */\r
+\r
+/**\r
+ * @defgroup groupFilters Filtering Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupMatrix Matrix Functions\r
+ *\r
+ * This set of functions provides basic matrix math operations.\r
+ * The functions operate on matrix data structures. For example,\r
+ * the type\r
+ * definition for the floating-point matrix structure is shown\r
+ * below:\r
+ * <pre>\r
+ * typedef struct\r
+ * {\r
+ * uint16_t numRows; // number of rows of the matrix.\r
+ * uint16_t numCols; // number of columns of the matrix.\r
+ * float32_t *pData; // points to the data of the matrix.\r
+ * } arm_matrix_instance_f32;\r
+ * </pre>\r
+ * There are similar definitions for Q15 and Q31 data types.\r
+ *\r
+ * The structure specifies the size of the matrix and then points to\r
+ * an array of data. The array is of size <code>numRows X numCols</code>\r
+ * and the values are arranged in row order. That is, the\r
+ * matrix element (i, j) is stored at:\r
+ * <pre>\r
+ * pData[i*numCols + j]\r
+ * </pre>\r
+ *\r
+ * \par Init Functions\r
+ * There is an associated initialization function for each type of matrix\r
+ * data structure.\r
+ * The initialization function sets the values of the internal structure fields.\r
+ * Refer to \ref arm_mat_init_f32(), \ref arm_mat_init_q31() and \ref arm_mat_init_q15()\r
+ * for floating-point, Q31 and Q15 types, respectively.\r
+ *\r
+ * \par\r
+ * Use of the initialization function is optional. However, if initialization function is used\r
+ * then the instance structure cannot be placed into a const data section.\r
+ * To place the instance structure in a const data\r
+ * section, manually initialize the data structure. For example:\r
+ * <pre>\r
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>\r
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>\r
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>\r
+ * </pre>\r
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>\r
+ * specifies the number of columns, and <code>pData</code> points to the\r
+ * data array.\r
+ *\r
+ * \par Size Checking\r
+ * By default all of the matrix functions perform size checking on the input and\r
+ * output matrices. For example, the matrix addition function verifies that the\r
+ * two input matrices and the output matrix all have the same number of rows and\r
+ * columns. If the size check fails the functions return:\r
+ * <pre>\r
+ * ARM_MATH_SIZE_MISMATCH\r
+ * </pre>\r
+ * Otherwise the functions return\r
+ * <pre>\r
+ * ARM_MATH_SUCCESS\r
+ * </pre>\r
+ * There is some overhead associated with this matrix size checking.\r
+ * The matrix size checking is enabled via the \#define\r
+ * <pre>\r
+ * ARM_MATH_MATRIX_CHECK\r
+ * </pre>\r
+ * within the library project settings. By default this macro is defined\r
+ * and size checking is enabled. By changing the project settings and\r
+ * undefining this macro size checking is eliminated and the functions\r
+ * run a bit faster. With size checking disabled the functions always\r
+ * return <code>ARM_MATH_SUCCESS</code>.\r
+ */\r
+\r
+/**\r
+ * @defgroup groupTransforms Transform Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupController Controller Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupStats Statistics Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupSupport Support Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupInterpolation Interpolation Functions\r
+ * These functions perform 1- and 2-dimensional interpolation of data.\r
+ * Linear interpolation is used for 1-dimensional data and\r
+ * bilinear interpolation is used for 2-dimensional data.\r
+ */\r
+\r
+/**\r
+ * @defgroup groupExamples Examples\r
+ */\r
+\r
+\r
+#ifndef _ARM_MATH_H\r
+#define _ARM_MATH_H\r
+\r
+/* Compiler specific diagnostic adjustment */\r
+#if defined ( __CC_ARM )\r
+\r
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )\r
+\r
+#elif defined ( __GNUC__ )\r
+ #pragma GCC diagnostic push\r
+ #pragma GCC diagnostic ignored "-Wsign-conversion"\r
+ #pragma GCC diagnostic ignored "-Wconversion"\r
+ #pragma GCC diagnostic ignored "-Wunused-parameter"\r
+\r
+#elif defined ( __ICCARM__ )\r
+\r
+#elif defined ( __TI_ARM__ )\r
+\r
+#elif defined ( __CSMC__ )\r
+\r
+#elif defined ( __TASKING__ )\r
+\r
+#else\r
+ #error Unknown compiler\r
+#endif\r
+\r
+\r
+#include "cmsis_compiler.h"\r
+#include "string.h"\r
+#include "math.h"\r
+\r
+/* evaluate ARM architecture */\r
+#if defined (__ARM_ARCH_6M__)\r
+ #define ARM_MATH_CM0_FAMILY 1\r
+#elif defined (__ARM_ARCH_7M__)\r
+//#define ARM_MATH_CM0_FAMILY 0\r
+#elif defined (__ARM_ARCH_7EM__)\r
+//#define ARM_MATH_CM0_FAMILY 0\r
+#elif defined (__ARM_ARCH_8M_BASE__)\r
+ #define ARM_MATH_CM0_FAMILY 1\r
+#elif defined (__ARM_ARCH_8M_MAIN__)\r
+//#define ARM_MATH_CM0_FAMILY 0\r
+#else\r
+ #error "Unknown Arm Architecture!"\r
+#endif\r
+\r
+/* evaluate ARM DSP feature */\r
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\r
+ #define ARM_MATH_DSP 1\r
+#endif\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+ /**\r
+ * @brief Macros required for reciprocal calculation in Normalized LMS\r
+ */\r
+\r
+#define DELTA_Q31 (0x100)\r
+#define DELTA_Q15 0x5\r
+#define INDEX_MASK 0x0000003F\r
+#ifndef PI\r
+ #define PI 3.14159265358979f\r
+#endif\r
+\r
+ /**\r
+ * @brief Macros required for SINE and COSINE Fast math approximations\r
+ */\r
+\r
+#define FAST_MATH_TABLE_SIZE 512\r
+#define FAST_MATH_Q31_SHIFT (32 - 10)\r
+#define FAST_MATH_Q15_SHIFT (16 - 10)\r
+#define CONTROLLER_Q31_SHIFT (32 - 9)\r
+#define TABLE_SPACING_Q31 0x400000\r
+#define TABLE_SPACING_Q15 0x80\r
+\r
+ /**\r
+ * @brief Macros required for SINE and COSINE Controller functions\r
+ */\r
+ /* 1.31(q31) Fixed value of 2/360 */\r
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */\r
+#define INPUT_SPACING 0xB60B61\r
+\r
+\r
+ /**\r
+ * @brief Error status returned by some functions in the library.\r
+ */\r
+\r
+ typedef enum\r
+ {\r
+ ARM_MATH_SUCCESS = 0, /**< No error */\r
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */\r
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */\r
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation */\r
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */\r
+ ARM_MATH_SINGULAR = -5, /**< Input matrix is singular and cannot be inverted */\r
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */\r
+ } arm_status;\r
+\r
+ /**\r
+ * @brief 8-bit fractional data type in 1.7 format.\r
+ */\r
+ typedef int8_t q7_t;\r
+\r
+ /**\r
+ * @brief 16-bit fractional data type in 1.15 format.\r
+ */\r
+ typedef int16_t q15_t;\r
+\r
+ /**\r
+ * @brief 32-bit fractional data type in 1.31 format.\r
+ */\r
+ typedef int32_t q31_t;\r
+\r
+ /**\r
+ * @brief 64-bit fractional data type in 1.63 format.\r
+ */\r
+ typedef int64_t q63_t;\r
+\r
+ /**\r
+ * @brief 32-bit floating-point type definition.\r
+ */\r
+ typedef float float32_t;\r
+\r
+ /**\r
+ * @brief 64-bit floating-point type definition.\r
+ */\r
+ typedef double float64_t;\r
+\r
+\r
+/**\r
+ @brief definition to read/write two 16 bit values.\r
+ @deprecated\r
+ */\r
+#if defined ( __CC_ARM )\r
+ #define __SIMD32_TYPE int32_t __packed\r
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )\r
+ #define __SIMD32_TYPE int32_t\r
+#elif defined ( __GNUC__ )\r
+ #define __SIMD32_TYPE int32_t\r
+#elif defined ( __ICCARM__ )\r
+ #define __SIMD32_TYPE int32_t __packed\r
+#elif defined ( __TI_ARM__ )\r
+ #define __SIMD32_TYPE int32_t\r
+#elif defined ( __CSMC__ )\r
+ #define __SIMD32_TYPE int32_t\r
+#elif defined ( __TASKING__ )\r
+ #define __SIMD32_TYPE __unaligned int32_t\r
+#else\r
+ #error Unknown compiler\r
+#endif\r
+\r
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))\r
+#define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr))\r
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr))\r
+#define __SIMD64(addr) (*( int64_t **) & (addr))\r
+\r
+/* SIMD replacement */\r
+\r
+/**\r
+ @brief Read 2 Q15 from Q15 pointer.\r
+ @param[in] pQ15 points to input value\r
+ @return Q31 value\r
+ */\r
+__STATIC_FORCEINLINE q31_t read_q15x2 (\r
+ q15_t * pQ15)\r
+{\r
+ q31_t val;\r
+\r
+ memcpy (&val, pQ15, 4);\r
+\r
+ return (val);\r
+}\r
+\r
+/**\r
+ @brief Read 2 Q15 from Q15 pointer and increment pointer afterwards.\r
+ @param[in] pQ15 points to input value\r
+ @return Q31 value\r
+ */\r
+__STATIC_FORCEINLINE q31_t read_q15x2_ia (\r
+ q15_t ** pQ15)\r
+{\r
+ q31_t val;\r
+\r
+ memcpy (&val, *pQ15, 4);\r
+ *pQ15 += 2;\r
+\r
+ return (val);\r
+}\r
+\r
+/**\r
+ @brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards.\r
+ @param[in] pQ15 points to input value\r
+ @return Q31 value\r
+ */\r
+__STATIC_FORCEINLINE q31_t read_q15x2_da (\r
+ q15_t ** pQ15)\r
+{\r
+ q31_t val;\r
+\r
+ memcpy (&val, *pQ15, 4);\r
+ *pQ15 -= 2;\r
+\r
+ return (val);\r
+}\r
+\r
+/**\r
+ @brief Write 2 Q15 to Q15 pointer and increment pointer afterwards.\r
+ @param[in] pQ15 points to input value\r
+ @param[in] value Q31 value\r
+ @return none\r
+ */\r
+__STATIC_FORCEINLINE void write_q15x2_ia (\r
+ q15_t ** pQ15,\r
+ q31_t value)\r
+{\r
+ q31_t val = value;\r
+\r
+ memcpy (*pQ15, &val, 4);\r
+ *pQ15 += 2;\r
+}\r
+\r
+/**\r
+ @brief Write 2 Q15 to Q15 pointer.\r
+ @param[in] pQ15 points to input value\r
+ @param[in] value Q31 value\r
+ @return none\r
+ */\r
+__STATIC_FORCEINLINE void write_q15x2 (\r
+ q15_t * pQ15,\r
+ q31_t value)\r
+{\r
+ q31_t val = value;\r
+\r
+ memcpy (pQ15, &val, 4);\r
+}\r
+\r
+\r
+/**\r
+ @brief Read 4 Q7 from Q7 pointer and increment pointer afterwards.\r
+ @param[in] pQ7 points to input value\r
+ @return Q31 value\r
+ */\r
+__STATIC_FORCEINLINE q31_t read_q7x4_ia (\r
+ q7_t ** pQ7)\r
+{\r
+ q31_t val;\r
+\r
+ memcpy (&val, *pQ7, 4);\r
+ *pQ7 += 4;\r
+\r
+ return (val);\r
+}\r
+\r
+/**\r
+ @brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards.\r
+ @param[in] pQ7 points to input value\r
+ @return Q31 value\r
+ */\r
+__STATIC_FORCEINLINE q31_t read_q7x4_da (\r
+ q7_t ** pQ7)\r
+{\r
+ q31_t val;\r
+\r
+ memcpy (&val, *pQ7, 4);\r
+ *pQ7 -= 4;\r
+\r
+ return (val);\r
+}\r
+\r
+/**\r
+ @brief Write 4 Q7 to Q7 pointer and increment pointer afterwards.\r
+ @param[in] pQ7 points to input value\r
+ @param[in] value Q31 value\r
+ @return none\r
+ */\r
+__STATIC_FORCEINLINE void write_q7x4_ia (\r
+ q7_t ** pQ7,\r
+ q31_t value)\r
+{\r
+ q31_t val = value;\r
+\r
+ memcpy (*pQ7, &val, 4);\r
+ *pQ7 += 4;\r
+}\r
+\r
+\r
+#ifndef ARM_MATH_DSP\r
+ /**\r
+ * @brief definition to pack two 16 bit values.\r
+ */\r
+ #define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \\r
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )\r
+ #define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \\r
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )\r
+#endif\r
+\r
+ /**\r
+ * @brief definition to pack four 8 bit values.\r
+ */\r
+#ifndef ARM_MATH_BIG_ENDIAN\r
+ #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \\r
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \\r
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \\r
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )\r
+#else\r
+ #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \\r
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \\r
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \\r
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )\r
+#endif\r
+\r
+\r
+ /**\r
+ * @brief Clips Q63 to Q31 values.\r
+ */\r
+ __STATIC_FORCEINLINE q31_t clip_q63_to_q31(\r
+ q63_t x)\r
+ {\r
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;\r
+ }\r
+\r
+ /**\r
+ * @brief Clips Q63 to Q15 values.\r
+ */\r
+ __STATIC_FORCEINLINE q15_t clip_q63_to_q15(\r
+ q63_t x)\r
+ {\r
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);\r
+ }\r
+\r
+ /**\r
+ * @brief Clips Q31 to Q7 values.\r
+ */\r
+ __STATIC_FORCEINLINE q7_t clip_q31_to_q7(\r
+ q31_t x)\r
+ {\r
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?\r
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;\r
+ }\r
+\r
+ /**\r
+ * @brief Clips Q31 to Q15 values.\r
+ */\r
+ __STATIC_FORCEINLINE q15_t clip_q31_to_q15(\r
+ q31_t x)\r
+ {\r
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?\r
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;\r
+ }\r
+\r
+ /**\r
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.\r
+ */\r
+ __STATIC_FORCEINLINE q63_t mult32x64(\r
+ q63_t x,\r
+ q31_t y)\r
+ {\r
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +\r
+ (((q63_t) (x >> 32) * y) ) );\r
+ }\r
+\r
+ /**\r
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.\r
+ */\r
+ __STATIC_FORCEINLINE uint32_t arm_recip_q31(\r
+ q31_t in,\r
+ q31_t * dst,\r
+ const q31_t * pRecipTable)\r
+ {\r
+ q31_t out;\r
+ uint32_t tempVal;\r
+ uint32_t index, i;\r
+ uint32_t signBits;\r
+\r
+ if (in > 0)\r
+ {\r
+ signBits = ((uint32_t) (__CLZ( in) - 1));\r
+ }\r
+ else\r
+ {\r
+ signBits = ((uint32_t) (__CLZ(-in) - 1));\r
+ }\r
+\r
+ /* Convert input sample to 1.31 format */\r
+ in = (in << signBits);\r
+\r
+ /* calculation of index for initial approximated Val */\r
+ index = (uint32_t)(in >> 24);\r
+ index = (index & INDEX_MASK);\r
+\r
+ /* 1.31 with exp 1 */\r
+ out = pRecipTable[index];\r
+\r
+ /* calculation of reciprocal value */\r
+ /* running approximation for two iterations */\r
+ for (i = 0U; i < 2U; i++)\r
+ {\r
+ tempVal = (uint32_t) (((q63_t) in * out) >> 31);\r
+ tempVal = 0x7FFFFFFFu - tempVal;\r
+ /* 1.31 with exp 1 */\r
+ /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */\r
+ out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);\r
+ }\r
+\r
+ /* write output */\r
+ *dst = out;\r
+\r
+ /* return num of signbits of out = 1/in value */\r
+ return (signBits + 1U);\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.\r
+ */\r
+ __STATIC_FORCEINLINE uint32_t arm_recip_q15(\r
+ q15_t in,\r
+ q15_t * dst,\r
+ const q15_t * pRecipTable)\r
+ {\r
+ q15_t out = 0;\r
+ uint32_t tempVal = 0;\r
+ uint32_t index = 0, i = 0;\r
+ uint32_t signBits = 0;\r
+\r
+ if (in > 0)\r
+ {\r
+ signBits = ((uint32_t)(__CLZ( in) - 17));\r
+ }\r
+ else\r
+ {\r
+ signBits = ((uint32_t)(__CLZ(-in) - 17));\r
+ }\r
+\r
+ /* Convert input sample to 1.15 format */\r
+ in = (in << signBits);\r
+\r
+ /* calculation of index for initial approximated Val */\r
+ index = (uint32_t)(in >> 8);\r
+ index = (index & INDEX_MASK);\r
+\r
+ /* 1.15 with exp 1 */\r
+ out = pRecipTable[index];\r
+\r
+ /* calculation of reciprocal value */\r
+ /* running approximation for two iterations */\r
+ for (i = 0U; i < 2U; i++)\r
+ {\r
+ tempVal = (uint32_t) (((q31_t) in * out) >> 15);\r
+ tempVal = 0x7FFFu - tempVal;\r
+ /* 1.15 with exp 1 */\r
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);\r
+ /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */\r
+ }\r
+\r
+ /* write output */\r
+ *dst = out;\r
+\r
+ /* return num of signbits of out = 1/in value */\r
+ return (signBits + 1);\r
+ }\r
+\r
+\r
+/*\r
+ * @brief C custom defined intrinsic functions\r
+ */\r
+#if !defined (ARM_MATH_DSP)\r
+\r
+ /*\r
+ * @brief C custom defined QADD8\r
+ */\r
+ __STATIC_FORCEINLINE uint32_t __QADD8(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ q31_t r, s, t, u;\r
+\r
+ r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;\r
+ s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;\r
+ t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;\r
+ u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;\r
+\r
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined QSUB8\r
+ */\r
+ __STATIC_FORCEINLINE uint32_t __QSUB8(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ q31_t r, s, t, u;\r
+\r
+ r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;\r
+ s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;\r
+ t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;\r
+ u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;\r
+\r
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined QADD16\r
+ */\r
+ __STATIC_FORCEINLINE uint32_t __QADD16(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */\r
+ q31_t r = 0, s = 0;\r
+\r
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;\r
+\r
+ return ((uint32_t)((s << 16) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SHADD16\r
+ */\r
+ __STATIC_FORCEINLINE uint32_t __SHADD16(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ q31_t r, s;\r
+\r
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
+\r
+ return ((uint32_t)((s << 16) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined QSUB16\r
+ */\r
+ __STATIC_FORCEINLINE uint32_t __QSUB16(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ q31_t r, s;\r
+\r
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;\r
+\r
+ return ((uint32_t)((s << 16) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SHSUB16\r
+ */\r
+ __STATIC_FORCEINLINE uint32_t __SHSUB16(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ q31_t r, s;\r
+\r
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
+\r
+ return ((uint32_t)((s << 16) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined QASX\r
+ */\r
+ __STATIC_FORCEINLINE uint32_t __QASX(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ q31_t r, s;\r
+\r
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;\r
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r
+\r
+ return ((uint32_t)((s << 16) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SHASX\r
+ */\r
+ __STATIC_FORCEINLINE uint32_t __SHASX(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ q31_t r, s;\r
+\r
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
+\r
+ return ((uint32_t)((s << 16) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined QSAX\r
+ */\r
+ __STATIC_FORCEINLINE uint32_t __QSAX(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ q31_t r, s;\r
+\r
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;\r
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r
+\r
+ return ((uint32_t)((s << 16) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SHSAX\r
+ */\r
+ __STATIC_FORCEINLINE uint32_t __SHSAX(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ q31_t r, s;\r
+\r
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
+\r
+ return ((uint32_t)((s << 16) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SMUSDX\r
+ */\r
+ __STATIC_FORCEINLINE uint32_t __SMUSDX(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -\r
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMUADX\r
+ */\r
+ __STATIC_FORCEINLINE uint32_t __SMUADX(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +\r
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined QADD\r
+ */\r
+ __STATIC_FORCEINLINE int32_t __QADD(\r
+ int32_t x,\r
+ int32_t y)\r
+ {\r
+ return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined QSUB\r
+ */\r
+ __STATIC_FORCEINLINE int32_t __QSUB(\r
+ int32_t x,\r
+ int32_t y)\r
+ {\r
+ return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SMLAD\r
+ */\r
+ __STATIC_FORCEINLINE uint32_t __SMLAD(\r
+ uint32_t x,\r
+ uint32_t y,\r
+ uint32_t sum)\r
+ {\r
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\r
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +\r
+ ( ((q31_t)sum ) ) ));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SMLADX\r
+ */\r
+ __STATIC_FORCEINLINE uint32_t __SMLADX(\r
+ uint32_t x,\r
+ uint32_t y,\r
+ uint32_t sum)\r
+ {\r
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +\r
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +\r
+ ( ((q31_t)sum ) ) ));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SMLSDX\r
+ */\r
+ __STATIC_FORCEINLINE uint32_t __SMLSDX(\r
+ uint32_t x,\r
+ uint32_t y,\r
+ uint32_t sum)\r
+ {\r
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -\r
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +\r
+ ( ((q31_t)sum ) ) ));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SMLALD\r
+ */\r
+ __STATIC_FORCEINLINE uint64_t __SMLALD(\r
+ uint32_t x,\r
+ uint32_t y,\r
+ uint64_t sum)\r
+ {\r
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */\r
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\r
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +\r
+ ( ((q63_t)sum ) ) ));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SMLALDX\r
+ */\r
+ __STATIC_FORCEINLINE uint64_t __SMLALDX(\r
+ uint32_t x,\r
+ uint32_t y,\r
+ uint64_t sum)\r
+ {\r
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */\r
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +\r
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +\r
+ ( ((q63_t)sum ) ) ));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SMUAD\r
+ */\r
+ __STATIC_FORCEINLINE uint32_t __SMUAD(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\r
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SMUSD\r
+ */\r
+ __STATIC_FORCEINLINE uint32_t __SMUSD(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -\r
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SXTB16\r
+ */\r
+ __STATIC_FORCEINLINE uint32_t __SXTB16(\r
+ uint32_t x)\r
+ {\r
+ return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |\r
+ ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMMLA\r
+ */\r
+ __STATIC_FORCEINLINE int32_t __SMMLA(\r
+ int32_t x,\r
+ int32_t y,\r
+ int32_t sum)\r
+ {\r
+ return (sum + (int32_t) (((int64_t) x * y) >> 32));\r
+ }\r
+\r
+#endif /* !defined (ARM_MATH_DSP) */\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q7 FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ } arm_fir_instance_q7;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ } arm_fir_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ } arm_fir_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ } arm_fir_instance_f32;\r
+\r
+ /**\r
+ * @brief Processing function for the Q7 FIR filter.\r
+ * @param[in] S points to an instance of the Q7 FIR filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_fir_q7(\r
+ const arm_fir_instance_q7 * S,\r
+ const q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q7 FIR filter.\r
+ * @param[in,out] S points to an instance of the Q7 FIR structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed.\r
+ */\r
+ void arm_fir_init_q7(\r
+ arm_fir_instance_q7 * S,\r
+ uint16_t numTaps,\r
+ const q7_t * pCoeffs,\r
+ q7_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR filter.\r
+ * @param[in] S points to an instance of the Q15 FIR structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_fir_q15(\r
+ const arm_fir_instance_q15 * S,\r
+ const q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the fast Q15 FIR filter (fast version).\r
+ * @param[in] S points to an instance of the Q15 FIR filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_fir_fast_q15(\r
+ const arm_fir_instance_q15 * S,\r
+ const q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR filter.\r
+ * @param[in,out] S points to an instance of the Q15 FIR filter structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed at a time.\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SUCCESS</code> if initialization was successful or\r
+ * <code>ARM_MATH_ARGUMENT_ERROR</code> if <code>numTaps</code> is not a supported value.\r
+ */\r
+ arm_status arm_fir_init_q15(\r
+ arm_fir_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ const q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR filter.\r
+ * @param[in] S points to an instance of the Q31 FIR filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_fir_q31(\r
+ const arm_fir_instance_q31 * S,\r
+ const q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the fast Q31 FIR filter (fast version).\r
+ * @param[in] S points to an instance of the Q31 FIR filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_fir_fast_q31(\r
+ const arm_fir_instance_q31 * S,\r
+ const q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR filter.\r
+ * @param[in,out] S points to an instance of the Q31 FIR structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed at a time.\r
+ */\r
+ void arm_fir_init_q31(\r
+ arm_fir_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ const q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR filter.\r
+ * @param[in] S points to an instance of the floating-point FIR structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_fir_f32(\r
+ const arm_fir_instance_f32 * S,\r
+ const float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point FIR filter.\r
+ * @param[in,out] S points to an instance of the floating-point FIR filter structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed at a time.\r
+ */\r
+ void arm_fir_init_f32(\r
+ arm_fir_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ const float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
+ const q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */\r
+ } arm_biquad_casd_df1_inst_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
+ const q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */\r
+ } arm_biquad_casd_df1_inst_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
+ const float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
+ } arm_biquad_casd_df1_inst_f32;\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 Biquad cascade filter.\r
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_biquad_cascade_df1_q15(\r
+ const arm_biquad_casd_df1_inst_q15 * S,\r
+ const q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 Biquad cascade filter.\r
+ * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format\r
+ */\r
+ void arm_biquad_cascade_df1_init_q15(\r
+ arm_biquad_casd_df1_inst_q15 * S,\r
+ uint8_t numStages,\r
+ const q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ int8_t postShift);\r
+\r
+ /**\r
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_biquad_cascade_df1_fast_q15(\r
+ const arm_biquad_casd_df1_inst_q15 * S,\r
+ const q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 Biquad cascade filter\r
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_biquad_cascade_df1_q31(\r
+ const arm_biquad_casd_df1_inst_q31 * S,\r
+ const q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_biquad_cascade_df1_fast_q31(\r
+ const arm_biquad_casd_df1_inst_q31 * S,\r
+ const q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 Biquad cascade filter.\r
+ * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format\r
+ */\r
+ void arm_biquad_cascade_df1_init_q31(\r
+ arm_biquad_casd_df1_inst_q31 * S,\r
+ uint8_t numStages,\r
+ const q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ int8_t postShift);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point Biquad cascade filter.\r
+ * @param[in] S points to an instance of the floating-point Biquad cascade structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_biquad_cascade_df1_f32(\r
+ const arm_biquad_casd_df1_inst_f32 * S,\r
+ const float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point Biquad cascade filter.\r
+ * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ */\r
+ void arm_biquad_cascade_df1_init_f32(\r
+ arm_biquad_casd_df1_inst_f32 * S,\r
+ uint8_t numStages,\r
+ const float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point matrix structure.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ float32_t *pData; /**< points to the data of the matrix. */\r
+ } arm_matrix_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point matrix structure.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ float64_t *pData; /**< points to the data of the matrix. */\r
+ } arm_matrix_instance_f64;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 matrix structure.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ q15_t *pData; /**< points to the data of the matrix. */\r
+ } arm_matrix_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 matrix structure.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ q31_t *pData; /**< points to the data of the matrix. */\r
+ } arm_matrix_instance_q31;\r
+\r
+ /**\r
+ * @brief Floating-point matrix addition.\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+arm_status arm_mat_add_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix addition.\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+arm_status arm_mat_add_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix addition.\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+arm_status arm_mat_add_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+ /**\r
+ * @brief Floating-point, complex, matrix multiplication.\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+arm_status arm_mat_cmplx_mult_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15, complex, matrix multiplication.\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+arm_status arm_mat_cmplx_mult_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst,\r
+ q15_t * pScratch);\r
+\r
+ /**\r
+ * @brief Q31, complex, matrix multiplication.\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+arm_status arm_mat_cmplx_mult_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+ /**\r
+ * @brief Floating-point matrix transpose.\r
+ * @param[in] pSrc points to the input matrix\r
+ * @param[out] pDst points to the output matrix\r
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+arm_status arm_mat_trans_f32(\r
+ const arm_matrix_instance_f32 * pSrc,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix transpose.\r
+ * @param[in] pSrc points to the input matrix\r
+ * @param[out] pDst points to the output matrix\r
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+arm_status arm_mat_trans_q15(\r
+ const arm_matrix_instance_q15 * pSrc,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix transpose.\r
+ * @param[in] pSrc points to the input matrix\r
+ * @param[out] pDst points to the output matrix\r
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+arm_status arm_mat_trans_q31(\r
+ const arm_matrix_instance_q31 * pSrc,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+ /**\r
+ * @brief Floating-point matrix multiplication\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+arm_status arm_mat_mult_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix multiplication\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @param[in] pState points to the array for storing intermediate results\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+arm_status arm_mat_mult_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst,\r
+ q15_t * pState);\r
+\r
+ /**\r
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @param[in] pState points to the array for storing intermediate results\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+arm_status arm_mat_mult_fast_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst,\r
+ q15_t * pState);\r
+\r
+ /**\r
+ * @brief Q31 matrix multiplication\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+arm_status arm_mat_mult_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+arm_status arm_mat_mult_fast_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+ /**\r
+ * @brief Floating-point matrix subtraction\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+arm_status arm_mat_sub_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix subtraction\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+arm_status arm_mat_sub_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix subtraction\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+arm_status arm_mat_sub_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+ /**\r
+ * @brief Floating-point matrix scaling.\r
+ * @param[in] pSrc points to the input matrix\r
+ * @param[in] scale scale factor\r
+ * @param[out] pDst points to the output matrix\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+arm_status arm_mat_scale_f32(\r
+ const arm_matrix_instance_f32 * pSrc,\r
+ float32_t scale,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix scaling.\r
+ * @param[in] pSrc points to input matrix\r
+ * @param[in] scaleFract fractional portion of the scale factor\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] pDst points to output matrix\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+arm_status arm_mat_scale_q15(\r
+ const arm_matrix_instance_q15 * pSrc,\r
+ q15_t scaleFract,\r
+ int32_t shift,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix scaling.\r
+ * @param[in] pSrc points to input matrix\r
+ * @param[in] scaleFract fractional portion of the scale factor\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+arm_status arm_mat_scale_q31(\r
+ const arm_matrix_instance_q31 * pSrc,\r
+ q31_t scaleFract,\r
+ int32_t shift,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix initialization.\r
+ * @param[in,out] S points to an instance of the floating-point matrix structure.\r
+ * @param[in] nRows number of rows in the matrix.\r
+ * @param[in] nColumns number of columns in the matrix.\r
+ * @param[in] pData points to the matrix data array.\r
+ */\r
+void arm_mat_init_q31(\r
+ arm_matrix_instance_q31 * S,\r
+ uint16_t nRows,\r
+ uint16_t nColumns,\r
+ q31_t * pData);\r
+\r
+ /**\r
+ * @brief Q15 matrix initialization.\r
+ * @param[in,out] S points to an instance of the floating-point matrix structure.\r
+ * @param[in] nRows number of rows in the matrix.\r
+ * @param[in] nColumns number of columns in the matrix.\r
+ * @param[in] pData points to the matrix data array.\r
+ */\r
+void arm_mat_init_q15(\r
+ arm_matrix_instance_q15 * S,\r
+ uint16_t nRows,\r
+ uint16_t nColumns,\r
+ q15_t * pData);\r
+\r
+ /**\r
+ * @brief Floating-point matrix initialization.\r
+ * @param[in,out] S points to an instance of the floating-point matrix structure.\r
+ * @param[in] nRows number of rows in the matrix.\r
+ * @param[in] nColumns number of columns in the matrix.\r
+ * @param[in] pData points to the matrix data array.\r
+ */\r
+void arm_mat_init_f32(\r
+ arm_matrix_instance_f32 * S,\r
+ uint16_t nRows,\r
+ uint16_t nColumns,\r
+ float32_t * pData);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 PID Control.\r
+ */\r
+ typedef struct\r
+ {\r
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
+#if !defined (ARM_MATH_DSP)\r
+ q15_t A1;\r
+ q15_t A2;\r
+#else\r
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/\r
+#endif\r
+ q15_t state[3]; /**< The state array of length 3. */\r
+ q15_t Kp; /**< The proportional gain. */\r
+ q15_t Ki; /**< The integral gain. */\r
+ q15_t Kd; /**< The derivative gain. */\r
+ } arm_pid_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 PID Control.\r
+ */\r
+ typedef struct\r
+ {\r
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */\r
+ q31_t A2; /**< The derived gain, A2 = Kd . */\r
+ q31_t state[3]; /**< The state array of length 3. */\r
+ q31_t Kp; /**< The proportional gain. */\r
+ q31_t Ki; /**< The integral gain. */\r
+ q31_t Kd; /**< The derivative gain. */\r
+ } arm_pid_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point PID Control.\r
+ */\r
+ typedef struct\r
+ {\r
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */\r
+ float32_t A2; /**< The derived gain, A2 = Kd . */\r
+ float32_t state[3]; /**< The state array of length 3. */\r
+ float32_t Kp; /**< The proportional gain. */\r
+ float32_t Ki; /**< The integral gain. */\r
+ float32_t Kd; /**< The derivative gain. */\r
+ } arm_pid_instance_f32;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point PID Control.\r
+ * @param[in,out] S points to an instance of the PID structure.\r
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
+ */\r
+ void arm_pid_init_f32(\r
+ arm_pid_instance_f32 * S,\r
+ int32_t resetStateFlag);\r
+\r
+\r
+ /**\r
+ * @brief Reset function for the floating-point PID Control.\r
+ * @param[in,out] S is an instance of the floating-point PID Control structure\r
+ */\r
+ void arm_pid_reset_f32(\r
+ arm_pid_instance_f32 * S);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 PID Control.\r
+ * @param[in,out] S points to an instance of the Q15 PID structure.\r
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
+ */\r
+ void arm_pid_init_q31(\r
+ arm_pid_instance_q31 * S,\r
+ int32_t resetStateFlag);\r
+\r
+\r
+ /**\r
+ * @brief Reset function for the Q31 PID Control.\r
+ * @param[in,out] S points to an instance of the Q31 PID Control structure\r
+ */\r
+\r
+ void arm_pid_reset_q31(\r
+ arm_pid_instance_q31 * S);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 PID Control.\r
+ * @param[in,out] S points to an instance of the Q15 PID structure.\r
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
+ */\r
+ void arm_pid_init_q15(\r
+ arm_pid_instance_q15 * S,\r
+ int32_t resetStateFlag);\r
+\r
+\r
+ /**\r
+ * @brief Reset function for the Q15 PID Control.\r
+ * @param[in,out] S points to an instance of the q15 PID Control structure\r
+ */\r
+ void arm_pid_reset_q15(\r
+ arm_pid_instance_q15 * S);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point Linear Interpolate function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t nValues; /**< nValues */\r
+ float32_t x1; /**< x1 */\r
+ float32_t xSpacing; /**< xSpacing */\r
+ float32_t *pYData; /**< pointer to the table of Y values */\r
+ } arm_linear_interp_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point bilinear interpolation function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ float32_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 bilinear interpolation function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ q31_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 bilinear interpolation function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ q15_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 bilinear interpolation function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ q7_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_q7;\r
+\r
+\r
+ /**\r
+ * @brief Q7 vector multiplication.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_mult_q7(\r
+ const q7_t * pSrcA,\r
+ const q7_t * pSrcB,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q15 vector multiplication.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_mult_q15(\r
+ const q15_t * pSrcA,\r
+ const q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q31 vector multiplication.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_mult_q31(\r
+ const q31_t * pSrcA,\r
+ const q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point vector multiplication.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_mult_f32(\r
+ const float32_t * pSrcA,\r
+ const float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ const q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */\r
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ } arm_cfft_radix2_instance_q15;\r
+\r
+/* Deprecated */\r
+ arm_status arm_cfft_radix2_init_q15(\r
+ arm_cfft_radix2_instance_q15 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+/* Deprecated */\r
+ void arm_cfft_radix2_q15(\r
+ const arm_cfft_radix2_instance_q15 * S,\r
+ q15_t * pSrc);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ const q15_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ } arm_cfft_radix4_instance_q15;\r
+\r
+/* Deprecated */\r
+ arm_status arm_cfft_radix4_init_q15(\r
+ arm_cfft_radix4_instance_q15 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+/* Deprecated */\r
+ void arm_cfft_radix4_q15(\r
+ const arm_cfft_radix4_instance_q15 * S,\r
+ q15_t * pSrc);\r
+\r
+ /**\r
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */\r
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ } arm_cfft_radix2_instance_q31;\r
+\r
+/* Deprecated */\r
+ arm_status arm_cfft_radix2_init_q31(\r
+ arm_cfft_radix2_instance_q31 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+/* Deprecated */\r
+ void arm_cfft_radix2_q31(\r
+ const arm_cfft_radix2_instance_q31 * S,\r
+ q31_t * pSrc);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ const q31_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ } arm_cfft_radix4_instance_q31;\r
+\r
+/* Deprecated */\r
+ void arm_cfft_radix4_q31(\r
+ const arm_cfft_radix4_instance_q31 * S,\r
+ q31_t * pSrc);\r
+\r
+/* Deprecated */\r
+ arm_status arm_cfft_radix4_init_q31(\r
+ arm_cfft_radix4_instance_q31 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */\r
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ float32_t onebyfftLen; /**< value of 1/fftLen. */\r
+ } arm_cfft_radix2_instance_f32;\r
+\r
+/* Deprecated */\r
+ arm_status arm_cfft_radix2_init_f32(\r
+ arm_cfft_radix2_instance_f32 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+/* Deprecated */\r
+ void arm_cfft_radix2_f32(\r
+ const arm_cfft_radix2_instance_f32 * S,\r
+ float32_t * pSrc);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */\r
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ float32_t onebyfftLen; /**< value of 1/fftLen. */\r
+ } arm_cfft_radix4_instance_f32;\r
+\r
+/* Deprecated */\r
+ arm_status arm_cfft_radix4_init_f32(\r
+ arm_cfft_radix4_instance_f32 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+/* Deprecated */\r
+ void arm_cfft_radix4_f32(\r
+ const arm_cfft_radix4_instance_f32 * S,\r
+ float32_t * pSrc);\r
+\r
+ /**\r
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ const q15_t *pTwiddle; /**< points to the Twiddle factor table. */\r
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t bitRevLength; /**< bit reversal table length. */\r
+ } arm_cfft_instance_q15;\r
+\r
+void arm_cfft_q15(\r
+ const arm_cfft_instance_q15 * S,\r
+ q15_t * p1,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */\r
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t bitRevLength; /**< bit reversal table length. */\r
+ } arm_cfft_instance_q31;\r
+\r
+void arm_cfft_q31(\r
+ const arm_cfft_instance_q31 * S,\r
+ q31_t * p1,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */\r
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t bitRevLength; /**< bit reversal table length. */\r
+ } arm_cfft_instance_f32;\r
+\r
+ void arm_cfft_f32(\r
+ const arm_cfft_instance_f32 * S,\r
+ float32_t * p1,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t fftLenReal; /**< length of the real FFT. */\r
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ const q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
+ const q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
+ const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_rfft_instance_q15;\r
+\r
+ arm_status arm_rfft_init_q15(\r
+ arm_rfft_instance_q15 * S,\r
+ uint32_t fftLenReal,\r
+ uint32_t ifftFlagR,\r
+ uint32_t bitReverseFlag);\r
+\r
+ void arm_rfft_q15(\r
+ const arm_rfft_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t fftLenReal; /**< length of the real FFT. */\r
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ const q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
+ const q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
+ const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_rfft_instance_q31;\r
+\r
+ arm_status arm_rfft_init_q31(\r
+ arm_rfft_instance_q31 * S,\r
+ uint32_t fftLenReal,\r
+ uint32_t ifftFlagR,\r
+ uint32_t bitReverseFlag);\r
+\r
+ void arm_rfft_q31(\r
+ const arm_rfft_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t fftLenReal; /**< length of the real FFT. */\r
+ uint16_t fftLenBy2; /**< length of the complex FFT. */\r
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ const float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
+ const float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_rfft_instance_f32;\r
+\r
+ arm_status arm_rfft_init_f32(\r
+ arm_rfft_instance_f32 * S,\r
+ arm_cfft_radix4_instance_f32 * S_CFFT,\r
+ uint32_t fftLenReal,\r
+ uint32_t ifftFlagR,\r
+ uint32_t bitReverseFlag);\r
+\r
+ void arm_rfft_f32(\r
+ const arm_rfft_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.\r
+ */\r
+typedef struct\r
+ {\r
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */\r
+ uint16_t fftLenRFFT; /**< length of the real sequence */\r
+ const float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */\r
+ } arm_rfft_fast_instance_f32 ;\r
+\r
+arm_status arm_rfft_fast_init_f32 (\r
+ arm_rfft_fast_instance_f32 * S,\r
+ uint16_t fftLen);\r
+\r
+arm_status arm_rfft_32_fast_init_f32 ( arm_rfft_fast_instance_f32 * S );\r
+\r
+arm_status arm_rfft_64_fast_init_f32 ( arm_rfft_fast_instance_f32 * S );\r
+\r
+arm_status arm_rfft_128_fast_init_f32 ( arm_rfft_fast_instance_f32 * S );\r
+\r
+arm_status arm_rfft_256_fast_init_f32 ( arm_rfft_fast_instance_f32 * S );\r
+\r
+arm_status arm_rfft_512_fast_init_f32 ( arm_rfft_fast_instance_f32 * S );\r
+\r
+arm_status arm_rfft_1024_fast_init_f32 ( arm_rfft_fast_instance_f32 * S );\r
+\r
+arm_status arm_rfft_2048_fast_init_f32 ( arm_rfft_fast_instance_f32 * S );\r
+\r
+arm_status arm_rfft_4096_fast_init_f32 ( arm_rfft_fast_instance_f32 * S );\r
+\r
+\r
+ void arm_rfft_fast_f32(\r
+ arm_rfft_fast_instance_f32 * S,\r
+ float32_t * p, float32_t * pOut,\r
+ uint8_t ifftFlag);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t N; /**< length of the DCT4. */\r
+ uint16_t Nby2; /**< half of the length of the DCT4. */\r
+ float32_t normalize; /**< normalizing factor. */\r
+ const float32_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ const float32_t *pCosFactor; /**< points to the cosFactor table. */\r
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */\r
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_dct4_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point DCT4/IDCT4.\r
+ * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.\r
+ * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.\r
+ * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.\r
+ * @param[in] N length of the DCT4.\r
+ * @param[in] Nby2 half of the length of the DCT4.\r
+ * @param[in] normalize normalizing factor.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.\r
+ */\r
+ arm_status arm_dct4_init_f32(\r
+ arm_dct4_instance_f32 * S,\r
+ arm_rfft_instance_f32 * S_RFFT,\r
+ arm_cfft_radix4_instance_f32 * S_CFFT,\r
+ uint16_t N,\r
+ uint16_t Nby2,\r
+ float32_t normalize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point DCT4/IDCT4.\r
+ * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.\r
+ * @param[in] pState points to state buffer.\r
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.\r
+ */\r
+ void arm_dct4_f32(\r
+ const arm_dct4_instance_f32 * S,\r
+ float32_t * pState,\r
+ float32_t * pInlineBuffer);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t N; /**< length of the DCT4. */\r
+ uint16_t Nby2; /**< half of the length of the DCT4. */\r
+ q31_t normalize; /**< normalizing factor. */\r
+ const q31_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ const q31_t *pCosFactor; /**< points to the cosFactor table. */\r
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */\r
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_dct4_instance_q31;\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 DCT4/IDCT4.\r
+ * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.\r
+ * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure\r
+ * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure\r
+ * @param[in] N length of the DCT4.\r
+ * @param[in] Nby2 half of the length of the DCT4.\r
+ * @param[in] normalize normalizing factor.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r
+ */\r
+ arm_status arm_dct4_init_q31(\r
+ arm_dct4_instance_q31 * S,\r
+ arm_rfft_instance_q31 * S_RFFT,\r
+ arm_cfft_radix4_instance_q31 * S_CFFT,\r
+ uint16_t N,\r
+ uint16_t Nby2,\r
+ q31_t normalize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 DCT4/IDCT4.\r
+ * @param[in] S points to an instance of the Q31 DCT4 structure.\r
+ * @param[in] pState points to state buffer.\r
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.\r
+ */\r
+ void arm_dct4_q31(\r
+ const arm_dct4_instance_q31 * S,\r
+ q31_t * pState,\r
+ q31_t * pInlineBuffer);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t N; /**< length of the DCT4. */\r
+ uint16_t Nby2; /**< half of the length of the DCT4. */\r
+ q15_t normalize; /**< normalizing factor. */\r
+ const q15_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ const q15_t *pCosFactor; /**< points to the cosFactor table. */\r
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */\r
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_dct4_instance_q15;\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 DCT4/IDCT4.\r
+ * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.\r
+ * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.\r
+ * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.\r
+ * @param[in] N length of the DCT4.\r
+ * @param[in] Nby2 half of the length of the DCT4.\r
+ * @param[in] normalize normalizing factor.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r
+ */\r
+ arm_status arm_dct4_init_q15(\r
+ arm_dct4_instance_q15 * S,\r
+ arm_rfft_instance_q15 * S_RFFT,\r
+ arm_cfft_radix4_instance_q15 * S_CFFT,\r
+ uint16_t N,\r
+ uint16_t Nby2,\r
+ q15_t normalize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 DCT4/IDCT4.\r
+ * @param[in] S points to an instance of the Q15 DCT4 structure.\r
+ * @param[in] pState points to state buffer.\r
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.\r
+ */\r
+ void arm_dct4_q15(\r
+ const arm_dct4_instance_q15 * S,\r
+ q15_t * pState,\r
+ q15_t * pInlineBuffer);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point vector addition.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_add_f32(\r
+ const float32_t * pSrcA,\r
+ const float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q7 vector addition.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_add_q7(\r
+ const q7_t * pSrcA,\r
+ const q7_t * pSrcB,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q15 vector addition.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_add_q15(\r
+ const q15_t * pSrcA,\r
+ const q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q31 vector addition.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_add_q31(\r
+ const q31_t * pSrcA,\r
+ const q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point vector subtraction.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_sub_f32(\r
+ const float32_t * pSrcA,\r
+ const float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q7 vector subtraction.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_sub_q7(\r
+ const q7_t * pSrcA,\r
+ const q7_t * pSrcB,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q15 vector subtraction.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_sub_q15(\r
+ const q15_t * pSrcA,\r
+ const q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q31 vector subtraction.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_sub_q31(\r
+ const q31_t * pSrcA,\r
+ const q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Multiplies a floating-point vector by a scalar.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] scale scale factor to be applied\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_scale_f32(\r
+ const float32_t * pSrc,\r
+ float32_t scale,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Multiplies a Q7 vector by a scalar.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] scaleFract fractional portion of the scale value\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_scale_q7(\r
+ const q7_t * pSrc,\r
+ q7_t scaleFract,\r
+ int8_t shift,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Multiplies a Q15 vector by a scalar.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] scaleFract fractional portion of the scale value\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_scale_q15(\r
+ const q15_t * pSrc,\r
+ q15_t scaleFract,\r
+ int8_t shift,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Multiplies a Q31 vector by a scalar.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] scaleFract fractional portion of the scale value\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_scale_q31(\r
+ const q31_t * pSrc,\r
+ q31_t scaleFract,\r
+ int8_t shift,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q7 vector absolute value.\r
+ * @param[in] pSrc points to the input buffer\r
+ * @param[out] pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_abs_q7(\r
+ const q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point vector absolute value.\r
+ * @param[in] pSrc points to the input buffer\r
+ * @param[out] pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_abs_f32(\r
+ const float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q15 vector absolute value.\r
+ * @param[in] pSrc points to the input buffer\r
+ * @param[out] pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_abs_q15(\r
+ const q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q31 vector absolute value.\r
+ * @param[in] pSrc points to the input buffer\r
+ * @param[out] pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_abs_q31(\r
+ const q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Dot product of floating-point vectors.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] result output result returned here\r
+ */\r
+ void arm_dot_prod_f32(\r
+ const float32_t * pSrcA,\r
+ const float32_t * pSrcB,\r
+ uint32_t blockSize,\r
+ float32_t * result);\r
+\r
+\r
+ /**\r
+ * @brief Dot product of Q7 vectors.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] result output result returned here\r
+ */\r
+ void arm_dot_prod_q7(\r
+ const q7_t * pSrcA,\r
+ const q7_t * pSrcB,\r
+ uint32_t blockSize,\r
+ q31_t * result);\r
+\r
+\r
+ /**\r
+ * @brief Dot product of Q15 vectors.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] result output result returned here\r
+ */\r
+ void arm_dot_prod_q15(\r
+ const q15_t * pSrcA,\r
+ const q15_t * pSrcB,\r
+ uint32_t blockSize,\r
+ q63_t * result);\r
+\r
+\r
+ /**\r
+ * @brief Dot product of Q31 vectors.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] result output result returned here\r
+ */\r
+ void arm_dot_prod_q31(\r
+ const q31_t * pSrcA,\r
+ const q31_t * pSrcB,\r
+ uint32_t blockSize,\r
+ q63_t * result);\r
+\r
+\r
+ /**\r
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_shift_q7(\r
+ const q7_t * pSrc,\r
+ int8_t shiftBits,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_shift_q15(\r
+ const q15_t * pSrc,\r
+ int8_t shiftBits,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_shift_q31(\r
+ const q31_t * pSrc,\r
+ int8_t shiftBits,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a floating-point vector.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_offset_f32(\r
+ const float32_t * pSrc,\r
+ float32_t offset,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a Q7 vector.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_offset_q7(\r
+ const q7_t * pSrc,\r
+ q7_t offset,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a Q15 vector.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_offset_q15(\r
+ const q15_t * pSrc,\r
+ q15_t offset,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a Q31 vector.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_offset_q31(\r
+ const q31_t * pSrc,\r
+ q31_t offset,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Negates the elements of a floating-point vector.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_negate_f32(\r
+ const float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Negates the elements of a Q7 vector.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_negate_q7(\r
+ const q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Negates the elements of a Q15 vector.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_negate_q15(\r
+ const q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Negates the elements of a Q31 vector.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_negate_q31(\r
+ const q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Copies the elements of a floating-point vector.\r
+ * @param[in] pSrc input pointer\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_copy_f32(\r
+ const float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Copies the elements of a Q7 vector.\r
+ * @param[in] pSrc input pointer\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_copy_q7(\r
+ const q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Copies the elements of a Q15 vector.\r
+ * @param[in] pSrc input pointer\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_copy_q15(\r
+ const q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Copies the elements of a Q31 vector.\r
+ * @param[in] pSrc input pointer\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_copy_q31(\r
+ const q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Fills a constant value into a floating-point vector.\r
+ * @param[in] value input value to be filled\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_fill_f32(\r
+ float32_t value,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Fills a constant value into a Q7 vector.\r
+ * @param[in] value input value to be filled\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_fill_q7(\r
+ q7_t value,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Fills a constant value into a Q15 vector.\r
+ * @param[in] value input value to be filled\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_fill_q15(\r
+ q15_t value,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Fills a constant value into a Q31 vector.\r
+ * @param[in] value input value to be filled\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_fill_q31(\r
+ q31_t value,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+/**\r
+ * @brief Convolution of floating-point sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.\r
+ */\r
+ void arm_conv_f32(\r
+ const float32_t * pSrcA,\r
+ uint32_t srcALen,\r
+ const float32_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ float32_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q15 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
+ */\r
+ void arm_conv_opt_q15(\r
+ const q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ const q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+/**\r
+ * @brief Convolution of Q15 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.\r
+ */\r
+ void arm_conv_q15(\r
+ const q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ const q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ */\r
+ void arm_conv_fast_q15(\r
+ const q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ const q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
+ */\r
+ void arm_conv_fast_opt_q15(\r
+ const q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ const q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q31 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ */\r
+ void arm_conv_q31(\r
+ const q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ const q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ */\r
+ void arm_conv_fast_q31(\r
+ const q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ const q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q7 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r
+ */\r
+ void arm_conv_opt_q7(\r
+ const q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ const q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q7 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ */\r
+ void arm_conv_q7(\r
+ const q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ const q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of floating-point sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+ arm_status arm_conv_partial_f32(\r
+ const float32_t * pSrcA,\r
+ uint32_t srcALen,\r
+ const float32_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ float32_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q15 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+ arm_status arm_conv_partial_opt_q15(\r
+ const q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ const q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q15 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+ arm_status arm_conv_partial_q15(\r
+ const q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ const q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+ arm_status arm_conv_partial_fast_q15(\r
+ const q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ const q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+ arm_status arm_conv_partial_fast_opt_q15(\r
+ const q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ const q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q31 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+ arm_status arm_conv_partial_q31(\r
+ const q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ const q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+ arm_status arm_conv_partial_fast_q31(\r
+ const q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ const q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q7 sequences\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+ arm_status arm_conv_partial_opt_q7(\r
+ const q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ const q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+/**\r
+ * @brief Partial convolution of Q7 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+ arm_status arm_conv_partial_q7(\r
+ const q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ const q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR decimator.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t M; /**< decimation factor. */\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ } arm_fir_decimate_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR decimator.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t M; /**< decimation factor. */\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ } arm_fir_decimate_instance_q31;\r
+\r
+/**\r
+ @brief Instance structure for floating-point FIR decimator.\r
+ */\r
+typedef struct\r
+ {\r
+ uint8_t M; /**< decimation factor. */\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ } arm_fir_decimate_instance_f32;\r
+\r
+\r
+/**\r
+ @brief Processing function for floating-point FIR decimator.\r
+ @param[in] S points to an instance of the floating-point FIR decimator structure\r
+ @param[in] pSrc points to the block of input data\r
+ @param[out] pDst points to the block of output data\r
+ @param[in] blockSize number of samples to process\r
+ */\r
+void arm_fir_decimate_f32(\r
+ const arm_fir_decimate_instance_f32 * S,\r
+ const float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+/**\r
+ @brief Initialization function for the floating-point FIR decimator.\r
+ @param[in,out] S points to an instance of the floating-point FIR decimator structure\r
+ @param[in] numTaps number of coefficients in the filter\r
+ @param[in] M decimation factor\r
+ @param[in] pCoeffs points to the filter coefficients\r
+ @param[in] pState points to the state buffer\r
+ @param[in] blockSize number of input samples to process per call\r
+ @return execution status\r
+ - \ref ARM_MATH_SUCCESS : Operation successful\r
+ - \ref ARM_MATH_LENGTH_ERROR : <code>blockSize</code> is not a multiple of <code>M</code>\r
+ */\r
+arm_status arm_fir_decimate_init_f32(\r
+ arm_fir_decimate_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ uint8_t M,\r
+ const float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR decimator.\r
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_decimate_q15(\r
+ const arm_fir_decimate_instance_q15 * S,\r
+ const q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_decimate_fast_q15(\r
+ const arm_fir_decimate_instance_q15 * S,\r
+ const q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR decimator.\r
+ * @param[in,out] S points to an instance of the Q15 FIR decimator structure.\r
+ * @param[in] numTaps number of coefficients in the filter.\r
+ * @param[in] M decimation factor.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * <code>blockSize</code> is not a multiple of <code>M</code>.\r
+ */\r
+ arm_status arm_fir_decimate_init_q15(\r
+ arm_fir_decimate_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ uint8_t M,\r
+ const q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR decimator.\r
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_decimate_q31(\r
+ const arm_fir_decimate_instance_q31 * S,\r
+ const q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_decimate_fast_q31(\r
+ const arm_fir_decimate_instance_q31 * S,\r
+ const q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR decimator.\r
+ * @param[in,out] S points to an instance of the Q31 FIR decimator structure.\r
+ * @param[in] numTaps number of coefficients in the filter.\r
+ * @param[in] M decimation factor.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * <code>blockSize</code> is not a multiple of <code>M</code>.\r
+ */\r
+ arm_status arm_fir_decimate_init_q31(\r
+ arm_fir_decimate_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ uint8_t M,\r
+ const q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR interpolator.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t L; /**< upsample factor. */\r
+ uint16_t phaseLength; /**< length of each polyphase filter component. */\r
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r
+ } arm_fir_interpolate_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR interpolator.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t L; /**< upsample factor. */\r
+ uint16_t phaseLength; /**< length of each polyphase filter component. */\r
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r
+ } arm_fir_interpolate_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR interpolator.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t L; /**< upsample factor. */\r
+ uint16_t phaseLength; /**< length of each polyphase filter component. */\r
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */\r
+ } arm_fir_interpolate_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR interpolator.\r
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_interpolate_q15(\r
+ const arm_fir_interpolate_instance_q15 * S,\r
+ const q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR interpolator.\r
+ * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.\r
+ * @param[in] L upsample factor.\r
+ * @param[in] numTaps number of filter coefficients in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficient buffer.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
+ */\r
+ arm_status arm_fir_interpolate_init_q15(\r
+ arm_fir_interpolate_instance_q15 * S,\r
+ uint8_t L,\r
+ uint16_t numTaps,\r
+ const q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR interpolator.\r
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_interpolate_q31(\r
+ const arm_fir_interpolate_instance_q31 * S,\r
+ const q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR interpolator.\r
+ * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.\r
+ * @param[in] L upsample factor.\r
+ * @param[in] numTaps number of filter coefficients in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficient buffer.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
+ */\r
+ arm_status arm_fir_interpolate_init_q31(\r
+ arm_fir_interpolate_instance_q31 * S,\r
+ uint8_t L,\r
+ uint16_t numTaps,\r
+ const q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR interpolator.\r
+ * @param[in] S points to an instance of the floating-point FIR interpolator structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_interpolate_f32(\r
+ const arm_fir_interpolate_instance_f32 * S,\r
+ const float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point FIR interpolator.\r
+ * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.\r
+ * @param[in] L upsample factor.\r
+ * @param[in] numTaps number of filter coefficients in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficient buffer.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
+ */\r
+ arm_status arm_fir_interpolate_init_f32(\r
+ arm_fir_interpolate_instance_f32 * S,\r
+ uint8_t L,\r
+ uint16_t numTaps,\r
+ const float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */\r
+ const q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */\r
+ } arm_biquad_cas_df1_32x64_ins_q31;\r
+\r
+\r
+ /**\r
+ * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_biquad_cas_df1_32x64_q31(\r
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format\r
+ */\r
+ void arm_biquad_cas_df1_32x64_init_q31(\r
+ arm_biquad_cas_df1_32x64_ins_q31 * S,\r
+ uint8_t numStages,\r
+ const q31_t * pCoeffs,\r
+ q63_t * pState,\r
+ uint8_t postShift);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */\r
+ const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
+ } arm_biquad_cascade_df2T_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */\r
+ const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
+ } arm_biquad_cascade_stereo_df2T_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */\r
+ float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
+ } arm_biquad_cascade_df2T_instance_f64;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in] S points to an instance of the filter data structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_biquad_cascade_df2T_f32(\r
+ const arm_biquad_cascade_df2T_instance_f32 * S,\r
+ const float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels\r
+ * @param[in] S points to an instance of the filter data structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_biquad_cascade_stereo_df2T_f32(\r
+ const arm_biquad_cascade_stereo_df2T_instance_f32 * S,\r
+ const float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in] S points to an instance of the filter data structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_biquad_cascade_df2T_f64(\r
+ const arm_biquad_cascade_df2T_instance_f64 * S,\r
+ float64_t * pSrc,\r
+ float64_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in,out] S points to an instance of the filter data structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ */\r
+ void arm_biquad_cascade_df2T_init_f32(\r
+ arm_biquad_cascade_df2T_instance_f32 * S,\r
+ uint8_t numStages,\r
+ const float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in,out] S points to an instance of the filter data structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ */\r
+ void arm_biquad_cascade_stereo_df2T_init_f32(\r
+ arm_biquad_cascade_stereo_df2T_instance_f32 * S,\r
+ uint8_t numStages,\r
+ const float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in,out] S points to an instance of the filter data structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ */\r
+ void arm_biquad_cascade_df2T_init_f64(\r
+ arm_biquad_cascade_df2T_instance_f64 * S,\r
+ uint8_t numStages,\r
+ float64_t * pCoeffs,\r
+ float64_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of filter stages. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
+ } arm_fir_lattice_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of filter stages. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
+ } arm_fir_lattice_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of filter stages. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
+ } arm_fir_lattice_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR lattice filter.\r
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.\r
+ * @param[in] numStages number of filter stages.\r
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.\r
+ * @param[in] pState points to the state buffer. The array is of length numStages.\r
+ */\r
+ void arm_fir_lattice_init_q15(\r
+ arm_fir_lattice_instance_q15 * S,\r
+ uint16_t numStages,\r
+ const q15_t * pCoeffs,\r
+ q15_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR lattice filter.\r
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_fir_lattice_q15(\r
+ const arm_fir_lattice_instance_q15 * S,\r
+ const q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR lattice filter.\r
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.\r
+ * @param[in] numStages number of filter stages.\r
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.\r
+ * @param[in] pState points to the state buffer. The array is of length numStages.\r
+ */\r
+ void arm_fir_lattice_init_q31(\r
+ arm_fir_lattice_instance_q31 * S,\r
+ uint16_t numStages,\r
+ const q31_t * pCoeffs,\r
+ q31_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR lattice filter.\r
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_fir_lattice_q31(\r
+ const arm_fir_lattice_instance_q31 * S,\r
+ const q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+/**\r
+ * @brief Initialization function for the floating-point FIR lattice filter.\r
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.\r
+ * @param[in] numStages number of filter stages.\r
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.\r
+ * @param[in] pState points to the state buffer. The array is of length numStages.\r
+ */\r
+ void arm_fir_lattice_init_f32(\r
+ arm_fir_lattice_instance_f32 * S,\r
+ uint16_t numStages,\r
+ const float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR lattice filter.\r
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_fir_lattice_f32(\r
+ const arm_fir_lattice_instance_f32 * S,\r
+ const float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 IIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of stages in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
+ } arm_iir_lattice_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 IIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of stages in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
+ } arm_iir_lattice_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point IIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of stages in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
+ } arm_iir_lattice_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point IIR lattice filter.\r
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_iir_lattice_f32(\r
+ const arm_iir_lattice_instance_f32 * S,\r
+ const float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point IIR lattice filter.\r
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.\r
+ * @param[in] numStages number of stages in the filter.\r
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.\r
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.\r
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_iir_lattice_init_f32(\r
+ arm_iir_lattice_instance_f32 * S,\r
+ uint16_t numStages,\r
+ float32_t * pkCoeffs,\r
+ float32_t * pvCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 IIR lattice filter.\r
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_iir_lattice_q31(\r
+ const arm_iir_lattice_instance_q31 * S,\r
+ const q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 IIR lattice filter.\r
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.\r
+ * @param[in] numStages number of stages in the filter.\r
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.\r
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.\r
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_iir_lattice_init_q31(\r
+ arm_iir_lattice_instance_q31 * S,\r
+ uint16_t numStages,\r
+ q31_t * pkCoeffs,\r
+ q31_t * pvCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 IIR lattice filter.\r
+ * @param[in] S points to an instance of the Q15 IIR lattice structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_iir_lattice_q15(\r
+ const arm_iir_lattice_instance_q15 * S,\r
+ const q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+/**\r
+ * @brief Initialization function for the Q15 IIR lattice filter.\r
+ * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.\r
+ * @param[in] numStages number of stages in the filter.\r
+ * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.\r
+ * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.\r
+ * @param[in] pState points to state buffer. The array is of length numStages+blockSize.\r
+ * @param[in] blockSize number of samples to process per call.\r
+ */\r
+ void arm_iir_lattice_init_q15(\r
+ arm_iir_lattice_instance_q15 * S,\r
+ uint16_t numStages,\r
+ q15_t * pkCoeffs,\r
+ q15_t * pvCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point LMS filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ float32_t mu; /**< step size that controls filter coefficient updates. */\r
+ } arm_lms_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for floating-point LMS filter.\r
+ * @param[in] S points to an instance of the floating-point LMS filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[in] pRef points to the block of reference data.\r
+ * @param[out] pOut points to the block of output data.\r
+ * @param[out] pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_lms_f32(\r
+ const arm_lms_instance_f32 * S,\r
+ const float32_t * pSrc,\r
+ float32_t * pRef,\r
+ float32_t * pOut,\r
+ float32_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for floating-point LMS filter.\r
+ * @param[in] S points to an instance of the floating-point LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] pCoeffs points to the coefficient buffer.\r
+ * @param[in] pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_lms_init_f32(\r
+ arm_lms_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ float32_t mu,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 LMS filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q15_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint32_t postShift; /**< bit shift applied to coefficients. */\r
+ } arm_lms_instance_q15;\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 LMS filter.\r
+ * @param[in] S points to an instance of the Q15 LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] pCoeffs points to the coefficient buffer.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ */\r
+ void arm_lms_init_q15(\r
+ arm_lms_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ q15_t mu,\r
+ uint32_t blockSize,\r
+ uint32_t postShift);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for Q15 LMS filter.\r
+ * @param[in] S points to an instance of the Q15 LMS filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[in] pRef points to the block of reference data.\r
+ * @param[out] pOut points to the block of output data.\r
+ * @param[out] pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_lms_q15(\r
+ const arm_lms_instance_q15 * S,\r
+ const q15_t * pSrc,\r
+ q15_t * pRef,\r
+ q15_t * pOut,\r
+ q15_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 LMS filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q31_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint32_t postShift; /**< bit shift applied to coefficients. */\r
+ } arm_lms_instance_q31;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for Q31 LMS filter.\r
+ * @param[in] S points to an instance of the Q15 LMS filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[in] pRef points to the block of reference data.\r
+ * @param[out] pOut points to the block of output data.\r
+ * @param[out] pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_lms_q31(\r
+ const arm_lms_instance_q31 * S,\r
+ const q31_t * pSrc,\r
+ q31_t * pRef,\r
+ q31_t * pOut,\r
+ q31_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for Q31 LMS filter.\r
+ * @param[in] S points to an instance of the Q31 LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] pCoeffs points to coefficient buffer.\r
+ * @param[in] pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ */\r
+ void arm_lms_init_q31(\r
+ arm_lms_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ q31_t mu,\r
+ uint32_t blockSize,\r
+ uint32_t postShift);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point normalized LMS filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ float32_t mu; /**< step size that control filter coefficient updates. */\r
+ float32_t energy; /**< saves previous frame energy. */\r
+ float32_t x0; /**< saves previous input sample. */\r
+ } arm_lms_norm_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for floating-point normalized LMS filter.\r
+ * @param[in] S points to an instance of the floating-point normalized LMS filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[in] pRef points to the block of reference data.\r
+ * @param[out] pOut points to the block of output data.\r
+ * @param[out] pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_lms_norm_f32(\r
+ arm_lms_norm_instance_f32 * S,\r
+ const float32_t * pSrc,\r
+ float32_t * pRef,\r
+ float32_t * pOut,\r
+ float32_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for floating-point normalized LMS filter.\r
+ * @param[in] S points to an instance of the floating-point LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] pCoeffs points to coefficient buffer.\r
+ * @param[in] pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_lms_norm_init_f32(\r
+ arm_lms_norm_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ float32_t mu,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 normalized LMS filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q31_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint8_t postShift; /**< bit shift applied to coefficients. */\r
+ const q31_t *recipTable; /**< points to the reciprocal initial value table. */\r
+ q31_t energy; /**< saves previous frame energy. */\r
+ q31_t x0; /**< saves previous input sample. */\r
+ } arm_lms_norm_instance_q31;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for Q31 normalized LMS filter.\r
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[in] pRef points to the block of reference data.\r
+ * @param[out] pOut points to the block of output data.\r
+ * @param[out] pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_lms_norm_q31(\r
+ arm_lms_norm_instance_q31 * S,\r
+ const q31_t * pSrc,\r
+ q31_t * pRef,\r
+ q31_t * pOut,\r
+ q31_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for Q31 normalized LMS filter.\r
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] pCoeffs points to coefficient buffer.\r
+ * @param[in] pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ */\r
+ void arm_lms_norm_init_q31(\r
+ arm_lms_norm_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ q31_t mu,\r
+ uint32_t blockSize,\r
+ uint8_t postShift);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 normalized LMS filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< Number of coefficients in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q15_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint8_t postShift; /**< bit shift applied to coefficients. */\r
+ const q15_t *recipTable; /**< Points to the reciprocal initial value table. */\r
+ q15_t energy; /**< saves previous frame energy. */\r
+ q15_t x0; /**< saves previous input sample. */\r
+ } arm_lms_norm_instance_q15;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for Q15 normalized LMS filter.\r
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[in] pRef points to the block of reference data.\r
+ * @param[out] pOut points to the block of output data.\r
+ * @param[out] pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_lms_norm_q15(\r
+ arm_lms_norm_instance_q15 * S,\r
+ const q15_t * pSrc,\r
+ q15_t * pRef,\r
+ q15_t * pOut,\r
+ q15_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for Q15 normalized LMS filter.\r
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] pCoeffs points to coefficient buffer.\r
+ * @param[in] pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ */\r
+ void arm_lms_norm_init_q15(\r
+ arm_lms_norm_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ q15_t mu,\r
+ uint32_t blockSize,\r
+ uint8_t postShift);\r
+\r
+\r
+ /**\r
+ * @brief Correlation of floating-point sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ */\r
+ void arm_correlate_f32(\r
+ const float32_t * pSrcA,\r
+ uint32_t srcALen,\r
+ const float32_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ float32_t * pDst);\r
+\r
+\r
+/**\r
+ @brief Correlation of Q15 sequences\r
+ @param[in] pSrcA points to the first input sequence\r
+ @param[in] srcALen length of the first input sequence\r
+ @param[in] pSrcB points to the second input sequence\r
+ @param[in] srcBLen length of the second input sequence\r
+ @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+*/\r
+void arm_correlate_opt_q15(\r
+ const q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ const q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ q15_t * pScratch);\r
+\r
+\r
+/**\r
+ @brief Correlation of Q15 sequences.\r
+ @param[in] pSrcA points to the first input sequence\r
+ @param[in] srcALen length of the first input sequence\r
+ @param[in] pSrcB points to the second input sequence\r
+ @param[in] srcBLen length of the second input sequence\r
+ @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ */\r
+ void arm_correlate_q15(\r
+ const q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ const q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+\r
+/**\r
+ @brief Correlation of Q15 sequences (fast version).\r
+ @param[in] pSrcA points to the first input sequence\r
+ @param[in] srcALen length of the first input sequence\r
+ @param[in] pSrcB points to the second input sequence\r
+ @param[in] srcBLen length of the second input sequence\r
+ @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.\r
+ @return none\r
+ */\r
+void arm_correlate_fast_q15(\r
+ const q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ const q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+\r
+/**\r
+ @brief Correlation of Q15 sequences (fast version).\r
+ @param[in] pSrcA points to the first input sequence.\r
+ @param[in] srcALen length of the first input sequence.\r
+ @param[in] pSrcB points to the second input sequence.\r
+ @param[in] srcBLen length of the second input sequence.\r
+ @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ */\r
+void arm_correlate_fast_opt_q15(\r
+ const q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ const q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ q15_t * pScratch);\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q31 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ */\r
+ void arm_correlate_q31(\r
+ const q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ const q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+\r
+/**\r
+ @brief Correlation of Q31 sequences (fast version).\r
+ @param[in] pSrcA points to the first input sequence\r
+ @param[in] srcALen length of the first input sequence\r
+ @param[in] pSrcB points to the second input sequence\r
+ @param[in] srcBLen length of the second input sequence\r
+ @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ */\r
+void arm_correlate_fast_q31(\r
+ const q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ const q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q7 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r
+ */\r
+ void arm_correlate_opt_q7(\r
+ const q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ const q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q7 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ */\r
+ void arm_correlate_q7(\r
+ const q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ const q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point sparse FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 sparse FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 sparse FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q7 sparse FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_q7;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point sparse FIR filter.\r
+ * @param[in] S points to an instance of the floating-point sparse FIR structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_sparse_f32(\r
+ arm_fir_sparse_instance_f32 * S,\r
+ const float32_t * pSrc,\r
+ float32_t * pDst,\r
+ float32_t * pScratchIn,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point sparse FIR filter.\r
+ * @param[in,out] S points to an instance of the floating-point sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] pCoeffs points to the array of filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ */\r
+ void arm_fir_sparse_init_f32(\r
+ arm_fir_sparse_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ const float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 sparse FIR filter.\r
+ * @param[in] S points to an instance of the Q31 sparse FIR structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_sparse_q31(\r
+ arm_fir_sparse_instance_q31 * S,\r
+ const q31_t * pSrc,\r
+ q31_t * pDst,\r
+ q31_t * pScratchIn,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 sparse FIR filter.\r
+ * @param[in,out] S points to an instance of the Q31 sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] pCoeffs points to the array of filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ */\r
+ void arm_fir_sparse_init_q31(\r
+ arm_fir_sparse_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ const q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 sparse FIR filter.\r
+ * @param[in] S points to an instance of the Q15 sparse FIR structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_sparse_q15(\r
+ arm_fir_sparse_instance_q15 * S,\r
+ const q15_t * pSrc,\r
+ q15_t * pDst,\r
+ q15_t * pScratchIn,\r
+ q31_t * pScratchOut,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 sparse FIR filter.\r
+ * @param[in,out] S points to an instance of the Q15 sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] pCoeffs points to the array of filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ */\r
+ void arm_fir_sparse_init_q15(\r
+ arm_fir_sparse_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ const q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q7 sparse FIR filter.\r
+ * @param[in] S points to an instance of the Q7 sparse FIR structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_sparse_q7(\r
+ arm_fir_sparse_instance_q7 * S,\r
+ const q7_t * pSrc,\r
+ q7_t * pDst,\r
+ q7_t * pScratchIn,\r
+ q31_t * pScratchOut,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q7 sparse FIR filter.\r
+ * @param[in,out] S points to an instance of the Q7 sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] pCoeffs points to the array of filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ */\r
+ void arm_fir_sparse_init_q7(\r
+ arm_fir_sparse_instance_q7 * S,\r
+ uint16_t numTaps,\r
+ const q7_t * pCoeffs,\r
+ q7_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point sin_cos function.\r
+ * @param[in] theta input value in degrees\r
+ * @param[out] pSinVal points to the processed sine output.\r
+ * @param[out] pCosVal points to the processed cos output.\r
+ */\r
+ void arm_sin_cos_f32(\r
+ float32_t theta,\r
+ float32_t * pSinVal,\r
+ float32_t * pCosVal);\r
+\r
+\r
+ /**\r
+ * @brief Q31 sin_cos function.\r
+ * @param[in] theta scaled input value in degrees\r
+ * @param[out] pSinVal points to the processed sine output.\r
+ * @param[out] pCosVal points to the processed cosine output.\r
+ */\r
+ void arm_sin_cos_q31(\r
+ q31_t theta,\r
+ q31_t * pSinVal,\r
+ q31_t * pCosVal);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex conjugate.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ */\r
+ void arm_cmplx_conj_f32(\r
+ const float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex conjugate.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ */\r
+ void arm_cmplx_conj_q31(\r
+ const q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Q15 complex conjugate.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ */\r
+ void arm_cmplx_conj_q15(\r
+ const q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex magnitude squared\r
+ * @param[in] pSrc points to the complex input vector\r
+ * @param[out] pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ */\r
+ void arm_cmplx_mag_squared_f32(\r
+ const float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Q31 complex magnitude squared\r
+ * @param[in] pSrc points to the complex input vector\r
+ * @param[out] pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ */\r
+ void arm_cmplx_mag_squared_q31(\r
+ const q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Q15 complex magnitude squared\r
+ * @param[in] pSrc points to the complex input vector\r
+ * @param[out] pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ */\r
+ void arm_cmplx_mag_squared_q15(\r
+ const q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup PID PID Motor Control\r
+ *\r
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control\r
+ * loop mechanism widely used in industrial control systems.\r
+ * A PID controller is the most commonly used type of feedback controller.\r
+ *\r
+ * This set of functions implements (PID) controllers\r
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample\r
+ * of data and each call to the function returns a single processed value.\r
+ * <code>S</code> points to an instance of the PID control data structure. <code>in</code>\r
+ * is the input sample value. The functions return the output value.\r
+ *\r
+ * \par Algorithm:\r
+ * <pre>\r
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]\r
+ * A0 = Kp + Ki + Kd\r
+ * A1 = (-Kp ) - (2 * Kd )\r
+ * A2 = Kd\r
+ * </pre>\r
+ *\r
+ * \par\r
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant\r
+ *\r
+ * \par\r
+ * \image html PID.gif "Proportional Integral Derivative Controller"\r
+ *\r
+ * \par\r
+ * The PID controller calculates an "error" value as the difference between\r
+ * the measured output and the reference input.\r
+ * The controller attempts to minimize the error by adjusting the process control inputs.\r
+ * The proportional value determines the reaction to the current error,\r
+ * the integral value determines the reaction based on the sum of recent errors,\r
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.\r
+ *\r
+ * \par Instance Structure\r
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.\r
+ * A separate instance structure must be defined for each PID Controller.\r
+ * There are separate instance structure declarations for each of the 3 supported data types.\r
+ *\r
+ * \par Reset Functions\r
+ * There is also an associated reset function for each data type which clears the state array.\r
+ *\r
+ * \par Initialization Functions\r
+ * There is also an associated initialization function for each data type.\r
+ * The initialization function performs the following operations:\r
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.\r
+ * - Zeros out the values in the state buffer.\r
+ *\r
+ * \par\r
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.\r
+ *\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.\r
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup PID\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Process function for the floating-point PID Control.\r
+ * @param[in,out] S is an instance of the floating-point PID Control structure\r
+ * @param[in] in input sample to process\r
+ * @return processed output sample.\r
+ */\r
+ __STATIC_FORCEINLINE float32_t arm_pid_f32(\r
+ arm_pid_instance_f32 * S,\r
+ float32_t in)\r
+ {\r
+ float32_t out;\r
+\r
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */\r
+ out = (S->A0 * in) +\r
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);\r
+\r
+ /* Update state */\r
+ S->state[1] = S->state[0];\r
+ S->state[0] = in;\r
+ S->state[2] = out;\r
+\r
+ /* return to application */\r
+ return (out);\r
+\r
+ }\r
+\r
+/**\r
+ @brief Process function for the Q31 PID Control.\r
+ @param[in,out] S points to an instance of the Q31 PID Control structure\r
+ @param[in] in input sample to process\r
+ @return processed output sample.\r
+\r
+ \par Scaling and Overflow Behavior\r
+ The function is implemented using an internal 64-bit accumulator.\r
+ The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.\r
+ Thus, if the accumulator result overflows it wraps around rather than clip.\r
+ In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.\r
+ After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.\r
+ */\r
+__STATIC_FORCEINLINE q31_t arm_pid_q31(\r
+ arm_pid_instance_q31 * S,\r
+ q31_t in)\r
+ {\r
+ q63_t acc;\r
+ q31_t out;\r
+\r
+ /* acc = A0 * x[n] */\r
+ acc = (q63_t) S->A0 * in;\r
+\r
+ /* acc += A1 * x[n-1] */\r
+ acc += (q63_t) S->A1 * S->state[0];\r
+\r
+ /* acc += A2 * x[n-2] */\r
+ acc += (q63_t) S->A2 * S->state[1];\r
+\r
+ /* convert output to 1.31 format to add y[n-1] */\r
+ out = (q31_t) (acc >> 31U);\r
+\r
+ /* out += y[n-1] */\r
+ out += S->state[2];\r
+\r
+ /* Update state */\r
+ S->state[1] = S->state[0];\r
+ S->state[0] = in;\r
+ S->state[2] = out;\r
+\r
+ /* return to application */\r
+ return (out);\r
+ }\r
+\r
+\r
+/**\r
+ @brief Process function for the Q15 PID Control.\r
+ @param[in,out] S points to an instance of the Q15 PID Control structure\r
+ @param[in] in input sample to process\r
+ @return processed output sample.\r
+\r
+ \par Scaling and Overflow Behavior\r
+ The function is implemented using a 64-bit internal accumulator.\r
+ Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.\r
+ The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.\r
+ There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.\r
+ After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.\r
+ Lastly, the accumulator is saturated to yield a result in 1.15 format.\r
+ */\r
+__STATIC_FORCEINLINE q15_t arm_pid_q15(\r
+ arm_pid_instance_q15 * S,\r
+ q15_t in)\r
+ {\r
+ q63_t acc;\r
+ q15_t out;\r
+\r
+#if defined (ARM_MATH_DSP)\r
+ /* Implementation of PID controller */\r
+\r
+ /* acc = A0 * x[n] */\r
+ acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);\r
+\r
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */\r
+ acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)read_q15x2 (S->state), (uint64_t)acc);\r
+#else\r
+ /* acc = A0 * x[n] */\r
+ acc = ((q31_t) S->A0) * in;\r
+\r
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */\r
+ acc += (q31_t) S->A1 * S->state[0];\r
+ acc += (q31_t) S->A2 * S->state[1];\r
+#endif\r
+\r
+ /* acc += y[n-1] */\r
+ acc += (q31_t) S->state[2] << 15;\r
+\r
+ /* saturate the output */\r
+ out = (q15_t) (__SSAT((acc >> 15), 16));\r
+\r
+ /* Update state */\r
+ S->state[1] = S->state[0];\r
+ S->state[0] = in;\r
+ S->state[2] = out;\r
+\r
+ /* return to application */\r
+ return (out);\r
+ }\r
+\r
+ /**\r
+ * @} end of PID group\r
+ */\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix inverse.\r
+ * @param[in] src points to the instance of the input floating-point matrix structure.\r
+ * @param[out] dst points to the instance of the output floating-point matrix structure.\r
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\r
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\r
+ */\r
+ arm_status arm_mat_inverse_f32(\r
+ const arm_matrix_instance_f32 * src,\r
+ arm_matrix_instance_f32 * dst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix inverse.\r
+ * @param[in] src points to the instance of the input floating-point matrix structure.\r
+ * @param[out] dst points to the instance of the output floating-point matrix structure.\r
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\r
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\r
+ */\r
+ arm_status arm_mat_inverse_f64(\r
+ const arm_matrix_instance_f64 * src,\r
+ arm_matrix_instance_f64 * dst);\r
+\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup clarke Vector Clarke Transform\r
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.\r
+ * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents\r
+ * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.\r
+ * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below\r
+ * \image html clarke.gif Stator current space vector and its components in (a,b).\r
+ * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>\r
+ * can be calculated using only <code>Ia</code> and <code>Ib</code>.\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output.\r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html clarkeFormula.gif\r
+ * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and\r
+ * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Clarke transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup clarke\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ *\r
+ * @brief Floating-point Clarke transform\r
+ * @param[in] Ia input three-phase coordinate <code>a</code>\r
+ * @param[in] Ib input three-phase coordinate <code>b</code>\r
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @return none\r
+ */\r
+ __STATIC_FORCEINLINE void arm_clarke_f32(\r
+ float32_t Ia,\r
+ float32_t Ib,\r
+ float32_t * pIalpha,\r
+ float32_t * pIbeta)\r
+ {\r
+ /* Calculate pIalpha using the equation, pIalpha = Ia */\r
+ *pIalpha = Ia;\r
+\r
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */\r
+ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);\r
+ }\r
+\r
+\r
+/**\r
+ @brief Clarke transform for Q31 version\r
+ @param[in] Ia input three-phase coordinate <code>a</code>\r
+ @param[in] Ib input three-phase coordinate <code>b</code>\r
+ @param[out] pIalpha points to output two-phase orthogonal vector axis alpha\r
+ @param[out] pIbeta points to output two-phase orthogonal vector axis beta\r
+ @return none\r
+\r
+ \par Scaling and Overflow Behavior\r
+ The function is implemented using an internal 32-bit accumulator.\r
+ The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ There is saturation on the addition, hence there is no risk of overflow.\r
+ */\r
+__STATIC_FORCEINLINE void arm_clarke_q31(\r
+ q31_t Ia,\r
+ q31_t Ib,\r
+ q31_t * pIalpha,\r
+ q31_t * pIbeta)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */\r
+ *pIalpha = Ia;\r
+\r
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */\r
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);\r
+\r
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */\r
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);\r
+\r
+ /* pIbeta is calculated by adding the intermediate products */\r
+ *pIbeta = __QADD(product1, product2);\r
+ }\r
+\r
+ /**\r
+ * @} end of clarke group\r
+ */\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup inv_clarke Vector Inverse Clarke Transform\r
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output.\r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html clarkeInvFormula.gif\r
+ * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and\r
+ * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Clarke transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup inv_clarke\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point Inverse Clarke transform\r
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha\r
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta\r
+ * @param[out] pIa points to output three-phase coordinate <code>a</code>\r
+ * @param[out] pIb points to output three-phase coordinate <code>b</code>\r
+ * @return none\r
+ */\r
+ __STATIC_FORCEINLINE void arm_inv_clarke_f32(\r
+ float32_t Ialpha,\r
+ float32_t Ibeta,\r
+ float32_t * pIa,\r
+ float32_t * pIb)\r
+ {\r
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r
+ *pIa = Ialpha;\r
+\r
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */\r
+ *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;\r
+ }\r
+\r
+\r
+/**\r
+ @brief Inverse Clarke transform for Q31 version\r
+ @param[in] Ialpha input two-phase orthogonal vector axis alpha\r
+ @param[in] Ibeta input two-phase orthogonal vector axis beta\r
+ @param[out] pIa points to output three-phase coordinate <code>a</code>\r
+ @param[out] pIb points to output three-phase coordinate <code>b</code>\r
+ @return none\r
+\r
+ \par Scaling and Overflow Behavior\r
+ The function is implemented using an internal 32-bit accumulator.\r
+ The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ There is saturation on the subtraction, hence there is no risk of overflow.\r
+ */\r
+__STATIC_FORCEINLINE void arm_inv_clarke_q31(\r
+ q31_t Ialpha,\r
+ q31_t Ibeta,\r
+ q31_t * pIa,\r
+ q31_t * pIb)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r
+ *pIa = Ialpha;\r
+\r
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */\r
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */\r
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);\r
+\r
+ /* pIb is calculated by subtracting the products */\r
+ *pIb = __QSUB(product2, product1);\r
+ }\r
+\r
+ /**\r
+ * @} end of inv_clarke group\r
+ */\r
+\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup park Vector Park Transform\r
+ *\r
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.\r
+ * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents\r
+ * from the stationary to the moving reference frame and control the spatial relationship between\r
+ * the stator vector current and rotor flux vector.\r
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the\r
+ * current vector and the relationship from the two reference frames:\r
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output.\r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html parkFormula.gif\r
+ * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,\r
+ * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\r
+ * cosine and sine values of theta (rotor flux position).\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Park transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup park\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point Park transform\r
+ * @param[in] Ialpha input two-phase vector coordinate alpha\r
+ * @param[in] Ibeta input two-phase vector coordinate beta\r
+ * @param[out] pId points to output rotor reference frame d\r
+ * @param[out] pIq points to output rotor reference frame q\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ * @return none\r
+ *\r
+ * The function implements the forward Park transform.\r
+ *\r
+ */\r
+ __STATIC_FORCEINLINE void arm_park_f32(\r
+ float32_t Ialpha,\r
+ float32_t Ibeta,\r
+ float32_t * pId,\r
+ float32_t * pIq,\r
+ float32_t sinVal,\r
+ float32_t cosVal)\r
+ {\r
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */\r
+ *pId = Ialpha * cosVal + Ibeta * sinVal;\r
+\r
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */\r
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;\r
+ }\r
+\r
+\r
+/**\r
+ @brief Park transform for Q31 version\r
+ @param[in] Ialpha input two-phase vector coordinate alpha\r
+ @param[in] Ibeta input two-phase vector coordinate beta\r
+ @param[out] pId points to output rotor reference frame d\r
+ @param[out] pIq points to output rotor reference frame q\r
+ @param[in] sinVal sine value of rotation angle theta\r
+ @param[in] cosVal cosine value of rotation angle theta\r
+ @return none\r
+\r
+ \par Scaling and Overflow Behavior\r
+ The function is implemented using an internal 32-bit accumulator.\r
+ The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ There is saturation on the addition and subtraction, hence there is no risk of overflow.\r
+ */\r
+__STATIC_FORCEINLINE void arm_park_q31(\r
+ q31_t Ialpha,\r
+ q31_t Ibeta,\r
+ q31_t * pId,\r
+ q31_t * pIq,\r
+ q31_t sinVal,\r
+ q31_t cosVal)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Intermediate product is calculated by (Ialpha * cosVal) */\r
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Ibeta * sinVal) */\r
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);\r
+\r
+\r
+ /* Intermediate product is calculated by (Ialpha * sinVal) */\r
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Ibeta * cosVal) */\r
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);\r
+\r
+ /* Calculate pId by adding the two intermediate products 1 and 2 */\r
+ *pId = __QADD(product1, product2);\r
+\r
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */\r
+ *pIq = __QSUB(product4, product3);\r
+ }\r
+\r
+ /**\r
+ * @} end of park group\r
+ */\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup inv_park Vector Inverse Park transform\r
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output.\r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html parkInvFormula.gif\r
+ * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,\r
+ * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\r
+ * cosine and sine values of theta (rotor flux position).\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Park transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup inv_park\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point Inverse Park transform\r
+ * @param[in] Id input coordinate of rotor reference frame d\r
+ * @param[in] Iq input coordinate of rotor reference frame q\r
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ * @return none\r
+ */\r
+ __STATIC_FORCEINLINE void arm_inv_park_f32(\r
+ float32_t Id,\r
+ float32_t Iq,\r
+ float32_t * pIalpha,\r
+ float32_t * pIbeta,\r
+ float32_t sinVal,\r
+ float32_t cosVal)\r
+ {\r
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */\r
+ *pIalpha = Id * cosVal - Iq * sinVal;\r
+\r
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */\r
+ *pIbeta = Id * sinVal + Iq * cosVal;\r
+ }\r
+\r
+\r
+/**\r
+ @brief Inverse Park transform for Q31 version\r
+ @param[in] Id input coordinate of rotor reference frame d\r
+ @param[in] Iq input coordinate of rotor reference frame q\r
+ @param[out] pIalpha points to output two-phase orthogonal vector axis alpha\r
+ @param[out] pIbeta points to output two-phase orthogonal vector axis beta\r
+ @param[in] sinVal sine value of rotation angle theta\r
+ @param[in] cosVal cosine value of rotation angle theta\r
+ @return none\r
+\r
+ @par Scaling and Overflow Behavior\r
+ The function is implemented using an internal 32-bit accumulator.\r
+ The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ There is saturation on the addition, hence there is no risk of overflow.\r
+ */\r
+__STATIC_FORCEINLINE void arm_inv_park_q31(\r
+ q31_t Id,\r
+ q31_t Iq,\r
+ q31_t * pIalpha,\r
+ q31_t * pIbeta,\r
+ q31_t sinVal,\r
+ q31_t cosVal)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Intermediate product is calculated by (Id * cosVal) */\r
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Iq * sinVal) */\r
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);\r
+\r
+\r
+ /* Intermediate product is calculated by (Id * sinVal) */\r
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Iq * cosVal) */\r
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);\r
+\r
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */\r
+ *pIalpha = __QSUB(product1, product2);\r
+\r
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */\r
+ *pIbeta = __QADD(product4, product3);\r
+ }\r
+\r
+ /**\r
+ * @} end of Inverse park group\r
+ */\r
+\r
+\r
+ /**\r
+ * @ingroup groupInterpolation\r
+ */\r
+\r
+ /**\r
+ * @defgroup LinearInterpolate Linear Interpolation\r
+ *\r
+ * Linear interpolation is a method of curve fitting using linear polynomials.\r
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line\r
+ *\r
+ * \par\r
+ * \image html LinearInterp.gif "Linear interpolation"\r
+ *\r
+ * \par\r
+ * A Linear Interpolate function calculates an output value(y), for the input(x)\r
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)\r
+ *\r
+ * \par Algorithm:\r
+ * <pre>\r
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))\r
+ * where x0, x1 are nearest values of input x\r
+ * y0, y1 are nearest values to output y\r
+ * </pre>\r
+ *\r
+ * \par\r
+ * This set of functions implements Linear interpolation process\r
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single\r
+ * sample of data and each call to the function returns a single processed value.\r
+ * <code>S</code> points to an instance of the Linear Interpolate function data structure.\r
+ * <code>x</code> is the input sample value. The functions returns the output value.\r
+ *\r
+ * \par\r
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table\r
+ * if x is below input range and returns last value of table if x is above range.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup LinearInterpolate\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Process function for the floating-point Linear Interpolation Function.\r
+ * @param[in,out] S is an instance of the floating-point Linear Interpolation structure\r
+ * @param[in] x input sample to process\r
+ * @return y processed output sample.\r
+ *\r
+ */\r
+ __STATIC_FORCEINLINE float32_t arm_linear_interp_f32(\r
+ arm_linear_interp_instance_f32 * S,\r
+ float32_t x)\r
+ {\r
+ float32_t y;\r
+ float32_t x0, x1; /* Nearest input values */\r
+ float32_t y0, y1; /* Nearest output values */\r
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */\r
+ int32_t i; /* Index variable */\r
+ float32_t *pYData = S->pYData; /* pointer to output table */\r
+\r
+ /* Calculation of index */\r
+ i = (int32_t) ((x - S->x1) / xSpacing);\r
+\r
+ if (i < 0)\r
+ {\r
+ /* Iniatilize output for below specified range as least output value of table */\r
+ y = pYData[0];\r
+ }\r
+ else if ((uint32_t)i >= S->nValues)\r
+ {\r
+ /* Iniatilize output for above specified range as last output value of table */\r
+ y = pYData[S->nValues - 1];\r
+ }\r
+ else\r
+ {\r
+ /* Calculation of nearest input values */\r
+ x0 = S->x1 + i * xSpacing;\r
+ x1 = S->x1 + (i + 1) * xSpacing;\r
+\r
+ /* Read of nearest output values */\r
+ y0 = pYData[i];\r
+ y1 = pYData[i + 1];\r
+\r
+ /* Calculation of output */\r
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));\r
+\r
+ }\r
+\r
+ /* returns output value */\r
+ return (y);\r
+ }\r
+\r
+\r
+ /**\r
+ *\r
+ * @brief Process function for the Q31 Linear Interpolation Function.\r
+ * @param[in] pYData pointer to Q31 Linear Interpolation table\r
+ * @param[in] x input sample to process\r
+ * @param[in] nValues number of table values\r
+ * @return y processed output sample.\r
+ *\r
+ * \par\r
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
+ * This function can support maximum of table size 2^12.\r
+ *\r
+ */\r
+ __STATIC_FORCEINLINE q31_t arm_linear_interp_q31(\r
+ q31_t * pYData,\r
+ q31_t x,\r
+ uint32_t nValues)\r
+ {\r
+ q31_t y; /* output */\r
+ q31_t y0, y1; /* Nearest output values */\r
+ q31_t fract; /* fractional part */\r
+ int32_t index; /* Index to read nearest output values */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ index = ((x & (q31_t)0xFFF00000) >> 20);\r
+\r
+ if (index >= (int32_t)(nValues - 1))\r
+ {\r
+ return (pYData[nValues - 1]);\r
+ }\r
+ else if (index < 0)\r
+ {\r
+ return (pYData[0]);\r
+ }\r
+ else\r
+ {\r
+ /* 20 bits for the fractional part */\r
+ /* shift left by 11 to keep fract in 1.31 format */\r
+ fract = (x & 0x000FFFFF) << 11;\r
+\r
+ /* Read two nearest output values from the index in 1.31(q31) format */\r
+ y0 = pYData[index];\r
+ y1 = pYData[index + 1];\r
+\r
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */\r
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));\r
+\r
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */\r
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));\r
+\r
+ /* Convert y to 1.31 format */\r
+ return (y << 1U);\r
+ }\r
+ }\r
+\r
+\r
+ /**\r
+ *\r
+ * @brief Process function for the Q15 Linear Interpolation Function.\r
+ * @param[in] pYData pointer to Q15 Linear Interpolation table\r
+ * @param[in] x input sample to process\r
+ * @param[in] nValues number of table values\r
+ * @return y processed output sample.\r
+ *\r
+ * \par\r
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
+ * This function can support maximum of table size 2^12.\r
+ *\r
+ */\r
+ __STATIC_FORCEINLINE q15_t arm_linear_interp_q15(\r
+ q15_t * pYData,\r
+ q31_t x,\r
+ uint32_t nValues)\r
+ {\r
+ q63_t y; /* output */\r
+ q15_t y0, y1; /* Nearest output values */\r
+ q31_t fract; /* fractional part */\r
+ int32_t index; /* Index to read nearest output values */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ index = ((x & (int32_t)0xFFF00000) >> 20);\r
+\r
+ if (index >= (int32_t)(nValues - 1))\r
+ {\r
+ return (pYData[nValues - 1]);\r
+ }\r
+ else if (index < 0)\r
+ {\r
+ return (pYData[0]);\r
+ }\r
+ else\r
+ {\r
+ /* 20 bits for the fractional part */\r
+ /* fract is in 12.20 format */\r
+ fract = (x & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ y0 = pYData[index];\r
+ y1 = pYData[index + 1];\r
+\r
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */\r
+ y = ((q63_t) y0 * (0xFFFFF - fract));\r
+\r
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */\r
+ y += ((q63_t) y1 * (fract));\r
+\r
+ /* convert y to 1.15 format */\r
+ return (q15_t) (y >> 20);\r
+ }\r
+ }\r
+\r
+\r
+ /**\r
+ *\r
+ * @brief Process function for the Q7 Linear Interpolation Function.\r
+ * @param[in] pYData pointer to Q7 Linear Interpolation table\r
+ * @param[in] x input sample to process\r
+ * @param[in] nValues number of table values\r
+ * @return y processed output sample.\r
+ *\r
+ * \par\r
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
+ * This function can support maximum of table size 2^12.\r
+ */\r
+ __STATIC_FORCEINLINE q7_t arm_linear_interp_q7(\r
+ q7_t * pYData,\r
+ q31_t x,\r
+ uint32_t nValues)\r
+ {\r
+ q31_t y; /* output */\r
+ q7_t y0, y1; /* Nearest output values */\r
+ q31_t fract; /* fractional part */\r
+ uint32_t index; /* Index to read nearest output values */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ if (x < 0)\r
+ {\r
+ return (pYData[0]);\r
+ }\r
+ index = (x >> 20) & 0xfff;\r
+\r
+ if (index >= (nValues - 1))\r
+ {\r
+ return (pYData[nValues - 1]);\r
+ }\r
+ else\r
+ {\r
+ /* 20 bits for the fractional part */\r
+ /* fract is in 12.20 format */\r
+ fract = (x & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index and are in 1.7(q7) format */\r
+ y0 = pYData[index];\r
+ y1 = pYData[index + 1];\r
+\r
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */\r
+ y = ((y0 * (0xFFFFF - fract)));\r
+\r
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */\r
+ y += (y1 * fract);\r
+\r
+ /* convert y to 1.7(q7) format */\r
+ return (q7_t) (y >> 20);\r
+ }\r
+ }\r
+\r
+ /**\r
+ * @} end of LinearInterpolate group\r
+ */\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.\r
+ * @param[in] x input value in radians.\r
+ * @return sin(x).\r
+ */\r
+ float32_t arm_sin_f32(\r
+ float32_t x);\r
+\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return sin(x).\r
+ */\r
+ q31_t arm_sin_q31(\r
+ q31_t x);\r
+\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return sin(x).\r
+ */\r
+ q15_t arm_sin_q15(\r
+ q15_t x);\r
+\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.\r
+ * @param[in] x input value in radians.\r
+ * @return cos(x).\r
+ */\r
+ float32_t arm_cos_f32(\r
+ float32_t x);\r
+\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return cos(x).\r
+ */\r
+ q31_t arm_cos_q31(\r
+ q31_t x);\r
+\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return cos(x).\r
+ */\r
+ q15_t arm_cos_q15(\r
+ q15_t x);\r
+\r
+\r
+ /**\r
+ * @ingroup groupFastMath\r
+ */\r
+\r
+\r
+ /**\r
+ * @defgroup SQRT Square Root\r
+ *\r
+ * Computes the square root of a number.\r
+ * There are separate functions for Q15, Q31, and floating-point data types.\r
+ * The square root function is computed using the Newton-Raphson algorithm.\r
+ * This is an iterative algorithm of the form:\r
+ * <pre>\r
+ * x1 = x0 - f(x0)/f'(x0)\r
+ * </pre>\r
+ * where <code>x1</code> is the current estimate,\r
+ * <code>x0</code> is the previous estimate, and\r
+ * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.\r
+ * For the square root function, the algorithm reduces to:\r
+ * <pre>\r
+ * x0 = in/2 [initial guess]\r
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]\r
+ * </pre>\r
+ */\r
+\r
+\r
+ /**\r
+ * @addtogroup SQRT\r
+ * @{\r
+ */\r
+\r
+/**\r
+ @brief Floating-point square root function.\r
+ @param[in] in input value\r
+ @param[out] pOut square root of input value\r
+ @return execution status\r
+ - \ref ARM_MATH_SUCCESS : input value is positive\r
+ - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0\r
+ */\r
+__STATIC_FORCEINLINE arm_status arm_sqrt_f32(\r
+ float32_t in,\r
+ float32_t * pOut)\r
+ {\r
+ if (in >= 0.0f)\r
+ {\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ *pOut = __sqrtf(in);\r
+ #else\r
+ *pOut = sqrtf(in);\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));\r
+ #else\r
+ *pOut = sqrtf(in);\r
+ #endif\r
+\r
+#else\r
+ *pOut = sqrtf(in);\r
+#endif\r
+\r
+ return (ARM_MATH_SUCCESS);\r
+ }\r
+ else\r
+ {\r
+ *pOut = 0.0f;\r
+ return (ARM_MATH_ARGUMENT_ERROR);\r
+ }\r
+ }\r
+\r
+\r
+/**\r
+ @brief Q31 square root function.\r
+ @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF\r
+ @param[out] pOut points to square root of input value\r
+ @return execution status\r
+ - \ref ARM_MATH_SUCCESS : input value is positive\r
+ - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0\r
+ */\r
+arm_status arm_sqrt_q31(\r
+ q31_t in,\r
+ q31_t * pOut);\r
+\r
+\r
+/**\r
+ @brief Q15 square root function.\r
+ @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF\r
+ @param[out] pOut points to square root of input value\r
+ @return execution status\r
+ - \ref ARM_MATH_SUCCESS : input value is positive\r
+ - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0\r
+ */\r
+arm_status arm_sqrt_q15(\r
+ q15_t in,\r
+ q15_t * pOut);\r
+\r
+ /**\r
+ * @} end of SQRT group\r
+ */\r
+\r
+\r
+ /**\r
+ * @brief floating-point Circular write function.\r
+ */\r
+ __STATIC_FORCEINLINE void arm_circularWrite_f32(\r
+ int32_t * circBuffer,\r
+ int32_t L,\r
+ uint16_t * writeOffset,\r
+ int32_t bufferInc,\r
+ const int32_t * src,\r
+ int32_t srcInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0U;\r
+ int32_t wOffset;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location where the input samples to be copied */\r
+ wOffset = *writeOffset;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while (i > 0U)\r
+ {\r
+ /* copy the input sample to the circular buffer */\r
+ circBuffer[wOffset] = *src;\r
+\r
+ /* Update the input pointer */\r
+ src += srcInc;\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ wOffset += bufferInc;\r
+ if (wOffset >= L)\r
+ wOffset -= L;\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *writeOffset = (uint16_t)wOffset;\r
+ }\r
+\r
+\r
+\r
+ /**\r
+ * @brief floating-point Circular Read function.\r
+ */\r
+ __STATIC_FORCEINLINE void arm_circularRead_f32(\r
+ int32_t * circBuffer,\r
+ int32_t L,\r
+ int32_t * readOffset,\r
+ int32_t bufferInc,\r
+ int32_t * dst,\r
+ int32_t * dst_base,\r
+ int32_t dst_length,\r
+ int32_t dstInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0U;\r
+ int32_t rOffset;\r
+ int32_t* dst_end;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location from where the input samples to be read */\r
+ rOffset = *readOffset;\r
+ dst_end = dst_base + dst_length;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while (i > 0U)\r
+ {\r
+ /* copy the sample from the circular buffer to the destination buffer */\r
+ *dst = circBuffer[rOffset];\r
+\r
+ /* Update the input pointer */\r
+ dst += dstInc;\r
+\r
+ if (dst == dst_end)\r
+ {\r
+ dst = dst_base;\r
+ }\r
+\r
+ /* Circularly update rOffset. Watch out for positive and negative value */\r
+ rOffset += bufferInc;\r
+\r
+ if (rOffset >= L)\r
+ {\r
+ rOffset -= L;\r
+ }\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *readOffset = rOffset;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q15 Circular write function.\r
+ */\r
+ __STATIC_FORCEINLINE void arm_circularWrite_q15(\r
+ q15_t * circBuffer,\r
+ int32_t L,\r
+ uint16_t * writeOffset,\r
+ int32_t bufferInc,\r
+ const q15_t * src,\r
+ int32_t srcInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0U;\r
+ int32_t wOffset;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location where the input samples to be copied */\r
+ wOffset = *writeOffset;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while (i > 0U)\r
+ {\r
+ /* copy the input sample to the circular buffer */\r
+ circBuffer[wOffset] = *src;\r
+\r
+ /* Update the input pointer */\r
+ src += srcInc;\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ wOffset += bufferInc;\r
+ if (wOffset >= L)\r
+ wOffset -= L;\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *writeOffset = (uint16_t)wOffset;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q15 Circular Read function.\r
+ */\r
+ __STATIC_FORCEINLINE void arm_circularRead_q15(\r
+ q15_t * circBuffer,\r
+ int32_t L,\r
+ int32_t * readOffset,\r
+ int32_t bufferInc,\r
+ q15_t * dst,\r
+ q15_t * dst_base,\r
+ int32_t dst_length,\r
+ int32_t dstInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0;\r
+ int32_t rOffset;\r
+ q15_t* dst_end;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location from where the input samples to be read */\r
+ rOffset = *readOffset;\r
+\r
+ dst_end = dst_base + dst_length;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while (i > 0U)\r
+ {\r
+ /* copy the sample from the circular buffer to the destination buffer */\r
+ *dst = circBuffer[rOffset];\r
+\r
+ /* Update the input pointer */\r
+ dst += dstInc;\r
+\r
+ if (dst == dst_end)\r
+ {\r
+ dst = dst_base;\r
+ }\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ rOffset += bufferInc;\r
+\r
+ if (rOffset >= L)\r
+ {\r
+ rOffset -= L;\r
+ }\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *readOffset = rOffset;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q7 Circular write function.\r
+ */\r
+ __STATIC_FORCEINLINE void arm_circularWrite_q7(\r
+ q7_t * circBuffer,\r
+ int32_t L,\r
+ uint16_t * writeOffset,\r
+ int32_t bufferInc,\r
+ const q7_t * src,\r
+ int32_t srcInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0U;\r
+ int32_t wOffset;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location where the input samples to be copied */\r
+ wOffset = *writeOffset;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while (i > 0U)\r
+ {\r
+ /* copy the input sample to the circular buffer */\r
+ circBuffer[wOffset] = *src;\r
+\r
+ /* Update the input pointer */\r
+ src += srcInc;\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ wOffset += bufferInc;\r
+ if (wOffset >= L)\r
+ wOffset -= L;\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *writeOffset = (uint16_t)wOffset;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q7 Circular Read function.\r
+ */\r
+ __STATIC_FORCEINLINE void arm_circularRead_q7(\r
+ q7_t * circBuffer,\r
+ int32_t L,\r
+ int32_t * readOffset,\r
+ int32_t bufferInc,\r
+ q7_t * dst,\r
+ q7_t * dst_base,\r
+ int32_t dst_length,\r
+ int32_t dstInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0;\r
+ int32_t rOffset;\r
+ q7_t* dst_end;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location from where the input samples to be read */\r
+ rOffset = *readOffset;\r
+\r
+ dst_end = dst_base + dst_length;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while (i > 0U)\r
+ {\r
+ /* copy the sample from the circular buffer to the destination buffer */\r
+ *dst = circBuffer[rOffset];\r
+\r
+ /* Update the input pointer */\r
+ dst += dstInc;\r
+\r
+ if (dst == dst_end)\r
+ {\r
+ dst = dst_base;\r
+ }\r
+\r
+ /* Circularly update rOffset. Watch out for positive and negative value */\r
+ rOffset += bufferInc;\r
+\r
+ if (rOffset >= L)\r
+ {\r
+ rOffset -= L;\r
+ }\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *readOffset = rOffset;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a Q31 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_power_q31(\r
+ const q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q63_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a floating-point vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_power_f32(\r
+ const float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a Q15 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_power_q15(\r
+ const q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q63_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a Q7 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_power_q7(\r
+ const q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Mean value of a Q7 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_mean_q7(\r
+ const q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q7_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Mean value of a Q15 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_mean_q15(\r
+ const q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Mean value of a Q31 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_mean_q31(\r
+ const q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Mean value of a floating-point vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_mean_f32(\r
+ const float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Variance of the elements of a floating-point vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_var_f32(\r
+ const float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Variance of the elements of a Q31 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_var_q31(\r
+ const q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Variance of the elements of a Q15 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_var_q15(\r
+ const q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Root Mean Square of the elements of a floating-point vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_rms_f32(\r
+ const float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Root Mean Square of the elements of a Q31 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_rms_q31(\r
+ const q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Root Mean Square of the elements of a Q15 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_rms_q15(\r
+ const q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Standard deviation of the elements of a floating-point vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_std_f32(\r
+ const float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Standard deviation of the elements of a Q31 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_std_q31(\r
+ const q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Standard deviation of the elements of a Q15 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_std_q15(\r
+ const q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex magnitude\r
+ * @param[in] pSrc points to the complex input vector\r
+ * @param[out] pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ */\r
+ void arm_cmplx_mag_f32(\r
+ const float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Q31 complex magnitude\r
+ * @param[in] pSrc points to the complex input vector\r
+ * @param[out] pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ */\r
+ void arm_cmplx_mag_q31(\r
+ const q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Q15 complex magnitude\r
+ * @param[in] pSrc points to the complex input vector\r
+ * @param[out] pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ */\r
+ void arm_cmplx_mag_q15(\r
+ const q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Q15 complex dot product\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @param[out] realResult real part of the result returned here\r
+ * @param[out] imagResult imaginary part of the result returned here\r
+ */\r
+ void arm_cmplx_dot_prod_q15(\r
+ const q15_t * pSrcA,\r
+ const q15_t * pSrcB,\r
+ uint32_t numSamples,\r
+ q31_t * realResult,\r
+ q31_t * imagResult);\r
+\r
+\r
+ /**\r
+ * @brief Q31 complex dot product\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @param[out] realResult real part of the result returned here\r
+ * @param[out] imagResult imaginary part of the result returned here\r
+ */\r
+ void arm_cmplx_dot_prod_q31(\r
+ const q31_t * pSrcA,\r
+ const q31_t * pSrcB,\r
+ uint32_t numSamples,\r
+ q63_t * realResult,\r
+ q63_t * imagResult);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex dot product\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @param[out] realResult real part of the result returned here\r
+ * @param[out] imagResult imaginary part of the result returned here\r
+ */\r
+ void arm_cmplx_dot_prod_f32(\r
+ const float32_t * pSrcA,\r
+ const float32_t * pSrcB,\r
+ uint32_t numSamples,\r
+ float32_t * realResult,\r
+ float32_t * imagResult);\r
+\r
+\r
+ /**\r
+ * @brief Q15 complex-by-real multiplication\r
+ * @param[in] pSrcCmplx points to the complex input vector\r
+ * @param[in] pSrcReal points to the real input vector\r
+ * @param[out] pCmplxDst points to the complex output vector\r
+ * @param[in] numSamples number of samples in each vector\r
+ */\r
+ void arm_cmplx_mult_real_q15(\r
+ const q15_t * pSrcCmplx,\r
+ const q15_t * pSrcReal,\r
+ q15_t * pCmplxDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Q31 complex-by-real multiplication\r
+ * @param[in] pSrcCmplx points to the complex input vector\r
+ * @param[in] pSrcReal points to the real input vector\r
+ * @param[out] pCmplxDst points to the complex output vector\r
+ * @param[in] numSamples number of samples in each vector\r
+ */\r
+ void arm_cmplx_mult_real_q31(\r
+ const q31_t * pSrcCmplx,\r
+ const q31_t * pSrcReal,\r
+ q31_t * pCmplxDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex-by-real multiplication\r
+ * @param[in] pSrcCmplx points to the complex input vector\r
+ * @param[in] pSrcReal points to the real input vector\r
+ * @param[out] pCmplxDst points to the complex output vector\r
+ * @param[in] numSamples number of samples in each vector\r
+ */\r
+ void arm_cmplx_mult_real_f32(\r
+ const float32_t * pSrcCmplx,\r
+ const float32_t * pSrcReal,\r
+ float32_t * pCmplxDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Minimum value of a Q7 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] result is output pointer\r
+ * @param[in] index is the array index of the minimum value in the input buffer.\r
+ */\r
+ void arm_min_q7(\r
+ const q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q7_t * result,\r
+ uint32_t * index);\r
+\r
+\r
+ /**\r
+ * @brief Minimum value of a Q15 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output pointer\r
+ * @param[in] pIndex is the array index of the minimum value in the input buffer.\r
+ */\r
+ void arm_min_q15(\r
+ const q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+\r
+ /**\r
+ * @brief Minimum value of a Q31 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output pointer\r
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.\r
+ */\r
+ void arm_min_q31(\r
+ const q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+\r
+ /**\r
+ * @brief Minimum value of a floating-point vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output pointer\r
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.\r
+ */\r
+ void arm_min_f32(\r
+ const float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+\r
+/**\r
+ * @brief Maximum value of a Q7 vector.\r
+ * @param[in] pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] pResult maximum value returned here\r
+ * @param[out] pIndex index of maximum value returned here\r
+ */\r
+ void arm_max_q7(\r
+ const q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q7_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+\r
+/**\r
+ * @brief Maximum value of a Q15 vector.\r
+ * @param[in] pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] pResult maximum value returned here\r
+ * @param[out] pIndex index of maximum value returned here\r
+ */\r
+ void arm_max_q15(\r
+ const q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+\r
+/**\r
+ * @brief Maximum value of a Q31 vector.\r
+ * @param[in] pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] pResult maximum value returned here\r
+ * @param[out] pIndex index of maximum value returned here\r
+ */\r
+ void arm_max_q31(\r
+ const q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+\r
+/**\r
+ * @brief Maximum value of a floating-point vector.\r
+ * @param[in] pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] pResult maximum value returned here\r
+ * @param[out] pIndex index of maximum value returned here\r
+ */\r
+ void arm_max_f32(\r
+ const float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+\r
+ /**\r
+ * @brief Q15 complex-by-complex multiplication\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ */\r
+ void arm_cmplx_mult_cmplx_q15(\r
+ const q15_t * pSrcA,\r
+ const q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Q31 complex-by-complex multiplication\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ */\r
+ void arm_cmplx_mult_cmplx_q31(\r
+ const q31_t * pSrcA,\r
+ const q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex-by-complex multiplication\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ */\r
+ void arm_cmplx_mult_cmplx_f32(\r
+ const float32_t * pSrcA,\r
+ const float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the floating-point vector to Q31 vector.\r
+ * @param[in] pSrc points to the floating-point input vector\r
+ * @param[out] pDst points to the Q31 output vector\r
+ * @param[in] blockSize length of the input vector\r
+ */\r
+ void arm_float_to_q31(\r
+ const float32_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the floating-point vector to Q15 vector.\r
+ * @param[in] pSrc points to the floating-point input vector\r
+ * @param[out] pDst points to the Q15 output vector\r
+ * @param[in] blockSize length of the input vector\r
+ */\r
+ void arm_float_to_q15(\r
+ const float32_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the floating-point vector to Q7 vector.\r
+ * @param[in] pSrc points to the floating-point input vector\r
+ * @param[out] pDst points to the Q7 output vector\r
+ * @param[in] blockSize length of the input vector\r
+ */\r
+ void arm_float_to_q7(\r
+ const float32_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q31 vector to floating-point vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[out] pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ */\r
+ void arm_q31_to_float(\r
+ const q31_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q31 vector to Q15 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[out] pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ */\r
+ void arm_q31_to_q15(\r
+ const q31_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q31 vector to Q7 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[out] pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ */\r
+ void arm_q31_to_q7(\r
+ const q31_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q15 vector to floating-point vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[out] pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ */\r
+ void arm_q15_to_float(\r
+ const q15_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q15 vector to Q31 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[out] pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ */\r
+ void arm_q15_to_q31(\r
+ const q15_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q15 vector to Q7 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[out] pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ */\r
+ void arm_q15_to_q7(\r
+ const q15_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q7 vector to floating-point vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[out] pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ */\r
+ void arm_q7_to_float(\r
+ const q7_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q7 vector to Q31 vector.\r
+ * @param[in] pSrc input pointer\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_q7_to_q31(\r
+ const q7_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q7 vector to Q15 vector.\r
+ * @param[in] pSrc input pointer\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_q7_to_q15(\r
+ const q7_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @ingroup groupInterpolation\r
+ */\r
+\r
+ /**\r
+ * @defgroup BilinearInterpolate Bilinear Interpolation\r
+ *\r
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.\r
+ * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process\r
+ * determines values between the grid points.\r
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.\r
+ * Bilinear interpolation is often used in image processing to rescale images.\r
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.\r
+ *\r
+ * <b>Algorithm</b>\r
+ * \par\r
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.\r
+ * For floating-point, the instance structure is defined as:\r
+ * <pre>\r
+ * typedef struct\r
+ * {\r
+ * uint16_t numRows;\r
+ * uint16_t numCols;\r
+ * float32_t *pData;\r
+ * } arm_bilinear_interp_instance_f32;\r
+ * </pre>\r
+ *\r
+ * \par\r
+ * where <code>numRows</code> specifies the number of rows in the table;\r
+ * <code>numCols</code> specifies the number of columns in the table;\r
+ * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.\r
+ * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.\r
+ * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.\r
+ *\r
+ * \par\r
+ * Let <code>(x, y)</code> specify the desired interpolation point. Then define:\r
+ * <pre>\r
+ * XF = floor(x)\r
+ * YF = floor(y)\r
+ * </pre>\r
+ * \par\r
+ * The interpolated output point is computed as:\r
+ * <pre>\r
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))\r
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))\r
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)\r
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)\r
+ * </pre>\r
+ * Note that the coordinates (x, y) contain integer and fractional components.\r
+ * The integer components specify which portion of the table to use while the\r
+ * fractional components control the interpolation processor.\r
+ *\r
+ * \par\r
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.\r
+ */\r
+\r
+\r
+ /**\r
+ * @addtogroup BilinearInterpolate\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point bilinear interpolation.\r
+ * @param[in,out] S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate.\r
+ * @param[in] Y interpolation coordinate.\r
+ * @return out interpolated value.\r
+ */\r
+ __STATIC_FORCEINLINE float32_t arm_bilinear_interp_f32(\r
+ const arm_bilinear_interp_instance_f32 * S,\r
+ float32_t X,\r
+ float32_t Y)\r
+ {\r
+ float32_t out;\r
+ float32_t f00, f01, f10, f11;\r
+ float32_t *pData = S->pData;\r
+ int32_t xIndex, yIndex, index;\r
+ float32_t xdiff, ydiff;\r
+ float32_t b1, b2, b3, b4;\r
+\r
+ xIndex = (int32_t) X;\r
+ yIndex = (int32_t) Y;\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))\r
+ {\r
+ return (0);\r
+ }\r
+\r
+ /* Calculation of index for two nearest points in X-direction */\r
+ index = (xIndex - 1) + (yIndex - 1) * S->numCols;\r
+\r
+\r
+ /* Read two nearest points in X-direction */\r
+ f00 = pData[index];\r
+ f01 = pData[index + 1];\r
+\r
+ /* Calculation of index for two nearest points in Y-direction */\r
+ index = (xIndex - 1) + (yIndex) * S->numCols;\r
+\r
+\r
+ /* Read two nearest points in Y-direction */\r
+ f10 = pData[index];\r
+ f11 = pData[index + 1];\r
+\r
+ /* Calculation of intermediate values */\r
+ b1 = f00;\r
+ b2 = f01 - f00;\r
+ b3 = f10 - f00;\r
+ b4 = f00 - f01 - f10 + f11;\r
+\r
+ /* Calculation of fractional part in X */\r
+ xdiff = X - xIndex;\r
+\r
+ /* Calculation of fractional part in Y */\r
+ ydiff = Y - yIndex;\r
+\r
+ /* Calculation of bi-linear interpolated output */\r
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;\r
+\r
+ /* return to application */\r
+ return (out);\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q31 bilinear interpolation.\r
+ * @param[in,out] S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate in 12.20 format.\r
+ * @param[in] Y interpolation coordinate in 12.20 format.\r
+ * @return out interpolated value.\r
+ */\r
+ __STATIC_FORCEINLINE q31_t arm_bilinear_interp_q31(\r
+ arm_bilinear_interp_instance_q31 * S,\r
+ q31_t X,\r
+ q31_t Y)\r
+ {\r
+ q31_t out; /* Temporary output */\r
+ q31_t acc = 0; /* output */\r
+ q31_t xfract, yfract; /* X, Y fractional parts */\r
+ q31_t x1, x2, y1, y2; /* Nearest output values */\r
+ int32_t rI, cI; /* Row and column indices */\r
+ q31_t *pYData = S->pData; /* pointer to output table values */\r
+ uint32_t nCols = S->numCols; /* num of rows */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ rI = ((X & (q31_t)0xFFF00000) >> 20);\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r
+ {\r
+ return (0);\r
+ }\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* shift left xfract by 11 to keep 1.31 format */\r
+ xfract = (X & 0x000FFFFF) << 11U;\r
+\r
+ /* Read two nearest output values from the index */\r
+ x1 = pYData[(rI) + (int32_t)nCols * (cI) ];\r
+ x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* shift left yfract by 11 to keep 1.31 format */\r
+ yfract = (Y & 0x000FFFFF) << 11U;\r
+\r
+ /* Read two nearest output values from the index */\r
+ y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];\r
+ y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];\r
+\r
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */\r
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));\r
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));\r
+\r
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */\r
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));\r
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));\r
+\r
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */\r
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));\r
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r
+\r
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */\r
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));\r
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r
+\r
+ /* Convert acc to 1.31(q31) format */\r
+ return ((q31_t)(acc << 2));\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q15 bilinear interpolation.\r
+ * @param[in,out] S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate in 12.20 format.\r
+ * @param[in] Y interpolation coordinate in 12.20 format.\r
+ * @return out interpolated value.\r
+ */\r
+ __STATIC_FORCEINLINE q15_t arm_bilinear_interp_q15(\r
+ arm_bilinear_interp_instance_q15 * S,\r
+ q31_t X,\r
+ q31_t Y)\r
+ {\r
+ q63_t acc = 0; /* output */\r
+ q31_t out; /* Temporary output */\r
+ q15_t x1, x2, y1, y2; /* Nearest output values */\r
+ q31_t xfract, yfract; /* X, Y fractional parts */\r
+ int32_t rI, cI; /* Row and column indices */\r
+ q15_t *pYData = S->pData; /* pointer to output table values */\r
+ uint32_t nCols = S->numCols; /* num of rows */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ rI = ((X & (q31_t)0xFFF00000) >> 20);\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r
+ {\r
+ return (0);\r
+ }\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* xfract should be in 12.20 format */\r
+ xfract = (X & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];\r
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* yfract should be in 12.20 format */\r
+ yfract = (Y & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];\r
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];\r
+\r
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */\r
+\r
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */\r
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */\r
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U);\r
+ acc = ((q63_t) out * (0xFFFFF - yfract));\r
+\r
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */\r
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U);\r
+ acc += ((q63_t) out * (xfract));\r
+\r
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */\r
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U);\r
+ acc += ((q63_t) out * (yfract));\r
+\r
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */\r
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U);\r
+ acc += ((q63_t) out * (yfract));\r
+\r
+ /* acc is in 13.51 format and down shift acc by 36 times */\r
+ /* Convert out to 1.15 format */\r
+ return ((q15_t)(acc >> 36));\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q7 bilinear interpolation.\r
+ * @param[in,out] S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate in 12.20 format.\r
+ * @param[in] Y interpolation coordinate in 12.20 format.\r
+ * @return out interpolated value.\r
+ */\r
+ __STATIC_FORCEINLINE q7_t arm_bilinear_interp_q7(\r
+ arm_bilinear_interp_instance_q7 * S,\r
+ q31_t X,\r
+ q31_t Y)\r
+ {\r
+ q63_t acc = 0; /* output */\r
+ q31_t out; /* Temporary output */\r
+ q31_t xfract, yfract; /* X, Y fractional parts */\r
+ q7_t x1, x2, y1, y2; /* Nearest output values */\r
+ int32_t rI, cI; /* Row and column indices */\r
+ q7_t *pYData = S->pData; /* pointer to output table values */\r
+ uint32_t nCols = S->numCols; /* num of rows */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ rI = ((X & (q31_t)0xFFF00000) >> 20);\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r
+ {\r
+ return (0);\r
+ }\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* xfract should be in 12.20 format */\r
+ xfract = (X & (q31_t)0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];\r
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* yfract should be in 12.20 format */\r
+ yfract = (Y & (q31_t)0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];\r
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];\r
+\r
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */\r
+ out = ((x1 * (0xFFFFF - xfract)));\r
+ acc = (((q63_t) out * (0xFFFFF - yfract)));\r
+\r
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */\r
+ out = ((x2 * (0xFFFFF - yfract)));\r
+ acc += (((q63_t) out * (xfract)));\r
+\r
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */\r
+ out = ((y1 * (0xFFFFF - xfract)));\r
+ acc += (((q63_t) out * (yfract)));\r
+\r
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */\r
+ out = ((y2 * (yfract)));\r
+ acc += (((q63_t) out * (xfract)));\r
+\r
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */\r
+ return ((q7_t)(acc >> 40));\r
+ }\r
+\r
+ /**\r
+ * @} end of BilinearInterpolate group\r
+ */\r
+\r
+\r
+/* SMMLAR */\r
+#define multAcc_32x32_keep32_R(a, x, y) \\r
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)\r
+\r
+/* SMMLSR */\r
+#define multSub_32x32_keep32_R(a, x, y) \\r
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)\r
+\r
+/* SMMULR */\r
+#define mult_32x32_keep32_R(a, x, y) \\r
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)\r
+\r
+/* SMMLA */\r
+#define multAcc_32x32_keep32(a, x, y) \\r
+ a += (q31_t) (((q63_t) x * y) >> 32)\r
+\r
+/* SMMLS */\r
+#define multSub_32x32_keep32(a, x, y) \\r
+ a -= (q31_t) (((q63_t) x * y) >> 32)\r
+\r
+/* SMMUL */\r
+#define mult_32x32_keep32(a, x, y) \\r
+ a = (q31_t) (((q63_t) x * y ) >> 32)\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ /* Enter low optimization region - place directly above function definition */\r
+ #if defined( __ARM_ARCH_7EM__ )\r
+ #define LOW_OPTIMIZATION_ENTER \\r
+ _Pragma ("push") \\r
+ _Pragma ("O1")\r
+ #else\r
+ #define LOW_OPTIMIZATION_ENTER\r
+ #endif\r
+\r
+ /* Exit low optimization region - place directly after end of function definition */\r
+ #if defined ( __ARM_ARCH_7EM__ )\r
+ #define LOW_OPTIMIZATION_EXIT \\r
+ _Pragma ("pop")\r
+ #else\r
+ #define LOW_OPTIMIZATION_EXIT\r
+ #endif\r
+\r
+ /* Enter low optimization region - place directly above function definition */\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
+\r
+ /* Exit low optimization region - place directly after end of function definition */\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )\r
+ #define LOW_OPTIMIZATION_ENTER\r
+ #define LOW_OPTIMIZATION_EXIT\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define LOW_OPTIMIZATION_ENTER \\r
+ __attribute__(( optimize("-O1") ))\r
+ #define LOW_OPTIMIZATION_EXIT\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#elif defined ( __ICCARM__ )\r
+ /* Enter low optimization region - place directly above function definition */\r
+ #if defined ( __ARM_ARCH_7EM__ )\r
+ #define LOW_OPTIMIZATION_ENTER \\r
+ _Pragma ("optimize=low")\r
+ #else\r
+ #define LOW_OPTIMIZATION_ENTER\r
+ #endif\r
+\r
+ /* Exit low optimization region - place directly after end of function definition */\r
+ #define LOW_OPTIMIZATION_EXIT\r
+\r
+ /* Enter low optimization region - place directly above function definition */\r
+ #if defined ( __ARM_ARCH_7EM__ )\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \\r
+ _Pragma ("optimize=low")\r
+ #else\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
+ #endif\r
+\r
+ /* Exit low optimization region - place directly after end of function definition */\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #define LOW_OPTIMIZATION_ENTER\r
+ #define LOW_OPTIMIZATION_EXIT\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#elif defined ( __CSMC__ )\r
+ #define LOW_OPTIMIZATION_ENTER\r
+ #define LOW_OPTIMIZATION_EXIT\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define LOW_OPTIMIZATION_ENTER\r
+ #define LOW_OPTIMIZATION_EXIT\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#endif\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/* Compiler specific diagnostic adjustment */\r
+#if defined ( __CC_ARM )\r
+\r
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )\r
+\r
+#elif defined ( __GNUC__ )\r
+#pragma GCC diagnostic pop\r
+\r
+#elif defined ( __ICCARM__ )\r
+\r
+#elif defined ( __TI_ARM__ )\r
+\r
+#elif defined ( __CSMC__ )\r
+\r
+#elif defined ( __TASKING__ )\r
+\r
+#else\r
+ #error Unknown compiler\r
+#endif\r
+\r
+#endif /* _ARM_MATH_H */\r
+\r
+/**\r
+ *\r
+ * End of file.\r
+ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_armcc.h\r
+ * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file\r
+ * @version V5.0.5\r
+ * @date 14. December 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#ifndef __CMSIS_ARMCC_H\r
+#define __CMSIS_ARMCC_H\r
+\r
+\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)\r
+ #error "Please use Arm Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+/* CMSIS compiler control architecture macros */\r
+#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \\r
+ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )\r
+ #define __ARM_ARCH_6M__ 1\r
+#endif\r
+\r
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))\r
+ #define __ARM_ARCH_7M__ 1\r
+#endif\r
+\r
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))\r
+ #define __ARM_ARCH_7EM__ 1\r
+#endif\r
+\r
+ /* __ARM_ARCH_8M_BASE__ not applicable */\r
+ /* __ARM_ARCH_8M_MAIN__ not applicable */\r
+\r
+/* CMSIS compiler control DSP macros */\r
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )\r
+ #define __ARM_FEATURE_DSP 1\r
+#endif\r
+\r
+/* CMSIS compiler specific defines */\r
+#ifndef __ASM\r
+ #define __ASM __asm\r
+#endif\r
+#ifndef __INLINE\r
+ #define __INLINE __inline\r
+#endif\r
+#ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static __inline\r
+#endif\r
+#ifndef __STATIC_FORCEINLINE \r
+ #define __STATIC_FORCEINLINE static __forceinline\r
+#endif \r
+#ifndef __NO_RETURN\r
+ #define __NO_RETURN __declspec(noreturn)\r
+#endif\r
+#ifndef __USED\r
+ #define __USED __attribute__((used))\r
+#endif\r
+#ifndef __WEAK\r
+ #define __WEAK __attribute__((weak))\r
+#endif\r
+#ifndef __PACKED\r
+ #define __PACKED __attribute__((packed))\r
+#endif\r
+#ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT __packed struct\r
+#endif\r
+#ifndef __PACKED_UNION\r
+ #define __PACKED_UNION __packed union\r
+#endif\r
+#ifndef __UNALIGNED_UINT32 /* deprecated */\r
+ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_WRITE\r
+ #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_READ\r
+ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_WRITE\r
+ #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_READ\r
+ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))\r
+#endif\r
+#ifndef __ALIGNED\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+#endif\r
+#ifndef __RESTRICT\r
+ #define __RESTRICT __restrict\r
+#endif\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Enable IRQ Interrupts\r
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+/* intrinsic void __enable_irq(); */\r
+\r
+\r
+/**\r
+ \brief Disable IRQ Interrupts\r
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+/**\r
+ \brief Get Control Register\r
+ \details Returns the content of the Control Register.\r
+ \return Control Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Control Register\r
+ \details Writes the given value to the Control Register.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get IPSR Register\r
+ \details Returns the content of the IPSR Register.\r
+ \return IPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ register uint32_t __regIPSR __ASM("ipsr");\r
+ return(__regIPSR);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get APSR Register\r
+ \details Returns the content of the APSR Register.\r
+ \return APSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ register uint32_t __regAPSR __ASM("apsr");\r
+ return(__regAPSR);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get xPSR Register\r
+ \details Returns the content of the xPSR Register.\r
+ \return xPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ register uint32_t __regXPSR __ASM("xpsr");\r
+ return(__regXPSR);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Process Stack Pointer\r
+ \details Returns the current value of the Process Stack Pointer (PSP).\r
+ \return PSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ return(__regProcessStackPointer);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer\r
+ \details Assigns the given value to the Process Stack Pointer (PSP).\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ __regProcessStackPointer = topOfProcStack;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer\r
+ \details Returns the current value of the Main Stack Pointer (MSP).\r
+ \return MSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ return(__regMainStackPointer);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer\r
+ \details Assigns the given value to the Main Stack Pointer (MSP).\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ __regMainStackPointer = topOfMainStack;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Mask\r
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Priority Mask\r
+ \details Assigns the given value to the Priority Mask Register.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )\r
+\r
+/**\r
+ \brief Enable FIQ\r
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_fault_irq __enable_fiq\r
+\r
+\r
+/**\r
+ \brief Disable FIQ\r
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+\r
+/**\r
+ \brief Get Base Priority\r
+ \details Returns the current value of the Base Priority register.\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Base Priority\r
+ \details Assigns the given value to the Base Priority register.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0xFFU);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Base Priority with condition\r
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
+ or the new value increases the BASEPRI priority level.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePriMax __ASM("basepri_max");\r
+ __regBasePriMax = (basePri & 0xFFU);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Fault Mask\r
+ \details Returns the current value of the Fault Mask register.\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Fault Mask\r
+ \details Assigns the given value to the Fault Mask register.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & (uint32_t)1U);\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */\r
+\r
+\r
+/**\r
+ \brief Get FPSCR\r
+ \details Returns the current value of the Floating Point Status/Control register.\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ return(__regfpscr);\r
+#else\r
+ return(0U);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Set FPSCR\r
+ \details Assigns the given value to the Floating Point Status/Control register.\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ __regfpscr = (fpscr);\r
+#else\r
+ (void)fpscr;\r
+#endif\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+/**\r
+ \brief No Operation\r
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP __nop\r
+\r
+\r
+/**\r
+ \brief Wait For Interrupt\r
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
+ */\r
+#define __WFI __wfi\r
+\r
+\r
+/**\r
+ \brief Wait For Event\r
+ \details Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE __wfe\r
+\r
+\r
+/**\r
+ \brief Send Event\r
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV __sev\r
+\r
+\r
+/**\r
+ \brief Instruction Synchronization Barrier\r
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or memory,\r
+ after the instruction has been completed.\r
+ */\r
+#define __ISB() do {\\r
+ __schedule_barrier();\\r
+ __isb(0xF);\\r
+ __schedule_barrier();\\r
+ } while (0U)\r
+\r
+/**\r
+ \brief Data Synchronization Barrier\r
+ \details Acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+#define __DSB() do {\\r
+ __schedule_barrier();\\r
+ __dsb(0xF);\\r
+ __schedule_barrier();\\r
+ } while (0U)\r
+\r
+/**\r
+ \brief Data Memory Barrier\r
+ \details Ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+#define __DMB() do {\\r
+ __schedule_barrier();\\r
+ __dmb(0xF);\\r
+ __schedule_barrier();\\r
+ } while (0U)\r
+\r
+ \r
+/**\r
+ \brief Reverse byte order (32 bit)\r
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV __rev\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\r
+{\r
+ rev16 r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)\r
+{\r
+ revsh r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Rotate Right in unsigned value (32 bit)\r
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+ \param [in] op1 Value to rotate\r
+ \param [in] op2 Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+#define __ROR __ror\r
+\r
+\r
+/**\r
+ \brief Breakpoint\r
+ \details Causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __breakpoint(value)\r
+\r
+\r
+/**\r
+ \brief Reverse bit order of value\r
+ \details Reverses the bit order of the given value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )\r
+ #define __RBIT __rbit\r
+#else\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */\r
+\r
+ result = value; /* r will be reversed bits of v; first get LSB of v */\r
+ for (value >>= 1U; value != 0U; value >>= 1U)\r
+ {\r
+ result <<= 1U;\r
+ result |= value & 1U;\r
+ s--;\r
+ }\r
+ result <<= s; /* shift when v's highest bits are zero */\r
+ return result;\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Count leading zeros\r
+ \details Counts the number of leading zeros of a data value.\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __clz\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )\r
+\r
+/**\r
+ \brief LDR Exclusive (8 bit)\r
+ \details Executes a exclusive LDR instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
+#else\r
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (16 bit)\r
+ \details Executes a exclusive LDR instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
+#else\r
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (32 bit)\r
+ \details Executes a exclusive LDR instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
+#else\r
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (8 bit)\r
+ \details Executes a exclusive STR instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __STREXB(value, ptr) __strex(value, ptr)\r
+#else\r
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (16 bit)\r
+ \details Executes a exclusive STR instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __STREXH(value, ptr) __strex(value, ptr)\r
+#else\r
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (32 bit)\r
+ \details Executes a exclusive STR instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __STREXW(value, ptr) __strex(value, ptr)\r
+#else\r
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Remove the exclusive lock\r
+ \details Removes the exclusive lock which is created by LDREX.\r
+ */\r
+#define __CLREX __clrex\r
+\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT __ssat\r
+\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT __usat\r
+\r
+\r
+/**\r
+ \brief Rotate Right with Extend (32 bit)\r
+ \details Moves each bit of a bitstring right by one bit.\r
+ The carry input is shifted in at the left end of the bitstring.\r
+ \param [in] value Value to rotate\r
+ \return Rotated value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)\r
+{\r
+ rrx r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged STRT instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+#define __STRBT(value, ptr) __strt(value, ptr)\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged STRT instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+#define __STRHT(value, ptr) __strt(value, ptr)\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged STRT instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+#define __STRT(value, ptr) __strt(value, ptr)\r
+\r
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)\r
+{\r
+ if ((sat >= 1U) && (sat <= 32U))\r
+ {\r
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\r
+ const int32_t min = -1 - max ;\r
+ if (val > max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < min)\r
+ {\r
+ return min;\r
+ }\r
+ }\r
+ return val;\r
+}\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)\r
+{\r
+ if (sat <= 31U)\r
+ {\r
+ const uint32_t max = ((1U << sat) - 1U);\r
+ if (val > (int32_t)max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < 0)\r
+ {\r
+ return 0U;\r
+ }\r
+ }\r
+ return (uint32_t)val;\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )\r
+\r
+#define __SADD8 __sadd8\r
+#define __QADD8 __qadd8\r
+#define __SHADD8 __shadd8\r
+#define __UADD8 __uadd8\r
+#define __UQADD8 __uqadd8\r
+#define __UHADD8 __uhadd8\r
+#define __SSUB8 __ssub8\r
+#define __QSUB8 __qsub8\r
+#define __SHSUB8 __shsub8\r
+#define __USUB8 __usub8\r
+#define __UQSUB8 __uqsub8\r
+#define __UHSUB8 __uhsub8\r
+#define __SADD16 __sadd16\r
+#define __QADD16 __qadd16\r
+#define __SHADD16 __shadd16\r
+#define __UADD16 __uadd16\r
+#define __UQADD16 __uqadd16\r
+#define __UHADD16 __uhadd16\r
+#define __SSUB16 __ssub16\r
+#define __QSUB16 __qsub16\r
+#define __SHSUB16 __shsub16\r
+#define __USUB16 __usub16\r
+#define __UQSUB16 __uqsub16\r
+#define __UHSUB16 __uhsub16\r
+#define __SASX __sasx\r
+#define __QASX __qasx\r
+#define __SHASX __shasx\r
+#define __UASX __uasx\r
+#define __UQASX __uqasx\r
+#define __UHASX __uhasx\r
+#define __SSAX __ssax\r
+#define __QSAX __qsax\r
+#define __SHSAX __shsax\r
+#define __USAX __usax\r
+#define __UQSAX __uqsax\r
+#define __UHSAX __uhsax\r
+#define __USAD8 __usad8\r
+#define __USADA8 __usada8\r
+#define __SSAT16 __ssat16\r
+#define __USAT16 __usat16\r
+#define __UXTB16 __uxtb16\r
+#define __UXTAB16 __uxtab16\r
+#define __SXTB16 __sxtb16\r
+#define __SXTAB16 __sxtab16\r
+#define __SMUAD __smuad\r
+#define __SMUADX __smuadx\r
+#define __SMLAD __smlad\r
+#define __SMLADX __smladx\r
+#define __SMLALD __smlald\r
+#define __SMLALDX __smlaldx\r
+#define __SMUSD __smusd\r
+#define __SMUSDX __smusdx\r
+#define __SMLSD __smlsd\r
+#define __SMLSDX __smlsdx\r
+#define __SMLSLD __smlsld\r
+#define __SMLSLDX __smlsldx\r
+#define __SEL __sel\r
+#define __QADD __qadd\r
+#define __QSUB __qsub\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \\r
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \\r
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )\r
+\r
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \\r
+ ((int64_t)(ARG3) << 32U) ) >> 32U))\r
+\r
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#endif /* __CMSIS_ARMCC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_armclang.h\r
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file\r
+ * @version V5.1.0\r
+ * @date 14. March 2019\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */\r
+\r
+#ifndef __CMSIS_ARMCLANG_H\r
+#define __CMSIS_ARMCLANG_H\r
+\r
+#pragma clang system_header /* treat file as system include file */\r
+\r
+#ifndef __ARM_COMPAT_H\r
+#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */\r
+#endif\r
+\r
+/* CMSIS compiler specific defines */\r
+#ifndef __ASM\r
+ #define __ASM __asm\r
+#endif\r
+#ifndef __INLINE\r
+ #define __INLINE __inline\r
+#endif\r
+#ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static __inline\r
+#endif\r
+#ifndef __STATIC_FORCEINLINE\r
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline\r
+#endif\r
+#ifndef __NO_RETURN\r
+ #define __NO_RETURN __attribute__((__noreturn__))\r
+#endif\r
+#ifndef __USED\r
+ #define __USED __attribute__((used))\r
+#endif\r
+#ifndef __WEAK\r
+ #define __WEAK __attribute__((weak))\r
+#endif\r
+#ifndef __PACKED\r
+ #define __PACKED __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __PACKED_UNION\r
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32 /* deprecated */\r
+ #pragma clang diagnostic push\r
+ #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */\r
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };\r
+ #pragma clang diagnostic pop\r
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_WRITE\r
+ #pragma clang diagnostic push\r
+ #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */\r
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
+ #pragma clang diagnostic pop\r
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_READ\r
+ #pragma clang diagnostic push\r
+ #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */\r
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
+ #pragma clang diagnostic pop\r
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_WRITE\r
+ #pragma clang diagnostic push\r
+ #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */\r
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
+ #pragma clang diagnostic pop\r
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_READ\r
+ #pragma clang diagnostic push\r
+ #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */\r
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
+ #pragma clang diagnostic pop\r
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
+#endif\r
+#ifndef __ALIGNED\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+#endif\r
+#ifndef __RESTRICT\r
+ #define __RESTRICT __restrict\r
+#endif\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Enable IRQ Interrupts\r
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+/* intrinsic void __enable_irq(); see arm_compat.h */\r
+\r
+\r
+/**\r
+ \brief Disable IRQ Interrupts\r
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+/* intrinsic void __disable_irq(); see arm_compat.h */\r
+\r
+\r
+/**\r
+ \brief Get Control Register\r
+ \details Returns the content of the Control Register.\r
+ \return Control Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Control Register (non-secure)\r
+ \details Returns the content of the non-secure Control Register when in secure mode.\r
+ \return non-secure Control Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Control Register\r
+ \details Writes the given value to the Control Register.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Control Register (non-secure)\r
+ \details Writes the given value to the non-secure Control Register when in secure state.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get IPSR Register\r
+ \details Returns the content of the IPSR Register.\r
+ \return IPSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get APSR Register\r
+ \details Returns the content of the APSR Register.\r
+ \return APSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get xPSR Register\r
+ \details Returns the content of the xPSR Register.\r
+ \return xPSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Process Stack Pointer\r
+ \details Returns the current value of the Process Stack Pointer (PSP).\r
+ \return PSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Process Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\r
+ \return PSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer\r
+ \details Assigns the given value to the Process Stack Pointer (PSP).\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Process Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer\r
+ \details Returns the current value of the Main Stack Pointer (MSP).\r
+ \return MSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Main Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\r
+ \return MSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer\r
+ \details Assigns the given value to the Main Stack Pointer (MSP).\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Main Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );\r
+}\r
+#endif\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\r
+ \return SP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\r
+ \param [in] topOfStack Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)\r
+{\r
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Priority Mask\r
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Priority Mask (non-secure)\r
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Priority Mask\r
+ \details Assigns the given value to the Priority Mask Register.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Priority Mask (non-secure)\r
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+/**\r
+ \brief Enable FIQ\r
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */\r
+\r
+\r
+/**\r
+ \brief Disable FIQ\r
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */\r
+\r
+\r
+/**\r
+ \brief Get Base Priority\r
+ \details Returns the current value of the Base Priority register.\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Base Priority (non-secure)\r
+ \details Returns the current value of the non-secure Base Priority register when in secure state.\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Base Priority\r
+ \details Assigns the given value to the Base Priority register.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Base Priority (non-secure)\r
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Base Priority with condition\r
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
+ or the new value increases the BASEPRI priority level.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Fault Mask\r
+ \details Returns the current value of the Fault Mask register.\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Fault Mask (non-secure)\r
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Fault Mask\r
+ \details Assigns the given value to the Fault Mask register.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Fault Mask (non-secure)\r
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");\r
+}\r
+#endif\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+\r
+/**\r
+ \brief Get Process Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always in non-secure\r
+ mode.\r
+ \r
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\r
+ \return PSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ uint32_t result;\r
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+\r
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Process Stack Pointer Limit (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always in non-secure\r
+ mode.\r
+\r
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
+ \return PSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ uint32_t result;\r
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored in non-secure\r
+ mode.\r
+ \r
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\r
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ (void)ProcStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Process Stack Pointer (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored in non-secure\r
+ mode.\r
+\r
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ (void)ProcStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always.\r
+\r
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\r
+ \return MSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ uint32_t result;\r
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Main Stack Pointer Limit (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always.\r
+\r
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\r
+ \return MSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ uint32_t result;\r
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored.\r
+\r
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\r
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ (void)MainStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Main Stack Pointer Limit (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored.\r
+\r
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\r
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ (void)MainStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));\r
+#endif\r
+}\r
+#endif\r
+\r
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+/**\r
+ \brief Get FPSCR\r
+ \details Returns the current value of the Floating Point Status/Control register.\r
+ \return Floating Point Status/Control register value\r
+ */\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr\r
+#else\r
+#define __get_FPSCR() ((uint32_t)0U)\r
+#endif\r
+\r
+/**\r
+ \brief Set FPSCR\r
+ \details Assigns the given value to the Floating Point Status/Control register.\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+#define __set_FPSCR __builtin_arm_set_fpscr\r
+#else\r
+#define __set_FPSCR(x) ((void)(x))\r
+#endif\r
+\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+/* Define macros for porting to both thumb1 and thumb2.\r
+ * For thumb1, use low register (r0-r7), specified by constraint "l"\r
+ * Otherwise, use general registers, specified by constraint "r" */\r
+#if defined (__thumb__) && !defined (__thumb2__)\r
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
+#else\r
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
+#endif\r
+\r
+/**\r
+ \brief No Operation\r
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP __builtin_arm_nop\r
+\r
+/**\r
+ \brief Wait For Interrupt\r
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
+ */\r
+#define __WFI __builtin_arm_wfi\r
+\r
+\r
+/**\r
+ \brief Wait For Event\r
+ \details Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE __builtin_arm_wfe\r
+\r
+\r
+/**\r
+ \brief Send Event\r
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV __builtin_arm_sev\r
+\r
+\r
+/**\r
+ \brief Instruction Synchronization Barrier\r
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or memory,\r
+ after the instruction has been completed.\r
+ */\r
+#define __ISB() __builtin_arm_isb(0xF)\r
+\r
+/**\r
+ \brief Data Synchronization Barrier\r
+ \details Acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+#define __DSB() __builtin_arm_dsb(0xF)\r
+\r
+\r
+/**\r
+ \brief Data Memory Barrier\r
+ \details Ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+#define __DMB() __builtin_arm_dmb(0xF)\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (32 bit)\r
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV(value) __builtin_bswap32(value)\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV16(value) __ROR(__REV(value), 16)\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)\r
+\r
+\r
+/**\r
+ \brief Rotate Right in unsigned value (32 bit)\r
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+ \param [in] op1 Value to rotate\r
+ \param [in] op2 Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+{\r
+ op2 %= 32U;\r
+ if (op2 == 0U)\r
+ {\r
+ return op1;\r
+ }\r
+ return (op1 >> op2) | (op1 << (32U - op2));\r
+}\r
+\r
+\r
+/**\r
+ \brief Breakpoint\r
+ \details Causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
+\r
+\r
+/**\r
+ \brief Reverse bit order of value\r
+ \details Reverses the bit order of the given value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __RBIT __builtin_arm_rbit\r
+\r
+/**\r
+ \brief Count leading zeros\r
+ \details Counts the number of leading zeros of a data value.\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)\r
+{\r
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally\r
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.\r
+ This guarantees ARM-compatible results if happening to compile on a non-ARM\r
+ target, and ensures the compiler doesn't decide to activate any\r
+ optimisations using the logic "value was passed to __builtin_clz, so it\r
+ is non-zero".\r
+ ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a\r
+ single CLZ instruction.\r
+ */\r
+ if (value == 0U)\r
+ {\r
+ return 32U;\r
+ }\r
+ return __builtin_clz(value);\r
+}\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+/**\r
+ \brief LDR Exclusive (8 bit)\r
+ \details Executes a exclusive LDR instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDREXB (uint8_t)__builtin_arm_ldrex\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (16 bit)\r
+ \details Executes a exclusive LDR instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDREXH (uint16_t)__builtin_arm_ldrex\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (32 bit)\r
+ \details Executes a exclusive LDR instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDREXW (uint32_t)__builtin_arm_ldrex\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (8 bit)\r
+ \details Executes a exclusive STR instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXB (uint32_t)__builtin_arm_strex\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (16 bit)\r
+ \details Executes a exclusive STR instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXH (uint32_t)__builtin_arm_strex\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (32 bit)\r
+ \details Executes a exclusive STR instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXW (uint32_t)__builtin_arm_strex\r
+\r
+\r
+/**\r
+ \brief Remove the exclusive lock\r
+ \details Removes the exclusive lock which is created by LDREX.\r
+ */\r
+#define __CLREX __builtin_arm_clrex\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT __builtin_arm_ssat\r
+\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT __builtin_arm_usat\r
+\r
+\r
+/**\r
+ \brief Rotate Right with Extend (32 bit)\r
+ \details Moves each bit of a bitstring right by one bit.\r
+ The carry input is shifted in at the left end of the bitstring.\r
+ \param [in] value Value to rotate\r
+ \return Rotated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint8_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint16_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged STRT instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged STRT instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged STRT instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );\r
+}\r
+\r
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)\r
+{\r
+ if ((sat >= 1U) && (sat <= 32U))\r
+ {\r
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\r
+ const int32_t min = -1 - max ;\r
+ if (val > max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < min)\r
+ {\r
+ return min;\r
+ }\r
+ }\r
+ return val;\r
+}\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)\r
+{\r
+ if (sat <= 31U)\r
+ {\r
+ const uint32_t max = ((1U << sat) - 1U);\r
+ if (val > (int32_t)max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < 0)\r
+ {\r
+ return 0U;\r
+ }\r
+ }\r
+ return (uint32_t)val;\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+/**\r
+ \brief Load-Acquire (8 bit)\r
+ \details Executes a LDAB instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint8_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire (16 bit)\r
+ \details Executes a LDAH instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint16_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire (32 bit)\r
+ \details Executes a LDA instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (8 bit)\r
+ \details Executes a STLB instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (16 bit)\r
+ \details Executes a STLH instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (32 bit)\r
+ \details Executes a STL instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (8 bit)\r
+ \details Executes a LDAB exclusive instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (16 bit)\r
+ \details Executes a LDAH exclusive instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (32 bit)\r
+ \details Executes a LDA exclusive instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDAEX (uint32_t)__builtin_arm_ldaex\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (8 bit)\r
+ \details Executes a STLB exclusive instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STLEXB (uint32_t)__builtin_arm_stlex\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (16 bit)\r
+ \details Executes a STLH exclusive instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STLEXH (uint32_t)__builtin_arm_stlex\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (32 bit)\r
+ \details Executes a STL exclusive instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STLEX (uint32_t)__builtin_arm_stlex\r
+\r
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\r
+\r
+#define __SADD8 __builtin_arm_sadd8\r
+#define __QADD8 __builtin_arm_qadd8\r
+#define __SHADD8 __builtin_arm_shadd8\r
+#define __UADD8 __builtin_arm_uadd8\r
+#define __UQADD8 __builtin_arm_uqadd8\r
+#define __UHADD8 __builtin_arm_uhadd8\r
+#define __SSUB8 __builtin_arm_ssub8\r
+#define __QSUB8 __builtin_arm_qsub8\r
+#define __SHSUB8 __builtin_arm_shsub8\r
+#define __USUB8 __builtin_arm_usub8\r
+#define __UQSUB8 __builtin_arm_uqsub8\r
+#define __UHSUB8 __builtin_arm_uhsub8\r
+#define __SADD16 __builtin_arm_sadd16\r
+#define __QADD16 __builtin_arm_qadd16\r
+#define __SHADD16 __builtin_arm_shadd16\r
+#define __UADD16 __builtin_arm_uadd16\r
+#define __UQADD16 __builtin_arm_uqadd16\r
+#define __UHADD16 __builtin_arm_uhadd16\r
+#define __SSUB16 __builtin_arm_ssub16\r
+#define __QSUB16 __builtin_arm_qsub16\r
+#define __SHSUB16 __builtin_arm_shsub16\r
+#define __USUB16 __builtin_arm_usub16\r
+#define __UQSUB16 __builtin_arm_uqsub16\r
+#define __UHSUB16 __builtin_arm_uhsub16\r
+#define __SASX __builtin_arm_sasx\r
+#define __QASX __builtin_arm_qasx\r
+#define __SHASX __builtin_arm_shasx\r
+#define __UASX __builtin_arm_uasx\r
+#define __UQASX __builtin_arm_uqasx\r
+#define __UHASX __builtin_arm_uhasx\r
+#define __SSAX __builtin_arm_ssax\r
+#define __QSAX __builtin_arm_qsax\r
+#define __SHSAX __builtin_arm_shsax\r
+#define __USAX __builtin_arm_usax\r
+#define __UQSAX __builtin_arm_uqsax\r
+#define __UHSAX __builtin_arm_uhsax\r
+#define __USAD8 __builtin_arm_usad8\r
+#define __USADA8 __builtin_arm_usada8\r
+#define __SSAT16 __builtin_arm_ssat16\r
+#define __USAT16 __builtin_arm_usat16\r
+#define __UXTB16 __builtin_arm_uxtb16\r
+#define __UXTAB16 __builtin_arm_uxtab16\r
+#define __SXTB16 __builtin_arm_sxtb16\r
+#define __SXTAB16 __builtin_arm_sxtab16\r
+#define __SMUAD __builtin_arm_smuad\r
+#define __SMUADX __builtin_arm_smuadx\r
+#define __SMLAD __builtin_arm_smlad\r
+#define __SMLADX __builtin_arm_smladx\r
+#define __SMLALD __builtin_arm_smlald\r
+#define __SMLALDX __builtin_arm_smlaldx\r
+#define __SMUSD __builtin_arm_smusd\r
+#define __SMUSDX __builtin_arm_smusdx\r
+#define __SMLSD __builtin_arm_smlsd\r
+#define __SMLSDX __builtin_arm_smlsdx\r
+#define __SMLSLD __builtin_arm_smlsld\r
+#define __SMLSLDX __builtin_arm_smlsldx\r
+#define __SEL __builtin_arm_sel\r
+#define __QADD __builtin_arm_qadd\r
+#define __QSUB __builtin_arm_qsub\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \\r
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \\r
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )\r
+\r
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (__ARM_FEATURE_DSP == 1) */\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#endif /* __CMSIS_ARMCLANG_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_armclang_ltm.h\r
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file\r
+ * @version V1.0.1\r
+ * @date 19. March 2019\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2018-2019 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */\r
+\r
+#ifndef __CMSIS_ARMCLANG_H\r
+#define __CMSIS_ARMCLANG_H\r
+\r
+#pragma clang system_header /* treat file as system include file */\r
+\r
+#ifndef __ARM_COMPAT_H\r
+#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */\r
+#endif\r
+\r
+/* CMSIS compiler specific defines */\r
+#ifndef __ASM\r
+ #define __ASM __asm\r
+#endif\r
+#ifndef __INLINE\r
+ #define __INLINE __inline\r
+#endif\r
+#ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static __inline\r
+#endif\r
+#ifndef __STATIC_FORCEINLINE\r
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline\r
+#endif\r
+#ifndef __NO_RETURN\r
+ #define __NO_RETURN __attribute__((__noreturn__))\r
+#endif\r
+#ifndef __USED\r
+ #define __USED __attribute__((used))\r
+#endif\r
+#ifndef __WEAK\r
+ #define __WEAK __attribute__((weak))\r
+#endif\r
+#ifndef __PACKED\r
+ #define __PACKED __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __PACKED_UNION\r
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32 /* deprecated */\r
+ #pragma clang diagnostic push\r
+ #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */\r
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };\r
+ #pragma clang diagnostic pop\r
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_WRITE\r
+ #pragma clang diagnostic push\r
+ #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */\r
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
+ #pragma clang diagnostic pop\r
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_READ\r
+ #pragma clang diagnostic push\r
+ #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */\r
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
+ #pragma clang diagnostic pop\r
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_WRITE\r
+ #pragma clang diagnostic push\r
+ #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */\r
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
+ #pragma clang diagnostic pop\r
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_READ\r
+ #pragma clang diagnostic push\r
+ #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */\r
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
+ #pragma clang diagnostic pop\r
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
+#endif\r
+#ifndef __ALIGNED\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+#endif\r
+#ifndef __RESTRICT\r
+ #define __RESTRICT __restrict\r
+#endif\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Enable IRQ Interrupts\r
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+/* intrinsic void __enable_irq(); see arm_compat.h */\r
+\r
+\r
+/**\r
+ \brief Disable IRQ Interrupts\r
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+/* intrinsic void __disable_irq(); see arm_compat.h */\r
+\r
+\r
+/**\r
+ \brief Get Control Register\r
+ \details Returns the content of the Control Register.\r
+ \return Control Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Control Register (non-secure)\r
+ \details Returns the content of the non-secure Control Register when in secure mode.\r
+ \return non-secure Control Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Control Register\r
+ \details Writes the given value to the Control Register.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Control Register (non-secure)\r
+ \details Writes the given value to the non-secure Control Register when in secure state.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get IPSR Register\r
+ \details Returns the content of the IPSR Register.\r
+ \return IPSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get APSR Register\r
+ \details Returns the content of the APSR Register.\r
+ \return APSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get xPSR Register\r
+ \details Returns the content of the xPSR Register.\r
+ \return xPSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Process Stack Pointer\r
+ \details Returns the current value of the Process Stack Pointer (PSP).\r
+ \return PSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Process Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\r
+ \return PSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer\r
+ \details Assigns the given value to the Process Stack Pointer (PSP).\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Process Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer\r
+ \details Returns the current value of the Main Stack Pointer (MSP).\r
+ \return MSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Main Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\r
+ \return MSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer\r
+ \details Assigns the given value to the Main Stack Pointer (MSP).\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Main Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );\r
+}\r
+#endif\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\r
+ \return SP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\r
+ \param [in] topOfStack Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)\r
+{\r
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Priority Mask\r
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Priority Mask (non-secure)\r
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Priority Mask\r
+ \details Assigns the given value to the Priority Mask Register.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Priority Mask (non-secure)\r
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+/**\r
+ \brief Enable FIQ\r
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */\r
+\r
+\r
+/**\r
+ \brief Disable FIQ\r
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */\r
+\r
+\r
+/**\r
+ \brief Get Base Priority\r
+ \details Returns the current value of the Base Priority register.\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Base Priority (non-secure)\r
+ \details Returns the current value of the non-secure Base Priority register when in secure state.\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Base Priority\r
+ \details Assigns the given value to the Base Priority register.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Base Priority (non-secure)\r
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Base Priority with condition\r
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
+ or the new value increases the BASEPRI priority level.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Fault Mask\r
+ \details Returns the current value of the Fault Mask register.\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Fault Mask (non-secure)\r
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Fault Mask\r
+ \details Assigns the given value to the Fault Mask register.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Fault Mask (non-secure)\r
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");\r
+}\r
+#endif\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+\r
+/**\r
+ \brief Get Process Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always in non-secure\r
+ mode.\r
+ \r
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\r
+ \return PSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ uint32_t result;\r
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+\r
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Process Stack Pointer Limit (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always in non-secure\r
+ mode.\r
+\r
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
+ \return PSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ uint32_t result;\r
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored in non-secure\r
+ mode.\r
+ \r
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\r
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ (void)ProcStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Process Stack Pointer (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored in non-secure\r
+ mode.\r
+\r
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ (void)ProcStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always.\r
+\r
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\r
+ \return MSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ uint32_t result;\r
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Main Stack Pointer Limit (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always.\r
+\r
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\r
+ \return MSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ uint32_t result;\r
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored.\r
+\r
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\r
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ (void)MainStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Main Stack Pointer Limit (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored.\r
+\r
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\r
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ (void)MainStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));\r
+#endif\r
+}\r
+#endif\r
+\r
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+/**\r
+ \brief Get FPSCR\r
+ \details Returns the current value of the Floating Point Status/Control register.\r
+ \return Floating Point Status/Control register value\r
+ */\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr\r
+#else\r
+#define __get_FPSCR() ((uint32_t)0U)\r
+#endif\r
+\r
+/**\r
+ \brief Set FPSCR\r
+ \details Assigns the given value to the Floating Point Status/Control register.\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+#define __set_FPSCR __builtin_arm_set_fpscr\r
+#else\r
+#define __set_FPSCR(x) ((void)(x))\r
+#endif\r
+\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+/* Define macros for porting to both thumb1 and thumb2.\r
+ * For thumb1, use low register (r0-r7), specified by constraint "l"\r
+ * Otherwise, use general registers, specified by constraint "r" */\r
+#if defined (__thumb__) && !defined (__thumb2__)\r
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
+#else\r
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
+#endif\r
+\r
+/**\r
+ \brief No Operation\r
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP __builtin_arm_nop\r
+\r
+/**\r
+ \brief Wait For Interrupt\r
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
+ */\r
+#define __WFI __builtin_arm_wfi\r
+\r
+\r
+/**\r
+ \brief Wait For Event\r
+ \details Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE __builtin_arm_wfe\r
+\r
+\r
+/**\r
+ \brief Send Event\r
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV __builtin_arm_sev\r
+\r
+\r
+/**\r
+ \brief Instruction Synchronization Barrier\r
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or memory,\r
+ after the instruction has been completed.\r
+ */\r
+#define __ISB() __builtin_arm_isb(0xF)\r
+\r
+/**\r
+ \brief Data Synchronization Barrier\r
+ \details Acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+#define __DSB() __builtin_arm_dsb(0xF)\r
+\r
+\r
+/**\r
+ \brief Data Memory Barrier\r
+ \details Ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+#define __DMB() __builtin_arm_dmb(0xF)\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (32 bit)\r
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV(value) __builtin_bswap32(value)\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV16(value) __ROR(__REV(value), 16)\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)\r
+\r
+\r
+/**\r
+ \brief Rotate Right in unsigned value (32 bit)\r
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+ \param [in] op1 Value to rotate\r
+ \param [in] op2 Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+{\r
+ op2 %= 32U;\r
+ if (op2 == 0U)\r
+ {\r
+ return op1;\r
+ }\r
+ return (op1 >> op2) | (op1 << (32U - op2));\r
+}\r
+\r
+\r
+/**\r
+ \brief Breakpoint\r
+ \details Causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
+\r
+\r
+/**\r
+ \brief Reverse bit order of value\r
+ \details Reverses the bit order of the given value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __RBIT __builtin_arm_rbit\r
+\r
+/**\r
+ \brief Count leading zeros\r
+ \details Counts the number of leading zeros of a data value.\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)\r
+{\r
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally\r
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.\r
+ This guarantees ARM-compatible results if happening to compile on a non-ARM\r
+ target, and ensures the compiler doesn't decide to activate any\r
+ optimisations using the logic "value was passed to __builtin_clz, so it\r
+ is non-zero".\r
+ ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a\r
+ single CLZ instruction.\r
+ */\r
+ if (value == 0U)\r
+ {\r
+ return 32U;\r
+ }\r
+ return __builtin_clz(value);\r
+}\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+/**\r
+ \brief LDR Exclusive (8 bit)\r
+ \details Executes a exclusive LDR instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDREXB (uint8_t)__builtin_arm_ldrex\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (16 bit)\r
+ \details Executes a exclusive LDR instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDREXH (uint16_t)__builtin_arm_ldrex\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (32 bit)\r
+ \details Executes a exclusive LDR instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDREXW (uint32_t)__builtin_arm_ldrex\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (8 bit)\r
+ \details Executes a exclusive STR instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXB (uint32_t)__builtin_arm_strex\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (16 bit)\r
+ \details Executes a exclusive STR instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXH (uint32_t)__builtin_arm_strex\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (32 bit)\r
+ \details Executes a exclusive STR instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXW (uint32_t)__builtin_arm_strex\r
+\r
+\r
+/**\r
+ \brief Remove the exclusive lock\r
+ \details Removes the exclusive lock which is created by LDREX.\r
+ */\r
+#define __CLREX __builtin_arm_clrex\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT __builtin_arm_ssat\r
+\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT __builtin_arm_usat\r
+\r
+\r
+/**\r
+ \brief Rotate Right with Extend (32 bit)\r
+ \details Moves each bit of a bitstring right by one bit.\r
+ The carry input is shifted in at the left end of the bitstring.\r
+ \param [in] value Value to rotate\r
+ \return Rotated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint8_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint16_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged STRT instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged STRT instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged STRT instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );\r
+}\r
+\r
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)\r
+{\r
+ if ((sat >= 1U) && (sat <= 32U))\r
+ {\r
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\r
+ const int32_t min = -1 - max ;\r
+ if (val > max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < min)\r
+ {\r
+ return min;\r
+ }\r
+ }\r
+ return val;\r
+}\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)\r
+{\r
+ if (sat <= 31U)\r
+ {\r
+ const uint32_t max = ((1U << sat) - 1U);\r
+ if (val > (int32_t)max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < 0)\r
+ {\r
+ return 0U;\r
+ }\r
+ }\r
+ return (uint32_t)val;\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+/**\r
+ \brief Load-Acquire (8 bit)\r
+ \details Executes a LDAB instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint8_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire (16 bit)\r
+ \details Executes a LDAH instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint16_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire (32 bit)\r
+ \details Executes a LDA instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (8 bit)\r
+ \details Executes a STLB instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (16 bit)\r
+ \details Executes a STLH instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (32 bit)\r
+ \details Executes a STL instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (8 bit)\r
+ \details Executes a LDAB exclusive instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (16 bit)\r
+ \details Executes a LDAH exclusive instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (32 bit)\r
+ \details Executes a LDA exclusive instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDAEX (uint32_t)__builtin_arm_ldaex\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (8 bit)\r
+ \details Executes a STLB exclusive instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STLEXB (uint32_t)__builtin_arm_stlex\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (16 bit)\r
+ \details Executes a STLH exclusive instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STLEXH (uint32_t)__builtin_arm_stlex\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (32 bit)\r
+ \details Executes a STL exclusive instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STLEX (uint32_t)__builtin_arm_stlex\r
+\r
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\r
+\r
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#define __SSAT16(ARG1,ARG2) \\r
+({ \\r
+ int32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __USAT16(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \\r
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \\r
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )\r
+\r
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (__ARM_FEATURE_DSP == 1) */\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#endif /* __CMSIS_ARMCLANG_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_compiler.h\r
+ * @brief CMSIS compiler generic header file\r
+ * @version V5.1.0\r
+ * @date 09. October 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#ifndef __CMSIS_COMPILER_H\r
+#define __CMSIS_COMPILER_H\r
+\r
+#include <stdint.h>\r
+\r
+/*\r
+ * Arm Compiler 4/5\r
+ */\r
+#if defined ( __CC_ARM )\r
+ #include "cmsis_armcc.h"\r
+\r
+\r
+/*\r
+ * Arm Compiler 6.6 LTM (armclang)\r
+ */\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)\r
+ #include "cmsis_armclang_ltm.h"\r
+\r
+ /*\r
+ * Arm Compiler above 6.10.1 (armclang)\r
+ */\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)\r
+ #include "cmsis_armclang.h"\r
+\r
+\r
+/*\r
+ * GNU Compiler\r
+ */\r
+#elif defined ( __GNUC__ )\r
+ #include "cmsis_gcc.h"\r
+\r
+\r
+/*\r
+ * IAR Compiler\r
+ */\r
+#elif defined ( __ICCARM__ )\r
+ #include <cmsis_iccarm.h>\r
+\r
+\r
+/*\r
+ * TI Arm Compiler\r
+ */\r
+#elif defined ( __TI_ARM__ )\r
+ #include <cmsis_ccs.h>\r
+\r
+ #ifndef __ASM\r
+ #define __ASM __asm\r
+ #endif\r
+ #ifndef __INLINE\r
+ #define __INLINE inline\r
+ #endif\r
+ #ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static inline\r
+ #endif\r
+ #ifndef __STATIC_FORCEINLINE\r
+ #define __STATIC_FORCEINLINE __STATIC_INLINE\r
+ #endif\r
+ #ifndef __NO_RETURN\r
+ #define __NO_RETURN __attribute__((noreturn))\r
+ #endif\r
+ #ifndef __USED\r
+ #define __USED __attribute__((used))\r
+ #endif\r
+ #ifndef __WEAK\r
+ #define __WEAK __attribute__((weak))\r
+ #endif\r
+ #ifndef __PACKED\r
+ #define __PACKED __attribute__((packed))\r
+ #endif\r
+ #ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT struct __attribute__((packed))\r
+ #endif\r
+ #ifndef __PACKED_UNION\r
+ #define __PACKED_UNION union __attribute__((packed))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32 /* deprecated */\r
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };\r
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT16_WRITE\r
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT16_READ\r
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32_WRITE\r
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32_READ\r
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
+ #endif\r
+ #ifndef __ALIGNED\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+ #endif\r
+ #ifndef __RESTRICT\r
+ #define __RESTRICT __restrict\r
+ #endif\r
+\r
+\r
+/*\r
+ * TASKING Compiler\r
+ */\r
+#elif defined ( __TASKING__ )\r
+ /*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+ #ifndef __ASM\r
+ #define __ASM __asm\r
+ #endif\r
+ #ifndef __INLINE\r
+ #define __INLINE inline\r
+ #endif\r
+ #ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static inline\r
+ #endif\r
+ #ifndef __STATIC_FORCEINLINE\r
+ #define __STATIC_FORCEINLINE __STATIC_INLINE\r
+ #endif\r
+ #ifndef __NO_RETURN\r
+ #define __NO_RETURN __attribute__((noreturn))\r
+ #endif\r
+ #ifndef __USED\r
+ #define __USED __attribute__((used))\r
+ #endif\r
+ #ifndef __WEAK\r
+ #define __WEAK __attribute__((weak))\r
+ #endif\r
+ #ifndef __PACKED\r
+ #define __PACKED __packed__\r
+ #endif\r
+ #ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT struct __packed__\r
+ #endif\r
+ #ifndef __PACKED_UNION\r
+ #define __PACKED_UNION union __packed__\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32 /* deprecated */\r
+ struct __packed__ T_UINT32 { uint32_t v; };\r
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT16_WRITE\r
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT16_READ\r
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32_WRITE\r
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32_READ\r
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
+ #endif\r
+ #ifndef __ALIGNED\r
+ #define __ALIGNED(x) __align(x)\r
+ #endif\r
+ #ifndef __RESTRICT\r
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\r
+ #define __RESTRICT\r
+ #endif\r
+\r
+\r
+/*\r
+ * COSMIC Compiler\r
+ */\r
+#elif defined ( __CSMC__ )\r
+ #include <cmsis_csm.h>\r
+\r
+ #ifndef __ASM\r
+ #define __ASM _asm\r
+ #endif\r
+ #ifndef __INLINE\r
+ #define __INLINE inline\r
+ #endif\r
+ #ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static inline\r
+ #endif\r
+ #ifndef __STATIC_FORCEINLINE\r
+ #define __STATIC_FORCEINLINE __STATIC_INLINE\r
+ #endif\r
+ #ifndef __NO_RETURN\r
+ // NO RETURN is automatically detected hence no warning here\r
+ #define __NO_RETURN\r
+ #endif\r
+ #ifndef __USED\r
+ #warning No compiler specific solution for __USED. __USED is ignored.\r
+ #define __USED\r
+ #endif\r
+ #ifndef __WEAK\r
+ #define __WEAK __weak\r
+ #endif\r
+ #ifndef __PACKED\r
+ #define __PACKED @packed\r
+ #endif\r
+ #ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT @packed struct\r
+ #endif\r
+ #ifndef __PACKED_UNION\r
+ #define __PACKED_UNION @packed union\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32 /* deprecated */\r
+ @packed struct T_UINT32 { uint32_t v; };\r
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT16_WRITE\r
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT16_READ\r
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32_WRITE\r
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32_READ\r
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
+ #endif\r
+ #ifndef __ALIGNED\r
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.\r
+ #define __ALIGNED(x)\r
+ #endif\r
+ #ifndef __RESTRICT\r
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\r
+ #define __RESTRICT\r
+ #endif\r
+\r
+\r
+#else\r
+ #error Unknown compiler.\r
+#endif\r
+\r
+\r
+#endif /* __CMSIS_COMPILER_H */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_gcc.h\r
+ * @brief CMSIS compiler GCC header file\r
+ * @version V5.1.0\r
+ * @date 20. December 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#ifndef __CMSIS_GCC_H\r
+#define __CMSIS_GCC_H\r
+\r
+/* ignore some GCC warnings */\r
+#pragma GCC diagnostic push\r
+#pragma GCC diagnostic ignored "-Wsign-conversion"\r
+#pragma GCC diagnostic ignored "-Wconversion"\r
+#pragma GCC diagnostic ignored "-Wunused-parameter"\r
+\r
+/* Fallback for __has_builtin */\r
+#ifndef __has_builtin\r
+ #define __has_builtin(x) (0)\r
+#endif\r
+\r
+/* CMSIS compiler specific defines */\r
+#ifndef __ASM\r
+ #define __ASM __asm\r
+#endif\r
+#ifndef __INLINE\r
+ #define __INLINE inline\r
+#endif\r
+#ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static inline\r
+#endif\r
+#ifndef __STATIC_FORCEINLINE \r
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline\r
+#endif \r
+#ifndef __NO_RETURN\r
+ #define __NO_RETURN __attribute__((__noreturn__))\r
+#endif\r
+#ifndef __USED\r
+ #define __USED __attribute__((used))\r
+#endif\r
+#ifndef __WEAK\r
+ #define __WEAK __attribute__((weak))\r
+#endif\r
+#ifndef __PACKED\r
+ #define __PACKED __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __PACKED_UNION\r
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32 /* deprecated */\r
+ #pragma GCC diagnostic push\r
+ #pragma GCC diagnostic ignored "-Wpacked"\r
+ #pragma GCC diagnostic ignored "-Wattributes"\r
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };\r
+ #pragma GCC diagnostic pop\r
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_WRITE\r
+ #pragma GCC diagnostic push\r
+ #pragma GCC diagnostic ignored "-Wpacked"\r
+ #pragma GCC diagnostic ignored "-Wattributes"\r
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
+ #pragma GCC diagnostic pop\r
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_READ\r
+ #pragma GCC diagnostic push\r
+ #pragma GCC diagnostic ignored "-Wpacked"\r
+ #pragma GCC diagnostic ignored "-Wattributes"\r
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
+ #pragma GCC diagnostic pop\r
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_WRITE\r
+ #pragma GCC diagnostic push\r
+ #pragma GCC diagnostic ignored "-Wpacked"\r
+ #pragma GCC diagnostic ignored "-Wattributes"\r
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
+ #pragma GCC diagnostic pop\r
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_READ\r
+ #pragma GCC diagnostic push\r
+ #pragma GCC diagnostic ignored "-Wpacked"\r
+ #pragma GCC diagnostic ignored "-Wattributes"\r
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
+ #pragma GCC diagnostic pop\r
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
+#endif\r
+#ifndef __ALIGNED\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+#endif\r
+#ifndef __RESTRICT\r
+ #define __RESTRICT __restrict\r
+#endif\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Enable IRQ Interrupts\r
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__STATIC_FORCEINLINE void __enable_irq(void)\r
+{\r
+ __ASM volatile ("cpsie i" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable IRQ Interrupts\r
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__STATIC_FORCEINLINE void __disable_irq(void)\r
+{\r
+ __ASM volatile ("cpsid i" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Control Register\r
+ \details Returns the content of the Control Register.\r
+ \return Control Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Control Register (non-secure)\r
+ \details Returns the content of the non-secure Control Register when in secure mode.\r
+ \return non-secure Control Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Control Register\r
+ \details Writes the given value to the Control Register.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Control Register (non-secure)\r
+ \details Writes the given value to the non-secure Control Register when in secure state.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get IPSR Register\r
+ \details Returns the content of the IPSR Register.\r
+ \return IPSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get APSR Register\r
+ \details Returns the content of the APSR Register.\r
+ \return APSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get xPSR Register\r
+ \details Returns the content of the xPSR Register.\r
+ \return xPSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Process Stack Pointer\r
+ \details Returns the current value of the Process Stack Pointer (PSP).\r
+ \return PSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Process Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\r
+ \return PSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer\r
+ \details Assigns the given value to the Process Stack Pointer (PSP).\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Process Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer\r
+ \details Returns the current value of the Main Stack Pointer (MSP).\r
+ \return MSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Main Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\r
+ \return MSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer\r
+ \details Assigns the given value to the Main Stack Pointer (MSP).\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Main Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );\r
+}\r
+#endif\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\r
+ \return SP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\r
+ \param [in] topOfStack Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)\r
+{\r
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Priority Mask\r
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Priority Mask (non-secure)\r
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Priority Mask\r
+ \details Assigns the given value to the Priority Mask Register.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Priority Mask (non-secure)\r
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+/**\r
+ \brief Enable FIQ\r
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__STATIC_FORCEINLINE void __enable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsie f" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable FIQ\r
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__STATIC_FORCEINLINE void __disable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsid f" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Base Priority\r
+ \details Returns the current value of the Base Priority register.\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Base Priority (non-secure)\r
+ \details Returns the current value of the non-secure Base Priority register when in secure state.\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Base Priority\r
+ \details Assigns the given value to the Base Priority register.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Base Priority (non-secure)\r
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Base Priority with condition\r
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
+ or the new value increases the BASEPRI priority level.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Fault Mask\r
+ \details Returns the current value of the Fault Mask register.\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Fault Mask (non-secure)\r
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Fault Mask\r
+ \details Assigns the given value to the Fault Mask register.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Fault Mask (non-secure)\r
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");\r
+}\r
+#endif\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+\r
+/**\r
+ \brief Get Process Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always in non-secure\r
+ mode.\r
+ \r
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\r
+ \return PSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ uint32_t result;\r
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+\r
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Process Stack Pointer Limit (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always.\r
+\r
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
+ \return PSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ uint32_t result;\r
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored in non-secure\r
+ mode.\r
+ \r
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\r
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ (void)ProcStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Process Stack Pointer (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored.\r
+\r
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ (void)ProcStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always in non-secure\r
+ mode.\r
+\r
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\r
+ \return MSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ uint32_t result;\r
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Main Stack Pointer Limit (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always.\r
+\r
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\r
+ \return MSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ uint32_t result;\r
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored in non-secure\r
+ mode.\r
+\r
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\r
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ (void)MainStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Main Stack Pointer Limit (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored.\r
+\r
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\r
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ (void)MainStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));\r
+#endif\r
+}\r
+#endif\r
+\r
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+\r
+/**\r
+ \brief Get FPSCR\r
+ \details Returns the current value of the Floating Point Status/Control register.\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+#if __has_builtin(__builtin_arm_get_fpscr) \r
+// Re-enable using built-in when GCC has been fixed\r
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\r
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\r
+ return __builtin_arm_get_fpscr();\r
+#else\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
+ return(result);\r
+#endif\r
+#else\r
+ return(0U);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Set FPSCR\r
+ \details Assigns the given value to the Floating Point Status/Control register.\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+#if __has_builtin(__builtin_arm_set_fpscr)\r
+// Re-enable using built-in when GCC has been fixed\r
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\r
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\r
+ __builtin_arm_set_fpscr(fpscr);\r
+#else\r
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");\r
+#endif\r
+#else\r
+ (void)fpscr;\r
+#endif\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+/* Define macros for porting to both thumb1 and thumb2.\r
+ * For thumb1, use low register (r0-r7), specified by constraint "l"\r
+ * Otherwise, use general registers, specified by constraint "r" */\r
+#if defined (__thumb__) && !defined (__thumb2__)\r
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
+#else\r
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
+#endif\r
+\r
+/**\r
+ \brief No Operation\r
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP() __ASM volatile ("nop")\r
+\r
+/**\r
+ \brief Wait For Interrupt\r
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
+ */\r
+#define __WFI() __ASM volatile ("wfi")\r
+\r
+\r
+/**\r
+ \brief Wait For Event\r
+ \details Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE() __ASM volatile ("wfe")\r
+\r
+\r
+/**\r
+ \brief Send Event\r
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV() __ASM volatile ("sev")\r
+\r
+\r
+/**\r
+ \brief Instruction Synchronization Barrier\r
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or memory,\r
+ after the instruction has been completed.\r
+ */\r
+__STATIC_FORCEINLINE void __ISB(void)\r
+{\r
+ __ASM volatile ("isb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Data Synchronization Barrier\r
+ \details Acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+__STATIC_FORCEINLINE void __DSB(void)\r
+{\r
+ __ASM volatile ("dsb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Data Memory Barrier\r
+ \details Ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+__STATIC_FORCEINLINE void __DMB(void)\r
+{\r
+ __ASM volatile ("dmb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (32 bit)\r
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r
+ return __builtin_bswap32(value);\r
+#else\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return result;\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return result;\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ return (int16_t)__builtin_bswap16(value);\r
+#else\r
+ int16_t result;\r
+\r
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return result;\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Rotate Right in unsigned value (32 bit)\r
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+ \param [in] op1 Value to rotate\r
+ \param [in] op2 Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+{\r
+ op2 %= 32U;\r
+ if (op2 == 0U)\r
+ {\r
+ return op1;\r
+ }\r
+ return (op1 >> op2) | (op1 << (32U - op2));\r
+}\r
+\r
+\r
+/**\r
+ \brief Breakpoint\r
+ \details Causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
+\r
+\r
+/**\r
+ \brief Reverse bit order of value\r
+ \details Reverses the bit order of the given value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+#else\r
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */\r
+\r
+ result = value; /* r will be reversed bits of v; first get LSB of v */\r
+ for (value >>= 1U; value != 0U; value >>= 1U)\r
+ {\r
+ result <<= 1U;\r
+ result |= value & 1U;\r
+ s--;\r
+ }\r
+ result <<= s; /* shift when v's highest bits are zero */\r
+#endif\r
+ return result;\r
+}\r
+\r
+\r
+/**\r
+ \brief Count leading zeros\r
+ \details Counts the number of leading zeros of a data value.\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)\r
+{\r
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally\r
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.\r
+ This guarantees ARM-compatible results if happening to compile on a non-ARM\r
+ target, and ensures the compiler doesn't decide to activate any\r
+ optimisations using the logic "value was passed to __builtin_clz, so it\r
+ is non-zero".\r
+ ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a\r
+ single CLZ instruction.\r
+ */\r
+ if (value == 0U)\r
+ {\r
+ return 32U;\r
+ }\r
+ return __builtin_clz(value);\r
+}\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+/**\r
+ \brief LDR Exclusive (8 bit)\r
+ \details Executes a exclusive LDR instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint8_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (16 bit)\r
+ \details Executes a exclusive LDR instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint16_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (32 bit)\r
+ \details Executes a exclusive LDR instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (8 bit)\r
+ \details Executes a exclusive STR instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (16 bit)\r
+ \details Executes a exclusive STR instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (32 bit)\r
+ \details Executes a exclusive STR instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Remove the exclusive lock\r
+ \details Removes the exclusive lock which is created by LDREX.\r
+ */\r
+__STATIC_FORCEINLINE void __CLREX(void)\r
+{\r
+ __ASM volatile ("clrex" ::: "memory");\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] ARG1 Value to be saturated\r
+ \param [in] ARG2 Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT(ARG1,ARG2) \\r
+__extension__ \\r
+({ \\r
+ int32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] ARG1 Value to be saturated\r
+ \param [in] ARG2 Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT(ARG1,ARG2) \\r
+ __extension__ \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/**\r
+ \brief Rotate Right with Extend (32 bit)\r
+ \details Moves each bit of a bitstring right by one bit.\r
+ The carry input is shifted in at the left end of the bitstring.\r
+ \param [in] value Value to rotate\r
+ \return Rotated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );\r
+#endif\r
+ return ((uint8_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );\r
+#endif\r
+ return ((uint16_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged STRT instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged STRT instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged STRT instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );\r
+}\r
+\r
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)\r
+{\r
+ if ((sat >= 1U) && (sat <= 32U))\r
+ {\r
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\r
+ const int32_t min = -1 - max ;\r
+ if (val > max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < min)\r
+ {\r
+ return min;\r
+ }\r
+ }\r
+ return val;\r
+}\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)\r
+{\r
+ if (sat <= 31U)\r
+ {\r
+ const uint32_t max = ((1U << sat) - 1U);\r
+ if (val > (int32_t)max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < 0)\r
+ {\r
+ return 0U;\r
+ }\r
+ }\r
+ return (uint32_t)val;\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+/**\r
+ \brief Load-Acquire (8 bit)\r
+ \details Executes a LDAB instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint8_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire (16 bit)\r
+ \details Executes a LDAH instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint16_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire (32 bit)\r
+ \details Executes a LDA instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (8 bit)\r
+ \details Executes a STLB instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (16 bit)\r
+ \details Executes a STLH instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (32 bit)\r
+ \details Executes a STL instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (8 bit)\r
+ \details Executes a LDAB exclusive instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint8_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (16 bit)\r
+ \details Executes a LDAH exclusive instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint16_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (32 bit)\r
+ \details Executes a LDA exclusive instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (8 bit)\r
+ \details Executes a STLB exclusive instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (16 bit)\r
+ \details Executes a STLH exclusive instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (32 bit)\r
+ \details Executes a STL exclusive instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\r
+\r
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#define __SSAT16(ARG1,ARG2) \\r
+({ \\r
+ int32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __USAT16(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+#if 0\r
+#define __PKHBT(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ if (ARG3 == 0) \\r
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \\r
+ else \\r
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+#endif\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \\r
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \\r
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )\r
+\r
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (__ARM_FEATURE_DSP == 1) */\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#pragma GCC diagnostic pop\r
+\r
+#endif /* __CMSIS_GCC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_iccarm.h\r
+ * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file\r
+ * @version V5.0.8\r
+ * @date 04. September 2018\r
+ ******************************************************************************/\r
+\r
+//------------------------------------------------------------------------------\r
+//\r
+// Copyright (c) 2017-2018 IAR Systems\r
+//\r
+// Licensed under the Apache License, Version 2.0 (the "License")\r
+// you may not use this file except in compliance with the License.\r
+// You may obtain a copy of the License at\r
+// http://www.apache.org/licenses/LICENSE-2.0\r
+//\r
+// Unless required by applicable law or agreed to in writing, software\r
+// distributed under the License is distributed on an "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+// See the License for the specific language governing permissions and\r
+// limitations under the License.\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+\r
+#ifndef __CMSIS_ICCARM_H__\r
+#define __CMSIS_ICCARM_H__\r
+\r
+#ifndef __ICCARM__\r
+ #error This file should only be compiled by ICCARM\r
+#endif\r
+\r
+#pragma system_include\r
+\r
+#define __IAR_FT _Pragma("inline=forced") __intrinsic\r
+\r
+#if (__VER__ >= 8000000)\r
+ #define __ICCARM_V8 1\r
+#else\r
+ #define __ICCARM_V8 0\r
+#endif\r
+\r
+#ifndef __ALIGNED\r
+ #if __ICCARM_V8\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+ #elif (__VER__ >= 7080000)\r
+ /* Needs IAR language extensions */\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+ #else\r
+ #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.\r
+ #define __ALIGNED(x)\r
+ #endif\r
+#endif\r
+\r
+\r
+/* Define compiler macros for CPU architecture, used in CMSIS 5.\r
+ */\r
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__\r
+/* Macros already defined */\r
+#else\r
+ #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)\r
+ #define __ARM_ARCH_8M_MAIN__ 1\r
+ #elif defined(__ARM8M_BASELINE__)\r
+ #define __ARM_ARCH_8M_BASE__ 1\r
+ #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'\r
+ #if __ARM_ARCH == 6\r
+ #define __ARM_ARCH_6M__ 1\r
+ #elif __ARM_ARCH == 7\r
+ #if __ARM_FEATURE_DSP\r
+ #define __ARM_ARCH_7EM__ 1\r
+ #else\r
+ #define __ARM_ARCH_7M__ 1\r
+ #endif\r
+ #endif /* __ARM_ARCH */\r
+ #endif /* __ARM_ARCH_PROFILE == 'M' */\r
+#endif\r
+\r
+/* Alternativ core deduction for older ICCARM's */\r
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \\r
+ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)\r
+ #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)\r
+ #define __ARM_ARCH_6M__ 1\r
+ #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)\r
+ #define __ARM_ARCH_7M__ 1\r
+ #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)\r
+ #define __ARM_ARCH_7EM__ 1\r
+ #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)\r
+ #define __ARM_ARCH_8M_BASE__ 1\r
+ #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)\r
+ #define __ARM_ARCH_8M_MAIN__ 1\r
+ #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)\r
+ #define __ARM_ARCH_8M_MAIN__ 1\r
+ #else\r
+ #error "Unknown target."\r
+ #endif\r
+#endif\r
+\r
+\r
+\r
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1\r
+ #define __IAR_M0_FAMILY 1\r
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1\r
+ #define __IAR_M0_FAMILY 1\r
+#else\r
+ #define __IAR_M0_FAMILY 0\r
+#endif\r
+\r
+\r
+#ifndef __ASM\r
+ #define __ASM __asm\r
+#endif\r
+\r
+#ifndef __INLINE\r
+ #define __INLINE inline\r
+#endif\r
+\r
+#ifndef __NO_RETURN\r
+ #if __ICCARM_V8\r
+ #define __NO_RETURN __attribute__((__noreturn__))\r
+ #else\r
+ #define __NO_RETURN _Pragma("object_attribute=__noreturn")\r
+ #endif\r
+#endif\r
+\r
+#ifndef __PACKED\r
+ #if __ICCARM_V8\r
+ #define __PACKED __attribute__((packed, aligned(1)))\r
+ #else\r
+ /* Needs IAR language extensions */\r
+ #define __PACKED __packed\r
+ #endif\r
+#endif\r
+\r
+#ifndef __PACKED_STRUCT\r
+ #if __ICCARM_V8\r
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))\r
+ #else\r
+ /* Needs IAR language extensions */\r
+ #define __PACKED_STRUCT __packed struct\r
+ #endif\r
+#endif\r
+\r
+#ifndef __PACKED_UNION\r
+ #if __ICCARM_V8\r
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))\r
+ #else\r
+ /* Needs IAR language extensions */\r
+ #define __PACKED_UNION __packed union\r
+ #endif\r
+#endif\r
+\r
+#ifndef __RESTRICT\r
+ #if __ICCARM_V8\r
+ #define __RESTRICT __restrict\r
+ #else\r
+ /* Needs IAR language extensions */\r
+ #define __RESTRICT restrict\r
+ #endif\r
+#endif\r
+\r
+#ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static inline\r
+#endif\r
+\r
+#ifndef __FORCEINLINE\r
+ #define __FORCEINLINE _Pragma("inline=forced")\r
+#endif\r
+\r
+#ifndef __STATIC_FORCEINLINE\r
+ #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE\r
+#endif\r
+\r
+#ifndef __UNALIGNED_UINT16_READ\r
+#pragma language=save\r
+#pragma language=extended\r
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)\r
+{\r
+ return *(__packed uint16_t*)(ptr);\r
+}\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)\r
+#endif\r
+\r
+\r
+#ifndef __UNALIGNED_UINT16_WRITE\r
+#pragma language=save\r
+#pragma language=extended\r
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)\r
+{\r
+ *(__packed uint16_t*)(ptr) = val;;\r
+}\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)\r
+#endif\r
+\r
+#ifndef __UNALIGNED_UINT32_READ\r
+#pragma language=save\r
+#pragma language=extended\r
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)\r
+{\r
+ return *(__packed uint32_t*)(ptr);\r
+}\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)\r
+#endif\r
+\r
+#ifndef __UNALIGNED_UINT32_WRITE\r
+#pragma language=save\r
+#pragma language=extended\r
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)\r
+{\r
+ *(__packed uint32_t*)(ptr) = val;;\r
+}\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)\r
+#endif\r
+\r
+#ifndef __UNALIGNED_UINT32 /* deprecated */\r
+#pragma language=save\r
+#pragma language=extended\r
+__packed struct __iar_u32 { uint32_t v; };\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)\r
+#endif\r
+\r
+#ifndef __USED\r
+ #if __ICCARM_V8\r
+ #define __USED __attribute__((used))\r
+ #else\r
+ #define __USED _Pragma("__root")\r
+ #endif\r
+#endif\r
+\r
+#ifndef __WEAK\r
+ #if __ICCARM_V8\r
+ #define __WEAK __attribute__((weak))\r
+ #else\r
+ #define __WEAK _Pragma("__weak")\r
+ #endif\r
+#endif\r
+\r
+\r
+#ifndef __ICCARM_INTRINSICS_VERSION__\r
+ #define __ICCARM_INTRINSICS_VERSION__ 0\r
+#endif\r
+\r
+#if __ICCARM_INTRINSICS_VERSION__ == 2\r
+\r
+ #if defined(__CLZ)\r
+ #undef __CLZ\r
+ #endif\r
+ #if defined(__REVSH)\r
+ #undef __REVSH\r
+ #endif\r
+ #if defined(__RBIT)\r
+ #undef __RBIT\r
+ #endif\r
+ #if defined(__SSAT)\r
+ #undef __SSAT\r
+ #endif\r
+ #if defined(__USAT)\r
+ #undef __USAT\r
+ #endif\r
+\r
+ #include "iccarm_builtin.h"\r
+\r
+ #define __disable_fault_irq __iar_builtin_disable_fiq\r
+ #define __disable_irq __iar_builtin_disable_interrupt\r
+ #define __enable_fault_irq __iar_builtin_enable_fiq\r
+ #define __enable_irq __iar_builtin_enable_interrupt\r
+ #define __arm_rsr __iar_builtin_rsr\r
+ #define __arm_wsr __iar_builtin_wsr\r
+\r
+\r
+ #define __get_APSR() (__arm_rsr("APSR"))\r
+ #define __get_BASEPRI() (__arm_rsr("BASEPRI"))\r
+ #define __get_CONTROL() (__arm_rsr("CONTROL"))\r
+ #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))\r
+\r
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+ #define __get_FPSCR() (__arm_rsr("FPSCR"))\r
+ #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))\r
+ #else\r
+ #define __get_FPSCR() ( 0 )\r
+ #define __set_FPSCR(VALUE) ((void)VALUE)\r
+ #endif\r
+\r
+ #define __get_IPSR() (__arm_rsr("IPSR"))\r
+ #define __get_MSP() (__arm_rsr("MSP"))\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ #define __get_MSPLIM() (0U)\r
+ #else\r
+ #define __get_MSPLIM() (__arm_rsr("MSPLIM"))\r
+ #endif\r
+ #define __get_PRIMASK() (__arm_rsr("PRIMASK"))\r
+ #define __get_PSP() (__arm_rsr("PSP"))\r
+\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ #define __get_PSPLIM() (0U)\r
+ #else\r
+ #define __get_PSPLIM() (__arm_rsr("PSPLIM"))\r
+ #endif\r
+\r
+ #define __get_xPSR() (__arm_rsr("xPSR"))\r
+\r
+ #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))\r
+ #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))\r
+ #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))\r
+ #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))\r
+ #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))\r
+\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ #define __set_MSPLIM(VALUE) ((void)(VALUE))\r
+ #else\r
+ #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))\r
+ #endif\r
+ #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))\r
+ #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ #define __set_PSPLIM(VALUE) ((void)(VALUE))\r
+ #else\r
+ #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))\r
+ #endif\r
+\r
+ #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))\r
+ #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))\r
+ #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))\r
+ #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))\r
+ #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))\r
+ #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))\r
+ #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))\r
+ #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))\r
+ #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))\r
+ #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))\r
+ #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))\r
+ #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))\r
+ #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))\r
+ #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))\r
+\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ #define __TZ_get_PSPLIM_NS() (0U)\r
+ #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))\r
+ #else\r
+ #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))\r
+ #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))\r
+ #endif\r
+\r
+ #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))\r
+ #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))\r
+\r
+ #define __NOP __iar_builtin_no_operation\r
+\r
+ #define __CLZ __iar_builtin_CLZ\r
+ #define __CLREX __iar_builtin_CLREX\r
+\r
+ #define __DMB __iar_builtin_DMB\r
+ #define __DSB __iar_builtin_DSB\r
+ #define __ISB __iar_builtin_ISB\r
+\r
+ #define __LDREXB __iar_builtin_LDREXB\r
+ #define __LDREXH __iar_builtin_LDREXH\r
+ #define __LDREXW __iar_builtin_LDREX\r
+\r
+ #define __RBIT __iar_builtin_RBIT\r
+ #define __REV __iar_builtin_REV\r
+ #define __REV16 __iar_builtin_REV16\r
+\r
+ __IAR_FT int16_t __REVSH(int16_t val)\r
+ {\r
+ return (int16_t) __iar_builtin_REVSH(val);\r
+ }\r
+\r
+ #define __ROR __iar_builtin_ROR\r
+ #define __RRX __iar_builtin_RRX\r
+\r
+ #define __SEV __iar_builtin_SEV\r
+\r
+ #if !__IAR_M0_FAMILY\r
+ #define __SSAT __iar_builtin_SSAT\r
+ #endif\r
+\r
+ #define __STREXB __iar_builtin_STREXB\r
+ #define __STREXH __iar_builtin_STREXH\r
+ #define __STREXW __iar_builtin_STREX\r
+\r
+ #if !__IAR_M0_FAMILY\r
+ #define __USAT __iar_builtin_USAT\r
+ #endif\r
+\r
+ #define __WFE __iar_builtin_WFE\r
+ #define __WFI __iar_builtin_WFI\r
+\r
+ #if __ARM_MEDIA__\r
+ #define __SADD8 __iar_builtin_SADD8\r
+ #define __QADD8 __iar_builtin_QADD8\r
+ #define __SHADD8 __iar_builtin_SHADD8\r
+ #define __UADD8 __iar_builtin_UADD8\r
+ #define __UQADD8 __iar_builtin_UQADD8\r
+ #define __UHADD8 __iar_builtin_UHADD8\r
+ #define __SSUB8 __iar_builtin_SSUB8\r
+ #define __QSUB8 __iar_builtin_QSUB8\r
+ #define __SHSUB8 __iar_builtin_SHSUB8\r
+ #define __USUB8 __iar_builtin_USUB8\r
+ #define __UQSUB8 __iar_builtin_UQSUB8\r
+ #define __UHSUB8 __iar_builtin_UHSUB8\r
+ #define __SADD16 __iar_builtin_SADD16\r
+ #define __QADD16 __iar_builtin_QADD16\r
+ #define __SHADD16 __iar_builtin_SHADD16\r
+ #define __UADD16 __iar_builtin_UADD16\r
+ #define __UQADD16 __iar_builtin_UQADD16\r
+ #define __UHADD16 __iar_builtin_UHADD16\r
+ #define __SSUB16 __iar_builtin_SSUB16\r
+ #define __QSUB16 __iar_builtin_QSUB16\r
+ #define __SHSUB16 __iar_builtin_SHSUB16\r
+ #define __USUB16 __iar_builtin_USUB16\r
+ #define __UQSUB16 __iar_builtin_UQSUB16\r
+ #define __UHSUB16 __iar_builtin_UHSUB16\r
+ #define __SASX __iar_builtin_SASX\r
+ #define __QASX __iar_builtin_QASX\r
+ #define __SHASX __iar_builtin_SHASX\r
+ #define __UASX __iar_builtin_UASX\r
+ #define __UQASX __iar_builtin_UQASX\r
+ #define __UHASX __iar_builtin_UHASX\r
+ #define __SSAX __iar_builtin_SSAX\r
+ #define __QSAX __iar_builtin_QSAX\r
+ #define __SHSAX __iar_builtin_SHSAX\r
+ #define __USAX __iar_builtin_USAX\r
+ #define __UQSAX __iar_builtin_UQSAX\r
+ #define __UHSAX __iar_builtin_UHSAX\r
+ #define __USAD8 __iar_builtin_USAD8\r
+ #define __USADA8 __iar_builtin_USADA8\r
+ #define __SSAT16 __iar_builtin_SSAT16\r
+ #define __USAT16 __iar_builtin_USAT16\r
+ #define __UXTB16 __iar_builtin_UXTB16\r
+ #define __UXTAB16 __iar_builtin_UXTAB16\r
+ #define __SXTB16 __iar_builtin_SXTB16\r
+ #define __SXTAB16 __iar_builtin_SXTAB16\r
+ #define __SMUAD __iar_builtin_SMUAD\r
+ #define __SMUADX __iar_builtin_SMUADX\r
+ #define __SMMLA __iar_builtin_SMMLA\r
+ #define __SMLAD __iar_builtin_SMLAD\r
+ #define __SMLADX __iar_builtin_SMLADX\r
+ #define __SMLALD __iar_builtin_SMLALD\r
+ #define __SMLALDX __iar_builtin_SMLALDX\r
+ #define __SMUSD __iar_builtin_SMUSD\r
+ #define __SMUSDX __iar_builtin_SMUSDX\r
+ #define __SMLSD __iar_builtin_SMLSD\r
+ #define __SMLSDX __iar_builtin_SMLSDX\r
+ #define __SMLSLD __iar_builtin_SMLSLD\r
+ #define __SMLSLDX __iar_builtin_SMLSLDX\r
+ #define __SEL __iar_builtin_SEL\r
+ #define __QADD __iar_builtin_QADD\r
+ #define __QSUB __iar_builtin_QSUB\r
+ #define __PKHBT __iar_builtin_PKHBT\r
+ #define __PKHTB __iar_builtin_PKHTB\r
+ #endif\r
+\r
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */\r
+\r
+ #if __IAR_M0_FAMILY\r
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */\r
+ #define __CLZ __cmsis_iar_clz_not_active\r
+ #define __SSAT __cmsis_iar_ssat_not_active\r
+ #define __USAT __cmsis_iar_usat_not_active\r
+ #define __RBIT __cmsis_iar_rbit_not_active\r
+ #define __get_APSR __cmsis_iar_get_APSR_not_active\r
+ #endif\r
+\r
+\r
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))\r
+ #define __get_FPSCR __cmsis_iar_get_FPSR_not_active\r
+ #define __set_FPSCR __cmsis_iar_set_FPSR_not_active\r
+ #endif\r
+\r
+ #ifdef __INTRINSICS_INCLUDED\r
+ #error intrinsics.h is already included previously!\r
+ #endif\r
+\r
+ #include <intrinsics.h>\r
+\r
+ #if __IAR_M0_FAMILY\r
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */\r
+ #undef __CLZ\r
+ #undef __SSAT\r
+ #undef __USAT\r
+ #undef __RBIT\r
+ #undef __get_APSR\r
+\r
+ __STATIC_INLINE uint8_t __CLZ(uint32_t data)\r
+ {\r
+ if (data == 0U) { return 32U; }\r
+\r
+ uint32_t count = 0U;\r
+ uint32_t mask = 0x80000000U;\r
+\r
+ while ((data & mask) == 0U)\r
+ {\r
+ count += 1U;\r
+ mask = mask >> 1U;\r
+ }\r
+ return count;\r
+ }\r
+\r
+ __STATIC_INLINE uint32_t __RBIT(uint32_t v)\r
+ {\r
+ uint8_t sc = 31U;\r
+ uint32_t r = v;\r
+ for (v >>= 1U; v; v >>= 1U)\r
+ {\r
+ r <<= 1U;\r
+ r |= v & 1U;\r
+ sc--;\r
+ }\r
+ return (r << sc);\r
+ }\r
+\r
+ __STATIC_INLINE uint32_t __get_APSR(void)\r
+ {\r
+ uint32_t res;\r
+ __asm("MRS %0,APSR" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ #endif\r
+\r
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))\r
+ #undef __get_FPSCR\r
+ #undef __set_FPSCR\r
+ #define __get_FPSCR() (0)\r
+ #define __set_FPSCR(VALUE) ((void)VALUE)\r
+ #endif\r
+\r
+ #pragma diag_suppress=Pe940\r
+ #pragma diag_suppress=Pe177\r
+\r
+ #define __enable_irq __enable_interrupt\r
+ #define __disable_irq __disable_interrupt\r
+ #define __NOP __no_operation\r
+\r
+ #define __get_xPSR __get_PSR\r
+\r
+ #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)\r
+\r
+ __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)\r
+ {\r
+ return __LDREX((unsigned long *)ptr);\r
+ }\r
+\r
+ __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)\r
+ {\r
+ return __STREX(value, (unsigned long *)ptr);\r
+ }\r
+ #endif\r
+\r
+\r
+ /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */\r
+ #if (__CORTEX_M >= 0x03)\r
+\r
+ __IAR_FT uint32_t __RRX(uint32_t value)\r
+ {\r
+ uint32_t result;\r
+ __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");\r
+ return(result);\r
+ }\r
+\r
+ __IAR_FT void __set_BASEPRI_MAX(uint32_t value)\r
+ {\r
+ __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));\r
+ }\r
+\r
+\r
+ #define __enable_fault_irq __enable_fiq\r
+ #define __disable_fault_irq __disable_fiq\r
+\r
+\r
+ #endif /* (__CORTEX_M >= 0x03) */\r
+\r
+ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+ {\r
+ return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));\r
+ }\r
+\r
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+\r
+ __IAR_FT uint32_t __get_MSPLIM(void)\r
+ {\r
+ uint32_t res;\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ res = 0U;\r
+ #else\r
+ __asm volatile("MRS %0,MSPLIM" : "=r" (res));\r
+ #endif\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __set_MSPLIM(uint32_t value)\r
+ {\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ (void)value;\r
+ #else\r
+ __asm volatile("MSR MSPLIM,%0" :: "r" (value));\r
+ #endif\r
+ }\r
+\r
+ __IAR_FT uint32_t __get_PSPLIM(void)\r
+ {\r
+ uint32_t res;\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ res = 0U;\r
+ #else\r
+ __asm volatile("MRS %0,PSPLIM" : "=r" (res));\r
+ #endif\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __set_PSPLIM(uint32_t value)\r
+ {\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ (void)value;\r
+ #else\r
+ __asm volatile("MSR PSPLIM,%0" :: "r" (value));\r
+ #endif\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_PSP_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,PSP_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_PSP_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR PSP_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_MSP_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,MSP_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_MSP_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR MSP_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_SP_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,SP_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+ __IAR_FT void __TZ_set_SP_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR SP_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)\r
+ {\r
+ uint32_t res;\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ res = 0U;\r
+ #else\r
+ __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));\r
+ #endif\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)\r
+ {\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ (void)value;\r
+ #else\r
+ __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));\r
+ #endif\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */\r
+\r
+#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */\r
+\r
+#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))\r
+\r
+#if __IAR_M0_FAMILY\r
+ __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)\r
+ {\r
+ if ((sat >= 1U) && (sat <= 32U))\r
+ {\r
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\r
+ const int32_t min = -1 - max ;\r
+ if (val > max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < min)\r
+ {\r
+ return min;\r
+ }\r
+ }\r
+ return val;\r
+ }\r
+\r
+ __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)\r
+ {\r
+ if (sat <= 31U)\r
+ {\r
+ const uint32_t max = ((1U << sat) - 1U);\r
+ if (val > (int32_t)max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < 0)\r
+ {\r
+ return 0U;\r
+ }\r
+ }\r
+ return (uint32_t)val;\r
+ }\r
+#endif\r
+\r
+#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */\r
+\r
+ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)\r
+ {\r
+ uint32_t res;\r
+ __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");\r
+ return ((uint8_t)res);\r
+ }\r
+\r
+ __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)\r
+ {\r
+ uint32_t res;\r
+ __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");\r
+ return ((uint16_t)res);\r
+ }\r
+\r
+ __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)\r
+ {\r
+ uint32_t res;\r
+ __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)\r
+ {\r
+ __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");\r
+ }\r
+\r
+ __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)\r
+ {\r
+ __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");\r
+ }\r
+\r
+ __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)\r
+ {\r
+ __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");\r
+ }\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+\r
+\r
+ __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+ return ((uint8_t)res);\r
+ }\r
+\r
+ __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+ return ((uint16_t)res);\r
+ }\r
+\r
+ __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)\r
+ {\r
+ __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");\r
+ }\r
+\r
+ __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)\r
+ {\r
+ __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");\r
+ }\r
+\r
+ __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)\r
+ {\r
+ __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");\r
+ }\r
+\r
+ __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+ return ((uint8_t)res);\r
+ }\r
+\r
+ __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+ return ((uint16_t)res);\r
+ }\r
+\r
+ __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");\r
+ return res;\r
+ }\r
+\r
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */\r
+\r
+#undef __IAR_FT\r
+#undef __IAR_M0_FAMILY\r
+#undef __ICCARM_V8\r
+\r
+#pragma diag_default=Pe940\r
+#pragma diag_default=Pe177\r
+\r
+#endif /* __CMSIS_ICCARM_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_version.h\r
+ * @brief CMSIS Core(M) Version definitions\r
+ * @version V5.0.2\r
+ * @date 19. April 2017\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CMSIS_VERSION_H\r
+#define __CMSIS_VERSION_H\r
+\r
+/* CMSIS Version definitions */\r
+#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */\r
+#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */\r
+#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_armv81mml.h\r
+ * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File\r
+ * @version V1.0.0\r
+ * @date 15. March 2019\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2018-2019 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_ARMV81MML_H_GENERIC\r
+#define __CORE_ARMV81MML_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_ARMV81MML\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+ \r
+#define __ARM_ARCH_8M_MAIN__ 1 // patching for now\r
+/* CMSIS ARMV81MML definitions */\r
+#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \\r
+ __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (81U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined(__ARM_FEATURE_DSP)\r
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U \r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+ \r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_FP\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined(__ARM_FEATURE_DSP)\r
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U \r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ \r
+ #if defined(__ARM_FEATURE_DSP)\r
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U \r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+ \r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined(__ARM_FEATURE_DSP)\r
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U \r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+ \r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_ARMV81MML_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_ARMV81MML_H_DEPENDANT\r
+#define __CORE_ARMV81MML_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __ARMv81MML_REV\r
+ #define __ARMv81MML_REV 0x0000U\r
+ #warning "__ARMv81MML_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0U\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __SAUREGION_PRESENT\r
+ #define __SAUREGION_PRESENT 0U\r
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __DSP_PRESENT\r
+ #define __DSP_PRESENT 0U\r
+ #warning "__DSP_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group ARMv81MML */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core SAU Register\r
+ - Core FPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */\r
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */\r
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */\r
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */\r
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */\r
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */\r
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */\r
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */\r
+\r
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */\r
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
+\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[16U];\r
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[16U];\r
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[16U];\r
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[16U];\r
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[16U];\r
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */\r
+ uint32_t RESERVED5[16U];\r
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED6[580U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */\r
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */\r
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */\r
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */\r
+ uint32_t RESERVED3[92U];\r
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */\r
+ uint32_t RESERVED4[15U];\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */\r
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */\r
+ uint32_t RESERVED5[1U];\r
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */\r
+ uint32_t RESERVED6[1U];\r
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */\r
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */\r
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */\r
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */\r
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */\r
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */\r
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */\r
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */\r
+ uint32_t RESERVED7[6U];\r
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */\r
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */\r
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */\r
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */\r
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */\r
+ uint32_t RESERVED8[1U];\r
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */\r
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */\r
+\r
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\r
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\r
+\r
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */\r
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */\r
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */\r
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */\r
+\r
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */\r
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */\r
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */\r
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */\r
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */\r
+\r
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */\r
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */\r
+\r
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */\r
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */\r
+\r
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */\r
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */\r
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */\r
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */\r
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */\r
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */\r
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */\r
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */\r
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */\r
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/* SCB Non-Secure Access Control Register Definitions */\r
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */\r
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */\r
+\r
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */\r
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */\r
+\r
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */\r
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */\r
+\r
+/* SCB Cache Level ID Register Definitions */\r
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */\r
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */\r
+\r
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */\r
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */\r
+\r
+/* SCB Cache Type Register Definitions */\r
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */\r
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */\r
+\r
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */\r
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */\r
+\r
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */\r
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */\r
+\r
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */\r
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */\r
+\r
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */\r
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */\r
+\r
+/* SCB Cache Size ID Register Definitions */\r
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */\r
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */\r
+\r
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */\r
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */\r
+\r
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */\r
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */\r
+\r
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */\r
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */\r
+\r
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */\r
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */\r
+\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */\r
+\r
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */\r
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */\r
+\r
+/* SCB Cache Size Selection Register Definitions */\r
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */\r
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */\r
+\r
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */\r
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */\r
+\r
+/* SCB Software Triggered Interrupt Register Definitions */\r
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */\r
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */\r
+\r
+/* SCB D-Cache Invalidate by Set-way Register Definitions */\r
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */\r
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */\r
+\r
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */\r
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */\r
+\r
+/* SCB D-Cache Clean by Set-way Register Definitions */\r
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */\r
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */\r
+\r
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */\r
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */\r
+\r
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\r
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */\r
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */\r
+\r
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */\r
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */\r
+\r
+/* Instruction Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */\r
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */\r
+\r
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */\r
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */\r
+\r
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */\r
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */\r
+\r
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */\r
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */\r
+\r
+/* Data Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */\r
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */\r
+\r
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */\r
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */\r
+\r
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */\r
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */\r
+\r
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */\r
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */\r
+\r
+/* AHBP Control Register Definitions */\r
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */\r
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */\r
+\r
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */\r
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */\r
+\r
+/* L1 Cache Control Register Definitions */\r
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */\r
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */\r
+\r
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */\r
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */\r
+\r
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */\r
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */\r
+\r
+/* AHBS Control Register Definitions */\r
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */\r
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */\r
+\r
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */\r
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */\r
+\r
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/\r
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */\r
+\r
+/* Auxiliary Bus Fault Status Register Definitions */\r
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/\r
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */\r
+\r
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/\r
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */\r
+\r
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/\r
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */\r
+\r
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/\r
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */\r
+\r
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/\r
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */\r
+\r
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/\r
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __OM union\r
+ {\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29U];\r
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[1U];\r
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */\r
+ uint32_t RESERVED6[4U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Stimulus Port Register Definitions */\r
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */\r
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */\r
+\r
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */\r
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */\r
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */\r
+\r
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */\r
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ uint32_t RESERVED3[1U];\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ uint32_t RESERVED5[1U];\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED6[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ uint32_t RESERVED7[1U];\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+ uint32_t RESERVED8[1U];\r
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */\r
+ uint32_t RESERVED9[1U];\r
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */\r
+ uint32_t RESERVED10[1U];\r
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */\r
+ uint32_t RESERVED11[1U];\r
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */\r
+ uint32_t RESERVED12[1U];\r
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */\r
+ uint32_t RESERVED13[1U];\r
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */\r
+ uint32_t RESERVED14[1U];\r
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */\r
+ uint32_t RESERVED15[1U];\r
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */\r
+ uint32_t RESERVED16[1U];\r
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */\r
+ uint32_t RESERVED17[1U];\r
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */\r
+ uint32_t RESERVED18[1U];\r
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */\r
+ uint32_t RESERVED19[1U];\r
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */\r
+ uint32_t RESERVED20[1U];\r
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */\r
+ uint32_t RESERVED21[1U];\r
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */\r
+ uint32_t RESERVED22[1U];\r
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */\r
+ uint32_t RESERVED23[1U];\r
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */\r
+ uint32_t RESERVED24[1U];\r
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */\r
+ uint32_t RESERVED25[1U];\r
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */\r
+ uint32_t RESERVED26[1U];\r
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */\r
+ uint32_t RESERVED27[1U];\r
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */\r
+ uint32_t RESERVED28[1U];\r
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */\r
+ uint32_t RESERVED29[1U];\r
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */\r
+ uint32_t RESERVED30[1U];\r
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */\r
+ uint32_t RESERVED31[1U];\r
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */\r
+ uint32_t RESERVED32[934U];\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */\r
+ uint32_t RESERVED33[1U];\r
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */\r
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */\r
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */\r
+\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */\r
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */\r
+\r
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */\r
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */\r
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */\r
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */\r
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */\r
+ uint32_t RESERVED0[1];\r
+ union {\r
+ __IOM uint32_t MAIR[2];\r
+ struct {\r
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */\r
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */\r
+ };\r
+ };\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES 4U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */\r
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */\r
+\r
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */\r
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */\r
+\r
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */\r
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */\r
+\r
+/* MPU Region Limit Address Register Definitions */\r
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */\r
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */\r
+\r
+#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */\r
+#define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */\r
+\r
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */\r
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */\r
+\r
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */\r
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 0 Definitions */\r
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */\r
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */\r
+\r
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */\r
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */\r
+\r
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */\r
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */\r
+\r
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */\r
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 1 Definitions */\r
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */\r
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */\r
+\r
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */\r
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */\r
+\r
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */\r
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */\r
+\r
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */\r
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)\r
+ \brief Type definitions for the Security Attribution Unit (SAU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Security Attribution Unit (SAU).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */\r
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */\r
+#else\r
+ uint32_t RESERVED0[3];\r
+#endif\r
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */\r
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */\r
+} SAU_Type;\r
+\r
+/* SAU Control Register Definitions */\r
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */\r
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */\r
+\r
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */\r
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */\r
+\r
+/* SAU Type Register Definitions */\r
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */\r
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */\r
+\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+/* SAU Region Number Register Definitions */\r
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */\r
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */\r
+\r
+/* SAU Region Base Address Register Definitions */\r
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */\r
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */\r
+\r
+/* SAU Region Limit Address Register Definitions */\r
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */\r
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */\r
+\r
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */\r
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */\r
+\r
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */\r
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */\r
+\r
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\r
+\r
+/* Secure Fault Status Register Definitions */\r
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */\r
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */\r
+\r
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */\r
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */\r
+\r
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */\r
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */\r
+\r
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */\r
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */\r
+\r
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */\r
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */\r
+\r
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */\r
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */\r
+\r
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */\r
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */\r
+\r
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */\r
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */\r
+\r
+/*@} end of group CMSIS_SAU */\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
+ \brief Type definitions for the Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register Definitions */\r
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */\r
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */\r
+\r
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */\r
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */\r
+\r
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */\r
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */\r
+\r
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */\r
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */\r
+\r
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */\r
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */\r
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */\r
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */\r
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register Definitions */\r
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register Definitions */\r
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 Definitions */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 Definitions */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */\r
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/* Debug Authentication Control Register Definitions */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\r
+\r
+/* Debug Security Control and Status Register Definitions */\r
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */\r
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */\r
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */\r
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+ #endif\r
+\r
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */\r
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */\r
+ #endif\r
+\r
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */\r
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */\r
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */\r
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */\r
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */\r
+\r
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */\r
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */\r
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */\r
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */\r
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */\r
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */\r
+ #endif\r
+\r
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */\r
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Get Interrupt Target State\r
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ \return 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Target State\r
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Interrupt Target State\r
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Set Priority Grouping (non-secure)\r
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
+ SCB_NS->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping (non-secure)\r
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)\r
+{\r
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt (non-secure)\r
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status (non-secure)\r
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt (non-secure)\r
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt (non-secure)\r
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt (non-secure)\r
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt (non-secure)\r
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt (non-secure)\r
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority (non-secure)\r
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every non-secure processor exception.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority (non-secure)\r
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ########################## MPU functions #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv8.h"\r
+\r
+#endif\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ uint32_t mvfr0;\r
+\r
+ mvfr0 = FPU->MVFR0;\r
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\r
+ {\r
+ return 2U; /* Double + Single precision FPU */\r
+ }\r
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r
+ {\r
+ return 1U; /* Single precision FPU */\r
+ }\r
+ else\r
+ {\r
+ return 0U; /* No FPU */\r
+ }\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ########################## SAU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions\r
+ \brief Functions that configure the SAU.\r
+ @{\r
+ */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+\r
+/**\r
+ \brief Enable SAU\r
+ \details Enables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Enable(void)\r
+{\r
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+\r
+\r
+/**\r
+ \brief Disable SAU\r
+ \details Disables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Disable(void)\r
+{\r
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_SAUFunctions */\r
+\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief System Tick Configuration (non-secure)\r
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_ARMV81MML_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_armv8mbl.h\r
+ * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File\r
+ * @version V5.0.8\r
+ * @date 12. November 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_ARMV8MBL_H_GENERIC\r
+#define __CORE_ARMV8MBL_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_ARMv8MBL\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/* CMSIS definitions */\r
+#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \\r
+ __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M ( 2U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0U\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_FP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_ARMV8MBL_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT\r
+#define __CORE_ARMV8MBL_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __ARMv8MBL_REV\r
+ #define __ARMv8MBL_REV 0x0000U\r
+ #warning "__ARMv8MBL_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0U\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __SAUREGION_PRESENT\r
+ #define __SAUREGION_PRESENT 0U\r
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __VTOR_PRESENT\r
+ #define __VTOR_PRESENT 0U\r
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __ETM_PRESENT\r
+ #define __ETM_PRESENT 0U\r
+ #warning "__ETM_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MTB_PRESENT\r
+ #define __MTB_PRESENT 0U\r
+ #warning "__MTB_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group ARMv8MBL */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core SAU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[16U];\r
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[16U];\r
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[16U];\r
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[16U];\r
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[16U];\r
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */\r
+ uint32_t RESERVED5[16U];\r
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+#else\r
+ uint32_t RESERVED0;\r
+#endif\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED1;\r
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */\r
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */\r
+\r
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\r
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\r
+\r
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */\r
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */\r
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#endif\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */\r
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */\r
+\r
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */\r
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */\r
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */\r
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */\r
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */\r
+\r
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */\r
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */\r
+\r
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */\r
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */\r
+\r
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */\r
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */\r
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */\r
+\r
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */\r
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ uint32_t RESERVED0[6U];\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ uint32_t RESERVED3[1U];\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ uint32_t RESERVED5[1U];\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED6[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ uint32_t RESERVED7[1U];\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+ uint32_t RESERVED8[1U];\r
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */\r
+ uint32_t RESERVED9[1U];\r
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */\r
+ uint32_t RESERVED10[1U];\r
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */\r
+ uint32_t RESERVED11[1U];\r
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */\r
+ uint32_t RESERVED12[1U];\r
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */\r
+ uint32_t RESERVED13[1U];\r
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */\r
+ uint32_t RESERVED14[1U];\r
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */\r
+ uint32_t RESERVED15[1U];\r
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */\r
+ uint32_t RESERVED16[1U];\r
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */\r
+ uint32_t RESERVED17[1U];\r
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */\r
+ uint32_t RESERVED18[1U];\r
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */\r
+ uint32_t RESERVED19[1U];\r
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */\r
+ uint32_t RESERVED20[1U];\r
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */\r
+ uint32_t RESERVED21[1U];\r
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */\r
+ uint32_t RESERVED22[1U];\r
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */\r
+ uint32_t RESERVED23[1U];\r
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */\r
+ uint32_t RESERVED24[1U];\r
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */\r
+ uint32_t RESERVED25[1U];\r
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */\r
+ uint32_t RESERVED26[1U];\r
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */\r
+ uint32_t RESERVED27[1U];\r
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */\r
+ uint32_t RESERVED28[1U];\r
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */\r
+ uint32_t RESERVED29[1U];\r
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */\r
+ uint32_t RESERVED30[1U];\r
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */\r
+ uint32_t RESERVED31[1U];\r
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */\r
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */\r
+\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */\r
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */\r
+\r
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */\r
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */\r
+ uint32_t RESERVED3[809U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */\r
+ uint32_t RESERVED4[4U];\r
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */\r
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */\r
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI Periodic Synchronization Control Register Definitions */\r
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */\r
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */\r
+\r
+/* TPI Software Lock Status Register Definitions */\r
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */\r
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */\r
+\r
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */\r
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */\r
+\r
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */\r
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */\r
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */\r
+ uint32_t RESERVED0[7U];\r
+ union {\r
+ __IOM uint32_t MAIR[2];\r
+ struct {\r
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */\r
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */\r
+ };\r
+ };\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES 1U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */\r
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */\r
+\r
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */\r
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */\r
+\r
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */\r
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */\r
+\r
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */\r
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */\r
+\r
+/* MPU Region Limit Address Register Definitions */\r
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */\r
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */\r
+\r
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */\r
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */\r
+\r
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */\r
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 0 Definitions */\r
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */\r
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */\r
+\r
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */\r
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */\r
+\r
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */\r
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */\r
+\r
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */\r
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 1 Definitions */\r
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */\r
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */\r
+\r
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */\r
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */\r
+\r
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */\r
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */\r
+\r
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */\r
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)\r
+ \brief Type definitions for the Security Attribution Unit (SAU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Security Attribution Unit (SAU).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */\r
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */\r
+#endif\r
+} SAU_Type;\r
+\r
+/* SAU Control Register Definitions */\r
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */\r
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */\r
+\r
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */\r
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */\r
+\r
+/* SAU Type Register Definitions */\r
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */\r
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */\r
+\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+/* SAU Region Number Register Definitions */\r
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */\r
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */\r
+\r
+/* SAU Region Base Address Register Definitions */\r
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */\r
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */\r
+\r
+/* SAU Region Limit Address Register Definitions */\r
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */\r
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */\r
+\r
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */\r
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */\r
+\r
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */\r
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */\r
+\r
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\r
+\r
+/*@} end of group CMSIS_SAU */\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */\r
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */\r
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/* Debug Authentication Control Register Definitions */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\r
+\r
+/* Debug Security Control and Status Register Definitions */\r
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */\r
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */\r
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */\r
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+\r
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+ #endif\r
+\r
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */\r
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */\r
+ #endif\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */\r
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */\r
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */\r
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */\r
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */\r
+\r
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */\r
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */\r
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */\r
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */\r
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */\r
+ #endif\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* Special LR values for Secure/Non-Secure call handling and exception handling */\r
+\r
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */\r
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */\r
+\r
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\r
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */\r
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */\r
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */\r
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */\r
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */\r
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */\r
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\r
+\r
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */\r
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */\r
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */\r
+#else\r
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */\r
+#endif\r
+\r
+\r
+/* Interrupt Priorities are WORD accessible only under Armv6-M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)\r
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )\r
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )\r
+\r
+#define __NVIC_SetPriorityGrouping(X) (void)(X)\r
+#define __NVIC_GetPriorityGrouping() (0U)\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Get Interrupt Target State\r
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ \return 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Target State\r
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Interrupt Target State\r
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+ else\r
+ {\r
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ If VTOR is not present address 0 must be mapped to SRAM.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+#else\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+#endif\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+#else\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+#endif\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Enable Interrupt (non-secure)\r
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status (non-secure)\r
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt (non-secure)\r
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt (non-secure)\r
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt (non-secure)\r
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt (non-secure)\r
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt (non-secure)\r
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority (non-secure)\r
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every non-secure processor exception.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+ else\r
+ {\r
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority (non-secure)\r
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ########################## MPU functions #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv8.h"\r
+\r
+#endif\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ return 0U; /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ########################## SAU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions\r
+ \brief Functions that configure the SAU.\r
+ @{\r
+ */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+\r
+/**\r
+ \brief Enable SAU\r
+ \details Enables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Enable(void)\r
+{\r
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+\r
+\r
+/**\r
+ \brief Disable SAU\r
+ \details Disables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Disable(void)\r
+{\r
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_SAUFunctions */\r
+\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief System Tick Configuration (non-secure)\r
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_armv8mml.h\r
+ * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File\r
+ * @version V5.1.0\r
+ * @date 12. September 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_ARMV8MML_H_GENERIC\r
+#define __CORE_ARMV8MML_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_ARMv8MML\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/* CMSIS Armv8MML definitions */\r
+#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \\r
+ __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (81U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined(__ARM_FEATURE_DSP)\r
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U\r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_FP\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined(__ARM_FEATURE_DSP)\r
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U\r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined(__ARM_FEATURE_DSP)\r
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U\r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined(__ARM_FEATURE_DSP)\r
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U\r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_ARMV8MML_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_ARMV8MML_H_DEPENDANT\r
+#define __CORE_ARMV8MML_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __ARMv8MML_REV\r
+ #define __ARMv8MML_REV 0x0000U\r
+ #warning "__ARMv8MML_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0U\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __SAUREGION_PRESENT\r
+ #define __SAUREGION_PRESENT 0U\r
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __DSP_PRESENT\r
+ #define __DSP_PRESENT 0U\r
+ #warning "__DSP_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group ARMv8MML */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core SAU Register\r
+ - Core FPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */\r
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */\r
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */\r
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */\r
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */\r
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */\r
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */\r
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */\r
+\r
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */\r
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
+\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[16U];\r
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[16U];\r
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[16U];\r
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[16U];\r
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[16U];\r
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */\r
+ uint32_t RESERVED5[16U];\r
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED6[580U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */\r
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */\r
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */\r
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */\r
+ uint32_t RESERVED3[92U];\r
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */\r
+ uint32_t RESERVED4[15U];\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */\r
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */\r
+ uint32_t RESERVED5[1U];\r
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */\r
+ uint32_t RESERVED6[1U];\r
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */\r
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */\r
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */\r
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */\r
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */\r
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */\r
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */\r
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */\r
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */\r
+\r
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\r
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\r
+\r
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */\r
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */\r
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */\r
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */\r
+\r
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */\r
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */\r
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */\r
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */\r
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */\r
+\r
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */\r
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */\r
+\r
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */\r
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */\r
+\r
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */\r
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */\r
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */\r
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */\r
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */\r
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */\r
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */\r
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */\r
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */\r
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/* SCB Non-Secure Access Control Register Definitions */\r
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */\r
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */\r
+\r
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */\r
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */\r
+\r
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */\r
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */\r
+\r
+/* SCB Cache Level ID Register Definitions */\r
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */\r
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */\r
+\r
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */\r
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */\r
+\r
+/* SCB Cache Type Register Definitions */\r
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */\r
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */\r
+\r
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */\r
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */\r
+\r
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */\r
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */\r
+\r
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */\r
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */\r
+\r
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */\r
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */\r
+\r
+/* SCB Cache Size ID Register Definitions */\r
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */\r
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */\r
+\r
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */\r
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */\r
+\r
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */\r
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */\r
+\r
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */\r
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */\r
+\r
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */\r
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */\r
+\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */\r
+\r
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */\r
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */\r
+\r
+/* SCB Cache Size Selection Register Definitions */\r
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */\r
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */\r
+\r
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */\r
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */\r
+\r
+/* SCB Software Triggered Interrupt Register Definitions */\r
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */\r
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */\r
+\r
+/* SCB D-Cache Invalidate by Set-way Register Definitions */\r
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */\r
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */\r
+\r
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */\r
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */\r
+\r
+/* SCB D-Cache Clean by Set-way Register Definitions */\r
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */\r
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */\r
+\r
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */\r
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */\r
+\r
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\r
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */\r
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */\r
+\r
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */\r
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __OM union\r
+ {\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[32U];\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[1U];\r
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */\r
+ uint32_t RESERVED6[4U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Stimulus Port Register Definitions */\r
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */\r
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */\r
+\r
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */\r
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */\r
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */\r
+\r
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */\r
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ uint32_t RESERVED3[1U];\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ uint32_t RESERVED5[1U];\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED6[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ uint32_t RESERVED7[1U];\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+ uint32_t RESERVED8[1U];\r
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */\r
+ uint32_t RESERVED9[1U];\r
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */\r
+ uint32_t RESERVED10[1U];\r
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */\r
+ uint32_t RESERVED11[1U];\r
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */\r
+ uint32_t RESERVED12[1U];\r
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */\r
+ uint32_t RESERVED13[1U];\r
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */\r
+ uint32_t RESERVED14[1U];\r
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */\r
+ uint32_t RESERVED15[1U];\r
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */\r
+ uint32_t RESERVED16[1U];\r
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */\r
+ uint32_t RESERVED17[1U];\r
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */\r
+ uint32_t RESERVED18[1U];\r
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */\r
+ uint32_t RESERVED19[1U];\r
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */\r
+ uint32_t RESERVED20[1U];\r
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */\r
+ uint32_t RESERVED21[1U];\r
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */\r
+ uint32_t RESERVED22[1U];\r
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */\r
+ uint32_t RESERVED23[1U];\r
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */\r
+ uint32_t RESERVED24[1U];\r
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */\r
+ uint32_t RESERVED25[1U];\r
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */\r
+ uint32_t RESERVED26[1U];\r
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */\r
+ uint32_t RESERVED27[1U];\r
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */\r
+ uint32_t RESERVED28[1U];\r
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */\r
+ uint32_t RESERVED29[1U];\r
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */\r
+ uint32_t RESERVED30[1U];\r
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */\r
+ uint32_t RESERVED31[1U];\r
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */\r
+ uint32_t RESERVED32[934U];\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */\r
+ uint32_t RESERVED33[1U];\r
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */\r
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */\r
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */\r
+\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */\r
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */\r
+\r
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */\r
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */\r
+ uint32_t RESERVED3[809U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */\r
+ uint32_t RESERVED4[4U];\r
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */\r
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */\r
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI Periodic Synchronization Control Register Definitions */\r
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */\r
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */\r
+\r
+/* TPI Software Lock Status Register Definitions */\r
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */\r
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */\r
+\r
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */\r
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */\r
+\r
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */\r
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */\r
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */\r
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */\r
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */\r
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */\r
+ uint32_t RESERVED0[1];\r
+ union {\r
+ __IOM uint32_t MAIR[2];\r
+ struct {\r
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */\r
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */\r
+ };\r
+ };\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES 4U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */\r
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */\r
+\r
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */\r
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */\r
+\r
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */\r
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */\r
+\r
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */\r
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */\r
+\r
+/* MPU Region Limit Address Register Definitions */\r
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */\r
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */\r
+\r
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */\r
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */\r
+\r
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */\r
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 0 Definitions */\r
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */\r
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */\r
+\r
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */\r
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */\r
+\r
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */\r
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */\r
+\r
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */\r
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 1 Definitions */\r
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */\r
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */\r
+\r
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */\r
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */\r
+\r
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */\r
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */\r
+\r
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */\r
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)\r
+ \brief Type definitions for the Security Attribution Unit (SAU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Security Attribution Unit (SAU).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */\r
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */\r
+#else\r
+ uint32_t RESERVED0[3];\r
+#endif\r
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */\r
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */\r
+} SAU_Type;\r
+\r
+/* SAU Control Register Definitions */\r
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */\r
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */\r
+\r
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */\r
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */\r
+\r
+/* SAU Type Register Definitions */\r
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */\r
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */\r
+\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+/* SAU Region Number Register Definitions */\r
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */\r
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */\r
+\r
+/* SAU Region Base Address Register Definitions */\r
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */\r
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */\r
+\r
+/* SAU Region Limit Address Register Definitions */\r
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */\r
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */\r
+\r
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */\r
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */\r
+\r
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */\r
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */\r
+\r
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\r
+\r
+/* Secure Fault Status Register Definitions */\r
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */\r
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */\r
+\r
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */\r
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */\r
+\r
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */\r
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */\r
+\r
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */\r
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */\r
+\r
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */\r
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */\r
+\r
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */\r
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */\r
+\r
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */\r
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */\r
+\r
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */\r
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */\r
+\r
+/*@} end of group CMSIS_SAU */\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
+ \brief Type definitions for the Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register Definitions */\r
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */\r
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */\r
+\r
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */\r
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */\r
+\r
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */\r
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */\r
+\r
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */\r
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */\r
+\r
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */\r
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */\r
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */\r
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */\r
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register Definitions */\r
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register Definitions */\r
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 Definitions */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 Definitions */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */\r
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/* Debug Authentication Control Register Definitions */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\r
+\r
+/* Debug Security Control and Status Register Definitions */\r
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */\r
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */\r
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */\r
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+ #endif\r
+\r
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */\r
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */\r
+ #endif\r
+\r
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */\r
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */\r
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */\r
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */\r
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */\r
+\r
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */\r
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */\r
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */\r
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */\r
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */\r
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */\r
+ #endif\r
+\r
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */\r
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* Special LR values for Secure/Non-Secure call handling and exception handling */\r
+\r
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */\r
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */\r
+\r
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\r
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */\r
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */\r
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */\r
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */\r
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */\r
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */\r
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\r
+\r
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */\r
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */\r
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */\r
+#else\r
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Get Interrupt Target State\r
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ \return 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Target State\r
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Interrupt Target State\r
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Set Priority Grouping (non-secure)\r
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */\r
+ SCB_NS->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping (non-secure)\r
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)\r
+{\r
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt (non-secure)\r
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status (non-secure)\r
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt (non-secure)\r
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt (non-secure)\r
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt (non-secure)\r
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt (non-secure)\r
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt (non-secure)\r
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority (non-secure)\r
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every non-secure processor exception.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority (non-secure)\r
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ########################## MPU functions #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv8.h"\r
+\r
+#endif\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ uint32_t mvfr0;\r
+\r
+ mvfr0 = FPU->MVFR0;\r
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\r
+ {\r
+ return 2U; /* Double + Single precision FPU */\r
+ }\r
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r
+ {\r
+ return 1U; /* Single precision FPU */\r
+ }\r
+ else\r
+ {\r
+ return 0U; /* No FPU */\r
+ }\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ########################## SAU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions\r
+ \brief Functions that configure the SAU.\r
+ @{\r
+ */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+\r
+/**\r
+ \brief Enable SAU\r
+ \details Enables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Enable(void)\r
+{\r
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+\r
+\r
+/**\r
+ \brief Disable SAU\r
+ \details Disables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Disable(void)\r
+{\r
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_SAUFunctions */\r
+\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief System Tick Configuration (non-secure)\r
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm4.h\r
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File\r
+ * @version V5.1.0\r
+ * @date 13. March 2019\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM4_H_GENERIC\r
+#define __CORE_CM4_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_M4\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/* CMSIS CM4 definitions */\r
+#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (4U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_FP\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM4_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM4_H_DEPENDANT\r
+#define __CORE_CM4_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM4_REV\r
+ #define __CM4_REV 0x0000U\r
+ #warning "__CM4_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0U\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M4 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core FPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */\r
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */\r
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit */\r
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */\r
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */\r
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
+\r
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */\r
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */\r
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
+\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24U];\r
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RESERVED1[24U];\r
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24U];\r
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24U];\r
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56U];\r
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5U];\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */\r
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */\r
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */\r
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */\r
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __OM union\r
+ {\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[32U];\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */\r
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */\r
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */\r
+\r
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */\r
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */\r
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */\r
+\r
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */\r
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES 4U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
+ \brief Type definitions for the Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register Definitions */\r
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register Definitions */\r
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register Definitions */\r
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 Definitions */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 Definitions */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/* Media and FP Feature Register 2 Definitions */\r
+\r
+#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */\r
+#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* The following EXC_RETURN values are saved the LR on exception entry */\r
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */\r
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */\r
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */\r
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */\r
+\r
+\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t vectors = (uint32_t )SCB->VTOR;\r
+ (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t vectors = (uint32_t )SCB->VTOR;\r
+ return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+/* ########################## MPU functions #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv7.h"\r
+\r
+#endif\r
+\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ uint32_t mvfr0;\r
+\r
+ mvfr0 = FPU->MVFR0;\r
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r
+ {\r
+ return 1U; /* Single precision FPU */\r
+ }\r
+ else\r
+ {\r
+ return 0U; /* No FPU */\r
+ }\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM4_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/******************************************************************************\r
+ * @file mpu_armv7.h\r
+ * @brief CMSIS MPU API for Armv7-M MPU\r
+ * @version V5.1.0\r
+ * @date 08. March 2019\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+ \r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+ \r
+#ifndef ARM_MPU_ARMV7_H\r
+#define ARM_MPU_ARMV7_H\r
+\r
+#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes\r
+#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes\r
+#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes\r
+#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes\r
+#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes\r
+#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte\r
+#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes\r
+#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes\r
+#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes\r
+#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes\r
+#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes\r
+#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes\r
+#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes\r
+#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes\r
+#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes\r
+#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte\r
+#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes\r
+#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes\r
+#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes\r
+#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes\r
+#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes\r
+#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes\r
+#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes\r
+#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes\r
+#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes\r
+#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte\r
+#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes\r
+#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes\r
+\r
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access\r
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only\r
+#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only\r
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access\r
+#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only\r
+#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access\r
+\r
+/** MPU Region Base Address Register Value\r
+*\r
+* \param Region The region to be configured, number 0 to 15.\r
+* \param BaseAddress The base address for the region.\r
+*/\r
+#define ARM_MPU_RBAR(Region, BaseAddress) \\r
+ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \\r
+ ((Region) & MPU_RBAR_REGION_Msk) | \\r
+ (MPU_RBAR_VALID_Msk))\r
+\r
+/**\r
+* MPU Memory Access Attributes\r
+* \r
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.\r
+* \param IsShareable Region is shareable between multiple bus masters.\r
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.\r
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.\r
+*/ \r
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \\r
+ ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \\r
+ (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \\r
+ (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \\r
+ (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))\r
+\r
+/**\r
+* MPU Region Attribute and Size Register Value\r
+* \r
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.\r
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.\r
+* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.\r
+* \param SubRegionDisable Sub-region disable field.\r
+* \param Size Region size of the region to be configured, for example 4K, 8K.\r
+*/\r
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \\r
+ ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \\r
+ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \\r
+ (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \\r
+ (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \\r
+ (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \\r
+ (((MPU_RASR_ENABLE_Msk))))\r
+\r
+/**\r
+* MPU Region Attribute and Size Register Value\r
+* \r
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.\r
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.\r
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.\r
+* \param IsShareable Region is shareable between multiple bus masters.\r
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.\r
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.\r
+* \param SubRegionDisable Sub-region disable field.\r
+* \param Size Region size of the region to be configured, for example 4K, 8K.\r
+*/ \r
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \\r
+ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)\r
+\r
+/**\r
+* MPU Memory Access Attribute for strongly ordered memory.\r
+* - TEX: 000b\r
+* - Shareable\r
+* - Non-cacheable\r
+* - Non-bufferable\r
+*/ \r
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)\r
+\r
+/**\r
+* MPU Memory Access Attribute for device memory.\r
+* - TEX: 000b (if shareable) or 010b (if non-shareable)\r
+* - Shareable or non-shareable\r
+* - Non-cacheable\r
+* - Bufferable (if shareable) or non-bufferable (if non-shareable)\r
+*\r
+* \param IsShareable Configures the device memory as shareable or non-shareable.\r
+*/ \r
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))\r
+\r
+/**\r
+* MPU Memory Access Attribute for normal memory.\r
+* - TEX: 1BBb (reflecting outer cacheability rules)\r
+* - Shareable or non-shareable\r
+* - Cacheable or non-cacheable (reflecting inner cacheability rules)\r
+* - Bufferable or non-bufferable (reflecting inner cacheability rules)\r
+*\r
+* \param OuterCp Configures the outer cache policy.\r
+* \param InnerCp Configures the inner cache policy.\r
+* \param IsShareable Configures the memory as shareable or non-shareable.\r
+*/ \r
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))\r
+\r
+/**\r
+* MPU Memory Access Attribute non-cacheable policy.\r
+*/\r
+#define ARM_MPU_CACHEP_NOCACHE 0U\r
+\r
+/**\r
+* MPU Memory Access Attribute write-back, write and read allocate policy.\r
+*/\r
+#define ARM_MPU_CACHEP_WB_WRA 1U\r
+\r
+/**\r
+* MPU Memory Access Attribute write-through, no write allocate policy.\r
+*/\r
+#define ARM_MPU_CACHEP_WT_NWA 2U\r
+\r
+/**\r
+* MPU Memory Access Attribute write-back, no write allocate policy.\r
+*/\r
+#define ARM_MPU_CACHEP_WB_NWA 3U\r
+\r
+\r
+/**\r
+* Struct for a single MPU Region\r
+*/\r
+typedef struct {\r
+ uint32_t RBAR; //!< The region base address register value (RBAR)\r
+ uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR\r
+} ARM_MPU_Region_t;\r
+ \r
+/** Enable the MPU.\r
+* \param MPU_Control Default access permissions for unconfigured regions.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)\r
+{\r
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+ __DSB();\r
+ __ISB();\r
+}\r
+\r
+/** Disable the MPU.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Disable(void)\r
+{\r
+ __DMB();\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;\r
+}\r
+\r
+/** Clear and disable the given MPU region.\r
+* \param rnr Region number to be cleared.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)\r
+{\r
+ MPU->RNR = rnr;\r
+ MPU->RASR = 0U;\r
+}\r
+\r
+/** Configure an MPU region.\r
+* \param rbar Value for RBAR register.\r
+* \param rsar Value for RSAR register.\r
+*/ \r
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)\r
+{\r
+ MPU->RBAR = rbar;\r
+ MPU->RASR = rasr;\r
+}\r
+\r
+/** Configure the given MPU region.\r
+* \param rnr Region number to be configured.\r
+* \param rbar Value for RBAR register.\r
+* \param rsar Value for RSAR register.\r
+*/ \r
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)\r
+{\r
+ MPU->RNR = rnr;\r
+ MPU->RBAR = rbar;\r
+ MPU->RASR = rasr;\r
+}\r
+\r
+/** Memcopy with strictly ordered memory access, e.g. for register targets.\r
+* \param dst Destination data is copied to.\r
+* \param src Source data is copied from.\r
+* \param len Amount of data words to be copied.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)\r
+{\r
+ uint32_t i;\r
+ for (i = 0U; i < len; ++i) \r
+ {\r
+ dst[i] = src[i];\r
+ }\r
+}\r
+\r
+/** Load the given number of MPU regions from a table.\r
+* \param table Pointer to the MPU configuration table.\r
+* \param cnt Amount of regions to be configured.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) \r
+{\r
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;\r
+ while (cnt > MPU_TYPE_RALIASES) {\r
+ ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);\r
+ table += MPU_TYPE_RALIASES;\r
+ cnt -= MPU_TYPE_RALIASES;\r
+ }\r
+ ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);\r
+}\r
+\r
+#endif\r
--- /dev/null
+/******************************************************************************\r
+ * @file mpu_armv8.h\r
+ * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU\r
+ * @version V5.1.0\r
+ * @date 08. March 2019\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef ARM_MPU_ARMV8_H\r
+#define ARM_MPU_ARMV8_H\r
+\r
+/** \brief Attribute for device memory (outer only) */\r
+#define ARM_MPU_ATTR_DEVICE ( 0U )\r
+\r
+/** \brief Attribute for non-cacheable, normal memory */\r
+#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )\r
+\r
+/** \brief Attribute for normal memory (outer and inner)\r
+* \param NT Non-Transient: Set to 1 for non-transient data.\r
+* \param WB Write-Back: Set to 1 to use write-back update policy.\r
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.\r
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.\r
+*/\r
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \\r
+ (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))\r
+\r
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */\r
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)\r
+\r
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */\r
+#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)\r
+\r
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */\r
+#define ARM_MPU_ATTR_DEVICE_nGRE (2U)\r
+\r
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */\r
+#define ARM_MPU_ATTR_DEVICE_GRE (3U)\r
+\r
+/** \brief Memory Attribute\r
+* \param O Outer memory attributes\r
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes\r
+*/\r
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))\r
+\r
+/** \brief Normal memory non-shareable */\r
+#define ARM_MPU_SH_NON (0U)\r
+\r
+/** \brief Normal memory outer shareable */\r
+#define ARM_MPU_SH_OUTER (2U)\r
+\r
+/** \brief Normal memory inner shareable */\r
+#define ARM_MPU_SH_INNER (3U)\r
+\r
+/** \brief Memory access permissions\r
+* \param RO Read-Only: Set to 1 for read-only memory.\r
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.\r
+*/\r
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))\r
+\r
+/** \brief Region Base Address Register value\r
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.\r
+* \param SH Defines the Shareability domain for this memory region.\r
+* \param RO Read-Only: Set to 1 for a read-only memory region.\r
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.\r
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.\r
+*/\r
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \\r
+ ((BASE & MPU_RBAR_BASE_Msk) | \\r
+ ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \\r
+ ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \\r
+ ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))\r
+\r
+/** \brief Region Limit Address Register value\r
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.\r
+* \param IDX The attribute index to be associated with this memory region.\r
+*/\r
+#define ARM_MPU_RLAR(LIMIT, IDX) \\r
+ ((LIMIT & MPU_RLAR_LIMIT_Msk) | \\r
+ ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \\r
+ (MPU_RLAR_EN_Msk))\r
+\r
+#if defined(MPU_RLAR_PXN_Pos)\r
+ \r
+/** \brief Region Limit Address Register with PXN value\r
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.\r
+* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.\r
+* \param IDX The attribute index to be associated with this memory region.\r
+*/\r
+#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \\r
+ ((LIMIT & MPU_RLAR_LIMIT_Msk) | \\r
+ ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \\r
+ ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \\r
+ (MPU_RLAR_EN_Msk))\r
+ \r
+#endif\r
+\r
+/**\r
+* Struct for a single MPU Region\r
+*/\r
+typedef struct {\r
+ uint32_t RBAR; /*!< Region Base Address Register value */\r
+ uint32_t RLAR; /*!< Region Limit Address Register value */\r
+} ARM_MPU_Region_t;\r
+ \r
+/** Enable the MPU.\r
+* \param MPU_Control Default access permissions for unconfigured regions.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)\r
+{\r
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+ __DSB();\r
+ __ISB();\r
+}\r
+\r
+/** Disable the MPU.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Disable(void)\r
+{\r
+ __DMB();\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;\r
+}\r
+\r
+#ifdef MPU_NS\r
+/** Enable the Non-secure MPU.\r
+* \param MPU_Control Default access permissions for unconfigured regions.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)\r
+{\r
+ MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+ SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+ __DSB();\r
+ __ISB();\r
+}\r
+\r
+/** Disable the Non-secure MPU.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)\r
+{\r
+ __DMB();\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+ SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+ MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;\r
+}\r
+#endif\r
+\r
+/** Set the memory attribute encoding to the given MPU.\r
+* \param mpu Pointer to the MPU to be configured.\r
+* \param idx The attribute index to be set [0-7]\r
+* \param attr The attribute value to be set.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)\r
+{\r
+ const uint8_t reg = idx / 4U;\r
+ const uint32_t pos = ((idx % 4U) * 8U);\r
+ const uint32_t mask = 0xFFU << pos;\r
+ \r
+ if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {\r
+ return; // invalid index\r
+ }\r
+ \r
+ mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));\r
+}\r
+\r
+/** Set the memory attribute encoding.\r
+* \param idx The attribute index to be set [0-7]\r
+* \param attr The attribute value to be set.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)\r
+{\r
+ ARM_MPU_SetMemAttrEx(MPU, idx, attr);\r
+}\r
+\r
+#ifdef MPU_NS\r
+/** Set the memory attribute encoding to the Non-secure MPU.\r
+* \param idx The attribute index to be set [0-7]\r
+* \param attr The attribute value to be set.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)\r
+{\r
+ ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);\r
+}\r
+#endif\r
+\r
+/** Clear and disable the given MPU region of the given MPU.\r
+* \param mpu Pointer to MPU to be used.\r
+* \param rnr Region number to be cleared.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)\r
+{\r
+ mpu->RNR = rnr;\r
+ mpu->RLAR = 0U;\r
+}\r
+\r
+/** Clear and disable the given MPU region.\r
+* \param rnr Region number to be cleared.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)\r
+{\r
+ ARM_MPU_ClrRegionEx(MPU, rnr);\r
+}\r
+\r
+#ifdef MPU_NS\r
+/** Clear and disable the given Non-secure MPU region.\r
+* \param rnr Region number to be cleared.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)\r
+{ \r
+ ARM_MPU_ClrRegionEx(MPU_NS, rnr);\r
+}\r
+#endif\r
+\r
+/** Configure the given MPU region of the given MPU.\r
+* \param mpu Pointer to MPU to be used.\r
+* \param rnr Region number to be configured.\r
+* \param rbar Value for RBAR register.\r
+* \param rlar Value for RLAR register.\r
+*/ \r
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)\r
+{\r
+ mpu->RNR = rnr;\r
+ mpu->RBAR = rbar;\r
+ mpu->RLAR = rlar;\r
+}\r
+\r
+/** Configure the given MPU region.\r
+* \param rnr Region number to be configured.\r
+* \param rbar Value for RBAR register.\r
+* \param rlar Value for RLAR register.\r
+*/ \r
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)\r
+{\r
+ ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);\r
+}\r
+\r
+#ifdef MPU_NS\r
+/** Configure the given Non-secure MPU region.\r
+* \param rnr Region number to be configured.\r
+* \param rbar Value for RBAR register.\r
+* \param rlar Value for RLAR register.\r
+*/ \r
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)\r
+{\r
+ ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); \r
+}\r
+#endif\r
+\r
+/** Memcopy with strictly ordered memory access, e.g. for register targets.\r
+* \param dst Destination data is copied to.\r
+* \param src Source data is copied from.\r
+* \param len Amount of data words to be copied.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)\r
+{\r
+ uint32_t i;\r
+ for (i = 0U; i < len; ++i) \r
+ {\r
+ dst[i] = src[i];\r
+ }\r
+}\r
+\r
+/** Load the given number of MPU regions from a table to the given MPU.\r
+* \param mpu Pointer to the MPU registers to be used.\r
+* \param rnr First region number to be configured.\r
+* \param table Pointer to the MPU configuration table.\r
+* \param cnt Amount of regions to be configured.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \r
+{\r
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;\r
+ if (cnt == 1U) {\r
+ mpu->RNR = rnr;\r
+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);\r
+ } else {\r
+ uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);\r
+ uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;\r
+ \r
+ mpu->RNR = rnrBase;\r
+ while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {\r
+ uint32_t c = MPU_TYPE_RALIASES - rnrOffset;\r
+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);\r
+ table += c;\r
+ cnt -= c;\r
+ rnrOffset = 0U;\r
+ rnrBase += MPU_TYPE_RALIASES;\r
+ mpu->RNR = rnrBase;\r
+ }\r
+ \r
+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);\r
+ }\r
+}\r
+\r
+/** Load the given number of MPU regions from a table.\r
+* \param rnr First region number to be configured.\r
+* \param table Pointer to the MPU configuration table.\r
+* \param cnt Amount of regions to be configured.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \r
+{\r
+ ARM_MPU_LoadEx(MPU, rnr, table, cnt);\r
+}\r
+\r
+#ifdef MPU_NS\r
+/** Load the given number of MPU regions from a table to the Non-secure MPU.\r
+* \param rnr First region number to be configured.\r
+* \param table Pointer to the MPU configuration table.\r
+* \param cnt Amount of regions to be configured.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \r
+{\r
+ ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);\r
+}\r
+#endif\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#include "board.h"\r
+#include <stdint.h>\r
+#include "clock_config.h"\r
+#include "fsl_common.h"\r
+#include "fsl_debug_console.h"\r
+#include "fsl_emc.h"\r
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED\r
+#include "fsl_i2c.h"\r
+#endif /* SDK_I2C_BASED_COMPONENT_USED */\r
+#if defined BOARD_USE_CODEC\r
+#include "fsl_wm8904.h"\r
+#endif\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+/* The SDRAM timing. */\r
+\r
+#define W9812G6JB6I\r
+\r
+#ifdef MTL48LC8M16A2B\r
+#define SDRAM_REFRESHPERIOD_NS (64 * 1000000 / 4096) /* 4096 rows/ 64ms */\r
+#define SDRAM_TRP_NS (18u)\r
+#define SDRAM_TRAS_NS (42u)\r
+#define SDRAM_TSREX_NS (67u)\r
+#define SDRAM_TAPR_NS (18u)\r
+#define SDRAM_TWRDELT_NS (6u)\r
+#define SDRAM_TRC_NS (60u)\r
+#define SDRAM_RFC_NS (60u)\r
+#define SDRAM_XSR_NS (67u)\r
+#define SDRAM_RRD_NS (12u)\r
+#define SDRAM_MRD_NCLK (2u)\r
+#define SDRAM_RAS_NCLK (2u)\r
+#define SDRAM_MODEREG_VALUE (0x23u)\r
+#define SDRAM_DEV_MEMORYMAP (0x09u) /* 128Mbits (8M*16, 4banks, 12 rows, 9 columns)*/\r
+#endif\r
+\r
+#ifdef W9812G6JB6I\r
+#define SDRAM_REFRESHPERIOD_NS (64 * 1000000 / 4096) /* 4096 rows/ 64ms */\r
+#define SDRAM_TRP_NS (20u)\r
+#define SDRAM_TRAS_NS (42u)\r
+#define SDRAM_TSREX_NS (72u)\r
+#define SDRAM_TAPR_NS (18u)\r
+#define SDRAM_TWRDELT_NS (12u)\r
+#define SDRAM_TRC_NS (60u)\r
+#define SDRAM_RFC_NS (60u)\r
+#define SDRAM_XSR_NS (67u)\r
+#define SDRAM_RRD_NS (12u)\r
+#define SDRAM_MRD_NCLK (2u)\r
+#define SDRAM_RAS_NCLK (2u)\r
+#define SDRAM_MODEREG_VALUE (0x23u)\r
+#define SDRAM_DEV_MEMORYMAP (0x09u) /* 128Mbits (8M*16, 4banks, 12 rows, 9 columns)*/\r
+#endif\r
+\r
+/*******************************************************************************\r
+ * Variables\r
+ ******************************************************************************/\r
+\r
+/* Clock rate on the CLKIN pin */\r
+const uint32_t ExtClockIn = BOARD_EXTCLKINRATE;\r
+\r
+/*******************************************************************************\r
+ * Code\r
+ ******************************************************************************/\r
+/* Initialize debug console. */\r
+status_t BOARD_InitDebugConsole(void)\r
+{\r
+#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART))\r
+ status_t result;\r
+ uint8_t instance = BOARD_DEBUG_UART_INSTANCE;\r
+\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+ if (BOARD_DEBUG_UART_TYPE == kSerialPort_UsbCdc)\r
+ {\r
+ instance = kSerialManager_UsbControllerLpcIp3511Hs0;\r
+ }\r
+#endif\r
+\r
+ /* attach 12 MHz clock to FLEXCOMM0 (debug console) */\r
+ CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);\r
+ RESET_PeripheralReset(BOARD_DEBUG_UART_RST);\r
+ result = DbgConsole_Init(instance, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, BOARD_DEBUG_UART_CLK_FREQ);\r
+ assert(kStatus_Success == result);\r
+ return result;\r
+#else\r
+ return kStatus_Success;\r
+#endif\r
+}\r
+\r
+/* Initialize the external memory. */\r
+void BOARD_InitSDRAM(void)\r
+{\r
+ uint32_t emcFreq;\r
+ emc_basic_config_t basicConfig;\r
+ emc_dynamic_timing_config_t dynTiming;\r
+ emc_dynamic_chip_config_t dynChipConfig;\r
+\r
+ emcFreq = CLOCK_GetEmcClkFreq();\r
+ assert(emcFreq != 0); /* Check the clock of emc */\r
+ /* Basic configuration. */\r
+ basicConfig.endian = kEMC_LittleEndian;\r
+ basicConfig.fbClkSrc = kEMC_IntloopbackEmcclk;\r
+ /* EMC Clock = CPU FREQ/2 here can fit CPU freq from 12M ~ 180M.\r
+ * If you change the divide to 0 and EMC clock is larger than 100M\r
+ * please take refer to emc.dox to adjust EMC clock delay.\r
+ */\r
+ basicConfig.emcClkDiv = 1;\r
+ /* Dynamic memory timing configuration. */\r
+ dynTiming.readConfig = kEMC_Cmddelay;\r
+ dynTiming.refreshPeriod_Nanosec = SDRAM_REFRESHPERIOD_NS;\r
+ dynTiming.tRp_Ns = SDRAM_TRP_NS;\r
+ dynTiming.tRas_Ns = SDRAM_TRAS_NS;\r
+ dynTiming.tSrex_Ns = SDRAM_TSREX_NS;\r
+ dynTiming.tApr_Ns = SDRAM_TAPR_NS;\r
+ dynTiming.tWr_Ns = (1000000000 / emcFreq + SDRAM_TWRDELT_NS); /* one clk + 6ns */\r
+ dynTiming.tDal_Ns = dynTiming.tWr_Ns + dynTiming.tRp_Ns;\r
+ dynTiming.tRc_Ns = SDRAM_TRC_NS;\r
+ dynTiming.tRfc_Ns = SDRAM_RFC_NS;\r
+ dynTiming.tXsr_Ns = SDRAM_XSR_NS;\r
+ dynTiming.tRrd_Ns = SDRAM_RRD_NS;\r
+ dynTiming.tMrd_Nclk = SDRAM_MRD_NCLK;\r
+ /* Dynamic memory chip specific configuration: Chip 0 - W9812G6JB-6I */\r
+ dynChipConfig.chipIndex = 0;\r
+ dynChipConfig.dynamicDevice = kEMC_Sdram;\r
+ dynChipConfig.rAS_Nclk = SDRAM_RAS_NCLK;\r
+ dynChipConfig.sdramModeReg = SDRAM_MODEREG_VALUE;\r
+ dynChipConfig.sdramExtModeReg = 0; /* it has no use for normal sdram */\r
+ dynChipConfig.devAddrMap = SDRAM_DEV_MEMORYMAP;\r
+ /* EMC Basic configuration. */\r
+ EMC_Init(EMC, &basicConfig);\r
+ /* EMC Dynamc memory configuration. */\r
+ EMC_DynamicMemInit(EMC, &dynTiming, &dynChipConfig, 1);\r
+}\r
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED\r
+void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz)\r
+{\r
+ i2c_master_config_t i2cConfig = {0};\r
+\r
+ I2C_MasterGetDefaultConfig(&i2cConfig);\r
+ I2C_MasterInit(base, &i2cConfig, clkSrc_Hz);\r
+}\r
+\r
+status_t BOARD_I2C_Send(I2C_Type *base,\r
+ uint8_t deviceAddress,\r
+ uint32_t subAddress,\r
+ uint8_t subaddressSize,\r
+ uint8_t *txBuff,\r
+ uint8_t txBuffSize)\r
+{\r
+ i2c_master_transfer_t masterXfer;\r
+\r
+ /* Prepare transfer structure. */\r
+ masterXfer.slaveAddress = deviceAddress;\r
+ masterXfer.direction = kI2C_Write;\r
+ masterXfer.subaddress = subAddress;\r
+ masterXfer.subaddressSize = subaddressSize;\r
+ masterXfer.data = txBuff;\r
+ masterXfer.dataSize = txBuffSize;\r
+ masterXfer.flags = kI2C_TransferDefaultFlag;\r
+\r
+ return I2C_MasterTransferBlocking(base, &masterXfer);\r
+}\r
+\r
+status_t BOARD_I2C_Receive(I2C_Type *base,\r
+ uint8_t deviceAddress,\r
+ uint32_t subAddress,\r
+ uint8_t subaddressSize,\r
+ uint8_t *rxBuff,\r
+ uint8_t rxBuffSize)\r
+{\r
+ i2c_master_transfer_t masterXfer;\r
+\r
+ /* Prepare transfer structure. */\r
+ masterXfer.slaveAddress = deviceAddress;\r
+ masterXfer.subaddress = subAddress;\r
+ masterXfer.subaddressSize = subaddressSize;\r
+ masterXfer.data = rxBuff;\r
+ masterXfer.dataSize = rxBuffSize;\r
+ masterXfer.direction = kI2C_Read;\r
+ masterXfer.flags = kI2C_TransferDefaultFlag;\r
+\r
+ return I2C_MasterTransferBlocking(base, &masterXfer);\r
+}\r
+\r
+void BOARD_Accel_I2C_Init(void)\r
+{\r
+ BOARD_I2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);\r
+}\r
+\r
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)\r
+{\r
+ uint8_t data = (uint8_t)txBuff;\r
+\r
+ return BOARD_I2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);\r
+}\r
+\r
+status_t BOARD_Accel_I2C_Receive(\r
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)\r
+{\r
+ return BOARD_I2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);\r
+}\r
+\r
+void BOARD_Codec_I2C_Init(void)\r
+{\r
+ BOARD_I2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);\r
+}\r
+\r
+status_t BOARD_Codec_I2C_Send(\r
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)\r
+{\r
+ return BOARD_I2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,\r
+ txBuffSize);\r
+}\r
+\r
+status_t BOARD_Codec_I2C_Receive(\r
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)\r
+{\r
+ return BOARD_I2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);\r
+}\r
+#endif /* SDK_I2C_BASED_COMPONENT_USED */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#ifndef _BOARD_H_\r
+#define _BOARD_H_\r
+\r
+#include "clock_config.h"\r
+#include "fsl_common.h"\r
+#include "fsl_gpio.h"\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+/*! @brief The board name */\r
+#define BOARD_NAME "LPC54018-IoT-Module"\r
+\r
+#define BOARD_EXTCLKINRATE (0)\r
+\r
+/*! @brief The UART to use for debug messages. */\r
+/* TODO: rename UART to USART */\r
+#ifndef BOARD_DEBUG_UART_TYPE\r
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart\r
+#endif\r
+\r
+#define BOARD_DEBUG_UART_BASEADDR (uint32_t) USART0\r
+#define BOARD_DEBUG_UART_INSTANCE 0U\r
+#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetFlexCommClkFreq(0U)\r
+#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM0\r
+#define BOARD_DEBUG_UART_RST kFC0_RST_SHIFT_RSTn\r
+#define BOARD_UART_IRQ_HANDLER FLEXCOMM0_IRQHandler\r
+#define BOARD_UART_IRQ FLEXCOMM0_IRQn\r
+/* TODO: obsolete */\r
+#define BOARD_DEBUG_SPI_CLK_FREQ 12000000\r
+\r
+#ifndef BOARD_DEBUG_UART_BAUDRATE\r
+#define BOARD_DEBUG_UART_BAUDRATE 115200\r
+#endif /* BOARD_DEBUG_UART_BAUDRATE */\r
+\r
+#define BOARD_ACCEL_I2C_BASEADDR I2C2\r
+#define BOARD_ACCEL_I2C_CLOCK_FREQ 12000000\r
+\r
+#define BOARD_CODEC_I2C_BASEADDR I2C2\r
+#define BOARD_CODEC_I2C_INSTANCE 2U\r
+#define BOARD_CODEC_I2C_CLOCK_FREQ 12000000\r
+\r
+/*! @brief The ENET PHY address. */\r
+#define BOARD_ENET0_PHY_ADDRESS (0x00U) /* Phy address of enet port 0. */\r
+\r
+#ifndef BOARD_LED1_GPIO\r
+#define BOARD_LED1_GPIO GPIO\r
+#endif\r
+#define BOARD_LED1_GPIO_PORT 3U\r
+#ifndef BOARD_LED1_GPIO_PIN\r
+#define BOARD_LED1_GPIO_PIN 14U\r
+#endif\r
+\r
+#ifndef BOARD_LED2_GPIO\r
+#define BOARD_LED2_GPIO GPIO\r
+#endif\r
+#define BOARD_LED2_GPIO_PORT 3U\r
+#ifndef BOARD_LED2_GPIO_PIN\r
+#define BOARD_LED2_GPIO_PIN 3U\r
+#endif\r
+#ifndef BOARD_LED3_GPIO\r
+#define BOARD_LED3_GPIO GPIO\r
+#endif\r
+#define BOARD_LED3_GPIO_PORT 3U\r
+#ifndef BOARD_LED3_GPIO_PIN\r
+#define BOARD_LED3_GPIO_PIN 13U\r
+#endif\r
+\r
+#ifndef BOARD_SW1_GPIO\r
+#define BOARD_SW1_GPIO GPIO\r
+#endif\r
+#define BOARD_SW1_GPIO_PORT 0U\r
+#ifndef BOARD_SW1_GPIO_PIN\r
+#define BOARD_SW1_GPIO_PIN 4U\r
+#endif\r
+#define BOARD_SW1_NAME "SW1"\r
+#define BOARD_SW3_IRQ PIN_INT0_IRQn\r
+#define BOARD_SW3_IRQ_HANDLER PIN_INT0_IRQHandler\r
+\r
+#ifndef BOARD_SW2_GPIO\r
+#define BOARD_SW2_GPIO GPIO\r
+#endif\r
+#define BOARD_SW2_GPIO_PORT 0U\r
+#ifndef BOARD_SW2_GPIO_PIN\r
+#define BOARD_SW2_GPIO_PIN 6U\r
+#endif\r
+#define BOARD_SW2_NAME "SW2"\r
+#define BOARD_SW2_IRQ PIN_INT0_IRQn\r
+#define BOARD_SW2_IRQ_HANDLER PIN_INT0_IRQHandler\r
+\r
+#ifndef BOARD_SW3_GPIO\r
+#define BOARD_SW3_GPIO GPIO\r
+#endif\r
+#define BOARD_SW3_GPIO_PORT 0U\r
+#ifndef BOARD_SW3_GPIO_PIN\r
+#define BOARD_SW3_GPIO_PIN 5U\r
+#endif\r
+#define BOARD_SW3_NAME "SW3"\r
+#define BOARD_SW3_IRQ PIN_INT0_IRQn\r
+#define BOARD_SW3_IRQ_HANDLER PIN_INT0_IRQHandler\r
+#define BOARD_SW3_GPIO_PININT_INDEX 0\r
+\r
+#ifndef BOARD_SW4_GPIO\r
+#define BOARD_SW4_GPIO GPIO\r
+#endif\r
+#ifndef BOARD_SW4_GPIO_PORT\r
+#define BOARD_SW4_GPIO_PORT 0U\r
+#endif\r
+#ifndef BOARD_SW4_GPIO_PIN\r
+#define BOARD_SW4_GPIO_PIN 4U\r
+#endif\r
+#define BOARD_SW4_NAME "SW4"\r
+#define BOARD_SW4_IRQ PIN_INT0_IRQn\r
+#define BOARD_SW4_IRQ_HANDLER PIN_INT0_IRQHandler\r
+#define BOARD_SW4_GPIO_PININT_INDEX 0\r
+\r
+#ifndef BOARD_SW5_GPIO\r
+#define BOARD_SW5_GPIO GPIO\r
+#endif\r
+#ifndef BOARD_SW5_GPIO_PORT\r
+#define BOARD_SW5_GPIO_PORT 1U\r
+#endif\r
+#ifndef BOARD_SW5_GPIO_PIN\r
+#define BOARD_SW5_GPIO_PIN 1U\r
+#endif\r
+#define BOARD_SW5_NAME "SW5"\r
+#define BOARD_SW5_IRQ PIN_INT1_IRQn\r
+#define BOARD_SW5_IRQ_HANDLER PIN_INT1_IRQHandler\r
+#define BOARD_SW5_GPIO_PININT_INDEX 0\r
+\r
+#define BOARD_SDIF_BASEADDR SDIF\r
+#define BOARD_SDIF_CLK_FREQ CLOCK_GetSdioClkFreq()\r
+#define BOARD_SDIF_CLK_ATTACH kMAIN_CLK_to_SDIO_CLK\r
+#define BOARD_SDIF_IRQ SDIO_IRQn\r
+\r
+#define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360\r
+#define BOARD_SD_CARD_DETECT_PIN 10\r
+#define BOARD_SD_CARD_DETECT_PORT 2\r
+#define BOARD_SD_CARD_DETECT_GPIO GPIO\r
+#define BOARD_SD_DETECT_TYPE kSDMMCHOST_DetectCardByHostCD\r
+\r
+#define BOARD_SDIF_CD_GPIO_INIT() \\r
+ { \\r
+ CLOCK_EnableClock(kCLOCK_Gpio2); \\r
+ GPIO_PinInit(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN, \\r
+ &(gpio_pin_config_t){kGPIO_DigitalInput, 0U}); \\r
+ }\r
+#define BOARD_SDIF_CD_STATUS() \\r
+ GPIO_PinRead(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN)\r
+\r
+/* Board led color mapping */\r
+#define LOGIC_LED_ON 0U\r
+#define LOGIC_LED_OFF 1U\r
+\r
+#define LED1_INIT(output) \\r
+ GPIO_PinInit(BOARD_LED1_GPIO, BOARD_LED1_GPIO_PORT, BOARD_LED1_GPIO_PIN, \\r
+ &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED1 */\r
+#define LED1_ON() \\r
+ GPIO_PortClear(BOARD_LED1_GPIO, BOARD_LED1_GPIO_PORT, 1U << BOARD_LED1_GPIO_PIN) /*!< Turn on target LED1 */\r
+#define LED1_OFF() \\r
+ GPIO_PortSet(BOARD_LED1_GPIO, BOARD_LED1_GPIO_PORT, 1U << BOARD_LED1_GPIO_PIN) /*!< Turn off target LED1 */\r
+#define LED1_TOGGLE() \\r
+ GPIO_PortToggle(BOARD_LED1_GPIO, BOARD_LED1_GPIO_PORT, 1U << BOARD_LED1_GPIO_PIN) /*!< Toggle on target LED1 */\r
+#define LED2_INIT(output) \\r
+ GPIO_PinInit(BOARD_LED2_GPIO, BOARD_LED2_GPIO_PORT, BOARD_LED2_GPIO_PIN, \\r
+ &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED2 */\r
+#define LED2_ON() \\r
+ GPIO_PortClear(BOARD_LED2_GPIO, BOARD_LED2_GPIO_PORT, 1U << BOARD_LED2_GPIO_PIN) /*!< Turn on target LED2 */\r
+#define LED2_OFF() \\r
+ GPIO_PortSet(BOARD_LED2_GPIO, BOARD_LED2_GPIO_PORT, 1U << BOARD_LED2_GPIO_PIN) /*!< Turn off target LED2 */\r
+#define LED2_TOGGLE() \\r
+ GPIO_PortToggle(BOARD_LED2_GPIO, BOARD_LED2_GPIO_PORT, 1U << BOARD_LED2_GPIO_PIN) /*!< Toggle on target LED2 */\r
+\r
+#define LED3_INIT(output) \\r
+ GPIO_PinInit(BOARD_LED3_GPIO, BOARD_LED3_GPIO_PORT, BOARD_LED3_GPIO_PIN, \\r
+ &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED3 */\r
+#define LED3_ON() \\r
+ GPIO_PortClear(BOARD_LED3_GPIO, BOARD_LED3_GPIO_PORT, 1U << BOARD_LED3_GPIO_PIN) /*!< Turn on target LED3 */\r
+#define LED3_OFF() \\r
+ GPIO_PortSet(BOARD_LED3_GPIO, BOARD_LED3_GPIO_PORT, 1U << BOARD_LED3_GPIO_PIN) /*!< Turn off target LED3 */\r
+#define LED3_TOGGLE() \\r
+ GPIO_PortToggle(BOARD_LED3_GPIO, BOARD_LED3_GPIO_PORT, 1U << BOARD_LED3_GPIO_PIN) /*!< Toggle on target LED3 */\r
+\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif /* __cplusplus */\r
+\r
+/*******************************************************************************\r
+ * API\r
+ ******************************************************************************/\r
+\r
+status_t BOARD_InitDebugConsole(void);\r
+void BOARD_InitSDRAM(void);\r
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED\r
+void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz);\r
+status_t BOARD_I2C_Send(I2C_Type *base,\r
+ uint8_t deviceAddress,\r
+ uint32_t subAddress,\r
+ uint8_t subaddressSize,\r
+ uint8_t *txBuff,\r
+ uint8_t txBuffSize);\r
+status_t BOARD_I2C_Receive(I2C_Type *base,\r
+ uint8_t deviceAddress,\r
+ uint32_t subAddress,\r
+ uint8_t subaddressSize,\r
+ uint8_t *rxBuff,\r
+ uint8_t rxBuffSize);\r
+void BOARD_Accel_I2C_Init(void);\r
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);\r
+status_t BOARD_Accel_I2C_Receive(\r
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);\r
+void BOARD_Codec_I2C_Init(void);\r
+status_t BOARD_Codec_I2C_Send(\r
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);\r
+status_t BOARD_Codec_I2C_Receive(\r
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);\r
+#endif /* SDK_I2C_BASED_COMPONENT_USED */\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* _BOARD_H_ */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2017,2019 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+/***********************************************************************************************************************\r
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file\r
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.\r
+ **********************************************************************************************************************/\r
+/*\r
+ * How to set up clock using clock driver functions:\r
+ *\r
+ * 1. Setup clock sources.\r
+ *\r
+ * 2. Setup voltage for the fastest of the clock outputs\r
+ *\r
+ * 3. Set up wait states of the flash.\r
+ *\r
+ * 4. Set up all dividers.\r
+ *\r
+ * 5. Set up all selectors to provide selected clocks.\r
+ */\r
+\r
+/* clang-format off */\r
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************\r
+!!GlobalInfo\r
+product: Clocks v7.0\r
+processor: LPC54018\r
+package_id: LPC54018JET180\r
+mcu_data: ksdk2_0\r
+processor_version: 0.7.1\r
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/\r
+/* clang-format on */\r
+\r
+#include "fsl_power.h"\r
+#include "fsl_clock.h"\r
+#include "clock_config.h"\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/*******************************************************************************\r
+ * Variables\r
+ ******************************************************************************/\r
+/* System clock frequency. */\r
+extern uint32_t SystemCoreClock;\r
+\r
+/*******************************************************************************\r
+ ************************ BOARD_InitBootClocks function ************************\r
+ ******************************************************************************/\r
+void BOARD_InitBootClocks(void)\r
+{\r
+ BOARD_BootClockPLL180M();\r
+}\r
+\r
+/*******************************************************************************\r
+ ******************** Configuration BOARD_BootClockFRO12M **********************\r
+ ******************************************************************************/\r
+/* clang-format off */\r
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************\r
+!!Configuration\r
+name: BOARD_BootClockFRO12M\r
+outputs:\r
+- {id: FRO12M_clock.outFreq, value: 12 MHz}\r
+- {id: FROHF_clock.outFreq, value: 48 MHz}\r
+- {id: MAIN_clock.outFreq, value: 12 MHz}\r
+- {id: System_clock.outFreq, value: 12 MHz}\r
+settings:\r
+- {id: SYSCON.EMCCLKDIV.scale, value: '1', locked: true}\r
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/\r
+/* clang-format on */\r
+\r
+/*******************************************************************************\r
+ * Variables for BOARD_BootClockFRO12M configuration\r
+ ******************************************************************************/\r
+/*******************************************************************************\r
+ * Code for BOARD_BootClockFRO12M configuration\r
+ ******************************************************************************/\r
+void BOARD_BootClockFRO12M(void)\r
+{\r
+ /*!< Set up the clock sources */\r
+ /*!< Set up FRO */\r
+ POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */\r
+ CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without\r
+ accidentally being below the voltage for current speed */\r
+ /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)\r
+ before calling this API since this API is implemented in ROM code */\r
+ CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */\r
+ POWER_SetVoltageForFreq(\r
+ 12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */\r
+\r
+ /*!< Set up dividers */\r
+ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */\r
+\r
+ /*!< Set up clock selectors - Attach clocks to the peripheries */\r
+ CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */\r
+ /* Set SystemCoreClock variable. */\r
+ SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;\r
+}\r
+\r
+/*******************************************************************************\r
+ ******************* Configuration BOARD_BootClockFROHF48M *********************\r
+ ******************************************************************************/\r
+/* clang-format off */\r
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************\r
+!!Configuration\r
+name: BOARD_BootClockFROHF48M\r
+outputs:\r
+- {id: FRO12M_clock.outFreq, value: 12 MHz}\r
+- {id: FROHF_clock.outFreq, value: 48 MHz}\r
+- {id: MAIN_clock.outFreq, value: 48 MHz}\r
+- {id: System_clock.outFreq, value: 48 MHz}\r
+settings:\r
+- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}\r
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/\r
+/* clang-format on */\r
+\r
+/*******************************************************************************\r
+ * Variables for BOARD_BootClockFROHF48M configuration\r
+ ******************************************************************************/\r
+/*******************************************************************************\r
+ * Code for BOARD_BootClockFROHF48M configuration\r
+ ******************************************************************************/\r
+void BOARD_BootClockFROHF48M(void)\r
+{\r
+ /*!< Set up the clock sources */\r
+ /*!< Set up FRO */\r
+ POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */\r
+ CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without\r
+ accidentally being below the voltage for current speed */\r
+ POWER_SetVoltageForFreq(\r
+ 48000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */\r
+ /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)\r
+ before calling this API since this API is implemented in ROM code */\r
+ CLOCK_SetupFROClocking(48000000U); /*!< Set up high frequency FRO output to selected frequency */\r
+\r
+ /*!< Set up dividers */\r
+ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */\r
+\r
+ /*!< Set up clock selectors - Attach clocks to the peripheries */\r
+ CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */\r
+ /* Set SystemCoreClock variable. */\r
+ SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;\r
+}\r
+\r
+/*******************************************************************************\r
+ ******************* Configuration BOARD_BootClockFROHF96M *********************\r
+ ******************************************************************************/\r
+/* clang-format off */\r
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************\r
+!!Configuration\r
+name: BOARD_BootClockFROHF96M\r
+outputs:\r
+- {id: FRO12M_clock.outFreq, value: 12 MHz}\r
+- {id: FROHF_clock.outFreq, value: 96 MHz}\r
+- {id: MAIN_clock.outFreq, value: 96 MHz}\r
+- {id: System_clock.outFreq, value: 96 MHz}\r
+settings:\r
+- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}\r
+sources:\r
+- {id: SYSCON.fro_hf.outFreq, value: 96 MHz}\r
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/\r
+/* clang-format on */\r
+\r
+/*******************************************************************************\r
+ * Variables for BOARD_BootClockFROHF96M configuration\r
+ ******************************************************************************/\r
+/*******************************************************************************\r
+ * Code for BOARD_BootClockFROHF96M configuration\r
+ ******************************************************************************/\r
+void BOARD_BootClockFROHF96M(void)\r
+{\r
+ /*!< Set up the clock sources */\r
+ /*!< Set up FRO */\r
+ POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */\r
+ CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without\r
+ accidentally being below the voltage for current speed */\r
+ POWER_SetVoltageForFreq(\r
+ 96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */\r
+ /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)\r
+ before calling this API since this API is implemented in ROM code */\r
+ CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */\r
+\r
+ /*!< Set up dividers */\r
+ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */\r
+\r
+ /*!< Set up clock selectors - Attach clocks to the peripheries */\r
+ CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */\r
+ /* Set SystemCoreClock variable. */\r
+ SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;\r
+}\r
+\r
+/*******************************************************************************\r
+ ******************** Configuration BOARD_BootClockPLL180M *********************\r
+ ******************************************************************************/\r
+/* clang-format off */\r
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************\r
+!!Configuration\r
+name: BOARD_BootClockPLL180M\r
+called_from_default_init: true\r
+outputs:\r
+- {id: FRO12M_clock.outFreq, value: 12 MHz}\r
+- {id: FROHF_clock.outFreq, value: 96 MHz}\r
+- {id: MAIN_clock.outFreq, value: 180 MHz}\r
+- {id: SYSPLL_clock.outFreq, value: 180 MHz}\r
+- {id: System_clock.outFreq, value: 180 MHz}\r
+- {id: USB0_clock.outFreq, value: 96 MHz}\r
+settings:\r
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL_BYPASS}\r
+- {id: SYSCON.M_MULT.scale, value: '30', locked: true}\r
+- {id: SYSCON.N_DIV.scale, value: '1', locked: true}\r
+- {id: SYSCON.PDEC.scale, value: '2', locked: true}\r
+- {id: SYSCON.USB0CLKSEL.sel, value: SYSCON.fro_hf}\r
+- {id: SYSCON_PDRUNCFG0_PDEN_SYS_PLL_CFG, value: Power_up}\r
+sources:\r
+- {id: SYSCON._clk_in.outFreq, value: 12 MHz, enabled: true}\r
+- {id: SYSCON.fro_hf.outFreq, value: 96 MHz}\r
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/\r
+/* clang-format on */\r
+\r
+/*******************************************************************************\r
+ * Variables for BOARD_BootClockPLL180M configuration\r
+ ******************************************************************************/\r
+/*******************************************************************************\r
+ * Code for BOARD_BootClockPLL180M configuration\r
+ ******************************************************************************/\r
+void BOARD_BootClockPLL180M(void)\r
+{\r
+ /*!< Set up the clock sources */\r
+ /*!< Set up FRO */\r
+ POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */\r
+ CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without\r
+ accidentally being below the voltage for current speed */\r
+ POWER_DisablePD(kPDRUNCFG_PD_SYS_OSC); /*!< Enable System Oscillator Power */\r
+ SYSCON->SYSOSCCTRL = ((SYSCON->SYSOSCCTRL & ~SYSCON_SYSOSCCTRL_FREQRANGE_MASK) |\r
+ SYSCON_SYSOSCCTRL_FREQRANGE(0U)); /*!< Set system oscillator range */\r
+ POWER_SetVoltageForFreq(\r
+ 180000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */\r
+ /*!< Set up SYS PLL */\r
+ const pll_setup_t pllSetup = {\r
+ .pllctrl = SYSCON_SYSPLLCTRL_SELI(32U) | SYSCON_SYSPLLCTRL_SELP(16U) | SYSCON_SYSPLLCTRL_SELR(0U),\r
+ .pllmdec = (SYSCON_SYSPLLMDEC_MDEC(8191U)),\r
+ .pllndec = (SYSCON_SYSPLLNDEC_NDEC(770U)),\r
+ .pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)),\r
+ .pllRate = 180000000U,\r
+ .flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP};\r
+ CLOCK_AttachClk(kFRO12M_to_SYS_PLL); /*!< Set sys pll clock source*/\r
+ CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired value */\r
+ /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)\r
+ before calling this API since this API is implemented in ROM code */\r
+ CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */\r
+\r
+ /*!< Set up dividers */\r
+ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */\r
+ CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 0U, true); /*!< Reset USB0CLKDIV divider counter and halt it */\r
+ CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Set USB0CLKDIV divider to value 1 */\r
+\r
+ /*!< Set up clock selectors - Attach clocks to the peripheries */\r
+ CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch MAIN_CLK to SYS_PLL */\r
+ CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); /*!< Switch USB0_CLK to FRO_HF */\r
+ SYSCON->MAINCLKSELA =\r
+ ((SYSCON->MAINCLKSELA & ~SYSCON_MAINCLKSELA_SEL_MASK) |\r
+ SYSCON_MAINCLKSELA_SEL(0U)); /*!< Switch MAINCLKSELA to FRO12M even it is not used for MAINCLKSELB */\r
+ /* Set SystemCoreClock variable. */\r
+ SystemCoreClock = BOARD_BOOTCLOCKPLL180M_CORE_CLOCK;\r
+}\r
--- /dev/null
+/*\r
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2017,2019 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+/***********************************************************************************************************************\r
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file\r
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.\r
+ **********************************************************************************************************************/\r
+\r
+#ifndef _CLOCK_CONFIG_H_\r
+#define _CLOCK_CONFIG_H_\r
+\r
+#include "fsl_common.h"\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+#define BOARD_XTAL0_CLK_HZ 12000000U /*!< Board xtal0 frequency in Hz */\r
+#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */\r
+\r
+/*******************************************************************************\r
+ ************************ BOARD_InitBootClocks function ************************\r
+ ******************************************************************************/\r
+\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif /* __cplusplus*/\r
+\r
+/*!\r
+ * @brief This function executes default configuration of clocks.\r
+ *\r
+ */\r
+void BOARD_InitBootClocks(void);\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif /* __cplusplus*/\r
+\r
+/*******************************************************************************\r
+ ******************** Configuration BOARD_BootClockFRO12M **********************\r
+ ******************************************************************************/\r
+/*******************************************************************************\r
+ * Definitions for BOARD_BootClockFRO12M configuration\r
+ ******************************************************************************/\r
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency:12000000Hz */\r
+\r
+/*******************************************************************************\r
+ * API for BOARD_BootClockFRO12M configuration\r
+ ******************************************************************************/\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif /* __cplusplus*/\r
+\r
+/*!\r
+ * @brief This function executes configuration of clocks.\r
+ *\r
+ */\r
+void BOARD_BootClockFRO12M(void);\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif /* __cplusplus*/\r
+\r
+/*******************************************************************************\r
+ ******************* Configuration BOARD_BootClockFROHF48M *********************\r
+ ******************************************************************************/\r
+/*******************************************************************************\r
+ * Definitions for BOARD_BootClockFROHF48M configuration\r
+ ******************************************************************************/\r
+#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK 48000000U /*!< Core clock frequency:48000000Hz */\r
+\r
+/*******************************************************************************\r
+ * API for BOARD_BootClockFROHF48M configuration\r
+ ******************************************************************************/\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif /* __cplusplus*/\r
+\r
+/*!\r
+ * @brief This function executes configuration of clocks.\r
+ *\r
+ */\r
+void BOARD_BootClockFROHF48M(void);\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif /* __cplusplus*/\r
+\r
+/*******************************************************************************\r
+ ******************* Configuration BOARD_BootClockFROHF96M *********************\r
+ ******************************************************************************/\r
+/*******************************************************************************\r
+ * Definitions for BOARD_BootClockFROHF96M configuration\r
+ ******************************************************************************/\r
+#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency:96000000Hz */\r
+\r
+/*******************************************************************************\r
+ * API for BOARD_BootClockFROHF96M configuration\r
+ ******************************************************************************/\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif /* __cplusplus*/\r
+\r
+/*!\r
+ * @brief This function executes configuration of clocks.\r
+ *\r
+ */\r
+void BOARD_BootClockFROHF96M(void);\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif /* __cplusplus*/\r
+\r
+/*******************************************************************************\r
+ ******************** Configuration BOARD_BootClockPLL180M *********************\r
+ ******************************************************************************/\r
+/*******************************************************************************\r
+ * Definitions for BOARD_BootClockPLL180M configuration\r
+ ******************************************************************************/\r
+#define BOARD_BOOTCLOCKPLL180M_CORE_CLOCK 180000000U /*!< Core clock frequency:180000000Hz */\r
+\r
+/*******************************************************************************\r
+ * API for BOARD_BootClockPLL180M configuration\r
+ ******************************************************************************/\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif /* __cplusplus*/\r
+\r
+/*!\r
+ * @brief This function executes configuration of clocks.\r
+ *\r
+ */\r
+void BOARD_BootClockPLL180M(void);\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif /* __cplusplus*/\r
+\r
+#endif /* _CLOCK_CONFIG_H_ */\r
--- /dev/null
+/*\r
+ * Copyright 2017, NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ *\r
+ */\r
+\r
+/*\r
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************\r
+!!GlobalInfo\r
+product: Pins v3.0\r
+processor: LPC54018\r
+package_id: LPC54018JET180\r
+mcu_data: ksdk2_0\r
+processor_version: 0.0.0\r
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********\r
+ */\r
+\r
+#include "fsl_common.h"\r
+#include "fsl_iocon.h"\r
+#include "pin_mux.h"\r
+\r
+/*FUNCTION**********************************************************************\r
+ * \r
+ * Function Name : BOARD_InitBootPins\r
+ * Description : Calls initialization functions.\r
+ * \r
+ *END**************************************************************************/\r
+void BOARD_InitBootPins(void) {\r
+ BOARD_InitPins();\r
+}\r
+\r
+#define IOCON_PIO_DIGITAL_EN 0x0100u /*!< Enables digital function */\r
+#define IOCON_PIO_FUNC1 0x01u /*!< Selects pin function 1 */\r
+#define IOCON_PIO_INPFILT_OFF 0x0200u /*!< Input filter disabled */\r
+#define IOCON_PIO_INV_DI 0x00u /*!< Input function is not inverted */\r
+#define IOCON_PIO_MODE_INACT 0x00u /*!< No addition pin function */\r
+#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!< Open drain is disabled */\r
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!< Standard mode, output slew rate control is enabled */\r
+#define PIN29_IDX 29u /*!< Pin number for pin 29 in a port 0 */\r
+#define PIN30_IDX 30u /*!< Pin number for pin 30 in a port 0 */\r
+#define PORT0_IDX 0u /*!< Port index */\r
+\r
+/*\r
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************\r
+BOARD_InitPins:\r
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}\r
+- pin_list:\r
+ - {pin_num: B13, peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI/CTIMER2_MAT3/SCT0_OUT8/TRACEDATA(2), mode: inactive, invert: disabled,\r
+ glitch_filter: disabled, slew_rate: standard, open_drain: disabled}\r
+ - {pin_num: A2, peripheral: FLEXCOMM0, signal: TXD_SCL_MISO, pin_signal: PIO0_30/FC0_TXD_SCL_MISO/CTIMER0_MAT0/SCT0_OUT9/TRACEDATA(1), mode: inactive, invert: disabled,\r
+ glitch_filter: disabled, slew_rate: standard, open_drain: disabled}\r
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********\r
+ */\r
+\r
+/*FUNCTION**********************************************************************\r
+ *\r
+ * Function Name : BOARD_InitPins\r
+ *\r
+ *END**************************************************************************/\r
+void BOARD_InitPins(void) { /* Function assigned for the Core #0 (ARM Cortex-M4) */\r
+ CLOCK_EnableClock(kCLOCK_Iocon); /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */\r
+\r
+ const uint32_t port0_pin29_config = (\r
+ IOCON_PIO_FUNC1 | /* Pin is configured as FC0_RXD_SDA_MOSI */\r
+ IOCON_PIO_MODE_INACT | /* No addition pin function */\r
+ IOCON_PIO_INV_DI | /* Input function is not inverted */\r
+ IOCON_PIO_DIGITAL_EN | /* Enables digital function */\r
+ IOCON_PIO_INPFILT_OFF | /* Input filter disabled */\r
+ IOCON_PIO_SLEW_STANDARD | /* Standard mode, output slew rate control is enabled */\r
+ IOCON_PIO_OPENDRAIN_DI /* Open drain is disabled */\r
+ );\r
+ IOCON_PinMuxSet(IOCON, PORT0_IDX, PIN29_IDX, port0_pin29_config); /* PORT0 PIN29 (coords: B13) is configured as FC0_RXD_SDA_MOSI */\r
+ const uint32_t port0_pin30_config = (\r
+ IOCON_PIO_FUNC1 | /* Pin is configured as FC0_TXD_SCL_MISO */\r
+ IOCON_PIO_MODE_INACT | /* No addition pin function */\r
+ IOCON_PIO_INV_DI | /* Input function is not inverted */\r
+ IOCON_PIO_DIGITAL_EN | /* Enables digital function */\r
+ IOCON_PIO_INPFILT_OFF | /* Input filter disabled */\r
+ IOCON_PIO_SLEW_STANDARD | /* Standard mode, output slew rate control is enabled */\r
+ IOCON_PIO_OPENDRAIN_DI /* Open drain is disabled */\r
+ );\r
+ IOCON_PinMuxSet(IOCON, PORT0_IDX, PIN30_IDX, port0_pin30_config); /* PORT0 PIN30 (coords: A2) is configured as FC0_TXD_SCL_MISO */\r
+}\r
+\r
+/*******************************************************************************\r
+ * EOF\r
+ ******************************************************************************/\r
--- /dev/null
+/*\r
+ * Copyright 2017, NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ *\r
+ */\r
+\r
+#ifndef _PIN_MUX_H_\r
+#define _PIN_MUX_H_\r
+\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/*! @brief Direction type */\r
+typedef enum _pin_mux_direction\r
+{\r
+ kPIN_MUX_DirectionInput = 0U, /* Input direction */\r
+ kPIN_MUX_DirectionOutput = 1U, /* Output direction */\r
+ kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */\r
+} pin_mux_direction_t;\r
+\r
+/*!\r
+ * @addtogroup pin_mux\r
+ * @{\r
+ */\r
+\r
+/*******************************************************************************\r
+ * API\r
+ ******************************************************************************/\r
+\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif\r
+\r
+/*!\r
+ * @brief Calls initialization functions.\r
+ *\r
+ */\r
+void BOARD_InitBootPins(void);\r
+\r
+/*!\r
+ *\r
+ */\r
+void BOARD_InitPins(void); /* Function assigned for the Cortex-M4F */\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif\r
+\r
+/*!\r
+ * @}\r
+ */\r
+#endif /* _PIN_MUX_H_ */\r
+\r
+/*******************************************************************************\r
+ * EOF\r
+ ******************************************************************************/\r
--- /dev/null
+/*\r
+ * Copyright 2018-2019 NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+/*! *********************************************************************************\r
+*************************************************************************************\r
+* Include\r
+*************************************************************************************\r
+********************************************************************************** */\r
+#include "fsl_common.h"\r
+#include "generic_list.h"\r
+\r
+static list_status_t LIST_Scan(list_handle_t list, list_element_handle_t newElement)\r
+{\r
+ list_element_handle_t element = list->head;\r
+\r
+ while (element != NULL)\r
+ {\r
+ if (element == newElement)\r
+ {\r
+ return kLIST_DuplicateError;\r
+ }\r
+ element = element->next;\r
+ }\r
+ return kLIST_Ok;\r
+}\r
+\r
+/*! *********************************************************************************\r
+*************************************************************************************\r
+* Public functions\r
+*************************************************************************************\r
+********************************************************************************** */\r
+/*! *********************************************************************************\r
+ * \brief Initialises the list descriptor.\r
+ *\r
+ * \param[in] list - LIST_ handle to init.\r
+ * max - Maximum number of elements in list. 0 for unlimited.\r
+ *\r
+ * \return void.\r
+ *\r
+ * \pre\r
+ *\r
+ * \post\r
+ *\r
+ * \remarks\r
+ *\r
+ ********************************************************************************** */\r
+void LIST_Init(list_handle_t list, uint32_t max)\r
+{\r
+ list->head = NULL;\r
+ list->tail = NULL;\r
+ list->max = (uint16_t)max;\r
+ list->size = 0;\r
+}\r
+\r
+/*! *********************************************************************************\r
+ * \brief Gets the list that contains the given element.\r
+ *\r
+ * \param[in] element - Handle of the element.\r
+ *\r
+ * \return NULL if element is orphan.\r
+ * Handle of the list the element is inserted into.\r
+ *\r
+ * \pre\r
+ *\r
+ * \post\r
+ *\r
+ * \remarks\r
+ *\r
+ ********************************************************************************** */\r
+list_handle_t LIST_GetList(list_element_handle_t element)\r
+{\r
+ return element->list;\r
+}\r
+\r
+/*! *********************************************************************************\r
+ * \brief Links element to the tail of the list.\r
+ *\r
+ * \param[in] list - ID of list to insert into.\r
+ * element - element to add\r
+ *\r
+ * \return kLIST_Full if list is full.\r
+ * kLIST_Ok if insertion was successful.\r
+ *\r
+ * \pre\r
+ *\r
+ * \post\r
+ *\r
+ * \remarks\r
+ *\r
+ ********************************************************************************** */\r
+list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element)\r
+{\r
+ uint32_t regPrimask = DisableGlobalIRQ();\r
+\r
+ if ((list->max != 0U) && (list->max == list->size))\r
+ {\r
+ EnableGlobalIRQ(regPrimask);\r
+ return kLIST_Full;\r
+ }\r
+\r
+ if (kLIST_DuplicateError == LIST_Scan(list, element))\r
+ {\r
+ EnableGlobalIRQ(regPrimask);\r
+ return kLIST_DuplicateError;\r
+ }\r
+\r
+ if (list->size == 0U)\r
+ {\r
+ list->head = element;\r
+ }\r
+ else\r
+ {\r
+ list->tail->next = element;\r
+ }\r
+ element->prev = list->tail;\r
+ element->next = NULL;\r
+ element->list = list;\r
+ list->tail = element;\r
+ list->size++;\r
+\r
+ EnableGlobalIRQ(regPrimask);\r
+ return kLIST_Ok;\r
+}\r
+\r
+/*! *********************************************************************************\r
+ * \brief Links element to the head of the list.\r
+ *\r
+ * \param[in] list - ID of list to insert into.\r
+ * element - element to add\r
+ *\r
+ * \return kLIST_Full if list is full.\r
+ * kLIST_Ok if insertion was successful.\r
+ *\r
+ * \pre\r
+ *\r
+ * \post\r
+ *\r
+ * \remarks\r
+ *\r
+ ********************************************************************************** */\r
+list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element)\r
+{\r
+ uint32_t regPrimask = DisableGlobalIRQ();\r
+\r
+ if ((list->max != 0U) && (list->max == list->size))\r
+ {\r
+ EnableGlobalIRQ(regPrimask);\r
+ return kLIST_Full;\r
+ }\r
+\r
+ if (kLIST_DuplicateError == LIST_Scan(list, element))\r
+ {\r
+ EnableGlobalIRQ(regPrimask);\r
+ return kLIST_DuplicateError;\r
+ }\r
+\r
+ if (list->size == 0U)\r
+ {\r
+ list->tail = element;\r
+ }\r
+ else\r
+ {\r
+ list->head->prev = element;\r
+ }\r
+ element->next = list->head;\r
+ element->prev = NULL;\r
+ element->list = list;\r
+ list->head = element;\r
+ list->size++;\r
+\r
+ EnableGlobalIRQ(regPrimask);\r
+ return kLIST_Ok;\r
+}\r
+\r
+/*! *********************************************************************************\r
+ * \brief Unlinks element from the head of the list.\r
+ *\r
+ * \param[in] list - ID of list to remove from.\r
+ *\r
+ * \return NULL if list is empty.\r
+ * ID of removed element(pointer) if removal was successful.\r
+ *\r
+ * \pre\r
+ *\r
+ * \post\r
+ *\r
+ * \remarks\r
+ *\r
+ ********************************************************************************** */\r
+list_element_handle_t LIST_RemoveHead(list_handle_t list)\r
+{\r
+ list_element_handle_t element;\r
+\r
+ uint32_t regPrimask = DisableGlobalIRQ();\r
+\r
+ if ((NULL == list) || (list->size == 0U))\r
+ {\r
+ EnableGlobalIRQ(regPrimask);\r
+ return NULL; /*LIST_ is empty*/\r
+ }\r
+\r
+ element = list->head;\r
+ list->size--;\r
+ if (list->size == 0U)\r
+ {\r
+ list->tail = NULL;\r
+ }\r
+ else\r
+ {\r
+ element->next->prev = NULL;\r
+ }\r
+ list->head = element->next; /*Is NULL if element is head*/\r
+ element->list = NULL;\r
+\r
+ EnableGlobalIRQ(regPrimask);\r
+ return element;\r
+}\r
+\r
+/*! *********************************************************************************\r
+ * \brief Gets head element ID.\r
+ *\r
+ * \param[in] list - ID of list.\r
+ *\r
+ * \return NULL if list is empty.\r
+ * ID of head element if list is not empty.\r
+ *\r
+ * \pre\r
+ *\r
+ * \post\r
+ *\r
+ * \remarks\r
+ *\r
+ ********************************************************************************** */\r
+list_element_handle_t LIST_GetHead(list_handle_t list)\r
+{\r
+ return list->head;\r
+}\r
+\r
+/*! *********************************************************************************\r
+ * \brief Gets next element ID.\r
+ *\r
+ * \param[in] element - ID of the element.\r
+ *\r
+ * \return NULL if element is tail.\r
+ * ID of next element if exists.\r
+ *\r
+ * \pre\r
+ *\r
+ * \post\r
+ *\r
+ * \remarks\r
+ *\r
+ ********************************************************************************** */\r
+list_element_handle_t LIST_GetNext(list_element_handle_t element)\r
+{\r
+ return element->next;\r
+}\r
+\r
+/*! *********************************************************************************\r
+ * \brief Gets previous element ID.\r
+ *\r
+ * \param[in] element - ID of the element.\r
+ *\r
+ * \return NULL if element is head.\r
+ * ID of previous element if exists.\r
+ *\r
+ * \pre\r
+ *\r
+ * \post\r
+ *\r
+ * \remarks\r
+ *\r
+ ********************************************************************************** */\r
+list_element_handle_t LIST_GetPrev(list_element_handle_t element)\r
+{\r
+ return element->prev;\r
+}\r
+\r
+/*! *********************************************************************************\r
+ * \brief Unlinks an element from its list.\r
+ *\r
+ * \param[in] element - ID of the element to remove.\r
+ *\r
+ * \return kLIST_OrphanElement if element is not part of any list.\r
+ * kLIST_Ok if removal was successful.\r
+ *\r
+ * \pre\r
+ *\r
+ * \post\r
+ *\r
+ * \remarks\r
+ *\r
+ ********************************************************************************** */\r
+list_status_t LIST_RemoveElement(list_element_handle_t element)\r
+{\r
+ if (element->list == NULL)\r
+ {\r
+ return kLIST_OrphanElement; /*Element was previusly removed or never added*/\r
+ }\r
+\r
+ uint32_t regPrimask = DisableGlobalIRQ();\r
+\r
+ if (element->prev == NULL) /*Element is head or solo*/\r
+ {\r
+ element->list->head = element->next; /*is null if solo*/\r
+ }\r
+ if (element->next == NULL) /*Element is tail or solo*/\r
+ {\r
+ element->list->tail = element->prev; /*is null if solo*/\r
+ }\r
+ if (element->prev != NULL) /*Element is not head*/\r
+ {\r
+ element->prev->next = element->next;\r
+ }\r
+ if (element->next != NULL) /*Element is not tail*/\r
+ {\r
+ element->next->prev = element->prev;\r
+ }\r
+ element->list->size--;\r
+ element->list = NULL;\r
+\r
+ EnableGlobalIRQ(regPrimask);\r
+ return kLIST_Ok;\r
+}\r
+\r
+/*! *********************************************************************************\r
+ * \brief Links an element in the previous position relative to a given member\r
+ * of a list.\r
+ *\r
+ * \param[in] element - ID of a member of a list.\r
+ * newElement - new element to insert before the given member.\r
+ *\r
+ * \return kLIST_OrphanElement if element is not part of any list.\r
+ * kLIST_Full if list is full.\r
+ * kLIST_Ok if insertion was successful.\r
+ *\r
+ * \pre\r
+ *\r
+ * \post\r
+ *\r
+ * \remarks\r
+ *\r
+ ********************************************************************************** */\r
+list_status_t LIST_AddPrevElement(list_element_handle_t element, list_element_handle_t newElement)\r
+{\r
+ if (element->list == NULL)\r
+ {\r
+ return kLIST_OrphanElement; /*Element was previusly removed or never added*/\r
+ }\r
+ uint32_t regPrimask = DisableGlobalIRQ();\r
+\r
+ if ((element->list->max != 0U) && (element->list->max == element->list->size))\r
+ {\r
+ EnableGlobalIRQ(regPrimask);\r
+ return kLIST_Full;\r
+ }\r
+\r
+ if (kLIST_DuplicateError == LIST_Scan(element->list, newElement))\r
+ {\r
+ EnableGlobalIRQ(regPrimask);\r
+ return kLIST_DuplicateError;\r
+ }\r
+\r
+ if (element->prev == NULL) /*Element is list head*/\r
+ {\r
+ element->list->head = newElement;\r
+ }\r
+ else\r
+ {\r
+ element->prev->next = newElement;\r
+ }\r
+ newElement->list = element->list;\r
+ element->list->size++;\r
+ newElement->next = element;\r
+ newElement->prev = element->prev;\r
+ element->prev = newElement;\r
+\r
+ EnableGlobalIRQ(regPrimask);\r
+ return kLIST_Ok;\r
+}\r
+\r
+/*! *********************************************************************************\r
+ * \brief Gets the current size of a list.\r
+ *\r
+ * \param[in] list - ID of the list.\r
+ *\r
+ * \return Current size of the list.\r
+ *\r
+ * \pre\r
+ *\r
+ * \post\r
+ *\r
+ * \remarks\r
+ *\r
+ ********************************************************************************** */\r
+uint32_t LIST_GetSize(list_handle_t list)\r
+{\r
+ return list->size;\r
+}\r
+\r
+/*! *********************************************************************************\r
+ * \brief Gets the number of free places in the list.\r
+ *\r
+ * \param[in] list - ID of the list.\r
+ *\r
+ * \return Available size of the list.\r
+ *\r
+ * \pre\r
+ *\r
+ * \post\r
+ *\r
+ * \remarks\r
+ *\r
+ ********************************************************************************** */\r
+uint32_t LIST_GetAvailableSize(list_handle_t list)\r
+{\r
+ return ((uint32_t)list->max - (uint32_t)list->size);\r
+}\r
--- /dev/null
+/*\r
+ * Copyright 2018-2019 NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#ifndef _GENERIC_LIST_H_\r
+#define _GENERIC_LIST_H_\r
+\r
+/*!\r
+ * @addtogroup GenericList\r
+ * @{\r
+ */\r
+\r
+/*!*********************************************************************************\r
+*************************************************************************************\r
+* Include\r
+*************************************************************************************\r
+********************************************************************************** */\r
+\r
+/*! *********************************************************************************\r
+*************************************************************************************\r
+* Public macro definitions\r
+*************************************************************************************\r
+********************************************************************************** */\r
+\r
+/*! *********************************************************************************\r
+*************************************************************************************\r
+* Public type definitions\r
+*************************************************************************************\r
+********************************************************************************** */\r
+/*! @brief The list status */\r
+typedef enum _list_status\r
+{\r
+ kLIST_Ok = kStatus_Success, /*!< Success */\r
+ kLIST_DuplicateError = MAKE_STATUS(kStatusGroup_LIST, 1), /*!< Duplicate Error */\r
+ kLIST_Full = MAKE_STATUS(kStatusGroup_LIST, 2), /*!< FULL */\r
+ kLIST_Empty = MAKE_STATUS(kStatusGroup_LIST, 3), /*!< Empty */\r
+ kLIST_OrphanElement = MAKE_STATUS(kStatusGroup_LIST, 4), /*!< Orphan Element */\r
+} list_status_t;\r
+\r
+/*! @brief The list structure*/\r
+typedef struct list_label\r
+{\r
+ struct list_element_tag *head; /*!< list head */\r
+ struct list_element_tag *tail; /*!< list tail */\r
+ uint16_t size; /*!< list size */\r
+ uint16_t max; /*!< list max number of elements */\r
+} list_label_t, *list_handle_t;\r
+\r
+/*! @brief The list element*/\r
+typedef struct list_element_tag\r
+{\r
+ struct list_element_tag *next; /*!< next list element */\r
+ struct list_element_tag *prev; /*!< previous list element */\r
+ struct list_label *list; /*!< pointer to the list */\r
+} list_element_t, *list_element_handle_t;\r
+\r
+/*! *********************************************************************************\r
+*************************************************************************************\r
+* Public prototypes\r
+*************************************************************************************\r
+********************************************************************************** */\r
+/*******************************************************************************\r
+ * API\r
+ ******************************************************************************/\r
+\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif /* _cplusplus */\r
+/*!\r
+ * @brief Initialize the list.\r
+ *\r
+ * This function initialize the list.\r
+ *\r
+ * @param list - List handle to initialize.\r
+ * @param max - Maximum number of elements in list. 0 for unlimited.\r
+ */\r
+void LIST_Init(list_handle_t list, uint32_t max);\r
+\r
+/*!\r
+ * @brief Gets the list that contains the given element.\r
+ *\r
+ *\r
+ * @param element - Handle of the element.\r
+ * @retval NULL if element is orphan, Handle of the list the element is inserted into.\r
+ */\r
+list_handle_t LIST_GetList(list_element_handle_t element);\r
+\r
+/*!\r
+ * @brief Links element to the head of the list.\r
+ *\r
+ * @param list - Handle of the list.\r
+ * @param element - Handle of the element.\r
+ * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful.\r
+ */\r
+list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element);\r
+\r
+/*!\r
+ * @brief Links element to the tail of the list.\r
+ *\r
+ * @param list - Handle of the list.\r
+ * @param element - Handle of the element.\r
+ * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful.\r
+ */\r
+list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element);\r
+\r
+/*!\r
+ * @brief Unlinks element from the head of the list.\r
+ *\r
+ * @param list - Handle of the list.\r
+ *\r
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.\r
+ */\r
+list_element_handle_t LIST_RemoveHead(list_handle_t list);\r
+\r
+/*!\r
+ * @brief Gets head element handle.\r
+ *\r
+ * @param list - Handle of the list.\r
+ *\r
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.\r
+ */\r
+list_element_handle_t LIST_GetHead(list_handle_t list);\r
+\r
+/*!\r
+ * @brief Gets next element handle for given element handle.\r
+ *\r
+ * @param element - Handle of the element.\r
+ *\r
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.\r
+ */\r
+list_element_handle_t LIST_GetNext(list_element_handle_t element);\r
+\r
+/*!\r
+ * @brief Gets previous element handle for given element handle.\r
+ *\r
+ * @param element - Handle of the element.\r
+ *\r
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.\r
+ */\r
+list_element_handle_t LIST_GetPrev(list_element_handle_t element);\r
+\r
+/*!\r
+ * @brief Unlinks an element from its list.\r
+ *\r
+ * @param element - Handle of the element.\r
+ *\r
+ * @retval kLIST_OrphanElement if element is not part of any list.\r
+ * @retval kLIST_Ok if removal was successful.\r
+ */\r
+list_status_t LIST_RemoveElement(list_element_handle_t element);\r
+\r
+/*!\r
+ * @brief Links an element in the previous position relative to a given member of a list.\r
+ *\r
+ * @param element - Handle of the element.\r
+ * @param newElement - New element to insert before the given member.\r
+ *\r
+ * @retval kLIST_OrphanElement if element is not part of any list.\r
+ * @retval kLIST_Ok if removal was successful.\r
+ */\r
+list_status_t LIST_AddPrevElement(list_element_handle_t element, list_element_handle_t newElement);\r
+\r
+/*!\r
+ * @brief Gets the current size of a list.\r
+ *\r
+ * @param list - Handle of the list.\r
+ *\r
+ * @retval Current size of the list.\r
+ */\r
+uint32_t LIST_GetSize(list_handle_t list);\r
+\r
+/*!\r
+ * @brief Gets the number of free places in the list.\r
+ *\r
+ * @param list - Handle of the list.\r
+ *\r
+ * @retval Available size of the list.\r
+ */\r
+uint32_t LIST_GetAvailableSize(list_handle_t list);\r
+\r
+/* @} */\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif\r
+/*! @}*/\r
+#endif /*_GENERIC_LIST_H_*/\r
--- /dev/null
+/*\r
+ * Copyright 2018-2019 NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#include "fsl_common.h"\r
+#include <string.h>\r
+\r
+#include "serial_manager.h"\r
+#include "serial_port_internal.h"\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+\r
+#include "generic_list.h"\r
+\r
+/*\r
+ * The OSA_USED macro can only be defined when the OSA component is used.\r
+ * If the source code of the OSA component does not exist, the OSA_USED cannot be defined.\r
+ * OR, If OSA component is not added into project event the OSA source code exists, the OSA_USED\r
+ * also cannot be defined.\r
+ * The source code path of the OSA component is <MCUXpresso_SDK>/components/osa.\r
+ *\r
+ */\r
+#if defined(OSA_USED)\r
+\r
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))\r
+#include "common_task.h"\r
+#else\r
+#include "fsl_os_abstraction.h"\r
+#endif\r
+\r
+#endif\r
+\r
+#endif\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+#ifndef NDEBUG\r
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))\r
+#undef assert\r
+#define assert(n)\r
+#endif\r
+#endif\r
+\r
+#define SERIAL_EVENT_DATA_RECEIVED (1U << 0)\r
+#define SERIAL_EVENT_DATA_SENT (1U << 1)\r
+\r
+#define SERIAL_MANAGER_WRITE_TAG 0xAABB5754U\r
+#define SERIAL_MANAGER_READ_TAG 0xBBAA5244U\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+typedef enum _serial_manager_transmission_mode\r
+{\r
+ kSerialManager_TransmissionBlocking = 0x0U, /*!< Blocking transmission*/\r
+ kSerialManager_TransmissionNonBlocking = 0x1U, /*!< None blocking transmission*/\r
+} serial_manager_transmission_mode_t;\r
+\r
+/* TX transfer structure */\r
+typedef struct _serial_manager_transfer\r
+{\r
+ uint8_t *buffer;\r
+ volatile uint32_t length;\r
+ volatile uint32_t soFar;\r
+ serial_manager_transmission_mode_t mode;\r
+ serial_manager_status_t status;\r
+} serial_manager_transfer_t;\r
+#endif\r
+\r
+/* write handle structure */\r
+typedef struct _serial_manager_send_handle\r
+{\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ list_element_t link; /*!< list element of the link */\r
+ serial_manager_transfer_t transfer;\r
+#endif\r
+ struct _serial_manager_handle *serialManagerHandle;\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ serial_manager_callback_t callback;\r
+ void *callbackParam;\r
+ uint32_t tag;\r
+#endif\r
+} serial_manager_write_handle_t;\r
+\r
+typedef serial_manager_write_handle_t serial_manager_read_handle_t;\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+/* receive state structure */\r
+typedef struct _serial_manager_read_ring_buffer\r
+{\r
+ uint8_t *ringBuffer;\r
+ uint32_t ringBufferSize;\r
+ volatile uint32_t ringHead;\r
+ volatile uint32_t ringTail;\r
+} serial_manager_read_ring_buffer_t;\r
+#endif\r
+\r
+#if defined(__CC_ARM)\r
+#pragma anon_unions\r
+#endif\r
+/* The serial manager handle structure */\r
+typedef struct _serial_manager_handle\r
+{\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ list_label_t runningWriteHandleHead; /*!< The queue of running write handle */\r
+ list_label_t completedWriteHandleHead; /*!< The queue of completed write handle */\r
+#endif\r
+ serial_manager_read_handle_t *volatile openedReadHandleHead;\r
+ volatile uint32_t openedWriteHandleCount;\r
+ union\r
+ {\r
+ uint8_t lowLevelhandleBuffer[1];\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+ uint8_t uartHandleBuffer[SERIAL_PORT_UART_HANDLE_SIZE];\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+ uint8_t usbcdcHandleBuffer[SERIAL_PORT_USB_CDC_HANDLE_SIZE];\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))\r
+ uint8_t swoHandleBuffer[SERIAL_PORT_SWO_HANDLE_SIZE];\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))\r
+ uint8_t usbcdcVirtualHandleBuffer[SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE];\r
+#endif\r
+ };\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ serial_manager_read_ring_buffer_t ringBuffer;\r
+#endif\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+\r
+#if defined(OSA_USED)\r
+\r
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))\r
+ common_task_message_t commontaskMsg;\r
+#else\r
+ uint8_t event[OSA_EVENT_HANDLE_SIZE]; /*!< Event instance */\r
+ uint8_t taskId[OSA_TASK_HANDLE_SIZE]; /*!< Task handle */\r
+#endif\r
+\r
+#endif\r
+\r
+#endif\r
+\r
+ serial_port_type_t type;\r
+} serial_manager_handle_t;\r
+\r
+/*******************************************************************************\r
+ * Prototypes\r
+ ******************************************************************************/\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+static void SerialManager_Task(void *param);\r
+#endif\r
+\r
+/*******************************************************************************\r
+ * Variables\r
+ ******************************************************************************/\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+\r
+#if defined(OSA_USED)\r
+\r
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))\r
+\r
+#else\r
+ /*\r
+ * \brief Defines the serial manager task's stack\r
+ */\r
+OSA_TASK_DEFINE(SerialManager_Task, SERIAL_MANAGER_TASK_PRIORITY, 1, SERIAL_MANAGER_TASK_STACK_SIZE, false);\r
+#endif\r
+\r
+#endif\r
+\r
+#endif\r
+\r
+/*******************************************************************************\r
+ * Code\r
+ ******************************************************************************/\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+static void SerialManager_AddTail(list_label_t *queue, serial_manager_write_handle_t *node)\r
+{\r
+ (void)LIST_AddTail(queue, &node->link);\r
+}\r
+\r
+static void SerialManager_RemoveHead(list_label_t *queue)\r
+{\r
+ (void)LIST_RemoveHead(queue);\r
+}\r
+#endif\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+\r
+static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_t *handle)\r
+{\r
+ serial_manager_status_t status = kStatus_SerialManager_Error;\r
+ serial_manager_write_handle_t *writeHandle =\r
+ (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->runningWriteHandleHead);\r
+\r
+ if (writeHandle != NULL)\r
+ {\r
+ switch (handle->type)\r
+ {\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+ case kSerialPort_Uart:\r
+ status = Serial_UartWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),\r
+ writeHandle->transfer.buffer, writeHandle->transfer.length);\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+ case kSerialPort_UsbCdc:\r
+ status = Serial_UsbCdcWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),\r
+ writeHandle->transfer.buffer, writeHandle->transfer.length);\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))\r
+ case kSerialPort_Swo:\r
+ status = Serial_SwoWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),\r
+ writeHandle->transfer.buffer, writeHandle->transfer.length);\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))\r
+ case kSerialPort_UsbCdcVirtual:\r
+ status = Serial_UsbCdcVirtualWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),\r
+ writeHandle->transfer.buffer, writeHandle->transfer.length);\r
+ break;\r
+#endif\r
+ default:\r
+ status = kStatus_SerialManager_Error;\r
+ break;\r
+ }\r
+ }\r
+ return status;\r
+}\r
+\r
+static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_t *handle,\r
+ serial_manager_read_handle_t *readHandle,\r
+ uint8_t *buffer,\r
+ uint32_t length)\r
+{\r
+ serial_manager_status_t status = kStatus_SerialManager_Error;\r
+\r
+ if (NULL != readHandle)\r
+ {\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+ if (handle->type == kSerialPort_UsbCdc)\r
+ {\r
+ status = Serial_UsbCdcRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);\r
+ }\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))\r
+ if (handle->type == kSerialPort_UsbCdcVirtual)\r
+ {\r
+ status = Serial_UsbCdcVirtualRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);\r
+ }\r
+#endif\r
+ }\r
+ return status;\r
+}\r
+\r
+#else\r
+\r
+static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_t *handle,\r
+ serial_manager_write_handle_t *writeHandle,\r
+ uint8_t *buffer,\r
+ uint32_t length)\r
+{\r
+ serial_manager_status_t status = kStatus_SerialManager_Error;\r
+\r
+ if (NULL != writeHandle)\r
+ {\r
+ switch (handle->type)\r
+ {\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+ case kSerialPort_Uart:\r
+ status = Serial_UartWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+ case kSerialPort_UsbCdc:\r
+ status = Serial_UsbCdcWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))\r
+ case kSerialPort_Swo:\r
+ status = Serial_SwoWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))\r
+ case kSerialPort_UsbCdcVirtual:\r
+ status = Serial_UsbCdcVirtualWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);\r
+ break;\r
+#endif\r
+ default:\r
+ status = kStatus_SerialManager_Error;\r
+ break;\r
+ }\r
+ }\r
+ return status;\r
+}\r
+\r
+static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_t *handle,\r
+ serial_manager_read_handle_t *readHandle,\r
+ uint8_t *buffer,\r
+ uint32_t length)\r
+{\r
+ serial_manager_status_t status = kStatus_SerialManager_Error;\r
+\r
+ if (NULL != readHandle)\r
+ {\r
+ switch (handle->type)\r
+ {\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+ case kSerialPort_Uart:\r
+ status = Serial_UartRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+ case kSerialPort_UsbCdc:\r
+ status = Serial_UsbCdcRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))\r
+ case kSerialPort_Swo:\r
+ status = Serial_SwoRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))\r
+ case kSerialPort_UsbCdcVirtual:\r
+ status = Serial_UsbCdcVirtualRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);\r
+ break;\r
+#endif\r
+ default:\r
+ status = kStatus_SerialManager_Error;\r
+ break;\r
+ }\r
+ }\r
+ return status;\r
+}\r
+#endif\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+static void SerialManager_IsrFunction(serial_manager_handle_t *handle)\r
+{\r
+ uint32_t regPrimask = DisableGlobalIRQ();\r
+ switch (handle->type)\r
+ {\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+ case kSerialPort_Uart:\r
+ Serial_UartIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+ case kSerialPort_UsbCdc:\r
+ Serial_UsbCdcIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))\r
+ case kSerialPort_Swo:\r
+ Serial_SwoIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))\r
+ case kSerialPort_UsbCdcVirtual:\r
+ Serial_UsbCdcVirtualIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));\r
+ break;\r
+#endif\r
+ default:\r
+ /*MISRA rule 16.4*/\r
+ break;\r
+ }\r
+ EnableGlobalIRQ(regPrimask);\r
+}\r
+\r
+static void SerialManager_Task(void *param)\r
+{\r
+ serial_manager_handle_t *handle = (serial_manager_handle_t *)param;\r
+ serial_manager_write_handle_t *serialWriteHandle;\r
+ serial_manager_read_handle_t *serialReadHandle;\r
+ uint32_t primask;\r
+ serial_manager_callback_message_t msg;\r
+\r
+ if (NULL != handle)\r
+ {\r
+#if defined(OSA_USED)\r
+\r
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))\r
+#else\r
+ osa_event_flags_t ev = 0;\r
+\r
+ do\r
+ {\r
+ if (KOSA_StatusSuccess ==\r
+ OSA_EventWait((osa_event_handle_t)handle->event, osaEventFlagsAll_c, false, osaWaitForever_c, &ev))\r
+ {\r
+ if (ev & SERIAL_EVENT_DATA_SENT)\r
+#endif\r
+\r
+#endif\r
+ {\r
+ serialWriteHandle =\r
+ (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->completedWriteHandleHead);\r
+ while (NULL != serialWriteHandle)\r
+ {\r
+ SerialManager_RemoveHead(&handle->completedWriteHandleHead);\r
+ msg.buffer = serialWriteHandle->transfer.buffer;\r
+ msg.length = serialWriteHandle->transfer.soFar;\r
+ serialWriteHandle->transfer.buffer = NULL;\r
+ if (NULL != serialWriteHandle->callback)\r
+ {\r
+ serialWriteHandle->callback(serialWriteHandle->callbackParam, &msg,\r
+ serialWriteHandle->transfer.status);\r
+ }\r
+ serialWriteHandle =\r
+ (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->completedWriteHandleHead);\r
+ }\r
+ }\r
+#if defined(OSA_USED)\r
+\r
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))\r
+#else\r
+ if (ev & SERIAL_EVENT_DATA_RECEIVED)\r
+#endif\r
+\r
+#endif\r
+ {\r
+ primask = DisableGlobalIRQ();\r
+ serialReadHandle = handle->openedReadHandleHead;\r
+ EnableGlobalIRQ(primask);\r
+\r
+ if (NULL != serialReadHandle)\r
+ {\r
+ if (NULL != serialReadHandle->transfer.buffer)\r
+ {\r
+ if (serialReadHandle->transfer.soFar >= serialReadHandle->transfer.length)\r
+ {\r
+ msg.buffer = serialReadHandle->transfer.buffer;\r
+ msg.length = serialReadHandle->transfer.soFar;\r
+ serialReadHandle->transfer.buffer = NULL;\r
+ if (NULL != serialReadHandle->callback)\r
+ {\r
+ serialReadHandle->callback(serialReadHandle->callbackParam, &msg,\r
+ serialReadHandle->transfer.status);\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+#if defined(OSA_USED)\r
+\r
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))\r
+#else\r
+ }\r
+ } while (gUseRtos_c);\r
+#endif\r
+\r
+#endif\r
+ }\r
+}\r
+#endif\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+static void SerialManager_TxCallback(void *callbackParam,\r
+ serial_manager_callback_message_t *message,\r
+ serial_manager_status_t status)\r
+{\r
+ serial_manager_handle_t *handle;\r
+ serial_manager_write_handle_t *writeHandle;\r
+\r
+ assert(callbackParam);\r
+ assert(message);\r
+\r
+ handle = (serial_manager_handle_t *)callbackParam;\r
+\r
+ writeHandle = (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->runningWriteHandleHead);\r
+\r
+ if (NULL != writeHandle)\r
+ {\r
+ SerialManager_RemoveHead(&handle->runningWriteHandleHead);\r
+ (void)SerialManager_StartWriting(handle);\r
+ writeHandle->transfer.soFar = message->length;\r
+ writeHandle->transfer.status = status;\r
+ if (kSerialManager_TransmissionNonBlocking == writeHandle->transfer.mode)\r
+ {\r
+ SerialManager_AddTail(&handle->completedWriteHandleHead, writeHandle);\r
+#if defined(OSA_USED)\r
+\r
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))\r
+ handle->commontaskMsg.callback = SerialManager_Task;\r
+ handle->commontaskMsg.callbackParam = handle;\r
+ COMMON_TASK_post_message(&handle->commontaskMsg);\r
+#else\r
+ (void)OSA_EventSet((osa_event_handle_t)handle->event, SERIAL_EVENT_DATA_SENT);\r
+#endif\r
+\r
+#else\r
+ SerialManager_Task(handle);\r
+#endif\r
+ }\r
+ else\r
+ {\r
+ writeHandle->transfer.buffer = NULL;\r
+ }\r
+ }\r
+}\r
+\r
+static void SerialManager_RxCallback(void *callbackParam,\r
+ serial_manager_callback_message_t *message,\r
+ serial_manager_status_t status)\r
+{\r
+ serial_manager_handle_t *handle;\r
+ uint32_t ringBufferLength;\r
+ uint32_t primask;\r
+\r
+ assert(callbackParam);\r
+ assert(message);\r
+\r
+ handle = (serial_manager_handle_t *)callbackParam;\r
+\r
+ status = kStatus_SerialManager_Notify;\r
+\r
+ for (uint32_t i = 0; i < message->length; i++)\r
+ {\r
+ handle->ringBuffer.ringBuffer[handle->ringBuffer.ringHead++] = message->buffer[i];\r
+ if (handle->ringBuffer.ringHead >= handle->ringBuffer.ringBufferSize)\r
+ {\r
+ handle->ringBuffer.ringHead = 0U;\r
+ }\r
+ if (handle->ringBuffer.ringHead == handle->ringBuffer.ringTail)\r
+ {\r
+ status = kStatus_SerialManager_RingBufferOverflow;\r
+ handle->ringBuffer.ringTail++;\r
+ if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize)\r
+ {\r
+ handle->ringBuffer.ringTail = 0U;\r
+ }\r
+ }\r
+ }\r
+\r
+ ringBufferLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail;\r
+ ringBufferLength = ringBufferLength % handle->ringBuffer.ringBufferSize;\r
+\r
+ primask = DisableGlobalIRQ();\r
+ if ((NULL != handle->openedReadHandleHead) && (NULL != handle->openedReadHandleHead->transfer.buffer))\r
+ {\r
+ if (handle->openedReadHandleHead->transfer.length > handle->openedReadHandleHead->transfer.soFar)\r
+ {\r
+ uint32_t remainLength =\r
+ handle->openedReadHandleHead->transfer.length - handle->openedReadHandleHead->transfer.soFar;\r
+ for (uint32_t i = 0; i < MIN(ringBufferLength, remainLength); i++)\r
+ {\r
+ handle->openedReadHandleHead->transfer.buffer[handle->openedReadHandleHead->transfer.soFar] =\r
+ handle->ringBuffer.ringBuffer[handle->ringBuffer.ringTail];\r
+ handle->ringBuffer.ringTail++;\r
+ handle->openedReadHandleHead->transfer.soFar++;\r
+ if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize)\r
+ {\r
+ handle->ringBuffer.ringTail = 0U;\r
+ }\r
+ }\r
+ ringBufferLength = ringBufferLength - MIN(ringBufferLength, remainLength);\r
+ }\r
+\r
+ if (handle->openedReadHandleHead->transfer.length > handle->openedReadHandleHead->transfer.soFar)\r
+ {\r
+ }\r
+ else\r
+ {\r
+ if (kSerialManager_TransmissionBlocking == handle->openedReadHandleHead->transfer.mode)\r
+ {\r
+ handle->openedReadHandleHead->transfer.buffer = NULL;\r
+ }\r
+ else\r
+ {\r
+ handle->openedReadHandleHead->transfer.status = kStatus_SerialManager_Success;\r
+\r
+#if defined(OSA_USED)\r
+\r
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))\r
+ handle->commontaskMsg.callback = SerialManager_Task;\r
+ handle->commontaskMsg.callbackParam = handle;\r
+ COMMON_TASK_post_message(&handle->commontaskMsg);\r
+#else\r
+ (void)OSA_EventSet((osa_event_handle_t)handle->event, SERIAL_EVENT_DATA_RECEIVED);\r
+#endif\r
+\r
+#else\r
+ SerialManager_Task(handle);\r
+#endif\r
+ }\r
+ }\r
+ }\r
+\r
+ if (0U != ringBufferLength)\r
+ {\r
+ message->buffer = NULL;\r
+ message->length = ringBufferLength;\r
+ if ((NULL != handle->openedReadHandleHead) && (NULL != handle->openedReadHandleHead->callback))\r
+ {\r
+ handle->openedReadHandleHead->callback(handle->openedReadHandleHead->callbackParam, message, status);\r
+ }\r
+ }\r
+\r
+ ringBufferLength = handle->ringBuffer.ringBufferSize - 1U - ringBufferLength;\r
+\r
+ if (NULL != handle->openedReadHandleHead)\r
+ {\r
+ (void)SerialManager_StartReading(handle, handle->openedReadHandleHead, NULL, ringBufferLength);\r
+ }\r
+ EnableGlobalIRQ(primask);\r
+}\r
+\r
+static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHandle,\r
+ uint8_t *buffer,\r
+ uint32_t length,\r
+ serial_manager_transmission_mode_t mode)\r
+{\r
+ serial_manager_write_handle_t *serialWriteHandle;\r
+ serial_manager_handle_t *handle;\r
+ serial_manager_status_t status = kStatus_SerialManager_Success;\r
+ uint32_t primask;\r
+ uint8_t isEmpty = 0U;\r
+\r
+ assert(writeHandle);\r
+ assert(buffer);\r
+ assert(length);\r
+\r
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;\r
+ handle = serialWriteHandle->serialManagerHandle;\r
+\r
+ assert(handle);\r
+ assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag);\r
+ assert(!((kSerialManager_TransmissionNonBlocking == mode) && (NULL == serialWriteHandle->callback)));\r
+\r
+ primask = DisableGlobalIRQ();\r
+ if (NULL != serialWriteHandle->transfer.buffer)\r
+ {\r
+ EnableGlobalIRQ(primask);\r
+ return kStatus_SerialManager_Busy;\r
+ }\r
+ serialWriteHandle->transfer.buffer = buffer;\r
+ serialWriteHandle->transfer.length = length;\r
+ serialWriteHandle->transfer.soFar = 0U;\r
+ serialWriteHandle->transfer.mode = mode;\r
+\r
+ if (NULL == LIST_GetHead(&handle->runningWriteHandleHead))\r
+ {\r
+ isEmpty = 1U;\r
+ }\r
+ SerialManager_AddTail(&handle->runningWriteHandleHead, serialWriteHandle);\r
+ EnableGlobalIRQ(primask);\r
+\r
+ if (0U != isEmpty)\r
+ {\r
+ status = SerialManager_StartWriting(handle);\r
+ if ((serial_manager_status_t)kStatus_SerialManager_Success != status)\r
+ {\r
+ return status;\r
+ }\r
+ }\r
+\r
+ if (kSerialManager_TransmissionBlocking == mode)\r
+ {\r
+ while (serialWriteHandle->transfer.length > serialWriteHandle->transfer.soFar)\r
+ {\r
+#if defined(__GIC_PRIO_BITS)\r
+ if (0x13 == (__get_CPSR() & CPSR_M_Msk))\r
+#else\r
+ if (0U != __get_IPSR())\r
+#endif\r
+ {\r
+ SerialManager_IsrFunction(handle);\r
+ }\r
+ }\r
+ }\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandle,\r
+ uint8_t *buffer,\r
+ uint32_t length,\r
+ serial_manager_transmission_mode_t mode,\r
+ uint32_t *receivedLength)\r
+{\r
+ serial_manager_read_handle_t *serialReadHandle;\r
+ serial_manager_handle_t *handle;\r
+ uint32_t dataLength;\r
+ uint32_t primask;\r
+\r
+ assert(readHandle);\r
+ assert(buffer);\r
+ assert(length);\r
+\r
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;\r
+ handle = serialReadHandle->serialManagerHandle;\r
+\r
+ assert(handle);\r
+ assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag);\r
+ assert(!((kSerialManager_TransmissionNonBlocking == mode) && (NULL == serialReadHandle->callback)));\r
+\r
+ primask = DisableGlobalIRQ();\r
+ if (NULL != serialReadHandle->transfer.buffer)\r
+ {\r
+ EnableGlobalIRQ(primask);\r
+ return kStatus_SerialManager_Busy;\r
+ }\r
+ serialReadHandle->transfer.buffer = buffer;\r
+ serialReadHandle->transfer.length = length;\r
+ serialReadHandle->transfer.soFar = 0U;\r
+ serialReadHandle->transfer.mode = mode;\r
+\r
+ dataLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail;\r
+ dataLength = dataLength % handle->ringBuffer.ringBufferSize;\r
+\r
+ for (serialReadHandle->transfer.soFar = 0U; serialReadHandle->transfer.soFar < MIN(dataLength, length);\r
+ serialReadHandle->transfer.soFar++)\r
+ {\r
+ buffer[serialReadHandle->transfer.soFar] = handle->ringBuffer.ringBuffer[handle->ringBuffer.ringTail];\r
+ handle->ringBuffer.ringTail++;\r
+ if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize)\r
+ {\r
+ handle->ringBuffer.ringTail = 0U;\r
+ }\r
+ }\r
+\r
+ dataLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail;\r
+ dataLength = dataLength % handle->ringBuffer.ringBufferSize;\r
+ dataLength = handle->ringBuffer.ringBufferSize - 1U - dataLength;\r
+\r
+ (void)SerialManager_StartReading(handle, readHandle, NULL, dataLength);\r
+\r
+ if (NULL != receivedLength)\r
+ {\r
+ *receivedLength = serialReadHandle->transfer.soFar;\r
+ serialReadHandle->transfer.buffer = NULL;\r
+ EnableGlobalIRQ(primask);\r
+ }\r
+ else\r
+ {\r
+ if (serialReadHandle->transfer.soFar >= serialReadHandle->transfer.length)\r
+ {\r
+ serialReadHandle->transfer.buffer = NULL;\r
+ EnableGlobalIRQ(primask);\r
+ if (kSerialManager_TransmissionNonBlocking == mode)\r
+ {\r
+ if (NULL != serialReadHandle->callback)\r
+ {\r
+ serial_manager_callback_message_t msg;\r
+ msg.buffer = buffer;\r
+ msg.length = serialReadHandle->transfer.soFar;\r
+ serialReadHandle->callback(serialReadHandle->callbackParam, &msg, kStatus_SerialManager_Success);\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ EnableGlobalIRQ(primask);\r
+ }\r
+\r
+ if (kSerialManager_TransmissionBlocking == mode)\r
+ {\r
+ while (serialReadHandle->transfer.length > serialReadHandle->transfer.soFar)\r
+ {\r
+ }\r
+ }\r
+ }\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+#else\r
+\r
+static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHandle, uint8_t *buffer, uint32_t length)\r
+{\r
+ serial_manager_write_handle_t *serialWriteHandle;\r
+ serial_manager_handle_t *handle;\r
+\r
+ assert(writeHandle);\r
+ assert(buffer);\r
+ assert(length);\r
+\r
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;\r
+ handle = serialWriteHandle->serialManagerHandle;\r
+\r
+ assert(handle);\r
+\r
+ return SerialManager_StartWriting(handle, serialWriteHandle, buffer, length);\r
+}\r
+\r
+static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length)\r
+{\r
+ serial_manager_read_handle_t *serialReadHandle;\r
+ serial_manager_handle_t *handle;\r
+\r
+ assert(readHandle);\r
+ assert(buffer);\r
+ assert(length);\r
+\r
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;\r
+ handle = serialReadHandle->serialManagerHandle;\r
+\r
+ assert(handle);\r
+\r
+ return SerialManager_StartReading(handle, serialReadHandle, buffer, length);\r
+}\r
+#endif\r
+\r
+serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, serial_manager_config_t *config)\r
+{\r
+ serial_manager_handle_t *handle;\r
+ serial_manager_status_t status = kStatus_SerialManager_Error;\r
+\r
+ assert(config);\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ assert(config->ringBuffer);\r
+ assert(config->ringBufferSize);\r
+#endif\r
+ assert(serialHandle);\r
+ assert(SERIAL_MANAGER_HANDLE_SIZE >= sizeof(serial_manager_handle_t));\r
+\r
+ handle = (serial_manager_handle_t *)serialHandle;\r
+\r
+ (void)memset(handle, 0, SERIAL_MANAGER_HANDLE_SIZE);\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+\r
+#if defined(OSA_USED)\r
+\r
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))\r
+\r
+ COMMON_TASK_init();\r
+\r
+#else\r
+ if (KOSA_StatusSuccess != OSA_EventCreate((osa_event_handle_t)handle->event, true))\r
+ {\r
+ return kStatus_SerialManager_Error;\r
+ }\r
+\r
+ if (KOSA_StatusSuccess != OSA_TaskCreate((osa_task_handle_t)handle->taskId, OSA_TASK(SerialManager_Task), handle))\r
+ {\r
+ return kStatus_SerialManager_Error;\r
+ }\r
+#endif\r
+\r
+#endif\r
+\r
+#endif\r
+\r
+ handle->type = config->type;\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ handle->ringBuffer.ringBuffer = config->ringBuffer;\r
+ handle->ringBuffer.ringBufferSize = config->ringBufferSize;\r
+#endif\r
+\r
+ switch (config->type)\r
+ {\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+ case kSerialPort_Uart:\r
+ status = Serial_UartInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig);\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ if ((serial_manager_status_t)kStatus_SerialManager_Success == status)\r
+ {\r
+ status = Serial_UartInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),\r
+ SerialManager_TxCallback, handle);\r
+ if ((serial_manager_status_t)kStatus_SerialManager_Success == status)\r
+ {\r
+ status = Serial_UartInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),\r
+ SerialManager_RxCallback, handle);\r
+ }\r
+ }\r
+#endif\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+ case kSerialPort_UsbCdc:\r
+ status = Serial_UsbCdcInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig);\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ if (kStatus_SerialManager_Success == status)\r
+ {\r
+ status = Serial_UsbCdcInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),\r
+ SerialManager_TxCallback, handle);\r
+ if (kStatus_SerialManager_Success == status)\r
+ {\r
+ status = Serial_UsbCdcInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),\r
+ SerialManager_RxCallback, handle);\r
+ }\r
+ }\r
+#endif\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))\r
+ case kSerialPort_Swo:\r
+ status = Serial_SwoInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig);\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ if (kStatus_SerialManager_Success == status)\r
+ {\r
+ status = Serial_SwoInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),\r
+ SerialManager_TxCallback, handle);\r
+ }\r
+#endif\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))\r
+ case kSerialPort_UsbCdcVirtual:\r
+ status = Serial_UsbCdcVirtualInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig);\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ if (kStatus_SerialManager_Success == status)\r
+ {\r
+ status = Serial_UsbCdcVirtualInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),\r
+ SerialManager_TxCallback, handle);\r
+ if (kStatus_SerialManager_Success == status)\r
+ {\r
+ status = Serial_UsbCdcVirtualInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),\r
+ SerialManager_RxCallback, handle);\r
+ }\r
+ }\r
+#endif\r
+ break;\r
+#endif\r
+ default:\r
+ /*MISRA rule 16.4*/\r
+ break;\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle)\r
+{\r
+ serial_manager_handle_t *handle;\r
+ uint32_t primask;\r
+\r
+ assert(serialHandle);\r
+\r
+ handle = (serial_manager_handle_t *)serialHandle;\r
+\r
+ primask = DisableGlobalIRQ();\r
+ if ((NULL != handle->openedReadHandleHead) || (0U != handle->openedWriteHandleCount))\r
+ {\r
+ EnableGlobalIRQ(primask);\r
+ return kStatus_SerialManager_Busy;\r
+ }\r
+ EnableGlobalIRQ(primask);\r
+\r
+ switch (handle->type)\r
+ {\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+ case kSerialPort_Uart:\r
+ (void)Serial_UartDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+ case kSerialPort_UsbCdc:\r
+ (void)Serial_UsbCdcDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))\r
+ case kSerialPort_Swo:\r
+ (void)Serial_SwoDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))\r
+ case kSerialPort_UsbCdcVirtual:\r
+ (void)Serial_UsbCdcVirtualDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));\r
+ break;\r
+#endif\r
+ default:\r
+ /*MISRA rule 16.4*/\r
+ break;\r
+ }\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+\r
+#if defined(OSA_USED)\r
+\r
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))\r
+#else\r
+ OSA_EventDestroy((osa_event_handle_t)handle->event);\r
+ OSA_TaskDestroy((osa_task_handle_t)handle->taskId);\r
+#endif\r
+\r
+#endif\r
+\r
+#endif\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle)\r
+{\r
+ serial_manager_handle_t *handle;\r
+ serial_manager_write_handle_t *serialWriteHandle;\r
+ uint32_t primask;\r
+\r
+ assert(serialHandle);\r
+ assert(writeHandle);\r
+ assert(SERIAL_MANAGER_WRITE_HANDLE_SIZE >= sizeof(serial_manager_write_handle_t));\r
+\r
+ handle = (serial_manager_handle_t *)serialHandle;\r
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;\r
+\r
+ (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_HANDLE_SIZE);\r
+\r
+ primask = DisableGlobalIRQ();\r
+ handle->openedWriteHandleCount++;\r
+ EnableGlobalIRQ(primask);\r
+\r
+ serialWriteHandle->serialManagerHandle = handle;\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ serialWriteHandle->tag = SERIAL_MANAGER_WRITE_TAG;\r
+#endif\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle)\r
+{\r
+ serial_manager_handle_t *handle;\r
+ serial_manager_write_handle_t *serialWriteHandle;\r
+ uint32_t primask;\r
+\r
+ assert(writeHandle);\r
+\r
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;\r
+ handle = (serial_manager_handle_t *)(void *)serialWriteHandle->serialManagerHandle;\r
+\r
+ assert(handle);\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag);\r
+#endif\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ (void)SerialManager_CancelWriting(writeHandle);\r
+#endif\r
+ primask = DisableGlobalIRQ();\r
+ if (handle->openedWriteHandleCount > 0U)\r
+ {\r
+ handle->openedWriteHandleCount--;\r
+ }\r
+ EnableGlobalIRQ(primask);\r
+\r
+ (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_HANDLE_SIZE);\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle)\r
+{\r
+ serial_manager_handle_t *handle;\r
+ serial_manager_read_handle_t *serialReadHandle;\r
+ uint32_t primask;\r
+\r
+ assert(serialHandle);\r
+ assert(readHandle);\r
+ assert(SERIAL_MANAGER_READ_HANDLE_SIZE >= sizeof(serial_manager_read_handle_t));\r
+\r
+ handle = (serial_manager_handle_t *)serialHandle;\r
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;\r
+\r
+ primask = DisableGlobalIRQ();\r
+ if (handle->openedReadHandleHead != NULL)\r
+ {\r
+ EnableGlobalIRQ(primask);\r
+ return kStatus_SerialManager_Busy;\r
+ }\r
+ handle->openedReadHandleHead = serialReadHandle;\r
+ EnableGlobalIRQ(primask);\r
+\r
+ (void)memset(readHandle, 0, SERIAL_MANAGER_READ_HANDLE_SIZE);\r
+\r
+ serialReadHandle->serialManagerHandle = handle;\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ serialReadHandle->tag = SERIAL_MANAGER_READ_TAG;\r
+#endif\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle)\r
+{\r
+ serial_manager_handle_t *handle;\r
+ serial_manager_read_handle_t *serialReadHandle;\r
+ uint32_t primask;\r
+\r
+ assert(readHandle);\r
+\r
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;\r
+ handle = (serial_manager_handle_t *)(void *)serialReadHandle->serialManagerHandle;\r
+\r
+ assert(handle && (handle->openedReadHandleHead == serialReadHandle));\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag);\r
+#endif\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ (void)SerialManager_CancelReading(readHandle);\r
+#endif\r
+\r
+ primask = DisableGlobalIRQ();\r
+ handle->openedReadHandleHead = NULL;\r
+ EnableGlobalIRQ(primask);\r
+\r
+ (void)memset(readHandle, 0, SERIAL_MANAGER_READ_HANDLE_SIZE);\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle, uint8_t *buffer, uint32_t length)\r
+{\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ return SerialManager_Write(writeHandle, buffer, length, kSerialManager_TransmissionBlocking);\r
+#else\r
+ return SerialManager_Write(writeHandle, buffer, length);\r
+#endif\r
+}\r
+\r
+serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length)\r
+{\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionBlocking, NULL);\r
+#else\r
+ return SerialManager_Read(readHandle, buffer, length);\r
+#endif\r
+}\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle,\r
+ uint8_t *buffer,\r
+ uint32_t length)\r
+{\r
+ return SerialManager_Write(writeHandle, buffer, length, kSerialManager_TransmissionNonBlocking);\r
+}\r
+\r
+serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length)\r
+{\r
+ return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionNonBlocking, NULL);\r
+}\r
+\r
+serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle)\r
+{\r
+ serial_manager_write_handle_t *serialWriteHandle;\r
+ uint32_t primask;\r
+ uint8_t isNotUsed = 0;\r
+\r
+ assert(writeHandle);\r
+\r
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;\r
+\r
+ assert(serialWriteHandle->serialManagerHandle);\r
+ assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag);\r
+\r
+ if ((NULL != serialWriteHandle->transfer.buffer) &&\r
+ (kSerialManager_TransmissionBlocking == serialWriteHandle->transfer.mode))\r
+ {\r
+ return kStatus_SerialManager_Error;\r
+ }\r
+\r
+ primask = DisableGlobalIRQ();\r
+ if (serialWriteHandle != (serial_manager_write_handle_t *)(void *)LIST_GetHead(\r
+ &serialWriteHandle->serialManagerHandle->runningWriteHandleHead))\r
+ {\r
+ (void)LIST_RemoveElement(&serialWriteHandle->link);\r
+ isNotUsed = 1;\r
+ }\r
+ EnableGlobalIRQ(primask);\r
+\r
+ if (0U != isNotUsed)\r
+ {\r
+ serialWriteHandle->transfer.soFar = 0;\r
+ serialWriteHandle->transfer.status = kStatus_SerialManager_Canceled;\r
+\r
+ SerialManager_AddTail(&serialWriteHandle->serialManagerHandle->completedWriteHandleHead, serialWriteHandle);\r
+#if defined(OSA_USED)\r
+\r
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))\r
+ serialWriteHandle->serialManagerHandle->commontaskMsg.callback = SerialManager_Task;\r
+ serialWriteHandle->serialManagerHandle->commontaskMsg.callbackParam = serialWriteHandle->serialManagerHandle;\r
+ COMMON_TASK_post_message(&serialWriteHandle->serialManagerHandle->commontaskMsg);\r
+#else\r
+ (void)OSA_EventSet((osa_event_handle_t)serialWriteHandle->serialManagerHandle->event, SERIAL_EVENT_DATA_SENT);\r
+#endif\r
+\r
+#else\r
+ SerialManager_Task(serialWriteHandle->serialManagerHandle);\r
+#endif\r
+ }\r
+ else\r
+ {\r
+ switch (serialWriteHandle->serialManagerHandle->type)\r
+ {\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+ case kSerialPort_Uart:\r
+ (void)Serial_UartCancelWrite(\r
+ ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+ case kSerialPort_UsbCdc:\r
+ (void)Serial_UsbCdcCancelWrite(\r
+ ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))\r
+ case kSerialPort_Swo:\r
+ (void)Serial_SwoCancelWrite(\r
+ ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))\r
+ case kSerialPort_UsbCdcVirtual:\r
+ (void)Serial_UsbCdcVirtualCancelWrite(\r
+ ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));\r
+ break;\r
+#endif\r
+ default:\r
+ /*MISRA rule 16.4*/\r
+ break;\r
+ }\r
+ }\r
+\r
+ (void)SerialManager_StartWriting(serialWriteHandle->serialManagerHandle);\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle)\r
+{\r
+ serial_manager_read_handle_t *serialReadHandle;\r
+ serial_manager_callback_message_t msg;\r
+ uint8_t *buffer;\r
+ uint32_t primask;\r
+\r
+ assert(readHandle);\r
+\r
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;\r
+\r
+ assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag);\r
+\r
+ if ((NULL != serialReadHandle->transfer.buffer) &&\r
+ (kSerialManager_TransmissionBlocking == serialReadHandle->transfer.mode))\r
+ {\r
+ return kStatus_SerialManager_Error;\r
+ }\r
+\r
+ primask = DisableGlobalIRQ();\r
+ buffer = serialReadHandle->transfer.buffer;\r
+ serialReadHandle->transfer.buffer = NULL;\r
+ serialReadHandle->transfer.length = 0;\r
+ msg.buffer = buffer;\r
+ msg.length = serialReadHandle->transfer.soFar;\r
+ EnableGlobalIRQ(primask);\r
+\r
+ if (NULL != buffer)\r
+ {\r
+ if (NULL != serialReadHandle->callback)\r
+ {\r
+ serialReadHandle->callback(serialReadHandle->callbackParam, &msg, kStatus_SerialManager_Canceled);\r
+ }\r
+ }\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle,\r
+ uint8_t *buffer,\r
+ uint32_t length,\r
+ uint32_t *receivedLength)\r
+{\r
+ assert(receivedLength);\r
+\r
+ return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionBlocking, receivedLength);\r
+}\r
+\r
+serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle,\r
+ serial_manager_callback_t callback,\r
+ void *callbackParam)\r
+{\r
+ serial_manager_write_handle_t *serialWriteHandle;\r
+\r
+ assert(writeHandle);\r
+\r
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;\r
+\r
+ assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag);\r
+\r
+ serialWriteHandle->callbackParam = callbackParam;\r
+ serialWriteHandle->callback = callback;\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle,\r
+ serial_manager_callback_t callback,\r
+ void *callbackParam)\r
+{\r
+ serial_manager_read_handle_t *serialReadHandle;\r
+\r
+ assert(readHandle);\r
+\r
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;\r
+\r
+ assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag);\r
+\r
+ serialReadHandle->callbackParam = callbackParam;\r
+ serialReadHandle->callback = callback;\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+#endif\r
+\r
+serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle)\r
+{\r
+ serial_manager_handle_t *handle;\r
+ serial_manager_status_t status = kStatus_SerialManager_Error;\r
+\r
+ assert(serialHandle);\r
+\r
+ handle = (serial_manager_handle_t *)serialHandle;\r
+\r
+ switch (handle->type)\r
+ {\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+ case kSerialPort_Uart:\r
+ status = Serial_UartEnterLowpower(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+ case kSerialPort_UsbCdc:\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))\r
+ case kSerialPort_Swo:\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))\r
+ case kSerialPort_UsbCdcVirtual:\r
+ break;\r
+#endif\r
+ default:\r
+ /*MISRA rule 16.4*/\r
+ break;\r
+ }\r
+ return status;\r
+}\r
+\r
+serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle)\r
+{\r
+ serial_manager_handle_t *handle;\r
+ serial_manager_status_t status = kStatus_SerialManager_Error;\r
+\r
+ assert(serialHandle);\r
+\r
+ handle = (serial_manager_handle_t *)serialHandle;\r
+\r
+ switch (handle->type)\r
+ {\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+ case kSerialPort_Uart:\r
+ status = Serial_UartExitLowpower(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+ case kSerialPort_UsbCdc:\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))\r
+ case kSerialPort_Swo:\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))\r
+ case kSerialPort_UsbCdcVirtual:\r
+ break;\r
+#endif\r
+ default:\r
+ /*MISRA rule 16.4*/\r
+ break;\r
+ }\r
+ return status;\r
+}\r
--- /dev/null
+/*\r
+ * Copyright 2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#ifndef __SERIAL_MANAGER_H__\r
+#define __SERIAL_MANAGER_H__\r
+\r
+/*!\r
+ * @addtogroup serialmanager\r
+ * @{\r
+ */\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING\r
+/*! @brief Enable or disable serial manager non-blocking mode (1 - enable, 0 - disable) */\r
+#define SERIAL_MANAGER_NON_BLOCKING_MODE (1U)\r
+#else\r
+#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE\r
+#define SERIAL_MANAGER_NON_BLOCKING_MODE (0U)\r
+#endif\r
+#endif\r
+\r
+/*! @brief Enable or disable uart port (1 - enable, 0 - disable) */\r
+#ifndef SERIAL_PORT_TYPE_UART\r
+#define SERIAL_PORT_TYPE_UART (0U)\r
+#endif\r
+\r
+/*! @brief Enable or disable USB CDC port (1 - enable, 0 - disable) */\r
+#ifndef SERIAL_PORT_TYPE_USBCDC\r
+#define SERIAL_PORT_TYPE_USBCDC (0U)\r
+#endif\r
+\r
+/*! @brief Enable or disable SWO port (1 - enable, 0 - disable) */\r
+#ifndef SERIAL_PORT_TYPE_SWO\r
+#define SERIAL_PORT_TYPE_SWO (0U)\r
+#endif\r
+\r
+/*! @brief Enable or disable USB CDC virtual port (1 - enable, 0 - disable) */\r
+#ifndef SERIAL_PORT_TYPE_USBCDC_VIRTUAL\r
+#define SERIAL_PORT_TYPE_USBCDC_VIRTUAL (0U)\r
+#endif\r
+\r
+/*! @brief Set serial manager write handle size */\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (44U)\r
+#define SERIAL_MANAGER_READ_HANDLE_SIZE (44U)\r
+#else\r
+#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (4U)\r
+#define SERIAL_MANAGER_READ_HANDLE_SIZE (4U)\r
+#endif\r
+\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+#include "serial_port_uart.h"\r
+#endif\r
+\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+\r
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+#error The serial manager blocking mode cannot be supported for USB CDC.\r
+#endif\r
+\r
+#include "serial_port_usb.h"\r
+#endif\r
+\r
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))\r
+#include "serial_port_swo.h"\r
+#endif\r
+\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))\r
+\r
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+#error The serial manager blocking mode cannot be supported for USB CDC.\r
+#endif\r
+\r
+#include "serial_port_usb_virtual.h"\r
+#endif\r
+\r
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP 0U\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+\r
+#if (SERIAL_PORT_UART_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)\r
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP\r
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_UART_HANDLE_SIZE\r
+#endif\r
+\r
+#endif\r
+\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+\r
+#if (SERIAL_PORT_USB_CDC_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)\r
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP\r
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_CDC_HANDLE_SIZE\r
+#endif\r
+\r
+#endif\r
+\r
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))\r
+\r
+#if (SERIAL_PORT_SWO_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)\r
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP\r
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_SWO_HANDLE_SIZE\r
+#endif\r
+\r
+#endif\r
+\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))\r
+\r
+#if (SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)\r
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP\r
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE\r
+#endif\r
+\r
+#endif\r
+\r
+/*! @brief SERIAL_PORT_UART_HANDLE_SIZE/SERIAL_PORT_USB_CDC_HANDLE_SIZE + serial manager dedicated size */\r
+#if ((defined(SERIAL_MANAGER_HANDLE_SIZE_TEMP) && (SERIAL_MANAGER_HANDLE_SIZE_TEMP > 0U)))\r
+#else\r
+#error SERIAL_PORT_TYPE_UART, SERIAL_PORT_TYPE_USBCDC, SERIAL_PORT_TYPE_SWO and SERIAL_PORT_TYPE_USBCDC_VIRTUAL should not be cleared at same time.\r
+#endif\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 120U)\r
+#else\r
+#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 12U)\r
+#endif\r
+\r
+#define SERIAL_MANAGER_USE_COMMON_TASK (1U)\r
+#define SERIAL_MANAGER_TASK_PRIORITY (2U)\r
+#define SERIAL_MANAGER_TASK_STACK_SIZE (1000U)\r
+\r
+typedef void *serial_handle_t;\r
+typedef void *serial_write_handle_t;\r
+typedef void *serial_read_handle_t;\r
+\r
+/*! @brief serial port type*/\r
+typedef enum _serial_port_type\r
+{\r
+ kSerialPort_Uart = 1U, /*!< Serial port UART */\r
+ kSerialPort_UsbCdc, /*!< Serial port USB CDC */\r
+ kSerialPort_Swo, /*!< Serial port SWO */\r
+ kSerialPort_UsbCdcVirtual, /*!< Serial port USB CDC Virtual */\r
+} serial_port_type_t;\r
+\r
+/*! @brief serial manager config structure*/\r
+typedef struct _serial_manager_config\r
+{\r
+ uint8_t *ringBuffer; /*!< Ring buffer address, it is used to buffer data received by the hardware.\r
+ Besides, the memory space cannot be free during the lifetime of the serial\r
+ manager module. */\r
+ uint32_t ringBufferSize; /*!< The size of the ring buffer */\r
+ serial_port_type_t type; /*!< Serial port type */\r
+ void *portConfig; /*!< Serial port configuration */\r
+} serial_manager_config_t;\r
+\r
+/*! @brief serial manager error code*/\r
+typedef enum _serial_manager_status\r
+{\r
+ kStatus_SerialManager_Success = kStatus_Success, /*!< Success */\r
+ kStatus_SerialManager_Error = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 1), /*!< Failed */\r
+ kStatus_SerialManager_Busy = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 2), /*!< Busy */\r
+ kStatus_SerialManager_Notify = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 3), /*!< Ring buffer is not empty */\r
+ kStatus_SerialManager_Canceled =\r
+ MAKE_STATUS(kStatusGroup_SERIALMANAGER, 4), /*!< the non-blocking request is canceled */\r
+ kStatus_SerialManager_HandleConflict = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 5), /*!< The handle is opened */\r
+ kStatus_SerialManager_RingBufferOverflow =\r
+ MAKE_STATUS(kStatusGroup_SERIALMANAGER, 6), /*!< The ring buffer is overflowed */\r
+} serial_manager_status_t;\r
+\r
+/*! @brief Callback message structure */\r
+typedef struct _serial_manager_callback_message\r
+{\r
+ uint8_t *buffer; /*!< Transferred buffer */\r
+ uint32_t length; /*!< Transferred data length */\r
+} serial_manager_callback_message_t;\r
+\r
+/*! @brief callback function */\r
+typedef void (*serial_manager_callback_t)(void *callbackParam,\r
+ serial_manager_callback_message_t *message,\r
+ serial_manager_status_t status);\r
+\r
+/*******************************************************************************\r
+ * API\r
+ ******************************************************************************/\r
+\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif /* _cplusplus */\r
+\r
+/*!\r
+ * @brief Initializes a serial manager module with the serial manager handle and the user configuration structure.\r
+ *\r
+ * This function configures the Serial Manager module with user-defined settings. The user can configure the\r
+ * configuration\r
+ * structure. The parameter serialHandle is a pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE\r
+ * allocated by the caller.\r
+ * The Serial Manager module supports two types of serial port, UART (includes UART, USART, LPSCI, LPUART, etc) and USB\r
+ * CDC.\r
+ * Please refer to #serial_port_type_t for serial port setting. These two types can be set by using\r
+ * #serial_manager_config_t.\r
+ *\r
+ * Example below shows how to use this API to configure the Serial Manager.\r
+ * For UART,\r
+ * @code\r
+ * #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U)\r
+ * static uint32_t s_serialHandleBuffer[((SERIAL_MANAGER_HANDLE_SIZE + sizeof(uint32_t) - 1) / sizeof(uitn32_t))];\r
+ * static serial_handle_t s_serialHandle = (serial_handle_t)&s_serialHandleBuffer[0];\r
+ * static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];\r
+ *\r
+ * serial_manager_config_t config;\r
+ * serial_port_uart_config_t uartConfig;\r
+ * config.type = kSerialPort_Uart;\r
+ * config.ringBuffer = &s_ringBuffer[0];\r
+ * config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;\r
+ * uartConfig.instance = 0;\r
+ * uartConfig.clockRate = 24000000;\r
+ * uartConfig.baudRate = 115200;\r
+ * uartConfig.parityMode = kSerialManager_UartParityDisabled;\r
+ * uartConfig.stopBitCount = kSerialManager_UartOneStopBit;\r
+ * uartConfig.enableRx = 1;\r
+ * uartConfig.enableTx = 1;\r
+ * config.portConfig = &uartConfig;\r
+ * SerialManager_Init(s_serialHandle, &config);\r
+ * @endcode\r
+ * For USB CDC,\r
+ * @code\r
+ * #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U)\r
+ * static uint32_t s_serialHandleBuffer[((SERIAL_MANAGER_HANDLE_SIZE + sizeof(uint32_t) - 1) / sizeof(uitn32_t))];\r
+ * static serial_handle_t s_serialHandle = (serial_handle_t)&s_serialHandleBuffer[0];\r
+ * static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];\r
+ *\r
+ * serial_manager_config_t config;\r
+ * serial_port_usb_cdc_config_t usbCdcConfig;\r
+ * config.type = kSerialPort_UsbCdc;\r
+ * config.ringBuffer = &s_ringBuffer[0];\r
+ * config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;\r
+ * usbCdcConfig.controllerIndex = kSerialManager_UsbControllerKhci0;\r
+ * config.portConfig = &usbCdcConfig;\r
+ * SerialManager_Init(s_serialHandle, &config);\r
+ * @endcode\r
+ *\r
+ * @param serialHandle Pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE allocated by the caller.\r
+ * The handle should be 4 byte aligned, because unaligned access does not support on some devices.\r
+ * @param config Pointer to user-defined configuration structure.\r
+ * @retval kStatus_SerialManager_Error An error occurred.\r
+ * @retval kStatus_SerialManager_Success The Serial Manager module initialization succeed.\r
+ */\r
+serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, serial_manager_config_t *config);\r
+\r
+/*!\r
+ * @brief De-initializes the serial manager module instance.\r
+ *\r
+ * This function de-initializes the serial manager module instance. If the opened writing or\r
+ * reading handle is not closed, the function will return kStatus_SerialManager_Busy.\r
+ *\r
+ * @param serialHandle The serial manager module handle pointer.\r
+ * @retval kStatus_SerialManager_Success The serial manager de-initialization succeed.\r
+ * @retval kStatus_SerialManager_Busy Opened reading or writing handle is not closed.\r
+ */\r
+serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle);\r
+\r
+/*!\r
+ * @brief Opens a writing handle for the serial manager module.\r
+ *\r
+ * This function Opens a writing handle for the serial manager module. If the serial manager needs to\r
+ * be used in different tasks, the task should open a dedicated write handle for itself by calling\r
+ * #SerialManager_OpenWriteHandle. Since there can only one buffer for transmission for the writing\r
+ * handle at the same time, multiple writing handles need to be opened when the multiple transmission\r
+ * is needed for a task.\r
+ *\r
+ * @param serialHandle The serial manager module handle pointer.\r
+ * The handle should be 4 byte aligned, because unaligned access does not support on some devices.\r
+ * @param writeHandle The serial manager module writing handle pointer.\r
+ * The handle should be 4 byte aligned, because unaligned access does not support on some devices.\r
+ * @retval kStatus_SerialManager_Error An error occurred.\r
+ * @retval kStatus_SerialManager_HandleConflict The writing handle was opened.\r
+ * @retval kStatus_SerialManager_Success The writing handle is opened.\r
+ *\r
+ * Example below shows how to use this API to write data.\r
+ * For task 1,\r
+ * @code\r
+ * static uint32_t s_serialWriteHandleBuffer1[((SERIAL_MANAGER_WRITE_HANDLE_SIZE + sizeof(uint32_t) - 1) /\r
+ * sizeof(uitn32_t))]; static serial_write_handle_t s_serialWriteHandle1 =\r
+ * (serial_write_handle_t)&s_serialWriteHandleBuffer1[0]; static uint8_t s_nonBlockingWelcome1[] = "This is non-blocking\r
+ * writing log for task1!\r\n"; SerialManager_OpenWriteHandle(serialHandle, s_serialWriteHandle1);\r
+ * SerialManager_InstallTxCallback(s_serialWriteHandle1, Task1_SerialManagerTxCallback, s_serialWriteHandle1);\r
+ * SerialManager_WriteNonBlocking(s_serialWriteHandle1, s_nonBlockingWelcome1, sizeof(s_nonBlockingWelcome1) - 1);\r
+ * @endcode\r
+ * For task 2,\r
+ * @code\r
+ * static uint32_t s_serialWriteHandleBuffer2[((SERIAL_MANAGER_WRITE_HANDLE_SIZE + sizeof(uint32_t) - 1) /\r
+ * sizeof(uitn32_t))]; static serial_write_handle_t s_serialWriteHandle2 =\r
+ * (serial_write_handle_t)&s_serialWriteHandleBuffer2[0]; static uint8_t s_nonBlockingWelcome2[] = "This is non-blocking\r
+ * writing log for task2!\r\n"; SerialManager_OpenWriteHandle(serialHandle, s_serialWriteHandle2);\r
+ * SerialManager_InstallTxCallback(s_serialWriteHandle2, Task2_SerialManagerTxCallback, s_serialWriteHandle2);\r
+ * SerialManager_WriteNonBlocking(s_serialWriteHandle2, s_nonBlockingWelcome2, sizeof(s_nonBlockingWelcome2) - 1);\r
+ * @endcode\r
+ */\r
+serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle);\r
+\r
+/*!\r
+ * @brief Closes a writing handle for the serial manager module.\r
+ *\r
+ * This function Closes a writing handle for the serial manager module.\r
+ *\r
+ * @param writeHandle The serial manager module writing handle pointer.\r
+ * @retval kStatus_SerialManager_Success The writing handle is closed.\r
+ */\r
+serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle);\r
+\r
+/*!\r
+ * @brief Opens a reading handle for the serial manager module.\r
+ *\r
+ * This function Opens a reading handle for the serial manager module. The reading handle can not be\r
+ * opened multiple at the same time. The error code kStatus_SerialManager_Busy would be returned when\r
+ * the previous reading handle is not closed. And There can only be one buffer for receiving for the\r
+ * reading handle at the same time.\r
+ *\r
+ * @param serialHandle The serial manager module handle pointer.\r
+ * The handle should be 4 byte aligned, because unaligned access does not support on some devices.\r
+ * @param readHandle The serial manager module reading handle pointer.\r
+ * The handle should be 4 byte aligned, because unaligned access does not support on some devices.\r
+ * @retval kStatus_SerialManager_Error An error occurred.\r
+ * @retval kStatus_SerialManager_Success The reading handle is opened.\r
+ * @retval kStatus_SerialManager_Busy Previous reading handle is not closed.\r
+ *\r
+ * Example below shows how to use this API to read data.\r
+ * @code\r
+ * static uint32_t s_serialReadHandleBuffer[((SERIAL_MANAGER_READ_HANDLE_SIZE + sizeof(uint32_t) - 1) /\r
+ * sizeof(uitn32_t))]; static serial_read_handle_t s_serialReadHandle =\r
+ * (serial_read_handle_t)&s_serialReadHandleBuffer[0]; SerialManager_OpenReadHandle(serialHandle, s_serialReadHandle);\r
+ * static uint8_t s_nonBlockingBuffer[64];\r
+ * SerialManager_InstallRxCallback(s_serialReadHandle, APP_SerialManagerRxCallback, s_serialReadHandle);\r
+ * SerialManager_ReadNonBlocking(s_serialReadHandle, s_nonBlockingBuffer, sizeof(s_nonBlockingBuffer));\r
+ * @endcode\r
+ */\r
+serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle);\r
+\r
+/*!\r
+ * @brief Closes a reading for the serial manager module.\r
+ *\r
+ * This function Closes a reading for the serial manager module.\r
+ *\r
+ * @param readHandle The serial manager module reading handle pointer.\r
+ * @retval kStatus_SerialManager_Success The reading handle is closed.\r
+ */\r
+serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle);\r
+\r
+/*!\r
+ * @brief Transmits data with the blocking mode.\r
+ *\r
+ * This is a blocking function, which polls the sending queue, waits for the sending queue to be empty.\r
+ * This function sends data using an interrupt method. The interrupt of the hardware could not be disabled.\r
+ * And There can only one buffer for transmission for the writing handle at the same time.\r
+ *\r
+ * @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking\r
+ * cannot be used at the same time.\r
+ * And, the function #SerialManager_CancelWriting cannot be used to abort the transmission of this function.\r
+ *\r
+ * @param writeHandle The serial manager module handle pointer.\r
+ * @param buffer Start address of the data to write.\r
+ * @param length Length of the data to write.\r
+ * @retval kStatus_SerialManager_Success Successfully sent all data.\r
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet.\r
+ * @retval kStatus_SerialManager_Error An error occurred.\r
+ */\r
+serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle,\r
+ uint8_t *buffer,\r
+ uint32_t length);\r
+\r
+/*!\r
+ * @brief Reads data with the blocking mode.\r
+ *\r
+ * This is a blocking function, which polls the receiving buffer, waits for the receiving buffer to be full.\r
+ * This function receives data using an interrupt method. The interrupt of the hardware could not be disabled.\r
+ * And There can only one buffer for receiving for the reading handle at the same time.\r
+ *\r
+ * @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking\r
+ * cannot be used at the same time.\r
+ * And, the function #SerialManager_CancelReading cannot be used to abort the transmission of this function.\r
+ *\r
+ * @param readHandle The serial manager module handle pointer.\r
+ * @param buffer Start address of the data to store the received data.\r
+ * @param length The length of the data to be received.\r
+ * @retval kStatus_SerialManager_Success Successfully received all data.\r
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.\r
+ * @retval kStatus_SerialManager_Error An error occurred.\r
+ */\r
+serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length);\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+/*!\r
+ * @brief Transmits data with the non-blocking mode.\r
+ *\r
+ * This is a non-blocking function, which returns directly without waiting for all data to be sent.\r
+ * When all data is sent, the module notifies the upper layer through a TX callback function and passes\r
+ * the status parameter @ref kStatus_SerialManager_Success.\r
+ * This function sends data using an interrupt method. The interrupt of the hardware could not be disabled.\r
+ * And There can only one buffer for transmission for the writing handle at the same time.\r
+ *\r
+ * @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking\r
+ * cannot be used at the same time. And, the TX callback is mandatory before the function could be used.\r
+ *\r
+ * @param writeHandle The serial manager module handle pointer.\r
+ * @param buffer Start address of the data to write.\r
+ * @param length Length of the data to write.\r
+ * @retval kStatus_SerialManager_Success Successfully sent all data.\r
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet.\r
+ * @retval kStatus_SerialManager_Error An error occurred.\r
+ */\r
+serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle,\r
+ uint8_t *buffer,\r
+ uint32_t length);\r
+\r
+/*!\r
+ * @brief Reads data with the non-blocking mode.\r
+ *\r
+ * This is a non-blocking function, which returns directly without waiting for all data to be received.\r
+ * When all data is received, the module driver notifies the upper layer\r
+ * through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Success.\r
+ * This function receives data using an interrupt method. The interrupt of the hardware could not be disabled.\r
+ * And There can only one buffer for receiving for the reading handle at the same time.\r
+ *\r
+ * @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking\r
+ * cannot be used at the same time. And, the RX callback is mandatory before the function could be used.\r
+ *\r
+ * @param readHandle The serial manager module handle pointer.\r
+ * @param buffer Start address of the data to store the received data.\r
+ * @param length The length of the data to be received.\r
+ * @retval kStatus_SerialManager_Success Successfully received all data.\r
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.\r
+ * @retval kStatus_SerialManager_Error An error occurred.\r
+ */\r
+serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle,\r
+ uint8_t *buffer,\r
+ uint32_t length);\r
+\r
+/*!\r
+ * @brief Tries to read data.\r
+ *\r
+ * The function tries to read data from internal ring buffer. If the ring buffer is not empty, the data will be\r
+ * copied from ring buffer to up layer buffer. The copied length is the minimum of the ring buffer and up layer length.\r
+ * After the data is copied, the actual data length is passed by the parameter length.\r
+ * And There can only one buffer for receiving for the reading handle at the same time.\r
+ *\r
+ * @param readHandle The serial manager module handle pointer.\r
+ * @param buffer Start address of the data to store the received data.\r
+ * @param length The length of the data to be received.\r
+ * @param receivedLength Length received from the ring buffer directly.\r
+ * @retval kStatus_SerialManager_Success Successfully received all data.\r
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.\r
+ * @retval kStatus_SerialManager_Error An error occurred.\r
+ */\r
+serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle,\r
+ uint8_t *buffer,\r
+ uint32_t length,\r
+ uint32_t *receivedLength);\r
+\r
+/*!\r
+ * @brief Cancels unfinished send transmission.\r
+ *\r
+ * The function cancels unfinished send transmission. When the transfer is canceled, the module notifies the upper layer\r
+ * through a TX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled.\r
+ *\r
+ * @note The function #SerialManager_CancelWriting cannot be used to abort the transmission of\r
+ * the function #SerialManager_WriteBlocking.\r
+ *\r
+ * @param writeHandle The serial manager module handle pointer.\r
+ * @retval kStatus_SerialManager_Success Get successfully abort the sending.\r
+ * @retval kStatus_SerialManager_Error An error occurred.\r
+ */\r
+serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle);\r
+\r
+/*!\r
+ * @brief Cancels unfinished receive transmission.\r
+ *\r
+ * The function cancels unfinished receive transmission. When the transfer is canceled, the module notifies the upper\r
+ * layer\r
+ * through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled.\r
+ *\r
+ * @note The function #SerialManager_CancelReading cannot be used to abort the transmission of\r
+ * the function #SerialManager_ReadBlocking.\r
+ *\r
+ * @param readHandle The serial manager module handle pointer.\r
+ * @retval kStatus_SerialManager_Success Get successfully abort the receiving.\r
+ * @retval kStatus_SerialManager_Error An error occurred.\r
+ */\r
+serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle);\r
+\r
+/*!\r
+ * @brief Installs a TX callback and callback parameter.\r
+ *\r
+ * This function is used to install the TX callback and callback parameter for the serial manager module.\r
+ * When any status of TX transmission changed, the driver will notify the upper layer by the installed callback\r
+ * function. And the status is also passed as status parameter when the callback is called.\r
+ *\r
+ * @param writeHandle The serial manager module handle pointer.\r
+ * @param callback The callback function.\r
+ * @param callbackParam The parameter of the callback function.\r
+ * @retval kStatus_SerialManager_Success Successfully install the callback.\r
+ */\r
+serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle,\r
+ serial_manager_callback_t callback,\r
+ void *callbackParam);\r
+\r
+/*!\r
+ * @brief Installs a RX callback and callback parameter.\r
+ *\r
+ * This function is used to install the RX callback and callback parameter for the serial manager module.\r
+ * When any status of RX transmission changed, the driver will notify the upper layer by the installed callback\r
+ * function. And the status is also passed as status parameter when the callback is called.\r
+ *\r
+ * @param readHandle The serial manager module handle pointer.\r
+ * @param callback The callback function.\r
+ * @param callbackParam The parameter of the callback function.\r
+ * @retval kStatus_SerialManager_Success Successfully install the callback.\r
+ */\r
+serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle,\r
+ serial_manager_callback_t callback,\r
+ void *callbackParam);\r
+\r
+#endif\r
+\r
+/*!\r
+ * @brief Prepares to enter low power consumption.\r
+ *\r
+ * This function is used to prepare to enter low power consumption.\r
+ *\r
+ * @param serialHandle The serial manager module handle pointer.\r
+ * @retval kStatus_SerialManager_Success Successful operation.\r
+ */\r
+serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle);\r
+\r
+/*!\r
+ * @brief Restores from low power consumption.\r
+ *\r
+ * This function is used to restore from low power consumption.\r
+ *\r
+ * @param serialHandle The serial manager module handle pointer.\r
+ * @retval kStatus_SerialManager_Success Successful operation.\r
+ */\r
+serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle);\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif\r
+/*! @} */\r
+#endif /* __SERIAL_MANAGER_H__ */\r
--- /dev/null
+/*\r
+ * Copyright 2019 NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#ifndef __SERIAL_PORT_INTERNAL_H__\r
+#define __SERIAL_PORT_INTERNAL_H__\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/*******************************************************************************\r
+ * API\r
+ ******************************************************************************/\r
+\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif /* _cplusplus */\r
+\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig);\r
+serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle);\r
+serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);\r
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);\r
+#endif\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle);\r
+serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle,\r
+ serial_manager_callback_t callback,\r
+ void *callbackParam);\r
+serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle,\r
+ serial_manager_callback_t callback,\r
+ void *callbackParam);\r
+void Serial_UartIsrFunction(serial_handle_t serialHandle);\r
+#endif\r
+serial_manager_status_t Serial_UartEnterLowpower(serial_handle_t serialHandle);\r
+serial_manager_status_t Serial_UartExitLowpower(serial_handle_t serialHandle);\r
+#endif\r
+\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+serial_manager_status_t Serial_UsbCdcInit(serial_handle_t serialHandle, void *config);\r
+serial_manager_status_t Serial_UsbCdcDeinit(serial_handle_t serialHandle);\r
+serial_manager_status_t Serial_UsbCdcWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);\r
+serial_manager_status_t Serial_UsbCdcRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);\r
+serial_manager_status_t Serial_UsbCdcCancelWrite(serial_handle_t serialHandle);\r
+serial_manager_status_t Serial_UsbCdcInstallTxCallback(serial_handle_t serialHandle,\r
+ serial_manager_callback_t callback,\r
+ void *callbackParam);\r
+serial_manager_status_t Serial_UsbCdcInstallRxCallback(serial_handle_t serialHandle,\r
+ serial_manager_callback_t callback,\r
+ void *callbackParam);\r
+void Serial_UsbCdcIsrFunction(serial_handle_t serialHandle);\r
+#endif\r
+\r
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))\r
+serial_manager_status_t Serial_SwoInit(serial_handle_t serialHandle, void *config);\r
+serial_manager_status_t Serial_SwoDeinit(serial_handle_t serialHandle);\r
+serial_manager_status_t Serial_SwoWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);\r
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+serial_manager_status_t Serial_SwoRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);\r
+#endif\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+serial_manager_status_t Serial_SwoCancelWrite(serial_handle_t serialHandle);\r
+serial_manager_status_t Serial_SwoInstallTxCallback(serial_handle_t serialHandle,\r
+ serial_manager_callback_t callback,\r
+ void *callbackParam);\r
+serial_manager_status_t Serial_SwoInstallRxCallback(serial_handle_t serialHandle,\r
+ serial_manager_callback_t callback,\r
+ void *callbackParam);\r
+void Serial_SwoIsrFunction(serial_handle_t serialHandle);\r
+#endif\r
+#endif\r
+\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))\r
+serial_manager_status_t Serial_UsbCdcVirtualInit(serial_handle_t serialHandle, void *config);\r
+serial_manager_status_t Serial_UsbCdcVirtualDeinit(serial_handle_t serialHandle);\r
+serial_manager_status_t Serial_UsbCdcVirtualWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);\r
+serial_manager_status_t Serial_UsbCdcVirtualRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);\r
+serial_manager_status_t Serial_UsbCdcVirtualCancelWrite(serial_handle_t serialHandle);\r
+serial_manager_status_t Serial_UsbCdcVirtualInstallTxCallback(serial_handle_t serialHandle,\r
+ serial_manager_callback_t callback,\r
+ void *callbackParam);\r
+serial_manager_status_t Serial_UsbCdcVirtualInstallRxCallback(serial_handle_t serialHandle,\r
+ serial_manager_callback_t callback,\r
+ void *callbackParam);\r
+void Serial_UsbCdcVirtualIsrFunction(serial_handle_t serialHandle);\r
+#endif\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif\r
+\r
+#endif /* __SERIAL_PORT_INTERNAL_H__ */\r
--- /dev/null
+/*\r
+ * Copyright 2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#include "fsl_common.h"\r
+#include "serial_manager.h"\r
+#include "serial_port_internal.h"\r
+\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+#include "uart.h"\r
+\r
+#include "serial_port_uart.h"\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+#ifndef NDEBUG\r
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))\r
+#undef assert\r
+#define assert(n)\r
+#endif\r
+#endif\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+#define SERIAL_PORT_UART_RECEIVE_DATA_LENGTH 1U\r
+\r
+typedef struct _serial_uart_send_state\r
+{\r
+ serial_manager_callback_t callback;\r
+ void *callbackParam;\r
+ uint8_t *buffer;\r
+ uint32_t length;\r
+ volatile uint8_t busy;\r
+} serial_uart_send_state_t;\r
+\r
+typedef struct _serial_uart_recv_state\r
+{\r
+ serial_manager_callback_t callback;\r
+ void *callbackParam;\r
+ volatile uint8_t busy;\r
+ uint8_t readBuffer[SERIAL_PORT_UART_RECEIVE_DATA_LENGTH];\r
+} serial_uart_recv_state_t;\r
+#endif\r
+\r
+typedef struct _serial_uart_state\r
+{\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ serial_uart_send_state_t tx;\r
+ serial_uart_recv_state_t rx;\r
+#endif\r
+ uint8_t usartHandleBuffer[HAL_UART_HANDLE_SIZE];\r
+} serial_uart_state_t;\r
+\r
+/*******************************************************************************\r
+ * Prototypes\r
+ ******************************************************************************/\r
+\r
+/*******************************************************************************\r
+ * Code\r
+ ******************************************************************************/\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+/* UART user callback */\r
+static void Serial_UartCallback(hal_uart_handle_t handle, hal_uart_status_t status, void *userData)\r
+{\r
+ serial_uart_state_t *serialUartHandle;\r
+ serial_manager_callback_message_t msg;\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+ hal_uart_transfer_t transfer;\r
+#endif\r
+\r
+ if (NULL == userData)\r
+ {\r
+ return;\r
+ }\r
+\r
+ serialUartHandle = (serial_uart_state_t *)userData;\r
+\r
+ if ((hal_uart_status_t)kStatus_HAL_UartRxIdle == status)\r
+ {\r
+ if ((NULL != serialUartHandle->rx.callback))\r
+ {\r
+ msg.buffer = &serialUartHandle->rx.readBuffer[0];\r
+ msg.length = sizeof(serialUartHandle->rx.readBuffer);\r
+ serialUartHandle->rx.callback(serialUartHandle->rx.callbackParam, &msg, kStatus_SerialManager_Success);\r
+ }\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+ transfer.data = &serialUartHandle->rx.readBuffer[0];\r
+ transfer.dataSize = sizeof(serialUartHandle->rx.readBuffer);\r
+ if (kStatus_HAL_UartSuccess ==\r
+ HAL_UartTransferReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer))\r
+#else\r
+ if ((hal_uart_status_t)kStatus_HAL_UartSuccess ==\r
+ HAL_UartReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),\r
+ &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer)))\r
+#endif\r
+ {\r
+ serialUartHandle->rx.busy = 1U;\r
+ }\r
+ else\r
+ {\r
+ serialUartHandle->rx.busy = 0U;\r
+ }\r
+ }\r
+ else if ((hal_uart_status_t)kStatus_HAL_UartTxIdle == status)\r
+ {\r
+ if (0U != serialUartHandle->tx.busy)\r
+ {\r
+ serialUartHandle->tx.busy = 0U;\r
+ if ((NULL != serialUartHandle->tx.callback))\r
+ {\r
+ msg.buffer = serialUartHandle->tx.buffer;\r
+ msg.length = serialUartHandle->tx.length;\r
+ serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &msg, kStatus_SerialManager_Success);\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ }\r
+}\r
+#endif\r
+\r
+serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig)\r
+{\r
+ serial_uart_state_t *serialUartHandle;\r
+ serial_port_uart_config_t *uartConfig;\r
+ hal_uart_config_t config;\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+ hal_uart_transfer_t transfer;\r
+#endif\r
+#endif\r
+\r
+ assert(serialConfig);\r
+ assert(serialHandle);\r
+ assert(SERIAL_PORT_UART_HANDLE_SIZE >= sizeof(serial_uart_state_t));\r
+\r
+ uartConfig = (serial_port_uart_config_t *)serialConfig;\r
+ serialUartHandle = (serial_uart_state_t *)serialHandle;\r
+\r
+ config.baudRate_Bps = uartConfig->baudRate;\r
+ config.parityMode = (hal_uart_parity_mode_t)uartConfig->parityMode;\r
+ config.stopBitCount = (hal_uart_stop_bit_count_t)uartConfig->stopBitCount;\r
+ config.enableRx = uartConfig->enableRx;\r
+ config.enableTx = uartConfig->enableTx;\r
+ config.srcClock_Hz = uartConfig->clockRate;\r
+ config.instance = uartConfig->instance;\r
+\r
+ if (kStatus_HAL_UartSuccess != HAL_UartInit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &config))\r
+ {\r
+ return kStatus_SerialManager_Error;\r
+ }\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+ if (kStatus_HAL_UartSuccess !=\r
+ HAL_UartTransferInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),\r
+ Serial_UartCallback, serialUartHandle))\r
+#else\r
+ if (kStatus_HAL_UartSuccess != HAL_UartInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),\r
+ Serial_UartCallback, serialUartHandle))\r
+#endif\r
+ {\r
+ return kStatus_SerialManager_Error;\r
+ }\r
+\r
+ if (0U != uartConfig->enableRx)\r
+ {\r
+ serialUartHandle->rx.busy = 1U;\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+ transfer.data = &serialUartHandle->rx.readBuffer[0];\r
+ transfer.dataSize = sizeof(serialUartHandle->rx.readBuffer);\r
+ if (kStatus_HAL_UartSuccess !=\r
+ HAL_UartTransferReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer))\r
+#else\r
+ if (kStatus_HAL_UartSuccess !=\r
+ HAL_UartReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),\r
+ &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer)))\r
+#endif\r
+ {\r
+ serialUartHandle->rx.busy = 0U;\r
+ return kStatus_SerialManager_Error;\r
+ }\r
+ }\r
+#endif\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle)\r
+{\r
+ serial_uart_state_t *serialUartHandle;\r
+\r
+ assert(serialHandle);\r
+\r
+ serialUartHandle = (serial_uart_state_t *)serialHandle;\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+ (void)HAL_UartTransferAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));\r
+#else\r
+ (void)HAL_UartAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));\r
+#endif\r
+#endif\r
+ (void)HAL_UartDeinit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ serialUartHandle->tx.busy = 0U;\r
+ serialUartHandle->rx.busy = 0U;\r
+#endif\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+\r
+serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)\r
+{\r
+ serial_uart_state_t *serialUartHandle;\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+ hal_uart_transfer_t transfer;\r
+#endif\r
+\r
+ assert(serialHandle);\r
+ assert(buffer);\r
+ assert(length);\r
+\r
+ serialUartHandle = (serial_uart_state_t *)serialHandle;\r
+\r
+ if (0U != serialUartHandle->tx.busy)\r
+ {\r
+ return kStatus_SerialManager_Busy;\r
+ }\r
+ serialUartHandle->tx.busy = 1U;\r
+\r
+ serialUartHandle->tx.buffer = buffer;\r
+ serialUartHandle->tx.length = length;\r
+\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+ transfer.data = buffer;\r
+ transfer.dataSize = length;\r
+ if (kStatus_HAL_UartSuccess !=\r
+ HAL_UartTransferSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer))\r
+#else\r
+ if (kStatus_HAL_UartSuccess !=\r
+ HAL_UartSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length))\r
+#endif\r
+ {\r
+ serialUartHandle->tx.busy = 0U;\r
+ return kStatus_SerialManager_Error;\r
+ }\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+#else\r
+\r
+serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)\r
+{\r
+ serial_uart_state_t *serialUartHandle;\r
+\r
+ assert(serialHandle);\r
+ assert(buffer);\r
+ assert(length);\r
+\r
+ serialUartHandle = (serial_uart_state_t *)serialHandle;\r
+\r
+ return (serial_manager_status_t)HAL_UartSendBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),\r
+ buffer, length);\r
+}\r
+\r
+serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)\r
+{\r
+ serial_uart_state_t *serialUartHandle;\r
+\r
+ assert(serialHandle);\r
+ assert(buffer);\r
+ assert(length);\r
+\r
+ serialUartHandle = (serial_uart_state_t *)serialHandle;\r
+\r
+ return (serial_manager_status_t)HAL_UartReceiveBlocking(\r
+ ((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length);\r
+}\r
+\r
+#endif\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle)\r
+{\r
+ serial_uart_state_t *serialUartHandle;\r
+ serial_manager_callback_message_t msg;\r
+ uint32_t primask;\r
+ uint8_t isBusy = 0U;\r
+\r
+ assert(serialHandle);\r
+\r
+ serialUartHandle = (serial_uart_state_t *)serialHandle;\r
+\r
+ primask = DisableGlobalIRQ();\r
+ isBusy = serialUartHandle->tx.busy;\r
+ serialUartHandle->tx.busy = 0U;\r
+ EnableGlobalIRQ(primask);\r
+\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+ (void)HAL_UartTransferAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));\r
+#else\r
+ (void)HAL_UartAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));\r
+#endif\r
+ if (0U != isBusy)\r
+ {\r
+ if ((NULL != serialUartHandle->tx.callback))\r
+ {\r
+ msg.buffer = serialUartHandle->tx.buffer;\r
+ msg.length = serialUartHandle->tx.length;\r
+ serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &msg, kStatus_SerialManager_Canceled);\r
+ }\r
+ }\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle,\r
+ serial_manager_callback_t callback,\r
+ void *callbackParam)\r
+{\r
+ serial_uart_state_t *serialUartHandle;\r
+\r
+ assert(serialHandle);\r
+\r
+ serialUartHandle = (serial_uart_state_t *)serialHandle;\r
+\r
+ serialUartHandle->tx.callback = callback;\r
+ serialUartHandle->tx.callbackParam = callbackParam;\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle,\r
+ serial_manager_callback_t callback,\r
+ void *callbackParam)\r
+{\r
+ serial_uart_state_t *serialUartHandle;\r
+\r
+ assert(serialHandle);\r
+\r
+ serialUartHandle = (serial_uart_state_t *)serialHandle;\r
+\r
+ serialUartHandle->rx.callback = callback;\r
+ serialUartHandle->rx.callbackParam = callbackParam;\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+void Serial_UartIsrFunction(serial_handle_t serialHandle)\r
+{\r
+ serial_uart_state_t *serialUartHandle;\r
+\r
+ assert(serialHandle);\r
+\r
+ serialUartHandle = (serial_uart_state_t *)serialHandle;\r
+\r
+ HAL_UartIsrFunction(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));\r
+}\r
+#endif\r
+\r
+serial_manager_status_t Serial_UartEnterLowpower(serial_handle_t serialHandle)\r
+{\r
+ serial_uart_state_t *serialUartHandle;\r
+\r
+ assert(serialHandle);\r
+\r
+ serialUartHandle = (serial_uart_state_t *)serialHandle;\r
+\r
+ if (kStatus_HAL_UartSuccess != HAL_UartEnterLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])))\r
+ {\r
+ return kStatus_SerialManager_Error;\r
+ }\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+serial_manager_status_t Serial_UartExitLowpower(serial_handle_t serialHandle)\r
+{\r
+ serial_uart_state_t *serialUartHandle;\r
+\r
+ assert(serialHandle);\r
+\r
+ serialUartHandle = (serial_uart_state_t *)serialHandle;\r
+\r
+ if (kStatus_HAL_UartSuccess != HAL_UartExitLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])))\r
+ {\r
+ return kStatus_SerialManager_Error;\r
+ }\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+#endif\r
--- /dev/null
+/*\r
+ * Copyright 2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#ifndef __SERIAL_PORT_UART_H__\r
+#define __SERIAL_PORT_UART_H__\r
+\r
+#include "uart.h"\r
+\r
+/*!\r
+ * @addtogroup serial_port_uart\r
+ * @{\r
+ */\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+/*! @brief serial port uart handle size*/\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+#define SERIAL_PORT_UART_HANDLE_SIZE (76U + HAL_UART_HANDLE_SIZE)\r
+#else\r
+#define SERIAL_PORT_UART_HANDLE_SIZE (HAL_UART_HANDLE_SIZE)\r
+#endif\r
+\r
+/*! @brief serial port uart parity mode*/\r
+typedef enum _serial_port_uart_parity_mode\r
+{\r
+ kSerialManager_UartParityDisabled = 0x0U, /*!< Parity disabled */\r
+ kSerialManager_UartParityEven = 0x1U, /*!< Parity even enabled */\r
+ kSerialManager_UartParityOdd = 0x2U, /*!< Parity odd enabled */\r
+} serial_port_uart_parity_mode_t;\r
+\r
+/*! @brief serial port uart stop bit count*/\r
+typedef enum _serial_port_uart_stop_bit_count\r
+{\r
+ kSerialManager_UartOneStopBit = 0U, /*!< One stop bit */\r
+ kSerialManager_UartTwoStopBit = 1U, /*!< Two stop bits */\r
+} serial_port_uart_stop_bit_count_t;\r
+\r
+/*! @brief serial port uart config struct*/\r
+typedef struct _serial_port_uart_config\r
+{\r
+ uint32_t clockRate; /*!< clock rate */\r
+ uint32_t baudRate; /*!< baud rate */\r
+ serial_port_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */\r
+ serial_port_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */\r
+ uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information\r
+ please refer to the SOC corresponding RM. */\r
+ uint8_t enableRx; /*!< Enable RX */\r
+ uint8_t enableTx; /*!< Enable TX */\r
+} serial_port_uart_config_t;\r
+/*! @} */\r
+#endif /* __SERIAL_PORT_UART_H__ */\r
--- /dev/null
+/*\r
+ * Copyright 2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#ifndef __HAL_UART_ADAPTER_H__\r
+#define __HAL_UART_ADAPTER_H__\r
+\r
+#if defined(FSL_RTOS_FREE_RTOS)\r
+#include "FreeRTOS.h"\r
+#endif\r
+\r
+/*!\r
+ * @addtogroup UART_Adapter\r
+ * @{\r
+ */\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/*! @brief Enable or disable UART adapter non-blocking mode (1 - enable, 0 - disable) */\r
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING\r
+#define UART_ADAPTER_NON_BLOCKING_MODE (1U)\r
+#else\r
+#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE\r
+#define UART_ADAPTER_NON_BLOCKING_MODE (0U)\r
+#else\r
+#define UART_ADAPTER_NON_BLOCKING_MODE SERIAL_MANAGER_NON_BLOCKING_MODE\r
+#endif\r
+#endif\r
+\r
+#if defined(__GIC_PRIO_BITS)\r
+#define HAL_UART_ISR_PRIORITY (25U)\r
+#else\r
+#if defined(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)\r
+#define HAL_UART_ISR_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)\r
+#else\r
+/* The default value 3 is used to support different ARM Core, such as CM0P, CM4, CM7, and CM33, etc.\r
+ * The minimum number of priority bits implemented in the NVIC is 2 on these SOCs. The value of mininum\r
+ * priority is 3 (2^2 - 1). So, the default value is 3.\r
+ */\r
+#define HAL_UART_ISR_PRIORITY (3U)\r
+#endif\r
+#endif\r
+\r
+#ifndef HAL_UART_ADAPTER_LOWPOWER\r
+#define HAL_UART_ADAPTER_LOWPOWER (0U)\r
+#endif /* HAL_UART_ADAPTER_LOWPOWER */\r
+\r
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))\r
+#define HAL_UART_HANDLE_SIZE (90U + HAL_UART_ADAPTER_LOWPOWER * 16U)\r
+#else\r
+#define HAL_UART_HANDLE_SIZE (4U + HAL_UART_ADAPTER_LOWPOWER * 16U)\r
+#endif\r
+\r
+/*! @brief Whether enable transactional function of the UART. (0 - disable, 1 - enable) */\r
+#define HAL_UART_TRANSFER_MODE (0U)\r
+\r
+typedef void *hal_uart_handle_t;\r
+\r
+/*! @brief UART status */\r
+typedef enum _hal_uart_status\r
+{\r
+ kStatus_HAL_UartSuccess = kStatus_Success, /*!< Successfully */\r
+ kStatus_HAL_UartTxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 1), /*!< TX busy */\r
+ kStatus_HAL_UartRxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 2), /*!< RX busy */\r
+ kStatus_HAL_UartTxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 3), /*!< HAL UART transmitter is idle. */\r
+ kStatus_HAL_UartRxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 4), /*!< HAL UART receiver is idle */\r
+ kStatus_HAL_UartBaudrateNotSupport =\r
+ MAKE_STATUS(kStatusGroup_HAL_UART, 5), /*!< Baudrate is not support in current clock source */\r
+ kStatus_HAL_UartProtocolError = MAKE_STATUS(\r
+ kStatusGroup_HAL_UART,\r
+ 6), /*!< Error occurs for Noise, Framing, Parity, etc.\r
+ For transactional transfer, The up layer needs to abort the transfer and then starts again */\r
+ kStatus_HAL_UartError = MAKE_STATUS(kStatusGroup_HAL_UART, 7), /*!< Error occurs on HAL UART */\r
+} hal_uart_status_t;\r
+\r
+/*! @brief UART parity mode. */\r
+typedef enum _hal_uart_parity_mode\r
+{\r
+ kHAL_UartParityDisabled = 0x0U, /*!< Parity disabled */\r
+ kHAL_UartParityEven = 0x1U, /*!< Parity even enabled */\r
+ kHAL_UartParityOdd = 0x2U, /*!< Parity odd enabled */\r
+} hal_uart_parity_mode_t;\r
+\r
+/*! @brief UART stop bit count. */\r
+typedef enum _hal_uart_stop_bit_count\r
+{\r
+ kHAL_UartOneStopBit = 0U, /*!< One stop bit */\r
+ kHAL_UartTwoStopBit = 1U, /*!< Two stop bits */\r
+} hal_uart_stop_bit_count_t;\r
+\r
+/*! @brief UART configuration structure. */\r
+typedef struct _hal_uart_config\r
+{\r
+ uint32_t srcClock_Hz; /*!< Source clock */\r
+ uint32_t baudRate_Bps; /*!< Baud rate */\r
+ hal_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */\r
+ hal_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */\r
+ uint8_t enableRx; /*!< Enable RX */\r
+ uint8_t enableTx; /*!< Enable TX */\r
+ uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information please refer to the\r
+ SOC corresponding RM.\r
+ Invalid instance value will cause initialization failure. */\r
+} hal_uart_config_t;\r
+\r
+/*! @brief UART transfer callback function. */\r
+typedef void (*hal_uart_transfer_callback_t)(hal_uart_handle_t handle, hal_uart_status_t status, void *callbackParam);\r
+\r
+/*! @brief UART transfer structure. */\r
+typedef struct _hal_uart_transfer\r
+{\r
+ uint8_t *data; /*!< The buffer of data to be transfer.*/\r
+ size_t dataSize; /*!< The byte count to be transfer. */\r
+} hal_uart_transfer_t;\r
+\r
+/*******************************************************************************\r
+ * API\r
+ ******************************************************************************/\r
+\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif /* _cplusplus */\r
+\r
+/*!\r
+ * @name Initialization and deinitialization\r
+ * @{\r
+ */\r
+\r
+/*!\r
+ * @brief Initializes a UART instance with the UART handle and the user configuration structure.\r
+ *\r
+ * This function configures the UART module with user-defined settings. The user can configure the configuration\r
+ * structure. The parameter handle is a pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by\r
+ * the caller. Example below shows how to use this API to configure the UART.\r
+ * @code\r
+ * uint32_t g_UartHandleBuffer[((HAL_UART_HANDLE_SIZE + sizeof(uint32_t) - 1) / sizeof(uitn32_t))];\r
+ * hal_uart_handle_t g_UartHandle = (hal_uart_handle_t)&g_UartHandleBuffer[0];\r
+ * hal_uart_config_t config;\r
+ * config.srcClock_Hz = 48000000;\r
+ * config.baudRate_Bps = 115200U;\r
+ * config.parityMode = kHAL_UartParityDisabled;\r
+ * config.stopBitCount = kHAL_UartOneStopBit;\r
+ * config.enableRx = 1;\r
+ * config.enableTx = 1;\r
+ * config.instance = 0;\r
+ * HAL_UartInit(g_UartHandle, &config);\r
+ * @endcode\r
+ *\r
+ * @param handle Pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by the caller.\r
+ * The handle should be 4 byte aligned, because unaligned access does not support on some devices.\r
+ * @param config Pointer to user-defined configuration structure.\r
+ * @retval kStatus_HAL_UartBaudrateNotSupport Baudrate is not support in current clock source.\r
+ * @retval kStatus_HAL_UartSuccess UART initialization succeed\r
+ */\r
+hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, hal_uart_config_t *config);\r
+\r
+/*!\r
+ * @brief Deinitializes a UART instance.\r
+ *\r
+ * This function waits for TX complete, disables TX and RX, and disables the UART clock.\r
+ *\r
+ * @param handle UART handle pointer.\r
+ * @retval kStatus_HAL_UartSuccess UART de-initialization succeed\r
+ */\r
+hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle);\r
+\r
+/*! @}*/\r
+\r
+/*!\r
+ * @name Blocking bus Operations\r
+ * @{\r
+ */\r
+\r
+/*!\r
+ * @brief Reads RX data register using a blocking method.\r
+ *\r
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to\r
+ * have data, and reads data from the RX register.\r
+ *\r
+ * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking\r
+ * cannot be used at the same time.\r
+ * And, the function #HAL_UartTransferAbortReceive cannot be used to abort the transmission of this function.\r
+ *\r
+ * @param handle UART handle pointer.\r
+ * @param data Start address of the buffer to store the received data.\r
+ * @param length Size of the buffer.\r
+ * @retval kStatus_HAL_UartError An error occurred while receiving data.\r
+ * @retval kStatus_HAL_UartParityError A parity error occurred while receiving data.\r
+ * @retval kStatus_HAL_UartSuccess Successfully received all data.\r
+ */\r
+hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);\r
+\r
+/*!\r
+ * @brief Writes to the TX register using a blocking method.\r
+ *\r
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO\r
+ * to have room and writes data to the TX buffer.\r
+ *\r
+ * @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking\r
+ * cannot be used at the same time.\r
+ * And, the function #HAL_UartTransferAbortSend cannot be used to abort the transmission of this function.\r
+ *\r
+ * @param handle UART handle pointer.\r
+ * @param data Start address of the data to write.\r
+ * @param length Size of the data to write.\r
+ * @retval kStatus_HAL_UartSuccess Successfully sent all data.\r
+ */\r
+hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length);\r
+\r
+/*! @}*/\r
+\r
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+\r
+/*!\r
+ * @name Transactional\r
+ * @note The transactional API and the functional API cannot be used at the same time. The macro\r
+ * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the\r
+ * functional API with non-blocking mode will be used. Otherwise, transactional API will be used.\r
+ * @{\r
+ */\r
+\r
+/*!\r
+ * @brief Installs a callback and callback parameter.\r
+ *\r
+ * This function is used to install the callback and callback parameter for UART module.\r
+ * When any status of the UART changed, the driver will notify the upper layer by the installed callback\r
+ * function. And the status is also passed as status parameter when the callback is called.\r
+ *\r
+ * @param handle UART handle pointer.\r
+ * @param callback The callback function.\r
+ * @param callbackParam The parameter of the callback function.\r
+ * @retval kStatus_HAL_UartSuccess Successfully install the callback.\r
+ */\r
+hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle,\r
+ hal_uart_transfer_callback_t callback,\r
+ void *callbackParam);\r
+\r
+/*!\r
+ * @brief Receives a buffer of data using an interrupt method.\r
+ *\r
+ * This function receives data using an interrupt method. This is a non-blocking function, which\r
+ * returns directly without waiting for all data to be received.\r
+ * The receive request is saved by the UART driver.\r
+ * When the new data arrives, the receive request is serviced first.\r
+ * When all data is received, the UART driver notifies the upper layer\r
+ * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle.\r
+ *\r
+ * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking\r
+ * cannot be used at the same time.\r
+ *\r
+ * @param handle UART handle pointer.\r
+ * @param transfer UART transfer structure, see #hal_uart_transfer_t.\r
+ * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue.\r
+ * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished.\r
+ * @retval kStatus_HAL_UartError An error occurred.\r
+ */\r
+hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer);\r
+\r
+/*!\r
+ * @brief Transmits a buffer of data using the interrupt method.\r
+ *\r
+ * This function sends data using an interrupt method. This is a non-blocking function, which\r
+ * returns directly without waiting for all data to be written to the TX register. When\r
+ * all data is written to the TX register in the ISR, the UART driver calls the callback\r
+ * function and passes the @ref kStatus_UART_TxIdle as status parameter.\r
+ *\r
+ * @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking\r
+ * cannot be used at the same time.\r
+ *\r
+ * @param handle UART handle pointer.\r
+ * @param transfer UART transfer structure. See #hal_uart_transfer_t.\r
+ * @retval kStatus_HAL_UartSuccess Successfully start the data transmission.\r
+ * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet.\r
+ * @retval kStatus_HAL_UartError An error occurred.\r
+ */\r
+hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer);\r
+\r
+/*!\r
+ * @brief Gets the number of bytes that have been received.\r
+ *\r
+ * This function gets the number of bytes that have been received.\r
+ *\r
+ * @param handle UART handle pointer.\r
+ * @param count Receive bytes count.\r
+ * @retval kStatus_HAL_UartError An error occurred.\r
+ * @retval kStatus_Success Get successfully through the parameter \p count.\r
+ */\r
+hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count);\r
+\r
+/*!\r
+ * @brief Gets the number of bytes written to the UART TX register.\r
+ *\r
+ * This function gets the number of bytes written to the UART TX\r
+ * register by using the interrupt method.\r
+ *\r
+ * @param handle UART handle pointer.\r
+ * @param count Send bytes count.\r
+ * @retval kStatus_HAL_UartError An error occurred.\r
+ * @retval kStatus_Success Get successfully through the parameter \p count.\r
+ */\r
+hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count);\r
+\r
+/*!\r
+ * @brief Aborts the interrupt-driven data receiving.\r
+ *\r
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know\r
+ * how many bytes are not received yet.\r
+ *\r
+ * @note The function #HAL_UartTransferAbortReceive cannot be used to abort the transmission of\r
+ * the function #HAL_UartReceiveBlocking.\r
+ *\r
+ * @param handle UART handle pointer.\r
+ * @retval kStatus_Success Get successfully abort the receiving.\r
+ */\r
+hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle);\r
+\r
+/*!\r
+ * @brief Aborts the interrupt-driven data sending.\r
+ *\r
+ * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out\r
+ * how many bytes are not sent out.\r
+ *\r
+ * @note The function #HAL_UartTransferAbortSend cannot be used to abort the transmission of\r
+ * the function #HAL_UartSendBlocking.\r
+ *\r
+ * @param handle UART handle pointer.\r
+ * @retval kStatus_Success Get successfully abort the sending.\r
+ */\r
+hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle);\r
+\r
+/*! @}*/\r
+\r
+#else\r
+\r
+/*!\r
+ * @name Functional API with non-blocking mode.\r
+ * @note The functional API and the transactional API cannot be used at the same time. The macro\r
+ * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the\r
+ * functional API with non-blocking mode will be used. Otherwise, transactional API will be used.\r
+ * @{\r
+ */\r
+\r
+/*!\r
+ * @brief Installs a callback and callback parameter.\r
+ *\r
+ * This function is used to install the callback and callback parameter for UART module.\r
+ * When non-blocking sending or receiving finished, the adapter will notify the upper layer by the installed callback\r
+ * function. And the status is also passed as status parameter when the callback is called.\r
+ *\r
+ * @param handle UART handle pointer.\r
+ * @param callback The callback function.\r
+ * @param callbackParam The parameter of the callback function.\r
+ * @retval kStatus_HAL_UartSuccess Successfully install the callback.\r
+ */\r
+hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle,\r
+ hal_uart_transfer_callback_t callback,\r
+ void *callbackParam);\r
+\r
+/*!\r
+ * @brief Receives a buffer of data using an interrupt method.\r
+ *\r
+ * This function receives data using an interrupt method. This is a non-blocking function, which\r
+ * returns directly without waiting for all data to be received.\r
+ * The receive request is saved by the UART adapter.\r
+ * When the new data arrives, the receive request is serviced first.\r
+ * When all data is received, the UART adapter notifies the upper layer\r
+ * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle.\r
+ *\r
+ * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartReceiveNonBlocking\r
+ * cannot be used at the same time.\r
+ *\r
+ * @param handle UART handle pointer.\r
+ * @param data Start address of the data to write.\r
+ * @param length Size of the data to write.\r
+ * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue.\r
+ * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished.\r
+ * @retval kStatus_HAL_UartError An error occurred.\r
+ */\r
+hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);\r
+\r
+/*!\r
+ * @brief Transmits a buffer of data using the interrupt method.\r
+ *\r
+ * This function sends data using an interrupt method. This is a non-blocking function, which\r
+ * returns directly without waiting for all data to be written to the TX register. When\r
+ * all data is written to the TX register in the ISR, the UART driver calls the callback\r
+ * function and passes the @ref kStatus_UART_TxIdle as status parameter.\r
+ *\r
+ * @note The function #HAL_UartSendBlocking and the function #HAL_UartSendNonBlocking\r
+ * cannot be used at the same time.\r
+ *\r
+ * @param handle UART handle pointer.\r
+ * @param data Start address of the data to write.\r
+ * @param length Size of the data to write.\r
+ * @retval kStatus_HAL_UartSuccess Successfully start the data transmission.\r
+ * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet.\r
+ * @retval kStatus_HAL_UartError An error occurred.\r
+ */\r
+hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);\r
+\r
+/*!\r
+ * @brief Gets the number of bytes that have been received.\r
+ *\r
+ * This function gets the number of bytes that have been received.\r
+ *\r
+ * @param handle UART handle pointer.\r
+ * @param count Receive bytes count.\r
+ * @retval kStatus_HAL_UartError An error occurred.\r
+ * @retval kStatus_Success Get successfully through the parameter \p count.\r
+ */\r
+hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount);\r
+\r
+/*!\r
+ * @brief Gets the number of bytes written to the UART TX register.\r
+ *\r
+ * This function gets the number of bytes written to the UART TX\r
+ * register by using the interrupt method.\r
+ *\r
+ * @param handle UART handle pointer.\r
+ * @param count Send bytes count.\r
+ * @retval kStatus_HAL_UartError An error occurred.\r
+ * @retval kStatus_Success Get successfully through the parameter \p count.\r
+ */\r
+hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount);\r
+\r
+/*!\r
+ * @brief Aborts the interrupt-driven data receiving.\r
+ *\r
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know\r
+ * how many bytes are not received yet.\r
+ *\r
+ * @note The function #HAL_UartAbortReceive cannot be used to abort the transmission of\r
+ * the function #HAL_UartReceiveBlocking.\r
+ *\r
+ * @param handle UART handle pointer.\r
+ * @retval kStatus_Success Get successfully abort the receiving.\r
+ */\r
+hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle);\r
+\r
+/*!\r
+ * @brief Aborts the interrupt-driven data sending.\r
+ *\r
+ * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out\r
+ * how many bytes are not sent out.\r
+ *\r
+ * @note The function #HAL_UartAbortSend cannot be used to abort the transmission of\r
+ * the function #HAL_UartSendBlocking.\r
+ *\r
+ * @param handle UART handle pointer.\r
+ * @retval kStatus_Success Get successfully abort the sending.\r
+ */\r
+hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle);\r
+\r
+/*! @}*/\r
+\r
+#endif\r
+#endif\r
+\r
+/*!\r
+ * @brief Prepares to enter low power consumption.\r
+ *\r
+ * This function is used to prepare to enter low power consumption.\r
+ *\r
+ * @param handle UART handle pointer.\r
+ * @retval kStatus_HAL_UartSuccess Successful operation.\r
+ * @retval kStatus_HAL_UartError An error occurred.\r
+ */\r
+hal_uart_status_t HAL_UartEnterLowpower(hal_uart_handle_t handle);\r
+\r
+/*!\r
+ * @brief Restores from low power consumption.\r
+ *\r
+ * This function is used to restore from low power consumption.\r
+ *\r
+ * @param handle UART handle pointer.\r
+ * @retval kStatus_HAL_UartSuccess Successful operation.\r
+ * @retval kStatus_HAL_UartError An error occurred.\r
+ */\r
+hal_uart_status_t HAL_UartExitLowpower(hal_uart_handle_t handle);\r
+\r
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))\r
+/*!\r
+ * @brief UART IRQ handle function.\r
+ *\r
+ * This function handles the UART transmit and receive IRQ request.\r
+ *\r
+ * @param handle UART handle pointer.\r
+ */\r
+void HAL_UartIsrFunction(hal_uart_handle_t handle);\r
+#endif\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif\r
+/*! @}*/\r
+#endif /* __HAL_UART_ADAPTER_H__ */\r
--- /dev/null
+/*\r
+ * Copyright 2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#include "fsl_common.h"\r
+#include "fsl_usart.h"\r
+#include "fsl_flexcomm.h"\r
+\r
+#include "uart.h"\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+#ifndef NDEBUG\r
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))\r
+#undef assert\r
+#define assert(n)\r
+#endif\r
+#endif\r
+\r
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))\r
+/*! @brief uart RX state structure. */\r
+typedef struct _hal_uart_receive_state\r
+{\r
+ volatile uint8_t *buffer;\r
+ volatile uint32_t bufferLength;\r
+ volatile uint32_t bufferSofar;\r
+} hal_uart_receive_state_t;\r
+\r
+/*! @brief uart TX state structure. */\r
+typedef struct _hal_uart_send_state\r
+{\r
+ volatile uint8_t *buffer;\r
+ volatile uint32_t bufferLength;\r
+ volatile uint32_t bufferSofar;\r
+} hal_uart_send_state_t;\r
+#endif\r
+/*! @brief uart state structure. */\r
+typedef struct _hal_uart_state\r
+{\r
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))\r
+ hal_uart_transfer_callback_t callback;\r
+ void *callbackParam;\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+ usart_handle_t hardwareHandle;\r
+#endif\r
+ hal_uart_receive_state_t rx;\r
+ hal_uart_send_state_t tx;\r
+#endif\r
+ uint8_t instance;\r
+} hal_uart_state_t;\r
+\r
+/*******************************************************************************\r
+ * Prototypes\r
+ ******************************************************************************/\r
+\r
+/*******************************************************************************\r
+ * Variables\r
+ ******************************************************************************/\r
+static USART_Type *const s_UsartAdapterBase[] = USART_BASE_PTRS;\r
+\r
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))\r
+\r
+#if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+/* Array of USART IRQ number. */\r
+static const IRQn_Type s_UsartIRQ[] = USART_IRQS;\r
+#endif\r
+\r
+#endif\r
+\r
+/*******************************************************************************\r
+ * Code\r
+ ******************************************************************************/\r
+\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+static hal_uart_status_t HAL_UartGetStatus(status_t status)\r
+{\r
+ hal_uart_status_t uartStatus = kStatus_HAL_UartError;\r
+ switch (status)\r
+ {\r
+ case kStatus_Success:\r
+ uartStatus = kStatus_HAL_UartSuccess;\r
+ break;\r
+ case kStatus_USART_TxBusy:\r
+ uartStatus = kStatus_HAL_UartTxBusy;\r
+ break;\r
+ case kStatus_USART_RxBusy:\r
+ uartStatus = kStatus_HAL_UartRxBusy;\r
+ break;\r
+ case kStatus_USART_TxIdle:\r
+ uartStatus = kStatus_HAL_UartTxIdle;\r
+ break;\r
+ case kStatus_USART_RxIdle:\r
+ uartStatus = kStatus_HAL_UartRxIdle;\r
+ break;\r
+ case kStatus_USART_BaudrateNotSupport:\r
+ uartStatus = kStatus_HAL_UartBaudrateNotSupport;\r
+ break;\r
+ case kStatus_USART_NoiseError:\r
+ case kStatus_USART_FramingError:\r
+ case kStatus_USART_ParityError:\r
+ uartStatus = kStatus_HAL_UartProtocolError;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ return uartStatus;\r
+}\r
+#else\r
+static hal_uart_status_t HAL_UartGetStatus(status_t status)\r
+{\r
+ if (kStatus_Success == status)\r
+ {\r
+ return kStatus_HAL_UartSuccess;\r
+ }\r
+ else\r
+ {\r
+ return kStatus_HAL_UartError;\r
+ }\r
+}\r
+#endif\r
+\r
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))\r
+\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+static void HAL_UartCallback(USART_Type *base, usart_handle_t *handle, status_t status, void *callbackParam)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ hal_uart_status_t uartStatus = HAL_UartGetStatus(status);\r
+ assert(callbackParam);\r
+\r
+ uartHandle = (hal_uart_state_t *)callbackParam;\r
+\r
+ if (kStatus_HAL_UartProtocolError == uartStatus)\r
+ {\r
+ if (uartHandle->hardwareHandle.rxDataSize)\r
+ {\r
+ uartStatus = kStatus_HAL_UartError;\r
+ }\r
+ }\r
+\r
+ if (uartHandle->callback)\r
+ {\r
+ uartHandle->callback(uartHandle, uartStatus, uartHandle->callbackParam);\r
+ }\r
+}\r
+\r
+#else\r
+\r
+static void HAL_UartInterruptHandle(USART_Type *base, void *handle)\r
+{\r
+ hal_uart_state_t *uartHandle = (hal_uart_state_t *)handle;\r
+ uint32_t status;\r
+ uint8_t instance;\r
+\r
+ if (NULL == uartHandle)\r
+ {\r
+ return;\r
+ }\r
+ instance = uartHandle->instance;\r
+\r
+ status = USART_GetStatusFlags(s_UsartAdapterBase[instance]);\r
+\r
+ /* Receive data register full */\r
+ if ((USART_FIFOSTAT_RXNOTEMPTY_MASK & status) &&\r
+ (USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_RXLVL_MASK))\r
+ {\r
+ if (uartHandle->rx.buffer)\r
+ {\r
+ uartHandle->rx.buffer[uartHandle->rx.bufferSofar++] = USART_ReadByte(s_UsartAdapterBase[instance]);\r
+ if (uartHandle->rx.bufferSofar >= uartHandle->rx.bufferLength)\r
+ {\r
+ USART_DisableInterrupts(s_UsartAdapterBase[instance],\r
+ USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK);\r
+ uartHandle->rx.buffer = NULL;\r
+ if (uartHandle->callback)\r
+ {\r
+ uartHandle->callback(uartHandle, kStatus_HAL_UartRxIdle, uartHandle->callbackParam);\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Send data register empty and the interrupt is enabled. */\r
+ if ((USART_FIFOSTAT_TXNOTFULL_MASK & status) &&\r
+ (USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_TXLVL_MASK))\r
+ {\r
+ if (uartHandle->tx.buffer)\r
+ {\r
+ USART_WriteByte(s_UsartAdapterBase[instance], uartHandle->tx.buffer[uartHandle->tx.bufferSofar++]);\r
+ if (uartHandle->tx.bufferSofar >= uartHandle->tx.bufferLength)\r
+ {\r
+ USART_DisableInterrupts(s_UsartAdapterBase[instance], USART_FIFOINTENCLR_TXLVL_MASK);\r
+ uartHandle->tx.buffer = NULL;\r
+ if (uartHandle->callback)\r
+ {\r
+ uartHandle->callback(uartHandle, kStatus_HAL_UartTxIdle, uartHandle->callbackParam);\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+#if 1\r
+ USART_ClearStatusFlags(s_UsartAdapterBase[instance], status);\r
+#endif\r
+}\r
+#endif\r
+\r
+#endif\r
+\r
+hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, hal_uart_config_t *config)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ usart_config_t usartConfig;\r
+ status_t status;\r
+ assert(handle);\r
+ assert(config);\r
+ assert(config->instance < (sizeof(s_UsartAdapterBase) / sizeof(USART_Type *)));\r
+ assert(s_UsartAdapterBase[config->instance]);\r
+\r
+ if (HAL_UART_HANDLE_SIZE < sizeof(hal_uart_state_t))\r
+ {\r
+ return kStatus_HAL_UartError;\r
+ }\r
+\r
+ USART_GetDefaultConfig(&usartConfig);\r
+ usartConfig.baudRate_Bps = config->baudRate_Bps;\r
+\r
+ if (kHAL_UartParityEven == config->parityMode)\r
+ {\r
+ usartConfig.parityMode = kUSART_ParityEven;\r
+ }\r
+ else if (kHAL_UartParityOdd == config->parityMode)\r
+ {\r
+ usartConfig.parityMode = kUSART_ParityOdd;\r
+ }\r
+ else\r
+ {\r
+ usartConfig.parityMode = kUSART_ParityDisabled;\r
+ }\r
+\r
+ if (kHAL_UartTwoStopBit == config->stopBitCount)\r
+ {\r
+ usartConfig.stopBitCount = kUSART_TwoStopBit;\r
+ }\r
+ else\r
+ {\r
+ usartConfig.stopBitCount = kUSART_OneStopBit;\r
+ }\r
+ usartConfig.enableRx = config->enableRx;\r
+ usartConfig.enableTx = config->enableTx;\r
+ usartConfig.txWatermark = kUSART_TxFifo0;\r
+ usartConfig.rxWatermark = kUSART_RxFifo1;\r
+\r
+ status = USART_Init(s_UsartAdapterBase[config->instance], &usartConfig, config->srcClock_Hz);\r
+\r
+ if (kStatus_Success != status)\r
+ {\r
+ return HAL_UartGetStatus(status);\r
+ }\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+ uartHandle->instance = config->instance;\r
+\r
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))\r
+\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+ USART_TransferCreateHandle(s_UsartAdapterBase[config->instance], &uartHandle->hardwareHandle,\r
+ (usart_transfer_callback_t)HAL_UartCallback, handle);\r
+#else\r
+ /* Enable interrupt in NVIC. */\r
+ FLEXCOMM_SetIRQHandler(s_UsartAdapterBase[config->instance], (flexcomm_irq_handler_t)HAL_UartInterruptHandle,\r
+ handle);\r
+ NVIC_SetPriority((IRQn_Type)s_UsartIRQ[config->instance], HAL_UART_ISR_PRIORITY);\r
+ EnableIRQ(s_UsartIRQ[config->instance]);\r
+#endif\r
+\r
+#endif\r
+\r
+ return kStatus_HAL_UartSuccess;\r
+}\r
+\r
+hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+\r
+ assert(handle);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ USART_Deinit(s_UsartAdapterBase[uartHandle->instance]);\r
+\r
+ return kStatus_HAL_UartSuccess;\r
+}\r
+\r
+hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ status_t status;\r
+ assert(handle);\r
+ assert(data);\r
+ assert(length);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))\r
+ if (uartHandle->rx.buffer)\r
+ {\r
+ return kStatus_HAL_UartRxBusy;\r
+ }\r
+#endif\r
+\r
+ status = USART_ReadBlocking(s_UsartAdapterBase[uartHandle->instance], data, length);\r
+\r
+ return HAL_UartGetStatus(status);\r
+}\r
+\r
+hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ assert(handle);\r
+ assert(data);\r
+ assert(length);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))\r
+ if (uartHandle->tx.buffer)\r
+ {\r
+ return kStatus_HAL_UartTxBusy;\r
+ }\r
+#endif\r
+\r
+ USART_WriteBlocking(s_UsartAdapterBase[uartHandle->instance], data, length);\r
+\r
+ return kStatus_HAL_UartSuccess;\r
+}\r
+\r
+hal_uart_status_t HAL_UartEnterLowpower(hal_uart_handle_t handle)\r
+{\r
+ assert(handle);\r
+\r
+ return kStatus_HAL_UartSuccess;\r
+}\r
+\r
+hal_uart_status_t HAL_UartExitLowpower(hal_uart_handle_t handle)\r
+{\r
+ assert(handle);\r
+\r
+ return kStatus_HAL_UartSuccess;\r
+}\r
+\r
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))\r
+\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+\r
+hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle,\r
+ hal_uart_transfer_callback_t callback,\r
+ void *callbackParam)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+\r
+ assert(handle);\r
+ assert(HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ uartHandle->callbackParam = callbackParam;\r
+ uartHandle->callback = callback;\r
+\r
+ return kStatus_HAL_UartSuccess;\r
+}\r
+\r
+hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ status_t status;\r
+ assert(handle);\r
+ assert(transfer);\r
+ assert(HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ status = USART_TransferReceiveNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle,\r
+ (usart_transfer_t *)transfer, NULL);\r
+\r
+ return HAL_UartGetStatus(status);\r
+}\r
+\r
+hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ status_t status;\r
+ assert(handle);\r
+ assert(transfer);\r
+ assert(HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ status = USART_TransferSendNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle,\r
+ (usart_transfer_t *)transfer);\r
+\r
+ return HAL_UartGetStatus(status);\r
+}\r
+\r
+hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ status_t status;\r
+ assert(handle);\r
+ assert(count);\r
+ assert(HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ status =\r
+ USART_TransferGetReceiveCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count);\r
+\r
+ return HAL_UartGetStatus(status);\r
+}\r
+\r
+hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ status_t status;\r
+ assert(handle);\r
+ assert(count);\r
+ assert(HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ status = USART_TransferGetSendCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count);\r
+\r
+ return HAL_UartGetStatus(status);\r
+}\r
+\r
+hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ assert(handle);\r
+ assert(HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ USART_TransferAbortReceive(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);\r
+\r
+ return kStatus_HAL_UartSuccess;\r
+}\r
+\r
+hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ assert(handle);\r
+ assert(HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ USART_TransferAbortSend(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);\r
+\r
+ return kStatus_HAL_UartSuccess;\r
+}\r
+\r
+#else\r
+\r
+/* None transactional API with non-blocking mode. */\r
+hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle,\r
+ hal_uart_transfer_callback_t callback,\r
+ void *callbackParam)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+\r
+ assert(handle);\r
+ assert(!HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ uartHandle->callbackParam = callbackParam;\r
+ uartHandle->callback = callback;\r
+\r
+ return kStatus_HAL_UartSuccess;\r
+}\r
+\r
+hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ assert(handle);\r
+ assert(data);\r
+ assert(length);\r
+ assert(!HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ if (uartHandle->rx.buffer)\r
+ {\r
+ return kStatus_HAL_UartRxBusy;\r
+ }\r
+\r
+ uartHandle->rx.bufferLength = length;\r
+ uartHandle->rx.bufferSofar = 0;\r
+ uartHandle->rx.buffer = data;\r
+ USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_RXLVL_MASK);\r
+ return kStatus_HAL_UartSuccess;\r
+}\r
+\r
+hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ assert(handle);\r
+ assert(data);\r
+ assert(length);\r
+ assert(!HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ if (uartHandle->tx.buffer)\r
+ {\r
+ return kStatus_HAL_UartTxBusy;\r
+ }\r
+ uartHandle->tx.bufferLength = length;\r
+ uartHandle->tx.bufferSofar = 0;\r
+ uartHandle->tx.buffer = (volatile uint8_t *)data;\r
+ USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_TXLVL_MASK);\r
+ return kStatus_HAL_UartSuccess;\r
+}\r
+\r
+hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ assert(handle);\r
+ assert(reCount);\r
+ assert(!HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ if (uartHandle->rx.buffer)\r
+ {\r
+ *reCount = uartHandle->rx.bufferSofar;\r
+ return kStatus_HAL_UartSuccess;\r
+ }\r
+ return kStatus_HAL_UartError;\r
+}\r
+\r
+hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ assert(handle);\r
+ assert(seCount);\r
+ assert(!HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ if (uartHandle->tx.buffer)\r
+ {\r
+ *seCount = uartHandle->tx.bufferSofar;\r
+ return kStatus_HAL_UartSuccess;\r
+ }\r
+ return kStatus_HAL_UartError;\r
+}\r
+\r
+hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ assert(handle);\r
+ assert(!HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ if (uartHandle->rx.buffer)\r
+ {\r
+ USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance],\r
+ USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK);\r
+ uartHandle->rx.buffer = NULL;\r
+ }\r
+\r
+ return kStatus_HAL_UartSuccess;\r
+}\r
+\r
+hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ assert(handle);\r
+ assert(!HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ if (uartHandle->tx.buffer)\r
+ {\r
+ USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENCLR_TXLVL_MASK);\r
+ uartHandle->tx.buffer = NULL;\r
+ }\r
+\r
+ return kStatus_HAL_UartSuccess;\r
+}\r
+\r
+#endif\r
+\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+\r
+void HAL_UartIsrFunction(hal_uart_handle_t handle)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ assert(handle);\r
+ assert(HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+#if 0\r
+ DisableIRQ(s_UsartIRQ[uartHandle->instance]);\r
+#endif\r
+ USART_TransferHandleIRQ(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);\r
+#if 0\r
+ NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);\r
+ EnableIRQ(s_UsartIRQ[uartHandle->instance]);\r
+#endif\r
+}\r
+\r
+#else\r
+\r
+void HAL_UartIsrFunction(hal_uart_handle_t handle)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ assert(handle);\r
+ assert(!HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+#if 0\r
+ DisableIRQ(s_UsartIRQ[uartHandle->instance]);\r
+#endif\r
+ HAL_UartInterruptHandle(s_UsartAdapterBase[uartHandle->instance], (void *)uartHandle);\r
+#if 0\r
+ NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);\r
+ EnableIRQ(s_UsartIRQ[uartHandle->instance]);\r
+#endif\r
+}\r
+\r
+#endif\r
+\r
+#endif\r
--- /dev/null
+/*\r
+** ###################################################################\r
+** Processors: LPC54018JBD208\r
+** LPC54018JET180\r
+**\r
+** Compilers: GNU C Compiler\r
+** IAR ANSI C/C++ Compiler for ARM\r
+** Keil ARM C/C++ Compiler\r
+** MCUXpresso Compiler\r
+**\r
+** Reference manual: LPC540xx/LPC54S0xx User manual Rev.0.8 5 June 2018\r
+** Version: rev. 1.2, 2017-06-08\r
+** Build: b191118\r
+**\r
+** Abstract:\r
+** CMSIS Peripheral Access Layer for LPC54018\r
+**\r
+** Copyright 1997-2016 Freescale Semiconductor, Inc.\r
+** Copyright 2016-2019 NXP\r
+** All rights reserved.\r
+**\r
+** SPDX-License-Identifier: BSD-3-Clause\r
+**\r
+** http: www.nxp.com\r
+** mail: support@nxp.com\r
+**\r
+** Revisions:\r
+** - rev. 1.0 (2016-08-12)\r
+** Initial version.\r
+** - rev. 1.1 (2016-11-25)\r
+** Update CANFD and Classic CAN register.\r
+** Add MAC TIMERSTAMP registers.\r
+** - rev. 1.2 (2017-06-08)\r
+** Remove RTC_CTRL_RTC_OSC_BYPASS.\r
+** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.\r
+** Remove RESET and HALT from SYSCON_AHBCLKDIV.\r
+**\r
+** ###################################################################\r
+*/\r
+\r
+/*!\r
+ * @file LPC54018.h\r
+ * @version 1.2\r
+ * @date 2017-06-08\r
+ * @brief CMSIS Peripheral Access Layer for LPC54018\r
+ *\r
+ * CMSIS Peripheral Access Layer for LPC54018\r
+ */\r
+\r
+#ifndef _LPC54018_H_\r
+#define _LPC54018_H_ /**< Symbol preventing repeated inclusion */\r
+\r
+/** Memory map major version (memory maps with equal major version number are\r
+ * compatible) */\r
+#define MCU_MEM_MAP_VERSION 0x0100U\r
+/** Memory map minor version */\r
+#define MCU_MEM_MAP_VERSION_MINOR 0x0002U\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- Interrupt vector numbers\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers\r
+ * @{\r
+ */\r
+\r
+/** Interrupt Number Definitions */\r
+#define NUMBER_OF_INT_VECTORS 73 /**< Number of interrupts in the Vector table */\r
+\r
+typedef enum IRQn {\r
+ /* Auxiliary constants */\r
+ NotAvail_IRQn = -128, /**< Not available device specific interrupt */\r
+\r
+ /* Core interrupts */\r
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */\r
+\r
+ /* Device specific interrupts */\r
+ WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect */\r
+ DMA0_IRQn = 1, /**< DMA controller */\r
+ GINT0_IRQn = 2, /**< GPIO group 0 */\r
+ GINT1_IRQn = 3, /**< GPIO group 1 */\r
+ PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */\r
+ PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */\r
+ PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */\r
+ PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */\r
+ UTICK0_IRQn = 8, /**< Micro-tick Timer */\r
+ MRT0_IRQn = 9, /**< Multi-rate timer */\r
+ CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */\r
+ CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */\r
+ SCT0_IRQn = 12, /**< SCTimer/PWM */\r
+ CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */\r
+ FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */\r
+ FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */\r
+ FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */\r
+ FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */\r
+ FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */\r
+ FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */\r
+ FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */\r
+ FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */\r
+ ADC0_SEQA_IRQn = 22, /**< ADC0 sequence A completion. */\r
+ ADC0_SEQB_IRQn = 23, /**< ADC0 sequence B completion. */\r
+ ADC0_THCMP_IRQn = 24, /**< ADC0 threshold compare and error. */\r
+ DMIC0_IRQn = 25, /**< Digital microphone and DMIC subsystem */\r
+ HWVAD0_IRQn = 26, /**< Hardware Voice Activity Detector */\r
+ USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */\r
+ USB0_IRQn = 28, /**< USB device */\r
+ RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */\r
+ FLEXCOMM10_IRQn = 30, /**< Flexcomm Interface 10 (SPI, FLEXCOMM) */\r
+ Reserved47_IRQn = 31, /**< Reserved interrupt */\r
+ PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */\r
+ PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */\r
+ PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */\r
+ PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */\r
+ CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */\r
+ CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */\r
+ RIT_IRQn = 38, /**< Repetitive Interrupt Timer */\r
+ SPIFI0_IRQn = 39, /**< SPI flash interface */\r
+ FLEXCOMM8_IRQn = 40, /**< Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */\r
+ FLEXCOMM9_IRQn = 41, /**< Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */\r
+ SDIO_IRQn = 42, /**< SD/MMC */\r
+ CAN0_IRQ0_IRQn = 43, /**< CAN0 interrupt0 */\r
+ CAN0_IRQ1_IRQn = 44, /**< CAN0 interrupt1 */\r
+ CAN1_IRQ0_IRQn = 45, /**< CAN1 interrupt0 */\r
+ CAN1_IRQ1_IRQn = 46, /**< CAN1 interrupt1 */\r
+ USB1_IRQn = 47, /**< USB1 interrupt */\r
+ USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */\r
+ ETHERNET_IRQn = 49, /**< Ethernet */\r
+ ETHERNET_PMT_IRQn = 50, /**< Ethernet power management interrupt */\r
+ ETHERNET_MACLP_IRQn = 51, /**< Ethernet MAC interrupt */\r
+ Reserved68_IRQn = 52, /**< Reserved interrupt */\r
+ LCD_IRQn = 53, /**< LCD interrupt */\r
+ SHA_IRQn = 54, /**< SHA interrupt */\r
+ SMARTCARD0_IRQn = 55, /**< Smart card 0 interrupt */\r
+ SMARTCARD1_IRQn = 56 /**< Smart card 1 interrupt */\r
+} IRQn_Type;\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group Interrupt_vector_numbers */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- Cortex M4 Core Configuration\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration\r
+ * @{\r
+ */\r
+\r
+#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */\r
+#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */\r
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */\r
+#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */\r
+\r
+#include "core_cm4.h" /* Core Peripheral Access Layer */\r
+#include "system_LPC54018.h" /* Device specific configuration file */\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group Cortex_Core_Configuration */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- Mapping Information\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup Mapping_Information Mapping Information\r
+ * @{\r
+ */\r
+\r
+/** Mapping Information */\r
+/*!\r
+ * @addtogroup dma_request\r
+ * @{\r
+ */\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/*!\r
+ * @brief Structure for the DMA hardware request\r
+ *\r
+ * Defines the structure for the DMA hardware request collections. The user can configure the\r
+ * hardware request to trigger the DMA transfer accordingly. The index\r
+ * of the hardware request varies according to the to SoC.\r
+ */\r
+typedef enum _dma_request_source\r
+{\r
+ kDmaRequestFlexcomm0Rx = 0U, /**< Flexcomm Interface 0 RX/I2C Slave */\r
+ kDmaRequestFlexcomm0Tx = 1U, /**< Flexcomm Interface 0 TX/I2C Master */\r
+ kDmaRequestFlexcomm1Rx = 2U, /**< Flexcomm Interface 1 RX/I2C Slave */\r
+ kDmaRequestFlexcomm1Tx = 3U, /**< Flexcomm Interface 1 TX/I2C Master */\r
+ kDmaRequestFlexcomm2Rx = 4U, /**< Flexcomm Interface 2 RX/I2C Slave */\r
+ kDmaRequestFlexcomm2Tx = 5U, /**< Flexcomm Interface 2 TX/I2C Master */\r
+ kDmaRequestFlexcomm3Rx = 6U, /**< Flexcomm Interface 3 RX/I2C Slave */\r
+ kDmaRequestFlexcomm3Tx = 7U, /**< Flexcomm Interface 3 TX/I2C Master */\r
+ kDmaRequestFlexcomm4Rx = 8U, /**< Flexcomm Interface 4 RX/I2C Slave */\r
+ kDmaRequestFlexcomm4Tx = 9U, /**< Flexcomm Interface 4 TX/I2C Master */\r
+ kDmaRequestFlexcomm5Rx = 10U, /**< Flexcomm Interface 5 RX/I2C Slave */\r
+ kDmaRequestFlexcomm5Tx = 11U, /**< Flexcomm Interface 5 TX/I2C Master */\r
+ kDmaRequestFlexcomm6Rx = 12U, /**< Flexcomm Interface 6 RX/I2C Slave */\r
+ kDmaRequestFlexcomm6Tx = 13U, /**< Flexcomm Interface 6 TX/I2C Master */\r
+ kDmaRequestFlexcomm7Rx = 14U, /**< Flexcomm Interface 7 RX/I2C Slave */\r
+ kDmaRequestFlexcomm7Tx = 15U, /**< Flexcomm Interface 7 TX/I2C Master */\r
+ kDmaRequestDMIC0 = 16U, /**< Digital microphone interface 0 channel 0 */\r
+ kDmaRequestDMIC1 = 17U, /**< Digital microphone interface 0 channel 1 */\r
+ kDmaRequestSPIFI = 18U, /**< SPI Flash Interface */\r
+ kDmaRequestSHA = 19U, /**< Secure Hash Algorithm */\r
+ kDmaRequestFlexcomm8Rx = 20U, /**< Flexcomm Interface 8 RX/I2C Slave */\r
+ kDmaRequestFlexcomm8Tx = 21U, /**< Flexcomm Interface 8 TX/I2C Slave */\r
+ kDmaRequestFlexcomm9Rx = 22U, /**< Flexcomm Interface 9 RX/I2C Slave */\r
+ kDmaRequestFlexcomm9Tx = 23U, /**< Flexcomm Interface 9 TX/I2C Slave */\r
+ kDmaRequestSMARTCARD0_RX = 24U, /**< SMARTCARD0 RX */\r
+ kDmaRequestSMARTCARD0_TX = 25U, /**< SMARTCARD0 TX */\r
+ kDmaRequestSMARTCARD1_RX = 26U, /**< SMARTCARD1 RX */\r
+ kDmaRequestSMARTCARD1_TX = 27U, /**< SMARTCARD1 TX */\r
+ kDmaRequestFlexcomm10Rx = 28U, /**< Flexcomm Interface 10 RX */\r
+ kDmaRequestFlexcomm10Tx = 29U, /**< Flexcomm Interface 10 TX */\r
+} dma_request_source_t;\r
+\r
+/* @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group Mapping_Information */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- Device Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+\r
+/*\r
+** Start of section using anonymous unions\r
+*/\r
+\r
+#if defined(__ARMCC_VERSION)\r
+ #if (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang diagnostic push\r
+ #else\r
+ #pragma push\r
+ #pragma anon_unions\r
+ #endif\r
+#elif defined(__GNUC__)\r
+ /* anonymous unions are enabled by default */\r
+#elif defined(__IAR_SYSTEMS_ICC__)\r
+ #pragma language=extended\r
+#else\r
+ #error Not supported compiler type\r
+#endif\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- ADC Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** ADC - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */\r
+ __IO uint32_t INSEL; /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */\r
+ __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */\r
+ __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */\r
+ uint8_t RESERVED_0[8];\r
+ __I uint32_t DAT[12]; /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */\r
+ __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */\r
+ __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */\r
+ __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */\r
+ __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */\r
+ __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */\r
+ __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */\r
+ __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */\r
+ __IO uint32_t STARTUP; /**< ADC Startup register., offset: 0x6C */\r
+ __IO uint32_t CALIB; /**< ADC Calibration register., offset: 0x70 */\r
+} ADC_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- ADC Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup ADC_Register_Masks ADC Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */\r
+/*! @{ */\r
+#define ADC_CTRL_CLKDIV_MASK (0xFFU)\r
+#define ADC_CTRL_CLKDIV_SHIFT (0U)\r
+/*! CLKDIV - In synchronous mode only, the system clock is divided by this value plus one to produce\r
+ * the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically,\r
+ * software should program the smallest value in this field that yields this maximum clock rate or\r
+ * slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may\r
+ * be desirable. This field is ignored in the asynchronous operating mode.\r
+ */\r
+#define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK)\r
+#define ADC_CTRL_ASYNMODE_MASK (0x100U)\r
+#define ADC_CTRL_ASYNMODE_SHIFT (8U)\r
+/*! ASYNMODE - Select clock mode.\r
+ * 0b0..Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in\r
+ * the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to\r
+ * eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger.\r
+ * In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC\r
+ * input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger\r
+ * pulse.\r
+ * 0b1..Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block.\r
+ */\r
+#define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK)\r
+#define ADC_CTRL_RESOL_MASK (0x600U)\r
+#define ADC_CTRL_RESOL_SHIFT (9U)\r
+/*! RESOL - The number of bits of ADC resolution. Accuracy can be reduced to achieve higher\r
+ * conversion rates. A single conversion (including one conversion in a burst or sequence) requires the\r
+ * selected number of bits of resolution plus 3 ADC clocks. This field must only be altered when\r
+ * the ADC is fully idle. Changing it during any kind of ADC operation may have unpredictable\r
+ * results. ADC clock frequencies for various resolutions must not exceed: - 5x the system clock rate\r
+ * for 12-bit resolution - 4.3x the system clock rate for 10-bit resolution - 3.6x the system\r
+ * clock for 8-bit resolution - 3x the bus clock rate for 6-bit resolution\r
+ * 0b00..6-bit resolution. An ADC conversion requires 9 ADC clocks, plus any clocks specified by the TSAMP field.\r
+ * 0b01..8-bit resolution. An ADC conversion requires 11 ADC clocks, plus any clocks specified by the TSAMP field.\r
+ * 0b10..10-bit resolution. An ADC conversion requires 13 ADC clocks, plus any clocks specified by the TSAMP field.\r
+ * 0b11..12-bit resolution. An ADC conversion requires 15 ADC clocks, plus any clocks specified by the TSAMP field.\r
+ */\r
+#define ADC_CTRL_RESOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK)\r
+#define ADC_CTRL_BYPASSCAL_MASK (0x800U)\r
+#define ADC_CTRL_BYPASSCAL_SHIFT (11U)\r
+/*! BYPASSCAL - Bypass Calibration. This bit may be set to avoid the need to calibrate if offset\r
+ * error is not a concern in the application.\r
+ * 0b0..Calibrate. The stored calibration value will be applied to the ADC during conversions to compensated for\r
+ * offset error. A calibration cycle must be performed each time the chip is powered-up. Re-calibration may\r
+ * be warranted periodically - especially if operating conditions have changed.\r
+ * 0b1..Bypass calibration. Calibration is not utilized. Less time is required when enabling the ADC -\r
+ * particularly following chip power-up. Attempts to launch a calibration cycle are blocked when this bit is set.\r
+ */\r
+#define ADC_CTRL_BYPASSCAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK)\r
+#define ADC_CTRL_TSAMP_MASK (0x7000U)\r
+#define ADC_CTRL_TSAMP_SHIFT (12U)\r
+/*! TSAMP - Sample Time. The default sampling period (TSAMP = '000') at the start of each conversion\r
+ * is 2.5 ADC clock periods. Depending on a variety of factors, including operating conditions\r
+ * and the output impedance of the analog source, longer sampling times may be required. See\r
+ * Section 28.7.10. The TSAMP field specifies the number of additional ADC clock cycles, from zero to\r
+ * seven, by which the sample period will be extended. The total conversion time will increase by\r
+ * the same number of clocks. 000 - The sample period will be the default 2.5 ADC clocks. A\r
+ * complete conversion with 12-bits of accuracy will require 15 clocks. 001- The sample period will\r
+ * be extended by one ADC clock to a total of 3.5 clock periods. A complete 12-bit conversion will\r
+ * require 16 clocks. 010 - The sample period will be extended by two clocks to 4.5 ADC clock\r
+ * cycles. A complete 12-bit conversion will require 17 ADC clocks. 111 - The sample period will be\r
+ * extended by seven clocks to 9.5 ADC clock cycles. A complete 12-bit conversion will require\r
+ * 22 ADC clocks.\r
+ */\r
+#define ADC_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK)\r
+/*! @} */\r
+\r
+/*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */\r
+/*! @{ */\r
+#define ADC_INSEL_SEL_MASK (0x3U)\r
+#define ADC_INSEL_SEL_SHIFT (0U)\r
+/*! SEL - Selects the input source for channel 0. All other values are reserved.\r
+ * 0b00..ADC0_IN0 function.\r
+ * 0b11..Internal temperature sensor.\r
+ */\r
+#define ADC_INSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */\r
+/*! @{ */\r
+#define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU)\r
+#define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U)\r
+/*! CHANNELS - Selects which one or more of the ADC channels will be sampled and converted when this\r
+ * sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be\r
+ * included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1\r
+ * and so forth. When this conversion sequence is triggered, either by a hardware trigger or via\r
+ * software command, ADC conversions will be performed on each enabled channel, in sequence,\r
+ * beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31)\r
+ * is LOW. It is allowed to change this field and set bit 31 in the same write.\r
+ */\r
+#define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK)\r
+#define ADC_SEQ_CTRL_TRIGGER_MASK (0x3F000U)\r
+#define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U)\r
+/*! TRIGGER - Selects which of the available hardware trigger sources will cause this conversion\r
+ * sequence to be initiated. Program the trigger input number in this field. See Table 476. In order\r
+ * to avoid generating a spurious trigger, it is recommended writing to this field only when\r
+ * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.\r
+ */\r
+#define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK)\r
+#define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U)\r
+#define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U)\r
+/*! TRIGPOL - Select the polarity of the selected input trigger for this conversion sequence. In\r
+ * order to avoid generating a spurious trigger, it is recommended writing to this field only when\r
+ * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.\r
+ * 0b0..Negative edge. A negative edge launches the conversion sequence on the selected trigger input.\r
+ * 0b1..Positive edge. A positive edge launches the conversion sequence on the selected trigger input.\r
+ */\r
+#define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK)\r
+#define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U)\r
+#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U)\r
+/*! SYNCBYPASS - Setting this bit allows the hardware trigger input to bypass synchronization\r
+ * flip-flop stages and therefore shorten the time between the trigger input signal and the start of a\r
+ * conversion. There are slightly different criteria for whether or not this bit can be set\r
+ * depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0):\r
+ * Synchronization may be bypassed (this bit may be set) if the selected trigger source is already\r
+ * synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer).\r
+ * Whether this bit is set or not, a trigger pulse must be maintained for at least one system\r
+ * clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be\r
+ * bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse\r
+ * will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and\r
+ * on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be\r
+ * maintained for one system clock period.\r
+ * 0b0..Enable trigger synchronization. The hardware trigger bypass is not enabled.\r
+ * 0b1..Bypass trigger synchronization. The hardware trigger bypass is enabled.\r
+ */\r
+#define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK)\r
+#define ADC_SEQ_CTRL_START_MASK (0x4000000U)\r
+#define ADC_SEQ_CTRL_START_SHIFT (26U)\r
+/*! START - Writing a 1 to this field will launch one pass through this conversion sequence. The\r
+ * behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this\r
+ * bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a\r
+ * conversion sequence. It will consequently always read back as a zero.\r
+ */\r
+#define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK)\r
+#define ADC_SEQ_CTRL_BURST_MASK (0x8000000U)\r
+#define ADC_SEQ_CTRL_BURST_SHIFT (27U)\r
+/*! BURST - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled\r
+ * through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions\r
+ * can be halted by clearing this bit. The sequence currently in progress will be completed before\r
+ * conversions are terminated. Note that a new sequence could begin just before BURST is cleared.\r
+ */\r
+#define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK)\r
+#define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U)\r
+#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U)\r
+/*! SINGLESTEP - When this bit is set, a hardware trigger or a write to the START bit will launch a\r
+ * single conversion on the next channel in the sequence instead of the default response of\r
+ * launching an entire sequence of conversions. Once all of the channels comprising a sequence have\r
+ * been converted, a subsequent trigger will repeat the sequence beginning with the first enabled\r
+ * channel. Interrupt generation will still occur either after each individual conversion or at\r
+ * the end of the entire sequence, depending on the state of the MODE bit.\r
+ */\r
+#define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK)\r
+#define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U)\r
+#define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U)\r
+/*! LOWPRIO - Set priority for sequence A.\r
+ * 0b0..Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost.\r
+ * 0b1..High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence\r
+ * software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion\r
+ * currently in progress will be terminated. The A sequence that was interrupted will automatically resume\r
+ * after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the\r
+ * conversion sequence will resume from that point.\r
+ */\r
+#define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK)\r
+#define ADC_SEQ_CTRL_MODE_MASK (0x40000000U)\r
+#define ADC_SEQ_CTRL_MODE_SHIFT (30U)\r
+/*! MODE - Indicates whether the primary method for retrieving conversion results for this sequence\r
+ * will be accomplished via reading the global data register (SEQA_GDAT) at the end of each\r
+ * conversion, or the individual channel result registers at the end of the entire sequence. Impacts\r
+ * when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which\r
+ * overrun conditions contribute to an overrun interrupt as described below.\r
+ * 0b0..End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC\r
+ * conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The\r
+ * OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger\r
+ * if enabled.\r
+ * 0b1..End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A\r
+ * conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in\r
+ * this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun\r
+ * interrupt/DMA trigger since it is assumed this register may not be utilized in this mode.\r
+ */\r
+#define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK)\r
+#define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U)\r
+#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U)\r
+/*! SEQ_ENA - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be\r
+ * taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state\r
+ * (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered\r
+ * immediately upon being enabled. In order to avoid spuriously triggering the sequence, care\r
+ * should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE\r
+ * state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be\r
+ * triggered immediately upon being enabled.\r
+ * 0b0..Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence\r
+ * n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is\r
+ * re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.\r
+ * 0b1..Enabled. Sequence n is enabled.\r
+ */\r
+#define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK)\r
+/*! @} */\r
+\r
+/* The count of ADC_SEQ_CTRL */\r
+#define ADC_SEQ_CTRL_COUNT (2U)\r
+\r
+/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */\r
+/*! @{ */\r
+#define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U)\r
+#define ADC_SEQ_GDAT_RESULT_SHIFT (4U)\r
+/*! RESULT - This field contains the 12-bit ADC conversion result from the most recent conversion\r
+ * performed under conversion sequence associated with this register. The result is a binary\r
+ * fraction representing the voltage on the currently-selected input channel as it falls within the\r
+ * range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less\r
+ * than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input\r
+ * was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this\r
+ * result has not yet been read.\r
+ */\r
+#define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK)\r
+#define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U)\r
+#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U)\r
+/*! THCMPRANGE - Indicates whether the result of the last conversion performed was above, below or\r
+ * within the range established by the designated threshold comparison registers (THRn_LOW and\r
+ * THRn_HIGH).\r
+ */\r
+#define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK)\r
+#define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U)\r
+#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U)\r
+/*! THCMPCROSS - Indicates whether the result of the last conversion performed represented a\r
+ * crossing of the threshold level established by the designated LOW threshold comparison register\r
+ * (THRn_LOW) and, if so, in what direction the crossing occurred.\r
+ */\r
+#define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK)\r
+#define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U)\r
+#define ADC_SEQ_GDAT_CHN_SHIFT (26U)\r
+/*! CHN - These bits contain the channel from which the RESULT bits were converted (e.g. 0000\r
+ * identifies channel 0, 0001 channel 1, etc.).\r
+ */\r
+#define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK)\r
+#define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U)\r
+#define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U)\r
+/*! OVERRUN - This bit is set if a new conversion result is loaded into the RESULT field before a\r
+ * previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along\r
+ * with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun\r
+ * interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set\r
+ * to '0' (and if the overrun interrupt is enabled).\r
+ */\r
+#define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK)\r
+#define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U)\r
+#define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U)\r
+/*! DATAVALID - This bit is set to '1' at the end of each conversion when a new result is loaded\r
+ * into the RESULT field. It is cleared whenever this register is read. This bit will cause a\r
+ * conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that\r
+ * sequence is set to 0 (and if the interrupt is enabled).\r
+ */\r
+#define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK)\r
+/*! @} */\r
+\r
+/* The count of ADC_SEQ_GDAT */\r
+#define ADC_SEQ_GDAT_COUNT (2U)\r
+\r
+/*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */\r
+/*! @{ */\r
+#define ADC_DAT_RESULT_MASK (0xFFF0U)\r
+#define ADC_DAT_RESULT_SHIFT (4U)\r
+/*! RESULT - This field contains the 12-bit ADC conversion result from the last conversion performed\r
+ * on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin,\r
+ * as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on\r
+ * the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that\r
+ * the voltage on the input was close to, equal to, or greater than that on VREFP.\r
+ */\r
+#define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK)\r
+#define ADC_DAT_THCMPRANGE_MASK (0x30000U)\r
+#define ADC_DAT_THCMPRANGE_SHIFT (16U)\r
+/*! THCMPRANGE - Threshold Range Comparison result. 0x0 = In Range: The last completed conversion\r
+ * was greater than or equal to the value programmed into the designated LOW threshold register\r
+ * (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold\r
+ * register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value\r
+ * programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last\r
+ * completed conversion was greater than the value programmed into the designated HIGH threshold\r
+ * register (THRn_HIGH). 0x3 = Reserved.\r
+ */\r
+#define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK)\r
+#define ADC_DAT_THCMPCROSS_MASK (0xC0000U)\r
+#define ADC_DAT_THCMPCROSS_SHIFT (18U)\r
+/*! THCMPCROSS - Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The\r
+ * most recent completed conversion on this channel had the same relationship (above or below) to\r
+ * the threshold value established by the designated LOW threshold register (THRn_LOW) as did the\r
+ * previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing\r
+ * Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the\r
+ * previous sample on this channel was above the threshold value established by the designated LOW\r
+ * threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward\r
+ * Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred\r
+ * - i.e. the previous sample on this channel was below the threshold value established by the\r
+ * designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.\r
+ */\r
+#define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK)\r
+#define ADC_DAT_CHANNEL_MASK (0x3C000000U)\r
+#define ADC_DAT_CHANNEL_SHIFT (26U)\r
+/*! CHANNEL - This field is hard-coded to contain the channel number that this particular register\r
+ * relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1\r
+ * register, etc)\r
+ */\r
+#define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK)\r
+#define ADC_DAT_OVERRUN_MASK (0x40000000U)\r
+#define ADC_DAT_OVERRUN_SHIFT (30U)\r
+/*! OVERRUN - This bit will be set to a 1 if a new conversion on this channel completes and\r
+ * overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit\r
+ * is set. This bit is cleared, along with the DONE bit, whenever this register is read or when\r
+ * the data related to this channel is read from either of the global SEQn_GDAT registers. This\r
+ * bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if\r
+ * the overrun interrupt is enabled. While it is allowed to include the same channels in both\r
+ * conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the\r
+ * data registers associated with any of the channels that are shared between the two sequences. Any\r
+ * erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.\r
+ */\r
+#define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK)\r
+#define ADC_DAT_DATAVALID_MASK (0x80000000U)\r
+#define ADC_DAT_DATAVALID_SHIFT (31U)\r
+/*! DATAVALID - This bit is set to 1 when an ADC conversion on this channel completes. This bit is\r
+ * cleared whenever this register is read or when the data related to this channel is read from\r
+ * either of the global SEQn_GDAT registers. While it is allowed to include the same channels in\r
+ * both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in\r
+ * the data registers associated with any of the channels that are shared between the two\r
+ * sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.\r
+ */\r
+#define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK)\r
+/*! @} */\r
+\r
+/* The count of ADC_DAT */\r
+#define ADC_DAT_COUNT (12U)\r
+\r
+/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */\r
+/*! @{ */\r
+#define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U)\r
+#define ADC_THR0_LOW_THRLOW_SHIFT (4U)\r
+/*! THRLOW - Low threshold value against which ADC results will be compared\r
+ */\r
+#define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK)\r
+/*! @} */\r
+\r
+/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */\r
+/*! @{ */\r
+#define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U)\r
+#define ADC_THR1_LOW_THRLOW_SHIFT (4U)\r
+/*! THRLOW - Low threshold value against which ADC results will be compared\r
+ */\r
+#define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK)\r
+/*! @} */\r
+\r
+/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */\r
+/*! @{ */\r
+#define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U)\r
+#define ADC_THR0_HIGH_THRHIGH_SHIFT (4U)\r
+/*! THRHIGH - High threshold value against which ADC results will be compared\r
+ */\r
+#define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK)\r
+/*! @} */\r
+\r
+/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */\r
+/*! @{ */\r
+#define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U)\r
+#define ADC_THR1_HIGH_THRHIGH_SHIFT (4U)\r
+/*! THRHIGH - High threshold value against which ADC results will be compared\r
+ */\r
+#define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK)\r
+/*! @} */\r
+\r
+/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */\r
+/*! @{ */\r
+#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U)\r
+#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U)\r
+/*! CH0_THRSEL - Threshold select for channel 0.\r
+ * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.\r
+ * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.\r
+ */\r
+#define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK)\r
+#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U)\r
+#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U)\r
+/*! CH1_THRSEL - Threshold select for channel 1. See description for channel 0.\r
+ */\r
+#define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK)\r
+#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U)\r
+#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U)\r
+/*! CH2_THRSEL - Threshold select for channel 2. See description for channel 0.\r
+ */\r
+#define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK)\r
+#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U)\r
+#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U)\r
+/*! CH3_THRSEL - Threshold select for channel 3. See description for channel 0.\r
+ */\r
+#define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK)\r
+#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U)\r
+#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U)\r
+/*! CH4_THRSEL - Threshold select for channel 4. See description for channel 0.\r
+ */\r
+#define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK)\r
+#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U)\r
+#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U)\r
+/*! CH5_THRSEL - Threshold select for channel 5. See description for channel 0.\r
+ */\r
+#define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK)\r
+#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U)\r
+#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U)\r
+/*! CH6_THRSEL - Threshold select for channel 6. See description for channel 0.\r
+ */\r
+#define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK)\r
+#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U)\r
+#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U)\r
+/*! CH7_THRSEL - Threshold select for channel 7. See description for channel 0.\r
+ */\r
+#define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK)\r
+#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U)\r
+#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U)\r
+/*! CH8_THRSEL - Threshold select for channel 8. See description for channel 0.\r
+ */\r
+#define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK)\r
+#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U)\r
+#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U)\r
+/*! CH9_THRSEL - Threshold select for channel 9. See description for channel 0.\r
+ */\r
+#define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK)\r
+#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U)\r
+#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U)\r
+/*! CH10_THRSEL - Threshold select for channel 10. See description for channel 0.\r
+ */\r
+#define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK)\r
+#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U)\r
+#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U)\r
+/*! CH11_THRSEL - Threshold select for channel 11. See description for channel 0.\r
+ */\r
+#define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */\r
+/*! @{ */\r
+#define ADC_INTEN_SEQA_INTEN_MASK (0x1U)\r
+#define ADC_INTEN_SEQA_INTEN_SHIFT (0U)\r
+/*! SEQA_INTEN - Sequence A interrupt enable.\r
+ * 0b0..Disabled. The sequence A interrupt/DMA trigger is disabled.\r
+ * 0b1..Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of\r
+ * each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of\r
+ * conversions, depending on the MODE bit in the SEQA_CTRL register.\r
+ */\r
+#define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK)\r
+#define ADC_INTEN_SEQB_INTEN_MASK (0x2U)\r
+#define ADC_INTEN_SEQB_INTEN_SHIFT (1U)\r
+/*! SEQB_INTEN - Sequence B interrupt enable.\r
+ * 0b0..Disabled. The sequence B interrupt/DMA trigger is disabled.\r
+ * 0b1..Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of\r
+ * each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of\r
+ * conversions, depending on the MODE bit in the SEQB_CTRL register.\r
+ */\r
+#define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK)\r
+#define ADC_INTEN_OVR_INTEN_MASK (0x4U)\r
+#define ADC_INTEN_OVR_INTEN_SHIFT (2U)\r
+/*! OVR_INTEN - Overrun interrupt enable.\r
+ * 0b0..Disabled. The overrun interrupt is disabled.\r
+ * 0b1..Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel\r
+ * data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular\r
+ * sequence is 0, then an overrun in the global data register for that sequence will also cause this\r
+ * interrupt/DMA trigger to be asserted.\r
+ */\r
+#define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK)\r
+#define ADC_INTEN_ADCMPINTEN0_MASK (0x18U)\r
+#define ADC_INTEN_ADCMPINTEN0_SHIFT (3U)\r
+/*! ADCMPINTEN0 - Threshold comparison interrupt enable for channel 0.\r
+ * 0b00..Disabled.\r
+ * 0b01..Outside threshold.\r
+ * 0b10..Crossing threshold.\r
+ * 0b11..Reserved\r
+ */\r
+#define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK)\r
+#define ADC_INTEN_ADCMPINTEN1_MASK (0x60U)\r
+#define ADC_INTEN_ADCMPINTEN1_SHIFT (5U)\r
+/*! ADCMPINTEN1 - Channel 1 threshold comparison interrupt enable. See description for channel 0.\r
+ */\r
+#define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK)\r
+#define ADC_INTEN_ADCMPINTEN2_MASK (0x180U)\r
+#define ADC_INTEN_ADCMPINTEN2_SHIFT (7U)\r
+/*! ADCMPINTEN2 - Channel 2 threshold comparison interrupt enable. See description for channel 0.\r
+ */\r
+#define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK)\r
+#define ADC_INTEN_ADCMPINTEN3_MASK (0x600U)\r
+#define ADC_INTEN_ADCMPINTEN3_SHIFT (9U)\r
+/*! ADCMPINTEN3 - Channel 3 threshold comparison interrupt enable. See description for channel 0.\r
+ */\r
+#define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK)\r
+#define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U)\r
+#define ADC_INTEN_ADCMPINTEN4_SHIFT (11U)\r
+/*! ADCMPINTEN4 - Channel 4 threshold comparison interrupt enable. See description for channel 0.\r
+ */\r
+#define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK)\r
+#define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U)\r
+#define ADC_INTEN_ADCMPINTEN5_SHIFT (13U)\r
+/*! ADCMPINTEN5 - Channel 5 threshold comparison interrupt enable. See description for channel 0.\r
+ */\r
+#define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK)\r
+#define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U)\r
+#define ADC_INTEN_ADCMPINTEN6_SHIFT (15U)\r
+/*! ADCMPINTEN6 - Channel 6 threshold comparison interrupt enable. See description for channel 0.\r
+ */\r
+#define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK)\r
+#define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U)\r
+#define ADC_INTEN_ADCMPINTEN7_SHIFT (17U)\r
+/*! ADCMPINTEN7 - Channel 7 threshold comparison interrupt enable. See description for channel 0.\r
+ */\r
+#define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK)\r
+#define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U)\r
+#define ADC_INTEN_ADCMPINTEN8_SHIFT (19U)\r
+/*! ADCMPINTEN8 - Channel 8 threshold comparison interrupt enable. See description for channel 0.\r
+ */\r
+#define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK)\r
+#define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U)\r
+#define ADC_INTEN_ADCMPINTEN9_SHIFT (21U)\r
+/*! ADCMPINTEN9 - Channel 9 threshold comparison interrupt enable. See description for channel 0.\r
+ */\r
+#define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK)\r
+#define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U)\r
+#define ADC_INTEN_ADCMPINTEN10_SHIFT (23U)\r
+/*! ADCMPINTEN10 - Channel 10 threshold comparison interrupt enable. See description for channel 0.\r
+ */\r
+#define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK)\r
+#define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U)\r
+#define ADC_INTEN_ADCMPINTEN11_SHIFT (25U)\r
+/*! ADCMPINTEN11 - Channel 21 threshold comparison interrupt enable. See description for channel 0.\r
+ */\r
+#define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK)\r
+/*! @} */\r
+\r
+/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */\r
+/*! @{ */\r
+#define ADC_FLAGS_THCMP0_MASK (0x1U)\r
+#define ADC_FLAGS_THCMP0_SHIFT (0U)\r
+/*! THCMP0 - Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or\r
+ * a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by\r
+ * writing a 1.\r
+ */\r
+#define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK)\r
+#define ADC_FLAGS_THCMP1_MASK (0x2U)\r
+#define ADC_FLAGS_THCMP1_SHIFT (1U)\r
+/*! THCMP1 - Threshold comparison event on Channel 1. See description for channel 0.\r
+ */\r
+#define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK)\r
+#define ADC_FLAGS_THCMP2_MASK (0x4U)\r
+#define ADC_FLAGS_THCMP2_SHIFT (2U)\r
+/*! THCMP2 - Threshold comparison event on Channel 2. See description for channel 0.\r
+ */\r
+#define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK)\r
+#define ADC_FLAGS_THCMP3_MASK (0x8U)\r
+#define ADC_FLAGS_THCMP3_SHIFT (3U)\r
+/*! THCMP3 - Threshold comparison event on Channel 3. See description for channel 0.\r
+ */\r
+#define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK)\r
+#define ADC_FLAGS_THCMP4_MASK (0x10U)\r
+#define ADC_FLAGS_THCMP4_SHIFT (4U)\r
+/*! THCMP4 - Threshold comparison event on Channel 4. See description for channel 0.\r
+ */\r
+#define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK)\r
+#define ADC_FLAGS_THCMP5_MASK (0x20U)\r
+#define ADC_FLAGS_THCMP5_SHIFT (5U)\r
+/*! THCMP5 - Threshold comparison event on Channel 5. See description for channel 0.\r
+ */\r
+#define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK)\r
+#define ADC_FLAGS_THCMP6_MASK (0x40U)\r
+#define ADC_FLAGS_THCMP6_SHIFT (6U)\r
+/*! THCMP6 - Threshold comparison event on Channel 6. See description for channel 0.\r
+ */\r
+#define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK)\r
+#define ADC_FLAGS_THCMP7_MASK (0x80U)\r
+#define ADC_FLAGS_THCMP7_SHIFT (7U)\r
+/*! THCMP7 - Threshold comparison event on Channel 7. See description for channel 0.\r
+ */\r
+#define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK)\r
+#define ADC_FLAGS_THCMP8_MASK (0x100U)\r
+#define ADC_FLAGS_THCMP8_SHIFT (8U)\r
+/*! THCMP8 - Threshold comparison event on Channel 8. See description for channel 0.\r
+ */\r
+#define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK)\r
+#define ADC_FLAGS_THCMP9_MASK (0x200U)\r
+#define ADC_FLAGS_THCMP9_SHIFT (9U)\r
+/*! THCMP9 - Threshold comparison event on Channel 9. See description for channel 0.\r
+ */\r
+#define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK)\r
+#define ADC_FLAGS_THCMP10_MASK (0x400U)\r
+#define ADC_FLAGS_THCMP10_SHIFT (10U)\r
+/*! THCMP10 - Threshold comparison event on Channel 10. See description for channel 0.\r
+ */\r
+#define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK)\r
+#define ADC_FLAGS_THCMP11_MASK (0x800U)\r
+#define ADC_FLAGS_THCMP11_SHIFT (11U)\r
+/*! THCMP11 - Threshold comparison event on Channel 11. See description for channel 0.\r
+ */\r
+#define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK)\r
+#define ADC_FLAGS_OVERRUN0_MASK (0x1000U)\r
+#define ADC_FLAGS_OVERRUN0_SHIFT (12U)\r
+/*! OVERRUN0 - Mirrors the OVERRRUN status flag from the result register for ADC channel 0\r
+ */\r
+#define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK)\r
+#define ADC_FLAGS_OVERRUN1_MASK (0x2000U)\r
+#define ADC_FLAGS_OVERRUN1_SHIFT (13U)\r
+/*! OVERRUN1 - Mirrors the OVERRRUN status flag from the result register for ADC channel 1\r
+ */\r
+#define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK)\r
+#define ADC_FLAGS_OVERRUN2_MASK (0x4000U)\r
+#define ADC_FLAGS_OVERRUN2_SHIFT (14U)\r
+/*! OVERRUN2 - Mirrors the OVERRRUN status flag from the result register for ADC channel 2\r
+ */\r
+#define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK)\r
+#define ADC_FLAGS_OVERRUN3_MASK (0x8000U)\r
+#define ADC_FLAGS_OVERRUN3_SHIFT (15U)\r
+/*! OVERRUN3 - Mirrors the OVERRRUN status flag from the result register for ADC channel 3\r
+ */\r
+#define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK)\r
+#define ADC_FLAGS_OVERRUN4_MASK (0x10000U)\r
+#define ADC_FLAGS_OVERRUN4_SHIFT (16U)\r
+/*! OVERRUN4 - Mirrors the OVERRRUN status flag from the result register for ADC channel 4\r
+ */\r
+#define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK)\r
+#define ADC_FLAGS_OVERRUN5_MASK (0x20000U)\r
+#define ADC_FLAGS_OVERRUN5_SHIFT (17U)\r
+/*! OVERRUN5 - Mirrors the OVERRRUN status flag from the result register for ADC channel 5\r
+ */\r
+#define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK)\r
+#define ADC_FLAGS_OVERRUN6_MASK (0x40000U)\r
+#define ADC_FLAGS_OVERRUN6_SHIFT (18U)\r
+/*! OVERRUN6 - Mirrors the OVERRRUN status flag from the result register for ADC channel 6\r
+ */\r
+#define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK)\r
+#define ADC_FLAGS_OVERRUN7_MASK (0x80000U)\r
+#define ADC_FLAGS_OVERRUN7_SHIFT (19U)\r
+/*! OVERRUN7 - Mirrors the OVERRRUN status flag from the result register for ADC channel 7\r
+ */\r
+#define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK)\r
+#define ADC_FLAGS_OVERRUN8_MASK (0x100000U)\r
+#define ADC_FLAGS_OVERRUN8_SHIFT (20U)\r
+/*! OVERRUN8 - Mirrors the OVERRRUN status flag from the result register for ADC channel 8\r
+ */\r
+#define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK)\r
+#define ADC_FLAGS_OVERRUN9_MASK (0x200000U)\r
+#define ADC_FLAGS_OVERRUN9_SHIFT (21U)\r
+/*! OVERRUN9 - Mirrors the OVERRRUN status flag from the result register for ADC channel 9\r
+ */\r
+#define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK)\r
+#define ADC_FLAGS_OVERRUN10_MASK (0x400000U)\r
+#define ADC_FLAGS_OVERRUN10_SHIFT (22U)\r
+/*! OVERRUN10 - Mirrors the OVERRRUN status flag from the result register for ADC channel 10\r
+ */\r
+#define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK)\r
+#define ADC_FLAGS_OVERRUN11_MASK (0x800000U)\r
+#define ADC_FLAGS_OVERRUN11_SHIFT (23U)\r
+/*! OVERRUN11 - Mirrors the OVERRRUN status flag from the result register for ADC channel 11\r
+ */\r
+#define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK)\r
+#define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U)\r
+#define ADC_FLAGS_SEQA_OVR_SHIFT (24U)\r
+/*! SEQA_OVR - Mirrors the global OVERRUN status flag in the SEQA_GDAT register\r
+ */\r
+#define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK)\r
+#define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U)\r
+#define ADC_FLAGS_SEQB_OVR_SHIFT (25U)\r
+/*! SEQB_OVR - Mirrors the global OVERRUN status flag in the SEQB_GDAT register\r
+ */\r
+#define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK)\r
+#define ADC_FLAGS_SEQA_INT_MASK (0x10000000U)\r
+#define ADC_FLAGS_SEQA_INT_SHIFT (28U)\r
+/*! SEQA_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0,\r
+ * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which\r
+ * is set at the end of every ADC conversion performed as part of sequence A. It will be cleared\r
+ * automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register\r
+ * is 1, this flag will be set upon completion of an entire A sequence. In this case it must be\r
+ * cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN\r
+ * register.\r
+ */\r
+#define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK)\r
+#define ADC_FLAGS_SEQB_INT_MASK (0x20000000U)\r
+#define ADC_FLAGS_SEQB_INT_SHIFT (29U)\r
+/*! SEQB_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0,\r
+ * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which\r
+ * is set at the end of every ADC conversion performed as part of sequence B. It will be cleared\r
+ * automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register\r
+ * is 1, this flag will be set upon completion of an entire B sequence. In this case it must be\r
+ * cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN\r
+ * register.\r
+ */\r
+#define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK)\r
+#define ADC_FLAGS_THCMP_INT_MASK (0x40000000U)\r
+#define ADC_FLAGS_THCMP_INT_SHIFT (30U)\r
+/*! THCMP_INT - Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in\r
+ * the lower bits of this register are set to 1 (due to an enabled out-of-range or\r
+ * threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be\r
+ * individually enabled in the INTEN register to cause this interrupt. This bit will be cleared\r
+ * when all of the individual threshold flags are cleared via writing 1s to those bits.\r
+ */\r
+#define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK)\r
+#define ADC_FLAGS_OVR_INT_MASK (0x80000000U)\r
+#define ADC_FLAGS_OVR_INT_SHIFT (31U)\r
+/*! OVR_INT - Overrun Interrupt flag. Any overrun bit in any of the individual channel data\r
+ * registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers\r
+ * is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this\r
+ * interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all\r
+ * of the individual overrun bits have been cleared via reading the corresponding data registers.\r
+ */\r
+#define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK)\r
+/*! @} */\r
+\r
+/*! @name STARTUP - ADC Startup register. */\r
+/*! @{ */\r
+#define ADC_STARTUP_ADC_ENA_MASK (0x1U)\r
+#define ADC_STARTUP_ADC_ENA_SHIFT (0U)\r
+/*! ADC_ENA - ADC Enable bit. This bit can only be set to a 1 by software. It is cleared\r
+ * automatically whenever the ADC is powered down. This bit must not be set until at least 10 microseconds\r
+ * after the ADC is powered up (typically by altering a system-level ADC power control bit).\r
+ */\r
+#define ADC_STARTUP_ADC_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK)\r
+#define ADC_STARTUP_ADC_INIT_MASK (0x2U)\r
+#define ADC_STARTUP_ADC_INIT_SHIFT (1U)\r
+/*! ADC_INIT - ADC Initialization. After enabling the ADC (setting the ADC_ENA bit), the API routine\r
+ * will EITHER set this bit or the CALIB bit in the CALIB register, depending on whether or not\r
+ * calibration is required. Setting this bit will launch the 'dummy' conversion cycle that is\r
+ * required if a calibration is not performed. It will also reload the stored calibration value from\r
+ * a previous calibration unless the BYPASSCAL bit is set. This bit should only be set AFTER the\r
+ * ADC_ENA bit is set and after the CALIREQD bit is tested to determine whether a calibration or\r
+ * an ADC dummy conversion cycle is required. It should not be set during the same write that\r
+ * sets the ADC_ENA bit. This bit can only be set to a '1' by software. It is cleared automatically\r
+ * when the 'dummy' conversion cycle completes.\r
+ */\r
+#define ADC_STARTUP_ADC_INIT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK)\r
+/*! @} */\r
+\r
+/*! @name CALIB - ADC Calibration register. */\r
+/*! @{ */\r
+#define ADC_CALIB_CALIB_MASK (0x1U)\r
+#define ADC_CALIB_CALIB_SHIFT (0U)\r
+/*! CALIB - Calibration request. Setting this bit will launch an ADC calibration cycle. This bit can\r
+ * only be set to a '1' by software. It is cleared automatically when the calibration cycle\r
+ * completes.\r
+ */\r
+#define ADC_CALIB_CALIB(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK)\r
+#define ADC_CALIB_CALREQD_MASK (0x2U)\r
+#define ADC_CALIB_CALREQD_SHIFT (1U)\r
+/*! CALREQD - Calibration required. This read-only bit indicates if calibration is required when\r
+ * enabling the ADC. CALREQD will be '1' if no calibration has been run since the chip was\r
+ * powered-up and if the BYPASSCAL bit in the CTRL register is low. Software will test this bit to\r
+ * determine whether to initiate a calibration cycle or whether to set the ADC_INIT bit (in the STARTUP\r
+ * register) to launch the ADC initialization process which includes a 'dummy' conversion cycle.\r
+ * Note: A 'dummy' conversion cycle requires approximately 6 ADC clocks as opposed to 81 clocks\r
+ * required for calibration.\r
+ */\r
+#define ADC_CALIB_CALREQD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK)\r
+#define ADC_CALIB_CALVALUE_MASK (0x1FCU)\r
+#define ADC_CALIB_CALVALUE_SHIFT (2U)\r
+/*! CALVALUE - Calibration Value. This read-only field displays the calibration value established\r
+ * during last calibration cycle. This value is not typically of any use to the user.\r
+ */\r
+#define ADC_CALIB_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group ADC_Register_Masks */\r
+\r
+\r
+/* ADC - Peripheral instance base addresses */\r
+/** Peripheral ADC0 base address */\r
+#define ADC0_BASE (0x400A0000u)\r
+/** Peripheral ADC0 base pointer */\r
+#define ADC0 ((ADC_Type *)ADC0_BASE)\r
+/** Array initializer of ADC peripheral base addresses */\r
+#define ADC_BASE_ADDRS { ADC0_BASE }\r
+/** Array initializer of ADC peripheral base pointers */\r
+#define ADC_BASE_PTRS { ADC0 }\r
+/** Interrupt vectors for the ADC peripheral type */\r
+#define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn }\r
+#define ADC_THCMP_IRQS { ADC0_THCMP_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group ADC_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- ASYNC_SYSCON Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** ASYNC_SYSCON - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t ASYNCPRESETCTRL; /**< Async peripheral reset control, offset: 0x0 */\r
+ __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */\r
+ __O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */\r
+ uint8_t RESERVED_0[4];\r
+ __IO uint32_t ASYNCAPBCLKCTRL; /**< Async peripheral clock control, offset: 0x10 */\r
+ __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */\r
+ __O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */\r
+ uint8_t RESERVED_1[4];\r
+ __IO uint32_t ASYNCAPBCLKSELA; /**< Async APB clock source select A, offset: 0x20 */\r
+} ASYNC_SYSCON_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- ASYNC_SYSCON Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name ASYNCPRESETCTRL - Async peripheral reset control */\r
+/*! @{ */\r
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U)\r
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U)\r
+/*! CTIMER3 - Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.\r
+ */\r
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK)\r
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U)\r
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U)\r
+/*! CTIMER4 - Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.\r
+ */\r
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK)\r
+/*! @} */\r
+\r
+/*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */\r
+/*! @{ */\r
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU)\r
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U)\r
+/*! ARST_SET - Writing ones to this register sets the corresponding bit or bits in the\r
+ * ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in\r
+ * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.\r
+ */\r
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK)\r
+/*! @} */\r
+\r
+/*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */\r
+/*! @{ */\r
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU)\r
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U)\r
+/*! ARST_CLR - Writing ones to this register clears the corresponding bit or bits in the\r
+ * ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in\r
+ * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.\r
+ */\r
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK)\r
+/*! @} */\r
+\r
+/*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */\r
+/*! @{ */\r
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U)\r
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U)\r
+/*! CTIMER3 - Controls the clock for CTIMER3. 0 = Disable; 1 = Enable.\r
+ */\r
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK)\r
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U)\r
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U)\r
+/*! CTIMER4 - Controls the clock for CTIMER4. 0 = Disable; 1 = Enable.\r
+ */\r
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK)\r
+/*! @} */\r
+\r
+/*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */\r
+/*! @{ */\r
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU)\r
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U)\r
+/*! ACLK_SET - Writing ones to this register sets the corresponding bit or bits in the\r
+ * ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in\r
+ * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.\r
+ */\r
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK)\r
+/*! @} */\r
+\r
+/*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */\r
+/*! @{ */\r
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU)\r
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U)\r
+/*! ACLK_CLR - Writing ones to this register clears the corresponding bit or bits in the\r
+ * ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in\r
+ * ASYNCAPBCLKCTRL are reserved and only zeroes should be written to them.\r
+ */\r
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK)\r
+/*! @} */\r
+\r
+/*! @name ASYNCAPBCLKSELA - Async APB clock source select A */\r
+/*! @{ */\r
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK (0x3U)\r
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT (0U)\r
+/*! SEL - Clock source for asynchronous clock source selector A\r
+ * 0b00..Main clock (main_clk)\r
+ * 0b01..FRO 12 MHz (fro_12m)\r
+ * 0b10..Audio PLL clock.(AUDPLL_BYPASS)\r
+ * 0b11..fc6 fclk (fc6_fclk)\r
+ */\r
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group ASYNC_SYSCON_Register_Masks */\r
+\r
+\r
+/* ASYNC_SYSCON - Peripheral instance base addresses */\r
+/** Peripheral ASYNC_SYSCON base address */\r
+#define ASYNC_SYSCON_BASE (0x40040000u)\r
+/** Peripheral ASYNC_SYSCON base pointer */\r
+#define ASYNC_SYSCON ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE)\r
+/** Array initializer of ASYNC_SYSCON peripheral base addresses */\r
+#define ASYNC_SYSCON_BASE_ADDRS { ASYNC_SYSCON_BASE }\r
+/** Array initializer of ASYNC_SYSCON peripheral base pointers */\r
+#define ASYNC_SYSCON_BASE_PTRS { ASYNC_SYSCON }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- CAN Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** CAN - Register Layout Typedef */\r
+typedef struct {\r
+ uint8_t RESERVED_0[12];\r
+ __IO uint32_t DBTP; /**< Data Bit Timing Prescaler Register, offset: 0xC */\r
+ __IO uint32_t TEST; /**< Test Register, offset: 0x10 */\r
+ uint8_t RESERVED_1[4];\r
+ __IO uint32_t CCCR; /**< CC Control Register, offset: 0x18 */\r
+ __IO uint32_t NBTP; /**< Nominal Bit Timing and Prescaler Register, offset: 0x1C */\r
+ __IO uint32_t TSCC; /**< Timestamp Counter Configuration, offset: 0x20 */\r
+ __I uint32_t TSCV; /**< Timestamp Counter Value, offset: 0x24 */\r
+ __IO uint32_t TOCC; /**< Timeout Counter Configuration, offset: 0x28 */\r
+ __I uint32_t TOCV; /**< Timeout Counter Value, offset: 0x2C */\r
+ uint8_t RESERVED_2[16];\r
+ __I uint32_t ECR; /**< Error Counter Register, offset: 0x40 */\r
+ __I uint32_t PSR; /**< Protocol Status Register, offset: 0x44 */\r
+ __IO uint32_t TDCR; /**< Transmitter Delay Compensator Register, offset: 0x48 */\r
+ uint8_t RESERVED_3[4];\r
+ __IO uint32_t IR; /**< Interrupt Register, offset: 0x50 */\r
+ __IO uint32_t IE; /**< Interrupt Enable, offset: 0x54 */\r
+ __IO uint32_t ILS; /**< Interrupt Line Select, offset: 0x58 */\r
+ __IO uint32_t ILE; /**< Interrupt Line Enable, offset: 0x5C */\r
+ uint8_t RESERVED_4[32];\r
+ __IO uint32_t GFC; /**< Global Filter Configuration, offset: 0x80 */\r
+ __IO uint32_t SIDFC; /**< Standard ID Filter Configuration, offset: 0x84 */\r
+ __IO uint32_t XIDFC; /**< Extended ID Filter Configuration, offset: 0x88 */\r
+ uint8_t RESERVED_5[4];\r
+ __IO uint32_t XIDAM; /**< Extended ID AND Mask, offset: 0x90 */\r
+ __I uint32_t HPMS; /**< High Priority Message Status, offset: 0x94 */\r
+ __IO uint32_t NDAT1; /**< New Data 1, offset: 0x98 */\r
+ __IO uint32_t NDAT2; /**< New Data 2, offset: 0x9C */\r
+ __IO uint32_t RXF0C; /**< Rx FIFO 0 Configuration, offset: 0xA0 */\r
+ __I uint32_t RXF0S; /**< Rx FIFO 0 Status, offset: 0xA4 */\r
+ __IO uint32_t RXF0A; /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */\r
+ __IO uint32_t RXBC; /**< Rx Buffer Configuration, offset: 0xAC */\r
+ __IO uint32_t RXF1C; /**< Rx FIFO 1 Configuration, offset: 0xB0 */\r
+ __I uint32_t RXF1S; /**< Rx FIFO 1 Status, offset: 0xB4 */\r
+ __IO uint32_t RXF1A; /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */\r
+ __IO uint32_t RXESC; /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */\r
+ __IO uint32_t TXBC; /**< Tx Buffer Configuration, offset: 0xC0 */\r
+ __IO uint32_t TXFQS; /**< Tx FIFO/Queue Status, offset: 0xC4 */\r
+ __IO uint32_t TXESC; /**< Tx Buffer Element Size Configuration, offset: 0xC8 */\r
+ __I uint32_t TXBRP; /**< Tx Buffer Request Pending, offset: 0xCC */\r
+ __IO uint32_t TXBAR; /**< Tx Buffer Add Request, offset: 0xD0 */\r
+ __IO uint32_t TXBCR; /**< Tx Buffer Cancellation Request, offset: 0xD4 */\r
+ __I uint32_t TXBTO; /**< Tx Buffer Transmission Occurred, offset: 0xD8 */\r
+ __I uint32_t TXBCF; /**< Tx Buffer Cancellation Finished, offset: 0xDC */\r
+ __IO uint32_t TXBTIE; /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */\r
+ __IO uint32_t TXBCIE; /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */\r
+ uint8_t RESERVED_6[8];\r
+ __IO uint32_t TXEFC; /**< Tx Event FIFO Configuration, offset: 0xF0 */\r
+ __I uint32_t TXEFS; /**< Tx Event FIFO Status, offset: 0xF4 */\r
+ __IO uint32_t TXEFA; /**< Tx Event FIFO Acknowledge, offset: 0xF8 */\r
+ uint8_t RESERVED_7[260];\r
+ __IO uint32_t MRBA; /**< CAN Message RAM Base Address, offset: 0x200 */\r
+ uint8_t RESERVED_8[508];\r
+ __IO uint32_t ETSCC; /**< External Timestamp Counter Configuration, offset: 0x400 */\r
+ uint8_t RESERVED_9[508];\r
+ __IO uint32_t ETSCV; /**< External Timestamp Counter Value, offset: 0x600 */\r
+} CAN_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- CAN Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup CAN_Register_Masks CAN Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name DBTP - Data Bit Timing Prescaler Register */\r
+/*! @{ */\r
+#define CAN_DBTP_DSJW_MASK (0xFU)\r
+#define CAN_DBTP_DSJW_SHIFT (0U)\r
+/*! DSJW - Data (re)synchronization jump width.\r
+ */\r
+#define CAN_DBTP_DSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DSJW_SHIFT)) & CAN_DBTP_DSJW_MASK)\r
+#define CAN_DBTP_DTSEG2_MASK (0xF0U)\r
+#define CAN_DBTP_DTSEG2_SHIFT (4U)\r
+/*! DTSEG2 - Data time segment after sample point.\r
+ */\r
+#define CAN_DBTP_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG2_SHIFT)) & CAN_DBTP_DTSEG2_MASK)\r
+#define CAN_DBTP_DTSEG1_MASK (0x1F00U)\r
+#define CAN_DBTP_DTSEG1_SHIFT (8U)\r
+/*! DTSEG1 - Data time segment before sample point.\r
+ */\r
+#define CAN_DBTP_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG1_SHIFT)) & CAN_DBTP_DTSEG1_MASK)\r
+#define CAN_DBTP_DBRP_MASK (0x1F0000U)\r
+#define CAN_DBTP_DBRP_SHIFT (16U)\r
+/*! DBRP - Data bit rate prescaler.\r
+ */\r
+#define CAN_DBTP_DBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DBRP_SHIFT)) & CAN_DBTP_DBRP_MASK)\r
+#define CAN_DBTP_TDC_MASK (0x800000U)\r
+#define CAN_DBTP_TDC_SHIFT (23U)\r
+/*! TDC - Transmitter delay compensation.\r
+ */\r
+#define CAN_DBTP_TDC(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_TDC_SHIFT)) & CAN_DBTP_TDC_MASK)\r
+/*! @} */\r
+\r
+/*! @name TEST - Test Register */\r
+/*! @{ */\r
+#define CAN_TEST_LBCK_MASK (0x10U)\r
+#define CAN_TEST_LBCK_SHIFT (4U)\r
+/*! LBCK - Loop back mode.\r
+ */\r
+#define CAN_TEST_LBCK(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK)\r
+#define CAN_TEST_TX_MASK (0x60U)\r
+#define CAN_TEST_TX_SHIFT (5U)\r
+/*! TX - Control of transmit pin.\r
+ */\r
+#define CAN_TEST_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK)\r
+#define CAN_TEST_RX_MASK (0x80U)\r
+#define CAN_TEST_RX_SHIFT (7U)\r
+/*! RX - Monitors the actual value of the CAN_RXD.\r
+ */\r
+#define CAN_TEST_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK)\r
+/*! @} */\r
+\r
+/*! @name CCCR - CC Control Register */\r
+/*! @{ */\r
+#define CAN_CCCR_INIT_MASK (0x1U)\r
+#define CAN_CCCR_INIT_SHIFT (0U)\r
+/*! INIT - Initialization.\r
+ */\r
+#define CAN_CCCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK)\r
+#define CAN_CCCR_CCE_MASK (0x2U)\r
+#define CAN_CCCR_CCE_SHIFT (1U)\r
+/*! CCE - Configuration change enable.\r
+ */\r
+#define CAN_CCCR_CCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK)\r
+#define CAN_CCCR_ASM_MASK (0x4U)\r
+#define CAN_CCCR_ASM_SHIFT (2U)\r
+/*! ASM - Restricted operational mode.\r
+ */\r
+#define CAN_CCCR_ASM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK)\r
+#define CAN_CCCR_CSA_MASK (0x8U)\r
+#define CAN_CCCR_CSA_SHIFT (3U)\r
+/*! CSA - Clock Stop Acknowledge.\r
+ */\r
+#define CAN_CCCR_CSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK)\r
+#define CAN_CCCR_CSR_MASK (0x10U)\r
+#define CAN_CCCR_CSR_SHIFT (4U)\r
+/*! CSR - Clock Stop Request.\r
+ */\r
+#define CAN_CCCR_CSR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK)\r
+#define CAN_CCCR_MON_MASK (0x20U)\r
+#define CAN_CCCR_MON_SHIFT (5U)\r
+/*! MON - Bus monitoring mode.\r
+ */\r
+#define CAN_CCCR_MON(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK)\r
+#define CAN_CCCR_DAR_MASK (0x40U)\r
+#define CAN_CCCR_DAR_SHIFT (6U)\r
+/*! DAR - Disable automatic retransmission.\r
+ */\r
+#define CAN_CCCR_DAR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK)\r
+#define CAN_CCCR_TEST_MASK (0x80U)\r
+#define CAN_CCCR_TEST_SHIFT (7U)\r
+/*! TEST - Test mode enable.\r
+ */\r
+#define CAN_CCCR_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK)\r
+#define CAN_CCCR_FDOE_MASK (0x100U)\r
+#define CAN_CCCR_FDOE_SHIFT (8U)\r
+/*! FDOE - CAN FD operation enable.\r
+ */\r
+#define CAN_CCCR_FDOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_FDOE_SHIFT)) & CAN_CCCR_FDOE_MASK)\r
+#define CAN_CCCR_BRSE_MASK (0x200U)\r
+#define CAN_CCCR_BRSE_SHIFT (9U)\r
+/*! BRSE - When CAN FD operation is disabled, this bit is not evaluated.\r
+ */\r
+#define CAN_CCCR_BRSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_BRSE_SHIFT)) & CAN_CCCR_BRSE_MASK)\r
+#define CAN_CCCR_PXHD_MASK (0x1000U)\r
+#define CAN_CCCR_PXHD_SHIFT (12U)\r
+/*! PXHD - Protocol exception handling disable.\r
+ */\r
+#define CAN_CCCR_PXHD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK)\r
+#define CAN_CCCR_EFBI_MASK (0x2000U)\r
+#define CAN_CCCR_EFBI_SHIFT (13U)\r
+/*! EFBI - Edge filtering during bus integration.\r
+ */\r
+#define CAN_CCCR_EFBI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK)\r
+#define CAN_CCCR_TXP_MASK (0x4000U)\r
+#define CAN_CCCR_TXP_SHIFT (14U)\r
+/*! TXP - Transmit pause.\r
+ */\r
+#define CAN_CCCR_TXP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK)\r
+#define CAN_CCCR_NISO_MASK (0x8000U)\r
+#define CAN_CCCR_NISO_SHIFT (15U)\r
+/*! NISO - Non ISO operation.\r
+ */\r
+#define CAN_CCCR_NISO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_NISO_SHIFT)) & CAN_CCCR_NISO_MASK)\r
+/*! @} */\r
+\r
+/*! @name NBTP - Nominal Bit Timing and Prescaler Register */\r
+/*! @{ */\r
+#define CAN_NBTP_NTSEG2_MASK (0x7FU)\r
+#define CAN_NBTP_NTSEG2_SHIFT (0U)\r
+/*! NTSEG2 - Nominal time segment after sample point.\r
+ */\r
+#define CAN_NBTP_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK)\r
+#define CAN_NBTP_NTSEG1_MASK (0xFF00U)\r
+#define CAN_NBTP_NTSEG1_SHIFT (8U)\r
+/*! NTSEG1 - Nominal time segment before sample point.\r
+ */\r
+#define CAN_NBTP_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK)\r
+#define CAN_NBTP_NBRP_MASK (0x1FF0000U)\r
+#define CAN_NBTP_NBRP_SHIFT (16U)\r
+/*! NBRP - Nominal bit rate prescaler.\r
+ */\r
+#define CAN_NBTP_NBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK)\r
+#define CAN_NBTP_NSJW_MASK (0xFE000000U)\r
+#define CAN_NBTP_NSJW_SHIFT (25U)\r
+/*! NSJW - Nominal (re)synchronization jump width.\r
+ */\r
+#define CAN_NBTP_NSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK)\r
+/*! @} */\r
+\r
+/*! @name TSCC - Timestamp Counter Configuration */\r
+/*! @{ */\r
+#define CAN_TSCC_TSS_MASK (0x3U)\r
+#define CAN_TSCC_TSS_SHIFT (0U)\r
+/*! TSS - Timestamp select.\r
+ */\r
+#define CAN_TSCC_TSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK)\r
+#define CAN_TSCC_TCP_MASK (0xF0000U)\r
+#define CAN_TSCC_TCP_SHIFT (16U)\r
+/*! TCP - Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times.\r
+ */\r
+#define CAN_TSCC_TCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK)\r
+/*! @} */\r
+\r
+/*! @name TSCV - Timestamp Counter Value */\r
+/*! @{ */\r
+#define CAN_TSCV_TSC_MASK (0xFFFFU)\r
+#define CAN_TSCV_TSC_SHIFT (0U)\r
+/*! TSC - Timestamp counter.\r
+ */\r
+#define CAN_TSCV_TSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK)\r
+/*! @} */\r
+\r
+/*! @name TOCC - Timeout Counter Configuration */\r
+/*! @{ */\r
+#define CAN_TOCC_ETOC_MASK (0x1U)\r
+#define CAN_TOCC_ETOC_SHIFT (0U)\r
+/*! ETOC - Enable timeout counter.\r
+ */\r
+#define CAN_TOCC_ETOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK)\r
+#define CAN_TOCC_TOS_MASK (0x6U)\r
+#define CAN_TOCC_TOS_SHIFT (1U)\r
+/*! TOS - Timeout select.\r
+ */\r
+#define CAN_TOCC_TOS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK)\r
+#define CAN_TOCC_TOP_MASK (0xFFFF0000U)\r
+#define CAN_TOCC_TOP_SHIFT (16U)\r
+/*! TOP - Timeout period.\r
+ */\r
+#define CAN_TOCC_TOP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK)\r
+/*! @} */\r
+\r
+/*! @name TOCV - Timeout Counter Value */\r
+/*! @{ */\r
+#define CAN_TOCV_TOC_MASK (0xFFFFU)\r
+#define CAN_TOCV_TOC_SHIFT (0U)\r
+/*! TOC - Timeout counter.\r
+ */\r
+#define CAN_TOCV_TOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK)\r
+/*! @} */\r
+\r
+/*! @name ECR - Error Counter Register */\r
+/*! @{ */\r
+#define CAN_ECR_TEC_MASK (0xFFU)\r
+#define CAN_ECR_TEC_SHIFT (0U)\r
+/*! TEC - Transmit error counter.\r
+ */\r
+#define CAN_ECR_TEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK)\r
+#define CAN_ECR_REC_MASK (0x7F00U)\r
+#define CAN_ECR_REC_SHIFT (8U)\r
+/*! REC - Receive error counter.\r
+ */\r
+#define CAN_ECR_REC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK)\r
+#define CAN_ECR_RP_MASK (0x8000U)\r
+#define CAN_ECR_RP_SHIFT (15U)\r
+/*! RP - Receive error passive.\r
+ */\r
+#define CAN_ECR_RP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK)\r
+#define CAN_ECR_CEL_MASK (0xFF0000U)\r
+#define CAN_ECR_CEL_SHIFT (16U)\r
+/*! CEL - CAN error logging.\r
+ */\r
+#define CAN_ECR_CEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name PSR - Protocol Status Register */\r
+/*! @{ */\r
+#define CAN_PSR_LEC_MASK (0x7U)\r
+#define CAN_PSR_LEC_SHIFT (0U)\r
+/*! LEC - Last error code.\r
+ */\r
+#define CAN_PSR_LEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK)\r
+#define CAN_PSR_ACT_MASK (0x18U)\r
+#define CAN_PSR_ACT_SHIFT (3U)\r
+/*! ACT - Activity.\r
+ */\r
+#define CAN_PSR_ACT(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK)\r
+#define CAN_PSR_EP_MASK (0x20U)\r
+#define CAN_PSR_EP_SHIFT (5U)\r
+/*! EP - Error Passive.\r
+ */\r
+#define CAN_PSR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK)\r
+#define CAN_PSR_EW_MASK (0x40U)\r
+#define CAN_PSR_EW_SHIFT (6U)\r
+/*! EW - Warning status.\r
+ */\r
+#define CAN_PSR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK)\r
+#define CAN_PSR_BO_MASK (0x80U)\r
+#define CAN_PSR_BO_SHIFT (7U)\r
+/*! BO - Bus Off Status.\r
+ */\r
+#define CAN_PSR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK)\r
+#define CAN_PSR_DLEC_MASK (0x700U)\r
+#define CAN_PSR_DLEC_SHIFT (8U)\r
+/*! DLEC - Data phase last error code.\r
+ */\r
+#define CAN_PSR_DLEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_DLEC_SHIFT)) & CAN_PSR_DLEC_MASK)\r
+#define CAN_PSR_RESI_MASK (0x800U)\r
+#define CAN_PSR_RESI_SHIFT (11U)\r
+/*! RESI - ESI flag of the last received CAN FD message.\r
+ */\r
+#define CAN_PSR_RESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RESI_SHIFT)) & CAN_PSR_RESI_MASK)\r
+#define CAN_PSR_RBRS_MASK (0x1000U)\r
+#define CAN_PSR_RBRS_SHIFT (12U)\r
+/*! RBRS - BRS flag of last received CAN FD message.\r
+ */\r
+#define CAN_PSR_RBRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RBRS_SHIFT)) & CAN_PSR_RBRS_MASK)\r
+#define CAN_PSR_RFDF_MASK (0x2000U)\r
+#define CAN_PSR_RFDF_SHIFT (13U)\r
+/*! RFDF - Received a CAN FD message.\r
+ */\r
+#define CAN_PSR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RFDF_SHIFT)) & CAN_PSR_RFDF_MASK)\r
+#define CAN_PSR_PXE_MASK (0x4000U)\r
+#define CAN_PSR_PXE_SHIFT (14U)\r
+/*! PXE - Protocol exception event.\r
+ */\r
+#define CAN_PSR_PXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK)\r
+#define CAN_PSR_TDCV_MASK (0x7F0000U)\r
+#define CAN_PSR_TDCV_SHIFT (16U)\r
+/*! TDCV - Transmitter delay compensation value.\r
+ */\r
+#define CAN_PSR_TDCV(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK)\r
+/*! @} */\r
+\r
+/*! @name TDCR - Transmitter Delay Compensator Register */\r
+/*! @{ */\r
+#define CAN_TDCR_TDCF_MASK (0x7FU)\r
+#define CAN_TDCR_TDCF_SHIFT (0U)\r
+/*! TDCF - Transmitter delay compensation filter window length.\r
+ */\r
+#define CAN_TDCR_TDCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK)\r
+#define CAN_TDCR_TDCO_MASK (0x7F00U)\r
+#define CAN_TDCR_TDCO_SHIFT (8U)\r
+/*! TDCO - Transmitter delay compensation offset.\r
+ */\r
+#define CAN_TDCR_TDCO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK)\r
+/*! @} */\r
+\r
+/*! @name IR - Interrupt Register */\r
+/*! @{ */\r
+#define CAN_IR_RF0N_MASK (0x1U)\r
+#define CAN_IR_RF0N_SHIFT (0U)\r
+/*! RF0N - Rx FIFO 0 new message.\r
+ */\r
+#define CAN_IR_RF0N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK)\r
+#define CAN_IR_RF0W_MASK (0x2U)\r
+#define CAN_IR_RF0W_SHIFT (1U)\r
+/*! RF0W - Rx FIFO 0 watermark reached.\r
+ */\r
+#define CAN_IR_RF0W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK)\r
+#define CAN_IR_RF0F_MASK (0x4U)\r
+#define CAN_IR_RF0F_SHIFT (2U)\r
+/*! RF0F - Rx FIFO 0 full.\r
+ */\r
+#define CAN_IR_RF0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK)\r
+#define CAN_IR_RF0L_MASK (0x8U)\r
+#define CAN_IR_RF0L_SHIFT (3U)\r
+/*! RF0L - Rx FIFO 0 message lost.\r
+ */\r
+#define CAN_IR_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK)\r
+#define CAN_IR_RF1N_MASK (0x10U)\r
+#define CAN_IR_RF1N_SHIFT (4U)\r
+/*! RF1N - Rx FIFO 1 new message.\r
+ */\r
+#define CAN_IR_RF1N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK)\r
+#define CAN_IR_RF1W_MASK (0x20U)\r
+#define CAN_IR_RF1W_SHIFT (5U)\r
+/*! RF1W - Rx FIFO 1 watermark reached.\r
+ */\r
+#define CAN_IR_RF1W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK)\r
+#define CAN_IR_RF1F_MASK (0x40U)\r
+#define CAN_IR_RF1F_SHIFT (6U)\r
+/*! RF1F - Rx FIFO 1 full.\r
+ */\r
+#define CAN_IR_RF1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK)\r
+#define CAN_IR_RF1L_MASK (0x80U)\r
+#define CAN_IR_RF1L_SHIFT (7U)\r
+/*! RF1L - Rx FIFO 1 message lost.\r
+ */\r
+#define CAN_IR_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK)\r
+#define CAN_IR_HPM_MASK (0x100U)\r
+#define CAN_IR_HPM_SHIFT (8U)\r
+/*! HPM - High priority message.\r
+ */\r
+#define CAN_IR_HPM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK)\r
+#define CAN_IR_TC_MASK (0x200U)\r
+#define CAN_IR_TC_SHIFT (9U)\r
+/*! TC - Transmission completed.\r
+ */\r
+#define CAN_IR_TC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK)\r
+#define CAN_IR_TCF_MASK (0x400U)\r
+#define CAN_IR_TCF_SHIFT (10U)\r
+/*! TCF - Transmission cancellation finished.\r
+ */\r
+#define CAN_IR_TCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK)\r
+#define CAN_IR_TFE_MASK (0x800U)\r
+#define CAN_IR_TFE_SHIFT (11U)\r
+/*! TFE - Tx FIFO empty.\r
+ */\r
+#define CAN_IR_TFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK)\r
+#define CAN_IR_TEFN_MASK (0x1000U)\r
+#define CAN_IR_TEFN_SHIFT (12U)\r
+/*! TEFN - Tx event FIFO new entry.\r
+ */\r
+#define CAN_IR_TEFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK)\r
+#define CAN_IR_TEFW_MASK (0x2000U)\r
+#define CAN_IR_TEFW_SHIFT (13U)\r
+/*! TEFW - Tx event FIFO watermark reached.\r
+ */\r
+#define CAN_IR_TEFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK)\r
+#define CAN_IR_TEFF_MASK (0x4000U)\r
+#define CAN_IR_TEFF_SHIFT (14U)\r
+/*! TEFF - Tx event FIFO full.\r
+ */\r
+#define CAN_IR_TEFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK)\r
+#define CAN_IR_TEFL_MASK (0x8000U)\r
+#define CAN_IR_TEFL_SHIFT (15U)\r
+/*! TEFL - Tx event FIFO element lost.\r
+ */\r
+#define CAN_IR_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK)\r
+#define CAN_IR_TSW_MASK (0x10000U)\r
+#define CAN_IR_TSW_SHIFT (16U)\r
+/*! TSW - Timestamp wraparound.\r
+ */\r
+#define CAN_IR_TSW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK)\r
+#define CAN_IR_MRAF_MASK (0x20000U)\r
+#define CAN_IR_MRAF_SHIFT (17U)\r
+/*! MRAF - Message RAM access failure.\r
+ */\r
+#define CAN_IR_MRAF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK)\r
+#define CAN_IR_TOO_MASK (0x40000U)\r
+#define CAN_IR_TOO_SHIFT (18U)\r
+/*! TOO - Timeout occurred.\r
+ */\r
+#define CAN_IR_TOO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK)\r
+#define CAN_IR_DRX_MASK (0x80000U)\r
+#define CAN_IR_DRX_SHIFT (19U)\r
+/*! DRX - Message stored in dedicated Rx buffer.\r
+ */\r
+#define CAN_IR_DRX(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK)\r
+#define CAN_IR_BEC_MASK (0x100000U)\r
+#define CAN_IR_BEC_SHIFT (20U)\r
+/*! BEC - Bit error corrected.\r
+ */\r
+#define CAN_IR_BEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK)\r
+#define CAN_IR_BEU_MASK (0x200000U)\r
+#define CAN_IR_BEU_SHIFT (21U)\r
+/*! BEU - Bit error uncorrected.\r
+ */\r
+#define CAN_IR_BEU(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK)\r
+#define CAN_IR_ELO_MASK (0x400000U)\r
+#define CAN_IR_ELO_SHIFT (22U)\r
+/*! ELO - Error logging overflow.\r
+ */\r
+#define CAN_IR_ELO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK)\r
+#define CAN_IR_EP_MASK (0x800000U)\r
+#define CAN_IR_EP_SHIFT (23U)\r
+/*! EP - Error passive.\r
+ */\r
+#define CAN_IR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK)\r
+#define CAN_IR_EW_MASK (0x1000000U)\r
+#define CAN_IR_EW_SHIFT (24U)\r
+/*! EW - Warning status.\r
+ */\r
+#define CAN_IR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK)\r
+#define CAN_IR_BO_MASK (0x2000000U)\r
+#define CAN_IR_BO_SHIFT (25U)\r
+/*! BO - Bus_Off Status.\r
+ */\r
+#define CAN_IR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK)\r
+#define CAN_IR_WDI_MASK (0x4000000U)\r
+#define CAN_IR_WDI_SHIFT (26U)\r
+/*! WDI - Watchdog interrupt.\r
+ */\r
+#define CAN_IR_WDI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK)\r
+#define CAN_IR_PEA_MASK (0x8000000U)\r
+#define CAN_IR_PEA_SHIFT (27U)\r
+/*! PEA - Protocol error in arbitration phase.\r
+ */\r
+#define CAN_IR_PEA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK)\r
+#define CAN_IR_PED_MASK (0x10000000U)\r
+#define CAN_IR_PED_SHIFT (28U)\r
+/*! PED - Protocol error in data phase.\r
+ */\r
+#define CAN_IR_PED(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK)\r
+#define CAN_IR_ARA_MASK (0x20000000U)\r
+#define CAN_IR_ARA_SHIFT (29U)\r
+/*! ARA - Access to reserved address.\r
+ */\r
+#define CAN_IR_ARA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK)\r
+/*! @} */\r
+\r
+/*! @name IE - Interrupt Enable */\r
+/*! @{ */\r
+#define CAN_IE_RF0NE_MASK (0x1U)\r
+#define CAN_IE_RF0NE_SHIFT (0U)\r
+/*! RF0NE - Rx FIFO 0 new message interrupt enable.\r
+ */\r
+#define CAN_IE_RF0NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK)\r
+#define CAN_IE_RF0WE_MASK (0x2U)\r
+#define CAN_IE_RF0WE_SHIFT (1U)\r
+/*! RF0WE - Rx FIFO 0 watermark reached interrupt enable.\r
+ */\r
+#define CAN_IE_RF0WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK)\r
+#define CAN_IE_RF0FE_MASK (0x4U)\r
+#define CAN_IE_RF0FE_SHIFT (2U)\r
+/*! RF0FE - Rx FIFO 0 full interrupt enable.\r
+ */\r
+#define CAN_IE_RF0FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK)\r
+#define CAN_IE_RF0LE_MASK (0x8U)\r
+#define CAN_IE_RF0LE_SHIFT (3U)\r
+/*! RF0LE - Rx FIFO 0 message lost interrupt enable.\r
+ */\r
+#define CAN_IE_RF0LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK)\r
+#define CAN_IE_RF1NE_MASK (0x10U)\r
+#define CAN_IE_RF1NE_SHIFT (4U)\r
+/*! RF1NE - Rx FIFO 1 new message interrupt enable.\r
+ */\r
+#define CAN_IE_RF1NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK)\r
+#define CAN_IE_RF1WE_MASK (0x20U)\r
+#define CAN_IE_RF1WE_SHIFT (5U)\r
+/*! RF1WE - Rx FIFO 1 watermark reached interrupt enable.\r
+ */\r
+#define CAN_IE_RF1WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK)\r
+#define CAN_IE_RF1FE_MASK (0x40U)\r
+#define CAN_IE_RF1FE_SHIFT (6U)\r
+/*! RF1FE - Rx FIFO 1 full interrupt enable.\r
+ */\r
+#define CAN_IE_RF1FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK)\r
+#define CAN_IE_RF1LE_MASK (0x80U)\r
+#define CAN_IE_RF1LE_SHIFT (7U)\r
+/*! RF1LE - Rx FIFO 1 message lost interrupt enable.\r
+ */\r
+#define CAN_IE_RF1LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK)\r
+#define CAN_IE_HPME_MASK (0x100U)\r
+#define CAN_IE_HPME_SHIFT (8U)\r
+/*! HPME - High priority message interrupt enable.\r
+ */\r
+#define CAN_IE_HPME(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK)\r
+#define CAN_IE_TCE_MASK (0x200U)\r
+#define CAN_IE_TCE_SHIFT (9U)\r
+/*! TCE - Transmission completed interrupt enable.\r
+ */\r
+#define CAN_IE_TCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK)\r
+#define CAN_IE_TCFE_MASK (0x400U)\r
+#define CAN_IE_TCFE_SHIFT (10U)\r
+/*! TCFE - Transmission cancellation finished interrupt enable.\r
+ */\r
+#define CAN_IE_TCFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK)\r
+#define CAN_IE_TFEE_MASK (0x800U)\r
+#define CAN_IE_TFEE_SHIFT (11U)\r
+/*! TFEE - Tx FIFO empty interrupt enable.\r
+ */\r
+#define CAN_IE_TFEE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK)\r
+#define CAN_IE_TEFNE_MASK (0x1000U)\r
+#define CAN_IE_TEFNE_SHIFT (12U)\r
+/*! TEFNE - Tx event FIFO new entry interrupt enable.\r
+ */\r
+#define CAN_IE_TEFNE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK)\r
+#define CAN_IE_TEFWE_MASK (0x2000U)\r
+#define CAN_IE_TEFWE_SHIFT (13U)\r
+/*! TEFWE - Tx event FIFO watermark reached interrupt enable.\r
+ */\r
+#define CAN_IE_TEFWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK)\r
+#define CAN_IE_TEFFE_MASK (0x4000U)\r
+#define CAN_IE_TEFFE_SHIFT (14U)\r
+/*! TEFFE - Tx event FIFO full interrupt enable.\r
+ */\r
+#define CAN_IE_TEFFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK)\r
+#define CAN_IE_TEFLE_MASK (0x8000U)\r
+#define CAN_IE_TEFLE_SHIFT (15U)\r
+/*! TEFLE - Tx event FIFO element lost interrupt enable.\r
+ */\r
+#define CAN_IE_TEFLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK)\r
+#define CAN_IE_TSWE_MASK (0x10000U)\r
+#define CAN_IE_TSWE_SHIFT (16U)\r
+/*! TSWE - Timestamp wraparound interrupt enable.\r
+ */\r
+#define CAN_IE_TSWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK)\r
+#define CAN_IE_MRAFE_MASK (0x20000U)\r
+#define CAN_IE_MRAFE_SHIFT (17U)\r
+/*! MRAFE - Message RAM access failure interrupt enable.\r
+ */\r
+#define CAN_IE_MRAFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK)\r
+#define CAN_IE_TOOE_MASK (0x40000U)\r
+#define CAN_IE_TOOE_SHIFT (18U)\r
+/*! TOOE - Timeout occurred interrupt enable.\r
+ */\r
+#define CAN_IE_TOOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK)\r
+#define CAN_IE_DRXE_MASK (0x80000U)\r
+#define CAN_IE_DRXE_SHIFT (19U)\r
+/*! DRXE - Message stored in dedicated Rx buffer interrupt enable.\r
+ */\r
+#define CAN_IE_DRXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK)\r
+#define CAN_IE_BECE_MASK (0x100000U)\r
+#define CAN_IE_BECE_SHIFT (20U)\r
+/*! BECE - Bit error corrected interrupt enable.\r
+ */\r
+#define CAN_IE_BECE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK)\r
+#define CAN_IE_BEUE_MASK (0x200000U)\r
+#define CAN_IE_BEUE_SHIFT (21U)\r
+/*! BEUE - Bit error uncorrected interrupt enable.\r
+ */\r
+#define CAN_IE_BEUE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK)\r
+#define CAN_IE_ELOE_MASK (0x400000U)\r
+#define CAN_IE_ELOE_SHIFT (22U)\r
+/*! ELOE - Error logging overflow interrupt enable.\r
+ */\r
+#define CAN_IE_ELOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK)\r
+#define CAN_IE_EPE_MASK (0x800000U)\r
+#define CAN_IE_EPE_SHIFT (23U)\r
+/*! EPE - Error passive interrupt enable.\r
+ */\r
+#define CAN_IE_EPE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK)\r
+#define CAN_IE_EWE_MASK (0x1000000U)\r
+#define CAN_IE_EWE_SHIFT (24U)\r
+/*! EWE - Warning status interrupt enable.\r
+ */\r
+#define CAN_IE_EWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK)\r
+#define CAN_IE_BOE_MASK (0x2000000U)\r
+#define CAN_IE_BOE_SHIFT (25U)\r
+/*! BOE - Bus_Off Status interrupt enable.\r
+ */\r
+#define CAN_IE_BOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK)\r
+#define CAN_IE_WDIE_MASK (0x4000000U)\r
+#define CAN_IE_WDIE_SHIFT (26U)\r
+/*! WDIE - Watchdog interrupt enable.\r
+ */\r
+#define CAN_IE_WDIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK)\r
+#define CAN_IE_PEAE_MASK (0x8000000U)\r
+#define CAN_IE_PEAE_SHIFT (27U)\r
+/*! PEAE - Protocol error in arbitration phase interrupt enable.\r
+ */\r
+#define CAN_IE_PEAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK)\r
+#define CAN_IE_PEDE_MASK (0x10000000U)\r
+#define CAN_IE_PEDE_SHIFT (28U)\r
+/*! PEDE - Protocol error in data phase interrupt enable.\r
+ */\r
+#define CAN_IE_PEDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK)\r
+#define CAN_IE_ARAE_MASK (0x20000000U)\r
+#define CAN_IE_ARAE_SHIFT (29U)\r
+/*! ARAE - Access to reserved address interrupt enable.\r
+ */\r
+#define CAN_IE_ARAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK)\r
+/*! @} */\r
+\r
+/*! @name ILS - Interrupt Line Select */\r
+/*! @{ */\r
+#define CAN_ILS_RF0NL_MASK (0x1U)\r
+#define CAN_ILS_RF0NL_SHIFT (0U)\r
+/*! RF0NL - Rx FIFO 0 new message interrupt line.\r
+ */\r
+#define CAN_ILS_RF0NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK)\r
+#define CAN_ILS_RF0WL_MASK (0x2U)\r
+#define CAN_ILS_RF0WL_SHIFT (1U)\r
+/*! RF0WL - Rx FIFO 0 watermark reached interrupt line.\r
+ */\r
+#define CAN_ILS_RF0WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK)\r
+#define CAN_ILS_RF0FL_MASK (0x4U)\r
+#define CAN_ILS_RF0FL_SHIFT (2U)\r
+/*! RF0FL - Rx FIFO 0 full interrupt line.\r
+ */\r
+#define CAN_ILS_RF0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK)\r
+#define CAN_ILS_RF0LL_MASK (0x8U)\r
+#define CAN_ILS_RF0LL_SHIFT (3U)\r
+/*! RF0LL - Rx FIFO 0 message lost interrupt line.\r
+ */\r
+#define CAN_ILS_RF0LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK)\r
+#define CAN_ILS_RF1NL_MASK (0x10U)\r
+#define CAN_ILS_RF1NL_SHIFT (4U)\r
+/*! RF1NL - Rx FIFO 1 new message interrupt line.\r
+ */\r
+#define CAN_ILS_RF1NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK)\r
+#define CAN_ILS_RF1WL_MASK (0x20U)\r
+#define CAN_ILS_RF1WL_SHIFT (5U)\r
+/*! RF1WL - Rx FIFO 1 watermark reached interrupt line.\r
+ */\r
+#define CAN_ILS_RF1WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK)\r
+#define CAN_ILS_RF1FL_MASK (0x40U)\r
+#define CAN_ILS_RF1FL_SHIFT (6U)\r
+/*! RF1FL - Rx FIFO 1 full interrupt line.\r
+ */\r
+#define CAN_ILS_RF1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK)\r
+#define CAN_ILS_RF1LL_MASK (0x80U)\r
+#define CAN_ILS_RF1LL_SHIFT (7U)\r
+/*! RF1LL - Rx FIFO 1 message lost interrupt line.\r
+ */\r
+#define CAN_ILS_RF1LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK)\r
+#define CAN_ILS_HPML_MASK (0x100U)\r
+#define CAN_ILS_HPML_SHIFT (8U)\r
+/*! HPML - High priority message interrupt line.\r
+ */\r
+#define CAN_ILS_HPML(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK)\r
+#define CAN_ILS_TCL_MASK (0x200U)\r
+#define CAN_ILS_TCL_SHIFT (9U)\r
+/*! TCL - Transmission completed interrupt line.\r
+ */\r
+#define CAN_ILS_TCL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK)\r
+#define CAN_ILS_TCFL_MASK (0x400U)\r
+#define CAN_ILS_TCFL_SHIFT (10U)\r
+/*! TCFL - Transmission cancellation finished interrupt line.\r
+ */\r
+#define CAN_ILS_TCFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK)\r
+#define CAN_ILS_TFEL_MASK (0x800U)\r
+#define CAN_ILS_TFEL_SHIFT (11U)\r
+/*! TFEL - Tx FIFO empty interrupt line.\r
+ */\r
+#define CAN_ILS_TFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK)\r
+#define CAN_ILS_TEFNL_MASK (0x1000U)\r
+#define CAN_ILS_TEFNL_SHIFT (12U)\r
+/*! TEFNL - Tx event FIFO new entry interrupt line.\r
+ */\r
+#define CAN_ILS_TEFNL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK)\r
+#define CAN_ILS_TEFWL_MASK (0x2000U)\r
+#define CAN_ILS_TEFWL_SHIFT (13U)\r
+/*! TEFWL - Tx event FIFO watermark reached interrupt line.\r
+ */\r
+#define CAN_ILS_TEFWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK)\r
+#define CAN_ILS_TEFFL_MASK (0x4000U)\r
+#define CAN_ILS_TEFFL_SHIFT (14U)\r
+/*! TEFFL - Tx event FIFO full interrupt line.\r
+ */\r
+#define CAN_ILS_TEFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK)\r
+#define CAN_ILS_TEFLL_MASK (0x8000U)\r
+#define CAN_ILS_TEFLL_SHIFT (15U)\r
+/*! TEFLL - Tx event FIFO element lost interrupt line.\r
+ */\r
+#define CAN_ILS_TEFLL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK)\r
+#define CAN_ILS_TSWL_MASK (0x10000U)\r
+#define CAN_ILS_TSWL_SHIFT (16U)\r
+/*! TSWL - Timestamp wraparound interrupt line.\r
+ */\r
+#define CAN_ILS_TSWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK)\r
+#define CAN_ILS_MRAFL_MASK (0x20000U)\r
+#define CAN_ILS_MRAFL_SHIFT (17U)\r
+/*! MRAFL - Message RAM access failure interrupt line.\r
+ */\r
+#define CAN_ILS_MRAFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK)\r
+#define CAN_ILS_TOOL_MASK (0x40000U)\r
+#define CAN_ILS_TOOL_SHIFT (18U)\r
+/*! TOOL - Timeout occurred interrupt line.\r
+ */\r
+#define CAN_ILS_TOOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK)\r
+#define CAN_ILS_DRXL_MASK (0x80000U)\r
+#define CAN_ILS_DRXL_SHIFT (19U)\r
+/*! DRXL - Message stored in dedicated Rx buffer interrupt line.\r
+ */\r
+#define CAN_ILS_DRXL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK)\r
+#define CAN_ILS_BECL_MASK (0x100000U)\r
+#define CAN_ILS_BECL_SHIFT (20U)\r
+/*! BECL - Bit error corrected interrupt line.\r
+ */\r
+#define CAN_ILS_BECL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK)\r
+#define CAN_ILS_BEUL_MASK (0x200000U)\r
+#define CAN_ILS_BEUL_SHIFT (21U)\r
+/*! BEUL - Bit error uncorrected interrupt line.\r
+ */\r
+#define CAN_ILS_BEUL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK)\r
+#define CAN_ILS_ELOL_MASK (0x400000U)\r
+#define CAN_ILS_ELOL_SHIFT (22U)\r
+/*! ELOL - Error logging overflow interrupt line.\r
+ */\r
+#define CAN_ILS_ELOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK)\r
+#define CAN_ILS_EPL_MASK (0x800000U)\r
+#define CAN_ILS_EPL_SHIFT (23U)\r
+/*! EPL - Error passive interrupt line.\r
+ */\r
+#define CAN_ILS_EPL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK)\r
+#define CAN_ILS_EWL_MASK (0x1000000U)\r
+#define CAN_ILS_EWL_SHIFT (24U)\r
+/*! EWL - Warning status interrupt line.\r
+ */\r
+#define CAN_ILS_EWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK)\r
+#define CAN_ILS_BOL_MASK (0x2000000U)\r
+#define CAN_ILS_BOL_SHIFT (25U)\r
+/*! BOL - Bus_Off Status interrupt line.\r
+ */\r
+#define CAN_ILS_BOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK)\r
+#define CAN_ILS_WDIL_MASK (0x4000000U)\r
+#define CAN_ILS_WDIL_SHIFT (26U)\r
+/*! WDIL - Watchdog interrupt line.\r
+ */\r
+#define CAN_ILS_WDIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK)\r
+#define CAN_ILS_PEAL_MASK (0x8000000U)\r
+#define CAN_ILS_PEAL_SHIFT (27U)\r
+/*! PEAL - Protocol error in arbitration phase interrupt line.\r
+ */\r
+#define CAN_ILS_PEAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK)\r
+#define CAN_ILS_PEDL_MASK (0x10000000U)\r
+#define CAN_ILS_PEDL_SHIFT (28U)\r
+/*! PEDL - Protocol error in data phase interrupt line.\r
+ */\r
+#define CAN_ILS_PEDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK)\r
+#define CAN_ILS_ARAL_MASK (0x20000000U)\r
+#define CAN_ILS_ARAL_SHIFT (29U)\r
+/*! ARAL - Access to reserved address interrupt line.\r
+ */\r
+#define CAN_ILS_ARAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name ILE - Interrupt Line Enable */\r
+/*! @{ */\r
+#define CAN_ILE_EINT0_MASK (0x1U)\r
+#define CAN_ILE_EINT0_SHIFT (0U)\r
+/*! EINT0 - Enable interrupt line 0.\r
+ */\r
+#define CAN_ILE_EINT0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK)\r
+#define CAN_ILE_EINT1_MASK (0x2U)\r
+#define CAN_ILE_EINT1_SHIFT (1U)\r
+/*! EINT1 - Enable interrupt line 1.\r
+ */\r
+#define CAN_ILE_EINT1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK)\r
+/*! @} */\r
+\r
+/*! @name GFC - Global Filter Configuration */\r
+/*! @{ */\r
+#define CAN_GFC_RRFE_MASK (0x1U)\r
+#define CAN_GFC_RRFE_SHIFT (0U)\r
+/*! RRFE - Reject remote frames extended.\r
+ */\r
+#define CAN_GFC_RRFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK)\r
+#define CAN_GFC_RRFS_MASK (0x2U)\r
+#define CAN_GFC_RRFS_SHIFT (1U)\r
+/*! RRFS - Reject remote frames standard.\r
+ */\r
+#define CAN_GFC_RRFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK)\r
+#define CAN_GFC_ANFE_MASK (0xCU)\r
+#define CAN_GFC_ANFE_SHIFT (2U)\r
+/*! ANFE - Accept non-matching frames extended.\r
+ */\r
+#define CAN_GFC_ANFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK)\r
+#define CAN_GFC_ANFS_MASK (0x30U)\r
+#define CAN_GFC_ANFS_SHIFT (4U)\r
+/*! ANFS - Accept non-matching frames standard.\r
+ */\r
+#define CAN_GFC_ANFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK)\r
+/*! @} */\r
+\r
+/*! @name SIDFC - Standard ID Filter Configuration */\r
+/*! @{ */\r
+#define CAN_SIDFC_FLSSA_MASK (0xFFFCU)\r
+#define CAN_SIDFC_FLSSA_SHIFT (2U)\r
+/*! FLSSA - Filter list standard start address.\r
+ */\r
+#define CAN_SIDFC_FLSSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK)\r
+#define CAN_SIDFC_LSS_MASK (0xFF0000U)\r
+#define CAN_SIDFC_LSS_SHIFT (16U)\r
+/*! LSS - List size standard 0 = No standard message ID filter.\r
+ */\r
+#define CAN_SIDFC_LSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK)\r
+/*! @} */\r
+\r
+/*! @name XIDFC - Extended ID Filter Configuration */\r
+/*! @{ */\r
+#define CAN_XIDFC_FLESA_MASK (0xFFFCU)\r
+#define CAN_XIDFC_FLESA_SHIFT (2U)\r
+/*! FLESA - Filter list extended start address.\r
+ */\r
+#define CAN_XIDFC_FLESA(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK)\r
+#define CAN_XIDFC_LSE_MASK (0xFF0000U)\r
+#define CAN_XIDFC_LSE_SHIFT (16U)\r
+/*! LSE - List size extended 0 = No extended message ID filter.\r
+ */\r
+#define CAN_XIDFC_LSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK)\r
+/*! @} */\r
+\r
+/*! @name XIDAM - Extended ID AND Mask */\r
+/*! @{ */\r
+#define CAN_XIDAM_EIDM_MASK (0x1FFFFFFFU)\r
+#define CAN_XIDAM_EIDM_SHIFT (0U)\r
+/*! EIDM - Extended ID mask.\r
+ */\r
+#define CAN_XIDAM_EIDM(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK)\r
+/*! @} */\r
+\r
+/*! @name HPMS - High Priority Message Status */\r
+/*! @{ */\r
+#define CAN_HPMS_BIDX_MASK (0x3FU)\r
+#define CAN_HPMS_BIDX_SHIFT (0U)\r
+/*! BIDX - Buffer index.\r
+ */\r
+#define CAN_HPMS_BIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK)\r
+#define CAN_HPMS_MSI_MASK (0xC0U)\r
+#define CAN_HPMS_MSI_SHIFT (6U)\r
+/*! MSI - Message storage indicator.\r
+ */\r
+#define CAN_HPMS_MSI(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK)\r
+#define CAN_HPMS_FIDX_MASK (0x7F00U)\r
+#define CAN_HPMS_FIDX_SHIFT (8U)\r
+/*! FIDX - Filter index.\r
+ */\r
+#define CAN_HPMS_FIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK)\r
+#define CAN_HPMS_FLST_MASK (0x8000U)\r
+#define CAN_HPMS_FLST_SHIFT (15U)\r
+/*! FLST - Filter list.\r
+ */\r
+#define CAN_HPMS_FLST(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK)\r
+/*! @} */\r
+\r
+/*! @name NDAT1 - New Data 1 */\r
+/*! @{ */\r
+#define CAN_NDAT1_ND_MASK (0xFFFFFFFFU)\r
+#define CAN_NDAT1_ND_SHIFT (0U)\r
+/*! ND - New Data.\r
+ */\r
+#define CAN_NDAT1_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK)\r
+/*! @} */\r
+\r
+/*! @name NDAT2 - New Data 2 */\r
+/*! @{ */\r
+#define CAN_NDAT2_ND_MASK (0xFFFFFFFFU)\r
+#define CAN_NDAT2_ND_SHIFT (0U)\r
+/*! ND - New Data.\r
+ */\r
+#define CAN_NDAT2_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK)\r
+/*! @} */\r
+\r
+/*! @name RXF0C - Rx FIFO 0 Configuration */\r
+/*! @{ */\r
+#define CAN_RXF0C_F0SA_MASK (0xFFFCU)\r
+#define CAN_RXF0C_F0SA_SHIFT (2U)\r
+/*! F0SA - Rx FIFO 0 start address.\r
+ */\r
+#define CAN_RXF0C_F0SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK)\r
+#define CAN_RXF0C_F0S_MASK (0x7F0000U)\r
+#define CAN_RXF0C_F0S_SHIFT (16U)\r
+/*! F0S - Rx FIFO 0 size.\r
+ */\r
+#define CAN_RXF0C_F0S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK)\r
+#define CAN_RXF0C_F0WM_MASK (0x7F000000U)\r
+#define CAN_RXF0C_F0WM_SHIFT (24U)\r
+/*! F0WM - Rx FIFO 0 watermark 0 = Watermark interrupt disabled.\r
+ */\r
+#define CAN_RXF0C_F0WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK)\r
+#define CAN_RXF0C_F0OM_MASK (0x80000000U)\r
+#define CAN_RXF0C_F0OM_SHIFT (31U)\r
+/*! F0OM - FIFO 0 operation mode.\r
+ */\r
+#define CAN_RXF0C_F0OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK)\r
+/*! @} */\r
+\r
+/*! @name RXF0S - Rx FIFO 0 Status */\r
+/*! @{ */\r
+#define CAN_RXF0S_F0FL_MASK (0x7FU)\r
+#define CAN_RXF0S_F0FL_SHIFT (0U)\r
+/*! F0FL - Rx FIFO 0 fill level.\r
+ */\r
+#define CAN_RXF0S_F0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK)\r
+#define CAN_RXF0S_F0GI_MASK (0x3F00U)\r
+#define CAN_RXF0S_F0GI_SHIFT (8U)\r
+/*! F0GI - Rx FIFO 0 get index.\r
+ */\r
+#define CAN_RXF0S_F0GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK)\r
+#define CAN_RXF0S_F0PI_MASK (0x3F0000U)\r
+#define CAN_RXF0S_F0PI_SHIFT (16U)\r
+/*! F0PI - Rx FIFO 0 put index.\r
+ */\r
+#define CAN_RXF0S_F0PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK)\r
+#define CAN_RXF0S_F0F_MASK (0x1000000U)\r
+#define CAN_RXF0S_F0F_SHIFT (24U)\r
+/*! F0F - Rx FIFO 0 full.\r
+ */\r
+#define CAN_RXF0S_F0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK)\r
+#define CAN_RXF0S_RF0L_MASK (0x2000000U)\r
+#define CAN_RXF0S_RF0L_SHIFT (25U)\r
+/*! RF0L - Rx FIFO 0 message lost.\r
+ */\r
+#define CAN_RXF0S_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK)\r
+/*! @} */\r
+\r
+/*! @name RXF0A - Rx FIFO 0 Acknowledge */\r
+/*! @{ */\r
+#define CAN_RXF0A_F0AI_MASK (0x3FU)\r
+#define CAN_RXF0A_F0AI_SHIFT (0U)\r
+/*! F0AI - Rx FIFO 0 acknowledge index.\r
+ */\r
+#define CAN_RXF0A_F0AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK)\r
+/*! @} */\r
+\r
+/*! @name RXBC - Rx Buffer Configuration */\r
+/*! @{ */\r
+#define CAN_RXBC_RBSA_MASK (0xFFFCU)\r
+#define CAN_RXBC_RBSA_SHIFT (2U)\r
+/*! RBSA - Rx buffer start address.\r
+ */\r
+#define CAN_RXBC_RBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK)\r
+/*! @} */\r
+\r
+/*! @name RXF1C - Rx FIFO 1 Configuration */\r
+/*! @{ */\r
+#define CAN_RXF1C_F1SA_MASK (0xFFFCU)\r
+#define CAN_RXF1C_F1SA_SHIFT (2U)\r
+/*! F1SA - Rx FIFO 1 start address.\r
+ */\r
+#define CAN_RXF1C_F1SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK)\r
+#define CAN_RXF1C_F1S_MASK (0x7F0000U)\r
+#define CAN_RXF1C_F1S_SHIFT (16U)\r
+/*! F1S - Rx FIFO 1 size 0 = No Rx FIFO 1.\r
+ */\r
+#define CAN_RXF1C_F1S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK)\r
+#define CAN_RXF1C_F1WM_MASK (0x7F000000U)\r
+#define CAN_RXF1C_F1WM_SHIFT (24U)\r
+/*! F1WM - Rx FIFO 1 watermark 0 = Watermark interrupt disabled.\r
+ */\r
+#define CAN_RXF1C_F1WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK)\r
+#define CAN_RXF1C_F1OM_MASK (0x80000000U)\r
+#define CAN_RXF1C_F1OM_SHIFT (31U)\r
+/*! F1OM - FIFO 1 operation mode.\r
+ */\r
+#define CAN_RXF1C_F1OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK)\r
+/*! @} */\r
+\r
+/*! @name RXF1S - Rx FIFO 1 Status */\r
+/*! @{ */\r
+#define CAN_RXF1S_F1FL_MASK (0x7FU)\r
+#define CAN_RXF1S_F1FL_SHIFT (0U)\r
+/*! F1FL - Rx FIFO 1 fill level.\r
+ */\r
+#define CAN_RXF1S_F1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK)\r
+#define CAN_RXF1S_F1GI_MASK (0x3F00U)\r
+#define CAN_RXF1S_F1GI_SHIFT (8U)\r
+/*! F1GI - Rx FIFO 1 get index.\r
+ */\r
+#define CAN_RXF1S_F1GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK)\r
+#define CAN_RXF1S_F1PI_MASK (0x3F0000U)\r
+#define CAN_RXF1S_F1PI_SHIFT (16U)\r
+/*! F1PI - Rx FIFO 1 put index.\r
+ */\r
+#define CAN_RXF1S_F1PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK)\r
+#define CAN_RXF1S_F1F_MASK (0x1000000U)\r
+#define CAN_RXF1S_F1F_SHIFT (24U)\r
+/*! F1F - Rx FIFO 1 full.\r
+ */\r
+#define CAN_RXF1S_F1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK)\r
+#define CAN_RXF1S_RF1L_MASK (0x2000000U)\r
+#define CAN_RXF1S_RF1L_SHIFT (25U)\r
+/*! RF1L - Rx FIFO 1 message lost.\r
+ */\r
+#define CAN_RXF1S_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK)\r
+/*! @} */\r
+\r
+/*! @name RXF1A - Rx FIFO 1 Acknowledge */\r
+/*! @{ */\r
+#define CAN_RXF1A_F1AI_MASK (0x3FU)\r
+#define CAN_RXF1A_F1AI_SHIFT (0U)\r
+/*! F1AI - Rx FIFO 1 acknowledge index.\r
+ */\r
+#define CAN_RXF1A_F1AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK)\r
+/*! @} */\r
+\r
+/*! @name RXESC - Rx Buffer and FIFO Element Size Configuration */\r
+/*! @{ */\r
+#define CAN_RXESC_F0DS_MASK (0x7U)\r
+#define CAN_RXESC_F0DS_SHIFT (0U)\r
+/*! F0DS - Rx FIFO 0 data field size.\r
+ */\r
+#define CAN_RXESC_F0DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK)\r
+#define CAN_RXESC_F1DS_MASK (0x70U)\r
+#define CAN_RXESC_F1DS_SHIFT (4U)\r
+/*! F1DS - Rx FIFO 1 data field size.\r
+ */\r
+#define CAN_RXESC_F1DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK)\r
+#define CAN_RXESC_RBDS_MASK (0x700U)\r
+#define CAN_RXESC_RBDS_SHIFT (8U)\r
+/*! RBDS - .\r
+ */\r
+#define CAN_RXESC_RBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK)\r
+/*! @} */\r
+\r
+/*! @name TXBC - Tx Buffer Configuration */\r
+/*! @{ */\r
+#define CAN_TXBC_TBSA_MASK (0xFFFCU)\r
+#define CAN_TXBC_TBSA_SHIFT (2U)\r
+/*! TBSA - Tx buffers start address.\r
+ */\r
+#define CAN_TXBC_TBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK)\r
+#define CAN_TXBC_NDTB_MASK (0x3F0000U)\r
+#define CAN_TXBC_NDTB_SHIFT (16U)\r
+/*! NDTB - Number of dedicated transmit buffers 0 = No dedicated Tx buffers.\r
+ */\r
+#define CAN_TXBC_NDTB(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK)\r
+#define CAN_TXBC_TFQS_MASK (0x3F000000U)\r
+#define CAN_TXBC_TFQS_SHIFT (24U)\r
+/*! TFQS - Transmit FIFO/queue size 0 = No tx FIFO/Queue.\r
+ */\r
+#define CAN_TXBC_TFQS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK)\r
+#define CAN_TXBC_TFQM_MASK (0x40000000U)\r
+#define CAN_TXBC_TFQM_SHIFT (30U)\r
+/*! TFQM - Tx FIFO/queue mode.\r
+ */\r
+#define CAN_TXBC_TFQM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK)\r
+/*! @} */\r
+\r
+/*! @name TXFQS - Tx FIFO/Queue Status */\r
+/*! @{ */\r
+#define CAN_TXFQS_TFGI_MASK (0x1F00U)\r
+#define CAN_TXFQS_TFGI_SHIFT (8U)\r
+/*! TFGI - Tx FIFO get index.\r
+ */\r
+#define CAN_TXFQS_TFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK)\r
+#define CAN_TXFQS_TFQPI_MASK (0x1F0000U)\r
+#define CAN_TXFQS_TFQPI_SHIFT (16U)\r
+/*! TFQPI - Tx FIFO/queue put index.\r
+ */\r
+#define CAN_TXFQS_TFQPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK)\r
+#define CAN_TXFQS_TFQF_MASK (0x200000U)\r
+#define CAN_TXFQS_TFQF_SHIFT (21U)\r
+/*! TFQF - Tx FIFO/queue full.\r
+ */\r
+#define CAN_TXFQS_TFQF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK)\r
+/*! @} */\r
+\r
+/*! @name TXESC - Tx Buffer Element Size Configuration */\r
+/*! @{ */\r
+#define CAN_TXESC_TBDS_MASK (0x7U)\r
+#define CAN_TXESC_TBDS_SHIFT (0U)\r
+/*! TBDS - Tx buffer data field size.\r
+ */\r
+#define CAN_TXESC_TBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK)\r
+/*! @} */\r
+\r
+/*! @name TXBRP - Tx Buffer Request Pending */\r
+/*! @{ */\r
+#define CAN_TXBRP_TRP_MASK (0xFFFFFFFFU)\r
+#define CAN_TXBRP_TRP_SHIFT (0U)\r
+/*! TRP - Transmission request pending.\r
+ */\r
+#define CAN_TXBRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK)\r
+/*! @} */\r
+\r
+/*! @name TXBAR - Tx Buffer Add Request */\r
+/*! @{ */\r
+#define CAN_TXBAR_AR_MASK (0xFFFFFFFFU)\r
+#define CAN_TXBAR_AR_SHIFT (0U)\r
+/*! AR - Add request.\r
+ */\r
+#define CAN_TXBAR_AR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK)\r
+/*! @} */\r
+\r
+/*! @name TXBCR - Tx Buffer Cancellation Request */\r
+/*! @{ */\r
+#define CAN_TXBCR_CR_MASK (0xFFFFFFFFU)\r
+#define CAN_TXBCR_CR_SHIFT (0U)\r
+/*! CR - Cancellation request.\r
+ */\r
+#define CAN_TXBCR_CR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK)\r
+/*! @} */\r
+\r
+/*! @name TXBTO - Tx Buffer Transmission Occurred */\r
+/*! @{ */\r
+#define CAN_TXBTO_TO_MASK (0xFFFFFFFFU)\r
+#define CAN_TXBTO_TO_SHIFT (0U)\r
+/*! TO - Transmission occurred.\r
+ */\r
+#define CAN_TXBTO_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK)\r
+/*! @} */\r
+\r
+/*! @name TXBCF - Tx Buffer Cancellation Finished */\r
+/*! @{ */\r
+#define CAN_TXBCF_TO_MASK (0xFFFFFFFFU)\r
+#define CAN_TXBCF_TO_SHIFT (0U)\r
+/*! TO - Cancellation finished.\r
+ */\r
+#define CAN_TXBCF_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK)\r
+/*! @} */\r
+\r
+/*! @name TXBTIE - Tx Buffer Transmission Interrupt Enable */\r
+/*! @{ */\r
+#define CAN_TXBTIE_TIE_MASK (0xFFFFFFFFU)\r
+#define CAN_TXBTIE_TIE_SHIFT (0U)\r
+/*! TIE - Transmission interrupt enable.\r
+ */\r
+#define CAN_TXBTIE_TIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK)\r
+/*! @} */\r
+\r
+/*! @name TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable */\r
+/*! @{ */\r
+#define CAN_TXBCIE_CFIE_MASK (0xFFFFFFFFU)\r
+#define CAN_TXBCIE_CFIE_SHIFT (0U)\r
+/*! CFIE - Cancellation finished interrupt enable.\r
+ */\r
+#define CAN_TXBCIE_CFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK)\r
+/*! @} */\r
+\r
+/*! @name TXEFC - Tx Event FIFO Configuration */\r
+/*! @{ */\r
+#define CAN_TXEFC_EFSA_MASK (0xFFFCU)\r
+#define CAN_TXEFC_EFSA_SHIFT (2U)\r
+/*! EFSA - Event FIFO start address.\r
+ */\r
+#define CAN_TXEFC_EFSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK)\r
+#define CAN_TXEFC_EFS_MASK (0x3F0000U)\r
+#define CAN_TXEFC_EFS_SHIFT (16U)\r
+/*! EFS - Event FIFO size 0 = Tx event FIFO disabled.\r
+ */\r
+#define CAN_TXEFC_EFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK)\r
+#define CAN_TXEFC_EFWM_MASK (0x3F000000U)\r
+#define CAN_TXEFC_EFWM_SHIFT (24U)\r
+/*! EFWM - Event FIFO watermark 0 = Watermark interrupt disabled.\r
+ */\r
+#define CAN_TXEFC_EFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK)\r
+/*! @} */\r
+\r
+/*! @name TXEFS - Tx Event FIFO Status */\r
+/*! @{ */\r
+#define CAN_TXEFS_EFFL_MASK (0x3FU)\r
+#define CAN_TXEFS_EFFL_SHIFT (0U)\r
+/*! EFFL - Event FIFO fill level.\r
+ */\r
+#define CAN_TXEFS_EFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK)\r
+#define CAN_TXEFS_EFGI_MASK (0x1F00U)\r
+#define CAN_TXEFS_EFGI_SHIFT (8U)\r
+/*! EFGI - Event FIFO get index.\r
+ */\r
+#define CAN_TXEFS_EFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK)\r
+#define CAN_TXEFS_EFPI_MASK (0x3F0000U)\r
+#define CAN_TXEFS_EFPI_SHIFT (16U)\r
+/*! EFPI - Event FIFO put index.\r
+ */\r
+#define CAN_TXEFS_EFPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK)\r
+#define CAN_TXEFS_EFF_MASK (0x1000000U)\r
+#define CAN_TXEFS_EFF_SHIFT (24U)\r
+/*! EFF - Event FIFO full.\r
+ */\r
+#define CAN_TXEFS_EFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK)\r
+#define CAN_TXEFS_TEFL_MASK (0x2000000U)\r
+#define CAN_TXEFS_TEFL_SHIFT (25U)\r
+/*! TEFL - Tx event FIFO element lost.\r
+ */\r
+#define CAN_TXEFS_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK)\r
+/*! @} */\r
+\r
+/*! @name TXEFA - Tx Event FIFO Acknowledge */\r
+/*! @{ */\r
+#define CAN_TXEFA_EFAI_MASK (0x1FU)\r
+#define CAN_TXEFA_EFAI_SHIFT (0U)\r
+/*! EFAI - Event FIFO acknowledge index.\r
+ */\r
+#define CAN_TXEFA_EFAI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK)\r
+/*! @} */\r
+\r
+/*! @name MRBA - CAN Message RAM Base Address */\r
+/*! @{ */\r
+#define CAN_MRBA_BA_MASK (0xFFFF0000U)\r
+#define CAN_MRBA_BA_SHIFT (16U)\r
+/*! BA - Base address for the message RAM in the chip memory map.\r
+ */\r
+#define CAN_MRBA_BA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK)\r
+/*! @} */\r
+\r
+/*! @name ETSCC - External Timestamp Counter Configuration */\r
+/*! @{ */\r
+#define CAN_ETSCC_ETCP_MASK (0x7FFU)\r
+#define CAN_ETSCC_ETCP_SHIFT (0U)\r
+/*! ETCP - External timestamp prescaler value.\r
+ */\r
+#define CAN_ETSCC_ETCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK)\r
+#define CAN_ETSCC_ETCE_MASK (0x80000000U)\r
+#define CAN_ETSCC_ETCE_SHIFT (31U)\r
+/*! ETCE - External timestamp counter enable.\r
+ */\r
+#define CAN_ETSCC_ETCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK)\r
+/*! @} */\r
+\r
+/*! @name ETSCV - External Timestamp Counter Value */\r
+/*! @{ */\r
+#define CAN_ETSCV_ETSC_MASK (0xFFFFU)\r
+#define CAN_ETSCV_ETSC_SHIFT (0U)\r
+/*! ETSC - External timestamp counter.\r
+ */\r
+#define CAN_ETSCV_ETSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group CAN_Register_Masks */\r
+\r
+\r
+/* CAN - Peripheral instance base addresses */\r
+/** Peripheral CAN0 base address */\r
+#define CAN0_BASE (0x4009D000u)\r
+/** Peripheral CAN0 base pointer */\r
+#define CAN0 ((CAN_Type *)CAN0_BASE)\r
+/** Peripheral CAN1 base address */\r
+#define CAN1_BASE (0x4009E000u)\r
+/** Peripheral CAN1 base pointer */\r
+#define CAN1 ((CAN_Type *)CAN1_BASE)\r
+/** Array initializer of CAN peripheral base addresses */\r
+#define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE }\r
+/** Array initializer of CAN peripheral base pointers */\r
+#define CAN_BASE_PTRS { CAN0, CAN1 }\r
+/** Interrupt vectors for the CAN peripheral type */\r
+#define CAN_IRQS { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn }, { CAN1_IRQ0_IRQn, CAN1_IRQ1_IRQn } }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group CAN_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- CRC Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** CRC - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */\r
+ __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */\r
+ union { /* offset: 0x8 */\r
+ __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */\r
+ __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */\r
+ };\r
+} CRC_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- CRC Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup CRC_Register_Masks CRC Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name MODE - CRC mode register */\r
+/*! @{ */\r
+#define CRC_MODE_CRC_POLY_MASK (0x3U)\r
+#define CRC_MODE_CRC_POLY_SHIFT (0U)\r
+/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial\r
+ */\r
+#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)\r
+#define CRC_MODE_BIT_RVS_WR_MASK (0x4U)\r
+#define CRC_MODE_BIT_RVS_WR_SHIFT (2U)\r
+/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)\r
+ */\r
+#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)\r
+#define CRC_MODE_CMPL_WR_MASK (0x8U)\r
+#define CRC_MODE_CMPL_WR_SHIFT (3U)\r
+/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA\r
+ */\r
+#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)\r
+#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U)\r
+#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U)\r
+/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM\r
+ */\r
+#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)\r
+#define CRC_MODE_CMPL_SUM_MASK (0x20U)\r
+#define CRC_MODE_CMPL_SUM_SHIFT (5U)\r
+/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM\r
+ */\r
+#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)\r
+/*! @} */\r
+\r
+/*! @name SEED - CRC seed register */\r
+/*! @{ */\r
+#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU)\r
+#define CRC_SEED_CRC_SEED_SHIFT (0U)\r
+/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with\r
+ * selected bit order and 1's complement pre-processes. A write access to this register will\r
+ * overrule the CRC calculation in progresses.\r
+ */\r
+#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)\r
+/*! @} */\r
+\r
+/*! @name SUM - CRC checksum register */\r
+/*! @{ */\r
+#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU)\r
+#define CRC_SUM_CRC_SUM_SHIFT (0U)\r
+/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.\r
+ */\r
+#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)\r
+/*! @} */\r
+\r
+/*! @name WR_DATA - CRC data register */\r
+/*! @{ */\r
+#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU)\r
+#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U)\r
+/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with\r
+ * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and\r
+ * accept back-to-back transactions.\r
+ */\r
+#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group CRC_Register_Masks */\r
+\r
+\r
+/* CRC - Peripheral instance base addresses */\r
+/** Peripheral CRC_ENGINE base address */\r
+#define CRC_ENGINE_BASE (0x40095000u)\r
+/** Peripheral CRC_ENGINE base pointer */\r
+#define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE)\r
+/** Array initializer of CRC peripheral base addresses */\r
+#define CRC_BASE_ADDRS { CRC_ENGINE_BASE }\r
+/** Array initializer of CRC peripheral base pointers */\r
+#define CRC_BASE_PTRS { CRC_ENGINE }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group CRC_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- CTIMER Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** CTIMER - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */\r
+ __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */\r
+ __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */\r
+ __IO uint32_t PR; /**< Prescale Register, offset: 0xC */\r
+ __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */\r
+ __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */\r
+ __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */\r
+ __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */\r
+ __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */\r
+ __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */\r
+ uint8_t RESERVED_0[48];\r
+ __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */\r
+ __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */\r
+ __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */\r
+} CTIMER_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- CTIMER Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup CTIMER_Register_Masks CTIMER Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */\r
+/*! @{ */\r
+#define CTIMER_IR_MR0INT_MASK (0x1U)\r
+#define CTIMER_IR_MR0INT_SHIFT (0U)\r
+/*! MR0INT - Interrupt flag for match channel 0.\r
+ */\r
+#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)\r
+#define CTIMER_IR_MR1INT_MASK (0x2U)\r
+#define CTIMER_IR_MR1INT_SHIFT (1U)\r
+/*! MR1INT - Interrupt flag for match channel 1.\r
+ */\r
+#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)\r
+#define CTIMER_IR_MR2INT_MASK (0x4U)\r
+#define CTIMER_IR_MR2INT_SHIFT (2U)\r
+/*! MR2INT - Interrupt flag for match channel 2.\r
+ */\r
+#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)\r
+#define CTIMER_IR_MR3INT_MASK (0x8U)\r
+#define CTIMER_IR_MR3INT_SHIFT (3U)\r
+/*! MR3INT - Interrupt flag for match channel 3.\r
+ */\r
+#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)\r
+#define CTIMER_IR_CR0INT_MASK (0x10U)\r
+#define CTIMER_IR_CR0INT_SHIFT (4U)\r
+/*! CR0INT - Interrupt flag for capture channel 0 event.\r
+ */\r
+#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)\r
+#define CTIMER_IR_CR1INT_MASK (0x20U)\r
+#define CTIMER_IR_CR1INT_SHIFT (5U)\r
+/*! CR1INT - Interrupt flag for capture channel 1 event.\r
+ */\r
+#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)\r
+#define CTIMER_IR_CR2INT_MASK (0x40U)\r
+#define CTIMER_IR_CR2INT_SHIFT (6U)\r
+/*! CR2INT - Interrupt flag for capture channel 2 event.\r
+ */\r
+#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)\r
+#define CTIMER_IR_CR3INT_MASK (0x80U)\r
+#define CTIMER_IR_CR3INT_SHIFT (7U)\r
+/*! CR3INT - Interrupt flag for capture channel 3 event.\r
+ */\r
+#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)\r
+/*! @} */\r
+\r
+/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */\r
+/*! @{ */\r
+#define CTIMER_TCR_CEN_MASK (0x1U)\r
+#define CTIMER_TCR_CEN_SHIFT (0U)\r
+/*! CEN - Counter enable.\r
+ * 0b0..Disabled.The counters are disabled.\r
+ * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled.\r
+ */\r
+#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)\r
+#define CTIMER_TCR_CRST_MASK (0x2U)\r
+#define CTIMER_TCR_CRST_SHIFT (1U)\r
+/*! CRST - Counter reset.\r
+ * 0b0..Disabled. Do nothing.\r
+ * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of\r
+ * the APB bus clock. The counters remain reset until TCR[1] is returned to zero.\r
+ */\r
+#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)\r
+/*! @} */\r
+\r
+/*! @name TC - Timer Counter */\r
+/*! @{ */\r
+#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU)\r
+#define CTIMER_TC_TCVAL_SHIFT (0U)\r
+/*! TCVAL - Timer counter value.\r
+ */\r
+#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name PR - Prescale Register */\r
+/*! @{ */\r
+#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU)\r
+#define CTIMER_PR_PRVAL_SHIFT (0U)\r
+/*! PRVAL - Prescale counter value.\r
+ */\r
+#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name PC - Prescale Counter */\r
+/*! @{ */\r
+#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU)\r
+#define CTIMER_PC_PCVAL_SHIFT (0U)\r
+/*! PCVAL - Prescale counter value.\r
+ */\r
+#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name MCR - Match Control Register */\r
+/*! @{ */\r
+#define CTIMER_MCR_MR0I_MASK (0x1U)\r
+#define CTIMER_MCR_MR0I_SHIFT (0U)\r
+/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.\r
+ */\r
+#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)\r
+#define CTIMER_MCR_MR0R_MASK (0x2U)\r
+#define CTIMER_MCR_MR0R_SHIFT (1U)\r
+/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it.\r
+ */\r
+#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)\r
+#define CTIMER_MCR_MR0S_MASK (0x4U)\r
+#define CTIMER_MCR_MR0S_SHIFT (2U)\r
+/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.\r
+ */\r
+#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)\r
+#define CTIMER_MCR_MR1I_MASK (0x8U)\r
+#define CTIMER_MCR_MR1I_SHIFT (3U)\r
+/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.\r
+ */\r
+#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)\r
+#define CTIMER_MCR_MR1R_MASK (0x10U)\r
+#define CTIMER_MCR_MR1R_SHIFT (4U)\r
+/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it.\r
+ */\r
+#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)\r
+#define CTIMER_MCR_MR1S_MASK (0x20U)\r
+#define CTIMER_MCR_MR1S_SHIFT (5U)\r
+/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.\r
+ */\r
+#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)\r
+#define CTIMER_MCR_MR2I_MASK (0x40U)\r
+#define CTIMER_MCR_MR2I_SHIFT (6U)\r
+/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.\r
+ */\r
+#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)\r
+#define CTIMER_MCR_MR2R_MASK (0x80U)\r
+#define CTIMER_MCR_MR2R_SHIFT (7U)\r
+/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it.\r
+ */\r
+#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)\r
+#define CTIMER_MCR_MR2S_MASK (0x100U)\r
+#define CTIMER_MCR_MR2S_SHIFT (8U)\r
+/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.\r
+ */\r
+#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)\r
+#define CTIMER_MCR_MR3I_MASK (0x200U)\r
+#define CTIMER_MCR_MR3I_SHIFT (9U)\r
+/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.\r
+ */\r
+#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)\r
+#define CTIMER_MCR_MR3R_MASK (0x400U)\r
+#define CTIMER_MCR_MR3R_SHIFT (10U)\r
+/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it.\r
+ */\r
+#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)\r
+#define CTIMER_MCR_MR3S_MASK (0x800U)\r
+#define CTIMER_MCR_MR3S_SHIFT (11U)\r
+/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.\r
+ */\r
+#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)\r
+#define CTIMER_MCR_MR0RL_MASK (0x1000000U)\r
+#define CTIMER_MCR_MR0RL_SHIFT (24U)\r
+/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero\r
+ * (either via a match event or a write to bit 1 of the TCR).\r
+ */\r
+#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)\r
+#define CTIMER_MCR_MR1RL_MASK (0x2000000U)\r
+#define CTIMER_MCR_MR1RL_SHIFT (25U)\r
+/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero\r
+ * (either via a match event or a write to bit 1 of the TCR).\r
+ */\r
+#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)\r
+#define CTIMER_MCR_MR2RL_MASK (0x4000000U)\r
+#define CTIMER_MCR_MR2RL_SHIFT (26U)\r
+/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero\r
+ * (either via a match event or a write to bit 1 of the TCR).\r
+ */\r
+#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)\r
+#define CTIMER_MCR_MR3RL_MASK (0x8000000U)\r
+#define CTIMER_MCR_MR3RL_SHIFT (27U)\r
+/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero\r
+ * (either via a match event or a write to bit 1 of the TCR).\r
+ */\r
+#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)\r
+/*! @} */\r
+\r
+/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */\r
+/*! @{ */\r
+#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU)\r
+#define CTIMER_MR_MATCH_SHIFT (0U)\r
+/*! MATCH - Timer counter match value.\r
+ */\r
+#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)\r
+/*! @} */\r
+\r
+/* The count of CTIMER_MR */\r
+#define CTIMER_MR_COUNT (4U)\r
+\r
+/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */\r
+/*! @{ */\r
+#define CTIMER_CCR_CAP0RE_MASK (0x1U)\r
+#define CTIMER_CCR_CAP0RE_SHIFT (0U)\r
+/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with\r
+ * the contents of TC. 0 = disabled. 1 = enabled.\r
+ */\r
+#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)\r
+#define CTIMER_CCR_CAP0FE_MASK (0x2U)\r
+#define CTIMER_CCR_CAP0FE_SHIFT (1U)\r
+/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with\r
+ * the contents of TC. 0 = disabled. 1 = enabled.\r
+ */\r
+#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)\r
+#define CTIMER_CCR_CAP0I_MASK (0x4U)\r
+#define CTIMER_CCR_CAP0I_SHIFT (2U)\r
+/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.\r
+ */\r
+#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)\r
+#define CTIMER_CCR_CAP1RE_MASK (0x8U)\r
+#define CTIMER_CCR_CAP1RE_SHIFT (3U)\r
+/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with\r
+ * the contents of TC. 0 = disabled. 1 = enabled.\r
+ */\r
+#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)\r
+#define CTIMER_CCR_CAP1FE_MASK (0x10U)\r
+#define CTIMER_CCR_CAP1FE_SHIFT (4U)\r
+/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with\r
+ * the contents of TC. 0 = disabled. 1 = enabled.\r
+ */\r
+#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)\r
+#define CTIMER_CCR_CAP1I_MASK (0x20U)\r
+#define CTIMER_CCR_CAP1I_SHIFT (5U)\r
+/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.\r
+ */\r
+#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)\r
+#define CTIMER_CCR_CAP2RE_MASK (0x40U)\r
+#define CTIMER_CCR_CAP2RE_SHIFT (6U)\r
+/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with\r
+ * the contents of TC. 0 = disabled. 1 = enabled.\r
+ */\r
+#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)\r
+#define CTIMER_CCR_CAP2FE_MASK (0x80U)\r
+#define CTIMER_CCR_CAP2FE_SHIFT (7U)\r
+/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with\r
+ * the contents of TC. 0 = disabled. 1 = enabled.\r
+ */\r
+#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)\r
+#define CTIMER_CCR_CAP2I_MASK (0x100U)\r
+#define CTIMER_CCR_CAP2I_SHIFT (8U)\r
+/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.\r
+ */\r
+#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)\r
+#define CTIMER_CCR_CAP3RE_MASK (0x200U)\r
+#define CTIMER_CCR_CAP3RE_SHIFT (9U)\r
+/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with\r
+ * the contents of TC. 0 = disabled. 1 = enabled.\r
+ */\r
+#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)\r
+#define CTIMER_CCR_CAP3FE_MASK (0x400U)\r
+#define CTIMER_CCR_CAP3FE_SHIFT (10U)\r
+/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with\r
+ * the contents of TC. 0 = disabled. 1 = enabled.\r
+ */\r
+#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)\r
+#define CTIMER_CCR_CAP3I_MASK (0x800U)\r
+#define CTIMER_CCR_CAP3I_SHIFT (11U)\r
+/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.\r
+ */\r
+#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)\r
+/*! @} */\r
+\r
+/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */\r
+/*! @{ */\r
+#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU)\r
+#define CTIMER_CR_CAP_SHIFT (0U)\r
+/*! CAP - Timer counter capture value.\r
+ */\r
+#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)\r
+/*! @} */\r
+\r
+/* The count of CTIMER_CR */\r
+#define CTIMER_CR_COUNT (4U)\r
+\r
+/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */\r
+/*! @{ */\r
+#define CTIMER_EMR_EM0_MASK (0x1U)\r
+#define CTIMER_EMR_EM0_SHIFT (0U)\r
+/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output\r
+ * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle,\r
+ * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if\r
+ * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.\r
+ */\r
+#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)\r
+#define CTIMER_EMR_EM1_MASK (0x2U)\r
+#define CTIMER_EMR_EM1_SHIFT (1U)\r
+/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output\r
+ * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle,\r
+ * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if\r
+ * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.\r
+ */\r
+#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)\r
+#define CTIMER_EMR_EM2_MASK (0x4U)\r
+#define CTIMER_EMR_EM2_SHIFT (2U)\r
+/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output\r
+ * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle,\r
+ * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if\r
+ * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.\r
+ */\r
+#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)\r
+#define CTIMER_EMR_EM3_MASK (0x8U)\r
+#define CTIMER_EMR_EM3_SHIFT (3U)\r
+/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output\r
+ * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle,\r
+ * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins\r
+ * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.\r
+ */\r
+#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)\r
+#define CTIMER_EMR_EMC0_MASK (0x30U)\r
+#define CTIMER_EMR_EMC0_SHIFT (4U)\r
+/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0.\r
+ * 0b00..Do Nothing.\r
+ * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).\r
+ * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).\r
+ * 0b11..Toggle. Toggle the corresponding External Match bit/output.\r
+ */\r
+#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)\r
+#define CTIMER_EMR_EMC1_MASK (0xC0U)\r
+#define CTIMER_EMR_EMC1_SHIFT (6U)\r
+/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1.\r
+ * 0b00..Do Nothing.\r
+ * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).\r
+ * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).\r
+ * 0b11..Toggle. Toggle the corresponding External Match bit/output.\r
+ */\r
+#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)\r
+#define CTIMER_EMR_EMC2_MASK (0x300U)\r
+#define CTIMER_EMR_EMC2_SHIFT (8U)\r
+/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2.\r
+ * 0b00..Do Nothing.\r
+ * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).\r
+ * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).\r
+ * 0b11..Toggle. Toggle the corresponding External Match bit/output.\r
+ */\r
+#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)\r
+#define CTIMER_EMR_EMC3_MASK (0xC00U)\r
+#define CTIMER_EMR_EMC3_SHIFT (10U)\r
+/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3.\r
+ * 0b00..Do Nothing.\r
+ * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).\r
+ * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).\r
+ * 0b11..Toggle. Toggle the corresponding External Match bit/output.\r
+ */\r
+#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)\r
+/*! @} */\r
+\r
+/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */\r
+/*! @{ */\r
+#define CTIMER_CTCR_CTMODE_MASK (0x3U)\r
+#define CTIMER_CTCR_CTMODE_SHIFT (0U)\r
+/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment\r
+ * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC\r
+ * is incremented when the Prescale Counter matches the Prescale Register.\r
+ * 0b00..Timer Mode. Incremented every rising APB bus clock edge.\r
+ * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.\r
+ * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.\r
+ * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.\r
+ */\r
+#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)\r
+#define CTIMER_CTCR_CINSEL_MASK (0xCU)\r
+#define CTIMER_CTCR_CINSEL_SHIFT (2U)\r
+/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which\r
+ * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input\r
+ * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be\r
+ * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the\r
+ * same timer.\r
+ * 0b00..Channel 0. CAPn.0 for CTIMERn\r
+ * 0b01..Channel 1. CAPn.1 for CTIMERn\r
+ * 0b10..Channel 2. CAPn.2 for CTIMERn\r
+ * 0b11..Channel 3. CAPn.3 for CTIMERn\r
+ */\r
+#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)\r
+#define CTIMER_CTCR_ENCC_MASK (0x10U)\r
+#define CTIMER_CTCR_ENCC_SHIFT (4U)\r
+/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the\r
+ * capture-edge event specified in bits 7:5 occurs.\r
+ */\r
+#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)\r
+#define CTIMER_CTCR_SELCC_MASK (0xE0U)\r
+#define CTIMER_CTCR_SELCC_SHIFT (5U)\r
+/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the\r
+ * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to\r
+ * 0x3 and 0x6 to 0x7 are reserved.\r
+ * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).\r
+ * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).\r
+ * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).\r
+ * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).\r
+ * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).\r
+ * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).\r
+ */\r
+#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)\r
+/*! @} */\r
+\r
+/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */\r
+/*! @{ */\r
+#define CTIMER_PWMC_PWMEN0_MASK (0x1U)\r
+#define CTIMER_PWMC_PWMEN0_SHIFT (0U)\r
+/*! PWMEN0 - PWM mode enable for channel0.\r
+ * 0b0..Match. CTIMERn_MAT0 is controlled by EM0.\r
+ * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0.\r
+ */\r
+#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)\r
+#define CTIMER_PWMC_PWMEN1_MASK (0x2U)\r
+#define CTIMER_PWMC_PWMEN1_SHIFT (1U)\r
+/*! PWMEN1 - PWM mode enable for channel1.\r
+ * 0b0..Match. CTIMERn_MAT01 is controlled by EM1.\r
+ * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1.\r
+ */\r
+#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)\r
+#define CTIMER_PWMC_PWMEN2_MASK (0x4U)\r
+#define CTIMER_PWMC_PWMEN2_SHIFT (2U)\r
+/*! PWMEN2 - PWM mode enable for channel2.\r
+ * 0b0..Match. CTIMERn_MAT2 is controlled by EM2.\r
+ * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2.\r
+ */\r
+#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)\r
+#define CTIMER_PWMC_PWMEN3_MASK (0x8U)\r
+#define CTIMER_PWMC_PWMEN3_SHIFT (3U)\r
+/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.\r
+ * 0b0..Match. CTIMERn_MAT3 is controlled by EM3.\r
+ * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3.\r
+ */\r
+#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)\r
+/*! @} */\r
+\r
+/*! @name MSR - Match Shadow Register */\r
+/*! @{ */\r
+#define CTIMER_MSR_SHADOWW_MASK (0xFFFFFFFFU)\r
+#define CTIMER_MSR_SHADOWW_SHIFT (0U)\r
+/*! SHADOWW - Timer counter match shadow value.\r
+ */\r
+#define CTIMER_MSR_SHADOWW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK)\r
+/*! @} */\r
+\r
+/* The count of CTIMER_MSR */\r
+#define CTIMER_MSR_COUNT (4U)\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group CTIMER_Register_Masks */\r
+\r
+\r
+/* CTIMER - Peripheral instance base addresses */\r
+/** Peripheral CTIMER0 base address */\r
+#define CTIMER0_BASE (0x40008000u)\r
+/** Peripheral CTIMER0 base pointer */\r
+#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE)\r
+/** Peripheral CTIMER1 base address */\r
+#define CTIMER1_BASE (0x40009000u)\r
+/** Peripheral CTIMER1 base pointer */\r
+#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE)\r
+/** Peripheral CTIMER2 base address */\r
+#define CTIMER2_BASE (0x40028000u)\r
+/** Peripheral CTIMER2 base pointer */\r
+#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE)\r
+/** Peripheral CTIMER3 base address */\r
+#define CTIMER3_BASE (0x40048000u)\r
+/** Peripheral CTIMER3 base pointer */\r
+#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE)\r
+/** Peripheral CTIMER4 base address */\r
+#define CTIMER4_BASE (0x40049000u)\r
+/** Peripheral CTIMER4 base pointer */\r
+#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE)\r
+/** Array initializer of CTIMER peripheral base addresses */\r
+#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }\r
+/** Array initializer of CTIMER peripheral base pointers */\r
+#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }\r
+/** Interrupt vectors for the CTIMER peripheral type */\r
+#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group CTIMER_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- DMA Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** DMA - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */\r
+ __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */\r
+ __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */\r
+ uint8_t RESERVED_0[20];\r
+ struct { /* offset: 0x20, array step: 0x5C */\r
+ __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */\r
+ uint8_t RESERVED_0[4];\r
+ __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */\r
+ uint8_t RESERVED_1[4];\r
+ __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */\r
+ uint8_t RESERVED_2[4];\r
+ __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */\r
+ uint8_t RESERVED_3[4];\r
+ __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */\r
+ uint8_t RESERVED_4[4];\r
+ __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */\r
+ uint8_t RESERVED_5[4];\r
+ __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */\r
+ uint8_t RESERVED_6[4];\r
+ __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */\r
+ uint8_t RESERVED_7[4];\r
+ __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */\r
+ uint8_t RESERVED_8[4];\r
+ __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */\r
+ uint8_t RESERVED_9[4];\r
+ __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */\r
+ uint8_t RESERVED_10[4];\r
+ __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */\r
+ } COMMON[1];\r
+ uint8_t RESERVED_1[900];\r
+ struct { /* offset: 0x400, array step: 0x10 */\r
+ __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */\r
+ __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */\r
+ __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */\r
+ uint8_t RESERVED_0[4];\r
+ } CHANNEL[32];\r
+} DMA_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- DMA Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup DMA_Register_Masks DMA Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CTRL - DMA control. */\r
+/*! @{ */\r
+#define DMA_CTRL_ENABLE_MASK (0x1U)\r
+#define DMA_CTRL_ENABLE_SHIFT (0U)\r
+/*! ENABLE - DMA controller master enable.\r
+ * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when\r
+ * disabled, but does not prevent re-triggering when the DMA controller is re-enabled.\r
+ * 0b1..Enabled. The DMA controller is enabled.\r
+ */\r
+#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTSTAT - Interrupt status. */\r
+/*! @{ */\r
+#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U)\r
+#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U)\r
+/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending.\r
+ * 0b0..Not pending. No enabled interrupts are pending.\r
+ * 0b1..Pending. At least one enabled interrupt is pending.\r
+ */\r
+#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)\r
+#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U)\r
+#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U)\r
+/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending.\r
+ * 0b0..Not pending. No error interrupts are pending.\r
+ * 0b1..Pending. At least one error interrupt is pending.\r
+ */\r
+#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)\r
+/*! @} */\r
+\r
+/*! @name SRAMBASE - SRAM address of the channel configuration table. */\r
+/*! @{ */\r
+#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U)\r
+#define DMA_SRAMBASE_OFFSET_SHIFT (9U)\r
+/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the\r
+ * table must begin on a 512 byte boundary.\r
+ */\r
+#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)\r
+/*! @} */\r
+\r
+/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */\r
+/*! @{ */\r
+#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU)\r
+#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U)\r
+/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits =\r
+ * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled.\r
+ */\r
+#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_COMMON_ENABLESET */\r
+#define DMA_COMMON_ENABLESET_COUNT (1U)\r
+\r
+/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */\r
+/*! @{ */\r
+#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU)\r
+#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U)\r
+/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears\r
+ * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits\r
+ * are reserved.\r
+ */\r
+#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_COMMON_ENABLECLR */\r
+#define DMA_COMMON_ENABLECLR_COUNT (1U)\r
+\r
+/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */\r
+/*! @{ */\r
+#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU)\r
+#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U)\r
+/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =\r
+ * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active.\r
+ */\r
+#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_COMMON_ACTIVE */\r
+#define DMA_COMMON_ACTIVE_COUNT (1U)\r
+\r
+/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */\r
+/*! @{ */\r
+#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU)\r
+#define DMA_COMMON_BUSY_BSY_SHIFT (0U)\r
+/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =\r
+ * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy.\r
+ */\r
+#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_COMMON_BUSY */\r
+#define DMA_COMMON_BUSY_COUNT (1U)\r
+\r
+/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */\r
+/*! @{ */\r
+#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU)\r
+#define DMA_COMMON_ERRINT_ERR_SHIFT (0U)\r
+/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of\r
+ * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is\r
+ * not active. 1 = error interrupt is active.\r
+ */\r
+#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_COMMON_ERRINT */\r
+#define DMA_COMMON_ERRINT_COUNT (1U)\r
+\r
+/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */\r
+/*! @{ */\r
+#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU)\r
+#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U)\r
+/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The\r
+ * number of bits = number of DMA channels in this device. Other bits are reserved. 0 =\r
+ * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled.\r
+ */\r
+#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_COMMON_INTENSET */\r
+#define DMA_COMMON_INTENSET_COUNT (1U)\r
+\r
+/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */\r
+/*! @{ */\r
+#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU)\r
+#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U)\r
+/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n\r
+ * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are\r
+ * reserved.\r
+ */\r
+#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_COMMON_INTENCLR */\r
+#define DMA_COMMON_INTENCLR_COUNT (1U)\r
+\r
+/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */\r
+/*! @{ */\r
+#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU)\r
+#define DMA_COMMON_INTA_IA_SHIFT (0U)\r
+/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of\r
+ * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel\r
+ * interrupt A is not active. 1 = the DMA channel interrupt A is active.\r
+ */\r
+#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_COMMON_INTA */\r
+#define DMA_COMMON_INTA_COUNT (1U)\r
+\r
+/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */\r
+/*! @{ */\r
+#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU)\r
+#define DMA_COMMON_INTB_IB_SHIFT (0U)\r
+/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of\r
+ * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel\r
+ * interrupt B is not active. 1 = the DMA channel interrupt B is active.\r
+ */\r
+#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_COMMON_INTB */\r
+#define DMA_COMMON_INTB_COUNT (1U)\r
+\r
+/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */\r
+/*! @{ */\r
+#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU)\r
+#define DMA_COMMON_SETVALID_SV_SHIFT (0U)\r
+/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits\r
+ * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the\r
+ * VALIDPENDING control bit for DMA channel n\r
+ */\r
+#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_COMMON_SETVALID */\r
+#define DMA_COMMON_SETVALID_COUNT (1U)\r
+\r
+/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */\r
+/*! @{ */\r
+#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU)\r
+#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U)\r
+/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number\r
+ * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 =\r
+ * sets the TRIG bit for DMA channel n.\r
+ */\r
+#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_COMMON_SETTRIG */\r
+#define DMA_COMMON_SETTRIG_COUNT (1U)\r
+\r
+/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */\r
+/*! @{ */\r
+#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU)\r
+#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U)\r
+/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect.\r
+ * 1 = aborts DMA operations on channel n.\r
+ */\r
+#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_COMMON_ABORT */\r
+#define DMA_COMMON_ABORT_COUNT (1U)\r
+\r
+/*! @name CHANNEL_CFG - Configuration register for DMA channel . */\r
+/*! @{ */\r
+#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U)\r
+#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U)\r
+/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory\r
+ * move, any peripheral DMA request associated with that channel can be disabled to prevent any\r
+ * interaction between the peripheral and the DMA controller.\r
+ * 0b0..Disabled. Peripheral DMA requests are disabled.\r
+ * 0b1..Enabled. Peripheral DMA requests are enabled.\r
+ */\r
+#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)\r
+#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U)\r
+#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U)\r
+/*! HWTRIGEN - Hardware Triggering Enable for this channel.\r
+ * 0b0..Disabled. Hardware triggering is not used.\r
+ * 0b1..Enabled. Use hardware triggering.\r
+ */\r
+#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)\r
+#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U)\r
+#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U)\r
+/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel.\r
+ * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.\r
+ * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.\r
+ */\r
+#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)\r
+#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U)\r
+#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U)\r
+/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered.\r
+ * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.\r
+ * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER =\r
+ * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the\r
+ * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger\r
+ * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the\r
+ * current BURSTPOWER length are completed.\r
+ */\r
+#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)\r
+#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U)\r
+#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U)\r
+/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.\r
+ * 0b0..Single transfer. Hardware trigger causes a single transfer.\r
+ * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a\r
+ * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a\r
+ * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is\r
+ * complete.\r
+ */\r
+#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)\r
+#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U)\r
+#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U)\r
+/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when\r
+ * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register).\r
+ * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many\r
+ * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that\r
+ * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000:\r
+ * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size =\r
+ * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The\r
+ * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even\r
+ * multiple of the burst size.\r
+ */\r
+#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)\r
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U)\r
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U)\r
+/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is\r
+ * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this\r
+ * could be used to read several sequential registers from a peripheral for each DMA burst,\r
+ * reading the same registers again for each burst.\r
+ * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel.\r
+ * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel.\r
+ */\r
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)\r
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U)\r
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U)\r
+/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is\r
+ * 'wrapped', meaning that the destination address range for each burst will be the same. As an\r
+ * example, this could be used to write several sequential registers to a peripheral for each DMA\r
+ * burst, writing the same registers again for each burst.\r
+ * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel.\r
+ * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel.\r
+ */\r
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)\r
+#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U)\r
+#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U)\r
+/*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority\r
+ * levels are supported: 0x0 = highest priority. 0x7 = lowest priority.\r
+ */\r
+#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_CHANNEL_CFG */\r
+#define DMA_CHANNEL_CFG_COUNT (32U)\r
+\r
+/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */\r
+/*! @{ */\r
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U)\r
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U)\r
+/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the\r
+ * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.\r
+ * 0b0..No effect. No effect on DMA operation.\r
+ * 0b1..Valid pending.\r
+ */\r
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)\r
+#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U)\r
+#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U)\r
+/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is\r
+ * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.\r
+ * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.\r
+ * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.\r
+ */\r
+#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_CHANNEL_CTLSTAT */\r
+#define DMA_CHANNEL_CTLSTAT_COUNT (32U)\r
+\r
+/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */\r
+/*! @{ */\r
+#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U)\r
+#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U)\r
+/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor\r
+ * is valid and can potentially be acted upon, if all other activation criteria are fulfilled.\r
+ * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.\r
+ * 0b1..Valid. The current channel descriptor is considered valid.\r
+ */\r
+#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)\r
+#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U)\r
+#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U)\r
+/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current\r
+ * descriptor is exhausted. Reloading allows ping-pong and linked transfers.\r
+ * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.\r
+ * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted.\r
+ */\r
+#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)\r
+#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U)\r
+#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U)\r
+/*! SWTRIG - Software Trigger.\r
+ * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by\r
+ * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.\r
+ * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not\r
+ * be used with level triggering when TRIGBURST = 0.\r
+ */\r
+#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)\r
+#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U)\r
+#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U)\r
+/*! CLRTRIG - Clear Trigger.\r
+ * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.\r
+ * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted\r
+ */\r
+#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)\r
+#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U)\r
+#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U)\r
+/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between\r
+ * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By\r
+ * convention, interrupt A may be used when only one interrupt flag is needed.\r
+ * 0b0..No effect.\r
+ * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted.\r
+ */\r
+#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)\r
+#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U)\r
+#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U)\r
+/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between\r
+ * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By\r
+ * convention, interrupt A may be used when only one interrupt flag is needed.\r
+ * 0b0..No effect.\r
+ * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted.\r
+ */\r
+#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)\r
+#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U)\r
+#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U)\r
+/*! WIDTH - Transfer width used for this DMA channel.\r
+ * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).\r
+ * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).\r
+ * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).\r
+ * 0b11..Reserved. Reserved setting, do not use.\r
+ */\r
+#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)\r
+#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U)\r
+#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U)\r
+/*! SRCINC - Determines whether the source address is incremented for each DMA transfer.\r
+ * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.\r
+ * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is\r
+ * the usual case when the source is memory.\r
+ * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.\r
+ * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.\r
+ */\r
+#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)\r
+#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U)\r
+#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U)\r
+/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer.\r
+ * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when\r
+ * the destination is a peripheral device.\r
+ * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer.\r
+ * This is the usual case when the destination is memory.\r
+ * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.\r
+ * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.\r
+ */\r
+#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)\r
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U)\r
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U)\r
+/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes\r
+ * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller\r
+ * uses this bit field during transfer to count down. Hence, it cannot be used by software to read\r
+ * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1\r
+ * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of\r
+ * 1,024 transfers will be performed.\r
+ */\r
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_CHANNEL_XFERCFG */\r
+#define DMA_CHANNEL_XFERCFG_COUNT (32U)\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group DMA_Register_Masks */\r
+\r
+\r
+/* DMA - Peripheral instance base addresses */\r
+/** Peripheral DMA0 base address */\r
+#define DMA0_BASE (0x40082000u)\r
+/** Peripheral DMA0 base pointer */\r
+#define DMA0 ((DMA_Type *)DMA0_BASE)\r
+/** Array initializer of DMA peripheral base addresses */\r
+#define DMA_BASE_ADDRS { DMA0_BASE }\r
+/** Array initializer of DMA peripheral base pointers */\r
+#define DMA_BASE_PTRS { DMA0 }\r
+/** Interrupt vectors for the DMA peripheral type */\r
+#define DMA_IRQS { DMA0_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group DMA_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- DMIC Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** DMIC - Register Layout Typedef */\r
+typedef struct {\r
+ struct { /* offset: 0x0, array step: 0x100 */\r
+ __IO uint32_t OSR; /**< Oversample Rate register 0, array offset: 0x0, array step: 0x100 */\r
+ __IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, array step: 0x100 */\r
+ __IO uint32_t PREAC2FSCOEF; /**< Pre-Emphasis Filter Coefficient for 2 FS register, array offset: 0x8, array step: 0x100 */\r
+ __IO uint32_t PREAC4FSCOEF; /**< Pre-Emphasis Filter Coefficient for 4 FS register, array offset: 0xC, array step: 0x100 */\r
+ __IO uint32_t GAINSHIFT; /**< Decimator Gain Shift register, array offset: 0x10, array step: 0x100 */\r
+ uint8_t RESERVED_0[108];\r
+ __IO uint32_t FIFO_CTRL; /**< FIFO Control register 0, array offset: 0x80, array step: 0x100 */\r
+ __IO uint32_t FIFO_STATUS; /**< FIFO Status register 0, array offset: 0x84, array step: 0x100 */\r
+ __IO uint32_t FIFO_DATA; /**< FIFO Data Register 0, array offset: 0x88, array step: 0x100 */\r
+ __IO uint32_t PHY_CTRL; /**< PDM Source Configuration register 0, array offset: 0x8C, array step: 0x100 */\r
+ __IO uint32_t DC_CTRL; /**< DC Control register 0, array offset: 0x90, array step: 0x100 */\r
+ uint8_t RESERVED_1[108];\r
+ } CHANNEL[2];\r
+ uint8_t RESERVED_0[3328];\r
+ __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */\r
+ uint8_t RESERVED_1[8];\r
+ __IO uint32_t IOCFG; /**< I/O Configuration register, offset: 0xF0C */\r
+ __IO uint32_t USE2FS; /**< Use 2FS register, offset: 0xF10 */\r
+ uint8_t RESERVED_2[108];\r
+ __IO uint32_t HWVADGAIN; /**< HWVAD input gain register, offset: 0xF80 */\r
+ __IO uint32_t HWVADHPFS; /**< HWVAD filter control register, offset: 0xF84 */\r
+ __IO uint32_t HWVADST10; /**< HWVAD control register, offset: 0xF88 */\r
+ __IO uint32_t HWVADRSTT; /**< HWVAD filter reset register, offset: 0xF8C */\r
+ __IO uint32_t HWVADTHGN; /**< HWVAD noise estimator gain register, offset: 0xF90 */\r
+ __IO uint32_t HWVADTHGS; /**< HWVAD signal estimator gain register, offset: 0xF94 */\r
+ __I uint32_t HWVADLOWZ; /**< HWVAD noise envelope estimator register, offset: 0xF98 */\r
+ uint8_t RESERVED_3[96];\r
+ __I uint32_t ID; /**< Module Identification register, offset: 0xFFC */\r
+} DMIC_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- DMIC Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup DMIC_Register_Masks DMIC Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CHANNEL_OSR - Oversample Rate register 0 */\r
+/*! @{ */\r
+#define DMIC_CHANNEL_OSR_OSR_MASK (0xFFU)\r
+#define DMIC_CHANNEL_OSR_OSR_SHIFT (0U)\r
+/*! OSR - Selects the oversample rate for the related input channel.\r
+ */\r
+#define DMIC_CHANNEL_OSR_OSR(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMIC_CHANNEL_OSR */\r
+#define DMIC_CHANNEL_OSR_COUNT (2U)\r
+\r
+/*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */\r
+/*! @{ */\r
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK (0xFU)\r
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT (0U)\r
+/*! PDMDIV - PDM clock divider value. 0 = divide by 1 1 = divide by 2 2 = divide by 3 3 = divide by\r
+ * 4 4 = divide by 6 5 = divide by 8 6 = divide by 12 7 = divide by 16 8 = divide by 24 9 =\r
+ * divide by 32 10 = divide by 48 11 = divide by 64 12 = divide by 96 13 = divide by 128 others =\r
+ * reserved.\r
+ */\r
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMIC_CHANNEL_DIVHFCLK */\r
+#define DMIC_CHANNEL_DIVHFCLK_COUNT (2U)\r
+\r
+/*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */\r
+/*! @{ */\r
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK (0x3U)\r
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT (0U)\r
+/*! COMP - Pre-emphasis filer coefficient for 2 FS mode. 0 = Compensation = 0 1 = Compensation = 16\r
+ * 2 = Compensation = 15 3 = Compensation = 13\r
+ */\r
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMIC_CHANNEL_PREAC2FSCOEF */\r
+#define DMIC_CHANNEL_PREAC2FSCOEF_COUNT (2U)\r
+\r
+/*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */\r
+/*! @{ */\r
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK (0x3U)\r
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT (0U)\r
+/*! COMP - Pre-emphasis filer coefficient for 4 FS mode. 0 = Compensation = 0 1 = Compensation = 16\r
+ * 2 = Compensation = 15 3 = Compensation = 13\r
+ */\r
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMIC_CHANNEL_PREAC4FSCOEF */\r
+#define DMIC_CHANNEL_PREAC4FSCOEF_COUNT (2U)\r
+\r
+/*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */\r
+/*! @{ */\r
+#define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK (0x3FU)\r
+#define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT (0U)\r
+/*! GAIN - Gain control, as a positive or negative (two's complement) number of bits to shift.\r
+ */\r
+#define DMIC_CHANNEL_GAINSHIFT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMIC_CHANNEL_GAINSHIFT */\r
+#define DMIC_CHANNEL_GAINSHIFT_COUNT (2U)\r
+\r
+/*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */\r
+/*! @{ */\r
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK (0x1U)\r
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT (0U)\r
+/*! ENABLE - FIFO enable.\r
+ * 0b0..FIFO is not enabled. Enabling a DMIC channel with the FIFO disabled could be useful while data is being\r
+ * streamed to the I2S, or in order to avoid a filter settling delay when a channel is re-enabled after a\r
+ * period when the data was not needed.\r
+ * 0b1..FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register.\r
+ */\r
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK)\r
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK (0x2U)\r
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT (1U)\r
+/*! RESETN - FIFO reset.\r
+ * 0b0..Reset the FIFO.\r
+ * 0b1..Normal operation\r
+ */\r
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK)\r
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK (0x4U)\r
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT (2U)\r
+/*! INTEN - Interrupt enable.\r
+ * 0b0..FIFO level interrupts are not enabled.\r
+ * 0b1..FIFO level interrupts are enabled.\r
+ */\r
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK)\r
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK (0x8U)\r
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT (3U)\r
+/*! DMAEN - DMA enable\r
+ * 0b0..DMA requests are not enabled.\r
+ * 0b1..DMA requests based on FIFO level are enabled.\r
+ */\r
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)\r
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK (0x1F0000U)\r
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT (16U)\r
+/*! TRIGLVL - FIFO trigger level. Selects the data trigger level for interrupt or DMA operation. If\r
+ * enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then\r
+ * return to the reduced power mode See Section 4.5.66 'Hardware Wake-up control register'. 0 =\r
+ * trigger when the FIFO has received one entry (is no longer empty). 1 = trigger when the FIFO has\r
+ * received two entries. 15 = trigger when the FIFO has received 16 entries (has become full).\r
+ */\r
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMIC_CHANNEL_FIFO_CTRL */\r
+#define DMIC_CHANNEL_FIFO_CTRL_COUNT (2U)\r
+\r
+/*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */\r
+/*! @{ */\r
+#define DMIC_CHANNEL_FIFO_STATUS_INT_MASK (0x1U)\r
+#define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT (0U)\r
+/*! INT - Interrupt flag. Asserted when FIFO data reaches the level specified in the FIFOCTRL\r
+ * register. Writing a one to this bit clears the flag. Remark: note that the bus clock to the DMIC\r
+ * subsystem must be running in order for an interrupt to occur.\r
+ */\r
+#define DMIC_CHANNEL_FIFO_STATUS_INT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK)\r
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK (0x2U)\r
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT (1U)\r
+/*! OVERRUN - Overrun flag. Indicates that a FIFO overflow has occurred at some point. Writing a one\r
+ * to this bit clears the flag. This flag does not cause an interrupt.\r
+ */\r
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK)\r
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK (0x4U)\r
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT (2U)\r
+/*! UNDERRUN - Underrun flag. Indicates that a FIFO underflow has occurred at some point. Writing a one to this bit clears the flag.\r
+ */\r
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMIC_CHANNEL_FIFO_STATUS */\r
+#define DMIC_CHANNEL_FIFO_STATUS_COUNT (2U)\r
+\r
+/*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */\r
+/*! @{ */\r
+#define DMIC_CHANNEL_FIFO_DATA_DATA_MASK (0xFFFFFFU)\r
+#define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT (0U)\r
+/*! DATA - Data from the top of the input filter FIFO.\r
+ */\r
+#define DMIC_CHANNEL_FIFO_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMIC_CHANNEL_FIFO_DATA */\r
+#define DMIC_CHANNEL_FIFO_DATA_COUNT (2U)\r
+\r
+/*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */\r
+/*! @{ */\r
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK (0x1U)\r
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT (0U)\r
+/*! PHY_FALL - Capture PDM_DATA\r
+ * 0b0..Capture PDM_DATA on the rising edge of PDM_CLK.\r
+ * 0b1..Capture PDM_DATA on the falling edge of PDM_CLK.\r
+ */\r
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK)\r
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK (0x2U)\r
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT (1U)\r
+/*! PHY_HALF - Half rate sampling\r
+ * 0b0..Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing.\r
+ * 0b1..Use half rate sampling. The clock to the DMIC is sent at half the rate as the decimator is providing.\r
+ */\r
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMIC_CHANNEL_PHY_CTRL */\r
+#define DMIC_CHANNEL_PHY_CTRL_COUNT (2U)\r
+\r
+/*! @name CHANNEL_DC_CTRL - DC Control register 0 */\r
+/*! @{ */\r
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK (0x3U)\r
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT (0U)\r
+/*! DCPOLE - DC block filter\r
+ * 0b00..Flat response, no filter.\r
+ * 0b01..155 Hz.\r
+ * 0b10..78 Hz.\r
+ * 0b11..39 Hz\r
+ */\r
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK)\r
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK (0xF0U)\r
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT (4U)\r
+/*! DCGAIN - Fine gain adjustment in the form of a number of bits to downshift.\r
+ */\r
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK)\r
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U)\r
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U)\r
+/*! SATURATEAT16BIT - Selects 16-bit saturation.\r
+ * 0b0..Results roll over if out range and do not saturate.\r
+ * 0b1..If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow.\r
+ */\r
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMIC_CHANNEL_DC_CTRL */\r
+#define DMIC_CHANNEL_DC_CTRL_COUNT (2U)\r
+\r
+/*! @name CHANEN - Channel Enable register */\r
+/*! @{ */\r
+#define DMIC_CHANEN_EN_CH0_MASK (0x1U)\r
+#define DMIC_CHANEN_EN_CH0_SHIFT (0U)\r
+/*! EN_CH0 - Enable channel 0. When 1, PDM channel 0 is enabled.\r
+ */\r
+#define DMIC_CHANEN_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK)\r
+#define DMIC_CHANEN_EN_CH1_MASK (0x2U)\r
+#define DMIC_CHANEN_EN_CH1_SHIFT (1U)\r
+/*! EN_CH1 - Enable channel 1. When 1, PDM channel 1 is enabled.\r
+ */\r
+#define DMIC_CHANEN_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK)\r
+/*! @} */\r
+\r
+/*! @name IOCFG - I/O Configuration register */\r
+/*! @{ */\r
+#define DMIC_IOCFG_CLK_BYPASS0_MASK (0x1U)\r
+#define DMIC_IOCFG_CLK_BYPASS0_SHIFT (0U)\r
+/*! CLK_BYPASS0 - Bypass CLK0. When 1, PDM_DATA1 becomes the clock for PDM channel 0. This provides\r
+ * for the possibility of an external codec taking over the PDM bus.\r
+ */\r
+#define DMIC_IOCFG_CLK_BYPASS0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK)\r
+#define DMIC_IOCFG_CLK_BYPASS1_MASK (0x2U)\r
+#define DMIC_IOCFG_CLK_BYPASS1_SHIFT (1U)\r
+/*! CLK_BYPASS1 - Bypass CLK1. When 1, PDM_DATA1 becomes the clock for PDM channel 1. This provides\r
+ * for the possibility of an external codec taking over the PDM bus.\r
+ */\r
+#define DMIC_IOCFG_CLK_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK)\r
+#define DMIC_IOCFG_STEREO_DATA0_MASK (0x4U)\r
+#define DMIC_IOCFG_STEREO_DATA0_SHIFT (2U)\r
+/*! STEREO_DATA0 - Stereo PDM select. When 1, PDM_DATA0 is routed to both PDM channels in a\r
+ * configuration that supports a single stereo digital microphone.\r
+ */\r
+#define DMIC_IOCFG_STEREO_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK)\r
+/*! @} */\r
+\r
+/*! @name USE2FS - Use 2FS register */\r
+/*! @{ */\r
+#define DMIC_USE2FS_USE2FS_MASK (0x1U)\r
+#define DMIC_USE2FS_USE2FS_SHIFT (0U)\r
+/*! USE2FS - Use 2FS register\r
+ * 0b0..Use 1FS output for PCM data.\r
+ * 0b1..Use 2FS output for PCM data.\r
+ */\r
+#define DMIC_USE2FS_USE2FS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK)\r
+/*! @} */\r
+\r
+/*! @name HWVADGAIN - HWVAD input gain register */\r
+/*! @{ */\r
+#define DMIC_HWVADGAIN_INPUTGAIN_MASK (0xFU)\r
+#define DMIC_HWVADGAIN_INPUTGAIN_SHIFT (0U)\r
+/*! INPUTGAIN - Shift value for input bits 0x00 -10 bits 0x01 -8 bits 0x02 -6 bits 0x03 -4 bits 0x04\r
+ * -2 bits 0x05 0 bits (default) 0x06 +2 bits 0x07 +4 bits 0x08 +6 bits 0x09 +8 bits 0x0A +10\r
+ * bits 0x0B +12 bits 0x0C +14 bits 0x0D to 0x0F Reserved.\r
+ */\r
+#define DMIC_HWVADGAIN_INPUTGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK)\r
+/*! @} */\r
+\r
+/*! @name HWVADHPFS - HWVAD filter control register */\r
+/*! @{ */\r
+#define DMIC_HWVADHPFS_HPFS_MASK (0x3U)\r
+#define DMIC_HWVADHPFS_HPFS_SHIFT (0U)\r
+/*! HPFS - High pass filter\r
+ * 0b00..First filter by-pass.\r
+ * 0b01..High pass filter with -3dB cut-off at 1750Hz.\r
+ * 0b10..High pass filter with -3dB cut-off at 215Hz.\r
+ * 0b11..Reserved.\r
+ */\r
+#define DMIC_HWVADHPFS_HPFS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK)\r
+/*! @} */\r
+\r
+/*! @name HWVADST10 - HWVAD control register */\r
+/*! @{ */\r
+#define DMIC_HWVADST10_ST10_MASK (0x1U)\r
+#define DMIC_HWVADST10_ST10_SHIFT (0U)\r
+/*! ST10 - Stage 0\r
+ * 0b0..Normal operation, waiting for HWVAD trigger event (stage 0).\r
+ * 0b1..Reset internal interrupt flag by writing a '1' pulse.\r
+ */\r
+#define DMIC_HWVADST10_ST10(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK)\r
+/*! @} */\r
+\r
+/*! @name HWVADRSTT - HWVAD filter reset register */\r
+/*! @{ */\r
+#define DMIC_HWVADRSTT_RSTT_MASK (0x1U)\r
+#define DMIC_HWVADRSTT_RSTT_SHIFT (0U)\r
+/*! RSTT - Writing a 1 resets all filter values\r
+ */\r
+#define DMIC_HWVADRSTT_RSTT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK)\r
+/*! @} */\r
+\r
+/*! @name HWVADTHGN - HWVAD noise estimator gain register */\r
+/*! @{ */\r
+#define DMIC_HWVADTHGN_THGN_MASK (0xFU)\r
+#define DMIC_HWVADTHGN_THGN_SHIFT (0U)\r
+/*! THGN - Gain value for the noise estimator. Values 0 to 14. 0 corresponds to a gain of 1.\r
+ */\r
+#define DMIC_HWVADTHGN_THGN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK)\r
+/*! @} */\r
+\r
+/*! @name HWVADTHGS - HWVAD signal estimator gain register */\r
+/*! @{ */\r
+#define DMIC_HWVADTHGS_THGS_MASK (0xFU)\r
+#define DMIC_HWVADTHGS_THGS_SHIFT (0U)\r
+/*! THGS - Gain value for the signal estimator. Values 0 to 14. 0 corresponds to a gain of 1.\r
+ */\r
+#define DMIC_HWVADTHGS_THGS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK)\r
+/*! @} */\r
+\r
+/*! @name HWVADLOWZ - HWVAD noise envelope estimator register */\r
+/*! @{ */\r
+#define DMIC_HWVADLOWZ_LOWZ_MASK (0xFFFFU)\r
+#define DMIC_HWVADLOWZ_LOWZ_SHIFT (0U)\r
+/*! LOWZ - Noise envelope estimator value.\r
+ */\r
+#define DMIC_HWVADLOWZ_LOWZ(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK)\r
+/*! @} */\r
+\r
+/*! @name ID - Module Identification register */\r
+/*! @{ */\r
+#define DMIC_ID_ID_MASK (0xFFFFFFFFU)\r
+#define DMIC_ID_ID_SHIFT (0U)\r
+/*! ID - Indicates module ID and the number of channels in this DMIC interface.\r
+ */\r
+#define DMIC_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group DMIC_Register_Masks */\r
+\r
+\r
+/* DMIC - Peripheral instance base addresses */\r
+/** Peripheral DMIC0 base address */\r
+#define DMIC0_BASE (0x40090000u)\r
+/** Peripheral DMIC0 base pointer */\r
+#define DMIC0 ((DMIC_Type *)DMIC0_BASE)\r
+/** Array initializer of DMIC peripheral base addresses */\r
+#define DMIC_BASE_ADDRS { DMIC0_BASE }\r
+/** Array initializer of DMIC peripheral base pointers */\r
+#define DMIC_BASE_PTRS { DMIC0 }\r
+/** Interrupt vectors for the DMIC peripheral type */\r
+#define DMIC_IRQS { DMIC0_IRQn }\r
+#define DMIC_HWVAD_IRQS { HWVAD0_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group DMIC_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- EMC Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup EMC_Peripheral_Access_Layer EMC Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** EMC - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t CONTROL; /**< Controls operation of the memory controller, offset: 0x0 */\r
+ __I uint32_t STATUS; /**< Provides EMC status information, offset: 0x4 */\r
+ __IO uint32_t CONFIG; /**< Configures operation of the memory controller, offset: 0x8 */\r
+ uint8_t RESERVED_0[20];\r
+ __IO uint32_t DYNAMICCONTROL; /**< Controls dynamic memory operation, offset: 0x20 */\r
+ __IO uint32_t DYNAMICREFRESH; /**< Configures dynamic memory refresh, offset: 0x24 */\r
+ __IO uint32_t DYNAMICREADCONFIG; /**< Configures dynamic memory read strategy, offset: 0x28 */\r
+ uint8_t RESERVED_1[4];\r
+ __IO uint32_t DYNAMICRP; /**< Precharge command period, offset: 0x30 */\r
+ __IO uint32_t DYNAMICRAS; /**< Active to precharge command period, offset: 0x34 */\r
+ __IO uint32_t DYNAMICSREX; /**< Self-refresh exit time, offset: 0x38 */\r
+ __IO uint32_t DYNAMICAPR; /**< Last-data-out to active command time, offset: 0x3C */\r
+ __IO uint32_t DYNAMICDAL; /**< Data-in to active command time, offset: 0x40 */\r
+ __IO uint32_t DYNAMICWR; /**< Write recovery time, offset: 0x44 */\r
+ __IO uint32_t DYNAMICRC; /**< Selects the active to active command period, offset: 0x48 */\r
+ __IO uint32_t DYNAMICRFC; /**< Selects the auto-refresh period, offset: 0x4C */\r
+ __IO uint32_t DYNAMICXSR; /**< Time for exit self-refresh to active command, offset: 0x50 */\r
+ __IO uint32_t DYNAMICRRD; /**< Latency for active bank A to active bank B, offset: 0x54 */\r
+ __IO uint32_t DYNAMICMRD; /**< Time for load mode register to active command, offset: 0x58 */\r
+ uint8_t RESERVED_2[36];\r
+ __IO uint32_t STATICEXTENDEDWAIT; /**< Time for long static memory read and write transfers, offset: 0x80 */\r
+ uint8_t RESERVED_3[124];\r
+ struct { /* offset: 0x100, array step: 0x20 */\r
+ __IO uint32_t DYNAMICCONFIG; /**< Configuration information for EMC_DYCSx, array offset: 0x100, array step: 0x20 */\r
+ __IO uint32_t DYNAMICRASCAS; /**< RAS and CAS latencies for EMC_DYCSx, array offset: 0x104, array step: 0x20 */\r
+ uint8_t RESERVED_0[24];\r
+ } DYNAMIC[4];\r
+ uint8_t RESERVED_4[128];\r
+ struct { /* offset: 0x200, array step: 0x20 */\r
+ __IO uint32_t STATICCONFIG; /**< Configuration for EMC_CSx, array offset: 0x200, array step: 0x20 */\r
+ __IO uint32_t STATICWAITWEN; /**< Delay from EMC_CSx to write enable, array offset: 0x204, array step: 0x20 */\r
+ __IO uint32_t STATICWAITOEN; /**< Delay from EMC_CSx or address change, whichever is later, to output enable, array offset: 0x208, array step: 0x20 */\r
+ __IO uint32_t STATICWAITRD; /**< Delay from EMC_CSx to a read access, array offset: 0x20C, array step: 0x20 */\r
+ __IO uint32_t STATICWAITPAGE; /**< Delay for asynchronous page mode sequential accesses for EMC_CSx, array offset: 0x210, array step: 0x20 */\r
+ __IO uint32_t STATICWAITWR; /**< Delay from EMC_CSx to a write access, array offset: 0x214, array step: 0x20 */\r
+ __IO uint32_t STATICWAITTURN; /**< Number of bus turnaround cycles EMC_CSx, array offset: 0x218, array step: 0x20 */\r
+ uint8_t RESERVED_0[4];\r
+ } STATIC[4];\r
+} EMC_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- EMC Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup EMC_Register_Masks EMC Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CONTROL - Controls operation of the memory controller */\r
+/*! @{ */\r
+#define EMC_CONTROL_E_MASK (0x1U)\r
+#define EMC_CONTROL_E_SHIFT (0U)\r
+/*! E - EMC Enable.\r
+ */\r
+#define EMC_CONTROL_E(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_E_SHIFT)) & EMC_CONTROL_E_MASK)\r
+#define EMC_CONTROL_M_MASK (0x2U)\r
+#define EMC_CONTROL_M_SHIFT (1U)\r
+/*! M - Address mirror.\r
+ */\r
+#define EMC_CONTROL_M(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_M_SHIFT)) & EMC_CONTROL_M_MASK)\r
+#define EMC_CONTROL_L_MASK (0x4U)\r
+#define EMC_CONTROL_L_SHIFT (2U)\r
+/*! L - Low-power mode.\r
+ */\r
+#define EMC_CONTROL_L(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_L_SHIFT)) & EMC_CONTROL_L_MASK)\r
+/*! @} */\r
+\r
+/*! @name STATUS - Provides EMC status information */\r
+/*! @{ */\r
+#define EMC_STATUS_B_MASK (0x1U)\r
+#define EMC_STATUS_B_SHIFT (0U)\r
+/*! B - Busy.\r
+ */\r
+#define EMC_STATUS_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_B_SHIFT)) & EMC_STATUS_B_MASK)\r
+#define EMC_STATUS_S_MASK (0x2U)\r
+#define EMC_STATUS_S_SHIFT (1U)\r
+/*! S - Write buffer status.\r
+ */\r
+#define EMC_STATUS_S(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_S_SHIFT)) & EMC_STATUS_S_MASK)\r
+#define EMC_STATUS_SA_MASK (0x4U)\r
+#define EMC_STATUS_SA_SHIFT (2U)\r
+/*! SA - Self-refresh acknowledge.\r
+ */\r
+#define EMC_STATUS_SA(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_SA_SHIFT)) & EMC_STATUS_SA_MASK)\r
+/*! @} */\r
+\r
+/*! @name CONFIG - Configures operation of the memory controller */\r
+/*! @{ */\r
+#define EMC_CONFIG_EM_MASK (0x1U)\r
+#define EMC_CONFIG_EM_SHIFT (0U)\r
+/*! EM - Endian mode.\r
+ */\r
+#define EMC_CONFIG_EM(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_EM_SHIFT)) & EMC_CONFIG_EM_MASK)\r
+#define EMC_CONFIG_CLKR_MASK (0x100U)\r
+#define EMC_CONFIG_CLKR_SHIFT (8U)\r
+/*! CLKR - This bit must contain 0 for proper operation of the EMC.\r
+ */\r
+#define EMC_CONFIG_CLKR(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_CLKR_SHIFT)) & EMC_CONFIG_CLKR_MASK)\r
+/*! @} */\r
+\r
+/*! @name DYNAMICCONTROL - Controls dynamic memory operation */\r
+/*! @{ */\r
+#define EMC_DYNAMICCONTROL_CE_MASK (0x1U)\r
+#define EMC_DYNAMICCONTROL_CE_SHIFT (0U)\r
+/*! CE - Dynamic memory clock enable.\r
+ */\r
+#define EMC_DYNAMICCONTROL_CE(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CE_SHIFT)) & EMC_DYNAMICCONTROL_CE_MASK)\r
+#define EMC_DYNAMICCONTROL_CS_MASK (0x2U)\r
+#define EMC_DYNAMICCONTROL_CS_SHIFT (1U)\r
+/*! CS - Dynamic memory clock control.\r
+ */\r
+#define EMC_DYNAMICCONTROL_CS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CS_SHIFT)) & EMC_DYNAMICCONTROL_CS_MASK)\r
+#define EMC_DYNAMICCONTROL_SR_MASK (0x4U)\r
+#define EMC_DYNAMICCONTROL_SR_SHIFT (2U)\r
+/*! SR - Self-refresh request, EMCSREFREQ.\r
+ */\r
+#define EMC_DYNAMICCONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_SR_SHIFT)) & EMC_DYNAMICCONTROL_SR_MASK)\r
+#define EMC_DYNAMICCONTROL_MMC_MASK (0x20U)\r
+#define EMC_DYNAMICCONTROL_MMC_SHIFT (5U)\r
+/*! MMC - Memory clock control.\r
+ */\r
+#define EMC_DYNAMICCONTROL_MMC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_MMC_SHIFT)) & EMC_DYNAMICCONTROL_MMC_MASK)\r
+#define EMC_DYNAMICCONTROL_I_MASK (0x180U)\r
+#define EMC_DYNAMICCONTROL_I_SHIFT (7U)\r
+/*! I - SDRAM initialization.\r
+ */\r
+#define EMC_DYNAMICCONTROL_I(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_I_SHIFT)) & EMC_DYNAMICCONTROL_I_MASK)\r
+/*! @} */\r
+\r
+/*! @name DYNAMICREFRESH - Configures dynamic memory refresh */\r
+/*! @{ */\r
+#define EMC_DYNAMICREFRESH_REFRESH_MASK (0x7FFU)\r
+#define EMC_DYNAMICREFRESH_REFRESH_SHIFT (0U)\r
+/*! REFRESH - Refresh timer.\r
+ */\r
+#define EMC_DYNAMICREFRESH_REFRESH(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREFRESH_REFRESH_SHIFT)) & EMC_DYNAMICREFRESH_REFRESH_MASK)\r
+/*! @} */\r
+\r
+/*! @name DYNAMICREADCONFIG - Configures dynamic memory read strategy */\r
+/*! @{ */\r
+#define EMC_DYNAMICREADCONFIG_RD_MASK (0x3U)\r
+#define EMC_DYNAMICREADCONFIG_RD_SHIFT (0U)\r
+/*! RD - Read data strategy.\r
+ */\r
+#define EMC_DYNAMICREADCONFIG_RD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREADCONFIG_RD_SHIFT)) & EMC_DYNAMICREADCONFIG_RD_MASK)\r
+/*! @} */\r
+\r
+/*! @name DYNAMICRP - Precharge command period */\r
+/*! @{ */\r
+#define EMC_DYNAMICRP_TRP_MASK (0xFU)\r
+#define EMC_DYNAMICRP_TRP_SHIFT (0U)\r
+/*! TRP - Precharge command period.\r
+ */\r
+#define EMC_DYNAMICRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRP_TRP_SHIFT)) & EMC_DYNAMICRP_TRP_MASK)\r
+/*! @} */\r
+\r
+/*! @name DYNAMICRAS - Active to precharge command period */\r
+/*! @{ */\r
+#define EMC_DYNAMICRAS_TRAS_MASK (0xFU)\r
+#define EMC_DYNAMICRAS_TRAS_SHIFT (0U)\r
+/*! TRAS - Active to precharge command period.\r
+ */\r
+#define EMC_DYNAMICRAS_TRAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRAS_TRAS_SHIFT)) & EMC_DYNAMICRAS_TRAS_MASK)\r
+/*! @} */\r
+\r
+/*! @name DYNAMICSREX - Self-refresh exit time */\r
+/*! @{ */\r
+#define EMC_DYNAMICSREX_TSREX_MASK (0xFU)\r
+#define EMC_DYNAMICSREX_TSREX_SHIFT (0U)\r
+/*! TSREX - Self-refresh exit time.\r
+ */\r
+#define EMC_DYNAMICSREX_TSREX(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICSREX_TSREX_SHIFT)) & EMC_DYNAMICSREX_TSREX_MASK)\r
+/*! @} */\r
+\r
+/*! @name DYNAMICAPR - Last-data-out to active command time */\r
+/*! @{ */\r
+#define EMC_DYNAMICAPR_TAPR_MASK (0xFU)\r
+#define EMC_DYNAMICAPR_TAPR_SHIFT (0U)\r
+/*! TAPR - Last-data-out to active command time.\r
+ */\r
+#define EMC_DYNAMICAPR_TAPR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICAPR_TAPR_SHIFT)) & EMC_DYNAMICAPR_TAPR_MASK)\r
+/*! @} */\r
+\r
+/*! @name DYNAMICDAL - Data-in to active command time */\r
+/*! @{ */\r
+#define EMC_DYNAMICDAL_TDAL_MASK (0xFU)\r
+#define EMC_DYNAMICDAL_TDAL_SHIFT (0U)\r
+/*! TDAL - Data-in to active command.\r
+ */\r
+#define EMC_DYNAMICDAL_TDAL(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICDAL_TDAL_SHIFT)) & EMC_DYNAMICDAL_TDAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name DYNAMICWR - Write recovery time */\r
+/*! @{ */\r
+#define EMC_DYNAMICWR_TWR_MASK (0xFU)\r
+#define EMC_DYNAMICWR_TWR_SHIFT (0U)\r
+/*! TWR - Write recovery time.\r
+ */\r
+#define EMC_DYNAMICWR_TWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICWR_TWR_SHIFT)) & EMC_DYNAMICWR_TWR_MASK)\r
+/*! @} */\r
+\r
+/*! @name DYNAMICRC - Selects the active to active command period */\r
+/*! @{ */\r
+#define EMC_DYNAMICRC_TRC_MASK (0x1FU)\r
+#define EMC_DYNAMICRC_TRC_SHIFT (0U)\r
+/*! TRC - Active to active command period.\r
+ */\r
+#define EMC_DYNAMICRC_TRC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRC_TRC_SHIFT)) & EMC_DYNAMICRC_TRC_MASK)\r
+/*! @} */\r
+\r
+/*! @name DYNAMICRFC - Selects the auto-refresh period */\r
+/*! @{ */\r
+#define EMC_DYNAMICRFC_TRFC_MASK (0x1FU)\r
+#define EMC_DYNAMICRFC_TRFC_SHIFT (0U)\r
+/*! TRFC - Auto-refresh period and auto-refresh to active command period.\r
+ */\r
+#define EMC_DYNAMICRFC_TRFC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRFC_TRFC_SHIFT)) & EMC_DYNAMICRFC_TRFC_MASK)\r
+/*! @} */\r
+\r
+/*! @name DYNAMICXSR - Time for exit self-refresh to active command */\r
+/*! @{ */\r
+#define EMC_DYNAMICXSR_TXSR_MASK (0x1FU)\r
+#define EMC_DYNAMICXSR_TXSR_SHIFT (0U)\r
+/*! TXSR - Exit self-refresh to active command time.\r
+ */\r
+#define EMC_DYNAMICXSR_TXSR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICXSR_TXSR_SHIFT)) & EMC_DYNAMICXSR_TXSR_MASK)\r
+/*! @} */\r
+\r
+/*! @name DYNAMICRRD - Latency for active bank A to active bank B */\r
+/*! @{ */\r
+#define EMC_DYNAMICRRD_TRRD_MASK (0xFU)\r
+#define EMC_DYNAMICRRD_TRRD_SHIFT (0U)\r
+/*! TRRD - Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles.\r
+ */\r
+#define EMC_DYNAMICRRD_TRRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRRD_TRRD_SHIFT)) & EMC_DYNAMICRRD_TRRD_MASK)\r
+/*! @} */\r
+\r
+/*! @name DYNAMICMRD - Time for load mode register to active command */\r
+/*! @{ */\r
+#define EMC_DYNAMICMRD_TMRD_MASK (0xFU)\r
+#define EMC_DYNAMICMRD_TMRD_SHIFT (0U)\r
+/*! TMRD - Load mode register to active command time.\r
+ */\r
+#define EMC_DYNAMICMRD_TMRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICMRD_TMRD_SHIFT)) & EMC_DYNAMICMRD_TMRD_MASK)\r
+/*! @} */\r
+\r
+/*! @name STATICEXTENDEDWAIT - Time for long static memory read and write transfers */\r
+/*! @{ */\r
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK (0x3FFU)\r
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT (0U)\r
+/*! EXTENDEDWAIT - Extended wait time out.\r
+ */\r
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT)) & EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK)\r
+/*! @} */\r
+\r
+/*! @name DYNAMIC_DYNAMICCONFIG - Configuration information for EMC_DYCSx */\r
+/*! @{ */\r
+#define EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK (0x18U)\r
+#define EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT (3U)\r
+/*! MD - Memory device.\r
+ */\r
+#define EMC_DYNAMIC_DYNAMICCONFIG_MD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK)\r
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK (0x1F80U)\r
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT (7U)\r
+/*! AM0 - See Table 933.\r
+ */\r
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM0(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK)\r
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK (0x4000U)\r
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT (14U)\r
+/*! AM1 - See Table 933.\r
+ */\r
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM1(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK)\r
+#define EMC_DYNAMIC_DYNAMICCONFIG_B_MASK (0x80000U)\r
+#define EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT (19U)\r
+/*! B - Buffer enable.\r
+ */\r
+#define EMC_DYNAMIC_DYNAMICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_B_MASK)\r
+#define EMC_DYNAMIC_DYNAMICCONFIG_P_MASK (0x100000U)\r
+#define EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT (20U)\r
+/*! P - Write protect.\r
+ */\r
+#define EMC_DYNAMIC_DYNAMICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_P_MASK)\r
+/*! @} */\r
+\r
+/* The count of EMC_DYNAMIC_DYNAMICCONFIG */\r
+#define EMC_DYNAMIC_DYNAMICCONFIG_COUNT (4U)\r
+\r
+/*! @name DYNAMIC_DYNAMICRASCAS - RAS and CAS latencies for EMC_DYCSx */\r
+/*! @{ */\r
+#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK (0x3U)\r
+#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT (0U)\r
+/*! RAS - RAS latency (active to read/write delay).\r
+ */\r
+#define EMC_DYNAMIC_DYNAMICRASCAS_RAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK)\r
+#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK (0x300U)\r
+#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT (8U)\r
+/*! CAS - CAS latency.\r
+ */\r
+#define EMC_DYNAMIC_DYNAMICRASCAS_CAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK)\r
+/*! @} */\r
+\r
+/* The count of EMC_DYNAMIC_DYNAMICRASCAS */\r
+#define EMC_DYNAMIC_DYNAMICRASCAS_COUNT (4U)\r
+\r
+/*! @name STATIC_STATICCONFIG - Configuration for EMC_CSx */\r
+/*! @{ */\r
+#define EMC_STATIC_STATICCONFIG_MW_MASK (0x3U)\r
+#define EMC_STATIC_STATICCONFIG_MW_SHIFT (0U)\r
+/*! MW - Memory width.\r
+ */\r
+#define EMC_STATIC_STATICCONFIG_MW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_MW_SHIFT)) & EMC_STATIC_STATICCONFIG_MW_MASK)\r
+#define EMC_STATIC_STATICCONFIG_PM_MASK (0x8U)\r
+#define EMC_STATIC_STATICCONFIG_PM_SHIFT (3U)\r
+/*! PM - Page mode.\r
+ */\r
+#define EMC_STATIC_STATICCONFIG_PM(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PM_SHIFT)) & EMC_STATIC_STATICCONFIG_PM_MASK)\r
+#define EMC_STATIC_STATICCONFIG_PC_MASK (0x40U)\r
+#define EMC_STATIC_STATICCONFIG_PC_SHIFT (6U)\r
+/*! PC - Chip select polarity.\r
+ */\r
+#define EMC_STATIC_STATICCONFIG_PC(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PC_SHIFT)) & EMC_STATIC_STATICCONFIG_PC_MASK)\r
+#define EMC_STATIC_STATICCONFIG_PB_MASK (0x80U)\r
+#define EMC_STATIC_STATICCONFIG_PB_SHIFT (7U)\r
+/*! PB - Byte lane state.\r
+ */\r
+#define EMC_STATIC_STATICCONFIG_PB(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PB_SHIFT)) & EMC_STATIC_STATICCONFIG_PB_MASK)\r
+#define EMC_STATIC_STATICCONFIG_EW_MASK (0x100U)\r
+#define EMC_STATIC_STATICCONFIG_EW_SHIFT (8U)\r
+/*! EW - Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write\r
+ * transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers.\r
+ */\r
+#define EMC_STATIC_STATICCONFIG_EW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_EW_SHIFT)) & EMC_STATIC_STATICCONFIG_EW_MASK)\r
+#define EMC_STATIC_STATICCONFIG_B_MASK (0x80000U)\r
+#define EMC_STATIC_STATICCONFIG_B_SHIFT (19U)\r
+/*! B - Buffer enable [2].\r
+ */\r
+#define EMC_STATIC_STATICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_B_SHIFT)) & EMC_STATIC_STATICCONFIG_B_MASK)\r
+#define EMC_STATIC_STATICCONFIG_P_MASK (0x100000U)\r
+#define EMC_STATIC_STATICCONFIG_P_SHIFT (20U)\r
+/*! P - Write protect.\r
+ */\r
+#define EMC_STATIC_STATICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_P_SHIFT)) & EMC_STATIC_STATICCONFIG_P_MASK)\r
+/*! @} */\r
+\r
+/* The count of EMC_STATIC_STATICCONFIG */\r
+#define EMC_STATIC_STATICCONFIG_COUNT (4U)\r
+\r
+/*! @name STATIC_STATICWAITWEN - Delay from EMC_CSx to write enable */\r
+/*! @{ */\r
+#define EMC_STATIC_STATICWAITWEN_WAITWEN_MASK (0xFU)\r
+#define EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT (0U)\r
+/*! WAITWEN - Wait write enable.\r
+ */\r
+#define EMC_STATIC_STATICWAITWEN_WAITWEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT)) & EMC_STATIC_STATICWAITWEN_WAITWEN_MASK)\r
+/*! @} */\r
+\r
+/* The count of EMC_STATIC_STATICWAITWEN */\r
+#define EMC_STATIC_STATICWAITWEN_COUNT (4U)\r
+\r
+/*! @name STATIC_STATICWAITOEN - Delay from EMC_CSx or address change, whichever is later, to output enable */\r
+/*! @{ */\r
+#define EMC_STATIC_STATICWAITOEN_WAITOEN_MASK (0xFU)\r
+#define EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT (0U)\r
+/*! WAITOEN - Wait output enable.\r
+ */\r
+#define EMC_STATIC_STATICWAITOEN_WAITOEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT)) & EMC_STATIC_STATICWAITOEN_WAITOEN_MASK)\r
+/*! @} */\r
+\r
+/* The count of EMC_STATIC_STATICWAITOEN */\r
+#define EMC_STATIC_STATICWAITOEN_COUNT (4U)\r
+\r
+/*! @name STATIC_STATICWAITRD - Delay from EMC_CSx to a read access */\r
+/*! @{ */\r
+#define EMC_STATIC_STATICWAITRD_WAITRD_MASK (0x1FU)\r
+#define EMC_STATIC_STATICWAITRD_WAITRD_SHIFT (0U)\r
+/*! WAITRD - .\r
+ */\r
+#define EMC_STATIC_STATICWAITRD_WAITRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITRD_WAITRD_SHIFT)) & EMC_STATIC_STATICWAITRD_WAITRD_MASK)\r
+/*! @} */\r
+\r
+/* The count of EMC_STATIC_STATICWAITRD */\r
+#define EMC_STATIC_STATICWAITRD_COUNT (4U)\r
+\r
+/*! @name STATIC_STATICWAITPAGE - Delay for asynchronous page mode sequential accesses for EMC_CSx */\r
+/*! @{ */\r
+#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK (0x1FU)\r
+#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT (0U)\r
+/*! WAITPAGE - Asynchronous page mode read after the first read wait states.\r
+ */\r
+#define EMC_STATIC_STATICWAITPAGE_WAITPAGE(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT)) & EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK)\r
+/*! @} */\r
+\r
+/* The count of EMC_STATIC_STATICWAITPAGE */\r
+#define EMC_STATIC_STATICWAITPAGE_COUNT (4U)\r
+\r
+/*! @name STATIC_STATICWAITWR - Delay from EMC_CSx to a write access */\r
+/*! @{ */\r
+#define EMC_STATIC_STATICWAITWR_WAITWR_MASK (0x1FU)\r
+#define EMC_STATIC_STATICWAITWR_WAITWR_SHIFT (0U)\r
+/*! WAITWR - Write wait states.\r
+ */\r
+#define EMC_STATIC_STATICWAITWR_WAITWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWR_WAITWR_SHIFT)) & EMC_STATIC_STATICWAITWR_WAITWR_MASK)\r
+/*! @} */\r
+\r
+/* The count of EMC_STATIC_STATICWAITWR */\r
+#define EMC_STATIC_STATICWAITWR_COUNT (4U)\r
+\r
+/*! @name STATIC_STATICWAITTURN - Number of bus turnaround cycles EMC_CSx */\r
+/*! @{ */\r
+#define EMC_STATIC_STATICWAITTURN_WAITTURN_MASK (0xFU)\r
+#define EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT (0U)\r
+/*! WAITTURN - Bus turn-around cycles.\r
+ */\r
+#define EMC_STATIC_STATICWAITTURN_WAITTURN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT)) & EMC_STATIC_STATICWAITTURN_WAITTURN_MASK)\r
+/*! @} */\r
+\r
+/* The count of EMC_STATIC_STATICWAITTURN */\r
+#define EMC_STATIC_STATICWAITTURN_COUNT (4U)\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group EMC_Register_Masks */\r
+\r
+\r
+/* EMC - Peripheral instance base addresses */\r
+/** Peripheral EMC base address */\r
+#define EMC_BASE (0x40081000u)\r
+/** Peripheral EMC base pointer */\r
+#define EMC ((EMC_Type *)EMC_BASE)\r
+/** Array initializer of EMC peripheral base addresses */\r
+#define EMC_BASE_ADDRS { EMC_BASE }\r
+/** Array initializer of EMC peripheral base pointers */\r
+#define EMC_BASE_PTRS { EMC }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group EMC_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- ENET Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** ENET - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t MAC_CONFIG; /**< MAC configuration register, offset: 0x0 */\r
+ __IO uint32_t MAC_EXT_CONFIG; /**< , offset: 0x4 */\r
+ __IO uint32_t MAC_FRAME_FILTER; /**< MAC frame filter register, offset: 0x8 */\r
+ __IO uint32_t MAC_WD_TIMEROUT; /**< MAC watchdog Timeout register, offset: 0xC */\r
+ uint8_t RESERVED_0[64];\r
+ __IO uint32_t MAC_VLAN_TAG; /**< MAC vlan tag register, offset: 0x50 */\r
+ uint8_t RESERVED_1[28];\r
+ __IO uint32_t MAC_TX_FLOW_CTRL_Q[2]; /**< Transmit flow control register, array offset: 0x70, array step: 0x4 */\r
+ uint8_t RESERVED_2[24];\r
+ __IO uint32_t MAC_RX_FLOW_CTRL; /**< Receive flow control register, offset: 0x90 */\r
+ uint8_t RESERVED_3[4];\r
+ __IO uint32_t MAC_TXQ_PRIO_MAP; /**< , offset: 0x98 */\r
+ uint8_t RESERVED_4[4];\r
+ __IO uint32_t MAC_RXQ_CTRL[3]; /**< Receive Queue Control 0 register 0x0000, array offset: 0xA0, array step: 0x4 */\r
+ uint8_t RESERVED_5[4];\r
+ __I uint32_t MAC_INTR_STAT; /**< Interrupt status register 0x0000, offset: 0xB0 */\r
+ __IO uint32_t MAC_INTR_EN; /**< Interrupt enable register 0x0000, offset: 0xB4 */\r
+ __I uint32_t MAC_RXTX_STAT; /**< Receive Transmit Status register, offset: 0xB8 */\r
+ uint8_t RESERVED_6[4];\r
+ __IO uint32_t MAC_PMT_CRTL_STAT; /**< , offset: 0xC0 */\r
+ __IO uint32_t MAC_RWAKE_FRFLT; /**< Remote wake-up frame filter, offset: 0xC4 */\r
+ uint8_t RESERVED_7[8];\r
+ __IO uint32_t MAC_LPI_CTRL_STAT; /**< LPI Control and Status Register, offset: 0xD0 */\r
+ __IO uint32_t MAC_LPI_TIMER_CTRL; /**< LPI Timers Control register, offset: 0xD4 */\r
+ __IO uint32_t MAC_LPI_ENTR_TIMR; /**< LPI entry Timer register, offset: 0xD8 */\r
+ __IO uint32_t MAC_1US_TIC_COUNTR; /**< , offset: 0xDC */\r
+ uint8_t RESERVED_8[48];\r
+ __I uint32_t MAC_VERSION; /**< MAC version register, offset: 0x110 */\r
+ __I uint32_t MAC_DBG; /**< MAC debug register, offset: 0x114 */\r
+ uint8_t RESERVED_9[4];\r
+ __I uint32_t MAC_HW_FEAT[3]; /**< MAC hardware feature register 0x0201, array offset: 0x11C, array step: 0x4 */\r
+ uint8_t RESERVED_10[216];\r
+ __IO uint32_t MAC_MDIO_ADDR; /**< MIDO address Register, offset: 0x200 */\r
+ __IO uint32_t MAC_MDIO_DATA; /**< MDIO Data register, offset: 0x204 */\r
+ uint8_t RESERVED_11[248];\r
+ __IO uint32_t MAC_ADDR_HIGH; /**< MAC address0 high register, offset: 0x300 */\r
+ __IO uint32_t MAC_ADDR_LOW; /**< MAC address0 low register, offset: 0x304 */\r
+ uint8_t RESERVED_12[2040];\r
+ __IO uint32_t MAC_TIMESTAMP_CTRL; /**< Time stamp control register, offset: 0xB00 */\r
+ __IO uint32_t MAC_SUB_SCND_INCR; /**< Sub-second increment register, offset: 0xB04 */\r
+ __I uint32_t MAC_SYS_TIME_SCND; /**< System time seconds register, offset: 0xB08 */\r
+ __I uint32_t MAC_SYS_TIME_NSCND; /**< System time nanoseconds register, offset: 0xB0C */\r
+ __IO uint32_t MAC_SYS_TIME_SCND_UPD; /**< , offset: 0xB10 */\r
+ __IO uint32_t MAC_SYS_TIME_NSCND_UPD; /**< , offset: 0xB14 */\r
+ __IO uint32_t MAC_SYS_TIMESTMP_ADDEND; /**< Time stamp addend register, offset: 0xB18 */\r
+ __IO uint32_t MAC_SYS_TIME_HWORD_SCND; /**< , offset: 0xB1C */\r
+ __I uint32_t MAC_SYS_TIMESTMP_STAT; /**< Time stamp status register, offset: 0xB20 */\r
+ uint8_t RESERVED_13[12];\r
+ __I uint32_t MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; /**< Tx timestamp status nanoseconds, offset: 0xB30 */\r
+ __I uint32_t MAC_TX_TIMESTAMP_STATUS_SECONDS; /**< Tx timestamp status seconds, offset: 0xB34 */\r
+ uint8_t RESERVED_14[32];\r
+ __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; /**< Timestamp ingress correction, offset: 0xB58 */\r
+ __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; /**< Timestamp egress correction, offset: 0xB5C */\r
+ uint8_t RESERVED_15[160];\r
+ __IO uint32_t MTL_OP_MODE; /**< MTL Operation Mode Register, offset: 0xC00 */\r
+ uint8_t RESERVED_16[28];\r
+ __I uint32_t MTL_INTR_STAT; /**< MTL Interrupt Status register, offset: 0xC20 */\r
+ uint8_t RESERVED_17[12];\r
+ __IO uint32_t MTL_RXQ_DMA_MAP; /**< MTL Receive Queue and DMA Channel Mapping register, offset: 0xC30 */\r
+ uint8_t RESERVED_18[204];\r
+ struct { /* offset: 0xD00, array step: 0x40 */\r
+ __IO uint32_t MTL_TXQX_OP_MODE; /**< MTL TxQx Operation Mode register, array offset: 0xD00, array step: 0x40 */\r
+ __I uint32_t MTL_TXQX_UNDRFLW; /**< MTL TxQx Underflow register, array offset: 0xD04, array step: 0x40 */\r
+ __I uint32_t MTL_TXQX_DBG; /**< MTL TxQx Debug register, array offset: 0xD08, array step: 0x40 */\r
+ uint8_t RESERVED_0[4];\r
+ __IO uint32_t MTL_TXQX_ETS_CTRL; /**< MTL TxQx ETS control register, only TxQ1 support, array offset: 0xD10, array step: 0x40 */\r
+ __I uint32_t MTL_TXQX_ETS_STAT; /**< MTL TxQx ETS Status register, array offset: 0xD14, array step: 0x40 */\r
+ __IO uint32_t MTL_TXQX_QNTM_WGHT; /**< , array offset: 0xD18, array step: 0x40 */\r
+ __IO uint32_t MTL_TXQX_SNDSLP_CRDT; /**< MTL TxQx SendSlopCredit register, only TxQ1 support, array offset: 0xD1C, array step: 0x40 */\r
+ __IO uint32_t MTL_TXQX_HI_CRDT; /**< MTL TxQx hiCredit register, only TxQ1 support, array offset: 0xD20, array step: 0x40 */\r
+ __IO uint32_t MTL_TXQX_LO_CRDT; /**< MTL TxQx loCredit register, only TxQ1 support, array offset: 0xD24, array step: 0x40 */\r
+ uint8_t RESERVED_1[4];\r
+ __IO uint32_t MTL_TXQX_INTCTRL_STAT; /**< , array offset: 0xD2C, array step: 0x40 */\r
+ __IO uint32_t MTL_RXQX_OP_MODE; /**< MTL RxQx Operation Mode register, array offset: 0xD30, array step: 0x40 */\r
+ __I uint32_t MTL_RXQX_MISSPKT_OVRFLW_CNT; /**< MTL RxQx Missed Packet Overflow Counter register, array offset: 0xD34, array step: 0x40 */\r
+ __I uint32_t MTL_RXQX_DBG; /**< MTL RxQx Debug register, array offset: 0xD38, array step: 0x40 */\r
+ __IO uint32_t MTL_RXQX_CTRL; /**< MTL RxQx Control register, array offset: 0xD3C, array step: 0x40 */\r
+ } MTL_QUEUE[2];\r
+ uint8_t RESERVED_19[640];\r
+ __IO uint32_t DMA_MODE; /**< DMA mode register, offset: 0x1000 */\r
+ __IO uint32_t DMA_SYSBUS_MODE; /**< DMA System Bus mode, offset: 0x1004 */\r
+ __IO uint32_t DMA_INTR_STAT; /**< DMA Interrupt status, offset: 0x1008 */\r
+ __I uint32_t DMA_DBG_STAT; /**< DMA Debug Status, offset: 0x100C */\r
+ uint8_t RESERVED_20[240];\r
+ struct { /* offset: 0x1100, array step: 0x80 */\r
+ __IO uint32_t DMA_CHX_CTRL; /**< DMA Channelx Control, array offset: 0x1100, array step: 0x80 */\r
+ __IO uint32_t DMA_CHX_TX_CTRL; /**< DMA Channelx Transmit Control, array offset: 0x1104, array step: 0x80 */\r
+ __IO uint32_t DMA_CHX_RX_CTRL; /**< DMA Channelx Receive Control, array offset: 0x1108, array step: 0x80 */\r
+ uint8_t RESERVED_0[8];\r
+ __IO uint32_t DMA_CHX_TXDESC_LIST_ADDR; /**< , array offset: 0x1114, array step: 0x80 */\r
+ uint8_t RESERVED_1[4];\r
+ __IO uint32_t DMA_CHX_RXDESC_LIST_ADDR; /**< , array offset: 0x111C, array step: 0x80 */\r
+ __IO uint32_t DMA_CHX_TXDESC_TAIL_PTR; /**< , array offset: 0x1120, array step: 0x80 */\r
+ uint8_t RESERVED_2[4];\r
+ __IO uint32_t DMA_CHX_RXDESC_TAIL_PTR; /**< , array offset: 0x1128, array step: 0x80 */\r
+ __IO uint32_t DMA_CHX_TXDESC_RING_LENGTH; /**< , array offset: 0x112C, array step: 0x80 */\r
+ __IO uint32_t DMA_CHX_RXDESC_RING_LENGTH; /**< Channelx Rx descriptor Ring Length, array offset: 0x1130, array step: 0x80 */\r
+ __IO uint32_t DMA_CHX_INT_EN; /**< Channelx Interrupt Enable, array offset: 0x1134, array step: 0x80 */\r
+ __IO uint32_t DMA_CHX_RX_INT_WDTIMER; /**< Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */\r
+ __IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT; /**< Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */\r
+ uint8_t RESERVED_3[4];\r
+ __I uint32_t DMA_CHX_CUR_HST_TXDESC; /**< Channelx Current Host Transmit descriptor, array offset: 0x1144, array step: 0x80 */\r
+ uint8_t RESERVED_4[4];\r
+ __I uint32_t DMA_CHX_CUR_HST_RXDESC; /**< , array offset: 0x114C, array step: 0x80 */\r
+ uint8_t RESERVED_5[4];\r
+ __I uint32_t DMA_CHX_CUR_HST_TXBUF; /**< , array offset: 0x1154, array step: 0x80 */\r
+ uint8_t RESERVED_6[4];\r
+ __I uint32_t DMA_CHX_CUR_HST_RXBUF; /**< Channelx Current Application Receive Buffer Address, array offset: 0x115C, array step: 0x80 */\r
+ __IO uint32_t DMA_CHX_STAT; /**< Channelx DMA status register, array offset: 0x1160, array step: 0x80 */\r
+ uint8_t RESERVED_7[8];\r
+ __IO uint32_t DMA_CHX_MISS_FRAME_CNT; /**< Channelx missed frame count., array offset: 0x116C, array step: 0x80 */\r
+ uint8_t RESERVED_8[16];\r
+ } DMA_CH[2];\r
+} ENET_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- ENET Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup ENET_Register_Masks ENET Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name MAC_CONFIG - MAC configuration register */\r
+/*! @{ */\r
+#define ENET_MAC_CONFIG_RE_MASK (0x1U)\r
+#define ENET_MAC_CONFIG_RE_SHIFT (0U)\r
+/*! RE - Receiver Enable When this bit is set, the receiver state machine of the MAC is enabled for\r
+ * receiving frames from the MII.\r
+ */\r
+#define ENET_MAC_CONFIG_RE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_RE_SHIFT)) & ENET_MAC_CONFIG_RE_MASK)\r
+#define ENET_MAC_CONFIG_TE_MASK (0x2U)\r
+#define ENET_MAC_CONFIG_TE_SHIFT (1U)\r
+/*! TE - Transmitter Enable When this bit is set, the transmit state machine of the MAC is enabled for transmission on the MII.\r
+ */\r
+#define ENET_MAC_CONFIG_TE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_TE_SHIFT)) & ENET_MAC_CONFIG_TE_MASK)\r
+#define ENET_MAC_CONFIG_PRELEN_MASK (0xCU)\r
+#define ENET_MAC_CONFIG_PRELEN_SHIFT (2U)\r
+/*! PRELEN - Preamble Length for Transmit packets These bits control the number of preamble bytes\r
+ * that are added to the beginning of every Tx packet.\r
+ */\r
+#define ENET_MAC_CONFIG_PRELEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PRELEN_SHIFT)) & ENET_MAC_CONFIG_PRELEN_MASK)\r
+#define ENET_MAC_CONFIG_DC_MASK (0x10U)\r
+#define ENET_MAC_CONFIG_DC_SHIFT (4U)\r
+/*! DC - Deferral Check When this bit is set, the deferral check function is enabled in the MAC.\r
+ */\r
+#define ENET_MAC_CONFIG_DC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DC_SHIFT)) & ENET_MAC_CONFIG_DC_MASK)\r
+#define ENET_MAC_CONFIG_BL_MASK (0x60U)\r
+#define ENET_MAC_CONFIG_BL_SHIFT (5U)\r
+/*! BL - Back-Off Limit The Back-Off limit determines the random integer number (r) of slot time\r
+ * delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the MAC waits before\r
+ * rescheduling a transmission attempt during retries after a collision.\r
+ */\r
+#define ENET_MAC_CONFIG_BL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BL_SHIFT)) & ENET_MAC_CONFIG_BL_MASK)\r
+#define ENET_MAC_CONFIG_DR_MASK (0x100U)\r
+#define ENET_MAC_CONFIG_DR_SHIFT (8U)\r
+/*! DR - Disable Retry When this bit is set, the MAC will attempt only one transmission.\r
+ */\r
+#define ENET_MAC_CONFIG_DR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DR_SHIFT)) & ENET_MAC_CONFIG_DR_MASK)\r
+#define ENET_MAC_CONFIG_DCRS_MASK (0x200U)\r
+#define ENET_MAC_CONFIG_DCRS_SHIFT (9U)\r
+/*! DCRS - Disable Carrier Sense During Transmission When this bit is set, the MAC transmitter\r
+ * ignores the MII CRS signal during packet transmission in the half-duplex mode.\r
+ */\r
+#define ENET_MAC_CONFIG_DCRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DCRS_SHIFT)) & ENET_MAC_CONFIG_DCRS_MASK)\r
+#define ENET_MAC_CONFIG_DO_MASK (0x400U)\r
+#define ENET_MAC_CONFIG_DO_SHIFT (10U)\r
+/*! DO - Disable Receive Own When this bit is set, the MAC disables the reception of frames when the\r
+ * gmii_txen_o is asserted in Half-Duplex mode.\r
+ */\r
+#define ENET_MAC_CONFIG_DO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DO_SHIFT)) & ENET_MAC_CONFIG_DO_MASK)\r
+#define ENET_MAC_CONFIG_ECRSFD_MASK (0x800U)\r
+#define ENET_MAC_CONFIG_ECRSFD_SHIFT (11U)\r
+/*! ECRSFD - Enable Carrier Sense Before Transmission in Full-Duplex Mode When this bit is set, the\r
+ * MAC transmitter checks the CRS signal before packet transmission in the full-duplex mode.\r
+ */\r
+#define ENET_MAC_CONFIG_ECRSFD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ECRSFD_SHIFT)) & ENET_MAC_CONFIG_ECRSFD_MASK)\r
+#define ENET_MAC_CONFIG_LM_MASK (0x1000U)\r
+#define ENET_MAC_CONFIG_LM_SHIFT (12U)\r
+/*! LM - Loopback Mode When this bit is set, the MAC operates in loopback mode at MII.\r
+ */\r
+#define ENET_MAC_CONFIG_LM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_LM_SHIFT)) & ENET_MAC_CONFIG_LM_MASK)\r
+#define ENET_MAC_CONFIG_DM_MASK (0x2000U)\r
+#define ENET_MAC_CONFIG_DM_SHIFT (13U)\r
+/*! DM - Duplex Mode When this bit is set, the MAC operates in a Full-Duplex mode where it can\r
+ * transmit and receive simultaneously.\r
+ */\r
+#define ENET_MAC_CONFIG_DM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DM_SHIFT)) & ENET_MAC_CONFIG_DM_MASK)\r
+#define ENET_MAC_CONFIG_FES_MASK (0x4000U)\r
+#define ENET_MAC_CONFIG_FES_SHIFT (14U)\r
+/*! FES - Speed Indicates the speed in Fast Ethernet (MII) mode: This bit is reserved (RO) by\r
+ * default and is enabled only when RMII/SMII is enabled during configuration.\r
+ */\r
+#define ENET_MAC_CONFIG_FES(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_FES_SHIFT)) & ENET_MAC_CONFIG_FES_MASK)\r
+#define ENET_MAC_CONFIG_PS_MASK (0x8000U)\r
+#define ENET_MAC_CONFIG_PS_SHIFT (15U)\r
+/*! PS - Portselect.\r
+ */\r
+#define ENET_MAC_CONFIG_PS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PS_SHIFT)) & ENET_MAC_CONFIG_PS_MASK)\r
+#define ENET_MAC_CONFIG_JE_MASK (0x10000U)\r
+#define ENET_MAC_CONFIG_JE_SHIFT (16U)\r
+/*! JE - Jumbo Frame Enable When this bit is set, MAC allows Jumbo frames of 9,018 bytes (9,022\r
+ * bytes for tagged frames) without reporting a giant frame error in the receive frame status.\r
+ */\r
+#define ENET_MAC_CONFIG_JE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JE_SHIFT)) & ENET_MAC_CONFIG_JE_MASK)\r
+#define ENET_MAC_CONFIG_JD_MASK (0x20000U)\r
+#define ENET_MAC_CONFIG_JD_SHIFT (17U)\r
+/*! JD - Jabber Disable When this bit is set, the MAC disables the jabber timer on the transmitter,\r
+ * and can transfer frames of up to 16,384 bytes.\r
+ */\r
+#define ENET_MAC_CONFIG_JD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JD_SHIFT)) & ENET_MAC_CONFIG_JD_MASK)\r
+#define ENET_MAC_CONFIG_BE_MASK (0x40000U)\r
+#define ENET_MAC_CONFIG_BE_SHIFT (18U)\r
+/*! BE - Packet Burst Enable When this bit is set, the MAC allows packet bursting during\r
+ * transmission in the MII half-duplex mode.\r
+ */\r
+#define ENET_MAC_CONFIG_BE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BE_SHIFT)) & ENET_MAC_CONFIG_BE_MASK)\r
+#define ENET_MAC_CONFIG_WD_MASK (0x80000U)\r
+#define ENET_MAC_CONFIG_WD_SHIFT (19U)\r
+/*! WD - Watchdog Disable When this bit is set, the MAC disables the watchdog timer on the receiver,\r
+ * and can receive frames of up to 16,384 bytes.\r
+ */\r
+#define ENET_MAC_CONFIG_WD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_WD_SHIFT)) & ENET_MAC_CONFIG_WD_MASK)\r
+#define ENET_MAC_CONFIG_ACS_MASK (0x100000U)\r
+#define ENET_MAC_CONFIG_ACS_SHIFT (20U)\r
+/*! ACS - Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS field\r
+ * on the incoming packets only if the value of the length field is less than 1,536 bytes.\r
+ */\r
+#define ENET_MAC_CONFIG_ACS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ACS_SHIFT)) & ENET_MAC_CONFIG_ACS_MASK)\r
+#define ENET_MAC_CONFIG_CST_MASK (0x200000U)\r
+#define ENET_MAC_CONFIG_CST_SHIFT (21U)\r
+/*! CST - CRC stripping for Type packets When this bit is set, the last four bytes (FCS) of all\r
+ * packets of Ether type (type field greater than 1,536) are stripped and dropped before forwarding\r
+ * the packet to the application.\r
+ */\r
+#define ENET_MAC_CONFIG_CST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_CST_SHIFT)) & ENET_MAC_CONFIG_CST_MASK)\r
+#define ENET_MAC_CONFIG_S2KP_MASK (0x400000U)\r
+#define ENET_MAC_CONFIG_S2KP_SHIFT (22U)\r
+/*! S2KP - IEEE 802.\r
+ */\r
+#define ENET_MAC_CONFIG_S2KP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_S2KP_SHIFT)) & ENET_MAC_CONFIG_S2KP_MASK)\r
+#define ENET_MAC_CONFIG_GPSLCE_MASK (0x800000U)\r
+#define ENET_MAC_CONFIG_GPSLCE_SHIFT (23U)\r
+/*! GPSLCE - Giant Packet Size Limit Control Enable When this bit is set, the MAC considers the\r
+ * value in GPSL field in MAC Ext Configuration register to declare a received packet as Giant packet.\r
+ */\r
+#define ENET_MAC_CONFIG_GPSLCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_GPSLCE_SHIFT)) & ENET_MAC_CONFIG_GPSLCE_MASK)\r
+#define ENET_MAC_CONFIG_IPG_MASK (0x7000000U)\r
+#define ENET_MAC_CONFIG_IPG_SHIFT (24U)\r
+/*! IPG - Inter-Packet Gap These bits control the minimum IPG between packets during transmission.\r
+ */\r
+#define ENET_MAC_CONFIG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPG_SHIFT)) & ENET_MAC_CONFIG_IPG_MASK)\r
+#define ENET_MAC_CONFIG_IPC_MASK (0x8000000U)\r
+#define ENET_MAC_CONFIG_IPC_SHIFT (27U)\r
+/*! IPC - Checksum Offload When set, this bit enables the IPv4 header checksum checking and IPv4 or\r
+ * IPv6 TCP, UDP, or ICMP payload checksum checking.\r
+ */\r
+#define ENET_MAC_CONFIG_IPC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPC_SHIFT)) & ENET_MAC_CONFIG_IPC_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_EXT_CONFIG - */\r
+/*! @{ */\r
+#define ENET_MAC_EXT_CONFIG_GPSL_MASK (0x3FFFU)\r
+#define ENET_MAC_EXT_CONFIG_GPSL_SHIFT (0U)\r
+/*! GPSL - Giant Packet Size Limit If the received packet size is greater than the value programmed\r
+ * in this field in units of bytes, the MAC declares the received packet as Giant packet.\r
+ */\r
+#define ENET_MAC_EXT_CONFIG_GPSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_GPSL_SHIFT)) & ENET_MAC_EXT_CONFIG_GPSL_MASK)\r
+#define ENET_MAC_EXT_CONFIG_DCRCC_MASK (0x10000U)\r
+#define ENET_MAC_EXT_CONFIG_DCRCC_SHIFT (16U)\r
+/*! DCRCC - Disable CRC Checking for Received Packets When this bit is set, the MAC receiver does\r
+ * not check the CRC field in the received packets.\r
+ */\r
+#define ENET_MAC_EXT_CONFIG_DCRCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_DCRCC_SHIFT)) & ENET_MAC_EXT_CONFIG_DCRCC_MASK)\r
+#define ENET_MAC_EXT_CONFIG_SPEN_MASK (0x20000U)\r
+#define ENET_MAC_EXT_CONFIG_SPEN_SHIFT (17U)\r
+/*! SPEN - Slow Protocol Detection Enable When this bit is set, MAC processes the Slow Protocol\r
+ * packets (Ether Type 0x8809) and provides the Rx status.\r
+ */\r
+#define ENET_MAC_EXT_CONFIG_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_SPEN_SHIFT)) & ENET_MAC_EXT_CONFIG_SPEN_MASK)\r
+#define ENET_MAC_EXT_CONFIG_USP_MASK (0x40000U)\r
+#define ENET_MAC_EXT_CONFIG_USP_SHIFT (18U)\r
+/*! USP - Unicast Slow Protocol Packet Detect When this bit is set, the MAC detects the Slow\r
+ * Protocol packets with unicast address of the station specified in the MAC Address High Table 747 and\r
+ * MAC Address Low Table 748 registers.\r
+ */\r
+#define ENET_MAC_EXT_CONFIG_USP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_USP_SHIFT)) & ENET_MAC_EXT_CONFIG_USP_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_FRAME_FILTER - MAC frame filter register */\r
+/*! @{ */\r
+#define ENET_MAC_FRAME_FILTER_PR_MASK (0x1U)\r
+#define ENET_MAC_FRAME_FILTER_PR_SHIFT (0U)\r
+/*! PR - Promiscuous Mode When this bit is set, the Address Filter module passes all incoming frames\r
+ * regardless of its destination or source address.\r
+ */\r
+#define ENET_MAC_FRAME_FILTER_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PR_SHIFT)) & ENET_MAC_FRAME_FILTER_PR_MASK)\r
+#define ENET_MAC_FRAME_FILTER_DAIF_MASK (0x8U)\r
+#define ENET_MAC_FRAME_FILTER_DAIF_SHIFT (3U)\r
+/*! DAIF - DA Inverse Filtering When this bit is set, the Address Check block operates in inverse\r
+ * filtering mode for the DA address comparison for both unicast and multicast frames.\r
+ */\r
+#define ENET_MAC_FRAME_FILTER_DAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_DAIF_MASK)\r
+#define ENET_MAC_FRAME_FILTER_PM_MASK (0x10U)\r
+#define ENET_MAC_FRAME_FILTER_PM_SHIFT (4U)\r
+/*! PM - Pass All Multicast When set, this bit indicates that all received frames with a multicast\r
+ * destination address (first bit in the destination address field is '1') are passed.\r
+ */\r
+#define ENET_MAC_FRAME_FILTER_PM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PM_SHIFT)) & ENET_MAC_FRAME_FILTER_PM_MASK)\r
+#define ENET_MAC_FRAME_FILTER_DBF_MASK (0x20U)\r
+#define ENET_MAC_FRAME_FILTER_DBF_SHIFT (5U)\r
+/*! DBF - Disable Broadcast Frames When this bit is set, the AFM module filters all incoming broadcast frames.\r
+ */\r
+#define ENET_MAC_FRAME_FILTER_DBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DBF_SHIFT)) & ENET_MAC_FRAME_FILTER_DBF_MASK)\r
+#define ENET_MAC_FRAME_FILTER_PCF_MASK (0xC0U)\r
+#define ENET_MAC_FRAME_FILTER_PCF_SHIFT (6U)\r
+/*! PCF - Pass Control Frames These bits control the forwarding of all control frames (including\r
+ * unicast and multicast PAUSE frames).\r
+ */\r
+#define ENET_MAC_FRAME_FILTER_PCF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PCF_SHIFT)) & ENET_MAC_FRAME_FILTER_PCF_MASK)\r
+#define ENET_MAC_FRAME_FILTER_SAIF_MASK (0x100U)\r
+#define ENET_MAC_FRAME_FILTER_SAIF_SHIFT (8U)\r
+/*! SAIF - SA Inverse Filtering When this bit is set, the Address Check block operates in the\r
+ * inverse filtering mode for SA address comparison.\r
+ */\r
+#define ENET_MAC_FRAME_FILTER_SAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAIF_MASK)\r
+#define ENET_MAC_FRAME_FILTER_SAF_MASK (0x200U)\r
+#define ENET_MAC_FRAME_FILTER_SAF_SHIFT (9U)\r
+/*! SAF - Source Address Filter Enable When this bit is set, the MAC compares the SA field of the\r
+ * received packets with the values programmed in the enabled SA registers.\r
+ */\r
+#define ENET_MAC_FRAME_FILTER_SAF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAF_MASK)\r
+#define ENET_MAC_FRAME_FILTER_RA_MASK (0x80000000U)\r
+#define ENET_MAC_FRAME_FILTER_RA_SHIFT (31U)\r
+/*! RA - Receive all When this bit is set, the MAC Receiver module passes to the Application all\r
+ * frames received irrespective of whether they pass the address filter.\r
+ */\r
+#define ENET_MAC_FRAME_FILTER_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_RA_SHIFT)) & ENET_MAC_FRAME_FILTER_RA_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_WD_TIMEROUT - MAC watchdog Timeout register */\r
+/*! @{ */\r
+#define ENET_MAC_WD_TIMEROUT_WTO_MASK (0xFU)\r
+#define ENET_MAC_WD_TIMEROUT_WTO_SHIFT (0U)\r
+/*! WTO - Watchdog Timeout When the PWE bit is set and the WD bit of the MAC Configuration register\r
+ * Table 722 is reset, this field is used as watchdog timeout for a received packet.\r
+ */\r
+#define ENET_MAC_WD_TIMEROUT_WTO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_WTO_SHIFT)) & ENET_MAC_WD_TIMEROUT_WTO_MASK)\r
+#define ENET_MAC_WD_TIMEROUT_PWE_MASK (0x100U)\r
+#define ENET_MAC_WD_TIMEROUT_PWE_SHIFT (8U)\r
+/*! PWE - Programmable Watchdog Enable When this bit is set and the WD bit of the MAC Configuration\r
+ * register Table 722 is reset, the WTO field is used as watchdog timeout for a received packet.\r
+ */\r
+#define ENET_MAC_WD_TIMEROUT_PWE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_PWE_SHIFT)) & ENET_MAC_WD_TIMEROUT_PWE_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_VLAN_TAG - MAC vlan tag register */\r
+/*! @{ */\r
+#define ENET_MAC_VLAN_TAG_VL_MASK (0xFFFFU)\r
+#define ENET_MAC_VLAN_TAG_VL_SHIFT (0U)\r
+/*! VL - VLAN Tag Identifier for Receive Packets.\r
+ */\r
+#define ENET_MAC_VLAN_TAG_VL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VL_SHIFT)) & ENET_MAC_VLAN_TAG_VL_MASK)\r
+#define ENET_MAC_VLAN_TAG_ETV_MASK (0x10000U)\r
+#define ENET_MAC_VLAN_TAG_ETV_SHIFT (16U)\r
+/*! ETV - Enable 12-Bit VLAN Tag Comparison.\r
+ */\r
+#define ENET_MAC_VLAN_TAG_ETV(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ETV_SHIFT)) & ENET_MAC_VLAN_TAG_ETV_MASK)\r
+#define ENET_MAC_VLAN_TAG_VTIM_MASK (0x20000U)\r
+#define ENET_MAC_VLAN_TAG_VTIM_SHIFT (17U)\r
+/*! VTIM - VLAN Tag Inverse Match Enable.\r
+ */\r
+#define ENET_MAC_VLAN_TAG_VTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTIM_SHIFT)) & ENET_MAC_VLAN_TAG_VTIM_MASK)\r
+#define ENET_MAC_VLAN_TAG_ESVL_MASK (0x40000U)\r
+#define ENET_MAC_VLAN_TAG_ESVL_SHIFT (18U)\r
+/*! ESVL - Enable S-VLAN.\r
+ */\r
+#define ENET_MAC_VLAN_TAG_ESVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ESVL_SHIFT)) & ENET_MAC_VLAN_TAG_ESVL_MASK)\r
+#define ENET_MAC_VLAN_TAG_ERSVLM_MASK (0x80000U)\r
+#define ENET_MAC_VLAN_TAG_ERSVLM_SHIFT (19U)\r
+/*! ERSVLM - Enable Receive S-VLAN Match.\r
+ */\r
+#define ENET_MAC_VLAN_TAG_ERSVLM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERSVLM_SHIFT)) & ENET_MAC_VLAN_TAG_ERSVLM_MASK)\r
+#define ENET_MAC_VLAN_TAG_DOVLTC_MASK (0x100000U)\r
+#define ENET_MAC_VLAN_TAG_DOVLTC_SHIFT (20U)\r
+/*! DOVLTC - Disable VLAN Type Check.\r
+ */\r
+#define ENET_MAC_VLAN_TAG_DOVLTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_DOVLTC_SHIFT)) & ENET_MAC_VLAN_TAG_DOVLTC_MASK)\r
+#define ENET_MAC_VLAN_TAG_EVLS_MASK (0x600000U)\r
+#define ENET_MAC_VLAN_TAG_EVLS_SHIFT (21U)\r
+/*! EVLS - Enable VLAN Tag Stripping on Receive.\r
+ */\r
+#define ENET_MAC_VLAN_TAG_EVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLS_MASK)\r
+#define ENET_MAC_VLAN_TAG_EVLRXS_MASK (0x1000000U)\r
+#define ENET_MAC_VLAN_TAG_EVLRXS_SHIFT (24U)\r
+/*! EVLRXS - Enable VLAN Tag in Rx status.\r
+ */\r
+#define ENET_MAC_VLAN_TAG_EVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLRXS_MASK)\r
+#define ENET_MAC_VLAN_TAG_VTHM_MASK (0x2000000U)\r
+#define ENET_MAC_VLAN_TAG_VTHM_SHIFT (25U)\r
+/*! VTHM - Disable VLAN Type Check.\r
+ */\r
+#define ENET_MAC_VLAN_TAG_VTHM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTHM_SHIFT)) & ENET_MAC_VLAN_TAG_VTHM_MASK)\r
+#define ENET_MAC_VLAN_TAG_EDVLP_MASK (0x4000000U)\r
+#define ENET_MAC_VLAN_TAG_EDVLP_SHIFT (26U)\r
+/*! EDVLP - Enable Double VLAN Processing.\r
+ */\r
+#define ENET_MAC_VLAN_TAG_EDVLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EDVLP_SHIFT)) & ENET_MAC_VLAN_TAG_EDVLP_MASK)\r
+#define ENET_MAC_VLAN_TAG_ERIVLT_MASK (0x8000000U)\r
+#define ENET_MAC_VLAN_TAG_ERIVLT_SHIFT (27U)\r
+/*! ERIVLT - Enable Inner VLAN Tag.\r
+ */\r
+#define ENET_MAC_VLAN_TAG_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERIVLT_SHIFT)) & ENET_MAC_VLAN_TAG_ERIVLT_MASK)\r
+#define ENET_MAC_VLAN_TAG_EIVLS_MASK (0x30000000U)\r
+#define ENET_MAC_VLAN_TAG_EIVLS_SHIFT (28U)\r
+/*! EIVLS - Enable Inner VLAN Tag Stripping on Receive.\r
+ */\r
+#define ENET_MAC_VLAN_TAG_EIVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLS_MASK)\r
+#define ENET_MAC_VLAN_TAG_EIVLRXS_MASK (0x80000000U)\r
+#define ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT (31U)\r
+/*! EIVLRXS - Enable Inner VLAN Tag in Rx Status.\r
+ */\r
+#define ENET_MAC_VLAN_TAG_EIVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLRXS_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_TX_FLOW_CTRL_Q - Transmit flow control register */\r
+/*! @{ */\r
+#define ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK (0x1U)\r
+#define ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT (0U)\r
+/*! FCB - Flow Control Busy/Backpressure Activate This register field can be read by the application\r
+ * (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is\r
+ * cleared to 0 by the core (Self Clear).\r
+ */\r
+#define ENET_MAC_TX_FLOW_CTRL_Q_FCB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK)\r
+#define ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK (0x2U)\r
+#define ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT (1U)\r
+/*! TFE - Transmit Flow Control Enable In Full-Duplex mode, when this bit is set, the MAC enables\r
+ * the flow control operation to transmit Pause frames.\r
+ */\r
+#define ENET_MAC_TX_FLOW_CTRL_Q_TFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK)\r
+#define ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK (0x70U)\r
+#define ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT (4U)\r
+/*! PLT - Pause Low Threshold This field configures the threshold of the PAUSE timer at which the\r
+ * input flow control signal is checked for automatic retransmission of PAUSE Frame.\r
+ */\r
+#define ENET_MAC_TX_FLOW_CTRL_Q_PLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK)\r
+#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK (0x80U)\r
+#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT (7U)\r
+/*! DZPQ - Disable Zero-Quanta Pause When set, this bit disables the automatic generation of\r
+ * Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer.\r
+ */\r
+#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK)\r
+#define ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK (0xFFFF0000U)\r
+#define ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT (16U)\r
+/*! PT - Pause time This field holds the value to be used in the Pause Time field in the transmit control frame.\r
+ */\r
+#define ENET_MAC_TX_FLOW_CTRL_Q_PT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_MAC_TX_FLOW_CTRL_Q */\r
+#define ENET_MAC_TX_FLOW_CTRL_Q_COUNT (2U)\r
+\r
+/*! @name MAC_RX_FLOW_CTRL - Receive flow control register */\r
+/*! @{ */\r
+#define ENET_MAC_RX_FLOW_CTRL_RFE_MASK (0x1U)\r
+#define ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT (0U)\r
+/*! RFE - Receive Flow Control Enable When this bit is set and the MAC is operating in full-duplex\r
+ * mode, the MAC decodes the received Pause packet and disables its transmitter for a specified\r
+ * (Pause) time.\r
+ */\r
+#define ENET_MAC_RX_FLOW_CTRL_RFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_RFE_MASK)\r
+#define ENET_MAC_RX_FLOW_CTRL_UP_MASK (0x2U)\r
+#define ENET_MAC_RX_FLOW_CTRL_UP_SHIFT (1U)\r
+/*! UP - Unicast Pause Packet Detect A pause packet is processed when it has the unique multicast\r
+ * address specified in the IEEE 802.\r
+ */\r
+#define ENET_MAC_RX_FLOW_CTRL_UP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_UP_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_TXQ_PRIO_MAP - */\r
+/*! @{ */\r
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK (0xFFU)\r
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT (0U)\r
+/*! PSTQ0 - Priorities Selected in Transmit Queue 0 This field holds the priorities assigned to Tx Queue 0 by the software.\r
+ */\r
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK)\r
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK (0xFF00U)\r
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT (8U)\r
+/*! PSTQ1 - Priorities Selected in Transmit Queue 1 This bit is similar to the PSTQ0 bit.\r
+ */\r
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_RXQ_CTRL - Receive Queue Control 0 register 0x0000 */\r
+/*! @{ */\r
+#define ENET_MAC_RXQ_CTRL_AVCPQ_MASK (0x7U)\r
+#define ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT (0U)\r
+/*! AVCPQ - AV Untagged Control Packets Queue.\r
+ */\r
+#define ENET_MAC_RXQ_CTRL_AVCPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVCPQ_MASK)\r
+#define ENET_MAC_RXQ_CTRL_PSRQ0_MASK (0xFFU)\r
+#define ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT (0U)\r
+/*! PSRQ0 - Priorities Selected in the Receive Queue 0.\r
+ */\r
+#define ENET_MAC_RXQ_CTRL_PSRQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ0_MASK)\r
+#define ENET_MAC_RXQ_CTRL_RXQ0EN_MASK (0x3U)\r
+#define ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT (0U)\r
+/*! RXQ0EN - Receive Queue 0 Enable.\r
+ */\r
+#define ENET_MAC_RXQ_CTRL_RXQ0EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ0EN_MASK)\r
+#define ENET_MAC_RXQ_CTRL_RXQ1EN_MASK (0xCU)\r
+#define ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT (2U)\r
+/*! RXQ1EN - Receive Queue 1 Enable.\r
+ */\r
+#define ENET_MAC_RXQ_CTRL_RXQ1EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ1EN_MASK)\r
+#define ENET_MAC_RXQ_CTRL_AVPTPQ_MASK (0x70U)\r
+#define ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT (4U)\r
+/*! AVPTPQ - AV PTP Packets Queue.\r
+ */\r
+#define ENET_MAC_RXQ_CTRL_AVPTPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVPTPQ_MASK)\r
+#define ENET_MAC_RXQ_CTRL_PSRQ1_MASK (0xFF00U)\r
+#define ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT (8U)\r
+/*! PSRQ1 - Priorities Selected in the Receive Queue 1.\r
+ */\r
+#define ENET_MAC_RXQ_CTRL_PSRQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ1_MASK)\r
+#define ENET_MAC_RXQ_CTRL_UPQ_MASK (0x7000U)\r
+#define ENET_MAC_RXQ_CTRL_UPQ_SHIFT (12U)\r
+/*! UPQ - Untagged Packet Queue.\r
+ */\r
+#define ENET_MAC_RXQ_CTRL_UPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_UPQ_MASK)\r
+#define ENET_MAC_RXQ_CTRL_MCBCQ_MASK (0x70000U)\r
+#define ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT (16U)\r
+/*! MCBCQ - Multicast and Broadcast Queue.\r
+ */\r
+#define ENET_MAC_RXQ_CTRL_MCBCQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQ_MASK)\r
+#define ENET_MAC_RXQ_CTRL_PSRQ2_MASK (0xFF0000U)\r
+#define ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT (16U)\r
+/*! PSRQ2 - Priorities Selected in the Receive Queue 2.\r
+ */\r
+#define ENET_MAC_RXQ_CTRL_PSRQ2(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ2_MASK)\r
+#define ENET_MAC_RXQ_CTRL_MCBCQEN_MASK (0x100000U)\r
+#define ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT (20U)\r
+/*! MCBCQEN - Multicast and Broadcast Queue Enable.\r
+ */\r
+#define ENET_MAC_RXQ_CTRL_MCBCQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQEN_MASK)\r
+#define ENET_MAC_RXQ_CTRL_PSRQ3_MASK (0xFF000000U)\r
+#define ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT (24U)\r
+/*! PSRQ3 - Priorities Selected in the Receive Queue 3.\r
+ */\r
+#define ENET_MAC_RXQ_CTRL_PSRQ3(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ3_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_MAC_RXQ_CTRL */\r
+#define ENET_MAC_RXQ_CTRL_COUNT (3U)\r
+\r
+/*! @name MAC_INTR_STAT - Interrupt status register 0x0000 */\r
+/*! @{ */\r
+#define ENET_MAC_INTR_STAT_PHYIS_MASK (0x8U)\r
+#define ENET_MAC_INTR_STAT_PHYIS_SHIFT (3U)\r
+/*! PHYIS - PHY Interrupt.\r
+ */\r
+#define ENET_MAC_INTR_STAT_PHYIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PHYIS_SHIFT)) & ENET_MAC_INTR_STAT_PHYIS_MASK)\r
+#define ENET_MAC_INTR_STAT_PMTIS_MASK (0x10U)\r
+#define ENET_MAC_INTR_STAT_PMTIS_SHIFT (4U)\r
+/*! PMTIS - PMT Interrupt Status.\r
+ */\r
+#define ENET_MAC_INTR_STAT_PMTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PMTIS_SHIFT)) & ENET_MAC_INTR_STAT_PMTIS_MASK)\r
+#define ENET_MAC_INTR_STAT_LPIIS_MASK (0x20U)\r
+#define ENET_MAC_INTR_STAT_LPIIS_SHIFT (5U)\r
+/*! LPIIS - LPI Interrupt Status.\r
+ */\r
+#define ENET_MAC_INTR_STAT_LPIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_LPIIS_SHIFT)) & ENET_MAC_INTR_STAT_LPIIS_MASK)\r
+#define ENET_MAC_INTR_STAT_TSIS_MASK (0x1000U)\r
+#define ENET_MAC_INTR_STAT_TSIS_SHIFT (12U)\r
+/*! TSIS - Timestamp interrupt status.\r
+ */\r
+#define ENET_MAC_INTR_STAT_TSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TSIS_SHIFT)) & ENET_MAC_INTR_STAT_TSIS_MASK)\r
+#define ENET_MAC_INTR_STAT_TXSTSIS_MASK (0x2000U)\r
+#define ENET_MAC_INTR_STAT_TXSTSIS_SHIFT (13U)\r
+/*! TXSTSIS - Transmit Status Interrupt.\r
+ */\r
+#define ENET_MAC_INTR_STAT_TXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_TXSTSIS_MASK)\r
+#define ENET_MAC_INTR_STAT_RXSTSIS_MASK (0x4000U)\r
+#define ENET_MAC_INTR_STAT_RXSTSIS_SHIFT (14U)\r
+/*! RXSTSIS - Receive Status Interrupt.\r
+ */\r
+#define ENET_MAC_INTR_STAT_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_RXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_RXSTSIS_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_INTR_EN - Interrupt enable register 0x0000 */\r
+/*! @{ */\r
+#define ENET_MAC_INTR_EN_PHYIE_MASK (0x8U)\r
+#define ENET_MAC_INTR_EN_PHYIE_SHIFT (3U)\r
+/*! PHYIE - PHY Interrupt Enable.\r
+ */\r
+#define ENET_MAC_INTR_EN_PHYIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PHYIE_SHIFT)) & ENET_MAC_INTR_EN_PHYIE_MASK)\r
+#define ENET_MAC_INTR_EN_PMTIE_MASK (0x10U)\r
+#define ENET_MAC_INTR_EN_PMTIE_SHIFT (4U)\r
+/*! PMTIE - PMT Interrupt Enable.\r
+ */\r
+#define ENET_MAC_INTR_EN_PMTIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PMTIE_SHIFT)) & ENET_MAC_INTR_EN_PMTIE_MASK)\r
+#define ENET_MAC_INTR_EN_LPIIE_MASK (0x20U)\r
+#define ENET_MAC_INTR_EN_LPIIE_SHIFT (5U)\r
+/*! LPIIE - LPI Interrupt Enable.\r
+ */\r
+#define ENET_MAC_INTR_EN_LPIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_LPIIE_SHIFT)) & ENET_MAC_INTR_EN_LPIIE_MASK)\r
+#define ENET_MAC_INTR_EN_TSIE_MASK (0x1000U)\r
+#define ENET_MAC_INTR_EN_TSIE_SHIFT (12U)\r
+/*! TSIE - Timestamp Interrupt Enable.\r
+ */\r
+#define ENET_MAC_INTR_EN_TSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TSIE_SHIFT)) & ENET_MAC_INTR_EN_TSIE_MASK)\r
+#define ENET_MAC_INTR_EN_TXSTSIE_MASK (0x2000U)\r
+#define ENET_MAC_INTR_EN_TXSTSIE_SHIFT (13U)\r
+/*! TXSTSIE - Transmit Status Interrupt Enable.\r
+ */\r
+#define ENET_MAC_INTR_EN_TXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TXSTSIE_SHIFT)) & ENET_MAC_INTR_EN_TXSTSIE_MASK)\r
+#define ENET_MAC_INTR_EN_RXSTSIS_MASK (0x4000U)\r
+#define ENET_MAC_INTR_EN_RXSTSIS_SHIFT (14U)\r
+/*! RXSTSIS - Receive Status Interrupt Enable.\r
+ */\r
+#define ENET_MAC_INTR_EN_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_RXSTSIS_SHIFT)) & ENET_MAC_INTR_EN_RXSTSIS_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_RXTX_STAT - Receive Transmit Status register */\r
+/*! @{ */\r
+#define ENET_MAC_RXTX_STAT_TJT_MASK (0x1U)\r
+#define ENET_MAC_RXTX_STAT_TJT_SHIFT (0U)\r
+/*! TJT - PHY Interrupt Enable When this bit is set, it enables the assertion of the interrupt\r
+ * signal because of the setting of PHYIS bit in MAC Interrupt Status register Table 731.\r
+ */\r
+#define ENET_MAC_RXTX_STAT_TJT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_TJT_SHIFT)) & ENET_MAC_RXTX_STAT_TJT_MASK)\r
+#define ENET_MAC_RXTX_STAT_NCARR_MASK (0x2U)\r
+#define ENET_MAC_RXTX_STAT_NCARR_SHIFT (1U)\r
+/*! NCARR - No Carrier When the DTXSTS bit is set in the MTL Operation Mode register Table 758, this\r
+ * bit indicates that the carrier signal from the PHY is not present at the end of preamble\r
+ * transmission.\r
+ */\r
+#define ENET_MAC_RXTX_STAT_NCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_NCARR_SHIFT)) & ENET_MAC_RXTX_STAT_NCARR_MASK)\r
+#define ENET_MAC_RXTX_STAT_LCARR_MASK (0x4U)\r
+#define ENET_MAC_RXTX_STAT_LCARR_SHIFT (2U)\r
+/*! LCARR - Loss of Carrier When the DTXSTS bit is set in the MTL Operation Mode register Table 758,\r
+ * this bit indicates that the loss of carrier occurred during packet transmission, that is, the\r
+ * PHY Carrier signal was inactive for one or more transmission clock periods during packet\r
+ * transmission.\r
+ */\r
+#define ENET_MAC_RXTX_STAT_LCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCARR_SHIFT)) & ENET_MAC_RXTX_STAT_LCARR_MASK)\r
+#define ENET_MAC_RXTX_STAT_EXDEF_MASK (0x8U)\r
+#define ENET_MAC_RXTX_STAT_EXDEF_SHIFT (3U)\r
+/*! EXDEF - Excessive Deferral When the DTXSTS bit is set in the MTL Operation Mode register Table\r
+ * 758 and the DC bit is set in the MAC Configuration register Table 758, this bit indicates that\r
+ * the transmission ended because of excessive deferral of over 24,288 bit times (155,680 when\r
+ * Jumbo packet is enabled).\r
+ */\r
+#define ENET_MAC_RXTX_STAT_EXDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXDEF_SHIFT)) & ENET_MAC_RXTX_STAT_EXDEF_MASK)\r
+#define ENET_MAC_RXTX_STAT_LCOL_MASK (0x10U)\r
+#define ENET_MAC_RXTX_STAT_LCOL_SHIFT (4U)\r
+/*! LCOL - Late Collision When the DTXSTS bit is set in the MTL Operation Mode register Table 758,\r
+ * this bit indicates that the packet transmission aborted because a collision occurred after the\r
+ * collision window (64 bytes including Preamble in MII mode).\r
+ */\r
+#define ENET_MAC_RXTX_STAT_LCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCOL_SHIFT)) & ENET_MAC_RXTX_STAT_LCOL_MASK)\r
+#define ENET_MAC_RXTX_STAT_EXCOL_MASK (0x20U)\r
+#define ENET_MAC_RXTX_STAT_EXCOL_SHIFT (5U)\r
+/*! EXCOL - Excessive Collisions When the DTXSTS bit is set in the MTL Operation Mode register Table\r
+ * 758, this bit indicates that the transmission aborted after 16 successive collisions while\r
+ * attempting to transmit the current packet.\r
+ */\r
+#define ENET_MAC_RXTX_STAT_EXCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXCOL_SHIFT)) & ENET_MAC_RXTX_STAT_EXCOL_MASK)\r
+#define ENET_MAC_RXTX_STAT_RWT_MASK (0x100U)\r
+#define ENET_MAC_RXTX_STAT_RWT_SHIFT (8U)\r
+/*! RWT - Receive Watchdog Timeout This bit is set when a packet with length greater than 2,048\r
+ * bytes is received (10,240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the\r
+ * MAC Configuration register Table 722.\r
+ */\r
+#define ENET_MAC_RXTX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_RWT_SHIFT)) & ENET_MAC_RXTX_STAT_RWT_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_PMT_CRTL_STAT - */\r
+/*! @{ */\r
+#define ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK (0x1U)\r
+#define ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT (0U)\r
+/*! PWRDWN - Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has\r
+ * entered the LPI state because of the setting of the LPIEN bit.\r
+ */\r
+#define ENET_MAC_PMT_CRTL_STAT_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK)\r
+#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK (0x2U)\r
+#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT (1U)\r
+/*! MGKPKTEN - Magic Packet Enable.\r
+ */\r
+#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK)\r
+#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK (0x4U)\r
+#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT (2U)\r
+/*! RWKPKTEN - Remote Wake-Up Packet Enable When this bit is set, a power management event is\r
+ * generated when the MAC receives a remote wake-up packet.\r
+ */\r
+#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK)\r
+#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK (0x20U)\r
+#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT (5U)\r
+/*! MGKPRCVD - Magic Packet Received.\r
+ */\r
+#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK)\r
+#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK (0x40U)\r
+#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT (6U)\r
+/*! RWKPRCVD - Remote Wake-Up Packet Received.\r
+ */\r
+#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK)\r
+#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK (0x200U)\r
+#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT (9U)\r
+/*! GLBLUCAST - Global Unicast When this bit set, any unicast packet filtered by the MAC (DAF)\r
+ * address recognition is detected as a remote wake-up packet.\r
+ */\r
+#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK)\r
+#define ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK (0x400U)\r
+#define ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT (10U)\r
+/*! RWKPFE - Remote Wake-up Packet Forwarding Enable When this bit is set along with RWKPKTEN, the\r
+ * MAC receiver drops all received frames until it receives the expected wake-up frame.\r
+ */\r
+#define ENET_MAC_PMT_CRTL_STAT_RWKPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK)\r
+#define ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK (0x1F000000U)\r
+#define ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT (24U)\r
+/*! RWKPTR - Remote Wake-up FIFO Pointer This field gives the current value (0 to 7) of the Remote\r
+ * Wake-up Packet Filter register pointer.\r
+ */\r
+#define ENET_MAC_PMT_CRTL_STAT_RWKPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK)\r
+#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK (0x80000000U)\r
+#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT (31U)\r
+/*! RWKFILTRST - Remote Wake-Up Packet Filter Register Pointer Reset When this bit is set, the\r
+ * remote wake-up packet filter register pointer is reset to 3'b000.\r
+ */\r
+#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_RWAKE_FRFLT - Remote wake-up frame filter */\r
+/*! @{ */\r
+#define ENET_MAC_RWAKE_FRFLT_ADDR_MASK (0xFFFFFFFFU)\r
+#define ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT (0U)\r
+/*! ADDR - WKUPFMFILTER address.\r
+ */\r
+#define ENET_MAC_RWAKE_FRFLT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT)) & ENET_MAC_RWAKE_FRFLT_ADDR_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_LPI_CTRL_STAT - LPI Control and Status Register */\r
+/*! @{ */\r
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK (0x1U)\r
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT (0U)\r
+/*! TLPIEN - Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has\r
+ * entered the LPI state because of the setting of the LPIEN bit.\r
+ */\r
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK)\r
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK (0x2U)\r
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT (1U)\r
+/*! TLPIEX - Transmit LPI Exit When this bit is set, it indicates that the MAC transmitter exited\r
+ * the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired.\r
+ */\r
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK)\r
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK (0x4U)\r
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT (2U)\r
+/*! RLPIEN - Receive LPI Entry When this bit is set, it indicates that the MAC Receiver has received\r
+ * an LPI pattern and entered the LPI state.\r
+ */\r
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK)\r
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK (0x8U)\r
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT (3U)\r
+/*! RLPIEX - Receive LPI Exit When this bit is set, it indicates that the MAC Receiver has stopped\r
+ * receiving the LPI pattern on the MII interface, exited the LPI state, and resumed the normal\r
+ * reception.\r
+ */\r
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK)\r
+#define ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK (0x100U)\r
+#define ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT (8U)\r
+/*! TLPIST - Transmit LPI State When this bit is set, it indicates that the MAC is transmitting the LPI pattern on the MII interface.\r
+ */\r
+#define ENET_MAC_LPI_CTRL_STAT_TLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK)\r
+#define ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK (0x200U)\r
+#define ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT (9U)\r
+/*! RLPIST - Receive LPI State When this bit is set, it indicates that the MAC is receiving the LPI pattern on the MII interface.\r
+ */\r
+#define ENET_MAC_LPI_CTRL_STAT_RLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK)\r
+#define ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK (0x10000U)\r
+#define ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT (16U)\r
+/*! LPIEN - LPI Enable When this bit is set, it instructs the MAC Transmitter to enter the LPI state.\r
+ */\r
+#define ENET_MAC_LPI_CTRL_STAT_LPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK)\r
+#define ENET_MAC_LPI_CTRL_STAT_PLS_MASK (0x20000U)\r
+#define ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT (17U)\r
+/*! PLS - PHY Link Status This bit indicates the link status of the PHY.\r
+ */\r
+#define ENET_MAC_LPI_CTRL_STAT_PLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_PLS_MASK)\r
+#define ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK (0x80000U)\r
+#define ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT (19U)\r
+/*! LPITXA - LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming\r
+ * out of the LPI mode on the Transmit side.\r
+ */\r
+#define ENET_MAC_LPI_CTRL_STAT_LPITXA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK)\r
+#define ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK (0x100000U)\r
+#define ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT (20U)\r
+/*! LPIATE - LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state.\r
+ */\r
+#define ENET_MAC_LPI_CTRL_STAT_LPIATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK)\r
+#define ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK (0x200000U)\r
+#define ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT (21U)\r
+/*! LPITCSE - LPI Tx Clock Stop Enable When this bit is set, the MAC asserts LPI Tx Clock Gating\r
+ * Control signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be\r
+ * stopped.\r
+ */\r
+#define ENET_MAC_LPI_CTRL_STAT_LPITCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_LPI_TIMER_CTRL - LPI Timers Control register */\r
+/*! @{ */\r
+#define ENET_MAC_LPI_TIMER_CTRL_TWT_MASK (0xFFFFU)\r
+#define ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT (0U)\r
+/*! TWT - LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC\r
+ * waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal\r
+ * transmission.\r
+ */\r
+#define ENET_MAC_LPI_TIMER_CTRL_TWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_TWT_MASK)\r
+#define ENET_MAC_LPI_TIMER_CTRL_LST_MASK (0x3FF0000U)\r
+#define ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT (16U)\r
+/*! LST - LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link\r
+ * status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY.\r
+ */\r
+#define ENET_MAC_LPI_TIMER_CTRL_LST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_LST_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_LPI_ENTR_TIMR - LPI entry Timer register */\r
+/*! @{ */\r
+#define ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK (0xFFFF8U)\r
+#define ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT (3U)\r
+/*! LPIET - LPI Entry Timer This field specifies the time in microseconds the MAC will wait to enter\r
+ * LPI mode, after it has transmitted all the frames.\r
+ */\r
+#define ENET_MAC_LPI_ENTR_TIMR_LPIET(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT)) & ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_1US_TIC_COUNTR - */\r
+/*! @{ */\r
+#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK (0xFFFU)\r
+#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT (0U)\r
+/*! TIC_1US_CNTR - 1US TIC Counter The application must program this counter so that the number of clock cycles of CSR clock is 1us.\r
+ */\r
+#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT)) & ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_VERSION - MAC version register */\r
+/*! @{ */\r
+#define ENET_MAC_VERSION_SNPVER_MASK (0xFFU)\r
+#define ENET_MAC_VERSION_SNPVER_SHIFT (0U)\r
+/*! SNPVER - NXP defined version.\r
+ */\r
+#define ENET_MAC_VERSION_SNPVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_SNPVER_SHIFT)) & ENET_MAC_VERSION_SNPVER_MASK)\r
+#define ENET_MAC_VERSION_USERVER_MASK (0xFF00U)\r
+#define ENET_MAC_VERSION_USERVER_SHIFT (8U)\r
+/*! USERVER - User defined version.\r
+ */\r
+#define ENET_MAC_VERSION_USERVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_USERVER_SHIFT)) & ENET_MAC_VERSION_USERVER_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_DBG - MAC debug register */\r
+/*! @{ */\r
+#define ENET_MAC_DBG_REPESTS_MASK (0x1U)\r
+#define ENET_MAC_DBG_REPESTS_SHIFT (0U)\r
+/*! REPESTS - MAC MII Receive Protocol Engine Status When this bit is set, it indicates that the MAC\r
+ * MII receive protocol engine is actively receiving data, and it is not in the Idle state.\r
+ */\r
+#define ENET_MAC_DBG_REPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_REPESTS_SHIFT)) & ENET_MAC_DBG_REPESTS_MASK)\r
+#define ENET_MAC_DBG_RFCFCSTS_MASK (0x6U)\r
+#define ENET_MAC_DBG_RFCFCSTS_SHIFT (1U)\r
+/*! RFCFCSTS - MAC Receive Packet Controller FIFO Status When this bit is set, this field indicates\r
+ * the active state of the small FIFO Read and Write controllers of the MAC Receive Packet\r
+ * Controller module.\r
+ */\r
+#define ENET_MAC_DBG_RFCFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_RFCFCSTS_SHIFT)) & ENET_MAC_DBG_RFCFCSTS_MASK)\r
+#define ENET_MAC_DBG_TPESTS_MASK (0x10000U)\r
+#define ENET_MAC_DBG_TPESTS_SHIFT (16U)\r
+/*! TPESTS - MAC MII Transmit Protocol Engine Status When this bit is set, it indicates that the MAC\r
+ * or MII transmit protocol engine is actively transmitting data, and it is not in the Idle\r
+ * state.\r
+ */\r
+#define ENET_MAC_DBG_TPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TPESTS_SHIFT)) & ENET_MAC_DBG_TPESTS_MASK)\r
+#define ENET_MAC_DBG_TFCSTS_MASK (0x60000U)\r
+#define ENET_MAC_DBG_TFCSTS_SHIFT (17U)\r
+/*! TFCSTS - MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module.\r
+ */\r
+#define ENET_MAC_DBG_TFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TFCSTS_SHIFT)) & ENET_MAC_DBG_TFCSTS_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_HW_FEAT - MAC hardware feature register 0x0201 */\r
+/*! @{ */\r
+#define ENET_MAC_HW_FEAT_MIISEL_MASK (0x1U)\r
+#define ENET_MAC_HW_FEAT_MIISEL_SHIFT (0U)\r
+/*! MIISEL - 10 or 100 Mbps Support.\r
+ */\r
+#define ENET_MAC_HW_FEAT_MIISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_MAC_HW_FEAT_MIISEL_MASK)\r
+#define ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK (0x1FU)\r
+#define ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT (0U)\r
+/*! RXFIFOSIZE - MTL Receive FIFO Size.\r
+ */\r
+#define ENET_MAC_HW_FEAT_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK)\r
+#define ENET_MAC_HW_FEAT_RXQCNT_MASK (0xFU)\r
+#define ENET_MAC_HW_FEAT_RXQCNT_SHIFT (0U)\r
+/*! RXQCNT - Number of MTL Receive Queues.\r
+ */\r
+#define ENET_MAC_HW_FEAT_RXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXQCNT_MASK)\r
+#define ENET_MAC_HW_FEAT_HDSEL_MASK (0x4U)\r
+#define ENET_MAC_HW_FEAT_HDSEL_SHIFT (2U)\r
+/*! HDSEL - Half-duplex Support.\r
+ */\r
+#define ENET_MAC_HW_FEAT_HDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_MAC_HW_FEAT_HDSEL_MASK)\r
+#define ENET_MAC_HW_FEAT_VLHASH_MASK (0x10U)\r
+#define ENET_MAC_HW_FEAT_VLHASH_SHIFT (4U)\r
+/*! VLHASH - Hash Table Based Filtering option.\r
+ */\r
+#define ENET_MAC_HW_FEAT_VLHASH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_MAC_HW_FEAT_VLHASH_MASK)\r
+#define ENET_MAC_HW_FEAT_SMASEL_MASK (0x20U)\r
+#define ENET_MAC_HW_FEAT_SMASEL_SHIFT (5U)\r
+/*! SMASEL - SMA (MDIO) Interface.\r
+ */\r
+#define ENET_MAC_HW_FEAT_SMASEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_MAC_HW_FEAT_SMASEL_MASK)\r
+#define ENET_MAC_HW_FEAT_RWKSEL_MASK (0x40U)\r
+#define ENET_MAC_HW_FEAT_RWKSEL_SHIFT (6U)\r
+/*! RWKSEL - PMT Remote Wake-up Packet Detection.\r
+ */\r
+#define ENET_MAC_HW_FEAT_RWKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_MAC_HW_FEAT_RWKSEL_MASK)\r
+#define ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK (0x7C0U)\r
+#define ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT (6U)\r
+/*! TXFIFOSIZE - MTL Transmit FIFO Size.\r
+ */\r
+#define ENET_MAC_HW_FEAT_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK)\r
+#define ENET_MAC_HW_FEAT_TXQCNT_MASK (0x3C0U)\r
+#define ENET_MAC_HW_FEAT_TXQCNT_SHIFT (6U)\r
+/*! TXQCNT - Number of MTL Transmit Queues.\r
+ */\r
+#define ENET_MAC_HW_FEAT_TXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXQCNT_MASK)\r
+#define ENET_MAC_HW_FEAT_MGKSEL_MASK (0x80U)\r
+#define ENET_MAC_HW_FEAT_MGKSEL_SHIFT (7U)\r
+/*! MGKSEL - PMT magic packet detection.\r
+ */\r
+#define ENET_MAC_HW_FEAT_MGKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_MAC_HW_FEAT_MGKSEL_MASK)\r
+#define ENET_MAC_HW_FEAT_MMCSEL_MASK (0x100U)\r
+#define ENET_MAC_HW_FEAT_MMCSEL_SHIFT (8U)\r
+/*! MMCSEL - RMON Module Enable.\r
+ */\r
+#define ENET_MAC_HW_FEAT_MMCSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_MAC_HW_FEAT_MMCSEL_MASK)\r
+#define ENET_MAC_HW_FEAT_ARPOFFSEL_MASK (0x200U)\r
+#define ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT (9U)\r
+/*! ARPOFFSEL - ARP Offload Enabled.\r
+ */\r
+#define ENET_MAC_HW_FEAT_ARPOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_MAC_HW_FEAT_ARPOFFSEL_MASK)\r
+#define ENET_MAC_HW_FEAT_OSTEN_MASK (0x800U)\r
+#define ENET_MAC_HW_FEAT_OSTEN_SHIFT (11U)\r
+/*! OSTEN - One-Step Timestamping Feature.\r
+ */\r
+#define ENET_MAC_HW_FEAT_OSTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_MAC_HW_FEAT_OSTEN_MASK)\r
+#define ENET_MAC_HW_FEAT_PTOEN_MASK (0x1000U)\r
+#define ENET_MAC_HW_FEAT_PTOEN_SHIFT (12U)\r
+/*! PTOEN - PTP OffLoad Feature.\r
+ */\r
+#define ENET_MAC_HW_FEAT_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_MAC_HW_FEAT_PTOEN_MASK)\r
+#define ENET_MAC_HW_FEAT_RXCHCNT_MASK (0xF000U)\r
+#define ENET_MAC_HW_FEAT_RXCHCNT_SHIFT (12U)\r
+/*! RXCHCNT - Number of DMA Receive Channels.\r
+ */\r
+#define ENET_MAC_HW_FEAT_RXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXCHCNT_MASK)\r
+#define ENET_MAC_HW_FEAT_TSSEL_MASK (0x1000U)\r
+#define ENET_MAC_HW_FEAT_TSSEL_SHIFT (12U)\r
+/*! TSSEL - IEEE 1588-2008 Timestamp support .\r
+ */\r
+#define ENET_MAC_HW_FEAT_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSEL_MASK)\r
+#define ENET_MAC_HW_FEAT_ADVTHWORD_MASK (0x2000U)\r
+#define ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT (13U)\r
+/*! ADVTHWORD - IEEE 1588 High Word Register Feature.\r
+ */\r
+#define ENET_MAC_HW_FEAT_ADVTHWORD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_MAC_HW_FEAT_ADVTHWORD_MASK)\r
+#define ENET_MAC_HW_FEAT_EEESEL_MASK (0x2000U)\r
+#define ENET_MAC_HW_FEAT_EEESEL_SHIFT (13U)\r
+/*! EEESEL - Energy Efficient Ethernet Support .\r
+ */\r
+#define ENET_MAC_HW_FEAT_EEESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_MAC_HW_FEAT_EEESEL_MASK)\r
+#define ENET_MAC_HW_FEAT_ADDR64_MASK (0xC000U)\r
+#define ENET_MAC_HW_FEAT_ADDR64_SHIFT (14U)\r
+/*! ADDR64 - Address width.\r
+ */\r
+#define ENET_MAC_HW_FEAT_ADDR64(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_MAC_HW_FEAT_ADDR64_MASK)\r
+#define ENET_MAC_HW_FEAT_TXCOESEL_MASK (0x4000U)\r
+#define ENET_MAC_HW_FEAT_TXCOESEL_SHIFT (14U)\r
+/*! TXCOESEL - Transmit Checksum Offload Support.\r
+ */\r
+#define ENET_MAC_HW_FEAT_TXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_TXCOESEL_MASK)\r
+#define ENET_MAC_HW_FEAT_DCBEN_MASK (0x10000U)\r
+#define ENET_MAC_HW_FEAT_DCBEN_SHIFT (16U)\r
+/*! DCBEN - Data Center Bridging feature.\r
+ */\r
+#define ENET_MAC_HW_FEAT_DCBEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_MAC_HW_FEAT_DCBEN_MASK)\r
+#define ENET_MAC_HW_FEAT_RXCOESEL_MASK (0x10000U)\r
+#define ENET_MAC_HW_FEAT_RXCOESEL_SHIFT (16U)\r
+/*! RXCOESEL - Receive Checksum Offload Support.\r
+ */\r
+#define ENET_MAC_HW_FEAT_RXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_RXCOESEL_MASK)\r
+#define ENET_MAC_HW_FEAT_SPEN_MASK (0x20000U)\r
+#define ENET_MAC_HW_FEAT_SPEN_SHIFT (17U)\r
+/*! SPEN - Split Header Structure feature.\r
+ */\r
+#define ENET_MAC_HW_FEAT_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SPEN_SHIFT)) & ENET_MAC_HW_FEAT_SPEN_MASK)\r
+#define ENET_MAC_HW_FEAT_TSOEN_MASK (0x40000U)\r
+#define ENET_MAC_HW_FEAT_TSOEN_SHIFT (18U)\r
+/*! TSOEN - TCP Segment Offload Feature.\r
+ */\r
+#define ENET_MAC_HW_FEAT_TSOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_MAC_HW_FEAT_TSOEN_MASK)\r
+#define ENET_MAC_HW_FEAT_TXCHCNT_MASK (0x3C0000U)\r
+#define ENET_MAC_HW_FEAT_TXCHCNT_SHIFT (18U)\r
+/*! TXCHCNT - Number of DMA Transmit Channels.\r
+ */\r
+#define ENET_MAC_HW_FEAT_TXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXCHCNT_MASK)\r
+#define ENET_MAC_HW_FEAT_DBGMEMA_MASK (0x80000U)\r
+#define ENET_MAC_HW_FEAT_DBGMEMA_SHIFT (19U)\r
+/*! DBGMEMA - DMA Debug Register Feature.\r
+ */\r
+#define ENET_MAC_HW_FEAT_DBGMEMA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_MAC_HW_FEAT_DBGMEMA_MASK)\r
+#define ENET_MAC_HW_FEAT_AVSEL_MASK (0x100000U)\r
+#define ENET_MAC_HW_FEAT_AVSEL_SHIFT (20U)\r
+/*! AVSEL - Audio Video Bridging Feature.\r
+ */\r
+#define ENET_MAC_HW_FEAT_AVSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_MAC_HW_FEAT_AVSEL_MASK)\r
+#define ENET_MAC_HW_FEAT_LPMODEEN_MASK (0x800000U)\r
+#define ENET_MAC_HW_FEAT_LPMODEEN_SHIFT (23U)\r
+/*! LPMODEEN - Low Power Mode Feature Support .\r
+ */\r
+#define ENET_MAC_HW_FEAT_LPMODEEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_LPMODEEN_SHIFT)) & ENET_MAC_HW_FEAT_LPMODEEN_MASK)\r
+#define ENET_MAC_HW_FEAT_HASHTBLSZ_MASK (0x3000000U)\r
+#define ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT (24U)\r
+/*! HASHTBLSZ - Hash Table Size.\r
+ */\r
+#define ENET_MAC_HW_FEAT_HASHTBLSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_MAC_HW_FEAT_HASHTBLSZ_MASK)\r
+#define ENET_MAC_HW_FEAT_PPSOUTNUM_MASK (0x7000000U)\r
+#define ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT (24U)\r
+/*! PPSOUTNUM - Number of PPS Outputs.\r
+ */\r
+#define ENET_MAC_HW_FEAT_PPSOUTNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_MAC_HW_FEAT_PPSOUTNUM_MASK)\r
+#define ENET_MAC_HW_FEAT_TSSTSSEL_MASK (0x6000000U)\r
+#define ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT (25U)\r
+/*! TSSTSSEL - Timestamp System Time Source.\r
+ */\r
+#define ENET_MAC_HW_FEAT_TSSTSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSTSSEL_MASK)\r
+#define ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK (0x78000000U)\r
+#define ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT (27U)\r
+/*! L3_L4_FILTER - Total Number of L3 and L4 Filters .\r
+ */\r
+#define ENET_MAC_HW_FEAT_L3_L4_FILTER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT)) & ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK)\r
+#define ENET_MAC_HW_FEAT_ACTPHYSEL_MASK (0x70000000U)\r
+#define ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT (28U)\r
+/*! ACTPHYSEL - Active PHY Selected.\r
+ */\r
+#define ENET_MAC_HW_FEAT_ACTPHYSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_MAC_HW_FEAT_ACTPHYSEL_MASK)\r
+#define ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK (0x70000000U)\r
+#define ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT (28U)\r
+/*! AUXSNAPNUM - Number of Auxiliary Snapshot Inputs.\r
+ */\r
+#define ENET_MAC_HW_FEAT_AUXSNAPNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_MAC_HW_FEAT */\r
+#define ENET_MAC_HW_FEAT_COUNT (3U)\r
+\r
+/*! @name MAC_MDIO_ADDR - MIDO address Register */\r
+/*! @{ */\r
+#define ENET_MAC_MDIO_ADDR_MB_MASK (0x1U)\r
+#define ENET_MAC_MDIO_ADDR_MB_SHIFT (0U)\r
+/*! MB - MII busy.\r
+ */\r
+#define ENET_MAC_MDIO_ADDR_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MB_SHIFT)) & ENET_MAC_MDIO_ADDR_MB_MASK)\r
+#define ENET_MAC_MDIO_ADDR_MOC_MASK (0xCU)\r
+#define ENET_MAC_MDIO_ADDR_MOC_SHIFT (2U)\r
+/*! MOC - MII Operation Command.\r
+ */\r
+#define ENET_MAC_MDIO_ADDR_MOC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MOC_SHIFT)) & ENET_MAC_MDIO_ADDR_MOC_MASK)\r
+#define ENET_MAC_MDIO_ADDR_CR_MASK (0xF00U)\r
+#define ENET_MAC_MDIO_ADDR_CR_SHIFT (8U)\r
+/*! CR - CSR Clock Range.\r
+ */\r
+#define ENET_MAC_MDIO_ADDR_CR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_CR_SHIFT)) & ENET_MAC_MDIO_ADDR_CR_MASK)\r
+#define ENET_MAC_MDIO_ADDR_NTC_MASK (0x7000U)\r
+#define ENET_MAC_MDIO_ADDR_NTC_SHIFT (12U)\r
+/*! NTC - Number of Training Clocks This field controls the number of trailing clock cycles\r
+ * generated on MDC after the end of transmission of MDIO frame.\r
+ */\r
+#define ENET_MAC_MDIO_ADDR_NTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_NTC_SHIFT)) & ENET_MAC_MDIO_ADDR_NTC_MASK)\r
+#define ENET_MAC_MDIO_ADDR_RDA_MASK (0x1F0000U)\r
+#define ENET_MAC_MDIO_ADDR_RDA_SHIFT (16U)\r
+/*! RDA - Register/Device Address These bits select the PHY register in selected PHY device.\r
+ */\r
+#define ENET_MAC_MDIO_ADDR_RDA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_RDA_SHIFT)) & ENET_MAC_MDIO_ADDR_RDA_MASK)\r
+#define ENET_MAC_MDIO_ADDR_PA_MASK (0x3E00000U)\r
+#define ENET_MAC_MDIO_ADDR_PA_SHIFT (21U)\r
+/*! PA - Physical Layer Address This field indicates which PHY devices (out of 32 devices) the MAC is accessing.\r
+ */\r
+#define ENET_MAC_MDIO_ADDR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PA_SHIFT)) & ENET_MAC_MDIO_ADDR_PA_MASK)\r
+#define ENET_MAC_MDIO_ADDR_BTB_MASK (0x4000000U)\r
+#define ENET_MAC_MDIO_ADDR_BTB_SHIFT (26U)\r
+/*! BTB - Back to Back transactions When this bit is set and the NTC has value greater than 0, then\r
+ * the MAC will inform the completion of a read or write command at the end of frame transfer\r
+ * (before the trailing clocks are transmitted).\r
+ */\r
+#define ENET_MAC_MDIO_ADDR_BTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_BTB_SHIFT)) & ENET_MAC_MDIO_ADDR_BTB_MASK)\r
+#define ENET_MAC_MDIO_ADDR_PSE_MASK (0x8000000U)\r
+#define ENET_MAC_MDIO_ADDR_PSE_SHIFT (27U)\r
+/*! PSE - Preamble Suppression Enable When this bit is set, the SMA will suppress the 32-bit\r
+ * preamble and transmit MDIO frames with only 1 preamble bit.\r
+ */\r
+#define ENET_MAC_MDIO_ADDR_PSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PSE_SHIFT)) & ENET_MAC_MDIO_ADDR_PSE_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_MDIO_DATA - MDIO Data register */\r
+/*! @{ */\r
+#define ENET_MAC_MDIO_DATA_MD_MASK (0xFFFFU)\r
+#define ENET_MAC_MDIO_DATA_MD_SHIFT (0U)\r
+/*! MD - MII Data This field contains the 16-bit data value read from the PHY after a Management\r
+ * Read operation or the 16-bit data value to be written to the PHY before a Management Write\r
+ * operation.\r
+ */\r
+#define ENET_MAC_MDIO_DATA_MD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_DATA_MD_SHIFT)) & ENET_MAC_MDIO_DATA_MD_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_ADDR_HIGH - MAC address0 high register */\r
+/*! @{ */\r
+#define ENET_MAC_ADDR_HIGH_A47_32_MASK (0xFFFFU)\r
+#define ENET_MAC_ADDR_HIGH_A47_32_SHIFT (0U)\r
+/*! A47_32 - MAC Address0 [47:32] This field contains the upper 16 bits (47:32) of the 6-byte first MAC address.\r
+ */\r
+#define ENET_MAC_ADDR_HIGH_A47_32(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_A47_32_SHIFT)) & ENET_MAC_ADDR_HIGH_A47_32_MASK)\r
+#define ENET_MAC_ADDR_HIGH_DCS_MASK (0x10000U)\r
+#define ENET_MAC_ADDR_HIGH_DCS_SHIFT (16U)\r
+/*! DCS - DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose\r
+ * DA matches the MAC Address content is routed.\r
+ */\r
+#define ENET_MAC_ADDR_HIGH_DCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_DCS_SHIFT)) & ENET_MAC_ADDR_HIGH_DCS_MASK)\r
+#define ENET_MAC_ADDR_HIGH_AE_MASK (0x80000000U)\r
+#define ENET_MAC_ADDR_HIGH_AE_SHIFT (31U)\r
+/*! AE - Address Enable.\r
+ */\r
+#define ENET_MAC_ADDR_HIGH_AE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_AE_SHIFT)) & ENET_MAC_ADDR_HIGH_AE_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_ADDR_LOW - MAC address0 low register */\r
+/*! @{ */\r
+#define ENET_MAC_ADDR_LOW_A31_0_MASK (0xFFFFFFFFU)\r
+#define ENET_MAC_ADDR_LOW_A31_0_SHIFT (0U)\r
+/*! A31_0 - MAC Address0 [31:0] This field contains the lower 32 bits of the 6-byte first MAC address.\r
+ */\r
+#define ENET_MAC_ADDR_LOW_A31_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_LOW_A31_0_SHIFT)) & ENET_MAC_ADDR_LOW_A31_0_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_TIMESTAMP_CTRL - Time stamp control register */\r
+/*! @{ */\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK (0x1U)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT (0U)\r
+/*! TSENA - Enable Timestamp When this bit is set, the timestamp is added for Transmit and Receive packets.\r
+ */\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK (0x2U)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT (1U)\r
+/*! TSCFUPDT - Fine or Coarse Timestamp Update When this bit is set, the Fine method is used to update system timestamp.\r
+ */\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK (0x4U)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT (2U)\r
+/*! TSINIT - Initialize Timestamp When this bit is set, the system time is initialized (overwritten)\r
+ * with the value specified in the MAC Register 80 (System Time Seconds Update.\r
+ */\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSINIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK (0x8U)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT (3U)\r
+/*! TSUPDT - Update Timestamp When this bit is set, the system time is updated (added or subtracted)\r
+ * with the value specified in MAC System Time Seconds Update Table 753 and MAC System Time\r
+ * Nanoseconds Update Table 754.\r
+ */\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK (0x10U)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT (4U)\r
+/*! TSTRIG - Enable Timestamp Interrupt Trigger When this bit is set, the timestamp interrupt is\r
+ * generated when the System Time becomes greater than the value written in the Target Time register.\r
+ */\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK (0x20U)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT (5U)\r
+/*! TADDREG - Update Addend Register When this bit is set, the content of the Timestamp Addend\r
+ * register is updated in the PTP block for fine correction.\r
+ */\r
+#define ENET_MAC_TIMESTAMP_CTRL_TADDREG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK (0x100U)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT (8U)\r
+/*! TSENALL - Enable Timestamp for All Packets When this bit is set, the timestamp snapshot is\r
+ * enabled for all packets received by the MAC.\r
+ */\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSENALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK (0x200U)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT (9U)\r
+/*! TSCTRLSSR - Timestamp Digital or Binary Rollover Control When this bit is set, the Timestamp Low\r
+ * register rolls over after 0x3B9AC9FF value (that is, 1 nanosecond accuracy) and increments\r
+ * the timestamp (High) seconds.\r
+ */\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK (0x400U)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT (10U)\r
+/*! TSVER2ENA - Enable PTP Packet Processing for Version 2 Format When this bit is set, the IEEE\r
+ * 1588 version 2 format is used to process the PTP packets.\r
+ */\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK (0x800U)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT (11U)\r
+/*! TSIPENA - Enable Processing of PTP over Ethernet Packets When this bit is set, the MAC receiver\r
+ * processes the PTP packets encapsulated directly in the Ethernet packets.\r
+ */\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK (0x1000U)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT (12U)\r
+/*! TSIPV6ENA - Enable Processing of PTP Packets Sent over 1Pv6-UDP When this bit is set, the MAC\r
+ * receiver processes the PTP packets encapsulated in IPv6-UDP packets.\r
+ */\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK (0x2000U)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT (13U)\r
+/*! TSIPV4ENA - Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set, the MAC\r
+ * receiver processes the PTP packets encapsulated in IPv4-UDP packets.\r
+ */\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK (0x4000U)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT (14U)\r
+/*! TSEVTENA - Enable Timestamp Snapshot for Event Messages When this bit is set, the timestamp\r
+ * snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp).\r
+ */\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK (0x8000U)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT (15U)\r
+/*! TSMSTRENA - Enable Snapshot for Messages Relevant to Master When this bit is set, the snapshot\r
+ * is taken only for the messages that are relevant to the master node.\r
+ */\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK)\r
+#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK (0x30000U)\r
+#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT (16U)\r
+/*! SNAPTYPSEL - Select PTP packets for Taking Snapshots These bits, along with Bits 15 and 14,\r
+ * decide the set of PTP packet types for which snapshot needs to be taken.\r
+ */\r
+#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK (0x40000U)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT (18U)\r
+/*! TSENMACADDR - Enable MAC Address for PTP Packet Filtering When this bit is set, the DA MAC\r
+ * address (that matches any MAC Address register) is used to filter the PTP packets when PTP is\r
+ * directly sent over Ethernet.\r
+ */\r
+#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK (0x1000000U)\r
+#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT (24U)\r
+/*! TXTTSSTSM - Transmit Timestamp Status Mode When this bit is set, the MAC overwrites the earlier\r
+ * transmit timestamp status even if it is not read by the software.\r
+ */\r
+#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK)\r
+#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK (0x10000000U)\r
+#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT (28U)\r
+/*! AV8021ASMEN - AV 802.\r
+ */\r
+#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_SUB_SCND_INCR - Sub-second increment register */\r
+/*! @{ */\r
+#define ENET_MAC_SUB_SCND_INCR_SSINC_MASK (0xFF0000U)\r
+#define ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT (16U)\r
+/*! SSINC - Sub-second increment value.\r
+ */\r
+#define ENET_MAC_SUB_SCND_INCR_SSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT)) & ENET_MAC_SUB_SCND_INCR_SSINC_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_SYS_TIME_SCND - System time seconds register */\r
+/*! @{ */\r
+#define ENET_MAC_SYS_TIME_SCND_TSS_MASK (0xFFFFFFFFU)\r
+#define ENET_MAC_SYS_TIME_SCND_TSS_SHIFT (0U)\r
+/*! TSS - Time stamp second The value in this field indicates the current value in seconds of the\r
+ * System Time maintained by the MAC.\r
+ */\r
+#define ENET_MAC_SYS_TIME_SCND_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_TSS_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_SYS_TIME_NSCND - System time nanoseconds register */\r
+/*! @{ */\r
+#define ENET_MAC_SYS_TIME_NSCND_TSSS_MASK (0x7FFFFFFFU)\r
+#define ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT (0U)\r
+/*! TSSS - Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.\r
+ */\r
+#define ENET_MAC_SYS_TIME_NSCND_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_TSSS_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_SYS_TIME_SCND_UPD - */\r
+/*! @{ */\r
+#define ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK (0xFFFFFFFFU)\r
+#define ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT (0U)\r
+/*! TSS - Time stamp second The value in this field indicates the time, in seconds, to be initialized or added to the system time.\r
+ */\r
+#define ENET_MAC_SYS_TIME_SCND_UPD_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_SYS_TIME_NSCND_UPD - */\r
+/*! @{ */\r
+#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK (0x7FFFFFFFU)\r
+#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT (0U)\r
+/*! TSSS - Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.\r
+ */\r
+#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK)\r
+#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK (0x80000000U)\r
+#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT (31U)\r
+/*! ADDSUB - Add or subtract time When this bit is set, the time value is subtracted with the contents of the update register.\r
+ */\r
+#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_SYS_TIMESTMP_ADDEND - Time stamp addend register */\r
+/*! @{ */\r
+#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK (0xFFFFFFFFU)\r
+#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT (0U)\r
+/*! TSAR - Time stamp addend This register indicates the 32-bit time value to be added to the\r
+ * Accumulator register to achieve time synchronization.\r
+ */\r
+#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT)) & ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_SYS_TIME_HWORD_SCND - */\r
+/*! @{ */\r
+#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK (0xFFFFU)\r
+#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT (0U)\r
+/*! TSHWR - Time stamp higher word Contains the most significant 16-bits of the Time stamp seconds value.\r
+ */\r
+#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT)) & ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_SYS_TIMESTMP_STAT - Time stamp status register */\r
+/*! @{ */\r
+#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK (0x1U)\r
+#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT (0U)\r
+/*! TSSOVF - Time stamp seconds overflow When set, indicates that the seconds value of the Time\r
+ * stamp has overflowed beyond 0xFFFF_FFFF.\r
+ */\r
+#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT)) & ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - Tx timestamp status nanoseconds */\r
+/*! @{ */\r
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK (0x7FFFFFFFU)\r
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT (0U)\r
+/*! TXTSSTSLO - Transmit timestamp status low.\r
+ */\r
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK)\r
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK (0x80000000U)\r
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT (31U)\r
+/*! TXTSSTSMIS - Transmit timestamp status missed.\r
+ */\r
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - Tx timestamp status seconds */\r
+/*! @{ */\r
+#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK (0xFFFFFFFFU)\r
+#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT (0U)\r
+/*! TXTSSTSHI - Transmit timestamp status high.\r
+ */\r
+#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - Timestamp ingress correction */\r
+/*! @{ */\r
+#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU)\r
+#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U)\r
+/*! TSIC - Transmit ingress correction.\r
+ */\r
+#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - Timestamp egress correction */\r
+/*! @{ */\r
+#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU)\r
+#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U)\r
+/*! TSEC - Transmit egress correction.\r
+ */\r
+#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK)\r
+/*! @} */\r
+\r
+/*! @name MTL_OP_MODE - MTL Operation Mode Register */\r
+/*! @{ */\r
+#define ENET_MTL_OP_MODE_DTXSTS_MASK (0x2U)\r
+#define ENET_MTL_OP_MODE_DTXSTS_SHIFT (1U)\r
+/*! DTXSTS - Drop Transmit Status When this bit is set, the Tx packet status received from the MAC is dropped in the MTL.\r
+ */\r
+#define ENET_MTL_OP_MODE_DTXSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_DTXSTS_SHIFT)) & ENET_MTL_OP_MODE_DTXSTS_MASK)\r
+#define ENET_MTL_OP_MODE_RAA_MASK (0x4U)\r
+#define ENET_MTL_OP_MODE_RAA_SHIFT (2U)\r
+/*! RAA - Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side.\r
+ */\r
+#define ENET_MTL_OP_MODE_RAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_RAA_SHIFT)) & ENET_MTL_OP_MODE_RAA_MASK)\r
+#define ENET_MTL_OP_MODE_SCHALG_MASK (0x60U)\r
+#define ENET_MTL_OP_MODE_SCHALG_SHIFT (5U)\r
+/*! SCHALG - Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling: 0x00: WRR\r
+ * algorithm 0x1: Reserved 0x2: Reserved 0x3: Strict priority algorithm.\r
+ */\r
+#define ENET_MTL_OP_MODE_SCHALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_SCHALG_SHIFT)) & ENET_MTL_OP_MODE_SCHALG_MASK)\r
+#define ENET_MTL_OP_MODE_CNTPRST_MASK (0x100U)\r
+#define ENET_MTL_OP_MODE_CNTPRST_SHIFT (8U)\r
+/*! CNTPRST - Counters Preset When this bit is set, MTL TxQ0 Underflow register (Table 762) and\r
+ * MTL_TxQ1_Underflow (Table 762) registers are initialized/preset to 0x7F0.\r
+ */\r
+#define ENET_MTL_OP_MODE_CNTPRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTPRST_SHIFT)) & ENET_MTL_OP_MODE_CNTPRST_MASK)\r
+#define ENET_MTL_OP_MODE_CNTCLR_MASK (0x200U)\r
+#define ENET_MTL_OP_MODE_CNTCLR_SHIFT (9U)\r
+/*! CNTCLR - Counters Reset When this bit is set, all counters are reset.\r
+ */\r
+#define ENET_MTL_OP_MODE_CNTCLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTCLR_SHIFT)) & ENET_MTL_OP_MODE_CNTCLR_MASK)\r
+/*! @} */\r
+\r
+/*! @name MTL_INTR_STAT - MTL Interrupt Status register */\r
+/*! @{ */\r
+#define ENET_MTL_INTR_STAT_Q0IS_MASK (0x1U)\r
+#define ENET_MTL_INTR_STAT_Q0IS_SHIFT (0U)\r
+/*! Q0IS - Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0.\r
+ */\r
+#define ENET_MTL_INTR_STAT_Q0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q0IS_SHIFT)) & ENET_MTL_INTR_STAT_Q0IS_MASK)\r
+#define ENET_MTL_INTR_STAT_Q1IS_MASK (0x2U)\r
+#define ENET_MTL_INTR_STAT_Q1IS_SHIFT (1U)\r
+/*! Q1IS - Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1.\r
+ */\r
+#define ENET_MTL_INTR_STAT_Q1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q1IS_SHIFT)) & ENET_MTL_INTR_STAT_Q1IS_MASK)\r
+/*! @} */\r
+\r
+/*! @name MTL_RXQ_DMA_MAP - MTL Receive Queue and DMA Channel Mapping register */\r
+/*! @{ */\r
+#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK (0x1U)\r
+#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT (0U)\r
+/*! Q0MDMACH - Queue 0 Mapped to DMA Channel This field controls the routing of the packet received\r
+ * in Queue 0 to the DMA channel: 0: DMA Channel 0 1: DMA Channel 1 This field is valid when the\r
+ * Q0DDMACH field is reset.\r
+ */\r
+#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK)\r
+#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK (0x10U)\r
+#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT (4U)\r
+/*! Q0DDMACH - Queue 0 Enabled for DA-based DMA Channel Selection When set, this bit indicates that\r
+ * the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC\r
+ * Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the\r
+ * Ethernet DA address.\r
+ */\r
+#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK)\r
+#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK (0x100U)\r
+#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT (8U)\r
+/*! Q1MDMACH - Queue 1 Mapped to DMA Channel This field controls the routing of the received packet\r
+ * in Queue 1 to the DMA channel: 0: DMA Channel 0 1: DMA Channel 1 This field is valid when the\r
+ * Q1DDMACH field is reset.\r
+ */\r
+#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK)\r
+#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK (0x1000U)\r
+#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT (12U)\r
+/*! Q1DDMACH - Queue 1 Enabled for DA-based DMA Channel Selection When set, this bit indicates that\r
+ * the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC\r
+ * Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the\r
+ * Ethernet DA address.\r
+ */\r
+#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK)\r
+/*! @} */\r
+\r
+/*! @name MTL_QUEUE_MTL_TXQX_OP_MODE - MTL TxQx Operation Mode register */\r
+/*! @{ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK (0x1U)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT (0U)\r
+/*! FTQ - Flush Transmit Queue When this bit is set, the Tx queue controller logic is reset to its default values.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK (0x2U)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT (1U)\r
+/*! TSF - Transmit Store and Forward When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK (0xCU)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT (2U)\r
+/*! TXQEN - Transmit Queue Enable This field is used to enable/disable the transmit queue 0.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK (0x70U)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT (4U)\r
+/*! TTC - Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK (0x70000U)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT (16U)\r
+/*! TQS - Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_OP_MODE */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_COUNT (2U)\r
+\r
+/*! @name MTL_QUEUE_MTL_TXQX_UNDRFLW - MTL TxQx Underflow register */\r
+/*! @{ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK (0x7FFU)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U)\r
+/*! UFFRMCNT - Underflow Packet Counter This field indicates the number of packets aborted by the\r
+ * controller because of Tx Queue Underflow.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK (0x800U)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U)\r
+/*! UFCNTOVF - Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue\r
+ * Underflow Packet Counter field overflows, that is, it has crossed the maximum count.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_COUNT (2U)\r
+\r
+/*! @name MTL_QUEUE_MTL_TXQX_DBG - MTL TxQx Debug register */\r
+/*! @{ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK (0x1U)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT (0U)\r
+/*! TXQPAUSED - Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it\r
+ * indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because\r
+ * of the following: - Reception of the PFC packet for the priorities assigned to the Tx Queue\r
+ * when PFC is enabled - Reception of 802.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK (0x6U)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT (1U)\r
+/*! TRCSTS - MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read\r
+ * Controller: 00: Idle state 01: Read state (transferring data to the MAC transmitter) 10:\r
+ * Waiting for pending Tx Status from the MAC transmitter 11: Flushing the Tx queue because of the\r
+ * Packet Abort request from the MAC.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK (0x8U)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT (3U)\r
+/*! TWCSTS - MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx\r
+ * Queue Write Controller is active, and it is transferring the data to the Tx Queue.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK (0x10U)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT (4U)\r
+/*! TXQSTS - MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx Queue\r
+ * is not empty and some data is left for transmission.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK (0x20U)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT (5U)\r
+/*! TXSTSFSTS - MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK (0x70000U)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT (16U)\r
+/*! PTXQ - Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK (0x700000U)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT (20U)\r
+/*! STSXSTSF - Number of Status Words in Tx Status FIFO of Queue This field indicates the current\r
+ * number of status in the Tx Status FIFO of this queue.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_DBG */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_COUNT (2U)\r
+\r
+/*! @name MTL_QUEUE_MTL_TXQX_ETS_CTRL - MTL TxQx ETS control register, only TxQ1 support */\r
+/*! @{ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK (0x4U)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT (2U)\r
+/*! AVALG - AV Algorithm.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK (0x8U)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT (3U)\r
+/*! CC - Credit Control.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK (0x70U)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT (4U)\r
+/*! SLC - Credit Control.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_COUNT (2U)\r
+\r
+/*! @name MTL_QUEUE_MTL_TXQX_ETS_STAT - MTL TxQx ETS Status register */\r
+/*! @{ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK (0xFFFFFFU)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT (0U)\r
+/*! ABS - Average Bits per Slot.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_COUNT (2U)\r
+\r
+/*! @name MTL_QUEUE_MTL_TXQX_QNTM_WGHT - */\r
+/*! @{ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK (0x1FFFFFU)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT (0U)\r
+/*! ISCQW - Average Bits per Slot.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_COUNT (2U)\r
+\r
+/*! @name MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT - MTL TxQx SendSlopCredit register, only TxQ1 support */\r
+/*! @{ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK (0x3FFFU)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT (0U)\r
+/*! SSC - sendSlopeCredit.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_COUNT (2U)\r
+\r
+/*! @name MTL_QUEUE_MTL_TXQX_HI_CRDT - MTL TxQx hiCredit register, only TxQ1 support */\r
+/*! @{ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK (0x1FFFFFFFU)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT (0U)\r
+/*! HC - hiCredit.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_COUNT (2U)\r
+\r
+/*! @name MTL_QUEUE_MTL_TXQX_LO_CRDT - MTL TxQx loCredit register, only TxQ1 support */\r
+/*! @{ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK (0x1FFFFFFFU)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT (0U)\r
+/*! LC - loCredit.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_COUNT (2U)\r
+\r
+/*! @name MTL_QUEUE_MTL_TXQX_INTCTRL_STAT - */\r
+/*! @{ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK (0x1U)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT (0U)\r
+/*! TXUNFIS - Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue\r
+ * had an underflow while transmitting the packet.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK (0x2U)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT (1U)\r
+/*! ABPSIS - Average Bits Per Slot Interrupt Status When set, this bit indicates that the MAC has updated the ABS value.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK (0x100U)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT (8U)\r
+/*! TXUIE - Transmit Queue Underflow Interrupt Enable When this bit is set, the Transmit Queue Underflow interrupt is enabled.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK (0x200U)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT (9U)\r
+/*! ABPSIE - Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts the\r
+ * interrupt when the average bits per slot status is updated.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT (16U)\r
+/*! RXOVFIS - Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had\r
+ * an overflow while receiving the packet.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK (0x1000000U)\r
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT (24U)\r
+/*! RXOIE - Receive Queue Overflow Interrupt Enable When this bit is set, the Receive Queue Overflow interrupt is enabled.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT */\r
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_COUNT (2U)\r
+\r
+/*! @name MTL_QUEUE_MTL_RXQX_OP_MODE - MTL RxQx Operation Mode register */\r
+/*! @{ */\r
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK (0x3U)\r
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT (0U)\r
+/*! RTC - Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue\r
+ * (in bytes): 00: 64 01: 32 10: 96 11: 128 The packet received is transferred to the\r
+ * application or DMA when the packet size within the MTL Rx queue is larger than the threshold.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK)\r
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK (0x8U)\r
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT (3U)\r
+/*! FUP - Forward Undersized Good Packets When this bit is set, the Rx queue forwards the undersized\r
+ * good packets (packets with no error and length less than 64 bytes), including pad-bytes and\r
+ * CRC.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK)\r
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK (0x10U)\r
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT (4U)\r
+/*! FEP - Forward Error Packets When this bit is reset, the Rx queue drops packets with error status\r
+ * (CRC error, Mll_ER, watchdog timeout, or overflow).\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK)\r
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK (0x20U)\r
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT (5U)\r
+/*! RSF - Receive Queue Store and Forward When this bit is set, the ethernet block on this chip\r
+ * reads a packet from the Rx queue only after the complete packet has been written to it, ignoring\r
+ * the RTC field of this register.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK)\r
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U)\r
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U)\r
+/*! DIS_TCP_EF - Disable Dropping of TCP/IP Checksum Error Packets When this bit is set, the MAC\r
+ * does not drop the packets which only have the errors detected by the Receive Checksum Offload\r
+ * engine.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK)\r
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK (0x700000U)\r
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT (20U)\r
+/*! RQS - This field indicates the size of the allocated Receive queues in blocks of 256 bytes.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_MTL_QUEUE_MTL_RXQX_OP_MODE */\r
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_COUNT (2U)\r
+\r
+/*! @name MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT - MTL RxQx Missed Packet Overflow Counter register */\r
+/*! @{ */\r
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU)\r
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U)\r
+/*! OVFPKTCNT - Overflow Packet Counter This field indicates the number of packets discarded by the\r
+ * Ethernet block because of Receive queue overflow.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK)\r
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U)\r
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U)\r
+/*! OVFCNTOVF - Overflow Counter Overflow Bit When set, this bit indicates that the Rx Queue\r
+ * Overflow Packet Counter field crossed the maximum limit.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT */\r
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_COUNT (2U)\r
+\r
+/*! @name MTL_QUEUE_MTL_RXQX_DBG - MTL RxQx Debug register */\r
+/*! @{ */\r
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK (0x1U)\r
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT (0U)\r
+/*! RWCSTS - MTL Rx Queue Write Controller Active Status When high, this bit indicates that the MTL\r
+ * Rx queue Write controller is active, and it is transferring a received packet to the Rx Queue.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK)\r
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK (0x6U)\r
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT (1U)\r
+/*! RRCSTS - MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read\r
+ * controller: 00: Idle state 01: Reading packet data 10: Reading packet status (or timestamp) 11:\r
+ * Flushing the packet data and status.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK)\r
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK (0x30U)\r
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT (4U)\r
+/*! RXQSTS - MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx\r
+ * Queue: 0x0: Rx Queue empty 0x1: Rx Queue fill-level below flow-control deactivate threshold\r
+ * 0x2: Rx Queue fill-level above flow-control activate threshold 0x3: Rx Queue full.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK)\r
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK (0x3FFF0000U)\r
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT (16U)\r
+/*! PRXQ - Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_MTL_QUEUE_MTL_RXQX_DBG */\r
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_COUNT (2U)\r
+\r
+/*! @name MTL_QUEUE_MTL_RXQX_CTRL - MTL RxQx Control register */\r
+/*! @{ */\r
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK (0x7U)\r
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT (0U)\r
+/*! RXQ_WEGT - Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK)\r
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U)\r
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U)\r
+/*! RXQ_FRM_ARBIT - Receive Queue Packet Arbitration When this bit is set, the The ethernet block\r
+ * drives the packet data to the ARI interface such that the entire packet data of\r
+ * currently-selected queue is transmitted before switching to other queue.\r
+ */\r
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_MTL_QUEUE_MTL_RXQX_CTRL */\r
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_COUNT (2U)\r
+\r
+/*! @name DMA_MODE - DMA mode register */\r
+/*! @{ */\r
+#define ENET_DMA_MODE_SWR_MASK (0x1U)\r
+#define ENET_DMA_MODE_SWR_SHIFT (0U)\r
+/*! SWR - Software Reset When this bit is set, the MAC and the OMA controller reset the logic and\r
+ * all internal registers of the OMA, MTL, and MAC.\r
+ */\r
+#define ENET_DMA_MODE_SWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_SWR_SHIFT)) & ENET_DMA_MODE_SWR_MASK)\r
+#define ENET_DMA_MODE_DA_MASK (0x2U)\r
+#define ENET_DMA_MODE_DA_SHIFT (1U)\r
+/*! DA - DMA Tx or Rx Arbitration Scheme This bit specifies the arbitration scheme between the\r
+ * Transmit and Receive paths of all channels: The Tx path has priority over the Rx path when the TXPR\r
+ * bit is set.\r
+ */\r
+#define ENET_DMA_MODE_DA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_DA_SHIFT)) & ENET_DMA_MODE_DA_MASK)\r
+#define ENET_DMA_MODE_TAA_MASK (0x1CU)\r
+#define ENET_DMA_MODE_TAA_SHIFT (2U)\r
+/*! TAA - Transmit Arbitration Algorithm This field is used to select the arbitration algorithm for\r
+ * the Transmit side when multiple Tx DMAs are selected.\r
+ */\r
+#define ENET_DMA_MODE_TAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TAA_SHIFT)) & ENET_DMA_MODE_TAA_MASK)\r
+#define ENET_DMA_MODE_TXPR_MASK (0x800U)\r
+#define ENET_DMA_MODE_TXPR_SHIFT (11U)\r
+/*! TXPR - Transmit Priority When set, this bit indicates that the Tx DMA has higher priority than\r
+ * the Rx DMA during arbitration for the system-side bus.\r
+ */\r
+#define ENET_DMA_MODE_TXPR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TXPR_SHIFT)) & ENET_DMA_MODE_TXPR_MASK)\r
+#define ENET_DMA_MODE_PR_MASK (0x7000U)\r
+#define ENET_DMA_MODE_PR_SHIFT (12U)\r
+/*! PR - Priority Ratio These bits control the priority ratio in weighted round-robin arbitration between the Rx DMA and Tx DMA.\r
+ */\r
+#define ENET_DMA_MODE_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_PR_SHIFT)) & ENET_DMA_MODE_PR_MASK)\r
+/*! @} */\r
+\r
+/*! @name DMA_SYSBUS_MODE - DMA System Bus mode */\r
+/*! @{ */\r
+#define ENET_DMA_SYSBUS_MODE_FB_MASK (0x1U)\r
+#define ENET_DMA_SYSBUS_MODE_FB_SHIFT (0U)\r
+/*! FB - Fixed Burst Length When this bit is set to 1, the AHB master will initiate burst transfers\r
+ * of specified length (INCRx or SINGLE).\r
+ */\r
+#define ENET_DMA_SYSBUS_MODE_FB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_FB_SHIFT)) & ENET_DMA_SYSBUS_MODE_FB_MASK)\r
+#define ENET_DMA_SYSBUS_MODE_AAL_MASK (0x1000U)\r
+#define ENET_DMA_SYSBUS_MODE_AAL_SHIFT (12U)\r
+/*! AAL - Address-Aligned Beats When this bit is set to 1, the AHB master performs address-aligned\r
+ * burst transfers on Read and Write channels.\r
+ */\r
+#define ENET_DMA_SYSBUS_MODE_AAL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_AAL_SHIFT)) & ENET_DMA_SYSBUS_MODE_AAL_MASK)\r
+#define ENET_DMA_SYSBUS_MODE_MB_MASK (0x4000U)\r
+#define ENET_DMA_SYSBUS_MODE_MB_SHIFT (14U)\r
+/*! MB - Mixed Burst When this bit is set high and the FB bit is low, the AHB master performs\r
+ * undefined bursts transfers (INCR) for burst length of 16 or more.\r
+ */\r
+#define ENET_DMA_SYSBUS_MODE_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_MB_SHIFT)) & ENET_DMA_SYSBUS_MODE_MB_MASK)\r
+#define ENET_DMA_SYSBUS_MODE_RB_MASK (0x8000U)\r
+#define ENET_DMA_SYSBUS_MODE_RB_SHIFT (15U)\r
+/*! RB - Rebuild INCRx Burst When this bit is set high and the AHB master gets SPLIT, RETRY, or\r
+ * EarlyBurst Termination (EBT) response, the AHB master interface rebuilds the pending beats of any\r
+ * initiated burst transfer with INCRx and SINGLEtransfers.\r
+ */\r
+#define ENET_DMA_SYSBUS_MODE_RB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_RB_SHIFT)) & ENET_DMA_SYSBUS_MODE_RB_MASK)\r
+/*! @} */\r
+\r
+/*! @name DMA_INTR_STAT - DMA Interrupt status */\r
+/*! @{ */\r
+#define ENET_DMA_INTR_STAT_DC0IS_MASK (0x1U)\r
+#define ENET_DMA_INTR_STAT_DC0IS_SHIFT (0U)\r
+/*! DC0IS - DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0.\r
+ */\r
+#define ENET_DMA_INTR_STAT_DC0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC0IS_SHIFT)) & ENET_DMA_INTR_STAT_DC0IS_MASK)\r
+#define ENET_DMA_INTR_STAT_DC1IS_MASK (0x2U)\r
+#define ENET_DMA_INTR_STAT_DC1IS_SHIFT (1U)\r
+/*! DC1IS - DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1.\r
+ */\r
+#define ENET_DMA_INTR_STAT_DC1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC1IS_SHIFT)) & ENET_DMA_INTR_STAT_DC1IS_MASK)\r
+#define ENET_DMA_INTR_STAT_MTLIS_MASK (0x10000U)\r
+#define ENET_DMA_INTR_STAT_MTLIS_SHIFT (16U)\r
+/*! MTLIS - MTL Interrupt Status This bit indicates an interrupt event in the MTL.\r
+ */\r
+#define ENET_DMA_INTR_STAT_MTLIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MTLIS_SHIFT)) & ENET_DMA_INTR_STAT_MTLIS_MASK)\r
+#define ENET_DMA_INTR_STAT_MACIS_MASK (0x20000U)\r
+#define ENET_DMA_INTR_STAT_MACIS_SHIFT (17U)\r
+/*! MACIS - MAC Interrupt Status This bit indicates an interrupt event in the MAC.\r
+ */\r
+#define ENET_DMA_INTR_STAT_MACIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MACIS_SHIFT)) & ENET_DMA_INTR_STAT_MACIS_MASK)\r
+/*! @} */\r
+\r
+/*! @name DMA_DBG_STAT - DMA Debug Status */\r
+/*! @{ */\r
+#define ENET_DMA_DBG_STAT_AHSTS_MASK (0x1U)\r
+#define ENET_DMA_DBG_STAT_AHSTS_SHIFT (0U)\r
+/*! AHSTS - AHB Master Status When high, this bit indicates that the AHB master FSMs are in the non-idle state.\r
+ */\r
+#define ENET_DMA_DBG_STAT_AHSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_AHSTS_SHIFT)) & ENET_DMA_DBG_STAT_AHSTS_MASK)\r
+#define ENET_DMA_DBG_STAT_RPS0_MASK (0xF00U)\r
+#define ENET_DMA_DBG_STAT_RPS0_SHIFT (8U)\r
+/*! RPS0 - DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel\r
+ * 0: 0x0: Stopped (Reset or Stop Receive Command issued) 0x1: Running (Fetching Rx Transfer )\r
+ * 0x2: Reserved 0x3: Running (Waiting for Rx packet) 0x4: Suspended (Rx Unavailable) 0x5: Running\r
+ * (Closing the Rx) 0x6: Timestamp write state 0x7: Running (Transferring the received packet\r
+ * data from the Rx buffer to the system memory) This field does not generate an interrupt.\r
+ */\r
+#define ENET_DMA_DBG_STAT_RPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS0_SHIFT)) & ENET_DMA_DBG_STAT_RPS0_MASK)\r
+#define ENET_DMA_DBG_STAT_TPS0_MASK (0xF000U)\r
+#define ENET_DMA_DBG_STAT_TPS0_SHIFT (12U)\r
+/*! TPS0 - DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for\r
+ * Channel 0: 000: Stopped (Reset or Stop Transmit Command issued) 0x1: Running (Fetching Tx Transfer)\r
+ * 0x2: Running (Waiting for status) 0x3: Running (Reading Data from system memory buffer and\r
+ * queuing it to the Tx buffer (Tx FIFO)) 0x4: Timestamp write state 0x5: Reserved for future use\r
+ * 0x6: Suspended (Tx Unavailable or Tx Buffer Underflow) 0x7: Running (Closing Tx ) This field\r
+ * does not generate an interrupt.\r
+ */\r
+#define ENET_DMA_DBG_STAT_TPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS0_SHIFT)) & ENET_DMA_DBG_STAT_TPS0_MASK)\r
+#define ENET_DMA_DBG_STAT_RPS1_MASK (0xF0000U)\r
+#define ENET_DMA_DBG_STAT_RPS1_SHIFT (16U)\r
+/*! RPS1 - DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1.\r
+ */\r
+#define ENET_DMA_DBG_STAT_RPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS1_SHIFT)) & ENET_DMA_DBG_STAT_RPS1_MASK)\r
+#define ENET_DMA_DBG_STAT_TPS1_MASK (0xF00000U)\r
+#define ENET_DMA_DBG_STAT_TPS1_SHIFT (20U)\r
+/*! TPS1 - DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1.\r
+ */\r
+#define ENET_DMA_DBG_STAT_TPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS1_SHIFT)) & ENET_DMA_DBG_STAT_TPS1_MASK)\r
+/*! @} */\r
+\r
+/*! @name DMA_CH_DMA_CHX_CTRL - DMA Channelx Control */\r
+/*! @{ */\r
+#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK (0x10000U)\r
+#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT (16U)\r
+/*! PBLx8 - 8xPBL mode When this bit is set, the PBL value programmed in Bits[21:16] in DMA Channel\r
+ * Transmit Control Table 780 is multiplied eight times.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK (0x1C0000U)\r
+#define ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT (18U)\r
+/*! DSL - Skip Length This bit specifies the Word, Dword, or Lword number (depending on the 32- bit,\r
+ * 64-bit, or 128-bit bus) to skip between two unchained s.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_DMA_CH_DMA_CHX_CTRL */\r
+#define ENET_DMA_CH_DMA_CHX_CTRL_COUNT (2U)\r
+\r
+/*! @name DMA_CH_DMA_CHX_TX_CTRL - DMA Channelx Transmit Control */\r
+/*! @{ */\r
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK (0x1U)\r
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT (0U)\r
+/*! ST - Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK (0xEU)\r
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT (1U)\r
+/*! TCW - Transmit Channel Weight This field indicates the weight assigned to the corresponding Transmit channel.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK (0x10U)\r
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT (4U)\r
+/*! OSF - Operate on Second Frame When this bit is set, it instructs the DMA to process the second\r
+ * packet of the Transmit data even before the status for the first packet is obtained.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK (0x3F0000U)\r
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT (16U)\r
+/*! TxPBL - Transmit Programmable Burst Length These bits indicate the maximum number of beats to be\r
+ * transferred in one DMA data transfer.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_DMA_CH_DMA_CHX_TX_CTRL */\r
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_COUNT (2U)\r
+\r
+/*! @name DMA_CH_DMA_CHX_RX_CTRL - DMA Channelx Receive Control */\r
+/*! @{ */\r
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK (0x1U)\r
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT (0U)\r
+/*! SR - Start or Stop Receive When this bit is set, the DMA tries to acquire the from the receive\r
+ * list and processes the incoming packets.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK (0x7FF8U)\r
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT (3U)\r
+/*! RBSZ - Receive Buffer size This field indicates the size of the Rx buffers specified in bytes.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK (0x3F0000U)\r
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT (16U)\r
+/*! RxPBL - Receive Programmable Burst Length These bits indicate the maximum number of beats to be\r
+ * transferred in one DMA data transfer.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK (0x80000000U)\r
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT (31U)\r
+/*! RPF - DMA Rx Channel 0 Packet Flush When this bit is set to 1, the DMA will automatically flush\r
+ * the packet from the Rx Queues destined to DMA Rx Channel 0 when the DMA Rx Channel 0 is\r
+ * stopped after a system bus error has occurred.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_DMA_CH_DMA_CHX_RX_CTRL */\r
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_COUNT (2U)\r
+\r
+/*! @name DMA_CH_DMA_CHX_TXDESC_LIST_ADDR - */\r
+/*! @{ */\r
+#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK (0xFFFFFFFCU)\r
+#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT (2U)\r
+/*! STL - Start of transmit list This field contains the base address of the first in the Transmit list.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR */\r
+#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_COUNT (2U)\r
+\r
+/*! @name DMA_CH_DMA_CHX_RXDESC_LIST_ADDR - */\r
+/*! @{ */\r
+#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK (0xFFFFFFFCU)\r
+#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT (2U)\r
+/*! SRL - Start of receive list This field contains the base address of the First in the Receive list.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR */\r
+#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_COUNT (2U)\r
+\r
+/*! @name DMA_CH_DMA_CHX_TXDESC_TAIL_PTR - */\r
+/*! @{ */\r
+#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFFCU)\r
+#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (2U)\r
+/*! TDTP - Transmit Tail Pointer This field contains the tail pointer for the Tx ring.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR */\r
+#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_COUNT (2U)\r
+\r
+/*! @name DMA_CH_DMA_CHX_RXDESC_TAIL_PTR - */\r
+/*! @{ */\r
+#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFFCU)\r
+#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (2U)\r
+/*! RDTP - Receive Tail Pointer This field contains the tail pointer for the Rx ring.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR */\r
+#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_COUNT (2U)\r
+\r
+/*! @name DMA_CH_DMA_CHX_TXDESC_RING_LENGTH - */\r
+/*! @{ */\r
+#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU)\r
+#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U)\r
+/*! TDRL - Transmit Ring Length This field sets the maximum number of Tx descriptors in the circular ring.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH */\r
+#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_COUNT (2U)\r
+\r
+/*! @name DMA_CH_DMA_CHX_RXDESC_RING_LENGTH - Channelx Rx descriptor Ring Length */\r
+/*! @{ */\r
+#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU)\r
+#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT (0U)\r
+/*! RDRL - Receive Ring Length This register sets the maximum number of Rx descriptors in the circular ring.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH */\r
+#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_COUNT (2U)\r
+\r
+/*! @name DMA_CH_DMA_CHX_INT_EN - Channelx Interrupt Enable */\r
+/*! @{ */\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK (0x1U)\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT (0U)\r
+/*! TIE - Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit\r
+ * 16 in this register), Transmit Interrupt is enabled.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK (0x2U)\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT (1U)\r
+/*! TSE - Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit\r
+ * 15 in this register), Transmission Stopped Interrupt is enabled.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK (0x4U)\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT (2U)\r
+/*! TBUE - Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary\r
+ * Enable (bit 16 in this register), Transmit Buffer Unavailable Interrupt is enabled.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK (0x40U)\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT (6U)\r
+/*! RIE - Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16\r
+ * in this register), Receive Interrupt is enabled.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK (0x80U)\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT (7U)\r
+/*! RBUE - Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary\r
+ * Enable (bit 15 in this register), Receive Buffer Unavailable Interrupt is enabled.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK (0x100U)\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT (8U)\r
+/*! RSE - Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit\r
+ * 15 in this register), Receive Stopped Interrupt is enabled.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK (0x200U)\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT (9U)\r
+/*! RWTE - Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary\r
+ * Enable (bit 15 in this register), the Receive Watchdog Timeout Interrupt is enabled.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK (0x400U)\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT (10U)\r
+/*! ETIE - Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary\r
+ * Enable (bit 15 in this register), Early Transmit Interrupt is enabled.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK (0x800U)\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT (11U)\r
+/*! ERIE - Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable\r
+ * (bit 16 in this register), Early Receive Interrupt is enabled.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK (0x1000U)\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT (12U)\r
+/*! FBEE - Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit\r
+ * 15 in this register), the Fatal Bus Error Interrupt is enabled.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK (0x4000U)\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT (14U)\r
+/*! AIE - Abnormal interrupt summary enable When this bit is set, an Abnormal Interrupt summary is enabled.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK (0x8000U)\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT (15U)\r
+/*! NIE - Normal interrupt summary enable When this bit is set, a normal interrupt is enabled.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_DMA_CH_DMA_CHX_INT_EN */\r
+#define ENET_DMA_CH_DMA_CHX_INT_EN_COUNT (2U)\r
+\r
+/*! @name DMA_CH_DMA_CHX_RX_INT_WDTIMER - Receive Interrupt Watchdog Timer */\r
+/*! @{ */\r
+#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK (0xFFU)\r
+#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT (0U)\r
+/*! RIWT - Receive Interrupt Watchdog Timer Count Indicates the number of system clock cycles\r
+ * multiplied by 256 for which the watchdog timer is set.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER */\r
+#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_COUNT (2U)\r
+\r
+/*! @name DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT - Slot Function Control and Status */\r
+/*! @{ */\r
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK (0x1U)\r
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT (0U)\r
+/*! ESC - Enable Slot Comparison When set, this bit enables the checking of the slot numbers\r
+ * programmed in the Tx descriptor with the current reference given in the RSN field.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK (0x2U)\r
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT (1U)\r
+/*! ASC - Advance Slot Check When set, this bit enables the D MA to fetch the data from the buffer\r
+ * when the slot number (SLOTNUM) programmed in the Tx descriptor is equal to the reference slot\r
+ * number given in the RSN field or, ahead of the reference slot number by up to two slots This\r
+ * bit is applicable only when the ESC bit is set.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK (0xF0000U)\r
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT (16U)\r
+/*! RSN - Reference Slot Number This field gives the current value of the reference slot number in the DMA.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT */\r
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_COUNT (2U)\r
+\r
+/*! @name DMA_CH_DMA_CHX_CUR_HST_TXDESC - Channelx Current Host Transmit descriptor */\r
+/*! @{ */\r
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK (0xFFFFFFFFU)\r
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT (0U)\r
+/*! HTD - Host Transmit descriptor Address Pointer Cleared on Reset.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC */\r
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_COUNT (2U)\r
+\r
+/*! @name DMA_CH_DMA_CHX_CUR_HST_RXDESC - */\r
+/*! @{ */\r
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK (0xFFFFFFFFU)\r
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT (0U)\r
+/*! HRD - Host Receive descriptor Address Pointer Cleared on Reset.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC */\r
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_COUNT (2U)\r
+\r
+/*! @name DMA_CH_DMA_CHX_CUR_HST_TXBUF - */\r
+/*! @{ */\r
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK (0xFFFFFFFFU)\r
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT (0U)\r
+/*! HTB - Host Transmit Buffer Address Pointer Cleared on Reset.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF */\r
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_COUNT (2U)\r
+\r
+/*! @name DMA_CH_DMA_CHX_CUR_HST_RXBUF - Channelx Current Application Receive Buffer Address */\r
+/*! @{ */\r
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK (0xFFFFFFFFU)\r
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT (0U)\r
+/*! HRB - Host Receive Buffer Address Pointer Cleared on Reset.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF */\r
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_COUNT (2U)\r
+\r
+/*! @name DMA_CH_DMA_CHX_STAT - Channelx DMA status register */\r
+/*! @{ */\r
+#define ENET_DMA_CH_DMA_CHX_STAT_TI_MASK (0x1U)\r
+#define ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT (0U)\r
+/*! TI - Transmit Interrupt This bit indicates that the packet transmission is complete.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_STAT_TI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TI_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK (0x2U)\r
+#define ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT (1U)\r
+/*! TPS - Transmit Process Stopped This bit is set when the transmission is stopped.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_STAT_TPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK (0x4U)\r
+#define ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT (2U)\r
+/*! TBU - Transmit Buffer Unavailable This bit indicates that the application owns the next\r
+ * descriptor in the transmit list, and the DMA cannot acquire it.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_STAT_TBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_STAT_RI_MASK (0x40U)\r
+#define ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT (6U)\r
+/*! RI - Receive Interrupt This bit indicates that the packet reception is complete.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_STAT_RI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RI_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK (0x80U)\r
+#define ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT (7U)\r
+/*! RBU - Receive Buffer Unavailable This bit indicates that the application owns the next in the\r
+ * receive list, and the DMA cannot acquire it.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_STAT_RBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK (0x100U)\r
+#define ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT (8U)\r
+/*! RPS - Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_STAT_RPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK (0x200U)\r
+#define ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT (9U)\r
+/*! RWT - Receive Watchdog time out This bit is asserted when a packet with length greater than\r
+ * 2,048 bytes (10,240 bytes when Jumbo Packet mode is enabled) is received.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK (0x400U)\r
+#define ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT (10U)\r
+/*! ETI - Early Transmit Interrupt This bit indicates that the packet to be transmitted is fully transferred to the MTL Tx FIFO.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_STAT_ETI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK (0x800U)\r
+#define ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT (11U)\r
+/*! ERI - Early Receive Interrupt This bit indicates that the DMA filled the first data buffer of the packet.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_STAT_ERI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK (0x1000U)\r
+#define ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT (12U)\r
+/*! FBE - Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field).\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_STAT_FBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK (0x4000U)\r
+#define ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT (14U)\r
+/*! AIS - Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the\r
+ * following when the corresponding interrupt bits are enabled in the DMA Channel Interrupt Enable\r
+ * register Table 778: Bit 1: Transmit Process Stopped Bit 7: Receive Buffer Unavailable Bit 8:\r
+ * Receive Process Stopped Bit 10: Ear1y Transmit Interrupt Bit 12: Fatal Bus Error Only unmasked\r
+ * bits affect the Abnormal Interrupt Summary bit.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_STAT_AIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK (0x8000U)\r
+#define ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT (15U)\r
+/*! NIS - Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the\r
+ * following bits when the corresponding interrupt bits are enabled in the DMA Channel Interrupt\r
+ * Enable register Table 778: Bit 0: Transmit Interrupt Bit 2: Transmit Buffer Unavailable Bit 6:\r
+ * Receive Interrupt Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which\r
+ * interrupt enable is set in DMA Channel Interrupt Enable register Table 778) affect the Normal\r
+ * Interrupt Summary bit.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_STAT_NIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_STAT_EB_MASK (0x70000U)\r
+#define ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT (16U)\r
+/*! EB - DMA Error Bits This field indicates the type of error that caused a Bus Error.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_STAT_EB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_EB_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_DMA_CH_DMA_CHX_STAT */\r
+#define ENET_DMA_CH_DMA_CHX_STAT_COUNT (2U)\r
+\r
+/*! @name DMA_CH_DMA_CHX_MISS_FRAME_CNT - Channelx missed frame count. */\r
+/*! @{ */\r
+#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_MASK (0x7FFU)\r
+#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT (0U)\r
+/*! MFC - Dropped packet counters.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT)) & ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_MASK)\r
+#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK (0x8000U)\r
+#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT (15U)\r
+/*! MFCO - Overflow status of the MFC counter.\r
+ */\r
+#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT)) & ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK)\r
+/*! @} */\r
+\r
+/* The count of ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT */\r
+#define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_COUNT (2U)\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group ENET_Register_Masks */\r
+\r
+\r
+/* ENET - Peripheral instance base addresses */\r
+/** Peripheral ENET base address */\r
+#define ENET_BASE (0x40092000u)\r
+/** Peripheral ENET base pointer */\r
+#define ENET ((ENET_Type *)ENET_BASE)\r
+/** Array initializer of ENET peripheral base addresses */\r
+#define ENET_BASE_ADDRS { ENET_BASE }\r
+/** Array initializer of ENET peripheral base pointers */\r
+#define ENET_BASE_PTRS { ENET }\r
+/** Interrupt vectors for the ENET peripheral type */\r
+#define ENET_IRQS { ETHERNET_IRQn }\r
+#define ENET_PMT_IRQS { ETHERNET_PMT_IRQn }\r
+#define ENET_MACLP_IRQS { ETHERNET_MACLP_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group ENET_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- FLEXCOMM Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** FLEXCOMM - Register Layout Typedef */\r
+typedef struct {\r
+ uint8_t RESERVED_0[4088];\r
+ __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */\r
+ __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */\r
+} FLEXCOMM_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- FLEXCOMM Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name PSELID - Peripheral Select and Flexcomm ID register. */\r
+/*! @{ */\r
+#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U)\r
+#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U)\r
+/*! PERSEL - Peripheral Select. This field is writable by software.\r
+ * 0b000..No peripheral selected.\r
+ * 0b001..USART function selected.\r
+ * 0b010..SPI function selected.\r
+ * 0b011..I2C function selected.\r
+ * 0b100..I2S transmit function selected.\r
+ * 0b101..I2S receive function selected.\r
+ * 0b110..Reserved\r
+ * 0b111..Reserved\r
+ */\r
+#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK)\r
+#define FLEXCOMM_PSELID_LOCK_MASK (0x8U)\r
+#define FLEXCOMM_PSELID_LOCK_SHIFT (3U)\r
+/*! LOCK - Lock the peripheral select. This field is writable by software.\r
+ * 0b0..Peripheral select can be changed by software.\r
+ * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset.\r
+ */\r
+#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK)\r
+#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U)\r
+#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U)\r
+/*! USARTPRESENT - USART present indicator. This field is Read-only.\r
+ * 0b0..This Flexcomm does not include the USART function.\r
+ * 0b1..This Flexcomm includes the USART function.\r
+ */\r
+#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK)\r
+#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U)\r
+#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U)\r
+/*! SPIPRESENT - SPI present indicator. This field is Read-only.\r
+ * 0b0..This Flexcomm does not include the SPI function.\r
+ * 0b1..This Flexcomm includes the SPI function.\r
+ */\r
+#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK)\r
+#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U)\r
+#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U)\r
+/*! I2CPRESENT - I2C present indicator. This field is Read-only.\r
+ * 0b0..This Flexcomm does not include the I2C function.\r
+ * 0b1..This Flexcomm includes the I2C function.\r
+ */\r
+#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK)\r
+#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U)\r
+#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U)\r
+/*! I2SPRESENT - I 2S present indicator. This field is Read-only.\r
+ * 0b0..This Flexcomm does not include the I2S function.\r
+ * 0b1..This Flexcomm includes the I2S function.\r
+ */\r
+#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK)\r
+#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U)\r
+#define FLEXCOMM_PSELID_ID_SHIFT (12U)\r
+/*! ID - Flexcomm ID.\r
+ */\r
+#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK)\r
+/*! @} */\r
+\r
+/*! @name PID - Peripheral identification register. */\r
+/*! @{ */\r
+#define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U)\r
+#define FLEXCOMM_PID_Minor_Rev_SHIFT (8U)\r
+/*! Minor_Rev - Minor revision of module implementation.\r
+ */\r
+#define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK)\r
+#define FLEXCOMM_PID_Major_Rev_MASK (0xF000U)\r
+#define FLEXCOMM_PID_Major_Rev_SHIFT (12U)\r
+/*! Major_Rev - Major revision of module implementation.\r
+ */\r
+#define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK)\r
+#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U)\r
+#define FLEXCOMM_PID_ID_SHIFT (16U)\r
+/*! ID - Module identifier for the selected function.\r
+ */\r
+#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group FLEXCOMM_Register_Masks */\r
+\r
+\r
+/* FLEXCOMM - Peripheral instance base addresses */\r
+/** Peripheral FLEXCOMM0 base address */\r
+#define FLEXCOMM0_BASE (0x40086000u)\r
+/** Peripheral FLEXCOMM0 base pointer */\r
+#define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE)\r
+/** Peripheral FLEXCOMM1 base address */\r
+#define FLEXCOMM1_BASE (0x40087000u)\r
+/** Peripheral FLEXCOMM1 base pointer */\r
+#define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE)\r
+/** Peripheral FLEXCOMM2 base address */\r
+#define FLEXCOMM2_BASE (0x40088000u)\r
+/** Peripheral FLEXCOMM2 base pointer */\r
+#define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE)\r
+/** Peripheral FLEXCOMM3 base address */\r
+#define FLEXCOMM3_BASE (0x40089000u)\r
+/** Peripheral FLEXCOMM3 base pointer */\r
+#define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE)\r
+/** Peripheral FLEXCOMM4 base address */\r
+#define FLEXCOMM4_BASE (0x4008A000u)\r
+/** Peripheral FLEXCOMM4 base pointer */\r
+#define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE)\r
+/** Peripheral FLEXCOMM5 base address */\r
+#define FLEXCOMM5_BASE (0x40096000u)\r
+/** Peripheral FLEXCOMM5 base pointer */\r
+#define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE)\r
+/** Peripheral FLEXCOMM6 base address */\r
+#define FLEXCOMM6_BASE (0x40097000u)\r
+/** Peripheral FLEXCOMM6 base pointer */\r
+#define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE)\r
+/** Peripheral FLEXCOMM7 base address */\r
+#define FLEXCOMM7_BASE (0x40098000u)\r
+/** Peripheral FLEXCOMM7 base pointer */\r
+#define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE)\r
+/** Peripheral FLEXCOMM8 base address */\r
+#define FLEXCOMM8_BASE (0x40099000u)\r
+/** Peripheral FLEXCOMM8 base pointer */\r
+#define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE)\r
+/** Peripheral FLEXCOMM9 base address */\r
+#define FLEXCOMM9_BASE (0x4009A000u)\r
+/** Peripheral FLEXCOMM9 base pointer */\r
+#define FLEXCOMM9 ((FLEXCOMM_Type *)FLEXCOMM9_BASE)\r
+/** Peripheral FLEXCOMM10 base address */\r
+#define FLEXCOMM10_BASE (0x4009F000u)\r
+/** Peripheral FLEXCOMM10 base pointer */\r
+#define FLEXCOMM10 ((FLEXCOMM_Type *)FLEXCOMM10_BASE)\r
+/** Array initializer of FLEXCOMM peripheral base addresses */\r
+#define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE, FLEXCOMM9_BASE, FLEXCOMM10_BASE }\r
+/** Array initializer of FLEXCOMM peripheral base pointers */\r
+#define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, FLEXCOMM9, FLEXCOMM10 }\r
+/** Interrupt vectors for the FLEXCOMM peripheral type */\r
+#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn, FLEXCOMM10_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group FLEXCOMM_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- GINT Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** GINT - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */\r
+ uint8_t RESERVED_0[28];\r
+ __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */\r
+ uint8_t RESERVED_1[24];\r
+ __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */\r
+} GINT_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- GINT Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup GINT_Register_Masks GINT Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CTRL - GPIO grouped interrupt control register */\r
+/*! @{ */\r
+#define GINT_CTRL_INT_MASK (0x1U)\r
+#define GINT_CTRL_INT_SHIFT (0U)\r
+/*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.\r
+ * 0b0..No request. No interrupt request is pending.\r
+ * 0b1..Request active. Interrupt request is active.\r
+ */\r
+#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK)\r
+#define GINT_CTRL_COMB_MASK (0x2U)\r
+#define GINT_CTRL_COMB_SHIFT (1U)\r
+/*! COMB - Combine enabled inputs for group interrupt\r
+ * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity).\r
+ * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity).\r
+ */\r
+#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK)\r
+#define GINT_CTRL_TRIG_MASK (0x4U)\r
+#define GINT_CTRL_TRIG_SHIFT (2U)\r
+/*! TRIG - Group interrupt trigger\r
+ * 0b0..Edge-triggered.\r
+ * 0b1..Level-triggered.\r
+ */\r
+#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK)\r
+/*! @} */\r
+\r
+/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */\r
+/*! @{ */\r
+#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU)\r
+#define GINT_PORT_POL_POL_SHIFT (0U)\r
+/*! POL - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n\r
+ * of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to\r
+ * the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin\r
+ * contributes to the group interrupt.\r
+ */\r
+#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK)\r
+/*! @} */\r
+\r
+/* The count of GINT_PORT_POL */\r
+#define GINT_PORT_POL_COUNT (2U)\r
+\r
+/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */\r
+/*! @{ */\r
+#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU)\r
+#define GINT_PORT_ENA_ENA_SHIFT (0U)\r
+/*! ENA - Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the\r
+ * port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is\r
+ * enabled and contributes to the grouped interrupt.\r
+ */\r
+#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK)\r
+/*! @} */\r
+\r
+/* The count of GINT_PORT_ENA */\r
+#define GINT_PORT_ENA_COUNT (2U)\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group GINT_Register_Masks */\r
+\r
+\r
+/* GINT - Peripheral instance base addresses */\r
+/** Peripheral GINT0 base address */\r
+#define GINT0_BASE (0x40002000u)\r
+/** Peripheral GINT0 base pointer */\r
+#define GINT0 ((GINT_Type *)GINT0_BASE)\r
+/** Peripheral GINT1 base address */\r
+#define GINT1_BASE (0x40003000u)\r
+/** Peripheral GINT1 base pointer */\r
+#define GINT1 ((GINT_Type *)GINT1_BASE)\r
+/** Array initializer of GINT peripheral base addresses */\r
+#define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE }\r
+/** Array initializer of GINT peripheral base pointers */\r
+#define GINT_BASE_PTRS { GINT0, GINT1 }\r
+/** Interrupt vectors for the GINT peripheral type */\r
+#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group GINT_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- GPIO Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** GPIO - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint8_t B[6][32]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */\r
+ uint8_t RESERVED_0[3904];\r
+ __IO uint32_t W[6][32]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */\r
+ uint8_t RESERVED_1[3328];\r
+ __IO uint32_t DIR[6]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */\r
+ uint8_t RESERVED_2[104];\r
+ __IO uint32_t MASK[6]; /**< Mask register, array offset: 0x2080, array step: 0x4 */\r
+ uint8_t RESERVED_3[104];\r
+ __IO uint32_t PIN[6]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */\r
+ uint8_t RESERVED_4[104];\r
+ __IO uint32_t MPIN[6]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */\r
+ uint8_t RESERVED_5[104];\r
+ __IO uint32_t SET[6]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */\r
+ uint8_t RESERVED_6[104];\r
+ __O uint32_t CLR[6]; /**< Clear port, array offset: 0x2280, array step: 0x4 */\r
+ uint8_t RESERVED_7[104];\r
+ __O uint32_t NOT[6]; /**< Toggle port, array offset: 0x2300, array step: 0x4 */\r
+ uint8_t RESERVED_8[104];\r
+ __O uint32_t DIRSET[6]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */\r
+ uint8_t RESERVED_9[104];\r
+ __O uint32_t DIRCLR[6]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */\r
+ uint8_t RESERVED_10[104];\r
+ __O uint32_t DIRNOT[6]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */\r
+} GPIO_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- GPIO Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */\r
+/*! @{ */\r
+#define GPIO_B_PBYTE_MASK (0x1U)\r
+#define GPIO_B_PBYTE_SHIFT (0U)\r
+/*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function,\r
+ * except that pins configured as analog I/O always read as 0. One register for each port pin.\r
+ * Supported pins depends on the specific device and package. Write: loads the pin's output bit.\r
+ * One register for each port pin. Supported pins depends on the specific device and package.\r
+ */\r
+#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK)\r
+/*! @} */\r
+\r
+/* The count of GPIO_B */\r
+#define GPIO_B_COUNT (6U)\r
+\r
+/* The count of GPIO_B */\r
+#define GPIO_B_COUNT2 (32U)\r
+\r
+/*! @name W - Word pin registers for all port 0 and 1 GPIO pins */\r
+/*! @{ */\r
+#define GPIO_W_PWORD_MASK (0xFFFFFFFFU)\r
+#define GPIO_W_PWORD_SHIFT (0U)\r
+/*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is\r
+ * HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be\r
+ * read. Writing any value other than 0 will set the output bit. One register for each port pin.\r
+ * Supported pins depends on the specific device and package.\r
+ */\r
+#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK)\r
+/*! @} */\r
+\r
+/* The count of GPIO_W */\r
+#define GPIO_W_COUNT (6U)\r
+\r
+/* The count of GPIO_W */\r
+#define GPIO_W_COUNT2 (32U)\r
+\r
+/*! @name DIR - Direction registers */\r
+/*! @{ */\r
+#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU)\r
+#define GPIO_DIR_DIRP_SHIFT (0U)\r
+/*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported\r
+ * pins depends on the specific device and package. 0 = input. 1 = output.\r
+ */\r
+#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK)\r
+/*! @} */\r
+\r
+/* The count of GPIO_DIR */\r
+#define GPIO_DIR_COUNT (6U)\r
+\r
+/*! @name MASK - Mask register */\r
+/*! @{ */\r
+#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU)\r
+#define GPIO_MASK_MASKP_SHIFT (0U)\r
+/*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 =\r
+ * PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 =\r
+ * Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit\r
+ * not affected.\r
+ */\r
+#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK)\r
+/*! @} */\r
+\r
+/* The count of GPIO_MASK */\r
+#define GPIO_MASK_COUNT (6U)\r
+\r
+/*! @name PIN - Port pin register */\r
+/*! @{ */\r
+#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU)\r
+#define GPIO_PIN_PORT_SHIFT (0U)\r
+/*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported\r
+ * pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit.\r
+ * 1 = Read: pin is high; write: set output bit.\r
+ */\r
+#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK)\r
+/*! @} */\r
+\r
+/* The count of GPIO_PIN */\r
+#define GPIO_PIN_COUNT (6U)\r
+\r
+/*! @name MPIN - Masked port register */\r
+/*! @{ */\r
+#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU)\r
+#define GPIO_MPIN_MPORTP_SHIFT (0U)\r
+/*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on\r
+ * the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK\r
+ * register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1\r
+ * = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit\r
+ * if the corresponding bit in the MASK register is 0.\r
+ */\r
+#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK)\r
+/*! @} */\r
+\r
+/* The count of GPIO_MPIN */\r
+#define GPIO_MPIN_COUNT (6U)\r
+\r
+/*! @name SET - Write: Set register for port Read: output bits for port */\r
+/*! @{ */\r
+#define GPIO_SET_SETP_MASK (0xFFFFFFFFU)\r
+#define GPIO_SET_SETP_SHIFT (0U)\r
+/*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on\r
+ * the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output\r
+ * bit; write: set output bit.\r
+ */\r
+#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)\r
+/*! @} */\r
+\r
+/* The count of GPIO_SET */\r
+#define GPIO_SET_COUNT (6U)\r
+\r
+/*! @name CLR - Clear port */\r
+/*! @{ */\r
+#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU)\r
+#define GPIO_CLR_CLRP_SHIFT (0U)\r
+/*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the\r
+ * specific device and package. 0 = No operation. 1 = Clear output bit.\r
+ */\r
+#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK)\r
+/*! @} */\r
+\r
+/* The count of GPIO_CLR */\r
+#define GPIO_CLR_COUNT (6U)\r
+\r
+/*! @name NOT - Toggle port */\r
+/*! @{ */\r
+#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU)\r
+#define GPIO_NOT_NOTP_SHIFT (0U)\r
+/*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the\r
+ * specific device and package. 0 = no operation. 1 = Toggle output bit.\r
+ */\r
+#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK)\r
+/*! @} */\r
+\r
+/* The count of GPIO_NOT */\r
+#define GPIO_NOT_COUNT (6U)\r
+\r
+/*! @name DIRSET - Set pin direction bits for port */\r
+/*! @{ */\r
+#define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU)\r
+#define GPIO_DIRSET_DIRSETP_SHIFT (0U)\r
+/*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on\r
+ * the specific device and package. 0 = No operation. 1 = Set direction bit.\r
+ */\r
+#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK)\r
+/*! @} */\r
+\r
+/* The count of GPIO_DIRSET */\r
+#define GPIO_DIRSET_COUNT (6U)\r
+\r
+/*! @name DIRCLR - Clear pin direction bits for port */\r
+/*! @{ */\r
+#define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU)\r
+#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U)\r
+/*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on\r
+ * the specific device and package. 0 = No operation. 1 = Clear direction bit.\r
+ */\r
+#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK)\r
+/*! @} */\r
+\r
+/* The count of GPIO_DIRCLR */\r
+#define GPIO_DIRCLR_COUNT (6U)\r
+\r
+/*! @name DIRNOT - Toggle pin direction bits for port */\r
+/*! @{ */\r
+#define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU)\r
+#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U)\r
+/*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends\r
+ * on the specific device and package. 0 = no operation. 1 = Toggle direction bit.\r
+ */\r
+#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK)\r
+/*! @} */\r
+\r
+/* The count of GPIO_DIRNOT */\r
+#define GPIO_DIRNOT_COUNT (6U)\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group GPIO_Register_Masks */\r
+\r
+\r
+/* GPIO - Peripheral instance base addresses */\r
+/** Peripheral GPIO base address */\r
+#define GPIO_BASE (0x4008C000u)\r
+/** Peripheral GPIO base pointer */\r
+#define GPIO ((GPIO_Type *)GPIO_BASE)\r
+/** Array initializer of GPIO peripheral base addresses */\r
+#define GPIO_BASE_ADDRS { GPIO_BASE }\r
+/** Array initializer of GPIO peripheral base pointers */\r
+#define GPIO_BASE_PTRS { GPIO }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group GPIO_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- I2C Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** I2C - Register Layout Typedef */\r
+typedef struct {\r
+ uint8_t RESERVED_0[2048];\r
+ __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */\r
+ __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */\r
+ __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */\r
+ __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */\r
+ __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */\r
+ __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */\r
+ __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */\r
+ uint8_t RESERVED_1[4];\r
+ __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */\r
+ __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */\r
+ __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */\r
+ uint8_t RESERVED_2[20];\r
+ __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */\r
+ __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */\r
+ __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */\r
+ __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */\r
+ uint8_t RESERVED_3[36];\r
+ __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */\r
+ uint8_t RESERVED_4[1912];\r
+ __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */\r
+} I2C_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- I2C Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup I2C_Register_Masks I2C Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CFG - Configuration for shared functions. */\r
+/*! @{ */\r
+#define I2C_CFG_MSTEN_MASK (0x1U)\r
+#define I2C_CFG_MSTEN_SHIFT (0U)\r
+/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not\r
+ * changed, but the Master function is internally reset.\r
+ * 0b0..Disabled. The I2C Master function is disabled.\r
+ * 0b1..Enabled. The I2C Master function is enabled.\r
+ */\r
+#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)\r
+#define I2C_CFG_SLVEN_MASK (0x2U)\r
+#define I2C_CFG_SLVEN_SHIFT (1U)\r
+/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not\r
+ * changed, but the Slave function is internally reset.\r
+ * 0b0..Disabled. The I2C slave function is disabled.\r
+ * 0b1..Enabled. The I2C slave function is enabled.\r
+ */\r
+#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)\r
+#define I2C_CFG_MONEN_MASK (0x4U)\r
+#define I2C_CFG_MONEN_SHIFT (2U)\r
+/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not\r
+ * changed, but the Monitor function is internally reset.\r
+ * 0b0..Disabled. The I2C Monitor function is disabled.\r
+ * 0b1..Enabled. The I2C Monitor function is enabled.\r
+ */\r
+#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)\r
+#define I2C_CFG_TIMEOUTEN_MASK (0x8U)\r
+#define I2C_CFG_TIMEOUTEN_SHIFT (3U)\r
+/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset.\r
+ * 0b0..Disabled. Time-out function is disabled.\r
+ * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause\r
+ * interrupts if they are enabled. Typically, only one time-out will be used in a system.\r
+ */\r
+#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)\r
+#define I2C_CFG_MONCLKSTR_MASK (0x10U)\r
+#define I2C_CFG_MONCLKSTR_SHIFT (4U)\r
+/*! MONCLKSTR - Monitor function Clock Stretching.\r
+ * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able\r
+ * to read data provided by the Monitor function before it is overwritten. This mode may be used when\r
+ * non-invasive monitoring is critical.\r
+ * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can\r
+ * read all incoming data supplied by the Monitor function.\r
+ */\r
+#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)\r
+#define I2C_CFG_HSCAPABLE_MASK (0x20U)\r
+#define I2C_CFG_HSCAPABLE_SHIFT (5U)\r
+/*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive\r
+ * and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies\r
+ * to all functions: Master, Slave, and Monitor.\r
+ * 0b0..Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the\r
+ * extent that the pin electronics support these modes. Any changes that need to be made to the pin controls,\r
+ * such as changing the drive strength or filtering, must be made by software via the IOCON register associated\r
+ * with each I2C pin,\r
+ * 0b1..High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support\r
+ * High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more\r
+ * information.\r
+ */\r
+#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK)\r
+/*! @} */\r
+\r
+/*! @name STAT - Status register for Master, Slave, and Monitor functions. */\r
+/*! @{ */\r
+#define I2C_STAT_MSTPENDING_MASK (0x1U)\r
+#define I2C_STAT_MSTPENDING_SHIFT (0U)\r
+/*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on\r
+ * the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what\r
+ * type of software service if any the master expects. This flag will cause an interrupt when set\r
+ * if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling\r
+ * an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle\r
+ * state, and no communication is needed, mask this interrupt.\r
+ * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.\r
+ * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the\r
+ * idle state, it is waiting to receive or transmit data or the NACK bit.\r
+ */\r
+#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)\r
+#define I2C_STAT_MSTSTATE_MASK (0xEU)\r
+#define I2C_STAT_MSTSTATE_SHIFT (1U)\r
+/*! MSTSTATE - Master State code. The master state code reflects the master state when the\r
+ * MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field\r
+ * indicates a specific required service for the Master function. All other values are reserved. See\r
+ * Table 400 for details of state values and appropriate responses.\r
+ * 0b000..Idle. The Master function is available to be used for a new transaction.\r
+ * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.\r
+ * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.\r
+ * 0b011..NACK Address. Slave NACKed address.\r
+ * 0b100..NACK Data. Slave NACKed transmitted data.\r
+ */\r
+#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK)\r
+#define I2C_STAT_MSTARBLOSS_MASK (0x10U)\r
+#define I2C_STAT_MSTARBLOSS_SHIFT (4U)\r
+/*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to\r
+ * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.\r
+ * 0b0..No Arbitration Loss has occurred.\r
+ * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master\r
+ * function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing,\r
+ * or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.\r
+ */\r
+#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK)\r
+#define I2C_STAT_MSTSTSTPERR_MASK (0x40U)\r
+#define I2C_STAT_MSTSTSTPERR_SHIFT (6U)\r
+/*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to\r
+ * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.\r
+ * 0b0..No Start/Stop Error has occurred.\r
+ * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is\r
+ * not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an\r
+ * idle state, no action is required. A request for a Start could be made, or software could attempt to insure\r
+ * that the bus has not stalled.\r
+ */\r
+#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK)\r
+#define I2C_STAT_SLVPENDING_MASK (0x100U)\r
+#define I2C_STAT_SLVPENDING_SHIFT (8U)\r
+/*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue\r
+ * communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if\r
+ * enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the\r
+ * SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is\r
+ * automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time\r
+ * when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section\r
+ * 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are\r
+ * detected automatically. Due to the requirements of the HS I2C specification, slave addresses must\r
+ * also be detected automatically, since the address must be acknowledged before the clock can be\r
+ * stretched.\r
+ * 0b0..In progress. The Slave function does not currently need service.\r
+ * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.\r
+ */\r
+#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK)\r
+#define I2C_STAT_SLVSTATE_MASK (0x600U)\r
+#define I2C_STAT_SLVSTATE_SHIFT (9U)\r
+/*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for\r
+ * the Slave function. All other values are reserved. See Table 401 for state values and actions.\r
+ * note that the occurrence of some states and how they are handled are affected by DMA mode and\r
+ * Automatic Operation modes.\r
+ * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.\r
+ * 0b01..Slave receive. Received data is available (Slave Receiver mode).\r
+ * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode).\r
+ */\r
+#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK)\r
+#define I2C_STAT_SLVNOTSTR_MASK (0x800U)\r
+#define I2C_STAT_SLVNOTSTR_SHIFT (11U)\r
+/*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock.\r
+ * This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave\r
+ * operation. This read-only flag reflects the slave function status in real time.\r
+ * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.\r
+ * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or\r
+ * Power-down mode could be entered at this time.\r
+ */\r
+#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK)\r
+#define I2C_STAT_SLVIDX_MASK (0x3000U)\r
+#define I2C_STAT_SLVIDX_SHIFT (12U)\r
+/*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been\r
+ * selected by receiving an address that matches one of the slave addresses defined by any enabled\r
+ * slave address registers, and provides an identification of the address that was matched. It is\r
+ * possible that more than one address could be matched, but only one match can be reported here.\r
+ * 0b00..Address 0. Slave address 0 was matched.\r
+ * 0b01..Address 1. Slave address 1 was matched.\r
+ * 0b10..Address 2. Slave address 2 was matched.\r
+ * 0b11..Address 3. Slave address 3 was matched.\r
+ */\r
+#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK)\r
+#define I2C_STAT_SLVSEL_MASK (0x4000U)\r
+#define I2C_STAT_SLVSEL_SHIFT (14U)\r
+/*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave\r
+ * function to acknowledge the address, or when the address has been automatically acknowledged.\r
+ * It is cleared when another address cycle presents an address that does not match an enabled\r
+ * address on the Slave function, when slave software decides to NACK a matched address, when\r
+ * there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of\r
+ * Automatic Operation. SLVSEL is not cleared if software NACKs data.\r
+ * 0b0..Not selected. The Slave function is not currently selected.\r
+ * 0b1..Selected. The Slave function is currently selected.\r
+ */\r
+#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK)\r
+#define I2C_STAT_SLVDESEL_MASK (0x8000U)\r
+#define I2C_STAT_SLVDESEL_SHIFT (15U)\r
+/*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via\r
+ * INTENSET. This flag can be cleared by writing a 1 to this bit.\r
+ * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently\r
+ * selected. That information can be found in the SLVSEL flag.\r
+ * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag\r
+ * changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.\r
+ */\r
+#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK)\r
+#define I2C_STAT_MONRDY_MASK (0x10000U)\r
+#define I2C_STAT_MONRDY_SHIFT (16U)\r
+/*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read.\r
+ * 0b0..No data. The Monitor function does not currently have data available.\r
+ * 0b1..Data waiting. The Monitor function has data waiting to be read.\r
+ */\r
+#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK)\r
+#define I2C_STAT_MONOV_MASK (0x20000U)\r
+#define I2C_STAT_MONOV_SHIFT (17U)\r
+/*! MONOV - Monitor Overflow flag.\r
+ * 0b0..No overrun. Monitor data has not overrun.\r
+ * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not\r
+ * enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.\r
+ */\r
+#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK)\r
+#define I2C_STAT_MONACTIVE_MASK (0x40000U)\r
+#define I2C_STAT_MONACTIVE_SHIFT (18U)\r
+/*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to\r
+ * be active. Active is defined here as when some Master is on the bus: a bus Start has occurred\r
+ * more recently than a bus Stop.\r
+ * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive.\r
+ * 0b1..Active. The Monitor function considers the I2C bus to be active.\r
+ */\r
+#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK)\r
+#define I2C_STAT_MONIDLE_MASK (0x80000U)\r
+#define I2C_STAT_MONIDLE_SHIFT (19U)\r
+/*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change\r
+ * from active to inactive. This can be used by software to decide when to process data\r
+ * accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the\r
+ * INTENSET register. The flag can be cleared by writing a 1 to this bit.\r
+ * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software.\r
+ * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.\r
+ */\r
+#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK)\r
+#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U)\r
+#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U)\r
+/*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been\r
+ * longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock\r
+ * edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus\r
+ * is idle.\r
+ * 0b0..No time-out. I2C bus events have not caused a time-out.\r
+ * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.\r
+ */\r
+#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK)\r
+#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U)\r
+#define I2C_STAT_SCLTIMEOUT_SHIFT (25U)\r
+/*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the\r
+ * time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.\r
+ * 0b0..No time-out. SCL low time has not caused a time-out.\r
+ * 0b1..Time-out. SCL low time has caused a time-out.\r
+ */\r
+#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTENSET - Interrupt Enable Set and read register. */\r
+/*! @{ */\r
+#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U)\r
+#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U)\r
+/*! MSTPENDINGEN - Master Pending interrupt Enable.\r
+ * 0b0..Disabled. The MstPending interrupt is disabled.\r
+ * 0b1..Enabled. The MstPending interrupt is enabled.\r
+ */\r
+#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK)\r
+#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U)\r
+#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U)\r
+/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable.\r
+ * 0b0..Disabled. The MstArbLoss interrupt is disabled.\r
+ * 0b1..Enabled. The MstArbLoss interrupt is enabled.\r
+ */\r
+#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK)\r
+#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U)\r
+#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U)\r
+/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable.\r
+ * 0b0..Disabled. The MstStStpErr interrupt is disabled.\r
+ * 0b1..Enabled. The MstStStpErr interrupt is enabled.\r
+ */\r
+#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK)\r
+#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U)\r
+#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U)\r
+/*! SLVPENDINGEN - Slave Pending interrupt Enable.\r
+ * 0b0..Disabled. The SlvPending interrupt is disabled.\r
+ * 0b1..Enabled. The SlvPending interrupt is enabled.\r
+ */\r
+#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK)\r
+#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U)\r
+#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U)\r
+/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable.\r
+ * 0b0..Disabled. The SlvNotStr interrupt is disabled.\r
+ * 0b1..Enabled. The SlvNotStr interrupt is enabled.\r
+ */\r
+#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK)\r
+#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U)\r
+#define I2C_INTENSET_SLVDESELEN_SHIFT (15U)\r
+/*! SLVDESELEN - Slave Deselect interrupt Enable.\r
+ * 0b0..Disabled. The SlvDeSel interrupt is disabled.\r
+ * 0b1..Enabled. The SlvDeSel interrupt is enabled.\r
+ */\r
+#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK)\r
+#define I2C_INTENSET_MONRDYEN_MASK (0x10000U)\r
+#define I2C_INTENSET_MONRDYEN_SHIFT (16U)\r
+/*! MONRDYEN - Monitor data Ready interrupt Enable.\r
+ * 0b0..Disabled. The MonRdy interrupt is disabled.\r
+ * 0b1..Enabled. The MonRdy interrupt is enabled.\r
+ */\r
+#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK)\r
+#define I2C_INTENSET_MONOVEN_MASK (0x20000U)\r
+#define I2C_INTENSET_MONOVEN_SHIFT (17U)\r
+/*! MONOVEN - Monitor Overrun interrupt Enable.\r
+ * 0b0..Disabled. The MonOv interrupt is disabled.\r
+ * 0b1..Enabled. The MonOv interrupt is enabled.\r
+ */\r
+#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK)\r
+#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U)\r
+#define I2C_INTENSET_MONIDLEEN_SHIFT (19U)\r
+/*! MONIDLEEN - Monitor Idle interrupt Enable.\r
+ * 0b0..Disabled. The MonIdle interrupt is disabled.\r
+ * 0b1..Enabled. The MonIdle interrupt is enabled.\r
+ */\r
+#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK)\r
+#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U)\r
+#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U)\r
+/*! EVENTTIMEOUTEN - Event time-out interrupt Enable.\r
+ * 0b0..Disabled. The Event time-out interrupt is disabled.\r
+ * 0b1..Enabled. The Event time-out interrupt is enabled.\r
+ */\r
+#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK)\r
+#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U)\r
+#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U)\r
+/*! SCLTIMEOUTEN - SCL time-out interrupt Enable.\r
+ * 0b0..Disabled. The SCL time-out interrupt is disabled.\r
+ * 0b1..Enabled. The SCL time-out interrupt is enabled.\r
+ */\r
+#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTENCLR - Interrupt Enable Clear register. */\r
+/*! @{ */\r
+#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U)\r
+#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U)\r
+/*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding\r
+ * bit in the INTENSET register if implemented.\r
+ */\r
+#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK)\r
+#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U)\r
+#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U)\r
+/*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear.\r
+ */\r
+#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK)\r
+#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U)\r
+#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U)\r
+/*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear.\r
+ */\r
+#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK)\r
+#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U)\r
+#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U)\r
+/*! SLVPENDINGCLR - Slave Pending interrupt clear.\r
+ */\r
+#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK)\r
+#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U)\r
+#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U)\r
+/*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear.\r
+ */\r
+#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK)\r
+#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U)\r
+#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U)\r
+/*! SLVDESELCLR - Slave Deselect interrupt clear.\r
+ */\r
+#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK)\r
+#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U)\r
+#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U)\r
+/*! MONRDYCLR - Monitor data Ready interrupt clear.\r
+ */\r
+#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK)\r
+#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U)\r
+#define I2C_INTENCLR_MONOVCLR_SHIFT (17U)\r
+/*! MONOVCLR - Monitor Overrun interrupt clear.\r
+ */\r
+#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK)\r
+#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U)\r
+#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U)\r
+/*! MONIDLECLR - Monitor Idle interrupt clear.\r
+ */\r
+#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK)\r
+#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U)\r
+#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U)\r
+/*! EVENTTIMEOUTCLR - Event time-out interrupt clear.\r
+ */\r
+#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK)\r
+#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U)\r
+#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U)\r
+/*! SCLTIMEOUTCLR - SCL time-out interrupt clear.\r
+ */\r
+#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK)\r
+/*! @} */\r
+\r
+/*! @name TIMEOUT - Time-out value register. */\r
+/*! @{ */\r
+#define I2C_TIMEOUT_TOMIN_MASK (0xFU)\r
+#define I2C_TIMEOUT_TOMIN_SHIFT (0U)\r
+/*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum\r
+ * time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks.\r
+ */\r
+#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK)\r
+#define I2C_TIMEOUT_TO_MASK (0xFFF0U)\r
+#define I2C_TIMEOUT_TO_SHIFT (4U)\r
+/*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C\r
+ * function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation,\r
+ * disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A\r
+ * time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after\r
+ * 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the\r
+ * I2C function clock.\r
+ */\r
+#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK)\r
+/*! @} */\r
+\r
+/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */\r
+/*! @{ */\r
+#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU)\r
+#define I2C_CLKDIV_DIVVAL_SHIFT (0U)\r
+/*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that\r
+ * need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 =\r
+ * FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is\r
+ * divided by 65,536 before use.\r
+ */\r
+#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */\r
+/*! @{ */\r
+#define I2C_INTSTAT_MSTPENDING_MASK (0x1U)\r
+#define I2C_INTSTAT_MSTPENDING_SHIFT (0U)\r
+/*! MSTPENDING - Master Pending.\r
+ */\r
+#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK)\r
+#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U)\r
+#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U)\r
+/*! MSTARBLOSS - Master Arbitration Loss flag.\r
+ */\r
+#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK)\r
+#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U)\r
+#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U)\r
+/*! MSTSTSTPERR - Master Start/Stop Error flag.\r
+ */\r
+#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK)\r
+#define I2C_INTSTAT_SLVPENDING_MASK (0x100U)\r
+#define I2C_INTSTAT_SLVPENDING_SHIFT (8U)\r
+/*! SLVPENDING - Slave Pending.\r
+ */\r
+#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK)\r
+#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U)\r
+#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U)\r
+/*! SLVNOTSTR - Slave Not Stretching status.\r
+ */\r
+#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK)\r
+#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U)\r
+#define I2C_INTSTAT_SLVDESEL_SHIFT (15U)\r
+/*! SLVDESEL - Slave Deselected flag.\r
+ */\r
+#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK)\r
+#define I2C_INTSTAT_MONRDY_MASK (0x10000U)\r
+#define I2C_INTSTAT_MONRDY_SHIFT (16U)\r
+/*! MONRDY - Monitor Ready.\r
+ */\r
+#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK)\r
+#define I2C_INTSTAT_MONOV_MASK (0x20000U)\r
+#define I2C_INTSTAT_MONOV_SHIFT (17U)\r
+/*! MONOV - Monitor Overflow flag.\r
+ */\r
+#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK)\r
+#define I2C_INTSTAT_MONIDLE_MASK (0x80000U)\r
+#define I2C_INTSTAT_MONIDLE_SHIFT (19U)\r
+/*! MONIDLE - Monitor Idle flag.\r
+ */\r
+#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK)\r
+#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U)\r
+#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U)\r
+/*! EVENTTIMEOUT - Event time-out Interrupt flag.\r
+ */\r
+#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK)\r
+#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U)\r
+#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U)\r
+/*! SCLTIMEOUT - SCL time-out Interrupt flag.\r
+ */\r
+#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK)\r
+/*! @} */\r
+\r
+/*! @name MSTCTL - Master control register. */\r
+/*! @{ */\r
+#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U)\r
+#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U)\r
+/*! MSTCONTINUE - Master Continue. This bit is write-only.\r
+ * 0b0..No effect.\r
+ * 0b1..Continue. Informs the Master function to continue to the next operation. This must done after writing\r
+ * transmit data, reading received data, or any other housekeeping related to the next bus operation.\r
+ */\r
+#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK)\r
+#define I2C_MSTCTL_MSTSTART_MASK (0x2U)\r
+#define I2C_MSTCTL_MSTSTART_SHIFT (1U)\r
+/*! MSTSTART - Master Start control. This bit is write-only.\r
+ * 0b0..No effect.\r
+ * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time.\r
+ */\r
+#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK)\r
+#define I2C_MSTCTL_MSTSTOP_MASK (0x4U)\r
+#define I2C_MSTCTL_MSTSTOP_SHIFT (2U)\r
+/*! MSTSTOP - Master Stop control. This bit is write-only.\r
+ * 0b0..No effect.\r
+ * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave\r
+ * if the master is receiving data from the slave (Master Receiver mode).\r
+ */\r
+#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK)\r
+#define I2C_MSTCTL_MSTDMA_MASK (0x8U)\r
+#define I2C_MSTCTL_MSTDMA_SHIFT (3U)\r
+/*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type\r
+ * operations such as Start, address, Stop, and address match must always be done with software,\r
+ * typically via an interrupt. Address acknowledgement must also be done by software except when\r
+ * the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by\r
+ * hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA\r
+ * must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is\r
+ * read/write.\r
+ * 0b0..Disable. No DMA requests are generated for master operation.\r
+ * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating\r
+ * Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.\r
+ */\r
+#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK)\r
+/*! @} */\r
+\r
+/*! @name MSTTIME - Master timing configuration. */\r
+/*! @{ */\r
+#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U)\r
+#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U)\r
+/*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this\r
+ * master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This\r
+ * corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters\r
+ * tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW.\r
+ * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.\r
+ * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.\r
+ * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.\r
+ * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.\r
+ * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.\r
+ * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.\r
+ * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.\r
+ * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.\r
+ */\r
+#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK)\r
+#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U)\r
+#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U)\r
+/*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this\r
+ * master on SCL. Other masters in a multi-master system could shorten this time. This\r
+ * corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters\r
+ * tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.\r
+ * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.\r
+ * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .\r
+ * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.\r
+ * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.\r
+ * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.\r
+ * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.\r
+ * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.\r
+ * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.\r
+ */\r
+#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK)\r
+/*! @} */\r
+\r
+/*! @name MSTDAT - Combined Master receiver and transmitter data register. */\r
+/*! @{ */\r
+#define I2C_MSTDAT_DATA_MASK (0xFFU)\r
+#define I2C_MSTDAT_DATA_SHIFT (0U)\r
+/*! DATA - Master function data register. Read: read the most recently received data for the Master\r
+ * function. Write: transmit data using the Master function.\r
+ */\r
+#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK)\r
+/*! @} */\r
+\r
+/*! @name SLVCTL - Slave control register. */\r
+/*! @{ */\r
+#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U)\r
+#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U)\r
+/*! SLVCONTINUE - Slave Continue.\r
+ * 0b0..No effect.\r
+ * 0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag\r
+ * in the STAT register. This must be done after writing transmit data, reading received data, or any other\r
+ * housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE\r
+ * should not be set unless SLVPENDING = 1.\r
+ */\r
+#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK)\r
+#define I2C_SLVCTL_SLVNACK_MASK (0x2U)\r
+#define I2C_SLVCTL_SLVNACK_SHIFT (1U)\r
+/*! SLVNACK - Slave NACK.\r
+ * 0b0..No effect.\r
+ * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode).\r
+ */\r
+#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK)\r
+#define I2C_SLVCTL_SLVDMA_MASK (0x8U)\r
+#define I2C_SLVCTL_SLVDMA_SHIFT (3U)\r
+/*! SLVDMA - Slave DMA enable.\r
+ * 0b0..Disabled. No DMA requests are issued for Slave mode operation.\r
+ * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception.\r
+ */\r
+#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK)\r
+#define I2C_SLVCTL_AUTOACK_MASK (0x100U)\r
+#define I2C_SLVCTL_AUTOACK_SHIFT (8U)\r
+/*! AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches\r
+ * SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA\r
+ * to allow processing of the data without intervention. If this bit is clear and a header\r
+ * matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or\r
+ * interrupt.\r
+ * 0b0..Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching\r
+ * address is received. If AUTONACK = 1, received addresses are NACKed (ignored).\r
+ * 0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately,\r
+ * allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does\r
+ * not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK\r
+ * is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated.\r
+ */\r
+#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK)\r
+#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U)\r
+#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U)\r
+/*! AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write\r
+ * request on the next header with an address matching SLVADR0. Since DMA needs to be configured to\r
+ * match the transfer direction, the direction needs to be specified. This bit allows a direction to\r
+ * be chosen for the next operation.\r
+ * 0b0..The expected next operation in Automatic Mode is an I2C write.\r
+ * 0b1..The expected next operation in Automatic Mode is an I2C read.\r
+ */\r
+#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK)\r
+/*! @} */\r
+\r
+/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */\r
+/*! @{ */\r
+#define I2C_SLVDAT_DATA_MASK (0xFFU)\r
+#define I2C_SLVDAT_DATA_SHIFT (0U)\r
+/*! DATA - Slave function data register. Read: read the most recently received data for the Slave\r
+ * function. Write: transmit data using the Slave function.\r
+ */\r
+#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK)\r
+/*! @} */\r
+\r
+/*! @name SLVADR - Slave address register. */\r
+/*! @{ */\r
+#define I2C_SLVADR_SADISABLE_MASK (0x1U)\r
+#define I2C_SLVADR_SADISABLE_SHIFT (0U)\r
+/*! SADISABLE - Slave Address n Disable.\r
+ * 0b0..Enabled. Slave Address n is enabled.\r
+ * 0b1..Ignored Slave Address n is ignored.\r
+ */\r
+#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK)\r
+#define I2C_SLVADR_SLVADR_MASK (0xFEU)\r
+#define I2C_SLVADR_SLVADR_SHIFT (1U)\r
+/*! SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled.\r
+ */\r
+#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK)\r
+#define I2C_SLVADR_AUTONACK_MASK (0x8000U)\r
+#define I2C_SLVADR_AUTONACK_SHIFT (15U)\r
+/*! AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows\r
+ * software to ignore I2C traffic while handling previous I2C data or other operations.\r
+ * 0b0..Normal operation, matching I2C addresses are not ignored.\r
+ * 0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches\r
+ * SLVADRn, and AUTOMATCHREAD matches the direction.\r
+ */\r
+#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK)\r
+/*! @} */\r
+\r
+/* The count of I2C_SLVADR */\r
+#define I2C_SLVADR_COUNT (4U)\r
+\r
+/*! @name SLVQUAL0 - Slave Qualification for address 0. */\r
+/*! @{ */\r
+#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U)\r
+#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U)\r
+/*! QUALMODE0 - Qualify mode for slave address 0.\r
+ * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.\r
+ * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.\r
+ */\r
+#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK)\r
+#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU)\r
+#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U)\r
+/*! SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to\r
+ * be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is\r
+ * set to 1 will cause an automatic match of the corresponding bit of the received address when it\r
+ * is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for\r
+ * address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0\r
+ * (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]).\r
+ */\r
+#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK)\r
+/*! @} */\r
+\r
+/*! @name MONRXDAT - Monitor receiver data register. */\r
+/*! @{ */\r
+#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU)\r
+#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U)\r
+/*! MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins.\r
+ */\r
+#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK)\r
+#define I2C_MONRXDAT_MONSTART_MASK (0x100U)\r
+#define I2C_MONRXDAT_MONSTART_SHIFT (8U)\r
+/*! MONSTART - Monitor Received Start.\r
+ * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus.\r
+ * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus.\r
+ */\r
+#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK)\r
+#define I2C_MONRXDAT_MONRESTART_MASK (0x200U)\r
+#define I2C_MONRXDAT_MONRESTART_SHIFT (9U)\r
+/*! MONRESTART - Monitor Received Repeated Start.\r
+ * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.\r
+ * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.\r
+ */\r
+#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK)\r
+#define I2C_MONRXDAT_MONNACK_MASK (0x400U)\r
+#define I2C_MONRXDAT_MONNACK_SHIFT (10U)\r
+/*! MONNACK - Monitor Received NACK.\r
+ * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.\r
+ * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.\r
+ */\r
+#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK)\r
+/*! @} */\r
+\r
+/*! @name ID - Peripheral identification register. */\r
+/*! @{ */\r
+#define I2C_ID_APERTURE_MASK (0xFFU)\r
+#define I2C_ID_APERTURE_SHIFT (0U)\r
+/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.\r
+ */\r
+#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK)\r
+#define I2C_ID_MINOR_REV_MASK (0xF00U)\r
+#define I2C_ID_MINOR_REV_SHIFT (8U)\r
+/*! MINOR_REV - Minor revision of module implementation.\r
+ */\r
+#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK)\r
+#define I2C_ID_MAJOR_REV_MASK (0xF000U)\r
+#define I2C_ID_MAJOR_REV_SHIFT (12U)\r
+/*! MAJOR_REV - Major revision of module implementation.\r
+ */\r
+#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK)\r
+#define I2C_ID_ID_MASK (0xFFFF0000U)\r
+#define I2C_ID_ID_SHIFT (16U)\r
+/*! ID - Module identifier for the selected function.\r
+ */\r
+#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group I2C_Register_Masks */\r
+\r
+\r
+/* I2C - Peripheral instance base addresses */\r
+/** Peripheral I2C0 base address */\r
+#define I2C0_BASE (0x40086000u)\r
+/** Peripheral I2C0 base pointer */\r
+#define I2C0 ((I2C_Type *)I2C0_BASE)\r
+/** Peripheral I2C1 base address */\r
+#define I2C1_BASE (0x40087000u)\r
+/** Peripheral I2C1 base pointer */\r
+#define I2C1 ((I2C_Type *)I2C1_BASE)\r
+/** Peripheral I2C2 base address */\r
+#define I2C2_BASE (0x40088000u)\r
+/** Peripheral I2C2 base pointer */\r
+#define I2C2 ((I2C_Type *)I2C2_BASE)\r
+/** Peripheral I2C3 base address */\r
+#define I2C3_BASE (0x40089000u)\r
+/** Peripheral I2C3 base pointer */\r
+#define I2C3 ((I2C_Type *)I2C3_BASE)\r
+/** Peripheral I2C4 base address */\r
+#define I2C4_BASE (0x4008A000u)\r
+/** Peripheral I2C4 base pointer */\r
+#define I2C4 ((I2C_Type *)I2C4_BASE)\r
+/** Peripheral I2C5 base address */\r
+#define I2C5_BASE (0x40096000u)\r
+/** Peripheral I2C5 base pointer */\r
+#define I2C5 ((I2C_Type *)I2C5_BASE)\r
+/** Peripheral I2C6 base address */\r
+#define I2C6_BASE (0x40097000u)\r
+/** Peripheral I2C6 base pointer */\r
+#define I2C6 ((I2C_Type *)I2C6_BASE)\r
+/** Peripheral I2C7 base address */\r
+#define I2C7_BASE (0x40098000u)\r
+/** Peripheral I2C7 base pointer */\r
+#define I2C7 ((I2C_Type *)I2C7_BASE)\r
+/** Peripheral I2C8 base address */\r
+#define I2C8_BASE (0x40099000u)\r
+/** Peripheral I2C8 base pointer */\r
+#define I2C8 ((I2C_Type *)I2C8_BASE)\r
+/** Peripheral I2C9 base address */\r
+#define I2C9_BASE (0x4009A000u)\r
+/** Peripheral I2C9 base pointer */\r
+#define I2C9 ((I2C_Type *)I2C9_BASE)\r
+/** Array initializer of I2C peripheral base addresses */\r
+#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE, I2C8_BASE, I2C9_BASE }\r
+/** Array initializer of I2C peripheral base pointers */\r
+#define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9 }\r
+/** Interrupt vectors for the I2C peripheral type */\r
+#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group I2C_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- I2S Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** I2S - Register Layout Typedef */\r
+typedef struct {\r
+ uint8_t RESERVED_0[3072];\r
+ __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */\r
+ __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */\r
+ __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */\r
+ uint8_t RESERVED_1[16];\r
+ __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */\r
+ struct { /* offset: 0xC20, array step: 0x20 */\r
+ __IO uint32_t PCFG1; /**< Configuration register 1 for channel pair, array offset: 0xC20, array step: 0x20 */\r
+ __IO uint32_t PCFG2; /**< Configuration register 2 for channel pair, array offset: 0xC24, array step: 0x20 */\r
+ __IO uint32_t PSTAT; /**< Status register for channel pair, array offset: 0xC28, array step: 0x20 */\r
+ uint8_t RESERVED_0[20];\r
+ } SECCHANNEL[3];\r
+ uint8_t RESERVED_2[384];\r
+ __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */\r
+ __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */\r
+ __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */\r
+ uint8_t RESERVED_3[4];\r
+ __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */\r
+ __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */\r
+ __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */\r
+ uint8_t RESERVED_4[4];\r
+ __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */\r
+ __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */\r
+ uint8_t RESERVED_5[8];\r
+ __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */\r
+ __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */\r
+ uint8_t RESERVED_6[8];\r
+ __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */\r
+ __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */\r
+ uint8_t RESERVED_7[4020];\r
+ __I uint32_t ID; /**< I2S Module identification, offset: 0x1DFC */\r
+} I2S_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- I2S Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup I2S_Register_Masks I2S Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CFG1 - Configuration register 1 for the primary channel pair. */\r
+/*! @{ */\r
+#define I2S_CFG1_MAINENABLE_MASK (0x1U)\r
+#define I2S_CFG1_MAINENABLE_SHIFT (0U)\r
+/*! MAINENABLE - Main enable for I 2S function in this Flexcomm\r
+ * 0b0..All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags\r
+ * are reset. No other channel pairs can be enabled.\r
+ * 0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits.\r
+ */\r
+#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK)\r
+#define I2S_CFG1_DATAPAUSE_MASK (0x2U)\r
+#define I2S_CFG1_DATAPAUSE_SHIFT (1U)\r
+/*! DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer\r
+ * and the FIFO. This could be done in order to change streams, or while restarting after a data\r
+ * underflow or overflow. When paused, FIFO operations can be done without corrupting data that is\r
+ * in the process of being sent or received. Once a data pause has been requested, the interface\r
+ * may need to complete sending data that was in progress before interrupting the flow of data.\r
+ * Software must check that the pause is actually in effect before taking action. This is done by\r
+ * monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer\r
+ * will resume at the beginning of the next frame.\r
+ * 0b0..Normal operation, or resuming normal operation at the next frame if the I2S has already been paused.\r
+ * 0b1..A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1.\r
+ */\r
+#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK)\r
+#define I2S_CFG1_PAIRCOUNT_MASK (0xCU)\r
+#define I2S_CFG1_PAIRCOUNT_SHIFT (2U)\r
+/*! PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field\r
+ * whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this\r
+ * Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs\r
+ * in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm.\r
+ * 0b00..1 I2S channel pairs in this flexcomm\r
+ * 0b01..2 I2S channel pairs in this flexcomm\r
+ * 0b10..3 I2S channel pairs in this flexcomm\r
+ * 0b11..4 I2S channel pairs in this flexcomm\r
+ */\r
+#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK)\r
+#define I2S_CFG1_MSTSLVCFG_MASK (0x30U)\r
+#define I2S_CFG1_MSTSLVCFG_SHIFT (4U)\r
+/*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm.\r
+ * 0b00..Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data.\r
+ * 0b01..WS synchronized master. WS is received from another master and used to synchronize the generation of\r
+ * SCK, when divided from the Flexcomm function clock.\r
+ * 0b10..Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data.\r
+ * 0b11..Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices.\r
+ */\r
+#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK)\r
+#define I2S_CFG1_MODE_MASK (0xC0U)\r
+#define I2S_CFG1_MODE_SHIFT (6U)\r
+/*! MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all\r
+ * supported cases. See Formats and modes for examples.\r
+ * 0b00..I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece\r
+ * of left channel data occurring during the first phase, and one pieces of right channel data occurring\r
+ * during the second phase. In this mode, the data region begins one clock after the leading WS edge for the\r
+ * frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If\r
+ * FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right.\r
+ * 0b01..DSP mode where WS has a 50% duty cycle. See remark for mode 0.\r
+ * 0b10..DSP mode where WS has a one clock long pulse at the beginning of each data frame.\r
+ * 0b11..DSP mode where WS has a one data slot long pulse at the beginning of each data frame.\r
+ */\r
+#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK)\r
+#define I2S_CFG1_RIGHTLOW_MASK (0x100U)\r
+#define I2S_CFG1_RIGHTLOW_SHIFT (8U)\r
+/*! RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left\r
+ * and right channel data as it is transferred to or from the FIFO. This bit is not used if the\r
+ * data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10\r
+ * of this register) = 1, the one channel to be used is the nominally the left channel. POSITION\r
+ * can still place that data in the frame where right channel data is normally located. if all\r
+ * enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed.\r
+ * 0b0..The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO\r
+ * bits 31:16 are used for the right channel.\r
+ * 0b1..The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO\r
+ * bits 15:0 are used for the right channel.\r
+ */\r
+#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK)\r
+#define I2S_CFG1_LEFTJUST_MASK (0x200U)\r
+#define I2S_CFG1_LEFTJUST_SHIFT (9U)\r
+/*! LEFTJUST - Left Justify data.\r
+ * 0b0..Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting\r
+ * from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data\r
+ * in the stream on the data bus.\r
+ * 0b1..Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting\r
+ * from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would\r
+ * correspond to left justified data in the stream on the data bus.\r
+ */\r
+#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK)\r
+#define I2S_CFG1_ONECHANNEL_MASK (0x400U)\r
+#define I2S_CFG1_ONECHANNEL_SHIFT (10U)\r
+/*! ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit\r
+ * applies only to the first I2S channel pair. Other channel pairs may select this mode\r
+ * independently in their separate CFG1 registers.\r
+ * 0b0..I2S data for this channel pair is treated as left and right channels.\r
+ * 0b1..I2S data for this channel pair is treated as a single channel, functionally the left channel for this\r
+ * pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a\r
+ * clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel\r
+ * of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side\r
+ * (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data\r
+ * for the single channel of data is placed at the clock defined by POSITION.\r
+ */\r
+#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)\r
+#define I2S_CFG1_PDMDATA_MASK (0x800U)\r
+#define I2S_CFG1_PDMDATA_SHIFT (11U)\r
+/*! PDMDATA - PDM Data selection. This bit controls the data source for I2S transmit, and cannot be\r
+ * set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a\r
+ * D-Mic subsystem. For the LPC5411x, this bit applies only to Flexcomm 7.\r
+ * 0b0..Normal operation, data is transferred to or from the Flexcomm FIFO.\r
+ * 0b1..The data source is the D-Mic subsystem. When PDMDATA = 1, only the primary channel pair can be used in\r
+ * this Flexcomm. If ONECHANNEL = 1, only the PDM left data is used. the WS rate must match the Fs (sample\r
+ * rate) of the D-Mic decimator. A rate mismatch will at some point cause the I2S to overrun or underrun.\r
+ */\r
+#define I2S_CFG1_PDMDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK)\r
+#define I2S_CFG1_SCK_POL_MASK (0x1000U)\r
+#define I2S_CFG1_SCK_POL_SHIFT (12U)\r
+/*! SCK_POL - SCK polarity.\r
+ * 0b0..Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S).\r
+ * 0b1..Data is launched on SCK rising edges and sampled on SCK falling edges.\r
+ */\r
+#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK)\r
+#define I2S_CFG1_WS_POL_MASK (0x2000U)\r
+#define I2S_CFG1_WS_POL_SHIFT (13U)\r
+/*! WS_POL - WS polarity.\r
+ * 0b0..Data frames begin at a falling edge of WS (standard for classic I2S).\r
+ * 0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S).\r
+ */\r
+#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK)\r
+#define I2S_CFG1_DATALEN_MASK (0x1F0000U)\r
+#define I2S_CFG1_DATALEN_SHIFT (16U)\r
+/*! DATALEN - Data Length, minus 1 encoded, defines the number of data bits to be transmitted or\r
+ * received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received\r
+ * from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the\r
+ * I2S: Determines the size of data transfers between the FIFO and the I2S\r
+ * serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of\r
+ * right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse\r
+ * at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to\r
+ * 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F =\r
+ * data is 32 bits in length\r
+ */\r
+#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK)\r
+/*! @} */\r
+\r
+/*! @name CFG2 - Configuration register 2 for the primary channel pair. */\r
+/*! @{ */\r
+#define I2S_CFG2_FRAMELEN_MASK (0x1FFU)\r
+#define I2S_CFG2_FRAMELEN_SHIFT (0U)\r
+/*! FRAMELEN - Frame Length, minus 1 encoded, defines the number of clocks and data bits in the\r
+ * frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported\r
+ * 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x1FF = frame is\r
+ * 512 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in\r
+ * mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger\r
+ * than DATALEN in order for the WS pulse to be generated correctly.\r
+ */\r
+#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK)\r
+#define I2S_CFG2_POSITION_MASK (0x1FF0000U)\r
+#define I2S_CFG2_POSITION_SHIFT (16U)\r
+/*! POSITION - Data Position. Defines the location within the frame of the data for this channel\r
+ * pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION\r
+ * defines the location of data in both the left phase and right phase, starting one clock after\r
+ * the WS edge. In other modes, POSITION defines the location of data within the entire frame.\r
+ * ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The\r
+ * combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels\r
+ * do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit\r
+ * position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS\r
+ * phase. 0x002 = data begins at bit position 2 within the frame or WS phase.\r
+ */\r
+#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK)\r
+/*! @} */\r
+\r
+/*! @name STAT - Status register for the primary channel pair. */\r
+/*! @{ */\r
+#define I2S_STAT_BUSY_MASK (0x1U)\r
+#define I2S_STAT_BUSY_SHIFT (0U)\r
+/*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair.\r
+ * 0b0..The transmitter/receiver for channel pair is currently idle.\r
+ * 0b1..The transmitter/receiver for channel pair is currently processing data.\r
+ */\r
+#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK)\r
+#define I2S_STAT_SLVFRMERR_MASK (0x2U)\r
+#define I2S_STAT_SLVFRMERR_SHIFT (1U)\r
+/*! SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as\r
+ * a slave. An error indicates that the incoming WS signal did not transition as expected due to\r
+ * a mismatch between FRAMELEN and the actual incoming I2S stream.\r
+ * 0b0..No error has been recorded.\r
+ * 0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position.\r
+ */\r
+#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK)\r
+#define I2S_STAT_LR_MASK (0x4U)\r
+#define I2S_STAT_LR_SHIFT (2U)\r
+/*! LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to\r
+ * be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data\r
+ * being processed for the currently busy channel pair.\r
+ * 0b0..Left channel.\r
+ * 0b1..Right channel.\r
+ */\r
+#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK)\r
+#define I2S_STAT_DATAPAUSED_MASK (0x8U)\r
+#define I2S_STAT_DATAPAUSED_SHIFT (3U)\r
+/*! DATAPAUSED - Data Paused status flag. Applies to all I2S channels\r
+ * 0b0..Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for\r
+ * an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register.\r
+ * 0b1..A data pause has been requested and is now in force.\r
+ */\r
+#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK)\r
+/*! @} */\r
+\r
+/*! @name DIV - Clock divider, used by all channel pairs. */\r
+/*! @{ */\r
+#define I2S_DIV_DIV_MASK (0xFFFU)\r
+#define I2S_DIV_DIV_SHIFT (0U)\r
+/*! DIV - This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The\r
+ * Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2.\r
+ * 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is\r
+ * divided by 4,096.\r
+ */\r
+#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK)\r
+/*! @} */\r
+\r
+/*! @name SECCHANNEL_PCFG1 - Configuration register 1 for channel pair */\r
+/*! @{ */\r
+#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK (0x1U)\r
+#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT (0U)\r
+/*! PAIRENABLE - Enable for this channel pair..\r
+ */\r
+#define I2S_SECCHANNEL_PCFG1_PAIRENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK)\r
+#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK (0x400U)\r
+#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT (10U)\r
+/*! ONECHANNEL - Single channel mode.\r
+ */\r
+#define I2S_SECCHANNEL_PCFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK)\r
+/*! @} */\r
+\r
+/* The count of I2S_SECCHANNEL_PCFG1 */\r
+#define I2S_SECCHANNEL_PCFG1_COUNT (3U)\r
+\r
+/*! @name SECCHANNEL_PCFG2 - Configuration register 2 for channel pair */\r
+/*! @{ */\r
+#define I2S_SECCHANNEL_PCFG2_POSITION_MASK (0x1FF0000U)\r
+#define I2S_SECCHANNEL_PCFG2_POSITION_SHIFT (16U)\r
+/*! POSITION - Data Position.\r
+ */\r
+#define I2S_SECCHANNEL_PCFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK)\r
+/*! @} */\r
+\r
+/* The count of I2S_SECCHANNEL_PCFG2 */\r
+#define I2S_SECCHANNEL_PCFG2_COUNT (3U)\r
+\r
+/*! @name SECCHANNEL_PSTAT - Status register for channel pair */\r
+/*! @{ */\r
+#define I2S_SECCHANNEL_PSTAT_BUSY_MASK (0x1U)\r
+#define I2S_SECCHANNEL_PSTAT_BUSY_SHIFT (0U)\r
+/*! BUSY - Busy status for this channel pair.\r
+ */\r
+#define I2S_SECCHANNEL_PSTAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK)\r
+#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK (0x2U)\r
+#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT (1U)\r
+/*! SLVFRMERR - Save Frame Error flag.\r
+ */\r
+#define I2S_SECCHANNEL_PSTAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK)\r
+#define I2S_SECCHANNEL_PSTAT_LR_MASK (0x4U)\r
+#define I2S_SECCHANNEL_PSTAT_LR_SHIFT (2U)\r
+/*! LR - Left/Right indication.\r
+ */\r
+#define I2S_SECCHANNEL_PSTAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK)\r
+#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK (0x8U)\r
+#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT (3U)\r
+/*! DATAPAUSED - Data Paused status flag.\r
+ */\r
+#define I2S_SECCHANNEL_PSTAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK)\r
+/*! @} */\r
+\r
+/* The count of I2S_SECCHANNEL_PSTAT */\r
+#define I2S_SECCHANNEL_PSTAT_COUNT (3U)\r
+\r
+/*! @name FIFOCFG - FIFO configuration and enable register. */\r
+/*! @{ */\r
+#define I2S_FIFOCFG_ENABLETX_MASK (0x1U)\r
+#define I2S_FIFOCFG_ENABLETX_SHIFT (0U)\r
+/*! ENABLETX - Enable the transmit FIFO.\r
+ * 0b0..The transmit FIFO is not enabled.\r
+ * 0b1..The transmit FIFO is enabled.\r
+ */\r
+#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK)\r
+#define I2S_FIFOCFG_ENABLERX_MASK (0x2U)\r
+#define I2S_FIFOCFG_ENABLERX_SHIFT (1U)\r
+/*! ENABLERX - Enable the receive FIFO.\r
+ * 0b0..The receive FIFO is not enabled.\r
+ * 0b1..The receive FIFO is enabled.\r
+ */\r
+#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK)\r
+#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U)\r
+#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U)\r
+/*! TXI2SE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX\r
+ * FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is\r
+ * cleared, new data is provided, and the I2S is un-paused.\r
+ * 0b0..If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24\r
+ * bits or less, or when MONO = 1 for this channel pair.\r
+ * 0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred.\r
+ */\r
+#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK)\r
+#define I2S_FIFOCFG_PACK48_MASK (0x8U)\r
+#define I2S_FIFOCFG_PACK48_SHIFT (3U)\r
+/*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA.\r
+ * 0b0..48-bit I2S FIFO entries are handled as all 24-bit values.\r
+ * 0b1..48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values.\r
+ */\r
+#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK)\r
+#define I2S_FIFOCFG_SIZE_MASK (0x30U)\r
+#define I2S_FIFOCFG_SIZE_SHIFT (4U)\r
+/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16\r
+ * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART.\r
+ */\r
+#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK)\r
+#define I2S_FIFOCFG_DMATX_MASK (0x1000U)\r
+#define I2S_FIFOCFG_DMATX_SHIFT (12U)\r
+/*! DMATX - DMA configuration for transmit.\r
+ * 0b0..DMA is not used for the transmit function.\r
+ * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.\r
+ */\r
+#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK)\r
+#define I2S_FIFOCFG_DMARX_MASK (0x2000U)\r
+#define I2S_FIFOCFG_DMARX_SHIFT (13U)\r
+/*! DMARX - DMA configuration for receive.\r
+ * 0b0..DMA is not used for the receive function.\r
+ * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.\r
+ */\r
+#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK)\r
+#define I2S_FIFOCFG_WAKETX_MASK (0x4000U)\r
+#define I2S_FIFOCFG_WAKETX_SHIFT (14U)\r
+/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power\r
+ * modes (up to power-down, as long as the peripheral function works in that power mode) without\r
+ * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The\r
+ * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware\r
+ * Wake-up control register.\r
+ * 0b0..Only enabled interrupts will wake up the device form reduced power modes.\r
+ * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in\r
+ * FIFOTRIG, even when the TXLVL interrupt is not enabled.\r
+ */\r
+#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK)\r
+#define I2S_FIFOCFG_WAKERX_MASK (0x8000U)\r
+#define I2S_FIFOCFG_WAKERX_SHIFT (15U)\r
+/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power\r
+ * modes (up to power-down, as long as the peripheral function works in that power mode) without\r
+ * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The\r
+ * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware\r
+ * Wake-up control register.\r
+ * 0b0..Only enabled interrupts will wake up the device form reduced power modes.\r
+ * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in\r
+ * FIFOTRIG, even when the RXLVL interrupt is not enabled.\r
+ */\r
+#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK)\r
+#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U)\r
+#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U)\r
+/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.\r
+ */\r
+#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK)\r
+#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U)\r
+#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U)\r
+/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.\r
+ */\r
+#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOSTAT - FIFO status register. */\r
+/*! @{ */\r
+#define I2S_FIFOSTAT_TXERR_MASK (0x1U)\r
+#define I2S_FIFOSTAT_TXERR_SHIFT (0U)\r
+/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow\r
+ * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is\r
+ * needed. Cleared by writing a 1 to this bit.\r
+ */\r
+#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK)\r
+#define I2S_FIFOSTAT_RXERR_MASK (0x2U)\r
+#define I2S_FIFOSTAT_RXERR_SHIFT (1U)\r
+/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA\r
+ * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit.\r
+ */\r
+#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK)\r
+#define I2S_FIFOSTAT_PERINT_MASK (0x8U)\r
+#define I2S_FIFOSTAT_PERINT_SHIFT (3U)\r
+/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted\r
+ * an interrupt. The details can be found by reading the peripheral's STAT register.\r
+ */\r
+#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK)\r
+#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U)\r
+#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U)\r
+/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data.\r
+ */\r
+#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK)\r
+#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U)\r
+#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U)\r
+/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be\r
+ * written. When 0, the transmit FIFO is full and another write would cause it to overflow.\r
+ */\r
+#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK)\r
+#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)\r
+#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)\r
+/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty.\r
+ */\r
+#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK)\r
+#define I2S_FIFOSTAT_RXFULL_MASK (0x80U)\r
+#define I2S_FIFOSTAT_RXFULL_SHIFT (7U)\r
+/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to\r
+ * prevent the peripheral from causing an overflow.\r
+ */\r
+#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK)\r
+#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U)\r
+#define I2S_FIFOSTAT_TXLVL_SHIFT (8U)\r
+/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY\r
+ * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at\r
+ * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be\r
+ * 0.\r
+ */\r
+#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK)\r
+#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U)\r
+#define I2S_FIFOSTAT_RXLVL_SHIFT (16U)\r
+/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and\r
+ * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the\r
+ * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be\r
+ * 1.\r
+ */\r
+#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */\r
+/*! @{ */\r
+#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U)\r
+#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U)\r
+/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled\r
+ * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.\r
+ * 0b0..Transmit FIFO level does not generate a FIFO level trigger.\r
+ * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.\r
+ */\r
+#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK)\r
+#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U)\r
+#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U)\r
+/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled\r
+ * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.\r
+ * 0b0..Receive FIFO level does not generate a FIFO level trigger.\r
+ * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.\r
+ */\r
+#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK)\r
+#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U)\r
+#define I2S_FIFOTRIG_TXLVL_SHIFT (8U)\r
+/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled\r
+ * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to\r
+ * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO\r
+ * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX\r
+ * FIFO level decreases to 15 entries (is no longer full).\r
+ */\r
+#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK)\r
+#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U)\r
+#define I2S_FIFOTRIG_RXLVL_SHIFT (16U)\r
+/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data\r
+ * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level\r
+ * can wake up the device just enough to perform DMA, then return to the reduced power mode. See\r
+ * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no\r
+ * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX\r
+ * FIFO has received 16 entries (has become full).\r
+ */\r
+#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */\r
+/*! @{ */\r
+#define I2S_FIFOINTENSET_TXERR_MASK (0x1U)\r
+#define I2S_FIFOINTENSET_TXERR_SHIFT (0U)\r
+/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.\r
+ * 0b0..No interrupt will be generated for a transmit error.\r
+ * 0b1..An interrupt will be generated when a transmit error occurs.\r
+ */\r
+#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK)\r
+#define I2S_FIFOINTENSET_RXERR_MASK (0x2U)\r
+#define I2S_FIFOINTENSET_RXERR_SHIFT (1U)\r
+/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.\r
+ * 0b0..No interrupt will be generated for a receive error.\r
+ * 0b1..An interrupt will be generated when a receive error occurs.\r
+ */\r
+#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK)\r
+#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U)\r
+#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U)\r
+/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level\r
+ * specified by the TXLVL field in the FIFOTRIG register.\r
+ * 0b0..No interrupt will be generated based on the TX FIFO level.\r
+ * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases\r
+ * to the level specified by TXLVL in the FIFOTRIG register.\r
+ */\r
+#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK)\r
+#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U)\r
+#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U)\r
+/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level\r
+ * specified by the TXLVL field in the FIFOTRIG register.\r
+ * 0b0..No interrupt will be generated based on the RX FIFO level.\r
+ * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level\r
+ * increases to the level specified by RXLVL in the FIFOTRIG register.\r
+ */\r
+#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */\r
+/*! @{ */\r
+#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U)\r
+#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U)\r
+/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.\r
+ */\r
+#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK)\r
+#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U)\r
+#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U)\r
+/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.\r
+ */\r
+#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK)\r
+#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U)\r
+#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U)\r
+/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.\r
+ */\r
+#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK)\r
+#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U)\r
+#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U)\r
+/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.\r
+ */\r
+#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOINTSTAT - FIFO interrupt status register. */\r
+/*! @{ */\r
+#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U)\r
+#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U)\r
+/*! TXERR - TX FIFO error.\r
+ */\r
+#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK)\r
+#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U)\r
+#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U)\r
+/*! RXERR - RX FIFO error.\r
+ */\r
+#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK)\r
+#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U)\r
+#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U)\r
+/*! TXLVL - Transmit FIFO level interrupt.\r
+ */\r
+#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK)\r
+#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U)\r
+#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U)\r
+/*! RXLVL - Receive FIFO level interrupt.\r
+ */\r
+#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK)\r
+#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U)\r
+#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U)\r
+/*! PERINT - Peripheral interrupt.\r
+ */\r
+#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOWR - FIFO write data. */\r
+/*! @{ */\r
+#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU)\r
+#define I2S_FIFOWR_TXDATA_SHIFT (0U)\r
+/*! TXDATA - Transmit data to the FIFO. The number of bits used depends on configuration details.\r
+ */\r
+#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */\r
+/*! @{ */\r
+#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU)\r
+#define I2S_FIFOWR48H_TXDATA_SHIFT (0U)\r
+/*! TXDATA - Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details.\r
+ */\r
+#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFORD - FIFO read data. */\r
+/*! @{ */\r
+#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU)\r
+#define I2S_FIFORD_RXDATA_SHIFT (0U)\r
+/*! RXDATA - Received data from the FIFO. The number of bits used depends on configuration details.\r
+ */\r
+#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */\r
+/*! @{ */\r
+#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU)\r
+#define I2S_FIFORD48H_RXDATA_SHIFT (0U)\r
+/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details.\r
+ */\r
+#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */\r
+/*! @{ */\r
+#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU)\r
+#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U)\r
+/*! RXDATA - Received data from the FIFO.\r
+ */\r
+#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */\r
+/*! @{ */\r
+#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU)\r
+#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U)\r
+/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details.\r
+ */\r
+#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK)\r
+/*! @} */\r
+\r
+/*! @name ID - I2S Module identification */\r
+/*! @{ */\r
+#define I2S_ID_Aperture_MASK (0xFFU)\r
+#define I2S_ID_Aperture_SHIFT (0U)\r
+/*! Aperture - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.\r
+ */\r
+#define I2S_ID_Aperture(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Aperture_SHIFT)) & I2S_ID_Aperture_MASK)\r
+#define I2S_ID_Minor_Rev_MASK (0xF00U)\r
+#define I2S_ID_Minor_Rev_SHIFT (8U)\r
+/*! Minor_Rev - Minor revision of module implementation, starting at 0.\r
+ */\r
+#define I2S_ID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Minor_Rev_SHIFT)) & I2S_ID_Minor_Rev_MASK)\r
+#define I2S_ID_Major_Rev_MASK (0xF000U)\r
+#define I2S_ID_Major_Rev_SHIFT (12U)\r
+/*! Major_Rev - Major revision of module implementation, starting at 0.\r
+ */\r
+#define I2S_ID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Major_Rev_SHIFT)) & I2S_ID_Major_Rev_MASK)\r
+#define I2S_ID_ID_MASK (0xFFFF0000U)\r
+#define I2S_ID_ID_SHIFT (16U)\r
+/*! ID - Unique module identifier for this IP block.\r
+ */\r
+#define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group I2S_Register_Masks */\r
+\r
+\r
+/* I2S - Peripheral instance base addresses */\r
+/** Peripheral I2S0 base address */\r
+#define I2S0_BASE (0x40097000u)\r
+/** Peripheral I2S0 base pointer */\r
+#define I2S0 ((I2S_Type *)I2S0_BASE)\r
+/** Peripheral I2S1 base address */\r
+#define I2S1_BASE (0x40098000u)\r
+/** Peripheral I2S1 base pointer */\r
+#define I2S1 ((I2S_Type *)I2S1_BASE)\r
+/** Array initializer of I2S peripheral base addresses */\r
+#define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE }\r
+/** Array initializer of I2S peripheral base pointers */\r
+#define I2S_BASE_PTRS { I2S0, I2S1 }\r
+/** Interrupt vectors for the I2S peripheral type */\r
+#define I2S_IRQS { FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group I2S_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- INPUTMUX Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** INPUTMUX - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t SCT0_INMUX[7]; /**< Trigger select register for DMA channel, array offset: 0x0, array step: 0x4 */\r
+ uint8_t RESERVED_0[164];\r
+ __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */\r
+ __IO uint32_t DMA_ITRIG_INMUX[32]; /**< Trigger select register for DMA channel, array offset: 0xE0, array step: 0x4 */\r
+ __IO uint32_t DMA_OTRIG_INMUX[4]; /**< DMA output trigger selection to become DMA trigger, array offset: 0x160, array step: 0x4 */\r
+ uint8_t RESERVED_1[16];\r
+ __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */\r
+ __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */\r
+} INPUTMUX_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- INPUTMUX Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name SCT0_INMUX - Trigger select register for DMA channel */\r
+/*! @{ */\r
+#define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU)\r
+#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U)\r
+/*! INP_N - Input number to SCT0 inputs 0 to 6..\r
+ */\r
+#define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK)\r
+/*! @} */\r
+\r
+/* The count of INPUTMUX_SCT0_INMUX */\r
+#define INPUTMUX_SCT0_INMUX_COUNT (7U)\r
+\r
+/*! @name PINTSEL - Pin interrupt select register */\r
+/*! @{ */\r
+#define INPUTMUX_PINTSEL_INTPIN_MASK (0xFFU)\r
+#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U)\r
+/*! INTPIN - Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO1_31 correspond to numbers 0 to 63).\r
+ */\r
+#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK)\r
+/*! @} */\r
+\r
+/* The count of INPUTMUX_PINTSEL */\r
+#define INPUTMUX_PINTSEL_COUNT (8U)\r
+\r
+/*! @name DMA_ITRIG_INMUX - Trigger select register for DMA channel */\r
+/*! @{ */\r
+#define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK (0x1FU)\r
+#define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT (0U)\r
+/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 31). 0 = ADC0 Sequence A\r
+ * interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 =\r
+ * Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match\r
+ * 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer\r
+ * CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin\r
+ * interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2\r
+ * 19 = DMA output trigger mux 3\r
+ */\r
+#define INPUTMUX_DMA_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK)\r
+/*! @} */\r
+\r
+/* The count of INPUTMUX_DMA_ITRIG_INMUX */\r
+#define INPUTMUX_DMA_ITRIG_INMUX_COUNT (32U)\r
+\r
+/*! @name DMA_OTRIG_INMUX - DMA output trigger selection to become DMA trigger */\r
+/*! @{ */\r
+#define INPUTMUX_DMA_OTRIG_INMUX_INP_MASK (0x1FU)\r
+#define INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT (0U)\r
+/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 19).\r
+ */\r
+#define INPUTMUX_DMA_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_OTRIG_INMUX_INP_MASK)\r
+/*! @} */\r
+\r
+/* The count of INPUTMUX_DMA_OTRIG_INMUX */\r
+#define INPUTMUX_DMA_OTRIG_INMUX_COUNT (4U)\r
+\r
+/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */\r
+/*! @{ */\r
+#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU)\r
+#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U)\r
+/*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: 0 =\r
+ * CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock\r
+ * (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4\r
+ */\r
+#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK)\r
+/*! @} */\r
+\r
+/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */\r
+/*! @{ */\r
+#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU)\r
+#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U)\r
+/*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: 0 =\r
+ * CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock\r
+ * (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4\r
+ */\r
+#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group INPUTMUX_Register_Masks */\r
+\r
+\r
+/* INPUTMUX - Peripheral instance base addresses */\r
+/** Peripheral INPUTMUX base address */\r
+#define INPUTMUX_BASE (0x40005000u)\r
+/** Peripheral INPUTMUX base pointer */\r
+#define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE)\r
+/** Array initializer of INPUTMUX peripheral base addresses */\r
+#define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE }\r
+/** Array initializer of INPUTMUX peripheral base pointers */\r
+#define INPUTMUX_BASE_PTRS { INPUTMUX }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group INPUTMUX_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- IOCON Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** IOCON - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t PIO[6][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 5 pins PIO5_31, array offset: 0x0, array step: index*0x80, index2*0x4 */\r
+} IOCON_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- IOCON Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup IOCON_Register_Masks IOCON Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 5 pins PIO5_31 */\r
+/*! @{ */\r
+#define IOCON_PIO_FUNC_MASK (0xFU)\r
+#define IOCON_PIO_FUNC_SHIFT (0U)\r
+/*! FUNC - Selects pin function.\r
+ * 0b0000..Alternative connection 0.\r
+ * 0b0001..Alternative connection 1.\r
+ * 0b0010..Alternative connection 2.\r
+ * 0b0011..Alternative connection 3.\r
+ * 0b0100..Alternative connection 4.\r
+ * 0b0101..Alternative connection 5.\r
+ * 0b0110..Alternative connection 6.\r
+ * 0b0111..Alternative connection 7.\r
+ * 0b1000..Alternative connection 8.\r
+ * 0b1001..Alternative connection 9.\r
+ * 0b1010..Alternative connection 10.\r
+ */\r
+#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK)\r
+#define IOCON_PIO_MODE_MASK (0x30U)\r
+#define IOCON_PIO_MODE_SHIFT (4U)\r
+/*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control).\r
+ * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled).\r
+ * 0b01..Pull-down. Pull-down resistor enabled.\r
+ * 0b10..Pull-up. Pull-up resistor enabled.\r
+ * 0b11..Repeater. Repeater mode.\r
+ */\r
+#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK)\r
+#define IOCON_PIO_ANAMODE_MASK (0x40U)\r
+#define IOCON_PIO_ANAMODE_SHIFT (6U)\r
+/*! ANAMODE - Enables or disables analog mode.\r
+ * 0b0..Enable analog Mode.\r
+ * 0b1..Disable analog Mode.\r
+ */\r
+#define IOCON_PIO_ANAMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ANAMODE_SHIFT)) & IOCON_PIO_ANAMODE_MASK)\r
+#define IOCON_PIO_I2CSLEW_MASK (0x40U)\r
+#define IOCON_PIO_I2CSLEW_SHIFT (6U)\r
+/*! I2CSLEW - Controls slew rate of I2C pad.\r
+ * 0b0..I2C mode.\r
+ * 0b1..GPIO mode.\r
+ */\r
+#define IOCON_PIO_I2CSLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CSLEW_SHIFT)) & IOCON_PIO_I2CSLEW_MASK)\r
+#define IOCON_PIO_INVERT_MASK (0x80U)\r
+#define IOCON_PIO_INVERT_SHIFT (7U)\r
+/*! INVERT - Input polarity.\r
+ * 0b0..Disabled. Input function is not inverted.\r
+ * 0b1..Enabled. Input is function inverted.\r
+ */\r
+#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK)\r
+#define IOCON_PIO_DIGIMODE_MASK (0x100U)\r
+#define IOCON_PIO_DIGIMODE_SHIFT (8U)\r
+/*! DIGIMODE - Select Analog/Digital mode.\r
+ * 0b0..Analog mode.\r
+ * 0b1..Digital mode.\r
+ */\r
+#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK)\r
+#define IOCON_PIO_FILTEROFF_MASK (0x200U)\r
+#define IOCON_PIO_FILTEROFF_SHIFT (9U)\r
+/*! FILTEROFF - Controls input glitch filter.\r
+ * 0b0..Filter enabled. Noise pulses below approximately 10 ns are filtered out.\r
+ * 0b1..Filter disabled. No input filtering is done.\r
+ */\r
+#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK)\r
+#define IOCON_PIO_I2CDRIVE_MASK (0x400U)\r
+#define IOCON_PIO_I2CDRIVE_SHIFT (10U)\r
+/*! I2CDRIVE - Controls the current sink capability of the pin.\r
+ * 0b0..Low drive. Output drive sink is 4 mA. This is sufficient for standard and fast mode I2C.\r
+ * 0b1..High drive. Output drive sink is 20 mA. This is needed for Fast Mode Plus I 2C. Refer to the appropriate\r
+ * specific device data sheet for details.\r
+ */\r
+#define IOCON_PIO_I2CDRIVE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CDRIVE_SHIFT)) & IOCON_PIO_I2CDRIVE_MASK)\r
+#define IOCON_PIO_SLEW_MASK (0x400U)\r
+#define IOCON_PIO_SLEW_SHIFT (10U)\r
+/*! SLEW - Driver slew rate.\r
+ * 0b0..Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.\r
+ * 0b1..Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.\r
+ */\r
+#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK)\r
+#define IOCON_PIO_I2CFILTEROFF_MASK (0x800U)\r
+#define IOCON_PIO_I2CFILTEROFF_SHIFT (11U)\r
+/*! I2CFILTEROFF - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation.\r
+ * 0b0..Enabled. I2C 50 ns glitch filter enabled.\r
+ * 0b1..Disabled. I2C 50 ns glitch filter disabled.\r
+ */\r
+#define IOCON_PIO_I2CFILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTEROFF_SHIFT)) & IOCON_PIO_I2CFILTEROFF_MASK)\r
+#define IOCON_PIO_OD_MASK (0x800U)\r
+#define IOCON_PIO_OD_SHIFT (11U)\r
+/*! OD - Controls open-drain mode.\r
+ * 0b0..Normal. Normal push-pull output\r
+ * 0b1..Open-drain. Simulated open-drain output (high drive disabled).\r
+ */\r
+#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK)\r
+/*! @} */\r
+\r
+/* The count of IOCON_PIO */\r
+#define IOCON_PIO_COUNT (6U)\r
+\r
+/* The count of IOCON_PIO */\r
+#define IOCON_PIO_COUNT2 (32U)\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group IOCON_Register_Masks */\r
+\r
+\r
+/* IOCON - Peripheral instance base addresses */\r
+/** Peripheral IOCON base address */\r
+#define IOCON_BASE (0x40001000u)\r
+/** Peripheral IOCON base pointer */\r
+#define IOCON ((IOCON_Type *)IOCON_BASE)\r
+/** Array initializer of IOCON peripheral base addresses */\r
+#define IOCON_BASE_ADDRS { IOCON_BASE }\r
+/** Array initializer of IOCON peripheral base pointers */\r
+#define IOCON_BASE_PTRS { IOCON }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group IOCON_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- LCD Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** LCD - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t TIMH; /**< Horizontal Timing Control register, offset: 0x0 */\r
+ __IO uint32_t TIMV; /**< Vertical Timing Control register, offset: 0x4 */\r
+ __IO uint32_t POL; /**< Clock and Signal Polarity Control register, offset: 0x8 */\r
+ __IO uint32_t LE; /**< Line End Control register, offset: 0xC */\r
+ __IO uint32_t UPBASE; /**< Upper Panel Frame Base Address register, offset: 0x10 */\r
+ __IO uint32_t LPBASE; /**< Lower Panel Frame Base Address register, offset: 0x14 */\r
+ __IO uint32_t CTRL; /**< LCD Control register, offset: 0x18 */\r
+ __IO uint32_t INTMSK; /**< Interrupt Mask register, offset: 0x1C */\r
+ __I uint32_t INTRAW; /**< Raw Interrupt Status register, offset: 0x20 */\r
+ __I uint32_t INTSTAT; /**< Masked Interrupt Status register, offset: 0x24 */\r
+ __O uint32_t INTCLR; /**< Interrupt Clear register, offset: 0x28 */\r
+ __I uint32_t UPCURR; /**< Upper Panel Current Address Value register, offset: 0x2C */\r
+ __I uint32_t LPCURR; /**< Lower Panel Current Address Value register, offset: 0x30 */\r
+ uint8_t RESERVED_0[460];\r
+ __IO uint32_t PAL[128]; /**< 256x16-bit Color Palette registers, array offset: 0x200, array step: 0x4 */\r
+ uint8_t RESERVED_1[1024];\r
+ __IO uint32_t CRSR_IMG[256]; /**< Cursor Image registers, array offset: 0x800, array step: 0x4 */\r
+ __IO uint32_t CRSR_CTRL; /**< Cursor Control register, offset: 0xC00 */\r
+ __IO uint32_t CRSR_CFG; /**< Cursor Configuration register, offset: 0xC04 */\r
+ __IO uint32_t CRSR_PAL0; /**< Cursor Palette register 0, offset: 0xC08 */\r
+ __IO uint32_t CRSR_PAL1; /**< Cursor Palette register 1, offset: 0xC0C */\r
+ __IO uint32_t CRSR_XY; /**< Cursor XY Position register, offset: 0xC10 */\r
+ __IO uint32_t CRSR_CLIP; /**< Cursor Clip Position register, offset: 0xC14 */\r
+ uint8_t RESERVED_2[8];\r
+ __IO uint32_t CRSR_INTMSK; /**< Cursor Interrupt Mask register, offset: 0xC20 */\r
+ __O uint32_t CRSR_INTCLR; /**< Cursor Interrupt Clear register, offset: 0xC24 */\r
+ __I uint32_t CRSR_INTRAW; /**< Cursor Raw Interrupt Status register, offset: 0xC28 */\r
+ __I uint32_t CRSR_INTSTAT; /**< Cursor Masked Interrupt Status register, offset: 0xC2C */\r
+} LCD_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- LCD Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup LCD_Register_Masks LCD Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name TIMH - Horizontal Timing Control register */\r
+/*! @{ */\r
+#define LCD_TIMH_PPL_MASK (0xFCU)\r
+#define LCD_TIMH_PPL_SHIFT (2U)\r
+/*! PPL - Pixels-per-line.\r
+ */\r
+#define LCD_TIMH_PPL(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_PPL_SHIFT)) & LCD_TIMH_PPL_MASK)\r
+#define LCD_TIMH_HSW_MASK (0xFF00U)\r
+#define LCD_TIMH_HSW_SHIFT (8U)\r
+/*! HSW - Horizontal synchronization pulse width.\r
+ */\r
+#define LCD_TIMH_HSW(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HSW_SHIFT)) & LCD_TIMH_HSW_MASK)\r
+#define LCD_TIMH_HFP_MASK (0xFF0000U)\r
+#define LCD_TIMH_HFP_SHIFT (16U)\r
+/*! HFP - Horizontal front porch.\r
+ */\r
+#define LCD_TIMH_HFP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HFP_SHIFT)) & LCD_TIMH_HFP_MASK)\r
+#define LCD_TIMH_HBP_MASK (0xFF000000U)\r
+#define LCD_TIMH_HBP_SHIFT (24U)\r
+/*! HBP - Horizontal back porch.\r
+ */\r
+#define LCD_TIMH_HBP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HBP_SHIFT)) & LCD_TIMH_HBP_MASK)\r
+/*! @} */\r
+\r
+/*! @name TIMV - Vertical Timing Control register */\r
+/*! @{ */\r
+#define LCD_TIMV_LPP_MASK (0x3FFU)\r
+#define LCD_TIMV_LPP_SHIFT (0U)\r
+/*! LPP - Lines per panel.\r
+ */\r
+#define LCD_TIMV_LPP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_LPP_SHIFT)) & LCD_TIMV_LPP_MASK)\r
+#define LCD_TIMV_VSW_MASK (0xFC00U)\r
+#define LCD_TIMV_VSW_SHIFT (10U)\r
+/*! VSW - Vertical synchronization pulse width.\r
+ */\r
+#define LCD_TIMV_VSW(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VSW_SHIFT)) & LCD_TIMV_VSW_MASK)\r
+#define LCD_TIMV_VFP_MASK (0xFF0000U)\r
+#define LCD_TIMV_VFP_SHIFT (16U)\r
+/*! VFP - Vertical front porch.\r
+ */\r
+#define LCD_TIMV_VFP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VFP_SHIFT)) & LCD_TIMV_VFP_MASK)\r
+#define LCD_TIMV_VBP_MASK (0xFF000000U)\r
+#define LCD_TIMV_VBP_SHIFT (24U)\r
+/*! VBP - Vertical back porch.\r
+ */\r
+#define LCD_TIMV_VBP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VBP_SHIFT)) & LCD_TIMV_VBP_MASK)\r
+/*! @} */\r
+\r
+/*! @name POL - Clock and Signal Polarity Control register */\r
+/*! @{ */\r
+#define LCD_POL_PCD_LO_MASK (0x1FU)\r
+#define LCD_POL_PCD_LO_SHIFT (0U)\r
+/*! PCD_LO - Lower five bits of panel clock divisor.\r
+ */\r
+#define LCD_POL_PCD_LO(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_PCD_LO_SHIFT)) & LCD_POL_PCD_LO_MASK)\r
+#define LCD_POL_ACB_MASK (0x7C0U)\r
+#define LCD_POL_ACB_SHIFT (6U)\r
+/*! ACB - AC bias pin frequency.\r
+ */\r
+#define LCD_POL_ACB(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_ACB_SHIFT)) & LCD_POL_ACB_MASK)\r
+#define LCD_POL_IVS_MASK (0x800U)\r
+#define LCD_POL_IVS_SHIFT (11U)\r
+/*! IVS - Invert vertical synchronization.\r
+ */\r
+#define LCD_POL_IVS(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IVS_SHIFT)) & LCD_POL_IVS_MASK)\r
+#define LCD_POL_IHS_MASK (0x1000U)\r
+#define LCD_POL_IHS_SHIFT (12U)\r
+/*! IHS - Invert horizontal synchronization.\r
+ */\r
+#define LCD_POL_IHS(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IHS_SHIFT)) & LCD_POL_IHS_MASK)\r
+#define LCD_POL_IPC_MASK (0x2000U)\r
+#define LCD_POL_IPC_SHIFT (13U)\r
+/*! IPC - Invert panel clock.\r
+ */\r
+#define LCD_POL_IPC(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IPC_SHIFT)) & LCD_POL_IPC_MASK)\r
+#define LCD_POL_IOE_MASK (0x4000U)\r
+#define LCD_POL_IOE_SHIFT (14U)\r
+/*! IOE - Invert output enable.\r
+ */\r
+#define LCD_POL_IOE(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IOE_SHIFT)) & LCD_POL_IOE_MASK)\r
+#define LCD_POL_CPL_MASK (0x3FF0000U)\r
+#define LCD_POL_CPL_SHIFT (16U)\r
+/*! CPL - Clocks per line.\r
+ */\r
+#define LCD_POL_CPL(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_CPL_SHIFT)) & LCD_POL_CPL_MASK)\r
+#define LCD_POL_BCD_MASK (0x4000000U)\r
+#define LCD_POL_BCD_SHIFT (26U)\r
+/*! BCD - Bypass panel clock divider.\r
+ */\r
+#define LCD_POL_BCD(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_BCD_SHIFT)) & LCD_POL_BCD_MASK)\r
+#define LCD_POL_PCD_HI_MASK (0xF8000000U)\r
+#define LCD_POL_PCD_HI_SHIFT (27U)\r
+/*! PCD_HI - Upper five bits of panel clock divisor.\r
+ */\r
+#define LCD_POL_PCD_HI(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_PCD_HI_SHIFT)) & LCD_POL_PCD_HI_MASK)\r
+/*! @} */\r
+\r
+/*! @name LE - Line End Control register */\r
+/*! @{ */\r
+#define LCD_LE_LED_MASK (0x7FU)\r
+#define LCD_LE_LED_SHIFT (0U)\r
+/*! LED - Line-end delay.\r
+ */\r
+#define LCD_LE_LED(x) (((uint32_t)(((uint32_t)(x)) << LCD_LE_LED_SHIFT)) & LCD_LE_LED_MASK)\r
+#define LCD_LE_LEE_MASK (0x10000U)\r
+#define LCD_LE_LEE_SHIFT (16U)\r
+/*! LEE - LCD Line end enable.\r
+ */\r
+#define LCD_LE_LEE(x) (((uint32_t)(((uint32_t)(x)) << LCD_LE_LEE_SHIFT)) & LCD_LE_LEE_MASK)\r
+/*! @} */\r
+\r
+/*! @name UPBASE - Upper Panel Frame Base Address register */\r
+/*! @{ */\r
+#define LCD_UPBASE_LCDUPBASE_MASK (0xFFFFFFF8U)\r
+#define LCD_UPBASE_LCDUPBASE_SHIFT (3U)\r
+/*! LCDUPBASE - LCD upper panel base address.\r
+ */\r
+#define LCD_UPBASE_LCDUPBASE(x) (((uint32_t)(((uint32_t)(x)) << LCD_UPBASE_LCDUPBASE_SHIFT)) & LCD_UPBASE_LCDUPBASE_MASK)\r
+/*! @} */\r
+\r
+/*! @name LPBASE - Lower Panel Frame Base Address register */\r
+/*! @{ */\r
+#define LCD_LPBASE_LCDLPBASE_MASK (0xFFFFFFF8U)\r
+#define LCD_LPBASE_LCDLPBASE_SHIFT (3U)\r
+/*! LCDLPBASE - LCD lower panel base address.\r
+ */\r
+#define LCD_LPBASE_LCDLPBASE(x) (((uint32_t)(((uint32_t)(x)) << LCD_LPBASE_LCDLPBASE_SHIFT)) & LCD_LPBASE_LCDLPBASE_MASK)\r
+/*! @} */\r
+\r
+/*! @name CTRL - LCD Control register */\r
+/*! @{ */\r
+#define LCD_CTRL_LCDEN_MASK (0x1U)\r
+#define LCD_CTRL_LCDEN_SHIFT (0U)\r
+/*! LCDEN - LCD enable control bit.\r
+ */\r
+#define LCD_CTRL_LCDEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDEN_SHIFT)) & LCD_CTRL_LCDEN_MASK)\r
+#define LCD_CTRL_LCDBPP_MASK (0xEU)\r
+#define LCD_CTRL_LCDBPP_SHIFT (1U)\r
+/*! LCDBPP - LCD bits per pixel.\r
+ */\r
+#define LCD_CTRL_LCDBPP(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDBPP_SHIFT)) & LCD_CTRL_LCDBPP_MASK)\r
+#define LCD_CTRL_LCDBW_MASK (0x10U)\r
+#define LCD_CTRL_LCDBW_SHIFT (4U)\r
+/*! LCDBW - STN LCD monochrome/color selection.\r
+ */\r
+#define LCD_CTRL_LCDBW(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDBW_SHIFT)) & LCD_CTRL_LCDBW_MASK)\r
+#define LCD_CTRL_LCDTFT_MASK (0x20U)\r
+#define LCD_CTRL_LCDTFT_SHIFT (5U)\r
+/*! LCDTFT - LCD panel TFT type selection.\r
+ */\r
+#define LCD_CTRL_LCDTFT(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDTFT_SHIFT)) & LCD_CTRL_LCDTFT_MASK)\r
+#define LCD_CTRL_LCDMONO8_MASK (0x40U)\r
+#define LCD_CTRL_LCDMONO8_SHIFT (6U)\r
+/*! LCDMONO8 - Monochrome LCD interface width.\r
+ */\r
+#define LCD_CTRL_LCDMONO8(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDMONO8_SHIFT)) & LCD_CTRL_LCDMONO8_MASK)\r
+#define LCD_CTRL_LCDDUAL_MASK (0x80U)\r
+#define LCD_CTRL_LCDDUAL_SHIFT (7U)\r
+/*! LCDDUAL - Single or Dual LCD panel selection.\r
+ */\r
+#define LCD_CTRL_LCDDUAL(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDDUAL_SHIFT)) & LCD_CTRL_LCDDUAL_MASK)\r
+#define LCD_CTRL_BGR_MASK (0x100U)\r
+#define LCD_CTRL_BGR_SHIFT (8U)\r
+/*! BGR - Color format selection.\r
+ */\r
+#define LCD_CTRL_BGR(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BGR_SHIFT)) & LCD_CTRL_BGR_MASK)\r
+#define LCD_CTRL_BEBO_MASK (0x200U)\r
+#define LCD_CTRL_BEBO_SHIFT (9U)\r
+/*! BEBO - Big-endian Byte Order.\r
+ */\r
+#define LCD_CTRL_BEBO(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BEBO_SHIFT)) & LCD_CTRL_BEBO_MASK)\r
+#define LCD_CTRL_BEPO_MASK (0x400U)\r
+#define LCD_CTRL_BEPO_SHIFT (10U)\r
+/*! BEPO - Big-Endian Pixel Ordering.\r
+ */\r
+#define LCD_CTRL_BEPO(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BEPO_SHIFT)) & LCD_CTRL_BEPO_MASK)\r
+#define LCD_CTRL_LCDPWR_MASK (0x800U)\r
+#define LCD_CTRL_LCDPWR_SHIFT (11U)\r
+/*! LCDPWR - LCD power enable.\r
+ */\r
+#define LCD_CTRL_LCDPWR(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDPWR_SHIFT)) & LCD_CTRL_LCDPWR_MASK)\r
+#define LCD_CTRL_LCDVCOMP_MASK (0x3000U)\r
+#define LCD_CTRL_LCDVCOMP_SHIFT (12U)\r
+/*! LCDVCOMP - LCD Vertical Compare Interrupt.\r
+ */\r
+#define LCD_CTRL_LCDVCOMP(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDVCOMP_SHIFT)) & LCD_CTRL_LCDVCOMP_MASK)\r
+#define LCD_CTRL_WATERMARK_MASK (0x10000U)\r
+#define LCD_CTRL_WATERMARK_SHIFT (16U)\r
+/*! WATERMARK - LCD DMA FIFO watermark level.\r
+ */\r
+#define LCD_CTRL_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_WATERMARK_SHIFT)) & LCD_CTRL_WATERMARK_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTMSK - Interrupt Mask register */\r
+/*! @{ */\r
+#define LCD_INTMSK_FUFIM_MASK (0x2U)\r
+#define LCD_INTMSK_FUFIM_SHIFT (1U)\r
+/*! FUFIM - FIFO underflow interrupt enable.\r
+ */\r
+#define LCD_INTMSK_FUFIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_FUFIM_SHIFT)) & LCD_INTMSK_FUFIM_MASK)\r
+#define LCD_INTMSK_LNBUIM_MASK (0x4U)\r
+#define LCD_INTMSK_LNBUIM_SHIFT (2U)\r
+/*! LNBUIM - LCD next base address update interrupt enable.\r
+ */\r
+#define LCD_INTMSK_LNBUIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_LNBUIM_SHIFT)) & LCD_INTMSK_LNBUIM_MASK)\r
+#define LCD_INTMSK_VCOMPIM_MASK (0x8U)\r
+#define LCD_INTMSK_VCOMPIM_SHIFT (3U)\r
+/*! VCOMPIM - Vertical compare interrupt enable.\r
+ */\r
+#define LCD_INTMSK_VCOMPIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_VCOMPIM_SHIFT)) & LCD_INTMSK_VCOMPIM_MASK)\r
+#define LCD_INTMSK_BERIM_MASK (0x10U)\r
+#define LCD_INTMSK_BERIM_SHIFT (4U)\r
+/*! BERIM - AHB master error interrupt enable.\r
+ */\r
+#define LCD_INTMSK_BERIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_BERIM_SHIFT)) & LCD_INTMSK_BERIM_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTRAW - Raw Interrupt Status register */\r
+/*! @{ */\r
+#define LCD_INTRAW_FUFRIS_MASK (0x2U)\r
+#define LCD_INTRAW_FUFRIS_SHIFT (1U)\r
+/*! FUFRIS - FIFO underflow raw interrupt status.\r
+ */\r
+#define LCD_INTRAW_FUFRIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_FUFRIS_SHIFT)) & LCD_INTRAW_FUFRIS_MASK)\r
+#define LCD_INTRAW_LNBURIS_MASK (0x4U)\r
+#define LCD_INTRAW_LNBURIS_SHIFT (2U)\r
+/*! LNBURIS - LCD next address base update raw interrupt status.\r
+ */\r
+#define LCD_INTRAW_LNBURIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_LNBURIS_SHIFT)) & LCD_INTRAW_LNBURIS_MASK)\r
+#define LCD_INTRAW_VCOMPRIS_MASK (0x8U)\r
+#define LCD_INTRAW_VCOMPRIS_SHIFT (3U)\r
+/*! VCOMPRIS - Vertical compare raw interrupt status.\r
+ */\r
+#define LCD_INTRAW_VCOMPRIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_VCOMPRIS_SHIFT)) & LCD_INTRAW_VCOMPRIS_MASK)\r
+#define LCD_INTRAW_BERRAW_MASK (0x10U)\r
+#define LCD_INTRAW_BERRAW_SHIFT (4U)\r
+/*! BERRAW - AHB master bus error raw interrupt status.\r
+ */\r
+#define LCD_INTRAW_BERRAW(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_BERRAW_SHIFT)) & LCD_INTRAW_BERRAW_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTSTAT - Masked Interrupt Status register */\r
+/*! @{ */\r
+#define LCD_INTSTAT_FUFMIS_MASK (0x2U)\r
+#define LCD_INTSTAT_FUFMIS_SHIFT (1U)\r
+/*! FUFMIS - FIFO underflow masked interrupt status.\r
+ */\r
+#define LCD_INTSTAT_FUFMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_FUFMIS_SHIFT)) & LCD_INTSTAT_FUFMIS_MASK)\r
+#define LCD_INTSTAT_LNBUMIS_MASK (0x4U)\r
+#define LCD_INTSTAT_LNBUMIS_SHIFT (2U)\r
+/*! LNBUMIS - LCD next address base update masked interrupt status.\r
+ */\r
+#define LCD_INTSTAT_LNBUMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_LNBUMIS_SHIFT)) & LCD_INTSTAT_LNBUMIS_MASK)\r
+#define LCD_INTSTAT_VCOMPMIS_MASK (0x8U)\r
+#define LCD_INTSTAT_VCOMPMIS_SHIFT (3U)\r
+/*! VCOMPMIS - Vertical compare masked interrupt status.\r
+ */\r
+#define LCD_INTSTAT_VCOMPMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_VCOMPMIS_SHIFT)) & LCD_INTSTAT_VCOMPMIS_MASK)\r
+#define LCD_INTSTAT_BERMIS_MASK (0x10U)\r
+#define LCD_INTSTAT_BERMIS_SHIFT (4U)\r
+/*! BERMIS - AHB master bus error masked interrupt status.\r
+ */\r
+#define LCD_INTSTAT_BERMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_BERMIS_SHIFT)) & LCD_INTSTAT_BERMIS_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTCLR - Interrupt Clear register */\r
+/*! @{ */\r
+#define LCD_INTCLR_FUFIC_MASK (0x2U)\r
+#define LCD_INTCLR_FUFIC_SHIFT (1U)\r
+/*! FUFIC - FIFO underflow interrupt clear.\r
+ */\r
+#define LCD_INTCLR_FUFIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_FUFIC_SHIFT)) & LCD_INTCLR_FUFIC_MASK)\r
+#define LCD_INTCLR_LNBUIC_MASK (0x4U)\r
+#define LCD_INTCLR_LNBUIC_SHIFT (2U)\r
+/*! LNBUIC - LCD next address base update interrupt clear.\r
+ */\r
+#define LCD_INTCLR_LNBUIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_LNBUIC_SHIFT)) & LCD_INTCLR_LNBUIC_MASK)\r
+#define LCD_INTCLR_VCOMPIC_MASK (0x8U)\r
+#define LCD_INTCLR_VCOMPIC_SHIFT (3U)\r
+/*! VCOMPIC - Vertical compare interrupt clear.\r
+ */\r
+#define LCD_INTCLR_VCOMPIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_VCOMPIC_SHIFT)) & LCD_INTCLR_VCOMPIC_MASK)\r
+#define LCD_INTCLR_BERIC_MASK (0x10U)\r
+#define LCD_INTCLR_BERIC_SHIFT (4U)\r
+/*! BERIC - AHB master error interrupt clear.\r
+ */\r
+#define LCD_INTCLR_BERIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_BERIC_SHIFT)) & LCD_INTCLR_BERIC_MASK)\r
+/*! @} */\r
+\r
+/*! @name UPCURR - Upper Panel Current Address Value register */\r
+/*! @{ */\r
+#define LCD_UPCURR_LCDUPCURR_MASK (0xFFFFFFFFU)\r
+#define LCD_UPCURR_LCDUPCURR_SHIFT (0U)\r
+/*! LCDUPCURR - LCD Upper Panel Current Address.\r
+ */\r
+#define LCD_UPCURR_LCDUPCURR(x) (((uint32_t)(((uint32_t)(x)) << LCD_UPCURR_LCDUPCURR_SHIFT)) & LCD_UPCURR_LCDUPCURR_MASK)\r
+/*! @} */\r
+\r
+/*! @name LPCURR - Lower Panel Current Address Value register */\r
+/*! @{ */\r
+#define LCD_LPCURR_LCDLPCURR_MASK (0xFFFFFFFFU)\r
+#define LCD_LPCURR_LCDLPCURR_SHIFT (0U)\r
+/*! LCDLPCURR - LCD Lower Panel Current Address.\r
+ */\r
+#define LCD_LPCURR_LCDLPCURR(x) (((uint32_t)(((uint32_t)(x)) << LCD_LPCURR_LCDLPCURR_SHIFT)) & LCD_LPCURR_LCDLPCURR_MASK)\r
+/*! @} */\r
+\r
+/*! @name PAL - 256x16-bit Color Palette registers */\r
+/*! @{ */\r
+#define LCD_PAL_R04_0_MASK (0x1FU)\r
+#define LCD_PAL_R04_0_SHIFT (0U)\r
+/*! R04_0 - Red palette data.\r
+ */\r
+#define LCD_PAL_R04_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_R04_0_SHIFT)) & LCD_PAL_R04_0_MASK)\r
+#define LCD_PAL_G04_0_MASK (0x3E0U)\r
+#define LCD_PAL_G04_0_SHIFT (5U)\r
+/*! G04_0 - Green palette data.\r
+ */\r
+#define LCD_PAL_G04_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_G04_0_SHIFT)) & LCD_PAL_G04_0_MASK)\r
+#define LCD_PAL_B04_0_MASK (0x7C00U)\r
+#define LCD_PAL_B04_0_SHIFT (10U)\r
+/*! B04_0 - Blue palette data.\r
+ */\r
+#define LCD_PAL_B04_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_B04_0_SHIFT)) & LCD_PAL_B04_0_MASK)\r
+#define LCD_PAL_I0_MASK (0x8000U)\r
+#define LCD_PAL_I0_SHIFT (15U)\r
+/*! I0 - Intensity / unused bit.\r
+ */\r
+#define LCD_PAL_I0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_I0_SHIFT)) & LCD_PAL_I0_MASK)\r
+#define LCD_PAL_R14_0_MASK (0x1F0000U)\r
+#define LCD_PAL_R14_0_SHIFT (16U)\r
+/*! R14_0 - Red palette data.\r
+ */\r
+#define LCD_PAL_R14_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_R14_0_SHIFT)) & LCD_PAL_R14_0_MASK)\r
+#define LCD_PAL_G14_0_MASK (0x3E00000U)\r
+#define LCD_PAL_G14_0_SHIFT (21U)\r
+/*! G14_0 - Green palette data.\r
+ */\r
+#define LCD_PAL_G14_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_G14_0_SHIFT)) & LCD_PAL_G14_0_MASK)\r
+#define LCD_PAL_B14_0_MASK (0x7C000000U)\r
+#define LCD_PAL_B14_0_SHIFT (26U)\r
+/*! B14_0 - Blue palette data.\r
+ */\r
+#define LCD_PAL_B14_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_B14_0_SHIFT)) & LCD_PAL_B14_0_MASK)\r
+#define LCD_PAL_I1_MASK (0x80000000U)\r
+#define LCD_PAL_I1_SHIFT (31U)\r
+/*! I1 - Intensity / unused bit.\r
+ */\r
+#define LCD_PAL_I1(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_I1_SHIFT)) & LCD_PAL_I1_MASK)\r
+/*! @} */\r
+\r
+/* The count of LCD_PAL */\r
+#define LCD_PAL_COUNT (128U)\r
+\r
+/*! @name CRSR_IMG - Cursor Image registers */\r
+/*! @{ */\r
+#define LCD_CRSR_IMG_CRSR_IMG_MASK (0xFFFFFFFFU)\r
+#define LCD_CRSR_IMG_CRSR_IMG_SHIFT (0U)\r
+/*! CRSR_IMG - Cursor Image data.\r
+ */\r
+#define LCD_CRSR_IMG_CRSR_IMG(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_IMG_CRSR_IMG_SHIFT)) & LCD_CRSR_IMG_CRSR_IMG_MASK)\r
+/*! @} */\r
+\r
+/* The count of LCD_CRSR_IMG */\r
+#define LCD_CRSR_IMG_COUNT (256U)\r
+\r
+/*! @name CRSR_CTRL - Cursor Control register */\r
+/*! @{ */\r
+#define LCD_CRSR_CTRL_CRSRON_MASK (0x1U)\r
+#define LCD_CRSR_CTRL_CRSRON_SHIFT (0U)\r
+/*! CRSRON - Cursor enable.\r
+ */\r
+#define LCD_CRSR_CTRL_CRSRON(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CTRL_CRSRON_SHIFT)) & LCD_CRSR_CTRL_CRSRON_MASK)\r
+#define LCD_CRSR_CTRL_CRSRNUM1_0_MASK (0x30U)\r
+#define LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT (4U)\r
+/*! CRSRNUM1_0 - Cursor image number.\r
+ */\r
+#define LCD_CRSR_CTRL_CRSRNUM1_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT)) & LCD_CRSR_CTRL_CRSRNUM1_0_MASK)\r
+/*! @} */\r
+\r
+/*! @name CRSR_CFG - Cursor Configuration register */\r
+/*! @{ */\r
+#define LCD_CRSR_CFG_CRSRSIZE_MASK (0x1U)\r
+#define LCD_CRSR_CFG_CRSRSIZE_SHIFT (0U)\r
+/*! CRSRSIZE - Cursor size selection.\r
+ */\r
+#define LCD_CRSR_CFG_CRSRSIZE(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CFG_CRSRSIZE_SHIFT)) & LCD_CRSR_CFG_CRSRSIZE_MASK)\r
+#define LCD_CRSR_CFG_FRAMESYNC_MASK (0x2U)\r
+#define LCD_CRSR_CFG_FRAMESYNC_SHIFT (1U)\r
+/*! FRAMESYNC - Cursor frame synchronization type.\r
+ */\r
+#define LCD_CRSR_CFG_FRAMESYNC(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CFG_FRAMESYNC_SHIFT)) & LCD_CRSR_CFG_FRAMESYNC_MASK)\r
+/*! @} */\r
+\r
+/*! @name CRSR_PAL0 - Cursor Palette register 0 */\r
+/*! @{ */\r
+#define LCD_CRSR_PAL0_RED_MASK (0xFFU)\r
+#define LCD_CRSR_PAL0_RED_SHIFT (0U)\r
+/*! RED - Red color component.\r
+ */\r
+#define LCD_CRSR_PAL0_RED(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_RED_SHIFT)) & LCD_CRSR_PAL0_RED_MASK)\r
+#define LCD_CRSR_PAL0_GREEN_MASK (0xFF00U)\r
+#define LCD_CRSR_PAL0_GREEN_SHIFT (8U)\r
+/*! GREEN - Green color component.\r
+ */\r
+#define LCD_CRSR_PAL0_GREEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_GREEN_SHIFT)) & LCD_CRSR_PAL0_GREEN_MASK)\r
+#define LCD_CRSR_PAL0_BLUE_MASK (0xFF0000U)\r
+#define LCD_CRSR_PAL0_BLUE_SHIFT (16U)\r
+/*! BLUE - Blue color component.\r
+ */\r
+#define LCD_CRSR_PAL0_BLUE(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_BLUE_SHIFT)) & LCD_CRSR_PAL0_BLUE_MASK)\r
+/*! @} */\r
+\r
+/*! @name CRSR_PAL1 - Cursor Palette register 1 */\r
+/*! @{ */\r
+#define LCD_CRSR_PAL1_RED_MASK (0xFFU)\r
+#define LCD_CRSR_PAL1_RED_SHIFT (0U)\r
+/*! RED - Red color component.\r
+ */\r
+#define LCD_CRSR_PAL1_RED(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_RED_SHIFT)) & LCD_CRSR_PAL1_RED_MASK)\r
+#define LCD_CRSR_PAL1_GREEN_MASK (0xFF00U)\r
+#define LCD_CRSR_PAL1_GREEN_SHIFT (8U)\r
+/*! GREEN - Green color component.\r
+ */\r
+#define LCD_CRSR_PAL1_GREEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_GREEN_SHIFT)) & LCD_CRSR_PAL1_GREEN_MASK)\r
+#define LCD_CRSR_PAL1_BLUE_MASK (0xFF0000U)\r
+#define LCD_CRSR_PAL1_BLUE_SHIFT (16U)\r
+/*! BLUE - Blue color component.\r
+ */\r
+#define LCD_CRSR_PAL1_BLUE(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_BLUE_SHIFT)) & LCD_CRSR_PAL1_BLUE_MASK)\r
+/*! @} */\r
+\r
+/*! @name CRSR_XY - Cursor XY Position register */\r
+/*! @{ */\r
+#define LCD_CRSR_XY_CRSRX_MASK (0x3FFU)\r
+#define LCD_CRSR_XY_CRSRX_SHIFT (0U)\r
+/*! CRSRX - X ordinate of the cursor origin measured in pixels.\r
+ */\r
+#define LCD_CRSR_XY_CRSRX(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_XY_CRSRX_SHIFT)) & LCD_CRSR_XY_CRSRX_MASK)\r
+#define LCD_CRSR_XY_CRSRY_MASK (0x3FF0000U)\r
+#define LCD_CRSR_XY_CRSRY_SHIFT (16U)\r
+/*! CRSRY - Y ordinate of the cursor origin measured in pixels.\r
+ */\r
+#define LCD_CRSR_XY_CRSRY(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_XY_CRSRY_SHIFT)) & LCD_CRSR_XY_CRSRY_MASK)\r
+/*! @} */\r
+\r
+/*! @name CRSR_CLIP - Cursor Clip Position register */\r
+/*! @{ */\r
+#define LCD_CRSR_CLIP_CRSRCLIPX_MASK (0x3FU)\r
+#define LCD_CRSR_CLIP_CRSRCLIPX_SHIFT (0U)\r
+/*! CRSRCLIPX - Cursor clip position for X direction.\r
+ */\r
+#define LCD_CRSR_CLIP_CRSRCLIPX(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CLIP_CRSRCLIPX_SHIFT)) & LCD_CRSR_CLIP_CRSRCLIPX_MASK)\r
+#define LCD_CRSR_CLIP_CRSRCLIPY_MASK (0x3F00U)\r
+#define LCD_CRSR_CLIP_CRSRCLIPY_SHIFT (8U)\r
+/*! CRSRCLIPY - Cursor clip position for Y direction.\r
+ */\r
+#define LCD_CRSR_CLIP_CRSRCLIPY(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CLIP_CRSRCLIPY_SHIFT)) & LCD_CRSR_CLIP_CRSRCLIPY_MASK)\r
+/*! @} */\r
+\r
+/*! @name CRSR_INTMSK - Cursor Interrupt Mask register */\r
+/*! @{ */\r
+#define LCD_CRSR_INTMSK_CRSRIM_MASK (0x1U)\r
+#define LCD_CRSR_INTMSK_CRSRIM_SHIFT (0U)\r
+/*! CRSRIM - Cursor interrupt mask.\r
+ */\r
+#define LCD_CRSR_INTMSK_CRSRIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTMSK_CRSRIM_SHIFT)) & LCD_CRSR_INTMSK_CRSRIM_MASK)\r
+/*! @} */\r
+\r
+/*! @name CRSR_INTCLR - Cursor Interrupt Clear register */\r
+/*! @{ */\r
+#define LCD_CRSR_INTCLR_CRSRIC_MASK (0x1U)\r
+#define LCD_CRSR_INTCLR_CRSRIC_SHIFT (0U)\r
+/*! CRSRIC - Cursor interrupt clear.\r
+ */\r
+#define LCD_CRSR_INTCLR_CRSRIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTCLR_CRSRIC_SHIFT)) & LCD_CRSR_INTCLR_CRSRIC_MASK)\r
+/*! @} */\r
+\r
+/*! @name CRSR_INTRAW - Cursor Raw Interrupt Status register */\r
+/*! @{ */\r
+#define LCD_CRSR_INTRAW_CRSRRIS_MASK (0x1U)\r
+#define LCD_CRSR_INTRAW_CRSRRIS_SHIFT (0U)\r
+/*! CRSRRIS - Cursor raw interrupt status.\r
+ */\r
+#define LCD_CRSR_INTRAW_CRSRRIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTRAW_CRSRRIS_SHIFT)) & LCD_CRSR_INTRAW_CRSRRIS_MASK)\r
+/*! @} */\r
+\r
+/*! @name CRSR_INTSTAT - Cursor Masked Interrupt Status register */\r
+/*! @{ */\r
+#define LCD_CRSR_INTSTAT_CRSRMIS_MASK (0x1U)\r
+#define LCD_CRSR_INTSTAT_CRSRMIS_SHIFT (0U)\r
+/*! CRSRMIS - Cursor masked interrupt status.\r
+ */\r
+#define LCD_CRSR_INTSTAT_CRSRMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTSTAT_CRSRMIS_SHIFT)) & LCD_CRSR_INTSTAT_CRSRMIS_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group LCD_Register_Masks */\r
+\r
+\r
+/* LCD - Peripheral instance base addresses */\r
+/** Peripheral LCD base address */\r
+#define LCD_BASE (0x40083000u)\r
+/** Peripheral LCD base pointer */\r
+#define LCD ((LCD_Type *)LCD_BASE)\r
+/** Array initializer of LCD peripheral base addresses */\r
+#define LCD_BASE_ADDRS { LCD_BASE }\r
+/** Array initializer of LCD peripheral base pointers */\r
+#define LCD_BASE_PTRS { LCD }\r
+/** Interrupt vectors for the LCD peripheral type */\r
+#define LCD_IRQS { LCD_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group LCD_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- MRT Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** MRT - Register Layout Typedef */\r
+typedef struct {\r
+ struct { /* offset: 0x0, array step: 0x10 */\r
+ __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */\r
+ __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */\r
+ __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */\r
+ __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */\r
+ } CHANNEL[4];\r
+ uint8_t RESERVED_0[176];\r
+ __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */\r
+ __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */\r
+ __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */\r
+} MRT_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- MRT Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup MRT_Register_Masks MRT Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */\r
+/*! @{ */\r
+#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU)\r
+#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U)\r
+/*! IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT\r
+ * channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to\r
+ * this bit field starts the timer immediately. If the timer is running, writing a zero to this\r
+ * bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer\r
+ * stops at the end of the time interval.\r
+ */\r
+#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK)\r
+#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U)\r
+#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U)\r
+/*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register.\r
+ * This bit is write-only. Reading this bit always returns 0.\r
+ * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the\r
+ * time interval if the repeat mode is selected.\r
+ * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.\r
+ */\r
+#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK)\r
+/*! @} */\r
+\r
+/* The count of MRT_CHANNEL_INTVAL */\r
+#define MRT_CHANNEL_INTVAL_COUNT (4U)\r
+\r
+/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */\r
+/*! @{ */\r
+#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU)\r
+#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U)\r
+/*! VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn\r
+ * register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval\r
+ * or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn\r
+ * register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields\r
+ * returns -1 (0x00FF FFFF).\r
+ */\r
+#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK)\r
+/*! @} */\r
+\r
+/* The count of MRT_CHANNEL_TIMER */\r
+#define MRT_CHANNEL_TIMER_COUNT (4U)\r
+\r
+/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */\r
+/*! @{ */\r
+#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U)\r
+#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U)\r
+/*! INTEN - Enable the TIMERn interrupt.\r
+ * 0b0..Disabled. TIMERn interrupt is disabled.\r
+ * 0b1..Enabled. TIMERn interrupt is enabled.\r
+ */\r
+#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK)\r
+#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U)\r
+#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U)\r
+/*! MODE - Selects timer mode.\r
+ * 0b00..Repeat interrupt mode.\r
+ * 0b01..One-shot interrupt mode.\r
+ * 0b10..One-shot stall mode.\r
+ * 0b11..Reserved.\r
+ */\r
+#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK)\r
+/*! @} */\r
+\r
+/* The count of MRT_CHANNEL_CTRL */\r
+#define MRT_CHANNEL_CTRL_COUNT (4U)\r
+\r
+/*! @name CHANNEL_STAT - MRT Status register. */\r
+/*! @{ */\r
+#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U)\r
+#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U)\r
+/*! INTFLAG - Monitors the interrupt flag.\r
+ * 0b0..No pending interrupt. Writing a zero is equivalent to no operation.\r
+ * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If\r
+ * the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt\r
+ * are raised. Writing a 1 to this bit clears the interrupt request.\r
+ */\r
+#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK)\r
+#define MRT_CHANNEL_STAT_RUN_MASK (0x2U)\r
+#define MRT_CHANNEL_STAT_RUN_SHIFT (1U)\r
+/*! RUN - Indicates the state of TIMERn. This bit is read-only.\r
+ * 0b0..Idle state. TIMERn is stopped.\r
+ * 0b1..Running. TIMERn is running.\r
+ */\r
+#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK)\r
+#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U)\r
+#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U)\r
+/*! INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG\r
+ * register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating\r
+ * modes.\r
+ * 0b0..This channel is not in use.\r
+ * 0b1..This channel is in use.\r
+ */\r
+#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK)\r
+/*! @} */\r
+\r
+/* The count of MRT_CHANNEL_STAT */\r
+#define MRT_CHANNEL_STAT_COUNT (4U)\r
+\r
+/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */\r
+/*! @{ */\r
+#define MRT_MODCFG_NOC_MASK (0xFU)\r
+#define MRT_MODCFG_NOC_SHIFT (0U)\r
+/*! NOC - Identifies the number of channels in this MRT.(4 channels on this device.)\r
+ */\r
+#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK)\r
+#define MRT_MODCFG_NOB_MASK (0x1F0U)\r
+#define MRT_MODCFG_NOB_SHIFT (4U)\r
+/*! NOB - Identifies the number of timer bits in this MRT. (24 bits wide on this device.)\r
+ */\r
+#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK)\r
+#define MRT_MODCFG_MULTITASK_MASK (0x80000000U)\r
+#define MRT_MODCFG_MULTITASK_SHIFT (31U)\r
+/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register.\r
+ * 0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset.\r
+ * 0b1..Multi-task mode.\r
+ */\r
+#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK)\r
+/*! @} */\r
+\r
+/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */\r
+/*! @{ */\r
+#define MRT_IDLE_CH_CHAN_MASK (0xF0U)\r
+#define MRT_IDLE_CH_CHAN_SHIFT (4U)\r
+/*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is\r
+ * positioned such that it can be used as an offset from the MRT base address in order to access\r
+ * the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See\r
+ * text above for more details.\r
+ */\r
+#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)\r
+/*! @} */\r
+\r
+/*! @name IRQ_FLAG - Global interrupt flag register */\r
+/*! @{ */\r
+#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U)\r
+#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U)\r
+/*! GFLAG0 - Monitors the interrupt flag of TIMER0.\r
+ * 0b0..No pending interrupt. Writing a zero is equivalent to no operation.\r
+ * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If\r
+ * the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global\r
+ * interrupt are raised. Writing a 1 to this bit clears the interrupt request.\r
+ */\r
+#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)\r
+#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U)\r
+#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U)\r
+/*! GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0.\r
+ */\r
+#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)\r
+#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U)\r
+#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U)\r
+/*! GFLAG2 - Monitors the interrupt flag of TIMER2. See description of channel 0.\r
+ */\r
+#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK)\r
+#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U)\r
+#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U)\r
+/*! GFLAG3 - Monitors the interrupt flag of TIMER3. See description of channel 0.\r
+ */\r
+#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group MRT_Register_Masks */\r
+\r
+\r
+/* MRT - Peripheral instance base addresses */\r
+/** Peripheral MRT0 base address */\r
+#define MRT0_BASE (0x4000D000u)\r
+/** Peripheral MRT0 base pointer */\r
+#define MRT0 ((MRT_Type *)MRT0_BASE)\r
+/** Array initializer of MRT peripheral base addresses */\r
+#define MRT_BASE_ADDRS { MRT0_BASE }\r
+/** Array initializer of MRT peripheral base pointers */\r
+#define MRT_BASE_PTRS { MRT0 }\r
+/** Interrupt vectors for the MRT peripheral type */\r
+#define MRT_IRQS { MRT0_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group MRT_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- OTPC Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup OTPC_Peripheral_Access_Layer OTPC Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** OTPC - Register Layout Typedef */\r
+typedef struct {\r
+ uint8_t RESERVED_0[16];\r
+ __I uint32_t AESKEY[8]; /**< Register for reading the AES key., array offset: 0x10, array step: 0x4 */\r
+ __I uint32_t ECRP; /**< ECRP options., offset: 0x30 */\r
+ uint8_t RESERVED_1[4];\r
+ __I uint32_t USER0; /**< User application specific options., offset: 0x38 */\r
+ __I uint32_t USER1; /**< User application specific options., offset: 0x3C */\r
+} OTPC_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- OTPC Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup OTPC_Register_Masks OTPC Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name AESKEY - Register for reading the AES key. */\r
+/*! @{ */\r
+#define OTPC_AESKEY_KEY_MASK (0xFFFFFFFFU)\r
+#define OTPC_AESKEY_KEY_SHIFT (0U)\r
+/*! KEY - AES key.\r
+ */\r
+#define OTPC_AESKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << OTPC_AESKEY_KEY_SHIFT)) & OTPC_AESKEY_KEY_MASK)\r
+/*! @} */\r
+\r
+/* The count of OTPC_AESKEY */\r
+#define OTPC_AESKEY_COUNT (8U)\r
+\r
+/*! @name ECRP - ECRP options. */\r
+/*! @{ */\r
+#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE_MASK (0x10U)\r
+#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE_SHIFT (4U)\r
+/*! CRP_MASS_ERASE_DISABLE - Disable or enable CRP mass erase.\r
+ */\r
+#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_MASS_ERASE_DISABLE_SHIFT)) & OTPC_ECRP_CRP_MASS_ERASE_DISABLE_MASK)\r
+#define OTPC_ECRP_IAP_PROTECTION_ENABLE_MASK (0x20U)\r
+#define OTPC_ECRP_IAP_PROTECTION_ENABLE_SHIFT (5U)\r
+/*! IAP_PROTECTION_ENABLE - This bit controls the ability to enable checking for ECRP in IAP functions.\r
+ */\r
+#define OTPC_ECRP_IAP_PROTECTION_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_IAP_PROTECTION_ENABLE_SHIFT)) & OTPC_ECRP_IAP_PROTECTION_ENABLE_MASK)\r
+#define OTPC_ECRP_CRP_ISP_DISABLE_PIN_MASK (0x40U)\r
+#define OTPC_ECRP_CRP_ISP_DISABLE_PIN_SHIFT (6U)\r
+/*! CRP_ISP_DISABLE_PIN - This bit controls the ability to enter ISP mode using the ISP pin.\r
+ */\r
+#define OTPC_ECRP_CRP_ISP_DISABLE_PIN(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ISP_DISABLE_PIN_SHIFT)) & OTPC_ECRP_CRP_ISP_DISABLE_PIN_MASK)\r
+#define OTPC_ECRP_CRP_ISP_DISABLE_IAP_MASK (0x80U)\r
+#define OTPC_ECRP_CRP_ISP_DISABLE_IAP_SHIFT (7U)\r
+/*! CRP_ISP_DISABLE_IAP - This bit controls the ability to re-invoke ISP using IAP routines.\r
+ */\r
+#define OTPC_ECRP_CRP_ISP_DISABLE_IAP(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ISP_DISABLE_IAP_SHIFT)) & OTPC_ECRP_CRP_ISP_DISABLE_IAP_MASK)\r
+#define OTPC_ECRP_CRP_ALLOW_ZERO_MASK (0x200U)\r
+#define OTPC_ECRP_CRP_ALLOW_ZERO_SHIFT (9U)\r
+/*! CRP_ALLOW_ZERO - This bit controls how 0 is treated when read as a ECRP value..\r
+ */\r
+#define OTPC_ECRP_CRP_ALLOW_ZERO(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ALLOW_ZERO_SHIFT)) & OTPC_ECRP_CRP_ALLOW_ZERO_MASK)\r
+#define OTPC_ECRP_JTAG_DISABLE_MASK (0x80000000U)\r
+#define OTPC_ECRP_JTAG_DISABLE_SHIFT (31U)\r
+/*! JTAG_DISABLE - 0 => Enable SWD/JTAG; 1 => Disable SWD/JTAG..\r
+ */\r
+#define OTPC_ECRP_JTAG_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_JTAG_DISABLE_SHIFT)) & OTPC_ECRP_JTAG_DISABLE_MASK)\r
+/*! @} */\r
+\r
+/*! @name USER0 - User application specific options. */\r
+/*! @{ */\r
+#define OTPC_USER0_USER0_MASK (0xFFFFFFFFU)\r
+#define OTPC_USER0_USER0_SHIFT (0U)\r
+/*! USER0 - User application specific option.\r
+ */\r
+#define OTPC_USER0_USER0(x) (((uint32_t)(((uint32_t)(x)) << OTPC_USER0_USER0_SHIFT)) & OTPC_USER0_USER0_MASK)\r
+/*! @} */\r
+\r
+/*! @name USER1 - User application specific options. */\r
+/*! @{ */\r
+#define OTPC_USER1_USER1_MASK (0xFFFFFFFFU)\r
+#define OTPC_USER1_USER1_SHIFT (0U)\r
+/*! USER1 - User application specific option.\r
+ */\r
+#define OTPC_USER1_USER1(x) (((uint32_t)(((uint32_t)(x)) << OTPC_USER1_USER1_SHIFT)) & OTPC_USER1_USER1_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group OTPC_Register_Masks */\r
+\r
+\r
+/* OTPC - Peripheral instance base addresses */\r
+/** Peripheral OTPC base address */\r
+#define OTPC_BASE (0x40015000u)\r
+/** Peripheral OTPC base pointer */\r
+#define OTPC ((OTPC_Type *)OTPC_BASE)\r
+/** Array initializer of OTPC peripheral base addresses */\r
+#define OTPC_BASE_ADDRS { OTPC_BASE }\r
+/** Array initializer of OTPC peripheral base pointers */\r
+#define OTPC_BASE_PTRS { OTPC }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group OTPC_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- PINT Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** PINT - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */\r
+ __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */\r
+ __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */\r
+ __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */\r
+ __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */\r
+ __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */\r
+ __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */\r
+ __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */\r
+ __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */\r
+ __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */\r
+ __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */\r
+ __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */\r
+ __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */\r
+} PINT_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- PINT Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup PINT_Register_Masks PINT Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name ISEL - Pin Interrupt Mode register */\r
+/*! @{ */\r
+#define PINT_ISEL_PMODE_MASK (0xFFU)\r
+#define PINT_ISEL_PMODE_SHIFT (0U)\r
+/*! PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt\r
+ * selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive\r
+ */\r
+#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK)\r
+/*! @} */\r
+\r
+/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */\r
+/*! @{ */\r
+#define PINT_IENR_ENRL_MASK (0xFFU)\r
+#define PINT_IENR_ENRL_SHIFT (0U)\r
+/*! ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the\r
+ * pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable\r
+ * rising edge or level interrupt.\r
+ */\r
+#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK)\r
+/*! @} */\r
+\r
+/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */\r
+/*! @{ */\r
+#define PINT_SIENR_SETENRL_MASK (0xFFU)\r
+#define PINT_SIENR_SETENRL_SHIFT (0U)\r
+/*! SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n\r
+ * sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.\r
+ */\r
+#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK)\r
+/*! @} */\r
+\r
+/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */\r
+/*! @{ */\r
+#define PINT_CIENR_CENRL_MASK (0xFFU)\r
+#define PINT_CIENR_CENRL_SHIFT (0U)\r
+/*! CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit\r
+ * n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level\r
+ * interrupt.\r
+ */\r
+#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK)\r
+/*! @} */\r
+\r
+/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */\r
+/*! @{ */\r
+#define PINT_IENF_ENAF_MASK (0xFFU)\r
+#define PINT_IENF_ENAF_SHIFT (0U)\r
+/*! ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt.\r
+ * Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt\r
+ * or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active\r
+ * interrupt level HIGH.\r
+ */\r
+#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK)\r
+/*! @} */\r
+\r
+/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */\r
+/*! @{ */\r
+#define PINT_SIENF_SETENAF_MASK (0xFFU)\r
+#define PINT_SIENF_SETENAF_SHIFT (0U)\r
+/*! SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n\r
+ * sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable\r
+ * falling edge interrupt.\r
+ */\r
+#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK)\r
+/*! @} */\r
+\r
+/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */\r
+/*! @{ */\r
+#define PINT_CIENF_CENAF_MASK (0xFFU)\r
+#define PINT_CIENF_CENAF_SHIFT (0U)\r
+/*! CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n\r
+ * clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or\r
+ * falling edge interrupt disabled.\r
+ */\r
+#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK)\r
+/*! @} */\r
+\r
+/*! @name RISE - Pin interrupt rising edge register */\r
+/*! @{ */\r
+#define PINT_RISE_RDET_MASK (0xFFU)\r
+#define PINT_RISE_RDET_SHIFT (0U)\r
+/*! RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read\r
+ * 0: No rising edge has been detected on this pin since Reset or the last time a one was written\r
+ * to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the\r
+ * last time a one was written to this bit. Write 1: clear rising edge detection for this pin.\r
+ */\r
+#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK)\r
+/*! @} */\r
+\r
+/*! @name FALL - Pin interrupt falling edge register */\r
+/*! @{ */\r
+#define PINT_FALL_FDET_MASK (0xFFU)\r
+#define PINT_FALL_FDET_SHIFT (0U)\r
+/*! FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read\r
+ * 0: No falling edge has been detected on this pin since Reset or the last time a one was\r
+ * written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or\r
+ * the last time a one was written to this bit. Write 1: clear falling edge detection for this\r
+ * pin.\r
+ */\r
+#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK)\r
+/*! @} */\r
+\r
+/*! @name IST - Pin interrupt status register */\r
+/*! @{ */\r
+#define PINT_IST_PSTAT_MASK (0xFFU)\r
+#define PINT_IST_PSTAT_SHIFT (0U)\r
+/*! PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts\r
+ * the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for\r
+ * this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this\r
+ * interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin.\r
+ * Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).\r
+ */\r
+#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK)\r
+/*! @} */\r
+\r
+/*! @name PMCTRL - Pattern match interrupt control register */\r
+/*! @{ */\r
+#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U)\r
+#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U)\r
+/*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function.\r
+ * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function.\r
+ * 0b1..Pattern match. Interrupts are driven in response to pattern matches.\r
+ */\r
+#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK)\r
+#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U)\r
+#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U)\r
+/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true.\r
+ * 0b0..Disabled. RXEV output to the CPU is disabled.\r
+ * 0b1..Enabled. RXEV output to the CPU is enabled.\r
+ */\r
+#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK)\r
+#define PINT_PMCTRL_PMAT_MASK (0xFF000000U)\r
+#define PINT_PMCTRL_PMAT_SHIFT (24U)\r
+/*! PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field\r
+ * indicates that the corresponding product term is matched by the current state of the appropriate\r
+ * inputs.\r
+ */\r
+#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK)\r
+/*! @} */\r
+\r
+/*! @name PMSRC - Pattern match interrupt bit-slice source register */\r
+/*! @{ */\r
+#define PINT_PMSRC_SRC0_MASK (0x700U)\r
+#define PINT_PMSRC_SRC0_SHIFT (8U)\r
+/*! SRC0 - Selects the input source for bit slice 0\r
+ * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0.\r
+ * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0.\r
+ * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0.\r
+ * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0.\r
+ * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0.\r
+ * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0.\r
+ * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0.\r
+ * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0.\r
+ */\r
+#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK)\r
+#define PINT_PMSRC_SRC1_MASK (0x3800U)\r
+#define PINT_PMSRC_SRC1_SHIFT (11U)\r
+/*! SRC1 - Selects the input source for bit slice 1\r
+ * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1.\r
+ * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1.\r
+ * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1.\r
+ * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1.\r
+ * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1.\r
+ * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1.\r
+ * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1.\r
+ * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1.\r
+ */\r
+#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK)\r
+#define PINT_PMSRC_SRC2_MASK (0x1C000U)\r
+#define PINT_PMSRC_SRC2_SHIFT (14U)\r
+/*! SRC2 - Selects the input source for bit slice 2\r
+ * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2.\r
+ * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2.\r
+ * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2.\r
+ * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2.\r
+ * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2.\r
+ * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2.\r
+ * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2.\r
+ * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2.\r
+ */\r
+#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK)\r
+#define PINT_PMSRC_SRC3_MASK (0xE0000U)\r
+#define PINT_PMSRC_SRC3_SHIFT (17U)\r
+/*! SRC3 - Selects the input source for bit slice 3\r
+ * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3.\r
+ * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3.\r
+ * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3.\r
+ * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3.\r
+ * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3.\r
+ * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3.\r
+ * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3.\r
+ * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3.\r
+ */\r
+#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK)\r
+#define PINT_PMSRC_SRC4_MASK (0x700000U)\r
+#define PINT_PMSRC_SRC4_SHIFT (20U)\r
+/*! SRC4 - Selects the input source for bit slice 4\r
+ * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4.\r
+ * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4.\r
+ * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4.\r
+ * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4.\r
+ * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4.\r
+ * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4.\r
+ * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4.\r
+ * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4.\r
+ */\r
+#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK)\r
+#define PINT_PMSRC_SRC5_MASK (0x3800000U)\r
+#define PINT_PMSRC_SRC5_SHIFT (23U)\r
+/*! SRC5 - Selects the input source for bit slice 5\r
+ * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5.\r
+ * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5.\r
+ * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5.\r
+ * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5.\r
+ * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5.\r
+ * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5.\r
+ * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5.\r
+ * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5.\r
+ */\r
+#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK)\r
+#define PINT_PMSRC_SRC6_MASK (0x1C000000U)\r
+#define PINT_PMSRC_SRC6_SHIFT (26U)\r
+/*! SRC6 - Selects the input source for bit slice 6\r
+ * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6.\r
+ * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6.\r
+ * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6.\r
+ * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6.\r
+ * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6.\r
+ * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6.\r
+ * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6.\r
+ * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6.\r
+ */\r
+#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK)\r
+#define PINT_PMSRC_SRC7_MASK (0xE0000000U)\r
+#define PINT_PMSRC_SRC7_SHIFT (29U)\r
+/*! SRC7 - Selects the input source for bit slice 7\r
+ * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7.\r
+ * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7.\r
+ * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7.\r
+ * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7.\r
+ * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7.\r
+ * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7.\r
+ * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7.\r
+ * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7.\r
+ */\r
+#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK)\r
+/*! @} */\r
+\r
+/*! @name PMCFG - Pattern match interrupt bit slice configuration register */\r
+/*! @{ */\r
+#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U)\r
+#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U)\r
+/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint.\r
+ * 0b0..No effect. Slice 0 is not an endpoint.\r
+ * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true.\r
+ */\r
+#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK)\r
+#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U)\r
+#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U)\r
+/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint.\r
+ * 0b0..No effect. Slice 1 is not an endpoint.\r
+ * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true.\r
+ */\r
+#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK)\r
+#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U)\r
+#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U)\r
+/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint.\r
+ * 0b0..No effect. Slice 2 is not an endpoint.\r
+ * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true.\r
+ */\r
+#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK)\r
+#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U)\r
+#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U)\r
+/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint.\r
+ * 0b0..No effect. Slice 3 is not an endpoint.\r
+ * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true.\r
+ */\r
+#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK)\r
+#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U)\r
+#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U)\r
+/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint.\r
+ * 0b0..No effect. Slice 4 is not an endpoint.\r
+ * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true.\r
+ */\r
+#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK)\r
+#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U)\r
+#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U)\r
+/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint.\r
+ * 0b0..No effect. Slice 5 is not an endpoint.\r
+ * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true.\r
+ */\r
+#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK)\r
+#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U)\r
+#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U)\r
+/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint.\r
+ * 0b0..No effect. Slice 6 is not an endpoint.\r
+ * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true.\r
+ */\r
+#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK)\r
+#define PINT_PMCFG_CFG0_MASK (0x700U)\r
+#define PINT_PMCFG_CFG0_SHIFT (8U)\r
+/*! CFG0 - Specifies the match contribution condition for bit slice 0.\r
+ * 0b000..Constant HIGH. This bit slice always contributes to a product term match.\r
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last\r
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the\r
+ * PMSRC registers are written to.\r
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last\r
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the\r
+ * PMSRC registers are written to.\r
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input\r
+ * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only\r
+ * cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.\r
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.\r
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).\r
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or\r
+ * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit\r
+ * is cleared after one clock cycle.\r
+ */\r
+#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK)\r
+#define PINT_PMCFG_CFG1_MASK (0x3800U)\r
+#define PINT_PMCFG_CFG1_SHIFT (11U)\r
+/*! CFG1 - Specifies the match contribution condition for bit slice 1.\r
+ * 0b000..Constant HIGH. This bit slice always contributes to a product term match.\r
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last\r
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the\r
+ * PMSRC registers are written to.\r
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last\r
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the\r
+ * PMSRC registers are written to.\r
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input\r
+ * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only\r
+ * cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.\r
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.\r
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).\r
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or\r
+ * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit\r
+ * is cleared after one clock cycle.\r
+ */\r
+#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK)\r
+#define PINT_PMCFG_CFG2_MASK (0x1C000U)\r
+#define PINT_PMCFG_CFG2_SHIFT (14U)\r
+/*! CFG2 - Specifies the match contribution condition for bit slice 2.\r
+ * 0b000..Constant HIGH. This bit slice always contributes to a product term match.\r
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last\r
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the\r
+ * PMSRC registers are written to.\r
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last\r
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the\r
+ * PMSRC registers are written to.\r
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input\r
+ * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only\r
+ * cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.\r
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.\r
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).\r
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or\r
+ * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit\r
+ * is cleared after one clock cycle.\r
+ */\r
+#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK)\r
+#define PINT_PMCFG_CFG3_MASK (0xE0000U)\r
+#define PINT_PMCFG_CFG3_SHIFT (17U)\r
+/*! CFG3 - Specifies the match contribution condition for bit slice 3.\r
+ * 0b000..Constant HIGH. This bit slice always contributes to a product term match.\r
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last\r
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the\r
+ * PMSRC registers are written to.\r
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last\r
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the\r
+ * PMSRC registers are written to.\r
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input\r
+ * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only\r
+ * cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.\r
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.\r
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).\r
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or\r
+ * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit\r
+ * is cleared after one clock cycle.\r
+ */\r
+#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK)\r
+#define PINT_PMCFG_CFG4_MASK (0x700000U)\r
+#define PINT_PMCFG_CFG4_SHIFT (20U)\r
+/*! CFG4 - Specifies the match contribution condition for bit slice 4.\r
+ * 0b000..Constant HIGH. This bit slice always contributes to a product term match.\r
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last\r
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the\r
+ * PMSRC registers are written to.\r
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last\r
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the\r
+ * PMSRC registers are written to.\r
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input\r
+ * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only\r
+ * cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.\r
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.\r
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).\r
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or\r
+ * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit\r
+ * is cleared after one clock cycle.\r
+ */\r
+#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK)\r
+#define PINT_PMCFG_CFG5_MASK (0x3800000U)\r
+#define PINT_PMCFG_CFG5_SHIFT (23U)\r
+/*! CFG5 - Specifies the match contribution condition for bit slice 5.\r
+ * 0b000..Constant HIGH. This bit slice always contributes to a product term match.\r
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last\r
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the\r
+ * PMSRC registers are written to.\r
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last\r
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the\r
+ * PMSRC registers are written to.\r
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input\r
+ * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only\r
+ * cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.\r
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.\r
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).\r
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or\r
+ * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit\r
+ * is cleared after one clock cycle.\r
+ */\r
+#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK)\r
+#define PINT_PMCFG_CFG6_MASK (0x1C000000U)\r
+#define PINT_PMCFG_CFG6_SHIFT (26U)\r
+/*! CFG6 - Specifies the match contribution condition for bit slice 6.\r
+ * 0b000..Constant HIGH. This bit slice always contributes to a product term match.\r
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last\r
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the\r
+ * PMSRC registers are written to.\r
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last\r
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the\r
+ * PMSRC registers are written to.\r
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input\r
+ * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only\r
+ * cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.\r
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.\r
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).\r
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or\r
+ * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit\r
+ * is cleared after one clock cycle.\r
+ */\r
+#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK)\r
+#define PINT_PMCFG_CFG7_MASK (0xE0000000U)\r
+#define PINT_PMCFG_CFG7_SHIFT (29U)\r
+/*! CFG7 - Specifies the match contribution condition for bit slice 7.\r
+ * 0b000..Constant HIGH. This bit slice always contributes to a product term match.\r
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last\r
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the\r
+ * PMSRC registers are written to.\r
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last\r
+ * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the\r
+ * PMSRC registers are written to.\r
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input\r
+ * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only\r
+ * cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.\r
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.\r
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).\r
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or\r
+ * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit\r
+ * is cleared after one clock cycle.\r
+ */\r
+#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group PINT_Register_Masks */\r
+\r
+\r
+/* PINT - Peripheral instance base addresses */\r
+/** Peripheral PINT base address */\r
+#define PINT_BASE (0x40004000u)\r
+/** Peripheral PINT base pointer */\r
+#define PINT ((PINT_Type *)PINT_BASE)\r
+/** Array initializer of PINT peripheral base addresses */\r
+#define PINT_BASE_ADDRS { PINT_BASE }\r
+/** Array initializer of PINT peripheral base pointers */\r
+#define PINT_BASE_PTRS { PINT }\r
+/** Interrupt vectors for the PINT peripheral type */\r
+#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group PINT_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- RIT Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup RIT_Peripheral_Access_Layer RIT Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** RIT - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t COMPVAL; /**< Compare value LSB register, offset: 0x0 */\r
+ __IO uint32_t MASK; /**< Mask LSB register, offset: 0x4 */\r
+ __IO uint32_t CTRL; /**< Control register, offset: 0x8 */\r
+ __IO uint32_t COUNTER; /**< Counter LSB register, offset: 0xC */\r
+ __IO uint32_t COMPVAL_H; /**< Compare value MSB register, offset: 0x10 */\r
+ __IO uint32_t MASK_H; /**< Mask MSB register, offset: 0x14 */\r
+ uint8_t RESERVED_0[4];\r
+ __IO uint32_t COUNTER_H; /**< Counter MSB register, offset: 0x1C */\r
+} RIT_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- RIT Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup RIT_Register_Masks RIT Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name COMPVAL - Compare value LSB register */\r
+/*! @{ */\r
+#define RIT_COMPVAL_RICOMP_MASK (0xFFFFFFFFU)\r
+#define RIT_COMPVAL_RICOMP_SHIFT (0U)\r
+/*! RICOMP - .\r
+ */\r
+#define RIT_COMPVAL_RICOMP(x) (((uint32_t)(((uint32_t)(x)) << RIT_COMPVAL_RICOMP_SHIFT)) & RIT_COMPVAL_RICOMP_MASK)\r
+/*! @} */\r
+\r
+/*! @name MASK - Mask LSB register */\r
+/*! @{ */\r
+#define RIT_MASK_RIMASK_MASK (0xFFFFFFFFU)\r
+#define RIT_MASK_RIMASK_SHIFT (0U)\r
+/*! RIMASK - Mask register.\r
+ */\r
+#define RIT_MASK_RIMASK(x) (((uint32_t)(((uint32_t)(x)) << RIT_MASK_RIMASK_SHIFT)) & RIT_MASK_RIMASK_MASK)\r
+/*! @} */\r
+\r
+/*! @name CTRL - Control register */\r
+/*! @{ */\r
+#define RIT_CTRL_RITINT_MASK (0x1U)\r
+#define RIT_CTRL_RITINT_SHIFT (0U)\r
+/*! RITINT - Interrupt flag.\r
+ */\r
+#define RIT_CTRL_RITINT(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITINT_SHIFT)) & RIT_CTRL_RITINT_MASK)\r
+#define RIT_CTRL_RITENCLR_MASK (0x2U)\r
+#define RIT_CTRL_RITENCLR_SHIFT (1U)\r
+/*! RITENCLR - Timer enable clear.\r
+ */\r
+#define RIT_CTRL_RITENCLR(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITENCLR_SHIFT)) & RIT_CTRL_RITENCLR_MASK)\r
+#define RIT_CTRL_RITENBR_MASK (0x4U)\r
+#define RIT_CTRL_RITENBR_SHIFT (2U)\r
+/*! RITENBR - Timer enable for debug.\r
+ */\r
+#define RIT_CTRL_RITENBR(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITENBR_SHIFT)) & RIT_CTRL_RITENBR_MASK)\r
+#define RIT_CTRL_RITEN_MASK (0x8U)\r
+#define RIT_CTRL_RITEN_SHIFT (3U)\r
+/*! RITEN - Timer enable.\r
+ */\r
+#define RIT_CTRL_RITEN(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITEN_SHIFT)) & RIT_CTRL_RITEN_MASK)\r
+/*! @} */\r
+\r
+/*! @name COUNTER - Counter LSB register */\r
+/*! @{ */\r
+#define RIT_COUNTER_RICOUNTER_MASK (0xFFFFFFFFU)\r
+#define RIT_COUNTER_RICOUNTER_SHIFT (0U)\r
+/*! RICOUNTER - 32 LSBs of the up counter.\r
+ */\r
+#define RIT_COUNTER_RICOUNTER(x) (((uint32_t)(((uint32_t)(x)) << RIT_COUNTER_RICOUNTER_SHIFT)) & RIT_COUNTER_RICOUNTER_MASK)\r
+/*! @} */\r
+\r
+/*! @name COMPVAL_H - Compare value MSB register */\r
+/*! @{ */\r
+#define RIT_COMPVAL_H_RICOMP_MASK (0xFFFFU)\r
+#define RIT_COMPVAL_H_RICOMP_SHIFT (0U)\r
+/*! RICOMP - Compare value MSB register.\r
+ */\r
+#define RIT_COMPVAL_H_RICOMP(x) (((uint32_t)(((uint32_t)(x)) << RIT_COMPVAL_H_RICOMP_SHIFT)) & RIT_COMPVAL_H_RICOMP_MASK)\r
+/*! @} */\r
+\r
+/*! @name MASK_H - Mask MSB register */\r
+/*! @{ */\r
+#define RIT_MASK_H_RIMASK_MASK (0xFFFFU)\r
+#define RIT_MASK_H_RIMASK_SHIFT (0U)\r
+/*! RIMASK - Mask register.\r
+ */\r
+#define RIT_MASK_H_RIMASK(x) (((uint32_t)(((uint32_t)(x)) << RIT_MASK_H_RIMASK_SHIFT)) & RIT_MASK_H_RIMASK_MASK)\r
+/*! @} */\r
+\r
+/*! @name COUNTER_H - Counter MSB register */\r
+/*! @{ */\r
+#define RIT_COUNTER_H_RICOUNTER_MASK (0xFFFFU)\r
+#define RIT_COUNTER_H_RICOUNTER_SHIFT (0U)\r
+/*! RICOUNTER - 16 LSBs of the up counter.\r
+ */\r
+#define RIT_COUNTER_H_RICOUNTER(x) (((uint32_t)(((uint32_t)(x)) << RIT_COUNTER_H_RICOUNTER_SHIFT)) & RIT_COUNTER_H_RICOUNTER_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group RIT_Register_Masks */\r
+\r
+\r
+/* RIT - Peripheral instance base addresses */\r
+/** Peripheral RIT base address */\r
+#define RIT_BASE (0x4002D000u)\r
+/** Peripheral RIT base pointer */\r
+#define RIT ((RIT_Type *)RIT_BASE)\r
+/** Array initializer of RIT peripheral base addresses */\r
+#define RIT_BASE_ADDRS { RIT_BASE }\r
+/** Array initializer of RIT peripheral base pointers */\r
+#define RIT_BASE_PTRS { RIT }\r
+/** Interrupt vectors for the RIT peripheral type */\r
+#define RIT_IRQS { RIT_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group RIT_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- RTC Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** RTC - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */\r
+ __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */\r
+ __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */\r
+ __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */\r
+ uint8_t RESERVED_0[48];\r
+ __IO uint32_t GPREG[8]; /**< General Purpose register, array offset: 0x40, array step: 0x4 */\r
+} RTC_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- RTC Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup RTC_Register_Masks RTC Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CTRL - RTC control register */\r
+/*! @{ */\r
+#define RTC_CTRL_SWRESET_MASK (0x1U)\r
+#define RTC_CTRL_SWRESET_SHIFT (0U)\r
+/*! SWRESET - Software reset control\r
+ * 0b0..Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC.\r
+ * 0b1..In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value\r
+ * except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes\r
+ * to set any of the other bits within this register. Do not attempt to write to any bits of this register at\r
+ * the same time that the reset bit is being cleared.\r
+ */\r
+#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK)\r
+#define RTC_CTRL_ALARM1HZ_MASK (0x4U)\r
+#define RTC_CTRL_ALARM1HZ_SHIFT (2U)\r
+/*! ALARM1HZ - RTC 1 Hz timer alarm flag status.\r
+ * 0b0..No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect.\r
+ * 0b1..Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt\r
+ * request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit.\r
+ */\r
+#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK)\r
+#define RTC_CTRL_WAKE1KHZ_MASK (0x8U)\r
+#define RTC_CTRL_WAKE1KHZ_SHIFT (3U)\r
+/*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status.\r
+ * 0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect.\r
+ * 0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up\r
+ * interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit.\r
+ */\r
+#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK)\r
+#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U)\r
+#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U)\r
+/*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down.\r
+ * 0b0..Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode.\r
+ * 0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode.\r
+ */\r
+#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK)\r
+#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U)\r
+#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U)\r
+/*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down.\r
+ * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode.\r
+ * 0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode.\r
+ */\r
+#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK)\r
+#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U)\r
+#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U)\r
+/*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz\r
+ * timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0).\r
+ * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode.\r
+ * 0b1..Enable. The 1 kHz RTC timer is enabled.\r
+ */\r
+#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK)\r
+#define RTC_CTRL_RTC_EN_MASK (0x80U)\r
+#define RTC_CTRL_RTC_EN_SHIFT (7U)\r
+/*! RTC_EN - RTC enable.\r
+ * 0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should\r
+ * be 0 when writing to load a value in the RTC counter register.\r
+ * 0b1..Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate\r
+ * operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the\r
+ * high-resolution, 1 kHz clock, set bit 6 in this register.\r
+ */\r
+#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK)\r
+#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U)\r
+#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U)\r
+/*! RTC_OSC_PD - RTC oscillator power-down control.\r
+ * 0b0..See RTC_OSC_BYPASS\r
+ * 0b1..RTC oscillator is powered-down.\r
+ */\r
+#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK)\r
+/*! @} */\r
+\r
+/*! @name MATCH - RTC match register */\r
+/*! @{ */\r
+#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU)\r
+#define RTC_MATCH_MATVAL_SHIFT (0U)\r
+/*! MATVAL - Contains the match value against which the 1 Hz RTC timer will be compared to set the\r
+ * alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled.\r
+ */\r
+#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name COUNT - RTC counter register */\r
+/*! @{ */\r
+#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU)\r
+#define RTC_COUNT_VAL_SHIFT (0U)\r
+/*! VAL - A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial\r
+ * value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC\r
+ * Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this\r
+ * register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after\r
+ * the RTC_EN bit is set.\r
+ */\r
+#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name WAKE - High-resolution/wake-up timer control register */\r
+/*! @{ */\r
+#define RTC_WAKE_VAL_MASK (0xFFFFU)\r
+#define RTC_WAKE_VAL_SHIFT (0U)\r
+/*! VAL - A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads\r
+ * a start count value into the wake-up timer and initializes a count-down sequence. Do not write\r
+ * to this register while counting is in progress.\r
+ */\r
+#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name GPREG - General Purpose register */\r
+/*! @{ */\r
+#define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU)\r
+#define RTC_GPREG_GPDATA_SHIFT (0U)\r
+/*! GPDATA - Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied.\r
+ */\r
+#define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK)\r
+/*! @} */\r
+\r
+/* The count of RTC_GPREG */\r
+#define RTC_GPREG_COUNT (8U)\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group RTC_Register_Masks */\r
+\r
+\r
+/* RTC - Peripheral instance base addresses */\r
+/** Peripheral RTC base address */\r
+#define RTC_BASE (0x4002C000u)\r
+/** Peripheral RTC base pointer */\r
+#define RTC ((RTC_Type *)RTC_BASE)\r
+/** Array initializer of RTC peripheral base addresses */\r
+#define RTC_BASE_ADDRS { RTC_BASE }\r
+/** Array initializer of RTC peripheral base pointers */\r
+#define RTC_BASE_PTRS { RTC }\r
+/** Interrupt vectors for the RTC peripheral type */\r
+#define RTC_IRQS { RTC_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group RTC_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SCT Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** SCT - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */\r
+ __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */\r
+ __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */\r
+ __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */\r
+ __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */\r
+ __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */\r
+ uint8_t RESERVED_0[40];\r
+ __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */\r
+ __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */\r
+ __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */\r
+ __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */\r
+ __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */\r
+ __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */\r
+ __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */\r
+ __IO uint32_t DMAREQ0; /**< SCT DMA request 0 register, offset: 0x5C */\r
+ __IO uint32_t DMAREQ1; /**< SCT DMA request 1 register, offset: 0x60 */\r
+ uint8_t RESERVED_1[140];\r
+ __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */\r
+ __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */\r
+ __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */\r
+ __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */\r
+ union { /* offset: 0x100 */\r
+ __IO uint32_t CAP[16]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */\r
+ __IO uint32_t MATCH[16]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */\r
+ };\r
+ uint8_t RESERVED_2[192];\r
+ union { /* offset: 0x200 */\r
+ __IO uint32_t CAPCTRL[16]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */\r
+ __IO uint32_t MATCHREL[16]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */\r
+ };\r
+ uint8_t RESERVED_3[192];\r
+ struct { /* offset: 0x300, array step: 0x8 */\r
+ __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */\r
+ __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */\r
+ } EV[16];\r
+ uint8_t RESERVED_4[384];\r
+ struct { /* offset: 0x500, array step: 0x8 */\r
+ __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */\r
+ __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */\r
+ } OUT[10];\r
+} SCT_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SCT Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup SCT_Register_Masks SCT Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CONFIG - SCT configuration register */\r
+/*! @{ */\r
+#define SCT_CONFIG_UNIFY_MASK (0x1U)\r
+#define SCT_CONFIG_UNIFY_SHIFT (0U)\r
+/*! UNIFY - SCT operation\r
+ * 0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H.\r
+ * 0b1..The SCT operates as a unified 32-bit counter.\r
+ */\r
+#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK)\r
+#define SCT_CONFIG_CLKMODE_MASK (0x6U)\r
+#define SCT_CONFIG_CLKMODE_SHIFT (1U)\r
+/*! CLKMODE - SCT clock mode\r
+ * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers.\r
+ * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are\r
+ * only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The\r
+ * minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the\r
+ * high-performance, sampled-clock mode.\r
+ * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the\r
+ * counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the\r
+ * clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode.\r
+ * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL\r
+ * field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system\r
+ * clock. The input clock rate must be at least half the system clock rate and can be the same or faster than\r
+ * the system clock.\r
+ */\r
+#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK)\r
+#define SCT_CONFIG_CKSEL_MASK (0x78U)\r
+#define SCT_CONFIG_CKSEL_SHIFT (3U)\r
+/*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent\r
+ * on the CLKMODE bit selection in this register.\r
+ * 0b0000..Rising edges on input 0.\r
+ * 0b0001..Falling edges on input 0.\r
+ * 0b0010..Rising edges on input 1.\r
+ * 0b0011..Falling edges on input 1.\r
+ * 0b0100..Rising edges on input 2.\r
+ * 0b0101..Falling edges on input 2.\r
+ * 0b0110..Rising edges on input 3.\r
+ * 0b0111..Falling edges on input 3.\r
+ * 0b1000..Rising edges on input 4.\r
+ * 0b1001..Falling edges on input 4.\r
+ * 0b1010..Rising edges on input 5.\r
+ * 0b1011..Falling edges on input 5.\r
+ * 0b1100..Rising edges on input 6.\r
+ * 0b1101..Falling edges on input 6.\r
+ * 0b1110..Rising edges on input 7.\r
+ * 0b1111..Falling edges on input 7.\r
+ */\r
+#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK)\r
+#define SCT_CONFIG_NORELOAD_L_MASK (0x80U)\r
+#define SCT_CONFIG_NORELOAD_L_SHIFT (7U)\r
+/*! NORELOAD_L - A 1 in this bit prevents the lower match registers from being reloaded from their\r
+ * respective reload registers. Setting this bit eliminates the need to write to the reload\r
+ * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any\r
+ * time. This bit applies to both the higher and lower registers when the UNIFY bit is set.\r
+ */\r
+#define SCT_CONFIG_NORELOAD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK)\r
+#define SCT_CONFIG_NORELOAD_H_MASK (0x100U)\r
+#define SCT_CONFIG_NORELOAD_H_SHIFT (8U)\r
+/*! NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their\r
+ * respective reload registers. Setting this bit eliminates the need to write to the reload\r
+ * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at\r
+ * any time. This bit is not used when the UNIFY bit is set.\r
+ */\r
+#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK)\r
+#define SCT_CONFIG_INSYNC_MASK (0x1FE00U)\r
+#define SCT_CONFIG_INSYNC_SHIFT (9U)\r
+/*! INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all\r
+ * other bits are reserved. A 1 in one of these bits subjects the corresponding input to\r
+ * synchronization to the SCT clock, before it is used to create an event. If an input is known to\r
+ * already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note:\r
+ * The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input\r
+ * clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation.\r
+ * It does not apply to the clock input specified in the CKSEL field.\r
+ */\r
+#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK)\r
+#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U)\r
+#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U)\r
+/*! AUTOLIMIT_L - A one in this bit causes a match on match register 0 to be treated as a de-facto\r
+ * LIMIT condition without the need to define an associated event. As with any LIMIT event, this\r
+ * automatic limit causes the counter to be cleared to zero in unidirectional mode or to change\r
+ * the direction of count in bi-directional mode. Software can write to set or clear this bit at\r
+ * any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.\r
+ */\r
+#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK)\r
+#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U)\r
+#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U)\r
+/*! AUTOLIMIT_H - A one in this bit will cause a match on match register 0 to be treated as a\r
+ * de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event,\r
+ * this automatic limit causes the counter to be cleared to zero in unidirectional mode or to\r
+ * change the direction of count in bi-directional mode. Software can write to set or clear this bit\r
+ * at any time. This bit is not used when the UNIFY bit is set.\r
+ */\r
+#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK)\r
+/*! @} */\r
+\r
+/*! @name CTRL - SCT control register */\r
+/*! @{ */\r
+#define SCT_CTRL_DOWN_L_MASK (0x1U)\r
+#define SCT_CTRL_DOWN_L_SHIFT (0U)\r
+/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit\r
+ * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit\r
+ * when the counter is counting down and a limit condition occurs or when the counter reaches 0.\r
+ */\r
+#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK)\r
+#define SCT_CTRL_STOP_L_MASK (0x2U)\r
+#define SCT_CTRL_STOP_L_SHIFT (1U)\r
+/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events\r
+ * related to the counter can occur. If a designated start event occurs, this bit is cleared and\r
+ * counting resumes.\r
+ */\r
+#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK)\r
+#define SCT_CTRL_HALT_L_MASK (0x4U)\r
+#define SCT_CTRL_HALT_L_SHIFT (2U)\r
+/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A\r
+ * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to\r
+ * remove the halt condition while keeping the SCT in the stop condition (not running) with a\r
+ * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set,\r
+ * only software can clear this bit to restore counter operation. This bit is set on reset.\r
+ */\r
+#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK)\r
+#define SCT_CTRL_CLRCTR_L_MASK (0x8U)\r
+#define SCT_CTRL_CLRCTR_L_SHIFT (3U)\r
+/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.\r
+ */\r
+#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK)\r
+#define SCT_CTRL_BIDIR_L_MASK (0x10U)\r
+#define SCT_CTRL_BIDIR_L_SHIFT (4U)\r
+/*! BIDIR_L - L or unified counter direction select\r
+ * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero.\r
+ * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0.\r
+ */\r
+#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK)\r
+#define SCT_CTRL_PRE_L_MASK (0x1FE0U)\r
+#define SCT_CTRL_PRE_L_SHIFT (5U)\r
+/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified\r
+ * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1.\r
+ * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.\r
+ */\r
+#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK)\r
+#define SCT_CTRL_DOWN_H_MASK (0x10000U)\r
+#define SCT_CTRL_DOWN_H_SHIFT (16U)\r
+/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the\r
+ * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit\r
+ * when the counter is counting down and a limit condition occurs or when the counter reaches 0.\r
+ */\r
+#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK)\r
+#define SCT_CTRL_STOP_H_MASK (0x20000U)\r
+#define SCT_CTRL_STOP_H_SHIFT (17U)\r
+/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to\r
+ * the counter can occur. If such an event matches the mask in the Start register, this bit is\r
+ * cleared and counting resumes.\r
+ */\r
+#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK)\r
+#define SCT_CTRL_HALT_H_MASK (0x40000U)\r
+#define SCT_CTRL_HALT_H_SHIFT (18U)\r
+/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets\r
+ * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the\r
+ * halt condition while keeping the SCT in the stop condition (not running) with a single write to\r
+ * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit\r
+ * can only be cleared by software to restore counter operation. This bit is set on reset.\r
+ */\r
+#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK)\r
+#define SCT_CTRL_CLRCTR_H_MASK (0x80000U)\r
+#define SCT_CTRL_CLRCTR_H_SHIFT (19U)\r
+/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0.\r
+ */\r
+#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK)\r
+#define SCT_CTRL_BIDIR_H_MASK (0x100000U)\r
+#define SCT_CTRL_BIDIR_H_SHIFT (20U)\r
+/*! BIDIR_H - Direction select\r
+ * 0b0..The H counter counts up to its limit condition, then is cleared to zero.\r
+ * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0.\r
+ */\r
+#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK)\r
+#define SCT_CTRL_PRE_H_MASK (0x1FE00000U)\r
+#define SCT_CTRL_PRE_H_SHIFT (21U)\r
+/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock.\r
+ * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the\r
+ * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.\r
+ */\r
+#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK)\r
+/*! @} */\r
+\r
+/*! @name LIMIT - SCT limit event select register */\r
+/*! @{ */\r
+#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU)\r
+#define SCT_LIMIT_LIMMSK_L_SHIFT (0U)\r
+/*! LIMMSK_L - If bit n is one, event n is used as a counter limit for the L or unified counter\r
+ * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.\r
+ */\r
+#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK)\r
+#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U)\r
+#define SCT_LIMIT_LIMMSK_H_SHIFT (16U)\r
+/*! LIMMSK_H - If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit\r
+ * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.\r
+ */\r
+#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK)\r
+/*! @} */\r
+\r
+/*! @name HALT - SCT halt event select register */\r
+/*! @{ */\r
+#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU)\r
+#define SCT_HALT_HALTMSK_L_SHIFT (0U)\r
+/*! HALTMSK_L - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0,\r
+ * event 1 = bit 1, etc.). The number of bits = number of events in this SCT.\r
+ */\r
+#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK)\r
+#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U)\r
+#define SCT_HALT_HALTMSK_H_SHIFT (16U)\r
+/*! HALTMSK_H - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16,\r
+ * event 1 = bit 17, etc.). The number of bits = number of events in this SCT.\r
+ */\r
+#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK)\r
+/*! @} */\r
+\r
+/*! @name STOP - SCT stop event select register */\r
+/*! @{ */\r
+#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU)\r
+#define SCT_STOP_STOPMSK_L_SHIFT (0U)\r
+/*! STOPMSK_L - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0,\r
+ * event 1 = bit 1, etc.). The number of bits = number of events in this SCT.\r
+ */\r
+#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK)\r
+#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U)\r
+#define SCT_STOP_STOPMSK_H_SHIFT (16U)\r
+/*! STOPMSK_H - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16,\r
+ * event 1 = bit 17, etc.). The number of bits = number of events in this SCT.\r
+ */\r
+#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK)\r
+/*! @} */\r
+\r
+/*! @name START - SCT start event select register */\r
+/*! @{ */\r
+#define SCT_START_STARTMSK_L_MASK (0xFFFFU)\r
+#define SCT_START_STARTMSK_L_SHIFT (0U)\r
+/*! STARTMSK_L - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit\r
+ * 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.\r
+ */\r
+#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK)\r
+#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U)\r
+#define SCT_START_STARTMSK_H_SHIFT (16U)\r
+/*! STARTMSK_H - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit\r
+ * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.\r
+ */\r
+#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK)\r
+/*! @} */\r
+\r
+/*! @name COUNT - SCT counter register */\r
+/*! @{ */\r
+#define SCT_COUNT_CTR_L_MASK (0xFFFFU)\r
+#define SCT_COUNT_CTR_L_SHIFT (0U)\r
+/*! CTR_L - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write\r
+ * the lower 16 bits of the 32-bit unified counter.\r
+ */\r
+#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK)\r
+#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U)\r
+#define SCT_COUNT_CTR_H_SHIFT (16U)\r
+/*! CTR_H - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write\r
+ * the upper 16 bits of the 32-bit unified counter.\r
+ */\r
+#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK)\r
+/*! @} */\r
+\r
+/*! @name STATE - SCT state register */\r
+/*! @{ */\r
+#define SCT_STATE_STATE_L_MASK (0x1FU)\r
+#define SCT_STATE_STATE_L_SHIFT (0U)\r
+/*! STATE_L - State variable.\r
+ */\r
+#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK)\r
+#define SCT_STATE_STATE_H_MASK (0x1F0000U)\r
+#define SCT_STATE_STATE_H_SHIFT (16U)\r
+/*! STATE_H - State variable.\r
+ */\r
+#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK)\r
+/*! @} */\r
+\r
+/*! @name INPUT - SCT input register */\r
+/*! @{ */\r
+#define SCT_INPUT_AIN0_MASK (0x1U)\r
+#define SCT_INPUT_AIN0_SHIFT (0U)\r
+/*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge.\r
+ */\r
+#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK)\r
+#define SCT_INPUT_AIN1_MASK (0x2U)\r
+#define SCT_INPUT_AIN1_SHIFT (1U)\r
+/*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge.\r
+ */\r
+#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK)\r
+#define SCT_INPUT_AIN2_MASK (0x4U)\r
+#define SCT_INPUT_AIN2_SHIFT (2U)\r
+/*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge.\r
+ */\r
+#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK)\r
+#define SCT_INPUT_AIN3_MASK (0x8U)\r
+#define SCT_INPUT_AIN3_SHIFT (3U)\r
+/*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge.\r
+ */\r
+#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK)\r
+#define SCT_INPUT_AIN4_MASK (0x10U)\r
+#define SCT_INPUT_AIN4_SHIFT (4U)\r
+/*! AIN4 - Input 4 state. Input 4 state on the last SCT clock edge.\r
+ */\r
+#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK)\r
+#define SCT_INPUT_AIN5_MASK (0x20U)\r
+#define SCT_INPUT_AIN5_SHIFT (5U)\r
+/*! AIN5 - Input 5 state. Input 5 state on the last SCT clock edge.\r
+ */\r
+#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK)\r
+#define SCT_INPUT_AIN6_MASK (0x40U)\r
+#define SCT_INPUT_AIN6_SHIFT (6U)\r
+/*! AIN6 - Input 6 state. Input 6 state on the last SCT clock edge.\r
+ */\r
+#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK)\r
+#define SCT_INPUT_AIN7_MASK (0x80U)\r
+#define SCT_INPUT_AIN7_SHIFT (7U)\r
+/*! AIN7 - Input 7 state. Input 7 state on the last SCT clock edge.\r
+ */\r
+#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK)\r
+#define SCT_INPUT_AIN8_MASK (0x100U)\r
+#define SCT_INPUT_AIN8_SHIFT (8U)\r
+/*! AIN8 - Input 8 state. Input 8 state on the last SCT clock edge.\r
+ */\r
+#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK)\r
+#define SCT_INPUT_AIN9_MASK (0x200U)\r
+#define SCT_INPUT_AIN9_SHIFT (9U)\r
+/*! AIN9 - Input 9 state. Input 9 state on the last SCT clock edge.\r
+ */\r
+#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK)\r
+#define SCT_INPUT_AIN10_MASK (0x400U)\r
+#define SCT_INPUT_AIN10_SHIFT (10U)\r
+/*! AIN10 - Input 10 state. Input 10 state on the last SCT clock edge.\r
+ */\r
+#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK)\r
+#define SCT_INPUT_AIN11_MASK (0x800U)\r
+#define SCT_INPUT_AIN11_SHIFT (11U)\r
+/*! AIN11 - Input 11 state. Input 11 state on the last SCT clock edge.\r
+ */\r
+#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK)\r
+#define SCT_INPUT_AIN12_MASK (0x1000U)\r
+#define SCT_INPUT_AIN12_SHIFT (12U)\r
+/*! AIN12 - Input 12 state. Input 12 state on the last SCT clock edge.\r
+ */\r
+#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK)\r
+#define SCT_INPUT_AIN13_MASK (0x2000U)\r
+#define SCT_INPUT_AIN13_SHIFT (13U)\r
+/*! AIN13 - Input 13 state. Input 13 state on the last SCT clock edge.\r
+ */\r
+#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK)\r
+#define SCT_INPUT_AIN14_MASK (0x4000U)\r
+#define SCT_INPUT_AIN14_SHIFT (14U)\r
+/*! AIN14 - Input 14 state. Input 14 state on the last SCT clock edge.\r
+ */\r
+#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK)\r
+#define SCT_INPUT_AIN15_MASK (0x8000U)\r
+#define SCT_INPUT_AIN15_SHIFT (15U)\r
+/*! AIN15 - Input 15 state. Input 15 state on the last SCT clock edge.\r
+ */\r
+#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK)\r
+#define SCT_INPUT_SIN0_MASK (0x10000U)\r
+#define SCT_INPUT_SIN0_SHIFT (16U)\r
+/*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC.\r
+ */\r
+#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK)\r
+#define SCT_INPUT_SIN1_MASK (0x20000U)\r
+#define SCT_INPUT_SIN1_SHIFT (17U)\r
+/*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC.\r
+ */\r
+#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK)\r
+#define SCT_INPUT_SIN2_MASK (0x40000U)\r
+#define SCT_INPUT_SIN2_SHIFT (18U)\r
+/*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC.\r
+ */\r
+#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK)\r
+#define SCT_INPUT_SIN3_MASK (0x80000U)\r
+#define SCT_INPUT_SIN3_SHIFT (19U)\r
+/*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC.\r
+ */\r
+#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK)\r
+#define SCT_INPUT_SIN4_MASK (0x100000U)\r
+#define SCT_INPUT_SIN4_SHIFT (20U)\r
+/*! SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC.\r
+ */\r
+#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK)\r
+#define SCT_INPUT_SIN5_MASK (0x200000U)\r
+#define SCT_INPUT_SIN5_SHIFT (21U)\r
+/*! SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC.\r
+ */\r
+#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK)\r
+#define SCT_INPUT_SIN6_MASK (0x400000U)\r
+#define SCT_INPUT_SIN6_SHIFT (22U)\r
+/*! SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC.\r
+ */\r
+#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK)\r
+#define SCT_INPUT_SIN7_MASK (0x800000U)\r
+#define SCT_INPUT_SIN7_SHIFT (23U)\r
+/*! SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC.\r
+ */\r
+#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK)\r
+#define SCT_INPUT_SIN8_MASK (0x1000000U)\r
+#define SCT_INPUT_SIN8_SHIFT (24U)\r
+/*! SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC.\r
+ */\r
+#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK)\r
+#define SCT_INPUT_SIN9_MASK (0x2000000U)\r
+#define SCT_INPUT_SIN9_SHIFT (25U)\r
+/*! SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC.\r
+ */\r
+#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK)\r
+#define SCT_INPUT_SIN10_MASK (0x4000000U)\r
+#define SCT_INPUT_SIN10_SHIFT (26U)\r
+/*! SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC.\r
+ */\r
+#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK)\r
+#define SCT_INPUT_SIN11_MASK (0x8000000U)\r
+#define SCT_INPUT_SIN11_SHIFT (27U)\r
+/*! SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC.\r
+ */\r
+#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK)\r
+#define SCT_INPUT_SIN12_MASK (0x10000000U)\r
+#define SCT_INPUT_SIN12_SHIFT (28U)\r
+/*! SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC.\r
+ */\r
+#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK)\r
+#define SCT_INPUT_SIN13_MASK (0x20000000U)\r
+#define SCT_INPUT_SIN13_SHIFT (29U)\r
+/*! SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC.\r
+ */\r
+#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK)\r
+#define SCT_INPUT_SIN14_MASK (0x40000000U)\r
+#define SCT_INPUT_SIN14_SHIFT (30U)\r
+/*! SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC.\r
+ */\r
+#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK)\r
+#define SCT_INPUT_SIN15_MASK (0x80000000U)\r
+#define SCT_INPUT_SIN15_SHIFT (31U)\r
+/*! SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC.\r
+ */\r
+#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK)\r
+/*! @} */\r
+\r
+/*! @name REGMODE - SCT match/capture mode register */\r
+/*! @{ */\r
+#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU)\r
+#define SCT_REGMODE_REGMOD_L_SHIFT (0U)\r
+/*! REGMOD_L - Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1,\r
+ * etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as\r
+ * match register. 1 = register operates as capture register.\r
+ */\r
+#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK)\r
+#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U)\r
+#define SCT_REGMODE_REGMOD_H_SHIFT (16U)\r
+/*! REGMOD_H - Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit\r
+ * 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as\r
+ * match registers. 1 = register operates as capture registers.\r
+ */\r
+#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK)\r
+/*! @} */\r
+\r
+/*! @name OUTPUT - SCT output register */\r
+/*! @{ */\r
+#define SCT_OUTPUT_OUT_MASK (0xFFFFU)\r
+#define SCT_OUTPUT_OUT_SHIFT (0U)\r
+/*! OUT - Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the\r
+ * corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of\r
+ * outputs in this SCT.\r
+ */\r
+#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK)\r
+/*! @} */\r
+\r
+/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */\r
+/*! @{ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U)\r
+/*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U)\r
+/*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U)\r
+/*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U)\r
+/*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U)\r
+/*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U)\r
+/*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U)\r
+/*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U)\r
+/*! SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U)\r
+/*! SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U)\r
+/*! SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U)\r
+/*! SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U)\r
+/*! SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U)\r
+/*! SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U)\r
+/*! SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U)\r
+/*! SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U)\r
+/*! SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK)\r
+/*! @} */\r
+\r
+/*! @name RES - SCT conflict resolution register */\r
+/*! @{ */\r
+#define SCT_RES_O0RES_MASK (0x3U)\r
+#define SCT_RES_O0RES_SHIFT (0U)\r
+/*! O0RES - Effect of simultaneous set and clear on output 0.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output (or set based on the SETCLR0 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK)\r
+#define SCT_RES_O1RES_MASK (0xCU)\r
+#define SCT_RES_O1RES_SHIFT (2U)\r
+/*! O1RES - Effect of simultaneous set and clear on output 1.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output (or set based on the SETCLR1 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK)\r
+#define SCT_RES_O2RES_MASK (0x30U)\r
+#define SCT_RES_O2RES_SHIFT (4U)\r
+/*! O2RES - Effect of simultaneous set and clear on output 2.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output n (or set based on the SETCLR2 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK)\r
+#define SCT_RES_O3RES_MASK (0xC0U)\r
+#define SCT_RES_O3RES_SHIFT (6U)\r
+/*! O3RES - Effect of simultaneous set and clear on output 3.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output (or set based on the SETCLR3 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK)\r
+#define SCT_RES_O4RES_MASK (0x300U)\r
+#define SCT_RES_O4RES_SHIFT (8U)\r
+/*! O4RES - Effect of simultaneous set and clear on output 4.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output (or set based on the SETCLR4 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK)\r
+#define SCT_RES_O5RES_MASK (0xC00U)\r
+#define SCT_RES_O5RES_SHIFT (10U)\r
+/*! O5RES - Effect of simultaneous set and clear on output 5.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output (or set based on the SETCLR5 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK)\r
+#define SCT_RES_O6RES_MASK (0x3000U)\r
+#define SCT_RES_O6RES_SHIFT (12U)\r
+/*! O6RES - Effect of simultaneous set and clear on output 6.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output (or set based on the SETCLR6 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK)\r
+#define SCT_RES_O7RES_MASK (0xC000U)\r
+#define SCT_RES_O7RES_SHIFT (14U)\r
+/*! O7RES - Effect of simultaneous set and clear on output 7.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output n (or set based on the SETCLR7 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK)\r
+#define SCT_RES_O8RES_MASK (0x30000U)\r
+#define SCT_RES_O8RES_SHIFT (16U)\r
+/*! O8RES - Effect of simultaneous set and clear on output 8.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output (or set based on the SETCLR8 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK)\r
+#define SCT_RES_O9RES_MASK (0xC0000U)\r
+#define SCT_RES_O9RES_SHIFT (18U)\r
+/*! O9RES - Effect of simultaneous set and clear on output 9.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output (or set based on the SETCLR9 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK)\r
+#define SCT_RES_O10RES_MASK (0x300000U)\r
+#define SCT_RES_O10RES_SHIFT (20U)\r
+/*! O10RES - Effect of simultaneous set and clear on output 10.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output (or set based on the SETCLR10 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK)\r
+#define SCT_RES_O11RES_MASK (0xC00000U)\r
+#define SCT_RES_O11RES_SHIFT (22U)\r
+/*! O11RES - Effect of simultaneous set and clear on output 11.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output (or set based on the SETCLR11 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK)\r
+#define SCT_RES_O12RES_MASK (0x3000000U)\r
+#define SCT_RES_O12RES_SHIFT (24U)\r
+/*! O12RES - Effect of simultaneous set and clear on output 12.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output (or set based on the SETCLR12 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK)\r
+#define SCT_RES_O13RES_MASK (0xC000000U)\r
+#define SCT_RES_O13RES_SHIFT (26U)\r
+/*! O13RES - Effect of simultaneous set and clear on output 13.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output (or set based on the SETCLR13 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK)\r
+#define SCT_RES_O14RES_MASK (0x30000000U)\r
+#define SCT_RES_O14RES_SHIFT (28U)\r
+/*! O14RES - Effect of simultaneous set and clear on output 14.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output (or set based on the SETCLR14 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK)\r
+#define SCT_RES_O15RES_MASK (0xC0000000U)\r
+#define SCT_RES_O15RES_SHIFT (30U)\r
+/*! O15RES - Effect of simultaneous set and clear on output 15.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output (or set based on the SETCLR15 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK)\r
+/*! @} */\r
+\r
+/*! @name DMAREQ0 - SCT DMA request 0 register */\r
+/*! @{ */\r
+#define SCT_DMAREQ0_DEV_0_MASK (0xFFFFU)\r
+#define SCT_DMAREQ0_DEV_0_SHIFT (0U)\r
+/*! DEV_0 - If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1,\r
+ * etc.). The number of bits = number of events in this SCT.\r
+ */\r
+#define SCT_DMAREQ0_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK)\r
+#define SCT_DMAREQ0_DRL0_MASK (0x40000000U)\r
+#define SCT_DMAREQ0_DRL0_SHIFT (30U)\r
+/*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers.\r
+ */\r
+#define SCT_DMAREQ0_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK)\r
+#define SCT_DMAREQ0_DRQ0_MASK (0x80000000U)\r
+#define SCT_DMAREQ0_DRQ0_SHIFT (31U)\r
+/*! DRQ0 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA\r
+ * channel is enabled and properly set up, it is unlikely that software will see this flag, it will\r
+ * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA\r
+ * setup.\r
+ */\r
+#define SCT_DMAREQ0_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK)\r
+/*! @} */\r
+\r
+/*! @name DMAREQ1 - SCT DMA request 1 register */\r
+/*! @{ */\r
+#define SCT_DMAREQ1_DEV_1_MASK (0xFFFFU)\r
+#define SCT_DMAREQ1_DEV_1_SHIFT (0U)\r
+/*! DEV_1 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1,\r
+ * etc.). The number of bits = number of events in this SCT.\r
+ */\r
+#define SCT_DMAREQ1_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK)\r
+#define SCT_DMAREQ1_DRL1_MASK (0x40000000U)\r
+#define SCT_DMAREQ1_DRL1_SHIFT (30U)\r
+/*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers.\r
+ */\r
+#define SCT_DMAREQ1_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK)\r
+#define SCT_DMAREQ1_DRQ1_MASK (0x80000000U)\r
+#define SCT_DMAREQ1_DRQ1_SHIFT (31U)\r
+/*! DRQ1 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA\r
+ * channel is enabled and properly set up, it is unlikely that software will see this flag, it will\r
+ * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA\r
+ * setup.\r
+ */\r
+#define SCT_DMAREQ1_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK)\r
+/*! @} */\r
+\r
+/*! @name EVEN - SCT event interrupt enable register */\r
+/*! @{ */\r
+#define SCT_EVEN_IEN_MASK (0xFFFFU)\r
+#define SCT_EVEN_IEN_SHIFT (0U)\r
+/*! IEN - The SCT requests an interrupt when bit n of this register and the event flag register are\r
+ * both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in\r
+ * this SCT.\r
+ */\r
+#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK)\r
+/*! @} */\r
+\r
+/*! @name EVFLAG - SCT event flag register */\r
+/*! @{ */\r
+#define SCT_EVFLAG_FLAG_MASK (0xFFFFU)\r
+#define SCT_EVFLAG_FLAG_SHIFT (0U)\r
+/*! FLAG - Bit n is one if event n has occurred since reset or a 1 was last written to this bit\r
+ * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.\r
+ */\r
+#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name CONEN - SCT conflict interrupt enable register */\r
+/*! @{ */\r
+#define SCT_CONEN_NCEN_MASK (0xFFFFU)\r
+#define SCT_CONEN_NCEN_SHIFT (0U)\r
+/*! NCEN - The SCT requests an interrupt when bit n of this register and the SCT conflict flag\r
+ * register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of\r
+ * outputs in this SCT.\r
+ */\r
+#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK)\r
+/*! @} */\r
+\r
+/*! @name CONFLAG - SCT conflict flag register */\r
+/*! @{ */\r
+#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU)\r
+#define SCT_CONFLAG_NCFLAG_SHIFT (0U)\r
+/*! NCFLAG - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was\r
+ * last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits =\r
+ * number of outputs in this SCT.\r
+ */\r
+#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK)\r
+#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U)\r
+#define SCT_CONFLAG_BUSERRL_SHIFT (30U)\r
+/*! BUSERRL - The most recent bus error from this SCT involved writing CTR L/Unified, STATE\r
+ * L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write\r
+ * to certain L and H registers can be half successful and half unsuccessful.\r
+ */\r
+#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK)\r
+#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U)\r
+#define SCT_CONFLAG_BUSERRH_SHIFT (31U)\r
+/*! BUSERRH - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or\r
+ * the Output register when the H counter was not halted.\r
+ */\r
+#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK)\r
+/*! @} */\r
+\r
+/*! @name CAP - SCT capture register of capture channel */\r
+/*! @{ */\r
+#define SCT_CAP_CAPn_L_MASK (0xFFFFU)\r
+#define SCT_CAP_CAPn_L_SHIFT (0U)\r
+/*! CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured.\r
+ * When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last\r
+ * captured.\r
+ */\r
+#define SCT_CAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK)\r
+#define SCT_CAP_CAPn_H_MASK (0xFFFF0000U)\r
+#define SCT_CAP_CAPn_H_SHIFT (16U)\r
+/*! CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured.\r
+ * When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last\r
+ * captured.\r
+ */\r
+#define SCT_CAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK)\r
+/*! @} */\r
+\r
+/* The count of SCT_CAP */\r
+#define SCT_CAP_COUNT (16U)\r
+\r
+/*! @name MATCH - SCT match value register of match channels */\r
+/*! @{ */\r
+#define SCT_MATCH_MATCHn_L_MASK (0xFFFFU)\r
+#define SCT_MATCH_MATCHn_L_SHIFT (0U)\r
+/*! MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When\r
+ * UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified\r
+ * counter.\r
+ */\r
+#define SCT_MATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK)\r
+#define SCT_MATCH_MATCHn_H_MASK (0xFFFF0000U)\r
+#define SCT_MATCH_MATCHn_H_SHIFT (16U)\r
+/*! MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When\r
+ * UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified\r
+ * counter.\r
+ */\r
+#define SCT_MATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK)\r
+/*! @} */\r
+\r
+/* The count of SCT_MATCH */\r
+#define SCT_MATCH_COUNT (16U)\r
+\r
+/*! @name CAPCTRL - SCT capture control register */\r
+/*! @{ */\r
+#define SCT_CAPCTRL_CAPCONn_L_MASK (0xFFFFU)\r
+#define SCT_CAPCTRL_CAPCONn_L_SHIFT (0U)\r
+/*! CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1)\r
+ * register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of\r
+ * match/captures in this SCT.\r
+ */\r
+#define SCT_CAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_CAPCTRL_CAPCONn_L_MASK)\r
+#define SCT_CAPCTRL_CAPCONn_H_MASK (0xFFFF0000U)\r
+#define SCT_CAPCTRL_CAPCONn_H_SHIFT (16U)\r
+/*! CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event\r
+ * 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.\r
+ */\r
+#define SCT_CAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_CAPCTRL_CAPCONn_H_MASK)\r
+/*! @} */\r
+\r
+/* The count of SCT_CAPCTRL */\r
+#define SCT_CAPCTRL_COUNT (16U)\r
+\r
+/*! @name MATCHREL - SCT match reload value register */\r
+/*! @{ */\r
+#define SCT_MATCHREL_RELOADn_L_MASK (0xFFFFU)\r
+#define SCT_MATCHREL_RELOADn_L_SHIFT (0U)\r
+/*! RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register.\r
+ * When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn\r
+ * register.\r
+ */\r
+#define SCT_MATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK)\r
+#define SCT_MATCHREL_RELOADn_H_MASK (0xFFFF0000U)\r
+#define SCT_MATCHREL_RELOADn_H_SHIFT (16U)\r
+/*! RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When\r
+ * UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn\r
+ * register.\r
+ */\r
+#define SCT_MATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK)\r
+/*! @} */\r
+\r
+/* The count of SCT_MATCHREL */\r
+#define SCT_MATCHREL_COUNT (16U)\r
+\r
+/*! @name EV_STATE - SCT event state register 0 */\r
+/*! @{ */\r
+#define SCT_EV_STATE_STATEMSKn_MASK (0xFFFFU)\r
+#define SCT_EV_STATE_STATEMSKn_SHIFT (0U)\r
+/*! STATEMSKn - If bit m is one, event n happens in state m of the counter selected by the HEVENT\r
+ * bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of\r
+ * bits = number of states in this SCT.\r
+ */\r
+#define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK)\r
+/*! @} */\r
+\r
+/* The count of SCT_EV_STATE */\r
+#define SCT_EV_STATE_COUNT (16U)\r
+\r
+/*! @name EV_CTRL - SCT event control register 0 */\r
+/*! @{ */\r
+#define SCT_EV_CTRL_MATCHSEL_MASK (0xFU)\r
+#define SCT_EV_CTRL_MATCHSEL_SHIFT (0U)\r
+/*! MATCHSEL - Selects the Match register associated with this event (if any). A match can occur\r
+ * only when the counter selected by the HEVENT bit is running.\r
+ */\r
+#define SCT_EV_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK)\r
+#define SCT_EV_CTRL_HEVENT_MASK (0x10U)\r
+#define SCT_EV_CTRL_HEVENT_SHIFT (4U)\r
+/*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1.\r
+ * 0b0..Selects the L state and the L match register selected by MATCHSEL.\r
+ * 0b1..Selects the H state and the H match register selected by MATCHSEL.\r
+ */\r
+#define SCT_EV_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK)\r
+#define SCT_EV_CTRL_OUTSEL_MASK (0x20U)\r
+#define SCT_EV_CTRL_OUTSEL_SHIFT (5U)\r
+/*! OUTSEL - Input/output select\r
+ * 0b0..Selects the inputs selected by IOSEL.\r
+ * 0b1..Selects the outputs selected by IOSEL.\r
+ */\r
+#define SCT_EV_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK)\r
+#define SCT_EV_CTRL_IOSEL_MASK (0x3C0U)\r
+#define SCT_EV_CTRL_IOSEL_SHIFT (6U)\r
+/*! IOSEL - Selects the input or output signal number associated with this event (if any). Do not\r
+ * select an input in this register if CKMODE is 1x. In this case the clock input is an implicit\r
+ * ingredient of every event.\r
+ */\r
+#define SCT_EV_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK)\r
+#define SCT_EV_CTRL_IOCOND_MASK (0xC00U)\r
+#define SCT_EV_CTRL_IOCOND_SHIFT (10U)\r
+/*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the\r
+ * conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state\r
+ * detection, an input must have a minimum pulse width of at least one SCT clock period .\r
+ * 0b00..LOW\r
+ * 0b01..Rise\r
+ * 0b10..Fall\r
+ * 0b11..HIGH\r
+ */\r
+#define SCT_EV_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK)\r
+#define SCT_EV_CTRL_COMBMODE_MASK (0x3000U)\r
+#define SCT_EV_CTRL_COMBMODE_SHIFT (12U)\r
+/*! COMBMODE - Selects how the specified match and I/O condition are used and combined.\r
+ * 0b00..OR. The event occurs when either the specified match or I/O condition occurs.\r
+ * 0b01..MATCH. Uses the specified match only.\r
+ * 0b10..IO. Uses the specified I/O condition only.\r
+ * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously.\r
+ */\r
+#define SCT_EV_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK)\r
+#define SCT_EV_CTRL_STATELD_MASK (0x4000U)\r
+#define SCT_EV_CTRL_STATELD_SHIFT (14U)\r
+/*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this\r
+ * event is the highest-numbered event occurring for that state.\r
+ * 0b0..STATEV value is added into STATE (the carry-out is ignored).\r
+ * 0b1..STATEV value is loaded into STATE.\r
+ */\r
+#define SCT_EV_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK)\r
+#define SCT_EV_CTRL_STATEV_MASK (0xF8000U)\r
+#define SCT_EV_CTRL_STATEV_SHIFT (15U)\r
+/*! STATEV - This value is loaded into or added to the state selected by HEVENT, depending on\r
+ * STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and\r
+ * STATEV are both zero, there is no change to the STATE value.\r
+ */\r
+#define SCT_EV_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK)\r
+#define SCT_EV_CTRL_MATCHMEM_MASK (0x100000U)\r
+#define SCT_EV_CTRL_MATCHMEM_SHIFT (20U)\r
+/*! MATCHMEM - If this bit is one and the COMBMODE field specifies a match component to the\r
+ * triggering of this event, then a match is considered to be active whenever the counter value is\r
+ * GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR\r
+ * EQUAL TO the match value when counting down. If this bit is zero, a match is only be active\r
+ * during the cycle when the counter is equal to the match value.\r
+ */\r
+#define SCT_EV_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK)\r
+#define SCT_EV_CTRL_DIRECTION_MASK (0x600000U)\r
+#define SCT_EV_CTRL_DIRECTION_SHIFT (21U)\r
+/*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters\r
+ * are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.\r
+ * 0b00..Direction independent. This event is triggered regardless of the count direction.\r
+ * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1.\r
+ * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1.\r
+ */\r
+#define SCT_EV_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK)\r
+/*! @} */\r
+\r
+/* The count of SCT_EV_CTRL */\r
+#define SCT_EV_CTRL_COUNT (16U)\r
+\r
+/*! @name OUT_SET - SCT output 0 set register */\r
+/*! @{ */\r
+#define SCT_OUT_SET_SET_MASK (0xFFFFU)\r
+#define SCT_OUT_SET_SET_SHIFT (0U)\r
+/*! SET - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output\r
+ * 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the\r
+ * counter is used in bi-directional mode, it is possible to reverse the action specified by the\r
+ * output set and clear registers when counting down, See the OUTPUTCTRL register.\r
+ */\r
+#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK)\r
+/*! @} */\r
+\r
+/* The count of SCT_OUT_SET */\r
+#define SCT_OUT_SET_COUNT (10U)\r
+\r
+/*! @name OUT_CLR - SCT output 0 clear register */\r
+/*! @{ */\r
+#define SCT_OUT_CLR_CLR_MASK (0xFFFFU)\r
+#define SCT_OUT_CLR_CLR_SHIFT (0U)\r
+/*! CLR - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0\r
+ * = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the\r
+ * counter is used in bi-directional mode, it is possible to reverse the action specified by the\r
+ * output set and clear registers when counting down, See the OUTPUTCTRL register.\r
+ */\r
+#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK)\r
+/*! @} */\r
+\r
+/* The count of SCT_OUT_CLR */\r
+#define SCT_OUT_CLR_COUNT (10U)\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group SCT_Register_Masks */\r
+\r
+\r
+/* SCT - Peripheral instance base addresses */\r
+/** Peripheral SCT0 base address */\r
+#define SCT0_BASE (0x40085000u)\r
+/** Peripheral SCT0 base pointer */\r
+#define SCT0 ((SCT_Type *)SCT0_BASE)\r
+/** Array initializer of SCT peripheral base addresses */\r
+#define SCT_BASE_ADDRS { SCT0_BASE }\r
+/** Array initializer of SCT peripheral base pointers */\r
+#define SCT_BASE_PTRS { SCT0 }\r
+/** Interrupt vectors for the SCT peripheral type */\r
+#define SCT_IRQS { SCT0_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group SCT_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SDIF Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup SDIF_Peripheral_Access_Layer SDIF Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** SDIF - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t CTRL; /**< Control register, offset: 0x0 */\r
+ __IO uint32_t PWREN; /**< Power Enable register, offset: 0x4 */\r
+ __IO uint32_t CLKDIV; /**< Clock Divider register, offset: 0x8 */\r
+ uint8_t RESERVED_0[4];\r
+ __IO uint32_t CLKENA; /**< Clock Enable register, offset: 0x10 */\r
+ __IO uint32_t TMOUT; /**< Time-out register, offset: 0x14 */\r
+ __IO uint32_t CTYPE; /**< Card Type register, offset: 0x18 */\r
+ __IO uint32_t BLKSIZ; /**< Block Size register, offset: 0x1C */\r
+ __IO uint32_t BYTCNT; /**< Byte Count register, offset: 0x20 */\r
+ __IO uint32_t INTMASK; /**< Interrupt Mask register, offset: 0x24 */\r
+ __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x28 */\r
+ __IO uint32_t CMD; /**< Command register, offset: 0x2C */\r
+ __I uint32_t RESP[4]; /**< Response register, array offset: 0x30, array step: 0x4 */\r
+ __I uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x40 */\r
+ __IO uint32_t RINTSTS; /**< Raw Interrupt Status register, offset: 0x44 */\r
+ __I uint32_t STATUS; /**< Status register, offset: 0x48 */\r
+ __IO uint32_t FIFOTH; /**< FIFO Threshold Watermark register, offset: 0x4C */\r
+ __I uint32_t CDETECT; /**< Card Detect register, offset: 0x50 */\r
+ __I uint32_t WRTPRT; /**< Write Protect register, offset: 0x54 */\r
+ uint8_t RESERVED_1[4];\r
+ __I uint32_t TCBCNT; /**< Transferred CIU Card Byte Count register, offset: 0x5C */\r
+ __I uint32_t TBBCNT; /**< Transferred Host to BIU-FIFO Byte Count register, offset: 0x60 */\r
+ __IO uint32_t DEBNCE; /**< Debounce Count register, offset: 0x64 */\r
+ uint8_t RESERVED_2[16];\r
+ __IO uint32_t RST_N; /**< Hardware Reset, offset: 0x78 */\r
+ uint8_t RESERVED_3[4];\r
+ __IO uint32_t BMOD; /**< Bus Mode register, offset: 0x80 */\r
+ __O uint32_t PLDMND; /**< Poll Demand register, offset: 0x84 */\r
+ __IO uint32_t DBADDR; /**< Descriptor List Base Address register, offset: 0x88 */\r
+ __IO uint32_t IDSTS; /**< Internal DMAC Status register, offset: 0x8C */\r
+ __IO uint32_t IDINTEN; /**< Internal DMAC Interrupt Enable register, offset: 0x90 */\r
+ __I uint32_t DSCADDR; /**< Current Host Descriptor Address register, offset: 0x94 */\r
+ __I uint32_t BUFADDR; /**< Current Buffer Descriptor Address register, offset: 0x98 */\r
+ uint8_t RESERVED_4[100];\r
+ __IO uint32_t CARDTHRCTL; /**< Card Threshold Control, offset: 0x100 */\r
+ __IO uint32_t BACKENDPWR; /**< Power control, offset: 0x104 */\r
+ uint8_t RESERVED_5[248];\r
+ __IO uint32_t FIFO[64]; /**< SDIF FIFO, array offset: 0x200, array step: 0x4 */\r
+} SDIF_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SDIF Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup SDIF_Register_Masks SDIF Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CTRL - Control register */\r
+/*! @{ */\r
+#define SDIF_CTRL_CONTROLLER_RESET_MASK (0x1U)\r
+#define SDIF_CTRL_CONTROLLER_RESET_SHIFT (0U)\r
+/*! CONTROLLER_RESET - Controller reset.\r
+ */\r
+#define SDIF_CTRL_CONTROLLER_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK)\r
+#define SDIF_CTRL_FIFO_RESET_MASK (0x2U)\r
+#define SDIF_CTRL_FIFO_RESET_SHIFT (1U)\r
+/*! FIFO_RESET - Fifo reset.\r
+ */\r
+#define SDIF_CTRL_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK)\r
+#define SDIF_CTRL_DMA_RESET_MASK (0x4U)\r
+#define SDIF_CTRL_DMA_RESET_SHIFT (2U)\r
+/*! DMA_RESET - DMA reset.\r
+ */\r
+#define SDIF_CTRL_DMA_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)\r
+#define SDIF_CTRL_INT_ENABLE_MASK (0x10U)\r
+#define SDIF_CTRL_INT_ENABLE_SHIFT (4U)\r
+/*! INT_ENABLE - Global interrupt enable/disable bit.\r
+ */\r
+#define SDIF_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK)\r
+#define SDIF_CTRL_READ_WAIT_MASK (0x40U)\r
+#define SDIF_CTRL_READ_WAIT_SHIFT (6U)\r
+/*! READ_WAIT - Read/wait.\r
+ */\r
+#define SDIF_CTRL_READ_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK)\r
+#define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK (0x80U)\r
+#define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U)\r
+/*! SEND_IRQ_RESPONSE - Send irq response.\r
+ */\r
+#define SDIF_CTRL_SEND_IRQ_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK)\r
+#define SDIF_CTRL_ABORT_READ_DATA_MASK (0x100U)\r
+#define SDIF_CTRL_ABORT_READ_DATA_SHIFT (8U)\r
+/*! ABORT_READ_DATA - Abort read data.\r
+ */\r
+#define SDIF_CTRL_ABORT_READ_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK)\r
+#define SDIF_CTRL_SEND_CCSD_MASK (0x200U)\r
+#define SDIF_CTRL_SEND_CCSD_SHIFT (9U)\r
+/*! SEND_CCSD - Send ccsd.\r
+ */\r
+#define SDIF_CTRL_SEND_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK)\r
+#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x400U)\r
+#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U)\r
+/*! SEND_AUTO_STOP_CCSD - Send auto stop ccsd.\r
+ */\r
+#define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK)\r
+#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U)\r
+#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U)\r
+/*! CEATA_DEVICE_INTERRUPT_STATUS - CEATA device interrupt status.\r
+ */\r
+#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK)\r
+#define SDIF_CTRL_CARD_VOLTAGE_A0_MASK (0x10000U)\r
+#define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT (16U)\r
+/*! CARD_VOLTAGE_A0 - Controls the state of the SD_VOLT0 pin.\r
+ */\r
+#define SDIF_CTRL_CARD_VOLTAGE_A0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK)\r
+#define SDIF_CTRL_CARD_VOLTAGE_A1_MASK (0x20000U)\r
+#define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT (17U)\r
+/*! CARD_VOLTAGE_A1 - Controls the state of the SD_VOLT1 pin.\r
+ */\r
+#define SDIF_CTRL_CARD_VOLTAGE_A1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK)\r
+#define SDIF_CTRL_CARD_VOLTAGE_A2_MASK (0x40000U)\r
+#define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT (18U)\r
+/*! CARD_VOLTAGE_A2 - Controls the state of the SD_VOLT2 pin.\r
+ */\r
+#define SDIF_CTRL_CARD_VOLTAGE_A2(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK)\r
+#define SDIF_CTRL_USE_INTERNAL_DMAC_MASK (0x2000000U)\r
+#define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT (25U)\r
+/*! USE_INTERNAL_DMAC - SD/MMC DMA use.\r
+ */\r
+#define SDIF_CTRL_USE_INTERNAL_DMAC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK)\r
+/*! @} */\r
+\r
+/*! @name PWREN - Power Enable register */\r
+/*! @{ */\r
+#define SDIF_PWREN_POWER_ENABLE_MASK (0x1U)\r
+#define SDIF_PWREN_POWER_ENABLE_SHIFT (0U)\r
+/*! POWER_ENABLE - Power on/off switch for card; once power is turned on, software should wait for\r
+ * regulator/switch ramp-up time before trying to initialize card.\r
+ */\r
+#define SDIF_PWREN_POWER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE_SHIFT)) & SDIF_PWREN_POWER_ENABLE_MASK)\r
+/*! @} */\r
+\r
+/*! @name CLKDIV - Clock Divider register */\r
+/*! @{ */\r
+#define SDIF_CLKDIV_CLK_DIVIDER0_MASK (0xFFU)\r
+#define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT (0U)\r
+/*! CLK_DIVIDER0 - Clock divider-0 value.\r
+ */\r
+#define SDIF_CLKDIV_CLK_DIVIDER0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK)\r
+/*! @} */\r
+\r
+/*! @name CLKENA - Clock Enable register */\r
+/*! @{ */\r
+#define SDIF_CLKENA_CCLK_ENABLE_MASK (0x1U)\r
+#define SDIF_CLKENA_CCLK_ENABLE_SHIFT (0U)\r
+/*! CCLK_ENABLE - Clock-enable control for SD card clock.\r
+ */\r
+#define SDIF_CLKENA_CCLK_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK_ENABLE_MASK)\r
+#define SDIF_CLKENA_CCLK_LOW_POWER_MASK (0x10000U)\r
+#define SDIF_CLKENA_CCLK_LOW_POWER_SHIFT (16U)\r
+/*! CCLK_LOW_POWER - Low-power control for SD card clock.\r
+ */\r
+#define SDIF_CLKENA_CCLK_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK_LOW_POWER_MASK)\r
+/*! @} */\r
+\r
+/*! @name TMOUT - Time-out register */\r
+/*! @{ */\r
+#define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU)\r
+#define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U)\r
+/*! RESPONSE_TIMEOUT - Response time-out value.\r
+ */\r
+#define SDIF_TMOUT_RESPONSE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK)\r
+#define SDIF_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFF00U)\r
+#define SDIF_TMOUT_DATA_TIMEOUT_SHIFT (8U)\r
+/*! DATA_TIMEOUT - Value for card Data Read time-out; same value also used for Data Starvation by Host time-out.\r
+ */\r
+#define SDIF_TMOUT_DATA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK)\r
+/*! @} */\r
+\r
+/*! @name CTYPE - Card Type register */\r
+/*! @{ */\r
+#define SDIF_CTYPE_CARD_WIDTH0_MASK (0x1U)\r
+#define SDIF_CTYPE_CARD_WIDTH0_SHIFT (0U)\r
+/*! CARD_WIDTH0 - Indicates if card is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit\r
+ * modes only work when 8-bit mode in CARD_WIDTH1 is not enabled (bit 16 in this register is set to\r
+ * 0).\r
+ */\r
+#define SDIF_CTYPE_CARD_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD_WIDTH0_MASK)\r
+#define SDIF_CTYPE_CARD_WIDTH1_MASK (0x10000U)\r
+#define SDIF_CTYPE_CARD_WIDTH1_SHIFT (16U)\r
+/*! CARD_WIDTH1 - Indicates if card is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode.\r
+ */\r
+#define SDIF_CTYPE_CARD_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD_WIDTH1_MASK)\r
+/*! @} */\r
+\r
+/*! @name BLKSIZ - Block Size register */\r
+/*! @{ */\r
+#define SDIF_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU)\r
+#define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT (0U)\r
+/*! BLOCK_SIZE - Block size.\r
+ */\r
+#define SDIF_BLKSIZ_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK)\r
+/*! @} */\r
+\r
+/*! @name BYTCNT - Byte Count register */\r
+/*! @{ */\r
+#define SDIF_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU)\r
+#define SDIF_BYTCNT_BYTE_COUNT_SHIFT (0U)\r
+/*! BYTE_COUNT - Number of bytes to be transferred; should be integer multiple of Block Size for block transfers.\r
+ */\r
+#define SDIF_BYTCNT_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTMASK - Interrupt Mask register */\r
+/*! @{ */\r
+#define SDIF_INTMASK_CDET_MASK (0x1U)\r
+#define SDIF_INTMASK_CDET_SHIFT (0U)\r
+/*! CDET - Card detect.\r
+ */\r
+#define SDIF_INTMASK_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK)\r
+#define SDIF_INTMASK_RE_MASK (0x2U)\r
+#define SDIF_INTMASK_RE_SHIFT (1U)\r
+/*! RE - Response error.\r
+ */\r
+#define SDIF_INTMASK_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK)\r
+#define SDIF_INTMASK_CDONE_MASK (0x4U)\r
+#define SDIF_INTMASK_CDONE_SHIFT (2U)\r
+/*! CDONE - Command done.\r
+ */\r
+#define SDIF_INTMASK_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK)\r
+#define SDIF_INTMASK_DTO_MASK (0x8U)\r
+#define SDIF_INTMASK_DTO_SHIFT (3U)\r
+/*! DTO - Data transfer over.\r
+ */\r
+#define SDIF_INTMASK_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK)\r
+#define SDIF_INTMASK_TXDR_MASK (0x10U)\r
+#define SDIF_INTMASK_TXDR_SHIFT (4U)\r
+/*! TXDR - Transmit FIFO data request.\r
+ */\r
+#define SDIF_INTMASK_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK)\r
+#define SDIF_INTMASK_RXDR_MASK (0x20U)\r
+#define SDIF_INTMASK_RXDR_SHIFT (5U)\r
+/*! RXDR - Receive FIFO data request.\r
+ */\r
+#define SDIF_INTMASK_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK)\r
+#define SDIF_INTMASK_RCRC_MASK (0x40U)\r
+#define SDIF_INTMASK_RCRC_SHIFT (6U)\r
+/*! RCRC - Response CRC error.\r
+ */\r
+#define SDIF_INTMASK_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK)\r
+#define SDIF_INTMASK_DCRC_MASK (0x80U)\r
+#define SDIF_INTMASK_DCRC_SHIFT (7U)\r
+/*! DCRC - Data CRC error.\r
+ */\r
+#define SDIF_INTMASK_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK)\r
+#define SDIF_INTMASK_RTO_MASK (0x100U)\r
+#define SDIF_INTMASK_RTO_SHIFT (8U)\r
+/*! RTO - Response time-out.\r
+ */\r
+#define SDIF_INTMASK_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK)\r
+#define SDIF_INTMASK_DRTO_MASK (0x200U)\r
+#define SDIF_INTMASK_DRTO_SHIFT (9U)\r
+/*! DRTO - Data read time-out.\r
+ */\r
+#define SDIF_INTMASK_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK)\r
+#define SDIF_INTMASK_HTO_MASK (0x400U)\r
+#define SDIF_INTMASK_HTO_SHIFT (10U)\r
+/*! HTO - Data starvation-by-host time-out (HTO).\r
+ */\r
+#define SDIF_INTMASK_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK)\r
+#define SDIF_INTMASK_FRUN_MASK (0x800U)\r
+#define SDIF_INTMASK_FRUN_SHIFT (11U)\r
+/*! FRUN - FIFO underrun/overrun error.\r
+ */\r
+#define SDIF_INTMASK_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK)\r
+#define SDIF_INTMASK_HLE_MASK (0x1000U)\r
+#define SDIF_INTMASK_HLE_SHIFT (12U)\r
+/*! HLE - Hardware locked write error.\r
+ */\r
+#define SDIF_INTMASK_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK)\r
+#define SDIF_INTMASK_SBE_MASK (0x2000U)\r
+#define SDIF_INTMASK_SBE_SHIFT (13U)\r
+/*! SBE - Start-bit error.\r
+ */\r
+#define SDIF_INTMASK_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK)\r
+#define SDIF_INTMASK_ACD_MASK (0x4000U)\r
+#define SDIF_INTMASK_ACD_SHIFT (14U)\r
+/*! ACD - Auto command done.\r
+ */\r
+#define SDIF_INTMASK_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK)\r
+#define SDIF_INTMASK_EBE_MASK (0x8000U)\r
+#define SDIF_INTMASK_EBE_SHIFT (15U)\r
+/*! EBE - End-bit error (read)/Write no CRC.\r
+ */\r
+#define SDIF_INTMASK_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK)\r
+#define SDIF_INTMASK_SDIO_INT_MASK_MASK (0x10000U)\r
+#define SDIF_INTMASK_SDIO_INT_MASK_SHIFT (16U)\r
+/*! SDIO_INT_MASK - Mask SDIO interrupt.\r
+ */\r
+#define SDIF_INTMASK_SDIO_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK)\r
+/*! @} */\r
+\r
+/*! @name CMDARG - Command Argument register */\r
+/*! @{ */\r
+#define SDIF_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU)\r
+#define SDIF_CMDARG_CMD_ARG_SHIFT (0U)\r
+/*! CMD_ARG - Value indicates command argument to be passed to card.\r
+ */\r
+#define SDIF_CMDARG_CMD_ARG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK)\r
+/*! @} */\r
+\r
+/*! @name CMD - Command register */\r
+/*! @{ */\r
+#define SDIF_CMD_CMD_INDEX_MASK (0x3FU)\r
+#define SDIF_CMD_CMD_INDEX_SHIFT (0U)\r
+/*! CMD_INDEX - Command index.\r
+ */\r
+#define SDIF_CMD_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK)\r
+#define SDIF_CMD_RESPONSE_EXPECT_MASK (0x40U)\r
+#define SDIF_CMD_RESPONSE_EXPECT_SHIFT (6U)\r
+/*! RESPONSE_EXPECT - Response expect.\r
+ */\r
+#define SDIF_CMD_RESPONSE_EXPECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK)\r
+#define SDIF_CMD_RESPONSE_LENGTH_MASK (0x80U)\r
+#define SDIF_CMD_RESPONSE_LENGTH_SHIFT (7U)\r
+/*! RESPONSE_LENGTH - Response length.\r
+ */\r
+#define SDIF_CMD_RESPONSE_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK)\r
+#define SDIF_CMD_CHECK_RESPONSE_CRC_MASK (0x100U)\r
+#define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT (8U)\r
+/*! CHECK_RESPONSE_CRC - Check response CRC.\r
+ */\r
+#define SDIF_CMD_CHECK_RESPONSE_CRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK)\r
+#define SDIF_CMD_DATA_EXPECTED_MASK (0x200U)\r
+#define SDIF_CMD_DATA_EXPECTED_SHIFT (9U)\r
+/*! DATA_EXPECTED - Data expected.\r
+ */\r
+#define SDIF_CMD_DATA_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK)\r
+#define SDIF_CMD_READ_WRITE_MASK (0x400U)\r
+#define SDIF_CMD_READ_WRITE_SHIFT (10U)\r
+/*! READ_WRITE - read/write.\r
+ */\r
+#define SDIF_CMD_READ_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK)\r
+#define SDIF_CMD_TRANSFER_MODE_MASK (0x800U)\r
+#define SDIF_CMD_TRANSFER_MODE_SHIFT (11U)\r
+/*! TRANSFER_MODE - Transfer mode.\r
+ */\r
+#define SDIF_CMD_TRANSFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK)\r
+#define SDIF_CMD_SEND_AUTO_STOP_MASK (0x1000U)\r
+#define SDIF_CMD_SEND_AUTO_STOP_SHIFT (12U)\r
+/*! SEND_AUTO_STOP - Send auto stop.\r
+ */\r
+#define SDIF_CMD_SEND_AUTO_STOP(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK)\r
+#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x2000U)\r
+#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U)\r
+/*! WAIT_PRVDATA_COMPLETE - Wait prvdata complete.\r
+ */\r
+#define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK)\r
+#define SDIF_CMD_STOP_ABORT_CMD_MASK (0x4000U)\r
+#define SDIF_CMD_STOP_ABORT_CMD_SHIFT (14U)\r
+/*! STOP_ABORT_CMD - Stop abort command.\r
+ */\r
+#define SDIF_CMD_STOP_ABORT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK)\r
+#define SDIF_CMD_SEND_INITIALIZATION_MASK (0x8000U)\r
+#define SDIF_CMD_SEND_INITIALIZATION_SHIFT (15U)\r
+/*! SEND_INITIALIZATION - Send initialization.\r
+ */\r
+#define SDIF_CMD_SEND_INITIALIZATION(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK)\r
+#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U)\r
+#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U)\r
+/*! UPDATE_CLOCK_REGISTERS_ONLY - Update clock registers only.\r
+ */\r
+#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK)\r
+#define SDIF_CMD_READ_CEATA_DEVICE_MASK (0x400000U)\r
+#define SDIF_CMD_READ_CEATA_DEVICE_SHIFT (22U)\r
+/*! READ_CEATA_DEVICE - Read ceata device.\r
+ */\r
+#define SDIF_CMD_READ_CEATA_DEVICE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK)\r
+#define SDIF_CMD_CCS_EXPECTED_MASK (0x800000U)\r
+#define SDIF_CMD_CCS_EXPECTED_SHIFT (23U)\r
+/*! CCS_EXPECTED - CCS expected.\r
+ */\r
+#define SDIF_CMD_CCS_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK)\r
+#define SDIF_CMD_ENABLE_BOOT_MASK (0x1000000U)\r
+#define SDIF_CMD_ENABLE_BOOT_SHIFT (24U)\r
+/*! ENABLE_BOOT - Enable Boot - this bit should be set only for mandatory boot mode.\r
+ */\r
+#define SDIF_CMD_ENABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK)\r
+#define SDIF_CMD_EXPECT_BOOT_ACK_MASK (0x2000000U)\r
+#define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT (25U)\r
+/*! EXPECT_BOOT_ACK - Expect Boot Acknowledge.\r
+ */\r
+#define SDIF_CMD_EXPECT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK)\r
+#define SDIF_CMD_DISABLE_BOOT_MASK (0x4000000U)\r
+#define SDIF_CMD_DISABLE_BOOT_SHIFT (26U)\r
+/*! DISABLE_BOOT - Disable Boot.\r
+ */\r
+#define SDIF_CMD_DISABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK)\r
+#define SDIF_CMD_BOOT_MODE_MASK (0x8000000U)\r
+#define SDIF_CMD_BOOT_MODE_SHIFT (27U)\r
+/*! BOOT_MODE - Boot Mode.\r
+ */\r
+#define SDIF_CMD_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK)\r
+#define SDIF_CMD_VOLT_SWITCH_MASK (0x10000000U)\r
+#define SDIF_CMD_VOLT_SWITCH_SHIFT (28U)\r
+/*! VOLT_SWITCH - Voltage switch bit.\r
+ */\r
+#define SDIF_CMD_VOLT_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK)\r
+#define SDIF_CMD_USE_HOLD_REG_MASK (0x20000000U)\r
+#define SDIF_CMD_USE_HOLD_REG_SHIFT (29U)\r
+/*! USE_HOLD_REG - Use Hold Register.\r
+ */\r
+#define SDIF_CMD_USE_HOLD_REG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK)\r
+#define SDIF_CMD_START_CMD_MASK (0x80000000U)\r
+#define SDIF_CMD_START_CMD_SHIFT (31U)\r
+/*! START_CMD - Start command.\r
+ */\r
+#define SDIF_CMD_START_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK)\r
+/*! @} */\r
+\r
+/*! @name RESP - Response register */\r
+/*! @{ */\r
+#define SDIF_RESP_RESPONSE_MASK (0xFFFFFFFFU)\r
+#define SDIF_RESP_RESPONSE_SHIFT (0U)\r
+/*! RESPONSE - Bits of response.\r
+ */\r
+#define SDIF_RESP_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK)\r
+/*! @} */\r
+\r
+/* The count of SDIF_RESP */\r
+#define SDIF_RESP_COUNT (4U)\r
+\r
+/*! @name MINTSTS - Masked Interrupt Status register */\r
+/*! @{ */\r
+#define SDIF_MINTSTS_CDET_MASK (0x1U)\r
+#define SDIF_MINTSTS_CDET_SHIFT (0U)\r
+/*! CDET - Card detect.\r
+ */\r
+#define SDIF_MINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK)\r
+#define SDIF_MINTSTS_RE_MASK (0x2U)\r
+#define SDIF_MINTSTS_RE_SHIFT (1U)\r
+/*! RE - Response error.\r
+ */\r
+#define SDIF_MINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK)\r
+#define SDIF_MINTSTS_CDONE_MASK (0x4U)\r
+#define SDIF_MINTSTS_CDONE_SHIFT (2U)\r
+/*! CDONE - Command done.\r
+ */\r
+#define SDIF_MINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK)\r
+#define SDIF_MINTSTS_DTO_MASK (0x8U)\r
+#define SDIF_MINTSTS_DTO_SHIFT (3U)\r
+/*! DTO - Data transfer over.\r
+ */\r
+#define SDIF_MINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK)\r
+#define SDIF_MINTSTS_TXDR_MASK (0x10U)\r
+#define SDIF_MINTSTS_TXDR_SHIFT (4U)\r
+/*! TXDR - Transmit FIFO data request.\r
+ */\r
+#define SDIF_MINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK)\r
+#define SDIF_MINTSTS_RXDR_MASK (0x20U)\r
+#define SDIF_MINTSTS_RXDR_SHIFT (5U)\r
+/*! RXDR - Receive FIFO data request.\r
+ */\r
+#define SDIF_MINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK)\r
+#define SDIF_MINTSTS_RCRC_MASK (0x40U)\r
+#define SDIF_MINTSTS_RCRC_SHIFT (6U)\r
+/*! RCRC - Response CRC error.\r
+ */\r
+#define SDIF_MINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK)\r
+#define SDIF_MINTSTS_DCRC_MASK (0x80U)\r
+#define SDIF_MINTSTS_DCRC_SHIFT (7U)\r
+/*! DCRC - Data CRC error.\r
+ */\r
+#define SDIF_MINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK)\r
+#define SDIF_MINTSTS_RTO_MASK (0x100U)\r
+#define SDIF_MINTSTS_RTO_SHIFT (8U)\r
+/*! RTO - Response time-out.\r
+ */\r
+#define SDIF_MINTSTS_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK)\r
+#define SDIF_MINTSTS_DRTO_MASK (0x200U)\r
+#define SDIF_MINTSTS_DRTO_SHIFT (9U)\r
+/*! DRTO - Data read time-out.\r
+ */\r
+#define SDIF_MINTSTS_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK)\r
+#define SDIF_MINTSTS_HTO_MASK (0x400U)\r
+#define SDIF_MINTSTS_HTO_SHIFT (10U)\r
+/*! HTO - Data starvation-by-host time-out (HTO).\r
+ */\r
+#define SDIF_MINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK)\r
+#define SDIF_MINTSTS_FRUN_MASK (0x800U)\r
+#define SDIF_MINTSTS_FRUN_SHIFT (11U)\r
+/*! FRUN - FIFO underrun/overrun error.\r
+ */\r
+#define SDIF_MINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK)\r
+#define SDIF_MINTSTS_HLE_MASK (0x1000U)\r
+#define SDIF_MINTSTS_HLE_SHIFT (12U)\r
+/*! HLE - Hardware locked write error.\r
+ */\r
+#define SDIF_MINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK)\r
+#define SDIF_MINTSTS_SBE_MASK (0x2000U)\r
+#define SDIF_MINTSTS_SBE_SHIFT (13U)\r
+/*! SBE - Start-bit error.\r
+ */\r
+#define SDIF_MINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK)\r
+#define SDIF_MINTSTS_ACD_MASK (0x4000U)\r
+#define SDIF_MINTSTS_ACD_SHIFT (14U)\r
+/*! ACD - Auto command done.\r
+ */\r
+#define SDIF_MINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK)\r
+#define SDIF_MINTSTS_EBE_MASK (0x8000U)\r
+#define SDIF_MINTSTS_EBE_SHIFT (15U)\r
+/*! EBE - End-bit error (read)/write no CRC.\r
+ */\r
+#define SDIF_MINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK)\r
+#define SDIF_MINTSTS_SDIO_INTERRUPT_MASK (0x10000U)\r
+#define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT (16U)\r
+/*! SDIO_INTERRUPT - Interrupt from SDIO card.\r
+ */\r
+#define SDIF_MINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK)\r
+/*! @} */\r
+\r
+/*! @name RINTSTS - Raw Interrupt Status register */\r
+/*! @{ */\r
+#define SDIF_RINTSTS_CDET_MASK (0x1U)\r
+#define SDIF_RINTSTS_CDET_SHIFT (0U)\r
+/*! CDET - Card detect.\r
+ */\r
+#define SDIF_RINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK)\r
+#define SDIF_RINTSTS_RE_MASK (0x2U)\r
+#define SDIF_RINTSTS_RE_SHIFT (1U)\r
+/*! RE - Response error.\r
+ */\r
+#define SDIF_RINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK)\r
+#define SDIF_RINTSTS_CDONE_MASK (0x4U)\r
+#define SDIF_RINTSTS_CDONE_SHIFT (2U)\r
+/*! CDONE - Command done.\r
+ */\r
+#define SDIF_RINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK)\r
+#define SDIF_RINTSTS_DTO_MASK (0x8U)\r
+#define SDIF_RINTSTS_DTO_SHIFT (3U)\r
+/*! DTO - Data transfer over.\r
+ */\r
+#define SDIF_RINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK)\r
+#define SDIF_RINTSTS_TXDR_MASK (0x10U)\r
+#define SDIF_RINTSTS_TXDR_SHIFT (4U)\r
+/*! TXDR - Transmit FIFO data request.\r
+ */\r
+#define SDIF_RINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK)\r
+#define SDIF_RINTSTS_RXDR_MASK (0x20U)\r
+#define SDIF_RINTSTS_RXDR_SHIFT (5U)\r
+/*! RXDR - Receive FIFO data request.\r
+ */\r
+#define SDIF_RINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK)\r
+#define SDIF_RINTSTS_RCRC_MASK (0x40U)\r
+#define SDIF_RINTSTS_RCRC_SHIFT (6U)\r
+/*! RCRC - Response CRC error.\r
+ */\r
+#define SDIF_RINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK)\r
+#define SDIF_RINTSTS_DCRC_MASK (0x80U)\r
+#define SDIF_RINTSTS_DCRC_SHIFT (7U)\r
+/*! DCRC - Data CRC error.\r
+ */\r
+#define SDIF_RINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK)\r
+#define SDIF_RINTSTS_RTO_BAR_MASK (0x100U)\r
+#define SDIF_RINTSTS_RTO_BAR_SHIFT (8U)\r
+/*! RTO_BAR - Response time-out (RTO)/Boot Ack Received (BAR).\r
+ */\r
+#define SDIF_RINTSTS_RTO_BAR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK)\r
+#define SDIF_RINTSTS_DRTO_BDS_MASK (0x200U)\r
+#define SDIF_RINTSTS_DRTO_BDS_SHIFT (9U)\r
+/*! DRTO_BDS - Data read time-out (DRTO)/Boot Data Start (BDS).\r
+ */\r
+#define SDIF_RINTSTS_DRTO_BDS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK)\r
+#define SDIF_RINTSTS_HTO_MASK (0x400U)\r
+#define SDIF_RINTSTS_HTO_SHIFT (10U)\r
+/*! HTO - Data starvation-by-host time-out (HTO).\r
+ */\r
+#define SDIF_RINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK)\r
+#define SDIF_RINTSTS_FRUN_MASK (0x800U)\r
+#define SDIF_RINTSTS_FRUN_SHIFT (11U)\r
+/*! FRUN - FIFO underrun/overrun error.\r
+ */\r
+#define SDIF_RINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK)\r
+#define SDIF_RINTSTS_HLE_MASK (0x1000U)\r
+#define SDIF_RINTSTS_HLE_SHIFT (12U)\r
+/*! HLE - Hardware locked write error.\r
+ */\r
+#define SDIF_RINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK)\r
+#define SDIF_RINTSTS_SBE_MASK (0x2000U)\r
+#define SDIF_RINTSTS_SBE_SHIFT (13U)\r
+/*! SBE - Start-bit error.\r
+ */\r
+#define SDIF_RINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK)\r
+#define SDIF_RINTSTS_ACD_MASK (0x4000U)\r
+#define SDIF_RINTSTS_ACD_SHIFT (14U)\r
+/*! ACD - Auto command done.\r
+ */\r
+#define SDIF_RINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK)\r
+#define SDIF_RINTSTS_EBE_MASK (0x8000U)\r
+#define SDIF_RINTSTS_EBE_SHIFT (15U)\r
+/*! EBE - End-bit error (read)/write no CRC.\r
+ */\r
+#define SDIF_RINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK)\r
+#define SDIF_RINTSTS_SDIO_INTERRUPT_MASK (0x10000U)\r
+#define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT (16U)\r
+/*! SDIO_INTERRUPT - Interrupt from SDIO card.\r
+ */\r
+#define SDIF_RINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK)\r
+/*! @} */\r
+\r
+/*! @name STATUS - Status register */\r
+/*! @{ */\r
+#define SDIF_STATUS_FIFO_RX_WATERMARK_MASK (0x1U)\r
+#define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT (0U)\r
+/*! FIFO_RX_WATERMARK - FIFO reached Receive watermark level; not qualified with data transfer.\r
+ */\r
+#define SDIF_STATUS_FIFO_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK)\r
+#define SDIF_STATUS_FIFO_TX_WATERMARK_MASK (0x2U)\r
+#define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT (1U)\r
+/*! FIFO_TX_WATERMARK - FIFO reached Transmit watermark level; not qualified with data transfer.\r
+ */\r
+#define SDIF_STATUS_FIFO_TX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK)\r
+#define SDIF_STATUS_FIFO_EMPTY_MASK (0x4U)\r
+#define SDIF_STATUS_FIFO_EMPTY_SHIFT (2U)\r
+/*! FIFO_EMPTY - FIFO is empty status.\r
+ */\r
+#define SDIF_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK)\r
+#define SDIF_STATUS_FIFO_FULL_MASK (0x8U)\r
+#define SDIF_STATUS_FIFO_FULL_SHIFT (3U)\r
+/*! FIFO_FULL - FIFO is full status.\r
+ */\r
+#define SDIF_STATUS_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK)\r
+#define SDIF_STATUS_CMDFSMSTATES_MASK (0xF0U)\r
+#define SDIF_STATUS_CMDFSMSTATES_SHIFT (4U)\r
+/*! CMDFSMSTATES - Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx\r
+ * cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 -\r
+ * Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp\r
+ * crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The\r
+ * command FSM state is represented using 19 bits.\r
+ */\r
+#define SDIF_STATUS_CMDFSMSTATES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK)\r
+#define SDIF_STATUS_DATA_3_STATUS_MASK (0x100U)\r
+#define SDIF_STATUS_DATA_3_STATUS_SHIFT (8U)\r
+/*! DATA_3_STATUS - Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present.\r
+ */\r
+#define SDIF_STATUS_DATA_3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK)\r
+#define SDIF_STATUS_DATA_BUSY_MASK (0x200U)\r
+#define SDIF_STATUS_DATA_BUSY_SHIFT (9U)\r
+/*! DATA_BUSY - Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy.\r
+ */\r
+#define SDIF_STATUS_DATA_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK)\r
+#define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK (0x400U)\r
+#define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U)\r
+/*! DATA_STATE_MC_BUSY - Data transmit or receive state-machine is busy.\r
+ */\r
+#define SDIF_STATUS_DATA_STATE_MC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK)\r
+#define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U)\r
+#define SDIF_STATUS_RESPONSE_INDEX_SHIFT (11U)\r
+/*! RESPONSE_INDEX - Index of previous response, including any auto-stop sent by core.\r
+ */\r
+#define SDIF_STATUS_RESPONSE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)\r
+#define SDIF_STATUS_FIFO_COUNT_MASK (0x3FFE0000U)\r
+#define SDIF_STATUS_FIFO_COUNT_SHIFT (17U)\r
+/*! FIFO_COUNT - FIFO count - Number of filled locations in FIFO.\r
+ */\r
+#define SDIF_STATUS_FIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK)\r
+#define SDIF_STATUS_DMA_ACK_MASK (0x40000000U)\r
+#define SDIF_STATUS_DMA_ACK_SHIFT (30U)\r
+/*! DMA_ACK - DMA acknowledge signal state.\r
+ */\r
+#define SDIF_STATUS_DMA_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK)\r
+#define SDIF_STATUS_DMA_REQ_MASK (0x80000000U)\r
+#define SDIF_STATUS_DMA_REQ_SHIFT (31U)\r
+/*! DMA_REQ - DMA request signal state.\r
+ */\r
+#define SDIF_STATUS_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOTH - FIFO Threshold Watermark register */\r
+/*! @{ */\r
+#define SDIF_FIFOTH_TX_WMARK_MASK (0xFFFU)\r
+#define SDIF_FIFOTH_TX_WMARK_SHIFT (0U)\r
+/*! TX_WMARK - FIFO threshold watermark level when transmitting data to card.\r
+ */\r
+#define SDIF_FIFOTH_TX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK)\r
+#define SDIF_FIFOTH_RX_WMARK_MASK (0xFFF0000U)\r
+#define SDIF_FIFOTH_RX_WMARK_SHIFT (16U)\r
+/*! RX_WMARK - FIFO threshold watermark level when receiving data to card.\r
+ */\r
+#define SDIF_FIFOTH_RX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK)\r
+#define SDIF_FIFOTH_DMA_MTS_MASK (0x70000000U)\r
+#define SDIF_FIFOTH_DMA_MTS_SHIFT (28U)\r
+/*! DMA_MTS - Burst size of multiple transaction; should be programmed same as DW-DMA controller\r
+ * multiple-transaction-size SRC/DEST_MSIZE.\r
+ */\r
+#define SDIF_FIFOTH_DMA_MTS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK)\r
+/*! @} */\r
+\r
+/*! @name CDETECT - Card Detect register */\r
+/*! @{ */\r
+#define SDIF_CDETECT_CARD_DETECT_MASK (0x1U)\r
+#define SDIF_CDETECT_CARD_DETECT_SHIFT (0U)\r
+/*! CARD_DETECT - Card detect.\r
+ */\r
+#define SDIF_CDETECT_CARD_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD_DETECT_SHIFT)) & SDIF_CDETECT_CARD_DETECT_MASK)\r
+/*! @} */\r
+\r
+/*! @name WRTPRT - Write Protect register */\r
+/*! @{ */\r
+#define SDIF_WRTPRT_WRITE_PROTECT_MASK (0x1U)\r
+#define SDIF_WRTPRT_WRITE_PROTECT_SHIFT (0U)\r
+/*! WRITE_PROTECT - Write protect.\r
+ */\r
+#define SDIF_WRTPRT_WRITE_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK)\r
+/*! @} */\r
+\r
+/*! @name TCBCNT - Transferred CIU Card Byte Count register */\r
+/*! @{ */\r
+#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU)\r
+#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U)\r
+/*! TRANS_CARD_BYTE_COUNT - Number of bytes transferred by CIU unit to card.\r
+ */\r
+#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK)\r
+/*! @} */\r
+\r
+/*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */\r
+/*! @{ */\r
+#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU)\r
+#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U)\r
+/*! TRANS_FIFO_BYTE_COUNT - Number of bytes transferred between Host/DMA memory and BIU FIFO.\r
+ */\r
+#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK)\r
+/*! @} */\r
+\r
+/*! @name DEBNCE - Debounce Count register */\r
+/*! @{ */\r
+#define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU)\r
+#define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U)\r
+/*! DEBOUNCE_COUNT - Number of host clocks (SD_CLK) used by debounce filter logic for card detect; typical debounce time is 5-25 ms.\r
+ */\r
+#define SDIF_DEBNCE_DEBOUNCE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK)\r
+/*! @} */\r
+\r
+/*! @name RST_N - Hardware Reset */\r
+/*! @{ */\r
+#define SDIF_RST_N_CARD_RESET_MASK (0x1U)\r
+#define SDIF_RST_N_CARD_RESET_SHIFT (0U)\r
+/*! CARD_RESET - Hardware reset.\r
+ */\r
+#define SDIF_RST_N_CARD_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK)\r
+/*! @} */\r
+\r
+/*! @name BMOD - Bus Mode register */\r
+/*! @{ */\r
+#define SDIF_BMOD_SWR_MASK (0x1U)\r
+#define SDIF_BMOD_SWR_SHIFT (0U)\r
+/*! SWR - Software Reset.\r
+ */\r
+#define SDIF_BMOD_SWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK)\r
+#define SDIF_BMOD_FB_MASK (0x2U)\r
+#define SDIF_BMOD_FB_SHIFT (1U)\r
+/*! FB - Fixed Burst.\r
+ */\r
+#define SDIF_BMOD_FB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK)\r
+#define SDIF_BMOD_DSL_MASK (0x7CU)\r
+#define SDIF_BMOD_DSL_SHIFT (2U)\r
+/*! DSL - Descriptor Skip Length.\r
+ */\r
+#define SDIF_BMOD_DSL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK)\r
+#define SDIF_BMOD_DE_MASK (0x80U)\r
+#define SDIF_BMOD_DE_SHIFT (7U)\r
+/*! DE - SD/MMC DMA Enable.\r
+ */\r
+#define SDIF_BMOD_DE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK)\r
+#define SDIF_BMOD_PBL_MASK (0x700U)\r
+#define SDIF_BMOD_PBL_SHIFT (8U)\r
+/*! PBL - Programmable Burst Length.\r
+ */\r
+#define SDIF_BMOD_PBL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK)\r
+/*! @} */\r
+\r
+/*! @name PLDMND - Poll Demand register */\r
+/*! @{ */\r
+#define SDIF_PLDMND_PD_MASK (0xFFFFFFFFU)\r
+#define SDIF_PLDMND_PD_SHIFT (0U)\r
+/*! PD - Poll Demand.\r
+ */\r
+#define SDIF_PLDMND_PD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK)\r
+/*! @} */\r
+\r
+/*! @name DBADDR - Descriptor List Base Address register */\r
+/*! @{ */\r
+#define SDIF_DBADDR_SDL_MASK (0xFFFFFFFFU)\r
+#define SDIF_DBADDR_SDL_SHIFT (0U)\r
+/*! SDL - Start of Descriptor List.\r
+ */\r
+#define SDIF_DBADDR_SDL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK)\r
+/*! @} */\r
+\r
+/*! @name IDSTS - Internal DMAC Status register */\r
+/*! @{ */\r
+#define SDIF_IDSTS_TI_MASK (0x1U)\r
+#define SDIF_IDSTS_TI_SHIFT (0U)\r
+/*! TI - Transmit Interrupt.\r
+ */\r
+#define SDIF_IDSTS_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK)\r
+#define SDIF_IDSTS_RI_MASK (0x2U)\r
+#define SDIF_IDSTS_RI_SHIFT (1U)\r
+/*! RI - Receive Interrupt.\r
+ */\r
+#define SDIF_IDSTS_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK)\r
+#define SDIF_IDSTS_FBE_MASK (0x4U)\r
+#define SDIF_IDSTS_FBE_SHIFT (2U)\r
+/*! FBE - Fatal Bus Error Interrupt.\r
+ */\r
+#define SDIF_IDSTS_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK)\r
+#define SDIF_IDSTS_DU_MASK (0x10U)\r
+#define SDIF_IDSTS_DU_SHIFT (4U)\r
+/*! DU - Descriptor Unavailable Interrupt.\r
+ */\r
+#define SDIF_IDSTS_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK)\r
+#define SDIF_IDSTS_CES_MASK (0x20U)\r
+#define SDIF_IDSTS_CES_SHIFT (5U)\r
+/*! CES - Card Error Summary.\r
+ */\r
+#define SDIF_IDSTS_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK)\r
+#define SDIF_IDSTS_NIS_MASK (0x100U)\r
+#define SDIF_IDSTS_NIS_SHIFT (8U)\r
+/*! NIS - Normal Interrupt Summary.\r
+ */\r
+#define SDIF_IDSTS_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK)\r
+#define SDIF_IDSTS_AIS_MASK (0x200U)\r
+#define SDIF_IDSTS_AIS_SHIFT (9U)\r
+/*! AIS - Abnormal Interrupt Summary.\r
+ */\r
+#define SDIF_IDSTS_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK)\r
+#define SDIF_IDSTS_EB_MASK (0x1C00U)\r
+#define SDIF_IDSTS_EB_SHIFT (10U)\r
+/*! EB - Error Bits.\r
+ */\r
+#define SDIF_IDSTS_EB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK)\r
+#define SDIF_IDSTS_FSM_MASK (0x1E000U)\r
+#define SDIF_IDSTS_FSM_SHIFT (13U)\r
+/*! FSM - DMAC state machine present state.\r
+ */\r
+#define SDIF_IDSTS_FSM(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK)\r
+/*! @} */\r
+\r
+/*! @name IDINTEN - Internal DMAC Interrupt Enable register */\r
+/*! @{ */\r
+#define SDIF_IDINTEN_TI_MASK (0x1U)\r
+#define SDIF_IDINTEN_TI_SHIFT (0U)\r
+/*! TI - Transmit Interrupt Enable.\r
+ */\r
+#define SDIF_IDINTEN_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK)\r
+#define SDIF_IDINTEN_RI_MASK (0x2U)\r
+#define SDIF_IDINTEN_RI_SHIFT (1U)\r
+/*! RI - Receive Interrupt Enable.\r
+ */\r
+#define SDIF_IDINTEN_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK)\r
+#define SDIF_IDINTEN_FBE_MASK (0x4U)\r
+#define SDIF_IDINTEN_FBE_SHIFT (2U)\r
+/*! FBE - Fatal Bus Error Enable.\r
+ */\r
+#define SDIF_IDINTEN_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK)\r
+#define SDIF_IDINTEN_DU_MASK (0x10U)\r
+#define SDIF_IDINTEN_DU_SHIFT (4U)\r
+/*! DU - Descriptor Unavailable Interrupt.\r
+ */\r
+#define SDIF_IDINTEN_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK)\r
+#define SDIF_IDINTEN_CES_MASK (0x20U)\r
+#define SDIF_IDINTEN_CES_SHIFT (5U)\r
+/*! CES - Card Error summary Interrupt Enable.\r
+ */\r
+#define SDIF_IDINTEN_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK)\r
+#define SDIF_IDINTEN_NIS_MASK (0x100U)\r
+#define SDIF_IDINTEN_NIS_SHIFT (8U)\r
+/*! NIS - Normal Interrupt Summary Enable.\r
+ */\r
+#define SDIF_IDINTEN_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK)\r
+#define SDIF_IDINTEN_AIS_MASK (0x200U)\r
+#define SDIF_IDINTEN_AIS_SHIFT (9U)\r
+/*! AIS - Abnormal Interrupt Summary Enable.\r
+ */\r
+#define SDIF_IDINTEN_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK)\r
+/*! @} */\r
+\r
+/*! @name DSCADDR - Current Host Descriptor Address register */\r
+/*! @{ */\r
+#define SDIF_DSCADDR_HDA_MASK (0xFFFFFFFFU)\r
+#define SDIF_DSCADDR_HDA_SHIFT (0U)\r
+/*! HDA - Host Descriptor Address Pointer.\r
+ */\r
+#define SDIF_DSCADDR_HDA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK)\r
+/*! @} */\r
+\r
+/*! @name BUFADDR - Current Buffer Descriptor Address register */\r
+/*! @{ */\r
+#define SDIF_BUFADDR_HBA_MASK (0xFFFFFFFFU)\r
+#define SDIF_BUFADDR_HBA_SHIFT (0U)\r
+/*! HBA - Host Buffer Address Pointer.\r
+ */\r
+#define SDIF_BUFADDR_HBA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK)\r
+/*! @} */\r
+\r
+/*! @name CARDTHRCTL - Card Threshold Control */\r
+/*! @{ */\r
+#define SDIF_CARDTHRCTL_CARDRDTHREN_MASK (0x1U)\r
+#define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT (0U)\r
+/*! CARDRDTHREN - Card Read Threshold Enable.\r
+ */\r
+#define SDIF_CARDTHRCTL_CARDRDTHREN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK)\r
+#define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK (0x2U)\r
+#define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT (1U)\r
+/*! BSYCLRINTEN - Busy Clear Interrupt Enable.\r
+ */\r
+#define SDIF_CARDTHRCTL_BSYCLRINTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK)\r
+#define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK (0xFF0000U)\r
+#define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT (16U)\r
+/*! CARDTHRESHOLD - Card Threshold size.\r
+ */\r
+#define SDIF_CARDTHRCTL_CARDTHRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK)\r
+/*! @} */\r
+\r
+/*! @name BACKENDPWR - Power control */\r
+/*! @{ */\r
+#define SDIF_BACKENDPWR_BACKENDPWR_MASK (0x1U)\r
+#define SDIF_BACKENDPWR_BACKENDPWR_SHIFT (0U)\r
+/*! BACKENDPWR - Back-end Power control for card application.\r
+ */\r
+#define SDIF_BACKENDPWR_BACKENDPWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFO - SDIF FIFO */\r
+/*! @{ */\r
+#define SDIF_FIFO_DATA_MASK (0xFFFFFFFFU)\r
+#define SDIF_FIFO_DATA_SHIFT (0U)\r
+/*! DATA - SDIF FIFO.\r
+ */\r
+#define SDIF_FIFO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK)\r
+/*! @} */\r
+\r
+/* The count of SDIF_FIFO */\r
+#define SDIF_FIFO_COUNT (64U)\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group SDIF_Register_Masks */\r
+\r
+\r
+/* SDIF - Peripheral instance base addresses */\r
+/** Peripheral SDIF base address */\r
+#define SDIF_BASE (0x4009B000u)\r
+/** Peripheral SDIF base pointer */\r
+#define SDIF ((SDIF_Type *)SDIF_BASE)\r
+/** Array initializer of SDIF peripheral base addresses */\r
+#define SDIF_BASE_ADDRS { SDIF_BASE }\r
+/** Array initializer of SDIF peripheral base pointers */\r
+#define SDIF_BASE_PTRS { SDIF }\r
+/** Interrupt vectors for the SDIF peripheral type */\r
+#define SDIF_IRQS { SDIO_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group SDIF_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SHA Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup SHA_Peripheral_Access_Layer SHA Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** SHA - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t CTRL; /**< Control register, offset: 0x0 */\r
+ __IO uint32_t STATUS; /**< Status register, offset: 0x4 */\r
+ __IO uint32_t INTENSET; /**< Interrupt Enable register, offset: 0x8 */\r
+ __O uint32_t INTENCLR; /**< Interrupt Clear register, offset: 0xC */\r
+ __IO uint32_t MEMCTRL; /**< Memory Control register, offset: 0x10 */\r
+ __IO uint32_t MEMADDR; /**< Memory Address register, offset: 0x14 */\r
+ uint8_t RESERVED_0[8];\r
+ __O uint32_t INDATA; /**< Input Data register, offset: 0x20 */\r
+ __O uint32_t ALIAS[7]; /**< Alias register, array offset: 0x24, array step: 0x4 */\r
+ __I uint32_t DIGEST[8]; /**< Digest register, array offset: 0x40, array step: 0x4 */\r
+} SHA_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SHA Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup SHA_Register_Masks SHA Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CTRL - Control register */\r
+/*! @{ */\r
+#define SHA_CTRL_MODE_MASK (0x3U)\r
+#define SHA_CTRL_MODE_SHIFT (0U)\r
+/*! MODE - This field is used to select the operational mode of SHA block.\r
+ */\r
+#define SHA_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << SHA_CTRL_MODE_SHIFT)) & SHA_CTRL_MODE_MASK)\r
+#define SHA_CTRL_NEW_MASK (0x10U)\r
+#define SHA_CTRL_NEW_SHIFT (4U)\r
+/*! NEW - When this bit is set, a new hash operation is started.\r
+ */\r
+#define SHA_CTRL_NEW(x) (((uint32_t)(((uint32_t)(x)) << SHA_CTRL_NEW_SHIFT)) & SHA_CTRL_NEW_MASK)\r
+#define SHA_CTRL_DMA_MASK (0x100U)\r
+#define SHA_CTRL_DMA_SHIFT (8U)\r
+/*! DMA - When this bit is set, the DMA is used to fill INDATA.\r
+ */\r
+#define SHA_CTRL_DMA(x) (((uint32_t)(((uint32_t)(x)) << SHA_CTRL_DMA_SHIFT)) & SHA_CTRL_DMA_MASK)\r
+/*! @} */\r
+\r
+/*! @name STATUS - Status register */\r
+/*! @{ */\r
+#define SHA_STATUS_WAITING_MASK (0x1U)\r
+#define SHA_STATUS_WAITING_SHIFT (0U)\r
+/*! WAITING - This field indicates if the block is waiting for more data to process.\r
+ */\r
+#define SHA_STATUS_WAITING(x) (((uint32_t)(((uint32_t)(x)) << SHA_STATUS_WAITING_SHIFT)) & SHA_STATUS_WAITING_MASK)\r
+#define SHA_STATUS_DIGEST_MASK (0x2U)\r
+#define SHA_STATUS_DIGEST_SHIFT (1U)\r
+/*! DIGEST - This field indicates if a DIGEST is ready and waiting and there is no active next block that has already started.\r
+ */\r
+#define SHA_STATUS_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << SHA_STATUS_DIGEST_SHIFT)) & SHA_STATUS_DIGEST_MASK)\r
+#define SHA_STATUS_ERROR_MASK (0x4U)\r
+#define SHA_STATUS_ERROR_SHIFT (2U)\r
+/*! ERROR - This field indicates if an error has occurred.\r
+ */\r
+#define SHA_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SHA_STATUS_ERROR_SHIFT)) & SHA_STATUS_ERROR_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTENSET - Interrupt Enable register */\r
+/*! @{ */\r
+#define SHA_INTENSET_WAITING_MASK (0x1U)\r
+#define SHA_INTENSET_WAITING_SHIFT (0U)\r
+/*! WAITING - This field indicates if interrupt should be enabled when waiting for input data.\r
+ */\r
+#define SHA_INTENSET_WAITING(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENSET_WAITING_SHIFT)) & SHA_INTENSET_WAITING_MASK)\r
+#define SHA_INTENSET_DIGEST_MASK (0x2U)\r
+#define SHA_INTENSET_DIGEST_SHIFT (1U)\r
+/*! DIGEST - This field indicates if interrupt is generated when Digest is ready (completed a Hash or completed a full sequence).\r
+ */\r
+#define SHA_INTENSET_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENSET_DIGEST_SHIFT)) & SHA_INTENSET_DIGEST_MASK)\r
+#define SHA_INTENSET_ERROR_MASK (0x4U)\r
+#define SHA_INTENSET_ERROR_SHIFT (2U)\r
+/*! ERROR - This field indicates if interrupt is generated on an ERROR (as defined in STAT register).\r
+ */\r
+#define SHA_INTENSET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENSET_ERROR_SHIFT)) & SHA_INTENSET_ERROR_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTENCLR - Interrupt Clear register */\r
+/*! @{ */\r
+#define SHA_INTENCLR_WAITING_MASK (0x1U)\r
+#define SHA_INTENCLR_WAITING_SHIFT (0U)\r
+/*! WAITING - Writing a 1 clears the interrupt enabled by the INTENSET register.\r
+ */\r
+#define SHA_INTENCLR_WAITING(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENCLR_WAITING_SHIFT)) & SHA_INTENCLR_WAITING_MASK)\r
+#define SHA_INTENCLR_DIGEST_MASK (0x2U)\r
+#define SHA_INTENCLR_DIGEST_SHIFT (1U)\r
+/*! DIGEST - Writing a 1 clears the interrupt enabled by the INTENSET register.\r
+ */\r
+#define SHA_INTENCLR_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENCLR_DIGEST_SHIFT)) & SHA_INTENCLR_DIGEST_MASK)\r
+#define SHA_INTENCLR_ERROR_MASK (0x4U)\r
+#define SHA_INTENCLR_ERROR_SHIFT (2U)\r
+/*! ERROR - Writing a 1 clears the interrupt enabled by the INTENSET register.\r
+ */\r
+#define SHA_INTENCLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENCLR_ERROR_SHIFT)) & SHA_INTENCLR_ERROR_MASK)\r
+/*! @} */\r
+\r
+/*! @name MEMCTRL - Memory Control register */\r
+/*! @{ */\r
+#define SHA_MEMCTRL_MASTER_MASK (0x1U)\r
+#define SHA_MEMCTRL_MASTER_SHIFT (0U)\r
+/*! MASTER - This field is used to enable SHA block as AHB bus master.\r
+ */\r
+#define SHA_MEMCTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SHA_MEMCTRL_MASTER_SHIFT)) & SHA_MEMCTRL_MASTER_MASK)\r
+#define SHA_MEMCTRL_COUNT_MASK (0x7FF0000U)\r
+#define SHA_MEMCTRL_COUNT_SHIFT (16U)\r
+/*! COUNT - This field indicates the number of 512-bit blocks to copy starting at MEMADDR.\r
+ */\r
+#define SHA_MEMCTRL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SHA_MEMCTRL_COUNT_SHIFT)) & SHA_MEMCTRL_COUNT_MASK)\r
+/*! @} */\r
+\r
+/*! @name MEMADDR - Memory Address register */\r
+/*! @{ */\r
+#define SHA_MEMADDR_BASEADDR_MASK (0xFFFFFFFFU)\r
+#define SHA_MEMADDR_BASEADDR_SHIFT (0U)\r
+/*! BASEADDR - This field indicates the base address in Internal Flash, SRAM0, SRAMX, or SPIFI to start copying from.\r
+ */\r
+#define SHA_MEMADDR_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << SHA_MEMADDR_BASEADDR_SHIFT)) & SHA_MEMADDR_BASEADDR_MASK)\r
+/*! @} */\r
+\r
+/*! @name INDATA - Input Data register */\r
+/*! @{ */\r
+#define SHA_INDATA_DATA_MASK (0xFFFFFFFFU)\r
+#define SHA_INDATA_DATA_SHIFT (0U)\r
+/*! DATA - In this field the next word is written in little-endian format.\r
+ */\r
+#define SHA_INDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SHA_INDATA_DATA_SHIFT)) & SHA_INDATA_DATA_MASK)\r
+/*! @} */\r
+\r
+/*! @name ALIAS - Alias register */\r
+/*! @{ */\r
+#define SHA_ALIAS_DATA_MASK (0xFFFFFFFFU)\r
+#define SHA_ALIAS_DATA_SHIFT (0U)\r
+/*! DATA - In this field the next word is written in little-endian format.\r
+ */\r
+#define SHA_ALIAS_DATA(x) (((uint32_t)(((uint32_t)(x)) << SHA_ALIAS_DATA_SHIFT)) & SHA_ALIAS_DATA_MASK)\r
+/*! @} */\r
+\r
+/* The count of SHA_ALIAS */\r
+#define SHA_ALIAS_COUNT (7U)\r
+\r
+/*! @name DIGEST - Digest register */\r
+/*! @{ */\r
+#define SHA_DIGEST_DIGEST_MASK (0xFFFFFFFFU)\r
+#define SHA_DIGEST_DIGEST_SHIFT (0U)\r
+/*! DIGEST - This field contains one word of the Digest.\r
+ */\r
+#define SHA_DIGEST_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << SHA_DIGEST_DIGEST_SHIFT)) & SHA_DIGEST_DIGEST_MASK)\r
+/*! @} */\r
+\r
+/* The count of SHA_DIGEST */\r
+#define SHA_DIGEST_COUNT (8U)\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group SHA_Register_Masks */\r
+\r
+\r
+/* SHA - Peripheral instance base addresses */\r
+/** Peripheral SHA0 base address */\r
+#define SHA0_BASE (0x400A4000u)\r
+/** Peripheral SHA0 base pointer */\r
+#define SHA0 ((SHA_Type *)SHA0_BASE)\r
+/** Array initializer of SHA peripheral base addresses */\r
+#define SHA_BASE_ADDRS { SHA0_BASE }\r
+/** Array initializer of SHA peripheral base pointers */\r
+#define SHA_BASE_PTRS { SHA0 }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group SHA_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SMARTCARD Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup SMARTCARD_Peripheral_Access_Layer SMARTCARD Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** SMARTCARD - Register Layout Typedef */\r
+typedef struct {\r
+ union { /* offset: 0x0 */\r
+ __IO uint32_t DLL; /**< Divisor Latch LSB, offset: 0x0 */\r
+ __I uint32_t RBR; /**< Receiver Buffer Register, offset: 0x0 */\r
+ __O uint32_t THR; /**< Transmit Holding Register, offset: 0x0 */\r
+ };\r
+ union { /* offset: 0x4 */\r
+ __IO uint32_t DLM; /**< Divisor Latch MSB, offset: 0x4 */\r
+ __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x4 */\r
+ };\r
+ union { /* offset: 0x8 */\r
+ __O uint32_t FCR; /**< FIFO Control Register, offset: 0x8 */\r
+ __I uint32_t IIR; /**< Interrupt ID Register, offset: 0x8 */\r
+ };\r
+ __IO uint32_t LCR; /**< Line Control Register, offset: 0xC */\r
+ uint8_t RESERVED_0[4];\r
+ __I uint32_t LSR; /**< Line Status Register, offset: 0x14 */\r
+ uint8_t RESERVED_1[4];\r
+ __IO uint32_t SCR; /**< Scratch Pad Register, offset: 0x1C */\r
+ uint8_t RESERVED_2[12];\r
+ __IO uint32_t OSR; /**< Oversampling register, offset: 0x2C */\r
+ uint8_t RESERVED_3[24];\r
+ __IO uint32_t SCICTRL; /**< Smart Card Interface control register, offset: 0x48 */\r
+} SMARTCARD_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SMARTCARD Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup SMARTCARD_Register_Masks SMARTCARD Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name DLL - Divisor Latch LSB */\r
+/*! @{ */\r
+#define SMARTCARD_DLL_DLLSB_MASK (0xFFU)\r
+#define SMARTCARD_DLL_DLLSB_SHIFT (0U)\r
+/*! DLLSB - The SCIn Divisor Latch LSB Register, along with the SCInDLM register, determines the baud rate of the SCIn.\r
+ */\r
+#define SMARTCARD_DLL_DLLSB(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_DLL_DLLSB_SHIFT)) & SMARTCARD_DLL_DLLSB_MASK)\r
+/*! @} */\r
+\r
+/*! @name RBR - Receiver Buffer Register */\r
+/*! @{ */\r
+#define SMARTCARD_RBR_RBR_MASK (0xFFU)\r
+#define SMARTCARD_RBR_RBR_SHIFT (0U)\r
+/*! RBR - The SCIn Receiver Buffer Register contains the oldest received byte in the SCIn Rx FIFO.\r
+ */\r
+#define SMARTCARD_RBR_RBR(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_RBR_RBR_SHIFT)) & SMARTCARD_RBR_RBR_MASK)\r
+/*! @} */\r
+\r
+/*! @name THR - Transmit Holding Register */\r
+/*! @{ */\r
+#define SMARTCARD_THR_THR_MASK (0xFFU)\r
+#define SMARTCARD_THR_THR_SHIFT (0U)\r
+/*! THR - Writing to the SCIn Transmit Holding Register causes the data to be stored in the SCIn transmit FIFO.\r
+ */\r
+#define SMARTCARD_THR_THR(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_THR_THR_SHIFT)) & SMARTCARD_THR_THR_MASK)\r
+/*! @} */\r
+\r
+/*! @name DLM - Divisor Latch MSB */\r
+/*! @{ */\r
+#define SMARTCARD_DLM_DLMSB_MASK (0xFFU)\r
+#define SMARTCARD_DLM_DLMSB_SHIFT (0U)\r
+/*! DLMSB - The SCIn Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the SCIn.\r
+ */\r
+#define SMARTCARD_DLM_DLMSB(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_DLM_DLMSB_SHIFT)) & SMARTCARD_DLM_DLMSB_MASK)\r
+/*! @} */\r
+\r
+/*! @name IER - Interrupt Enable Register */\r
+/*! @{ */\r
+#define SMARTCARD_IER_RBRIE_MASK (0x1U)\r
+#define SMARTCARD_IER_RBRIE_SHIFT (0U)\r
+/*! RBRIE - RBR Interrupt Enable.\r
+ */\r
+#define SMARTCARD_IER_RBRIE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_RBRIE_SHIFT)) & SMARTCARD_IER_RBRIE_MASK)\r
+#define SMARTCARD_IER_THREIE_MASK (0x2U)\r
+#define SMARTCARD_IER_THREIE_SHIFT (1U)\r
+/*! THREIE - THRE Interrupt Enable.\r
+ */\r
+#define SMARTCARD_IER_THREIE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_THREIE_SHIFT)) & SMARTCARD_IER_THREIE_MASK)\r
+#define SMARTCARD_IER_RXIE_MASK (0x4U)\r
+#define SMARTCARD_IER_RXIE_SHIFT (2U)\r
+/*! RXIE - RX Line Status Interrupt Enable.\r
+ */\r
+#define SMARTCARD_IER_RXIE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_RXIE_SHIFT)) & SMARTCARD_IER_RXIE_MASK)\r
+/*! @} */\r
+\r
+/*! @name FCR - FIFO Control Register */\r
+/*! @{ */\r
+#define SMARTCARD_FCR_FIFOEN_MASK (0x1U)\r
+#define SMARTCARD_FCR_FIFOEN_SHIFT (0U)\r
+/*! FIFOEN - FIFO Enable.\r
+ */\r
+#define SMARTCARD_FCR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_FIFOEN_SHIFT)) & SMARTCARD_FCR_FIFOEN_MASK)\r
+#define SMARTCARD_FCR_RXFIFORES_MASK (0x2U)\r
+#define SMARTCARD_FCR_RXFIFORES_SHIFT (1U)\r
+/*! RXFIFORES - RX FIFO Reset.\r
+ */\r
+#define SMARTCARD_FCR_RXFIFORES(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_RXFIFORES_SHIFT)) & SMARTCARD_FCR_RXFIFORES_MASK)\r
+#define SMARTCARD_FCR_TXFIFORES_MASK (0x4U)\r
+#define SMARTCARD_FCR_TXFIFORES_SHIFT (2U)\r
+/*! TXFIFORES - TX FIFO Reset.\r
+ */\r
+#define SMARTCARD_FCR_TXFIFORES(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_TXFIFORES_SHIFT)) & SMARTCARD_FCR_TXFIFORES_MASK)\r
+#define SMARTCARD_FCR_DMAMODE_MASK (0x8U)\r
+#define SMARTCARD_FCR_DMAMODE_SHIFT (3U)\r
+/*! DMAMODE - DMA Mode Select.\r
+ */\r
+#define SMARTCARD_FCR_DMAMODE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_DMAMODE_SHIFT)) & SMARTCARD_FCR_DMAMODE_MASK)\r
+#define SMARTCARD_FCR_RXTRIGLVL_MASK (0xC0U)\r
+#define SMARTCARD_FCR_RXTRIGLVL_SHIFT (6U)\r
+/*! RXTRIGLVL - RX Trigger Level.\r
+ */\r
+#define SMARTCARD_FCR_RXTRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_RXTRIGLVL_SHIFT)) & SMARTCARD_FCR_RXTRIGLVL_MASK)\r
+/*! @} */\r
+\r
+/*! @name IIR - Interrupt ID Register */\r
+/*! @{ */\r
+#define SMARTCARD_IIR_INTSTATUS_MASK (0x1U)\r
+#define SMARTCARD_IIR_INTSTATUS_SHIFT (0U)\r
+/*! INTSTATUS - Interrupt status.\r
+ */\r
+#define SMARTCARD_IIR_INTSTATUS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_INTSTATUS_SHIFT)) & SMARTCARD_IIR_INTSTATUS_MASK)\r
+#define SMARTCARD_IIR_INTID_MASK (0xEU)\r
+#define SMARTCARD_IIR_INTID_SHIFT (1U)\r
+/*! INTID - Interrupt identification.\r
+ */\r
+#define SMARTCARD_IIR_INTID(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_INTID_SHIFT)) & SMARTCARD_IIR_INTID_MASK)\r
+#define SMARTCARD_IIR_FIFOENABLE_MASK (0xC0U)\r
+#define SMARTCARD_IIR_FIFOENABLE_SHIFT (6U)\r
+/*! FIFOENABLE - Copies of SCInFCR[0].\r
+ */\r
+#define SMARTCARD_IIR_FIFOENABLE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_FIFOENABLE_SHIFT)) & SMARTCARD_IIR_FIFOENABLE_MASK)\r
+/*! @} */\r
+\r
+/*! @name LCR - Line Control Register */\r
+/*! @{ */\r
+#define SMARTCARD_LCR_WLS_MASK (0x3U)\r
+#define SMARTCARD_LCR_WLS_SHIFT (0U)\r
+/*! WLS - Word Length Select.\r
+ */\r
+#define SMARTCARD_LCR_WLS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_WLS_SHIFT)) & SMARTCARD_LCR_WLS_MASK)\r
+#define SMARTCARD_LCR_SBS_MASK (0x4U)\r
+#define SMARTCARD_LCR_SBS_SHIFT (2U)\r
+/*! SBS - Stop Bit Select.\r
+ */\r
+#define SMARTCARD_LCR_SBS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_SBS_SHIFT)) & SMARTCARD_LCR_SBS_MASK)\r
+#define SMARTCARD_LCR_PE_MASK (0x8U)\r
+#define SMARTCARD_LCR_PE_SHIFT (3U)\r
+/*! PE - Parity Enable.\r
+ */\r
+#define SMARTCARD_LCR_PE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_PE_SHIFT)) & SMARTCARD_LCR_PE_MASK)\r
+#define SMARTCARD_LCR_PS_MASK (0x30U)\r
+#define SMARTCARD_LCR_PS_SHIFT (4U)\r
+/*! PS - Parity Select.\r
+ */\r
+#define SMARTCARD_LCR_PS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_PS_SHIFT)) & SMARTCARD_LCR_PS_MASK)\r
+#define SMARTCARD_LCR_DLAB_MASK (0x80U)\r
+#define SMARTCARD_LCR_DLAB_SHIFT (7U)\r
+/*! DLAB - Divisor Latch Access Bit.\r
+ */\r
+#define SMARTCARD_LCR_DLAB(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_DLAB_SHIFT)) & SMARTCARD_LCR_DLAB_MASK)\r
+/*! @} */\r
+\r
+/*! @name LSR - Line Status Register */\r
+/*! @{ */\r
+#define SMARTCARD_LSR_RDR_MASK (0x1U)\r
+#define SMARTCARD_LSR_RDR_SHIFT (0U)\r
+/*! RDR - Receiver Data Ready.\r
+ */\r
+#define SMARTCARD_LSR_RDR(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_RDR_SHIFT)) & SMARTCARD_LSR_RDR_MASK)\r
+#define SMARTCARD_LSR_OE_MASK (0x2U)\r
+#define SMARTCARD_LSR_OE_SHIFT (1U)\r
+/*! OE - Overrun Error.\r
+ */\r
+#define SMARTCARD_LSR_OE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_OE_SHIFT)) & SMARTCARD_LSR_OE_MASK)\r
+#define SMARTCARD_LSR_PE_MASK (0x4U)\r
+#define SMARTCARD_LSR_PE_SHIFT (2U)\r
+/*! PE - Parity Error.\r
+ */\r
+#define SMARTCARD_LSR_PE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_PE_SHIFT)) & SMARTCARD_LSR_PE_MASK)\r
+#define SMARTCARD_LSR_FE_MASK (0x8U)\r
+#define SMARTCARD_LSR_FE_SHIFT (3U)\r
+/*! FE - Framing Error.\r
+ */\r
+#define SMARTCARD_LSR_FE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_FE_SHIFT)) & SMARTCARD_LSR_FE_MASK)\r
+#define SMARTCARD_LSR_THRE_MASK (0x20U)\r
+#define SMARTCARD_LSR_THRE_SHIFT (5U)\r
+/*! THRE - Transmitter Holding Register Empty.\r
+ */\r
+#define SMARTCARD_LSR_THRE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_THRE_SHIFT)) & SMARTCARD_LSR_THRE_MASK)\r
+#define SMARTCARD_LSR_TEMT_MASK (0x40U)\r
+#define SMARTCARD_LSR_TEMT_SHIFT (6U)\r
+/*! TEMT - Transmitter Empty.\r
+ */\r
+#define SMARTCARD_LSR_TEMT(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_TEMT_SHIFT)) & SMARTCARD_LSR_TEMT_MASK)\r
+#define SMARTCARD_LSR_RXFE_MASK (0x80U)\r
+#define SMARTCARD_LSR_RXFE_SHIFT (7U)\r
+/*! RXFE - Error in RX FIFO.\r
+ */\r
+#define SMARTCARD_LSR_RXFE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_RXFE_SHIFT)) & SMARTCARD_LSR_RXFE_MASK)\r
+/*! @} */\r
+\r
+/*! @name SCR - Scratch Pad Register */\r
+/*! @{ */\r
+#define SMARTCARD_SCR_PAD_MASK (0xFFU)\r
+#define SMARTCARD_SCR_PAD_SHIFT (0U)\r
+/*! PAD - A readable, writable byte.\r
+ */\r
+#define SMARTCARD_SCR_PAD(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCR_PAD_SHIFT)) & SMARTCARD_SCR_PAD_MASK)\r
+/*! @} */\r
+\r
+/*! @name OSR - Oversampling register */\r
+/*! @{ */\r
+#define SMARTCARD_OSR_OSFRAC_MASK (0xEU)\r
+#define SMARTCARD_OSR_OSFRAC_SHIFT (1U)\r
+/*! OSFRAC - Fractional part of the oversampling ratio, in units of 1/8th of an input clock period.\r
+ */\r
+#define SMARTCARD_OSR_OSFRAC(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_OSFRAC_SHIFT)) & SMARTCARD_OSR_OSFRAC_MASK)\r
+#define SMARTCARD_OSR_OSINT_MASK (0xF0U)\r
+#define SMARTCARD_OSR_OSINT_SHIFT (4U)\r
+/*! OSINT - Integer part of the oversampling ratio, minus 1.\r
+ */\r
+#define SMARTCARD_OSR_OSINT(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_OSINT_SHIFT)) & SMARTCARD_OSR_OSINT_MASK)\r
+#define SMARTCARD_OSR_FDINT_MASK (0x7F00U)\r
+#define SMARTCARD_OSR_FDINT_SHIFT (8U)\r
+/*! FDINT - These bits act as a more-significant extension of the OSint field, allowing an\r
+ * oversampling ratio up to 2048 as required by ISO7816-3.\r
+ */\r
+#define SMARTCARD_OSR_FDINT(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_FDINT_SHIFT)) & SMARTCARD_OSR_FDINT_MASK)\r
+/*! @} */\r
+\r
+/*! @name SCICTRL - Smart Card Interface control register */\r
+/*! @{ */\r
+#define SMARTCARD_SCICTRL_SCIEN_MASK (0x1U)\r
+#define SMARTCARD_SCICTRL_SCIEN_SHIFT (0U)\r
+/*! SCIEN - Smart Card Interface Enable.\r
+ */\r
+#define SMARTCARD_SCICTRL_SCIEN(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_SCIEN_SHIFT)) & SMARTCARD_SCICTRL_SCIEN_MASK)\r
+#define SMARTCARD_SCICTRL_NACKDIS_MASK (0x2U)\r
+#define SMARTCARD_SCICTRL_NACKDIS_SHIFT (1U)\r
+/*! NACKDIS - NACK response disable.\r
+ */\r
+#define SMARTCARD_SCICTRL_NACKDIS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_NACKDIS_SHIFT)) & SMARTCARD_SCICTRL_NACKDIS_MASK)\r
+#define SMARTCARD_SCICTRL_PROTSEL_MASK (0x4U)\r
+#define SMARTCARD_SCICTRL_PROTSEL_SHIFT (2U)\r
+/*! PROTSEL - Protocol selection as defined in the ISO7816-3 standard.\r
+ */\r
+#define SMARTCARD_SCICTRL_PROTSEL(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_PROTSEL_SHIFT)) & SMARTCARD_SCICTRL_PROTSEL_MASK)\r
+#define SMARTCARD_SCICTRL_TXRETRY_MASK (0xE0U)\r
+#define SMARTCARD_SCICTRL_TXRETRY_SHIFT (5U)\r
+/*! TXRETRY - Maximum number of retransmissions in case of a negative acknowledge (protocol T=0).\r
+ */\r
+#define SMARTCARD_SCICTRL_TXRETRY(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_TXRETRY_SHIFT)) & SMARTCARD_SCICTRL_TXRETRY_MASK)\r
+#define SMARTCARD_SCICTRL_GUARDTIME_MASK (0xFF00U)\r
+#define SMARTCARD_SCICTRL_GUARDTIME_SHIFT (8U)\r
+/*! GUARDTIME - Extra guard time.\r
+ */\r
+#define SMARTCARD_SCICTRL_GUARDTIME(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_GUARDTIME_SHIFT)) & SMARTCARD_SCICTRL_GUARDTIME_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group SMARTCARD_Register_Masks */\r
+\r
+\r
+/* SMARTCARD - Peripheral instance base addresses */\r
+/** Peripheral SMARTCARD0 base address */\r
+#define SMARTCARD0_BASE (0x40036000u)\r
+/** Peripheral SMARTCARD0 base pointer */\r
+#define SMARTCARD0 ((SMARTCARD_Type *)SMARTCARD0_BASE)\r
+/** Peripheral SMARTCARD1 base address */\r
+#define SMARTCARD1_BASE (0x40037000u)\r
+/** Peripheral SMARTCARD1 base pointer */\r
+#define SMARTCARD1 ((SMARTCARD_Type *)SMARTCARD1_BASE)\r
+/** Array initializer of SMARTCARD peripheral base addresses */\r
+#define SMARTCARD_BASE_ADDRS { SMARTCARD0_BASE, SMARTCARD1_BASE }\r
+/** Array initializer of SMARTCARD peripheral base pointers */\r
+#define SMARTCARD_BASE_PTRS { SMARTCARD0, SMARTCARD1 }\r
+/** Interrupt vectors for the SMARTCARD peripheral type */\r
+#define SMARTCARD_IRQS { SMARTCARD0_IRQn, SMARTCARD1_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group SMARTCARD_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SPI Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** SPI - Register Layout Typedef */\r
+typedef struct {\r
+ uint8_t RESERVED_0[1024];\r
+ __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */\r
+ __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */\r
+ __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */\r
+ __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */\r
+ __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */\r
+ uint8_t RESERVED_1[16];\r
+ __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */\r
+ __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */\r
+ uint8_t RESERVED_2[2516];\r
+ __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */\r
+ __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */\r
+ __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */\r
+ uint8_t RESERVED_3[4];\r
+ __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */\r
+ __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */\r
+ __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */\r
+ uint8_t RESERVED_4[4];\r
+ __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */\r
+ uint8_t RESERVED_5[12];\r
+ __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */\r
+ uint8_t RESERVED_6[12];\r
+ __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */\r
+ uint8_t RESERVED_7[440];\r
+ __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */\r
+} SPI_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SPI Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup SPI_Register_Masks SPI Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CFG - SPI Configuration register */\r
+/*! @{ */\r
+#define SPI_CFG_ENABLE_MASK (0x1U)\r
+#define SPI_CFG_ENABLE_SHIFT (0U)\r
+/*! ENABLE - SPI enable.\r
+ * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset.\r
+ * 0b1..Enabled. The SPI is enabled for operation.\r
+ */\r
+#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)\r
+#define SPI_CFG_MASTER_MASK (0x4U)\r
+#define SPI_CFG_MASTER_SHIFT (2U)\r
+/*! MASTER - Master mode select.\r
+ * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.\r
+ * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.\r
+ */\r
+#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK)\r
+#define SPI_CFG_LSBF_MASK (0x8U)\r
+#define SPI_CFG_LSBF_SHIFT (3U)\r
+/*! LSBF - LSB First mode enable.\r
+ * 0b0..Standard. Data is transmitted and received in standard MSB first order.\r
+ * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first).\r
+ */\r
+#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK)\r
+#define SPI_CFG_CPHA_MASK (0x10U)\r
+#define SPI_CFG_CPHA_SHIFT (4U)\r
+/*! CPHA - Clock Phase select.\r
+ * 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock\r
+ * changes away from the rest state). Data is changed on the following edge.\r
+ * 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock\r
+ * changes away from the rest state). Data is captured on the following edge.\r
+ */\r
+#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK)\r
+#define SPI_CFG_CPOL_MASK (0x20U)\r
+#define SPI_CFG_CPOL_SHIFT (5U)\r
+/*! CPOL - Clock Polarity select.\r
+ * 0b0..Low. The rest state of the clock (between transfers) is low.\r
+ * 0b1..High. The rest state of the clock (between transfers) is high.\r
+ */\r
+#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK)\r
+#define SPI_CFG_LOOP_MASK (0x80U)\r
+#define SPI_CFG_LOOP_SHIFT (7U)\r
+/*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit\r
+ * and receive data connected together to allow simple software testing.\r
+ * 0b0..Disabled.\r
+ * 0b1..Enabled.\r
+ */\r
+#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK)\r
+#define SPI_CFG_SPOL0_MASK (0x100U)\r
+#define SPI_CFG_SPOL0_SHIFT (8U)\r
+/*! SPOL0 - SSEL0 Polarity select.\r
+ * 0b0..Low. The SSEL0 pin is active low.\r
+ * 0b1..High. The SSEL0 pin is active high.\r
+ */\r
+#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)\r
+#define SPI_CFG_SPOL1_MASK (0x200U)\r
+#define SPI_CFG_SPOL1_SHIFT (9U)\r
+/*! SPOL1 - SSEL1 Polarity select.\r
+ * 0b0..Low. The SSEL1 pin is active low.\r
+ * 0b1..High. The SSEL1 pin is active high.\r
+ */\r
+#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK)\r
+#define SPI_CFG_SPOL2_MASK (0x400U)\r
+#define SPI_CFG_SPOL2_SHIFT (10U)\r
+/*! SPOL2 - SSEL2 Polarity select.\r
+ * 0b0..Low. The SSEL2 pin is active low.\r
+ * 0b1..High. The SSEL2 pin is active high.\r
+ */\r
+#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)\r
+#define SPI_CFG_SPOL3_MASK (0x800U)\r
+#define SPI_CFG_SPOL3_SHIFT (11U)\r
+/*! SPOL3 - SSEL3 Polarity select.\r
+ * 0b0..Low. The SSEL3 pin is active low.\r
+ * 0b1..High. The SSEL3 pin is active high.\r
+ */\r
+#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK)\r
+/*! @} */\r
+\r
+/*! @name DLY - SPI Delay register */\r
+/*! @{ */\r
+#define SPI_DLY_PRE_DELAY_MASK (0xFU)\r
+#define SPI_DLY_PRE_DELAY_SHIFT (0U)\r
+/*! PRE_DELAY - Controls the amount of time between SSEL assertion and the beginning of a data\r
+ * transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This\r
+ * is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI\r
+ * clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are\r
+ * inserted.\r
+ */\r
+#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK)\r
+#define SPI_DLY_POST_DELAY_MASK (0xF0U)\r
+#define SPI_DLY_POST_DELAY_SHIFT (4U)\r
+/*! POST_DELAY - Controls the amount of time between the end of a data transfer and SSEL\r
+ * deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock\r
+ * times are inserted. 0xF = 15 SPI clock times are inserted.\r
+ */\r
+#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK)\r
+#define SPI_DLY_FRAME_DELAY_MASK (0xF00U)\r
+#define SPI_DLY_FRAME_DELAY_SHIFT (8U)\r
+/*! FRAME_DELAY - If the EOF flag is set, controls the minimum amount of time between the current\r
+ * frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1\r
+ * = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock\r
+ * times are inserted.\r
+ */\r
+#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK)\r
+#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U)\r
+#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U)\r
+/*! TRANSFER_DELAY - Controls the minimum amount of time that the SSEL is deasserted between\r
+ * transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1\r
+ * = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that\r
+ * SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16\r
+ * SPI clock times.\r
+ */\r
+#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK)\r
+/*! @} */\r
+\r
+/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */\r
+/*! @{ */\r
+#define SPI_STAT_SSA_MASK (0x10U)\r
+#define SPI_STAT_SSA_SHIFT (4U)\r
+/*! SSA - Slave Select Assert. This flag is set whenever any slave select transitions from\r
+ * deasserted to asserted, in both master and slave modes. This allows determining when the SPI\r
+ * transmit/receive functions become busy, and allows waking up the device from reduced power modes when a\r
+ * slave mode access begins. This flag is cleared by software.\r
+ */\r
+#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK)\r
+#define SPI_STAT_SSD_MASK (0x20U)\r
+#define SPI_STAT_SSD_SHIFT (5U)\r
+/*! SSD - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to\r
+ * deasserted, in both master and slave modes. This allows determining when the SPI\r
+ * transmit/receive functions become idle. This flag is cleared by software.\r
+ */\r
+#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK)\r
+#define SPI_STAT_STALLED_MASK (0x40U)\r
+#define SPI_STAT_STALLED_SHIFT (6U)\r
+/*! STALLED - Stalled status flag. This indicates whether the SPI is currently in a stall condition.\r
+ */\r
+#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK)\r
+#define SPI_STAT_ENDTRANSFER_MASK (0x80U)\r
+#define SPI_STAT_ENDTRANSFER_SHIFT (7U)\r
+/*! ENDTRANSFER - End Transfer control bit. Software can set this bit to force an end to the current\r
+ * transfer when the transmitter finishes any activity already in progress, as if the EOT flag\r
+ * had been set prior to the last transmission. This capability is included to support cases where\r
+ * it is not known when transmit data is written that it will be the end of a transfer. The bit\r
+ * is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end\r
+ * of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted.\r
+ */\r
+#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK)\r
+#define SPI_STAT_MSTIDLE_MASK (0x100U)\r
+#define SPI_STAT_MSTIDLE_SHIFT (8U)\r
+/*! MSTIDLE - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle.\r
+ * This means that the transmit holding register is empty and the transmitter is not in the\r
+ * process of sending data.\r
+ */\r
+#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */\r
+/*! @{ */\r
+#define SPI_INTENSET_SSAEN_MASK (0x10U)\r
+#define SPI_INTENSET_SSAEN_SHIFT (4U)\r
+/*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted.\r
+ * 0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted.\r
+ * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted.\r
+ */\r
+#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK)\r
+#define SPI_INTENSET_SSDEN_MASK (0x20U)\r
+#define SPI_INTENSET_SSDEN_SHIFT (5U)\r
+/*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted.\r
+ * 0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted.\r
+ * 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted.\r
+ */\r
+#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK)\r
+#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U)\r
+#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U)\r
+/*! MSTIDLEEN - Master idle interrupt enable.\r
+ * 0b0..No interrupt will be generated when the SPI master function is idle.\r
+ * 0b1..An interrupt will be generated when the SPI master function is fully idle.\r
+ */\r
+#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */\r
+/*! @{ */\r
+#define SPI_INTENCLR_SSAEN_MASK (0x10U)\r
+#define SPI_INTENCLR_SSAEN_SHIFT (4U)\r
+/*! SSAEN - Writing 1 clears the corresponding bit in the INTENSET register.\r
+ */\r
+#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK)\r
+#define SPI_INTENCLR_SSDEN_MASK (0x20U)\r
+#define SPI_INTENCLR_SSDEN_SHIFT (5U)\r
+/*! SSDEN - Writing 1 clears the corresponding bit in the INTENSET register.\r
+ */\r
+#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK)\r
+#define SPI_INTENCLR_MSTIDLE_MASK (0x100U)\r
+#define SPI_INTENCLR_MSTIDLE_SHIFT (8U)\r
+/*! MSTIDLE - Writing 1 clears the corresponding bit in the INTENSET register.\r
+ */\r
+#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK)\r
+/*! @} */\r
+\r
+/*! @name DIV - SPI clock Divider */\r
+/*! @{ */\r
+#define SPI_DIV_DIVVAL_MASK (0xFFFFU)\r
+#define SPI_DIV_DIVVAL_SHIFT (0U)\r
+/*! DIVVAL - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the\r
+ * SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1,\r
+ * the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results\r
+ * in FCLK/65536.\r
+ */\r
+#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTSTAT - SPI Interrupt Status */\r
+/*! @{ */\r
+#define SPI_INTSTAT_SSA_MASK (0x10U)\r
+#define SPI_INTSTAT_SSA_SHIFT (4U)\r
+/*! SSA - Slave Select Assert.\r
+ */\r
+#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK)\r
+#define SPI_INTSTAT_SSD_MASK (0x20U)\r
+#define SPI_INTSTAT_SSD_SHIFT (5U)\r
+/*! SSD - Slave Select Deassert.\r
+ */\r
+#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK)\r
+#define SPI_INTSTAT_MSTIDLE_MASK (0x100U)\r
+#define SPI_INTSTAT_MSTIDLE_SHIFT (8U)\r
+/*! MSTIDLE - Master Idle status flag.\r
+ */\r
+#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOCFG - FIFO configuration and enable register. */\r
+/*! @{ */\r
+#define SPI_FIFOCFG_ENABLETX_MASK (0x1U)\r
+#define SPI_FIFOCFG_ENABLETX_SHIFT (0U)\r
+/*! ENABLETX - Enable the transmit FIFO.\r
+ * 0b0..The transmit FIFO is not enabled.\r
+ * 0b1..The transmit FIFO is enabled.\r
+ */\r
+#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)\r
+#define SPI_FIFOCFG_ENABLERX_MASK (0x2U)\r
+#define SPI_FIFOCFG_ENABLERX_SHIFT (1U)\r
+/*! ENABLERX - Enable the receive FIFO.\r
+ * 0b0..The receive FIFO is not enabled.\r
+ * 0b1..The receive FIFO is enabled.\r
+ */\r
+#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK)\r
+#define SPI_FIFOCFG_SIZE_MASK (0x30U)\r
+#define SPI_FIFOCFG_SIZE_SHIFT (4U)\r
+/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16\r
+ * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART.\r
+ */\r
+#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK)\r
+#define SPI_FIFOCFG_DMATX_MASK (0x1000U)\r
+#define SPI_FIFOCFG_DMATX_SHIFT (12U)\r
+/*! DMATX - DMA configuration for transmit.\r
+ * 0b0..DMA is not used for the transmit function.\r
+ * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.\r
+ */\r
+#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK)\r
+#define SPI_FIFOCFG_DMARX_MASK (0x2000U)\r
+#define SPI_FIFOCFG_DMARX_SHIFT (13U)\r
+/*! DMARX - DMA configuration for receive.\r
+ * 0b0..DMA is not used for the receive function.\r
+ * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.\r
+ */\r
+#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK)\r
+#define SPI_FIFOCFG_WAKETX_MASK (0x4000U)\r
+#define SPI_FIFOCFG_WAKETX_SHIFT (14U)\r
+/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power\r
+ * modes (up to power-down, as long as the peripheral function works in that power mode) without\r
+ * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The\r
+ * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware\r
+ * Wake-up control register.\r
+ * 0b0..Only enabled interrupts will wake up the device form reduced power modes.\r
+ * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in\r
+ * FIFOTRIG, even when the TXLVL interrupt is not enabled.\r
+ */\r
+#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK)\r
+#define SPI_FIFOCFG_WAKERX_MASK (0x8000U)\r
+#define SPI_FIFOCFG_WAKERX_SHIFT (15U)\r
+/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power\r
+ * modes (up to power-down, as long as the peripheral function works in that power mode) without\r
+ * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The\r
+ * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware\r
+ * Wake-up control register.\r
+ * 0b0..Only enabled interrupts will wake up the device form reduced power modes.\r
+ * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in\r
+ * FIFOTRIG, even when the RXLVL interrupt is not enabled.\r
+ */\r
+#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK)\r
+#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U)\r
+#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U)\r
+/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.\r
+ */\r
+#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK)\r
+#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U)\r
+#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U)\r
+/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.\r
+ */\r
+#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOSTAT - FIFO status register. */\r
+/*! @{ */\r
+#define SPI_FIFOSTAT_TXERR_MASK (0x1U)\r
+#define SPI_FIFOSTAT_TXERR_SHIFT (0U)\r
+/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow\r
+ * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is\r
+ * needed. Cleared by writing a 1 to this bit.\r
+ */\r
+#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK)\r
+#define SPI_FIFOSTAT_RXERR_MASK (0x2U)\r
+#define SPI_FIFOSTAT_RXERR_SHIFT (1U)\r
+/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA\r
+ * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit.\r
+ */\r
+#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK)\r
+#define SPI_FIFOSTAT_PERINT_MASK (0x8U)\r
+#define SPI_FIFOSTAT_PERINT_SHIFT (3U)\r
+/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted\r
+ * an interrupt. The details can be found by reading the peripheral's STAT register.\r
+ */\r
+#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK)\r
+#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U)\r
+#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U)\r
+/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data.\r
+ */\r
+#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK)\r
+#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U)\r
+#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U)\r
+/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be\r
+ * written. When 0, the transmit FIFO is full and another write would cause it to overflow.\r
+ */\r
+#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK)\r
+#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)\r
+#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)\r
+/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty.\r
+ */\r
+#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK)\r
+#define SPI_FIFOSTAT_RXFULL_MASK (0x80U)\r
+#define SPI_FIFOSTAT_RXFULL_SHIFT (7U)\r
+/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to\r
+ * prevent the peripheral from causing an overflow.\r
+ */\r
+#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK)\r
+#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U)\r
+#define SPI_FIFOSTAT_TXLVL_SHIFT (8U)\r
+/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY\r
+ * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at\r
+ * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be\r
+ * 0.\r
+ */\r
+#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK)\r
+#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U)\r
+#define SPI_FIFOSTAT_RXLVL_SHIFT (16U)\r
+/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and\r
+ * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the\r
+ * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be\r
+ * 1.\r
+ */\r
+#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */\r
+/*! @{ */\r
+#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U)\r
+#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U)\r
+/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled\r
+ * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.\r
+ * 0b0..Transmit FIFO level does not generate a FIFO level trigger.\r
+ * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.\r
+ */\r
+#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK)\r
+#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U)\r
+#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U)\r
+/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled\r
+ * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.\r
+ * 0b0..Receive FIFO level does not generate a FIFO level trigger.\r
+ * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.\r
+ */\r
+#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK)\r
+#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U)\r
+#define SPI_FIFOTRIG_TXLVL_SHIFT (8U)\r
+/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled\r
+ * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to\r
+ * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO\r
+ * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX\r
+ * FIFO level decreases to 15 entries (is no longer full).\r
+ */\r
+#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK)\r
+#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U)\r
+#define SPI_FIFOTRIG_RXLVL_SHIFT (16U)\r
+/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data\r
+ * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level\r
+ * can wake up the device just enough to perform DMA, then return to the reduced power mode. See\r
+ * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no\r
+ * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX\r
+ * FIFO has received 16 entries (has become full).\r
+ */\r
+#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */\r
+/*! @{ */\r
+#define SPI_FIFOINTENSET_TXERR_MASK (0x1U)\r
+#define SPI_FIFOINTENSET_TXERR_SHIFT (0U)\r
+/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.\r
+ * 0b0..No interrupt will be generated for a transmit error.\r
+ * 0b1..An interrupt will be generated when a transmit error occurs.\r
+ */\r
+#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK)\r
+#define SPI_FIFOINTENSET_RXERR_MASK (0x2U)\r
+#define SPI_FIFOINTENSET_RXERR_SHIFT (1U)\r
+/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.\r
+ * 0b0..No interrupt will be generated for a receive error.\r
+ * 0b1..An interrupt will be generated when a receive error occurs.\r
+ */\r
+#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK)\r
+#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U)\r
+#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U)\r
+/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level\r
+ * specified by the TXLVL field in the FIFOTRIG register.\r
+ * 0b0..No interrupt will be generated based on the TX FIFO level.\r
+ * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases\r
+ * to the level specified by TXLVL in the FIFOTRIG register.\r
+ */\r
+#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK)\r
+#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U)\r
+#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U)\r
+/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level\r
+ * specified by the TXLVL field in the FIFOTRIG register.\r
+ * 0b0..No interrupt will be generated based on the RX FIFO level.\r
+ * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level\r
+ * increases to the level specified by RXLVL in the FIFOTRIG register.\r
+ */\r
+#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */\r
+/*! @{ */\r
+#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U)\r
+#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U)\r
+/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.\r
+ */\r
+#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK)\r
+#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U)\r
+#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U)\r
+/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.\r
+ */\r
+#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK)\r
+#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U)\r
+#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U)\r
+/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.\r
+ */\r
+#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK)\r
+#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U)\r
+#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U)\r
+/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.\r
+ */\r
+#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOINTSTAT - FIFO interrupt status register. */\r
+/*! @{ */\r
+#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U)\r
+#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U)\r
+/*! TXERR - TX FIFO error.\r
+ */\r
+#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK)\r
+#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U)\r
+#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U)\r
+/*! RXERR - RX FIFO error.\r
+ */\r
+#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK)\r
+#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U)\r
+#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U)\r
+/*! TXLVL - Transmit FIFO level interrupt.\r
+ */\r
+#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK)\r
+#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U)\r
+#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U)\r
+/*! RXLVL - Receive FIFO level interrupt.\r
+ */\r
+#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK)\r
+#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U)\r
+#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U)\r
+/*! PERINT - Peripheral interrupt.\r
+ */\r
+#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOWR - FIFO write data. */\r
+/*! @{ */\r
+#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU)\r
+#define SPI_FIFOWR_TXDATA_SHIFT (0U)\r
+/*! TXDATA - Transmit data to the FIFO.\r
+ */\r
+#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK)\r
+#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U)\r
+#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U)\r
+/*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default.\r
+ * 0b0..SSEL0 asserted.\r
+ * 0b1..SSEL0 not asserted.\r
+ */\r
+#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK)\r
+#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U)\r
+#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U)\r
+/*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default.\r
+ * 0b0..SSEL1 asserted.\r
+ * 0b1..SSEL1 not asserted.\r
+ */\r
+#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK)\r
+#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U)\r
+#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U)\r
+/*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default.\r
+ * 0b0..SSEL2 asserted.\r
+ * 0b1..SSEL2 not asserted.\r
+ */\r
+#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)\r
+#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U)\r
+#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U)\r
+/*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default.\r
+ * 0b0..SSEL3 asserted.\r
+ * 0b1..SSEL3 not asserted.\r
+ */\r
+#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK)\r
+#define SPI_FIFOWR_EOT_MASK (0x100000U)\r
+#define SPI_FIFOWR_EOT_SHIFT (20U)\r
+/*! EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain\r
+ * so far at least the time specified by the Transfer_delay value in the DLY register.\r
+ * 0b0..SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.\r
+ * 0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.\r
+ */\r
+#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK)\r
+#define SPI_FIFOWR_EOF_MASK (0x200000U)\r
+#define SPI_FIFOWR_EOF_SHIFT (21U)\r
+/*! EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value\r
+ * in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay\r
+ * value = 0. This control can be used as part of the support for frame lengths greater than 16\r
+ * bits.\r
+ * 0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame.\r
+ * 0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be\r
+ * inserted before subsequent data is transmitted.\r
+ */\r
+#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK)\r
+#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U)\r
+#define SPI_FIFOWR_RXIGNORE_SHIFT (22U)\r
+/*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to\r
+ * read unneeded data from the receiver. Setting this bit simplifies the transmit process and can\r
+ * be used with the DMA.\r
+ * 0b0..Read received data. Received data must be read in order to allow transmission to progress. SPI transmit\r
+ * will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data\r
+ * is not read before new data is received.\r
+ * 0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received\r
+ * data. No receiver flags are generated.\r
+ */\r
+#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK)\r
+#define SPI_FIFOWR_LEN_MASK (0xF000000U)\r
+#define SPI_FIFOWR_LEN_SHIFT (24U)\r
+/*! LEN - Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths\r
+ * greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved.\r
+ * 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data\r
+ * transfer is 16 bits in length.\r
+ */\r
+#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFORD - FIFO read data. */\r
+/*! @{ */\r
+#define SPI_FIFORD_RXDATA_MASK (0xFFFFU)\r
+#define SPI_FIFORD_RXDATA_SHIFT (0U)\r
+/*! RXDATA - Received data from the FIFO.\r
+ */\r
+#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK)\r
+#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U)\r
+#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U)\r
+/*! RXSSEL0_N - Slave Select for receive. This field allows the state of the SSEL0 pin to be saved\r
+ * along with received data. The value will reflect the SSEL0 pin for both master and slave\r
+ * operation. A zero indicates that a slave select is active. The actual polarity of each slave select\r
+ * pin is configured by the related SPOL bit in CFG.\r
+ */\r
+#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK)\r
+#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U)\r
+#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U)\r
+/*! RXSSEL1_N - Slave Select for receive. This field allows the state of the SSEL1 pin to be saved\r
+ * along with received data. The value will reflect the SSEL1 pin for both master and slave\r
+ * operation. A zero indicates that a slave select is active. The actual polarity of each slave select\r
+ * pin is configured by the related SPOL bit in CFG.\r
+ */\r
+#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK)\r
+#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U)\r
+#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U)\r
+/*! RXSSEL2_N - Slave Select for receive. This field allows the state of the SSEL2 pin to be saved\r
+ * along with received data. The value will reflect the SSEL2 pin for both master and slave\r
+ * operation. A zero indicates that a slave select is active. The actual polarity of each slave select\r
+ * pin is configured by the related SPOL bit in CFG.\r
+ */\r
+#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK)\r
+#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U)\r
+#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U)\r
+/*! RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved\r
+ * along with received data. The value will reflect the SSEL3 pin for both master and slave\r
+ * operation. A zero indicates that a slave select is active. The actual polarity of each slave select\r
+ * pin is configured by the related SPOL bit in CFG.\r
+ */\r
+#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK)\r
+#define SPI_FIFORD_SOT_MASK (0x100000U)\r
+#define SPI_FIFORD_SOT_SHIFT (20U)\r
+/*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went\r
+ * from deasserted to asserted (i.e., any previous transfer has ended). This information can be\r
+ * used to identify the first piece of data in cases where the transfer length is greater than 16\r
+ * bits.\r
+ */\r
+#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */\r
+/*! @{ */\r
+#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU)\r
+#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U)\r
+/*! RXDATA - Received data from the FIFO.\r
+ */\r
+#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK)\r
+#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U)\r
+#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U)\r
+/*! RXSSEL0_N - Slave Select for receive.\r
+ */\r
+#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK)\r
+#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U)\r
+#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U)\r
+/*! RXSSEL1_N - Slave Select for receive.\r
+ */\r
+#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK)\r
+#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U)\r
+#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U)\r
+/*! RXSSEL2_N - Slave Select for receive.\r
+ */\r
+#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK)\r
+#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U)\r
+#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U)\r
+/*! RXSSEL3_N - Slave Select for receive.\r
+ */\r
+#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK)\r
+#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U)\r
+#define SPI_FIFORDNOPOP_SOT_SHIFT (20U)\r
+/*! SOT - Start of transfer flag.\r
+ */\r
+#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK)\r
+/*! @} */\r
+\r
+/*! @name ID - Peripheral identification register. */\r
+/*! @{ */\r
+#define SPI_ID_APERTURE_MASK (0xFFU)\r
+#define SPI_ID_APERTURE_SHIFT (0U)\r
+/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.\r
+ */\r
+#define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK)\r
+#define SPI_ID_MINOR_REV_MASK (0xF00U)\r
+#define SPI_ID_MINOR_REV_SHIFT (8U)\r
+/*! MINOR_REV - Minor revision of module implementation.\r
+ */\r
+#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK)\r
+#define SPI_ID_MAJOR_REV_MASK (0xF000U)\r
+#define SPI_ID_MAJOR_REV_SHIFT (12U)\r
+/*! MAJOR_REV - Major revision of module implementation.\r
+ */\r
+#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK)\r
+#define SPI_ID_ID_MASK (0xFFFF0000U)\r
+#define SPI_ID_ID_SHIFT (16U)\r
+/*! ID - Module identifier for the selected function.\r
+ */\r
+#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group SPI_Register_Masks */\r
+\r
+\r
+/* SPI - Peripheral instance base addresses */\r
+/** Peripheral SPI0 base address */\r
+#define SPI0_BASE (0x40086000u)\r
+/** Peripheral SPI0 base pointer */\r
+#define SPI0 ((SPI_Type *)SPI0_BASE)\r
+/** Peripheral SPI1 base address */\r
+#define SPI1_BASE (0x40087000u)\r
+/** Peripheral SPI1 base pointer */\r
+#define SPI1 ((SPI_Type *)SPI1_BASE)\r
+/** Peripheral SPI2 base address */\r
+#define SPI2_BASE (0x40088000u)\r
+/** Peripheral SPI2 base pointer */\r
+#define SPI2 ((SPI_Type *)SPI2_BASE)\r
+/** Peripheral SPI3 base address */\r
+#define SPI3_BASE (0x40089000u)\r
+/** Peripheral SPI3 base pointer */\r
+#define SPI3 ((SPI_Type *)SPI3_BASE)\r
+/** Peripheral SPI4 base address */\r
+#define SPI4_BASE (0x4008A000u)\r
+/** Peripheral SPI4 base pointer */\r
+#define SPI4 ((SPI_Type *)SPI4_BASE)\r
+/** Peripheral SPI5 base address */\r
+#define SPI5_BASE (0x40096000u)\r
+/** Peripheral SPI5 base pointer */\r
+#define SPI5 ((SPI_Type *)SPI5_BASE)\r
+/** Peripheral SPI6 base address */\r
+#define SPI6_BASE (0x40097000u)\r
+/** Peripheral SPI6 base pointer */\r
+#define SPI6 ((SPI_Type *)SPI6_BASE)\r
+/** Peripheral SPI7 base address */\r
+#define SPI7_BASE (0x40098000u)\r
+/** Peripheral SPI7 base pointer */\r
+#define SPI7 ((SPI_Type *)SPI7_BASE)\r
+/** Peripheral SPI8 base address */\r
+#define SPI8_BASE (0x40099000u)\r
+/** Peripheral SPI8 base pointer */\r
+#define SPI8 ((SPI_Type *)SPI8_BASE)\r
+/** Peripheral SPI9 base address */\r
+#define SPI9_BASE (0x4009A000u)\r
+/** Peripheral SPI9 base pointer */\r
+#define SPI9 ((SPI_Type *)SPI9_BASE)\r
+/** Peripheral SPI10 base address */\r
+#define SPI10_BASE (0x4009F000u)\r
+/** Peripheral SPI10 base pointer */\r
+#define SPI10 ((SPI_Type *)SPI10_BASE)\r
+/** Array initializer of SPI peripheral base addresses */\r
+#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE, SPI9_BASE, SPI10_BASE }\r
+/** Array initializer of SPI peripheral base pointers */\r
+#define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8, SPI9, SPI10 }\r
+/** Interrupt vectors for the SPI peripheral type */\r
+#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn, FLEXCOMM10_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group SPI_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SPIFI Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup SPIFI_Peripheral_Access_Layer SPIFI Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** SPIFI - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t CTRL; /**< SPIFI control register, offset: 0x0 */\r
+ __IO uint32_t CMD; /**< SPIFI command register, offset: 0x4 */\r
+ __IO uint32_t ADDR; /**< SPIFI address register, offset: 0x8 */\r
+ __IO uint32_t IDATA; /**< SPIFI intermediate data register, offset: 0xC */\r
+ __IO uint32_t CLIMIT; /**< SPIFI limit register, offset: 0x10 */\r
+ __IO uint32_t DATA; /**< SPIFI data register, offset: 0x14 */\r
+ __IO uint32_t MCMD; /**< SPIFI memory command register, offset: 0x18 */\r
+ __IO uint32_t STAT; /**< SPIFI status register, offset: 0x1C */\r
+} SPIFI_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SPIFI Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup SPIFI_Register_Masks SPIFI Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CTRL - SPIFI control register */\r
+/*! @{ */\r
+#define SPIFI_CTRL_TIMEOUT_MASK (0xFFFFU)\r
+#define SPIFI_CTRL_TIMEOUT_SHIFT (0U)\r
+/*! TIMEOUT - This field contains the number of serial clock periods without the processor reading\r
+ * data in memory mode, which will cause the SPIFI hardware to terminate the command by driving\r
+ * the CS pin high and negating the CMD bit in the Status register. (This allows the flash memory\r
+ * to enter a lower-power state.) If the processor reads data from the flash region after a\r
+ * time-out, the command in the Memory Command Register is issued again.\r
+ */\r
+#define SPIFI_CTRL_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_TIMEOUT_SHIFT)) & SPIFI_CTRL_TIMEOUT_MASK)\r
+#define SPIFI_CTRL_CSHIGH_MASK (0xF0000U)\r
+#define SPIFI_CTRL_CSHIGH_SHIFT (16U)\r
+/*! CSHIGH - This field controls the minimum CS high time, expressed as a number of serial clock periods minus one.\r
+ */\r
+#define SPIFI_CTRL_CSHIGH(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_CSHIGH_SHIFT)) & SPIFI_CTRL_CSHIGH_MASK)\r
+#define SPIFI_CTRL_D_PRFTCH_DIS_MASK (0x200000U)\r
+#define SPIFI_CTRL_D_PRFTCH_DIS_SHIFT (21U)\r
+/*! D_PRFTCH_DIS - This bit allows conditioning of memory mode prefetches based on the AHB HPROT\r
+ * (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt\r
+ * a speculative prefetch when it encounters data accesses.\r
+ */\r
+#define SPIFI_CTRL_D_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_D_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_D_PRFTCH_DIS_MASK)\r
+#define SPIFI_CTRL_INTEN_MASK (0x400000U)\r
+#define SPIFI_CTRL_INTEN_SHIFT (22U)\r
+/*! INTEN - If this bit is 1 when a command ends, the SPIFI will assert its interrupt request\r
+ * output. See INTRQ in the status register for further details.\r
+ */\r
+#define SPIFI_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_INTEN_SHIFT)) & SPIFI_CTRL_INTEN_MASK)\r
+#define SPIFI_CTRL_MODE3_MASK (0x800000U)\r
+#define SPIFI_CTRL_MODE3_SHIFT (23U)\r
+/*! MODE3 - SPI Mode 3 select.\r
+ * 0b0..SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit of each command is\r
+ * captured, and keeps it low while CS is HIGH.\r
+ * 0b1..SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of each command and while CS is\r
+ * HIGH, and drives it low after it drives CS LOW. (Known serial flash devices can handle either mode, but\r
+ * some devices may require a particular mode for proper operation.) MODE3, RFCLK, and FBCLK should not all be\r
+ * 1, because in this case there is no final falling edge on SCK on which to sample the last data bit of the\r
+ * frame.\r
+ */\r
+#define SPIFI_CTRL_MODE3(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_MODE3_SHIFT)) & SPIFI_CTRL_MODE3_MASK)\r
+#define SPIFI_CTRL_PRFTCH_DIS_MASK (0x8000000U)\r
+#define SPIFI_CTRL_PRFTCH_DIS_SHIFT (27U)\r
+/*! PRFTCH_DIS - Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines.\r
+ * 0b0..Enable. Cache prefetching enabled.\r
+ * 0b1..Disable. Disables prefetching of cache lines.\r
+ */\r
+#define SPIFI_CTRL_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_PRFTCH_DIS_MASK)\r
+#define SPIFI_CTRL_DUAL_MASK (0x10000000U)\r
+#define SPIFI_CTRL_DUAL_SHIFT (28U)\r
+/*! DUAL - Select dual protocol.\r
+ * 0b0..Quad protocol. This protocol uses IO3:0.\r
+ * 0b1..Dual protocol. This protocol uses IO1:0.\r
+ */\r
+#define SPIFI_CTRL_DUAL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DUAL_SHIFT)) & SPIFI_CTRL_DUAL_MASK)\r
+#define SPIFI_CTRL_RFCLK_MASK (0x20000000U)\r
+#define SPIFI_CTRL_RFCLK_SHIFT (29U)\r
+/*! RFCLK - Select active clock edge for input data.\r
+ * 0b0..Rising edge. Read data is sampled on rising edges on the clock, as in classic SPI operation.\r
+ * 0b1..Falling edge. Read data is sampled on falling edges of the clock, allowing a full serial clock of of time\r
+ * in order to maximize the serial clock frequency. MODE3, RFCLK, and FBCLK should not all be 1, because in\r
+ * this case there is no final falling edge on SCK on which to sample the last data bit of the frame.\r
+ */\r
+#define SPIFI_CTRL_RFCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_RFCLK_SHIFT)) & SPIFI_CTRL_RFCLK_MASK)\r
+#define SPIFI_CTRL_FBCLK_MASK (0x40000000U)\r
+#define SPIFI_CTRL_FBCLK_SHIFT (30U)\r
+/*! FBCLK - Feedback clock select.\r
+ * 0b0..Internal clock. The SPIFI samples read data using an internal clock.\r
+ * 0b1..Feedback clock. Read data is sampled using a feedback clock from the SCK pin. This allows slightly more\r
+ * time for each received bit. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no\r
+ * final falling edge on SCK on which to sample the last data bit of the frame.\r
+ */\r
+#define SPIFI_CTRL_FBCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_FBCLK_SHIFT)) & SPIFI_CTRL_FBCLK_MASK)\r
+#define SPIFI_CTRL_DMAEN_MASK (0x80000000U)\r
+#define SPIFI_CTRL_DMAEN_SHIFT (31U)\r
+/*! DMAEN - A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a\r
+ * DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA\r
+ * channel is used for memory-to-memory transfers from the SPIFI memory area. DMAEN should only be used\r
+ * in Command mode.\r
+ */\r
+#define SPIFI_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DMAEN_SHIFT)) & SPIFI_CTRL_DMAEN_MASK)\r
+/*! @} */\r
+\r
+/*! @name CMD - SPIFI command register */\r
+/*! @{ */\r
+#define SPIFI_CMD_DATALEN_MASK (0x3FFFU)\r
+#define SPIFI_CMD_DATALEN_SHIFT (0U)\r
+/*! DATALEN - Except when the POLL bit in this register is 1, this field controls how many data\r
+ * bytes are in the command. 0 indicates that the command does not contain a data field.\r
+ */\r
+#define SPIFI_CMD_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DATALEN_SHIFT)) & SPIFI_CMD_DATALEN_MASK)\r
+#define SPIFI_CMD_POLL_MASK (0x4000U)\r
+#define SPIFI_CMD_POLL_SHIFT (14U)\r
+/*! POLL - This bit should be written as 1 only with an opcode that a) contains an input data field,\r
+ * and b) causes the serial flash device to return byte status repetitively (e.g., a Read Status\r
+ * command). When this bit is 1, the SPIFI hardware continues to read bytes until the test\r
+ * specified by the DATALEN field is met. The hardware tests the bit in each status byte selected by\r
+ * DATALEN bits 2:0, until a bit is found that is equal to DATALEN bit 3. When the test succeeds,\r
+ * the SPIFI captures the byte that meets this test so that it can be read from the Data\r
+ * Register, and terminates the command by raising CS. The end-of-command interrupt can be enabled to\r
+ * inform software when this occurs\r
+ */\r
+#define SPIFI_CMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_POLL_SHIFT)) & SPIFI_CMD_POLL_MASK)\r
+#define SPIFI_CMD_DOUT_MASK (0x8000U)\r
+#define SPIFI_CMD_DOUT_SHIFT (15U)\r
+/*! DOUT - If the DATALEN field is not zero, this bit controls the direction of the data:\r
+ * 0b0..Input from serial flash.\r
+ * 0b1..Output to serial flash.\r
+ */\r
+#define SPIFI_CMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DOUT_SHIFT)) & SPIFI_CMD_DOUT_MASK)\r
+#define SPIFI_CMD_INTLEN_MASK (0x70000U)\r
+#define SPIFI_CMD_INTLEN_SHIFT (16U)\r
+/*! INTLEN - This field controls how many intermediate bytes precede the data. (Each such byte may\r
+ * require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or\r
+ * 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control\r
+ * information, dummy and delay bytes. See the description of the Intermediate Data register for\r
+ * the contents of such bytes.\r
+ */\r
+#define SPIFI_CMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_INTLEN_SHIFT)) & SPIFI_CMD_INTLEN_MASK)\r
+#define SPIFI_CMD_FIELDFORM_MASK (0x180000U)\r
+#define SPIFI_CMD_FIELDFORM_SHIFT (19U)\r
+/*! FIELDFORM - This field controls how the fields of the command are sent.\r
+ * 0b00..All serial. All fields of the command are serial.\r
+ * 0b01..Quad/dual data. Data field is quad/dual, other fields are serial.\r
+ * 0b10..Serial opcode. Opcode field is serial. Other fields are quad/dual.\r
+ * 0b11..All quad/dual. All fields of the command are in quad/dual format.\r
+ */\r
+#define SPIFI_CMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FIELDFORM_SHIFT)) & SPIFI_CMD_FIELDFORM_MASK)\r
+#define SPIFI_CMD_FRAMEFORM_MASK (0xE00000U)\r
+#define SPIFI_CMD_FRAMEFORM_SHIFT (21U)\r
+/*! FRAMEFORM - This field controls the opcode and address fields.\r
+ * 0b000..Reserved.\r
+ * 0b001..Opcode. Opcode only, no address.\r
+ * 0b010..Opcode one byte. Opcode, least significant byte of address.\r
+ * 0b011..Opcode two bytes. Opcode, two least significant bytes of address.\r
+ * 0b100..Opcode three bytes. Opcode, three least significant bytes of address.\r
+ * 0b101..Opcode four bytes. Opcode, 4 bytes of address.\r
+ * 0b110..No opcode three bytes. No opcode, 3 least significant bytes of address.\r
+ * 0b111..No opcode four bytes. No opcode, 4 bytes of address.\r
+ */\r
+#define SPIFI_CMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FRAMEFORM_SHIFT)) & SPIFI_CMD_FRAMEFORM_MASK)\r
+#define SPIFI_CMD_OPCODE_MASK (0xFF000000U)\r
+#define SPIFI_CMD_OPCODE_SHIFT (24U)\r
+/*! OPCODE - The opcode of the command (not used for some FRAMEFORM values).\r
+ */\r
+#define SPIFI_CMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_OPCODE_SHIFT)) & SPIFI_CMD_OPCODE_MASK)\r
+/*! @} */\r
+\r
+/*! @name ADDR - SPIFI address register */\r
+/*! @{ */\r
+#define SPIFI_ADDR_ADDRESS_MASK (0xFFFFFFFFU)\r
+#define SPIFI_ADDR_ADDRESS_SHIFT (0U)\r
+/*! ADDRESS - Address.\r
+ */\r
+#define SPIFI_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_ADDR_ADDRESS_SHIFT)) & SPIFI_ADDR_ADDRESS_MASK)\r
+/*! @} */\r
+\r
+/*! @name IDATA - SPIFI intermediate data register */\r
+/*! @{ */\r
+#define SPIFI_IDATA_IDATA_MASK (0xFFFFFFFFU)\r
+#define SPIFI_IDATA_IDATA_SHIFT (0U)\r
+/*! IDATA - Value of intermediate bytes.\r
+ */\r
+#define SPIFI_IDATA_IDATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_IDATA_IDATA_SHIFT)) & SPIFI_IDATA_IDATA_MASK)\r
+/*! @} */\r
+\r
+/*! @name CLIMIT - SPIFI limit register */\r
+/*! @{ */\r
+#define SPIFI_CLIMIT_CLIMIT_MASK (0xFFFFFFFFU)\r
+#define SPIFI_CLIMIT_CLIMIT_SHIFT (0U)\r
+/*! CLIMIT - Zero-based upper limit of cacheable memory\r
+ */\r
+#define SPIFI_CLIMIT_CLIMIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CLIMIT_CLIMIT_SHIFT)) & SPIFI_CLIMIT_CLIMIT_MASK)\r
+/*! @} */\r
+\r
+/*! @name DATA - SPIFI data register */\r
+/*! @{ */\r
+#define SPIFI_DATA_DATA_MASK (0xFFFFFFFFU)\r
+#define SPIFI_DATA_DATA_SHIFT (0U)\r
+/*! DATA - Input or output data\r
+ */\r
+#define SPIFI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_DATA_DATA_SHIFT)) & SPIFI_DATA_DATA_MASK)\r
+/*! @} */\r
+\r
+/*! @name MCMD - SPIFI memory command register */\r
+/*! @{ */\r
+#define SPIFI_MCMD_POLL_MASK (0x4000U)\r
+#define SPIFI_MCMD_POLL_SHIFT (14U)\r
+/*! POLL - This bit should be written as 0.\r
+ */\r
+#define SPIFI_MCMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_POLL_SHIFT)) & SPIFI_MCMD_POLL_MASK)\r
+#define SPIFI_MCMD_DOUT_MASK (0x8000U)\r
+#define SPIFI_MCMD_DOUT_SHIFT (15U)\r
+/*! DOUT - This bit should be written as 0.\r
+ */\r
+#define SPIFI_MCMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_DOUT_SHIFT)) & SPIFI_MCMD_DOUT_MASK)\r
+#define SPIFI_MCMD_INTLEN_MASK (0x70000U)\r
+#define SPIFI_MCMD_INTLEN_SHIFT (16U)\r
+/*! INTLEN - This field controls how many intermediate bytes precede the data. (Each such byte may\r
+ * require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or\r
+ * 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control\r
+ * information, dummy and delay bytes. See the description of the Intermediate Data register for\r
+ * the contents of such bytes.\r
+ */\r
+#define SPIFI_MCMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_INTLEN_SHIFT)) & SPIFI_MCMD_INTLEN_MASK)\r
+#define SPIFI_MCMD_FIELDFORM_MASK (0x180000U)\r
+#define SPIFI_MCMD_FIELDFORM_SHIFT (19U)\r
+/*! FIELDFORM - This field controls how the fields of the command are sent.\r
+ * 0b00..All serial. All fields of the command are serial.\r
+ * 0b01..Quad/dual data. Data field is quad/dual, other fields are serial.\r
+ * 0b10..Serial opcode. Opcode field is serial. Other fields are quad/dual.\r
+ * 0b11..All quad/dual. All fields of the command are in quad/dual format.\r
+ */\r
+#define SPIFI_MCMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FIELDFORM_SHIFT)) & SPIFI_MCMD_FIELDFORM_MASK)\r
+#define SPIFI_MCMD_FRAMEFORM_MASK (0xE00000U)\r
+#define SPIFI_MCMD_FRAMEFORM_SHIFT (21U)\r
+/*! FRAMEFORM - This field controls the opcode and address fields.\r
+ * 0b000..Reserved.\r
+ * 0b001..Opcode. Opcode only, no address.\r
+ * 0b010..Opcode one byte. Opcode, least-significant byte of address.\r
+ * 0b011..Opcode two bytes. Opcode, 2 least-significant bytes of address.\r
+ * 0b100..Opcode three bytes. Opcode, 3 least-significant bytes of address.\r
+ * 0b101..Opcode four bytes. Opcode, 4 bytes of address.\r
+ * 0b110..No opcode three bytes. No opcode, 3 least-significant bytes of address.\r
+ * 0b111..No opcode, 4 bytes of address.\r
+ */\r
+#define SPIFI_MCMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FRAMEFORM_SHIFT)) & SPIFI_MCMD_FRAMEFORM_MASK)\r
+#define SPIFI_MCMD_OPCODE_MASK (0xFF000000U)\r
+#define SPIFI_MCMD_OPCODE_SHIFT (24U)\r
+/*! OPCODE - The opcode of the command (not used for some FRAMEFORM values).\r
+ */\r
+#define SPIFI_MCMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_OPCODE_SHIFT)) & SPIFI_MCMD_OPCODE_MASK)\r
+/*! @} */\r
+\r
+/*! @name STAT - SPIFI status register */\r
+/*! @{ */\r
+#define SPIFI_STAT_MCINIT_MASK (0x1U)\r
+#define SPIFI_STAT_MCINIT_SHIFT (0U)\r
+/*! MCINIT - This bit is set when software successfully writes the Memory Command register, and is\r
+ * cleared by Reset or by writing a 1 to the RESET bit in this register.\r
+ */\r
+#define SPIFI_STAT_MCINIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_MCINIT_SHIFT)) & SPIFI_STAT_MCINIT_MASK)\r
+#define SPIFI_STAT_CMD_MASK (0x2U)\r
+#define SPIFI_STAT_CMD_SHIFT (1U)\r
+/*! CMD - This bit is 1 when the Command register is written. It is cleared by a hardware reset, a\r
+ * write to the RESET bit in this register, or the deassertion of CS which indicates that the\r
+ * command has completed communication with the SPI Flash.\r
+ */\r
+#define SPIFI_STAT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_CMD_SHIFT)) & SPIFI_STAT_CMD_MASK)\r
+#define SPIFI_STAT_RESET_MASK (0x10U)\r
+#define SPIFI_STAT_RESET_SHIFT (4U)\r
+/*! RESET - Write a 1 to this bit to abort a current command or memory mode. This bit is cleared\r
+ * when the hardware is ready for a new command to be written to the Command register.\r
+ */\r
+#define SPIFI_STAT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_RESET_SHIFT)) & SPIFI_STAT_RESET_MASK)\r
+#define SPIFI_STAT_INTRQ_MASK (0x20U)\r
+#define SPIFI_STAT_INTRQ_SHIFT (5U)\r
+/*! INTRQ - This bit reflects the SPIFI interrupt request. Write a 1 to this bit to clear it. This\r
+ * bit is set when a CMD was previously 1 and has been cleared due to the deassertion of CS.\r
+ */\r
+#define SPIFI_STAT_INTRQ(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_INTRQ_SHIFT)) & SPIFI_STAT_INTRQ_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group SPIFI_Register_Masks */\r
+\r
+\r
+/* SPIFI - Peripheral instance base addresses */\r
+/** Peripheral SPIFI0 base address */\r
+#define SPIFI0_BASE (0x40080000u)\r
+/** Peripheral SPIFI0 base pointer */\r
+#define SPIFI0 ((SPIFI_Type *)SPIFI0_BASE)\r
+/** Array initializer of SPIFI peripheral base addresses */\r
+#define SPIFI_BASE_ADDRS { SPIFI0_BASE }\r
+/** Array initializer of SPIFI peripheral base pointers */\r
+#define SPIFI_BASE_PTRS { SPIFI0 }\r
+/** Interrupt vectors for the SPIFI peripheral type */\r
+#define SPIFI_IRQS { SPIFI0_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group SPIFI_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SYSCON Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** SYSCON - Register Layout Typedef */\r
+typedef struct {\r
+ uint8_t RESERVED_0[16];\r
+ __IO uint32_t AHBMATPRIO; /**< AHB multilayer matrix priority control, offset: 0x10 */\r
+ uint8_t RESERVED_1[44];\r
+ __IO uint32_t SYSTCKCAL; /**< System tick counter calibration, offset: 0x40 */\r
+ uint8_t RESERVED_2[4];\r
+ __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */\r
+ __IO uint32_t ASYNCAPBCTRL; /**< Asynchronous APB Control, offset: 0x4C */\r
+ uint8_t RESERVED_3[112];\r
+ __I uint32_t PIOPORCAP[2]; /**< POR captured value of port n, array offset: 0xC0, array step: 0x4 */\r
+ uint8_t RESERVED_4[8];\r
+ __I uint32_t PIORESCAP[2]; /**< Reset captured value of port n, array offset: 0xD0, array step: 0x4 */\r
+ uint8_t RESERVED_5[40];\r
+ __IO uint32_t PRESETCTRL[3]; /**< Peripheral reset control n, array offset: 0x100, array step: 0x4 */\r
+ uint8_t RESERVED_6[20];\r
+ __O uint32_t PRESETCTRLSET[3]; /**< Set bits in PRESETCTRLn, array offset: 0x120, array step: 0x4 */\r
+ uint8_t RESERVED_7[20];\r
+ __O uint32_t PRESETCTRLCLR[3]; /**< Clear bits in PRESETCTRLn, array offset: 0x140, array step: 0x4 */\r
+ uint8_t RESERVED_8[164];\r
+ __IO uint32_t SYSRSTSTAT; /**< System reset status register, offset: 0x1F0 */\r
+ uint8_t RESERVED_9[12];\r
+ __IO uint32_t AHBCLKCTRL[3]; /**< AHB Clock control n, array offset: 0x200, array step: 0x4 */\r
+ uint8_t RESERVED_10[20];\r
+ __O uint32_t AHBCLKCTRLSET[3]; /**< Set bits in AHBCLKCTRLn, array offset: 0x220, array step: 0x4 */\r
+ uint8_t RESERVED_11[20];\r
+ __O uint32_t AHBCLKCTRLCLR[3]; /**< Clear bits in AHBCLKCTRLn, array offset: 0x240, array step: 0x4 */\r
+ uint8_t RESERVED_12[48];\r
+ __IO uint32_t STICKCLKSEL; /**< Systick timer clock source selection, offset: 0x27C */\r
+ __IO uint32_t MAINCLKSELA; /**< Main clock source select A, offset: 0x280 */\r
+ __IO uint32_t MAINCLKSELB; /**< Main clock source select B, offset: 0x284 */\r
+ __IO uint32_t CLKOUTSELA; /**< CLKOUT clock source select A, offset: 0x288 */\r
+ uint8_t RESERVED_13[4];\r
+ __IO uint32_t SYSPLLCLKSEL; /**< PLL clock source select, offset: 0x290 */\r
+ uint8_t RESERVED_14[4];\r
+ __IO uint32_t AUDPLLCLKSEL; /**< Audio PLL clock source select, offset: 0x298 */\r
+ uint8_t RESERVED_15[4];\r
+ __IO uint32_t SPIFICLKSEL; /**< SPIFI clock source select, offset: 0x2A0 */\r
+ __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */\r
+ __IO uint32_t USB0CLKSEL; /**< USB0 clock source select, offset: 0x2A8 */\r
+ __IO uint32_t USB1CLKSEL; /**< USB1 clock source select, offset: 0x2AC */\r
+ __IO uint32_t FCLKSEL[10]; /**< Flexcomm clock source select, array offset: 0x2B0, array step: 0x4 */\r
+ __IO uint32_t FCLKSEL10; /**< Flexcomm 10 clock source select, offset: 0x2D8 */\r
+ uint8_t RESERVED_16[4];\r
+ __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */\r
+ uint8_t RESERVED_17[4];\r
+ __IO uint32_t FRGCLKSEL; /**< Fractional Rate Generator clock source select, offset: 0x2E8 */\r
+ __IO uint32_t DMICCLKSEL; /**< Digital microphone (DMIC) subsystem clock select, offset: 0x2EC */\r
+ __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */\r
+ __IO uint32_t LCDCLKSEL; /**< LCD clock source select, offset: 0x2F4 */\r
+ __IO uint32_t SDIOCLKSEL; /**< SDIO clock source select, offset: 0x2F8 */\r
+ uint8_t RESERVED_18[4];\r
+ __IO uint32_t SYSTICKCLKDIV; /**< SYSTICK clock divider, offset: 0x300 */\r
+ __IO uint32_t ARMTRACECLKDIV; /**< ARM Trace clock divider, offset: 0x304 */\r
+ __IO uint32_t CAN0CLKDIV; /**< MCAN0 clock divider, offset: 0x308 */\r
+ __IO uint32_t CAN1CLKDIV; /**< MCAN1 clock divider, offset: 0x30C */\r
+ __IO uint32_t SC0CLKDIV; /**< Smartcard0 clock divider, offset: 0x310 */\r
+ __IO uint32_t SC1CLKDIV; /**< Smartcard1 clock divider, offset: 0x314 */\r
+ uint8_t RESERVED_19[104];\r
+ __IO uint32_t AHBCLKDIV; /**< AHB clock divider, offset: 0x380 */\r
+ __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */\r
+ __IO uint32_t FROHFDIV; /**< FROHF clock divider, offset: 0x388 */\r
+ uint8_t RESERVED_20[4];\r
+ __IO uint32_t SPIFICLKDIV; /**< SPIFI clock divider, offset: 0x390 */\r
+ __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */\r
+ __IO uint32_t USB0CLKDIV; /**< USB0 clock divider, offset: 0x398 */\r
+ __IO uint32_t USB1CLKDIV; /**< USB1 clock divider, offset: 0x39C */\r
+ __IO uint32_t FRGCTRL; /**< Fractional rate divider, offset: 0x3A0 */\r
+ uint8_t RESERVED_21[4];\r
+ __IO uint32_t DMICCLKDIV; /**< DMIC clock divider, offset: 0x3A8 */\r
+ __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */\r
+ __IO uint32_t LCDCLKDIV; /**< LCD clock divider, offset: 0x3B0 */\r
+ __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */\r
+ __IO uint32_t EMCCLKDIV; /**< EMC clock divider, offset: 0x3B8 */\r
+ __IO uint32_t SDIOCLKDIV; /**< SDIO clock divider, offset: 0x3BC */\r
+ uint8_t RESERVED_22[76];\r
+ __IO uint32_t USB0CLKCTRL; /**< USB0 clock control, offset: 0x40C */\r
+ __IO uint32_t USB0CLKSTAT; /**< USB0 clock status, offset: 0x410 */\r
+ uint8_t RESERVED_23[4];\r
+ __IO uint32_t FREQMECTRL; /**< Frequency measure register, offset: 0x418 */\r
+ uint8_t RESERVED_24[4];\r
+ __IO uint32_t MCLKIO; /**< MCLK input/output control, offset: 0x420 */\r
+ __IO uint32_t USB1CLKCTRL; /**< USB1 clock control, offset: 0x424 */\r
+ __IO uint32_t USB1CLKSTAT; /**< USB1 clock status, offset: 0x428 */\r
+ uint8_t RESERVED_25[24];\r
+ __IO uint32_t EMCSYSCTRL; /**< EMC system control, offset: 0x444 */\r
+ __IO uint32_t EMCDYCTRL; /**< EMC clock delay control, offset: 0x448 */\r
+ __IO uint32_t EMCCAL; /**< EMC delay chain calibration control, offset: 0x44C */\r
+ __IO uint32_t ETHPHYSEL; /**< Ethernet PHY Selection, offset: 0x450 */\r
+ __IO uint32_t ETHSBDCTRL; /**< Ethernet SBD flow control, offset: 0x454 */\r
+ uint8_t RESERVED_26[8];\r
+ __IO uint32_t SDIOCLKCTRL; /**< SDIO CCLKIN phase and delay control, offset: 0x460 */\r
+ uint8_t RESERVED_27[12];\r
+ __IO uint32_t KEYMUXSEL; /**< AES key source selection, offset: 0x470 */\r
+ uint8_t RESERVED_28[140];\r
+ __IO uint32_t FROCTRL; /**< FRO oscillator control, offset: 0x500 */\r
+ __IO uint32_t SYSOSCCTRL; /**< System oscillator control, offset: 0x504 */\r
+ __IO uint32_t WDTOSCCTRL; /**< Watchdog oscillator control, offset: 0x508 */\r
+ __IO uint32_t RTCOSCCTRL; /**< RTC oscillator 32 kHz output control, offset: 0x50C */\r
+ uint8_t RESERVED_29[12];\r
+ __IO uint32_t USBPLLCTRL; /**< USB PLL control, offset: 0x51C */\r
+ __IO uint32_t USBPLLSTAT; /**< USB PLL status, offset: 0x520 */\r
+ uint8_t RESERVED_30[92];\r
+ __IO uint32_t SYSPLLCTRL; /**< System PLL control, offset: 0x580 */\r
+ __IO uint32_t SYSPLLSTAT; /**< PLL status, offset: 0x584 */\r
+ __IO uint32_t SYSPLLNDEC; /**< PLL N divider, offset: 0x588 */\r
+ __IO uint32_t SYSPLLPDEC; /**< PLL P divider, offset: 0x58C */\r
+ __IO uint32_t SYSPLLMDEC; /**< System PLL M divider, offset: 0x590 */\r
+ uint8_t RESERVED_31[12];\r
+ __IO uint32_t AUDPLLCTRL; /**< Audio PLL control, offset: 0x5A0 */\r
+ __IO uint32_t AUDPLLSTAT; /**< Audio PLL status, offset: 0x5A4 */\r
+ __IO uint32_t AUDPLLNDEC; /**< Audio PLL N divider, offset: 0x5A8 */\r
+ __IO uint32_t AUDPLLPDEC; /**< Audio PLL P divider, offset: 0x5AC */\r
+ __IO uint32_t AUDPLLMDEC; /**< Audio PLL M divider, offset: 0x5B0 */\r
+ __IO uint32_t AUDPLLFRAC; /**< Audio PLL fractional divider control, offset: 0x5B4 */\r
+ uint8_t RESERVED_32[72];\r
+ __IO uint32_t PDSLEEPCFG[2]; /**< Sleep configuration register, array offset: 0x600, array step: 0x4 */\r
+ uint8_t RESERVED_33[8];\r
+ __IO uint32_t PDRUNCFG[2]; /**< Power configuration register, array offset: 0x610, array step: 0x4 */\r
+ uint8_t RESERVED_34[8];\r
+ __IO uint32_t PDRUNCFGSET[2]; /**< Power configuration set register, array offset: 0x620, array step: 0x4 */\r
+ uint8_t RESERVED_35[8];\r
+ __IO uint32_t PDRUNCFGCLR[2]; /**< Power configuration clear register, array offset: 0x630, array step: 0x4 */\r
+ uint8_t RESERVED_36[72];\r
+ __IO uint32_t STARTER[2]; /**< Start logic 0 wake-up enable register, array offset: 0x680, array step: 0x4 */\r
+ uint8_t RESERVED_37[24];\r
+ __O uint32_t STARTERSET[2]; /**< Set bits in STARTER, array offset: 0x6A0, array step: 0x4 */\r
+ uint8_t RESERVED_38[24];\r
+ __O uint32_t STARTERCLR[2]; /**< Clear bits in STARTER0, array offset: 0x6C0, array step: 0x4 */\r
+ uint8_t RESERVED_39[184];\r
+ __IO uint32_t HWWAKE; /**< Configures special cases of hardware wake-up, offset: 0x780 */\r
+ uint8_t RESERVED_40[1664];\r
+ __IO uint32_t AUTOCGOR; /**< Auto Clock-Gate Override Register, offset: 0xE04 */\r
+ uint8_t RESERVED_41[492];\r
+ __I uint32_t JTAGIDCODE; /**< JTAG ID code register, offset: 0xFF4 */\r
+ __I uint32_t DEVICE_ID0; /**< Part ID register, offset: 0xFF8 */\r
+ __I uint32_t DEVICE_ID1; /**< Boot ROM and die revision register, offset: 0xFFC */\r
+ uint8_t RESERVED_42[127044];\r
+ __IO uint32_t BODCTRL; /**< Brown-Out Detect control, offset: 0x20044 */\r
+} SYSCON_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SYSCON Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup SYSCON_Register_Masks SYSCON Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name AHBMATPRIO - AHB multilayer matrix priority control */\r
+/*! @{ */\r
+#define SYSCON_AHBMATPRIO_PRI_ICODE_MASK (0x3U)\r
+#define SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT (0U)\r
+/*! PRI_ICODE - I-Code bus priority.\r
+ */\r
+#define SYSCON_AHBMATPRIO_PRI_ICODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ICODE_MASK)\r
+#define SYSCON_AHBMATPRIO_PRI_DCODE_MASK (0xCU)\r
+#define SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT (2U)\r
+/*! PRI_DCODE - D-Code bus priority.\r
+ */\r
+#define SYSCON_AHBMATPRIO_PRI_DCODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DCODE_MASK)\r
+#define SYSCON_AHBMATPRIO_PRI_SYS_MASK (0x30U)\r
+#define SYSCON_AHBMATPRIO_PRI_SYS_SHIFT (4U)\r
+/*! PRI_SYS - System bus priority.\r
+ */\r
+#define SYSCON_AHBMATPRIO_PRI_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SYS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SYS_MASK)\r
+#define SYSCON_AHBMATPRIO_PRI_DMA_MASK (0xC0U)\r
+#define SYSCON_AHBMATPRIO_PRI_DMA_SHIFT (6U)\r
+/*! PRI_DMA - DMA controller priority.\r
+ */\r
+#define SYSCON_AHBMATPRIO_PRI_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DMA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DMA_MASK)\r
+#define SYSCON_AHBMATPRIO_PRI_ETH_MASK (0x300U)\r
+#define SYSCON_AHBMATPRIO_PRI_ETH_SHIFT (8U)\r
+/*! PRI_ETH - Ethernet DMA priority.\r
+ */\r
+#define SYSCON_AHBMATPRIO_PRI_ETH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ETH_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ETH_MASK)\r
+#define SYSCON_AHBMATPRIO_PRI_LCD_MASK (0xC00U)\r
+#define SYSCON_AHBMATPRIO_PRI_LCD_SHIFT (10U)\r
+/*! PRI_LCD - LCD DMA priority.\r
+ */\r
+#define SYSCON_AHBMATPRIO_PRI_LCD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_LCD_SHIFT)) & SYSCON_AHBMATPRIO_PRI_LCD_MASK)\r
+#define SYSCON_AHBMATPRIO_PRI_USB0_MASK (0x3000U)\r
+#define SYSCON_AHBMATPRIO_PRI_USB0_SHIFT (12U)\r
+/*! PRI_USB0 - USB0 DMA priority.\r
+ */\r
+#define SYSCON_AHBMATPRIO_PRI_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB0_MASK)\r
+#define SYSCON_AHBMATPRIO_PRI_USB1_MASK (0xC000U)\r
+#define SYSCON_AHBMATPRIO_PRI_USB1_SHIFT (14U)\r
+/*! PRI_USB1 - USB1 DMA priority.\r
+ */\r
+#define SYSCON_AHBMATPRIO_PRI_USB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB1_MASK)\r
+#define SYSCON_AHBMATPRIO_PRI_SDIO_MASK (0x30000U)\r
+#define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT (16U)\r
+/*! PRI_SDIO - SDIO priority.\r
+ */\r
+#define SYSCON_AHBMATPRIO_PRI_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK)\r
+#define SYSCON_AHBMATPRIO_PRI_MCAN1_MASK (0xC0000U)\r
+#define SYSCON_AHBMATPRIO_PRI_MCAN1_SHIFT (18U)\r
+/*! PRI_MCAN1 - MCAN1 priority.\r
+ */\r
+#define SYSCON_AHBMATPRIO_PRI_MCAN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN1_MASK)\r
+#define SYSCON_AHBMATPRIO_PRI_MCAN2_MASK (0x300000U)\r
+#define SYSCON_AHBMATPRIO_PRI_MCAN2_SHIFT (20U)\r
+/*! PRI_MCAN2 - MCAN2 priority.\r
+ */\r
+#define SYSCON_AHBMATPRIO_PRI_MCAN2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN2_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN2_MASK)\r
+/*! @} */\r
+\r
+/*! @name SYSTCKCAL - System tick counter calibration */\r
+/*! @{ */\r
+#define SYSCON_SYSTCKCAL_CAL_MASK (0xFFFFFFU)\r
+#define SYSCON_SYSTCKCAL_CAL_SHIFT (0U)\r
+/*! CAL - System tick timer calibration value.\r
+ */\r
+#define SYSCON_SYSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_CAL_SHIFT)) & SYSCON_SYSTCKCAL_CAL_MASK)\r
+#define SYSCON_SYSTCKCAL_SKEW_MASK (0x1000000U)\r
+#define SYSCON_SYSTCKCAL_SKEW_SHIFT (24U)\r
+/*! SKEW - Initial value for the Systick timer.\r
+ */\r
+#define SYSCON_SYSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_SKEW_SHIFT)) & SYSCON_SYSTCKCAL_SKEW_MASK)\r
+#define SYSCON_SYSTCKCAL_NOREF_MASK (0x2000000U)\r
+#define SYSCON_SYSTCKCAL_NOREF_SHIFT (25U)\r
+/*! NOREF - Initial value for the Systick timer.\r
+ */\r
+#define SYSCON_SYSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_NOREF_SHIFT)) & SYSCON_SYSTCKCAL_NOREF_MASK)\r
+/*! @} */\r
+\r
+/*! @name NMISRC - NMI Source Select */\r
+/*! @{ */\r
+#define SYSCON_NMISRC_IRQM4_MASK (0x3FU)\r
+#define SYSCON_NMISRC_IRQM4_SHIFT (0U)\r
+/*! IRQM4 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M4, if enabled by NMIENM4.\r
+ */\r
+#define SYSCON_NMISRC_IRQM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM4_SHIFT)) & SYSCON_NMISRC_IRQM4_MASK)\r
+#define SYSCON_NMISRC_NMIENM4_MASK (0x80000000U)\r
+#define SYSCON_NMISRC_NMIENM4_SHIFT (31U)\r
+/*! NMIENM4 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM4.\r
+ */\r
+#define SYSCON_NMISRC_NMIENM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM4_SHIFT)) & SYSCON_NMISRC_NMIENM4_MASK)\r
+/*! @} */\r
+\r
+/*! @name ASYNCAPBCTRL - Asynchronous APB Control */\r
+/*! @{ */\r
+#define SYSCON_ASYNCAPBCTRL_ENABLE_MASK (0x1U)\r
+#define SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT (0U)\r
+/*! ENABLE - Enables the asynchronous APB bridge and subsystem.\r
+ * 0b0..Disabled. Asynchronous APB bridge is disabled.\r
+ * 0b1..Enabled. Asynchronous APB bridge is enabled.\r
+ */\r
+#define SYSCON_ASYNCAPBCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT)) & SYSCON_ASYNCAPBCTRL_ENABLE_MASK)\r
+/*! @} */\r
+\r
+/*! @name PIOPORCAP - POR captured value of port n */\r
+/*! @{ */\r
+#define SYSCON_PIOPORCAP_PIOPORCAP_MASK (0xFFFFFFFFU)\r
+#define SYSCON_PIOPORCAP_PIOPORCAP_SHIFT (0U)\r
+/*! PIOPORCAP - State of PIOn_31 through PIOn_0 at power-on reset\r
+ */\r
+#define SYSCON_PIOPORCAP_PIOPORCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIOPORCAP_PIOPORCAP_SHIFT)) & SYSCON_PIOPORCAP_PIOPORCAP_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_PIOPORCAP */\r
+#define SYSCON_PIOPORCAP_COUNT (2U)\r
+\r
+/*! @name PIORESCAP - Reset captured value of port n */\r
+/*! @{ */\r
+#define SYSCON_PIORESCAP_PIORESCAP_MASK (0xFFFFFFFFU)\r
+#define SYSCON_PIORESCAP_PIORESCAP_SHIFT (0U)\r
+/*! PIORESCAP - State of PIOn_31 through PIOn_0 for resets other than POR.\r
+ */\r
+#define SYSCON_PIORESCAP_PIORESCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIORESCAP_PIORESCAP_SHIFT)) & SYSCON_PIORESCAP_PIORESCAP_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_PIORESCAP */\r
+#define SYSCON_PIORESCAP_COUNT (2U)\r
+\r
+/*! @name PRESETCTRL - Peripheral reset control n */\r
+/*! @{ */\r
+#define SYSCON_PRESETCTRL_MRT_RST_MASK (0x1U)\r
+#define SYSCON_PRESETCTRL_MRT_RST_SHIFT (0U)\r
+/*! MRT_RST - Multi-rate timer (MRT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.\r
+ */\r
+#define SYSCON_PRESETCTRL_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL_MRT_RST_MASK)\r
+#define SYSCON_PRESETCTRL_LCD_RST_MASK (0x4U)\r
+#define SYSCON_PRESETCTRL_LCD_RST_SHIFT (2U)\r
+/*! LCD_RST - LCD reset control.\r
+ */\r
+#define SYSCON_PRESETCTRL_LCD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_LCD_RST_SHIFT)) & SYSCON_PRESETCTRL_LCD_RST_MASK)\r
+#define SYSCON_PRESETCTRL_SCT0_RST_MASK (0x4U)\r
+#define SYSCON_PRESETCTRL_SCT0_RST_SHIFT (2U)\r
+/*! SCT0_RST - State configurable timer 0 (SCT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.\r
+ */\r
+#define SYSCON_PRESETCTRL_SCT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL_SCT0_RST_MASK)\r
+#define SYSCON_PRESETCTRL_SDIO_RST_MASK (0x8U)\r
+#define SYSCON_PRESETCTRL_SDIO_RST_SHIFT (3U)\r
+/*! SDIO_RST - SDIO reset control.\r
+ */\r
+#define SYSCON_PRESETCTRL_SDIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL_SDIO_RST_MASK)\r
+#define SYSCON_PRESETCTRL_USB1H_RST_MASK (0x10U)\r
+#define SYSCON_PRESETCTRL_USB1H_RST_SHIFT (4U)\r
+/*! USB1H_RST - USB1 Host reset control.\r
+ */\r
+#define SYSCON_PRESETCTRL_USB1H_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1H_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1H_RST_MASK)\r
+#define SYSCON_PRESETCTRL_USB1D_RST_MASK (0x20U)\r
+#define SYSCON_PRESETCTRL_USB1D_RST_SHIFT (5U)\r
+/*! USB1D_RST - USB1 Device reset control.\r
+ */\r
+#define SYSCON_PRESETCTRL_USB1D_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1D_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1D_RST_MASK)\r
+#define SYSCON_PRESETCTRL_USB1RAM_RST_MASK (0x40U)\r
+#define SYSCON_PRESETCTRL_USB1RAM_RST_SHIFT (6U)\r
+/*! USB1RAM_RST - USB1 RAM reset control.\r
+ */\r
+#define SYSCON_PRESETCTRL_USB1RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1RAM_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1RAM_RST_MASK)\r
+#define SYSCON_PRESETCTRL_EMC_RESET_MASK (0x80U)\r
+#define SYSCON_PRESETCTRL_EMC_RESET_SHIFT (7U)\r
+/*! EMC_RESET - EMC reset control.\r
+ */\r
+#define SYSCON_PRESETCTRL_EMC_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_EMC_RESET_SHIFT)) & SYSCON_PRESETCTRL_EMC_RESET_MASK)\r
+#define SYSCON_PRESETCTRL_MCAN0_RST_MASK (0x80U)\r
+#define SYSCON_PRESETCTRL_MCAN0_RST_SHIFT (7U)\r
+/*! MCAN0_RST - 0 = Clear reset to this function.\r
+ */\r
+#define SYSCON_PRESETCTRL_MCAN0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MCAN0_RST_SHIFT)) & SYSCON_PRESETCTRL_MCAN0_RST_MASK)\r
+#define SYSCON_PRESETCTRL_ETH_RST_MASK (0x100U)\r
+#define SYSCON_PRESETCTRL_ETH_RST_SHIFT (8U)\r
+/*! ETH_RST - Ethernet reset control.\r
+ */\r
+#define SYSCON_PRESETCTRL_ETH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ETH_RST_SHIFT)) & SYSCON_PRESETCTRL_ETH_RST_MASK)\r
+#define SYSCON_PRESETCTRL_MCAN1_RST_MASK (0x100U)\r
+#define SYSCON_PRESETCTRL_MCAN1_RST_SHIFT (8U)\r
+/*! MCAN1_RST - 0 = Clear reset to this function.\r
+ */\r
+#define SYSCON_PRESETCTRL_MCAN1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MCAN1_RST_SHIFT)) & SYSCON_PRESETCTRL_MCAN1_RST_MASK)\r
+#define SYSCON_PRESETCTRL_GPIO4_RST_MASK (0x200U)\r
+#define SYSCON_PRESETCTRL_GPIO4_RST_SHIFT (9U)\r
+/*! GPIO4_RST - GPIO4 reset control.\r
+ */\r
+#define SYSCON_PRESETCTRL_GPIO4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO4_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO4_RST_MASK)\r
+#define SYSCON_PRESETCTRL_GPIO5_RST_MASK (0x400U)\r
+#define SYSCON_PRESETCTRL_GPIO5_RST_SHIFT (10U)\r
+/*! GPIO5_RST - GPIO5 reset control.\r
+ */\r
+#define SYSCON_PRESETCTRL_GPIO5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO5_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO5_RST_MASK)\r
+#define SYSCON_PRESETCTRL_SPIFI_RST_MASK (0x400U)\r
+#define SYSCON_PRESETCTRL_SPIFI_RST_SHIFT (10U)\r
+/*! SPIFI_RST - SPIFI reset control.\r
+ */\r
+#define SYSCON_PRESETCTRL_SPIFI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SPIFI_RST_SHIFT)) & SYSCON_PRESETCTRL_SPIFI_RST_MASK)\r
+#define SYSCON_PRESETCTRL_UTICK_RST_MASK (0x400U)\r
+#define SYSCON_PRESETCTRL_UTICK_RST_SHIFT (10U)\r
+/*! UTICK_RST - Micro-tick Timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.\r
+ */\r
+#define SYSCON_PRESETCTRL_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL_UTICK_RST_MASK)\r
+#define SYSCON_PRESETCTRL_FC0_RST_MASK (0x800U)\r
+#define SYSCON_PRESETCTRL_FC0_RST_SHIFT (11U)\r
+/*! FC0_RST - Flexcomm 0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.\r
+ */\r
+#define SYSCON_PRESETCTRL_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL_FC0_RST_MASK)\r
+#define SYSCON_PRESETCTRL_MUX_RST_MASK (0x800U)\r
+#define SYSCON_PRESETCTRL_MUX_RST_SHIFT (11U)\r
+/*! MUX_RST - Input mux reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.\r
+ */\r
+#define SYSCON_PRESETCTRL_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL_MUX_RST_MASK)\r
+#define SYSCON_PRESETCTRL_FC1_RST_MASK (0x1000U)\r
+#define SYSCON_PRESETCTRL_FC1_RST_SHIFT (12U)\r
+/*! FC1_RST - Flexcomm 1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.\r
+ */\r
+#define SYSCON_PRESETCTRL_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL_FC1_RST_MASK)\r
+#define SYSCON_PRESETCTRL_OTP_RST_MASK (0x1000U)\r
+#define SYSCON_PRESETCTRL_OTP_RST_SHIFT (12U)\r
+/*! OTP_RST - OTP reset control.\r
+ */\r
+#define SYSCON_PRESETCTRL_OTP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_OTP_RST_SHIFT)) & SYSCON_PRESETCTRL_OTP_RST_MASK)\r
+#define SYSCON_PRESETCTRL_FC2_RST_MASK (0x2000U)\r
+#define SYSCON_PRESETCTRL_FC2_RST_SHIFT (13U)\r
+/*! FC2_RST - Flexcomm 2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.\r
+ */\r
+#define SYSCON_PRESETCTRL_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL_FC2_RST_MASK)\r
+#define SYSCON_PRESETCTRL_IOCON_RST_MASK (0x2000U)\r
+#define SYSCON_PRESETCTRL_IOCON_RST_SHIFT (13U)\r
+/*! IOCON_RST - IOCON reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.\r
+ */\r
+#define SYSCON_PRESETCTRL_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL_IOCON_RST_MASK)\r
+#define SYSCON_PRESETCTRL_RNG_RST_MASK (0x2000U)\r
+#define SYSCON_PRESETCTRL_RNG_RST_SHIFT (13U)\r
+/*! RNG_RST - RNG reset control.\r
+ */\r
+#define SYSCON_PRESETCTRL_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL_RNG_RST_MASK)\r
+#define SYSCON_PRESETCTRL_FC3_RST_MASK (0x4000U)\r
+#define SYSCON_PRESETCTRL_FC3_RST_SHIFT (14U)\r
+/*! FC3_RST - Flexcomm 3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.\r
+ */\r
+#define SYSCON_PRESETCTRL_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL_FC3_RST_MASK)\r
+#define SYSCON_PRESETCTRL_FC8_RST_MASK (0x4000U)\r
+#define SYSCON_PRESETCTRL_FC8_RST_SHIFT (14U)\r
+/*! FC8_RST - Flexcomm 8 reset control.\r
+ */\r
+#define SYSCON_PRESETCTRL_FC8_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC8_RST_SHIFT)) & SYSCON_PRESETCTRL_FC8_RST_MASK)\r
+#define SYSCON_PRESETCTRL_GPIO0_RST_MASK (0x4000U)\r
+#define SYSCON_PRESETCTRL_GPIO0_RST_SHIFT (14U)\r
+/*! GPIO0_RST - GPIO0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.\r
+ */\r
+#define SYSCON_PRESETCTRL_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO0_RST_MASK)\r
+#define SYSCON_PRESETCTRL_FC4_RST_MASK (0x8000U)\r
+#define SYSCON_PRESETCTRL_FC4_RST_SHIFT (15U)\r
+/*! FC4_RST - Flexcomm 4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.\r
+ */\r
+#define SYSCON_PRESETCTRL_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL_FC4_RST_MASK)\r
+#define SYSCON_PRESETCTRL_FC9_RST_MASK (0x8000U)\r
+#define SYSCON_PRESETCTRL_FC9_RST_SHIFT (15U)\r
+/*! FC9_RST - Flexcomm 9 reset control.\r
+ */\r
+#define SYSCON_PRESETCTRL_FC9_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC9_RST_SHIFT)) & SYSCON_PRESETCTRL_FC9_RST_MASK)\r
+#define SYSCON_PRESETCTRL_GPIO1_RST_MASK (0x8000U)\r
+#define SYSCON_PRESETCTRL_GPIO1_RST_SHIFT (15U)\r
+/*! GPIO1_RST - GPIO1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.\r
+ */\r
+#define SYSCON_PRESETCTRL_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO1_RST_MASK)\r
+#define SYSCON_PRESETCTRL_FC5_RST_MASK (0x10000U)\r
+#define SYSCON_PRESETCTRL_FC5_RST_SHIFT (16U)\r
+/*! FC5_RST - Flexcomm 5 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.\r
+ */\r
+#define SYSCON_PRESETCTRL_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL_FC5_RST_MASK)\r
+#define SYSCON_PRESETCTRL_GPIO2_RST_MASK (0x10000U)\r
+#define SYSCON_PRESETCTRL_GPIO2_RST_SHIFT (16U)\r
+/*! GPIO2_RST - GPIO2 reset control.\r
+ */\r
+#define SYSCON_PRESETCTRL_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO2_RST_MASK)\r
+#define SYSCON_PRESETCTRL_USB0HMR_RST_MASK (0x10000U)\r
+#define SYSCON_PRESETCTRL_USB0HMR_RST_SHIFT (16U)\r
+/*! USB0HMR_RST - USB0 HOST master reset control.\r
+ */\r
+#define SYSCON_PRESETCTRL_USB0HMR_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0HMR_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0HMR_RST_MASK)\r
+#define SYSCON_PRESETCTRL_FC6_RST_MASK (0x20000U)\r
+#define SYSCON_PRESETCTRL_FC6_RST_SHIFT (17U)\r
+/*! FC6_RST - Flexcomm 6 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.\r
+ */\r
+#define SYSCON_PRESETCTRL_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL_FC6_RST_MASK)\r
+#define SYSCON_PRESETCTRL_GPIO3_RST_MASK (0x20000U)\r
+#define SYSCON_PRESETCTRL_GPIO3_RST_SHIFT (17U)\r
+/*! GPIO3_RST - GPIO3 reset control.\r
+ */\r
+#define SYSCON_PRESETCTRL_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO3_RST_MASK)\r
+#define SYSCON_PRESETCTRL_USB0HSL_RST_MASK (0x20000U)\r
+#define SYSCON_PRESETCTRL_USB0HSL_RST_SHIFT (17U)\r
+/*! USB0HSL_RST - USB0 HOST slave reset control.\r
+ */\r
+#define SYSCON_PRESETCTRL_USB0HSL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0HSL_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0HSL_RST_MASK)\r
+#define SYSCON_PRESETCTRL_FC7_RST_MASK (0x40000U)\r
+#define SYSCON_PRESETCTRL_FC7_RST_SHIFT (18U)\r
+/*! FC7_RST - Flexcomm 7 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.\r
+ */\r
+#define SYSCON_PRESETCTRL_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL_FC7_RST_MASK)\r
+#define SYSCON_PRESETCTRL_PINT_RST_MASK (0x40000U)\r
+#define SYSCON_PRESETCTRL_PINT_RST_SHIFT (18U)\r
+/*! PINT_RST - Pin interrupt (PINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.\r
+ */\r
+#define SYSCON_PRESETCTRL_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL_PINT_RST_MASK)\r
+#define SYSCON_PRESETCTRL_SHA_RST_MASK (0x40000U)\r
+#define SYSCON_PRESETCTRL_SHA_RST_SHIFT (18U)\r
+/*! SHA_RST - SHA reset control.\r
+ */\r
+#define SYSCON_PRESETCTRL_SHA_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SHA_RST_SHIFT)) & SYSCON_PRESETCTRL_SHA_RST_MASK)\r
+#define SYSCON_PRESETCTRL_DMIC_RST_MASK (0x80000U)\r
+#define SYSCON_PRESETCTRL_DMIC_RST_SHIFT (19U)\r
+/*! DMIC_RST - Digital microphone interface reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.\r
+ */\r
+#define SYSCON_PRESETCTRL_DMIC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMIC_RST_SHIFT)) & SYSCON_PRESETCTRL_DMIC_RST_MASK)\r
+#define SYSCON_PRESETCTRL_GINT_RST_MASK (0x80000U)\r
+#define SYSCON_PRESETCTRL_GINT_RST_SHIFT (19U)\r
+/*! GINT_RST - Grouped interrupt (GINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.\r
+ */\r
+#define SYSCON_PRESETCTRL_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL_GINT_RST_MASK)\r
+#define SYSCON_PRESETCTRL_SC0_RST_MASK (0x80000U)\r
+#define SYSCON_PRESETCTRL_SC0_RST_SHIFT (19U)\r
+/*! SC0_RST - Smart card 0 reset control.\r
+ */\r
+#define SYSCON_PRESETCTRL_SC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SC0_RST_SHIFT)) & SYSCON_PRESETCTRL_SC0_RST_MASK)\r
+#define SYSCON_PRESETCTRL_DMA_RST_MASK (0x100000U)\r
+#define SYSCON_PRESETCTRL_DMA_RST_SHIFT (20U)\r
+/*! DMA_RST - DMA reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.\r
+ */\r
+#define SYSCON_PRESETCTRL_DMA_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMA_RST_SHIFT)) & SYSCON_PRESETCTRL_DMA_RST_MASK)\r
+#define SYSCON_PRESETCTRL_SC1_RST_MASK (0x100000U)\r
+#define SYSCON_PRESETCTRL_SC1_RST_SHIFT (20U)\r
+/*! SC1_RST - Smart card 1 reset control.\r
+ */\r
+#define SYSCON_PRESETCTRL_SC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SC1_RST_SHIFT)) & SYSCON_PRESETCTRL_SC1_RST_MASK)\r
+#define SYSCON_PRESETCTRL_CRC_RST_MASK (0x200000U)\r
+#define SYSCON_PRESETCTRL_CRC_RST_SHIFT (21U)\r
+/*! CRC_RST - CRC generator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.\r
+ */\r
+#define SYSCON_PRESETCTRL_CRC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CRC_RST_SHIFT)) & SYSCON_PRESETCTRL_CRC_RST_MASK)\r
+#define SYSCON_PRESETCTRL_FC10_RST_MASK (0x200000U)\r
+#define SYSCON_PRESETCTRL_FC10_RST_SHIFT (21U)\r
+/*! FC10_RST - Flexcomm 10 reset control.\r
+ */\r
+#define SYSCON_PRESETCTRL_FC10_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC10_RST_SHIFT)) & SYSCON_PRESETCTRL_FC10_RST_MASK)\r
+#define SYSCON_PRESETCTRL_CTIMER2_RST_MASK (0x400000U)\r
+#define SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT (22U)\r
+/*! CTIMER2_RST - CTIMER2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function\r
+ */\r
+#define SYSCON_PRESETCTRL_CTIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER2_RST_MASK)\r
+#define SYSCON_PRESETCTRL_WWDT_RST_MASK (0x400000U)\r
+#define SYSCON_PRESETCTRL_WWDT_RST_SHIFT (22U)\r
+/*! WWDT_RST - Watchdog timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.\r
+ */\r
+#define SYSCON_PRESETCTRL_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL_WWDT_RST_MASK)\r
+#define SYSCON_PRESETCTRL_USB0D_RST_MASK (0x2000000U)\r
+#define SYSCON_PRESETCTRL_USB0D_RST_SHIFT (25U)\r
+/*! USB0D_RST - USB0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.\r
+ */\r
+#define SYSCON_PRESETCTRL_USB0D_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0D_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0D_RST_MASK)\r
+#define SYSCON_PRESETCTRL_CTIMER0_RST_MASK (0x4000000U)\r
+#define SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT (26U)\r
+/*! CTIMER0_RST - CTIMER0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.\r
+ */\r
+#define SYSCON_PRESETCTRL_CTIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER0_RST_MASK)\r
+#define SYSCON_PRESETCTRL_ADC0_RST_MASK (0x8000000U)\r
+#define SYSCON_PRESETCTRL_ADC0_RST_SHIFT (27U)\r
+/*! ADC0_RST - ADC0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.\r
+ */\r
+#define SYSCON_PRESETCTRL_ADC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL_ADC0_RST_MASK)\r
+#define SYSCON_PRESETCTRL_CTIMER1_RST_MASK (0x8000000U)\r
+#define SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT (27U)\r
+/*! CTIMER1_RST - CTIMER1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.\r
+ */\r
+#define SYSCON_PRESETCTRL_CTIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER1_RST_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_PRESETCTRL */\r
+#define SYSCON_PRESETCTRL_COUNT (3U)\r
+\r
+/*! @name PRESETCTRLSET - Set bits in PRESETCTRLn */\r
+/*! @{ */\r
+#define SYSCON_PRESETCTRLSET_RST_SET_MASK (0xFFFFFFFFU)\r
+#define SYSCON_PRESETCTRLSET_RST_SET_SHIFT (0U)\r
+/*! RST_SET - Writing ones to this register sets the corresponding bit or bits in the PRESETCTRLn\r
+ * register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn\r
+ * are reserved and only zeroes should be written to them.\r
+ */\r
+#define SYSCON_PRESETCTRLSET_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET_RST_SET_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_PRESETCTRLSET */\r
+#define SYSCON_PRESETCTRLSET_COUNT (3U)\r
+\r
+/*! @name PRESETCTRLCLR - Clear bits in PRESETCTRLn */\r
+/*! @{ */\r
+#define SYSCON_PRESETCTRLCLR_RST_CLR_MASK (0xFFFFFFFFU)\r
+#define SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT (0U)\r
+/*! RST_CLR - Writing ones to this register clears the corresponding bit or bits in the PRESETCTRLn\r
+ * register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn\r
+ * are reserved and only zeroes should be written to them.\r
+ */\r
+#define SYSCON_PRESETCTRLCLR_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR_RST_CLR_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_PRESETCTRLCLR */\r
+#define SYSCON_PRESETCTRLCLR_COUNT (3U)\r
+\r
+/*! @name SYSRSTSTAT - System reset status register */\r
+/*! @{ */\r
+#define SYSCON_SYSRSTSTAT_POR_MASK (0x1U)\r
+#define SYSCON_SYSRSTSTAT_POR_SHIFT (0U)\r
+/*! POR - POR reset status\r
+ * 0b0..No POR detected\r
+ * 0b1..POR detected. Writing a one clears this reset.\r
+ */\r
+#define SYSCON_SYSRSTSTAT_POR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_POR_SHIFT)) & SYSCON_SYSRSTSTAT_POR_MASK)\r
+#define SYSCON_SYSRSTSTAT_EXTRST_MASK (0x2U)\r
+#define SYSCON_SYSRSTSTAT_EXTRST_SHIFT (1U)\r
+/*! EXTRST - Status of the external RESET pin. External reset status\r
+ * 0b0..No reset event detected.\r
+ * 0b1..Reset detected. Writing a one clears this reset.\r
+ */\r
+#define SYSCON_SYSRSTSTAT_EXTRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_EXTRST_SHIFT)) & SYSCON_SYSRSTSTAT_EXTRST_MASK)\r
+#define SYSCON_SYSRSTSTAT_WDT_MASK (0x4U)\r
+#define SYSCON_SYSRSTSTAT_WDT_SHIFT (2U)\r
+/*! WDT - Status of the Watchdog reset\r
+ * 0b0..No WDT reset detected\r
+ * 0b1..WDT reset detected. Writing a one clears this reset.\r
+ */\r
+#define SYSCON_SYSRSTSTAT_WDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_WDT_SHIFT)) & SYSCON_SYSRSTSTAT_WDT_MASK)\r
+#define SYSCON_SYSRSTSTAT_BOD_MASK (0x8U)\r
+#define SYSCON_SYSRSTSTAT_BOD_SHIFT (3U)\r
+/*! BOD - Status of the Brown-out detect reset\r
+ * 0b0..No BOD reset detected\r
+ * 0b1..BOD reset detected. Writing a one clears this reset.\r
+ */\r
+#define SYSCON_SYSRSTSTAT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_BOD_SHIFT)) & SYSCON_SYSRSTSTAT_BOD_MASK)\r
+#define SYSCON_SYSRSTSTAT_SYSRST_MASK (0x10U)\r
+#define SYSCON_SYSRSTSTAT_SYSRST_SHIFT (4U)\r
+/*! SYSRST - Status of the software system reset\r
+ * 0b0..No System reset detected\r
+ * 0b1..System reset detected. Writing a one clears this reset.\r
+ */\r
+#define SYSCON_SYSRSTSTAT_SYSRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_SYSRST_SHIFT)) & SYSCON_SYSRSTSTAT_SYSRST_MASK)\r
+/*! @} */\r
+\r
+/*! @name AHBCLKCTRL - AHB Clock control n */\r
+/*! @{ */\r
+#define SYSCON_AHBCLKCTRL_MRT_MASK (0x1U)\r
+#define SYSCON_AHBCLKCTRL_MRT_SHIFT (0U)\r
+/*! MRT - Enables the clock for the Multi-Rate Timer.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MRT_SHIFT)) & SYSCON_AHBCLKCTRL_MRT_MASK)\r
+#define SYSCON_AHBCLKCTRL_RIT_MASK (0x2U)\r
+#define SYSCON_AHBCLKCTRL_RIT_SHIFT (1U)\r
+/*! RIT - Enables the clock for the Repetitive Interrupt Timer.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_RIT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RIT_SHIFT)) & SYSCON_AHBCLKCTRL_RIT_MASK)\r
+#define SYSCON_AHBCLKCTRL_ROM_MASK (0x2U)\r
+#define SYSCON_AHBCLKCTRL_ROM_SHIFT (1U)\r
+/*! ROM - Enables the clock for the Boot ROM. 0 = Disable; 1 = Enable.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ROM_SHIFT)) & SYSCON_AHBCLKCTRL_ROM_MASK)\r
+#define SYSCON_AHBCLKCTRL_LCD_MASK (0x4U)\r
+#define SYSCON_AHBCLKCTRL_LCD_SHIFT (2U)\r
+/*! LCD - Enables the clock for the LCD interface.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_LCD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_LCD_SHIFT)) & SYSCON_AHBCLKCTRL_LCD_MASK)\r
+#define SYSCON_AHBCLKCTRL_SCT0_MASK (0x4U)\r
+#define SYSCON_AHBCLKCTRL_SCT0_SHIFT (2U)\r
+/*! SCT0 - Enables the clock for SCT0.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL_SCT0_MASK)\r
+#define SYSCON_AHBCLKCTRL_SDIO_MASK (0x8U)\r
+#define SYSCON_AHBCLKCTRL_SDIO_SHIFT (3U)\r
+/*! SDIO - Enables the clock for the SDIO interface.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL_SDIO_MASK)\r
+#define SYSCON_AHBCLKCTRL_SRAM1_MASK (0x8U)\r
+#define SYSCON_AHBCLKCTRL_SRAM1_SHIFT (3U)\r
+/*! SRAM1 - Enables the clock for SRAM1. 0 = Disable; 1 = Enable.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_SRAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM1_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM1_MASK)\r
+#define SYSCON_AHBCLKCTRL_SRAM2_MASK (0x10U)\r
+#define SYSCON_AHBCLKCTRL_SRAM2_SHIFT (4U)\r
+/*! SRAM2 - Enables the clock for SRAM2. 0 = Disable; 1 = Enable.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_SRAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM2_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM2_MASK)\r
+#define SYSCON_AHBCLKCTRL_USB1H_MASK (0x10U)\r
+#define SYSCON_AHBCLKCTRL_USB1H_SHIFT (4U)\r
+/*! USB1H - Enables the clock for the USB1 host interface.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_USB1H(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1H_SHIFT)) & SYSCON_AHBCLKCTRL_USB1H_MASK)\r
+#define SYSCON_AHBCLKCTRL_SRAM3_MASK (0x20U)\r
+#define SYSCON_AHBCLKCTRL_SRAM3_SHIFT (5U)\r
+/*! SRAM3 - Enables the clock for SRAM3.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_SRAM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM3_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM3_MASK)\r
+#define SYSCON_AHBCLKCTRL_USB1D_MASK (0x20U)\r
+#define SYSCON_AHBCLKCTRL_USB1D_SHIFT (5U)\r
+/*! USB1D - Enables the clock for the USB1 device interface.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_USB1D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1D_SHIFT)) & SYSCON_AHBCLKCTRL_USB1D_MASK)\r
+#define SYSCON_AHBCLKCTRL_USB1RAM_MASK (0x40U)\r
+#define SYSCON_AHBCLKCTRL_USB1RAM_SHIFT (6U)\r
+/*! USB1RAM - Enables the clock for the USB1 RAM interface.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_USB1RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1RAM_SHIFT)) & SYSCON_AHBCLKCTRL_USB1RAM_MASK)\r
+#define SYSCON_AHBCLKCTRL_EMC_MASK (0x80U)\r
+#define SYSCON_AHBCLKCTRL_EMC_SHIFT (7U)\r
+/*! EMC - Enables the clock for the EMC interface.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_EMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_EMC_SHIFT)) & SYSCON_AHBCLKCTRL_EMC_MASK)\r
+#define SYSCON_AHBCLKCTRL_MCAN0_MASK (0x80U)\r
+#define SYSCON_AHBCLKCTRL_MCAN0_SHIFT (7U)\r
+/*! MCAN0 - Enables the clock for MCAN0.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_MCAN0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MCAN0_SHIFT)) & SYSCON_AHBCLKCTRL_MCAN0_MASK)\r
+#define SYSCON_AHBCLKCTRL_ETH_MASK (0x100U)\r
+#define SYSCON_AHBCLKCTRL_ETH_SHIFT (8U)\r
+/*! ETH - Enables the clock for the ethernet interface.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_ETH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ETH_SHIFT)) & SYSCON_AHBCLKCTRL_ETH_MASK)\r
+#define SYSCON_AHBCLKCTRL_MCAN1_MASK (0x100U)\r
+#define SYSCON_AHBCLKCTRL_MCAN1_SHIFT (8U)\r
+/*! MCAN1 - Enables the clock for MCAN1.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_MCAN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MCAN1_SHIFT)) & SYSCON_AHBCLKCTRL_MCAN1_MASK)\r
+#define SYSCON_AHBCLKCTRL_GPIO4_MASK (0x200U)\r
+#define SYSCON_AHBCLKCTRL_GPIO4_SHIFT (9U)\r
+/*! GPIO4 - Enables the clock for the GPIO4 interface.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO4_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO4_MASK)\r
+#define SYSCON_AHBCLKCTRL_GPIO5_MASK (0x400U)\r
+#define SYSCON_AHBCLKCTRL_GPIO5_SHIFT (10U)\r
+/*! GPIO5 - Enables the clock for the GPIO5 interface.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_GPIO5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO5_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO5_MASK)\r
+#define SYSCON_AHBCLKCTRL_SPIFI_MASK (0x400U)\r
+#define SYSCON_AHBCLKCTRL_SPIFI_SHIFT (10U)\r
+/*! SPIFI - Enables the clock for the SPIFI. 0 = Disable; 1 = Enable.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_SPIFI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SPIFI_SHIFT)) & SYSCON_AHBCLKCTRL_SPIFI_MASK)\r
+#define SYSCON_AHBCLKCTRL_UTICK_MASK (0x400U)\r
+#define SYSCON_AHBCLKCTRL_UTICK_SHIFT (10U)\r
+/*! UTICK - Enables the clock for the Micro-tick Timer. 0 = Disable; 1 = Enable.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL_UTICK_MASK)\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK (0x800U)\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT (11U)\r
+/*! FLEXCOMM0 - Enables the clock for Flexcomm 0. 0 = Disable; 1 = Enable.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK)\r
+#define SYSCON_AHBCLKCTRL_INPUTMUX_MASK (0x800U)\r
+#define SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT (11U)\r
+/*! INPUTMUX - Enables the clock for the input muxes. 0 = Disable; 1 = Enable.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_INPUTMUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT)) & SYSCON_AHBCLKCTRL_INPUTMUX_MASK)\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK (0x1000U)\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT (12U)\r
+/*! FLEXCOMM1 - Enables the clock for Flexcomm 1. 0 = Disable; 1 = Enable.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK)\r
+#define SYSCON_AHBCLKCTRL_OTP_MASK (0x1000U)\r
+#define SYSCON_AHBCLKCTRL_OTP_SHIFT (12U)\r
+/*! OTP - Enables the clock for the OTP interface.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_OTP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_OTP_SHIFT)) & SYSCON_AHBCLKCTRL_OTP_MASK)\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK (0x2000U)\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT (13U)\r
+/*! FLEXCOMM2 - Enables the clock for Flexcomm 2. 0 = Disable; 1 = Enable.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK)\r
+#define SYSCON_AHBCLKCTRL_IOCON_MASK (0x2000U)\r
+#define SYSCON_AHBCLKCTRL_IOCON_SHIFT (13U)\r
+/*! IOCON - Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL_IOCON_MASK)\r
+#define SYSCON_AHBCLKCTRL_RNG_MASK (0x2000U)\r
+#define SYSCON_AHBCLKCTRL_RNG_SHIFT (13U)\r
+/*! RNG - Enables the clock for the RNG interface.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RNG_SHIFT)) & SYSCON_AHBCLKCTRL_RNG_MASK)\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK (0x4000U)\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT (14U)\r
+/*! FLEXCOMM3 - Enables the clock for Flexcomm 3. 0 = Disable; 1 = Enable.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK)\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM8_MASK (0x4000U)\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM8_SHIFT (14U)\r
+/*! FLEXCOMM8 - Enables the clock for the Flexcomm8 interface.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM8_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM8_MASK)\r
+#define SYSCON_AHBCLKCTRL_GPIO0_MASK (0x4000U)\r
+#define SYSCON_AHBCLKCTRL_GPIO0_SHIFT (14U)\r
+/*! GPIO0 - Enables the clock for the GPIO0 port registers. 0 = Disable; 1 = Enable.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO0_MASK)\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK (0x8000U)\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT (15U)\r
+/*! FLEXCOMM4 - Enables the clock for Flexcomm 4. 0 = Disable; 1 = Enable.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK)\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM9_MASK (0x8000U)\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM9_SHIFT (15U)\r
+/*! FLEXCOMM9 - Enables the clock for the Flexcomm9 interface.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM9_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM9_MASK)\r
+#define SYSCON_AHBCLKCTRL_GPIO1_MASK (0x8000U)\r
+#define SYSCON_AHBCLKCTRL_GPIO1_SHIFT (15U)\r
+/*! GPIO1 - Enables the clock for the GPIO1 port registers. 0 = Disable; 1 = Enable.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO1_MASK)\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK (0x10000U)\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT (16U)\r
+/*! FLEXCOMM5 - Enables the clock for Flexcomm 5. 0 = Disable; 1 = Enable.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK)\r
+#define SYSCON_AHBCLKCTRL_GPIO2_MASK (0x10000U)\r
+#define SYSCON_AHBCLKCTRL_GPIO2_SHIFT (16U)\r
+/*! GPIO2 - Enables the clock for the GPIO2 port registers.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO2_MASK)\r
+#define SYSCON_AHBCLKCTRL_USB0HMR_MASK (0x10000U)\r
+#define SYSCON_AHBCLKCTRL_USB0HMR_SHIFT (16U)\r
+/*! USB0HMR - Enables the clock for the USB host master interface.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_USB0HMR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0HMR_SHIFT)) & SYSCON_AHBCLKCTRL_USB0HMR_MASK)\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK (0x20000U)\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT (17U)\r
+/*! FLEXCOMM6 - Enables the clock for Flexcomm 6. 0 = Disable; 1 = Enable.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK)\r
+#define SYSCON_AHBCLKCTRL_GPIO3_MASK (0x20000U)\r
+#define SYSCON_AHBCLKCTRL_GPIO3_SHIFT (17U)\r
+/*! GPIO3 - Enables the clock for the GPIO3 port registers.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO3_MASK)\r
+#define SYSCON_AHBCLKCTRL_USB0HSL_MASK (0x20000U)\r
+#define SYSCON_AHBCLKCTRL_USB0HSL_SHIFT (17U)\r
+/*! USB0HSL - Enables the clock for the USB host slave interface.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_USB0HSL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0HSL_SHIFT)) & SYSCON_AHBCLKCTRL_USB0HSL_MASK)\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK (0x40000U)\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT (18U)\r
+/*! FLEXCOMM7 - Enables the clock for Flexcomm 7. 0 = Disable; 1 = Enable.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK)\r
+#define SYSCON_AHBCLKCTRL_PINT_MASK (0x40000U)\r
+#define SYSCON_AHBCLKCTRL_PINT_SHIFT (18U)\r
+/*! PINT - Enables the clock for the pin interrupt block.0 = Disable; 1 = Enable.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_PINT_SHIFT)) & SYSCON_AHBCLKCTRL_PINT_MASK)\r
+#define SYSCON_AHBCLKCTRL_SHA_MASK (0x40000U)\r
+#define SYSCON_AHBCLKCTRL_SHA_SHIFT (18U)\r
+/*! SHA - Enables the clock for the SHA interface.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_SHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SHA_SHIFT)) & SYSCON_AHBCLKCTRL_SHA_MASK)\r
+#define SYSCON_AHBCLKCTRL_DMIC_MASK (0x80000U)\r
+#define SYSCON_AHBCLKCTRL_DMIC_SHIFT (19U)\r
+/*! DMIC - Enables the clock for the digital microphone interface. 0 = Disable; 1 = Enable.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_DMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMIC_SHIFT)) & SYSCON_AHBCLKCTRL_DMIC_MASK)\r
+#define SYSCON_AHBCLKCTRL_GINT_MASK (0x80000U)\r
+#define SYSCON_AHBCLKCTRL_GINT_SHIFT (19U)\r
+/*! GINT - Enables the clock for the grouped pin interrupt block. 0 = Disable; 1 = Enable.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GINT_SHIFT)) & SYSCON_AHBCLKCTRL_GINT_MASK)\r
+#define SYSCON_AHBCLKCTRL_SC0_MASK (0x80000U)\r
+#define SYSCON_AHBCLKCTRL_SC0_SHIFT (19U)\r
+/*! SC0 - Enables the clock for the Smart card0 interface.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_SC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SC0_SHIFT)) & SYSCON_AHBCLKCTRL_SC0_MASK)\r
+#define SYSCON_AHBCLKCTRL_DMA_MASK (0x100000U)\r
+#define SYSCON_AHBCLKCTRL_DMA_SHIFT (20U)\r
+/*! DMA - Enables the clock for the DMA controller. 0 = Disable; 1 = Enable.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMA_SHIFT)) & SYSCON_AHBCLKCTRL_DMA_MASK)\r
+#define SYSCON_AHBCLKCTRL_SC1_MASK (0x100000U)\r
+#define SYSCON_AHBCLKCTRL_SC1_SHIFT (20U)\r
+/*! SC1 - Enables the clock for the Smart card1 interface.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_SC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SC1_SHIFT)) & SYSCON_AHBCLKCTRL_SC1_MASK)\r
+#define SYSCON_AHBCLKCTRL_CRC_MASK (0x200000U)\r
+#define SYSCON_AHBCLKCTRL_CRC_SHIFT (21U)\r
+/*! CRC - Enables the clock for the CRC engine. 0 = Disable; 1 = Enable.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_CRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CRC_SHIFT)) & SYSCON_AHBCLKCTRL_CRC_MASK)\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM10_MASK (0x200000U)\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM10_SHIFT (21U)\r
+/*! FLEXCOMM10 - Enables the clock for the Flexcomm10 interface.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_FLEXCOMM10(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM10_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM10_MASK)\r
+#define SYSCON_AHBCLKCTRL_CTIMER2_MASK (0x400000U)\r
+#define SYSCON_AHBCLKCTRL_CTIMER2_SHIFT (22U)\r
+/*! CTIMER2 - Enables the clock for CTIMER 2. 0 = Disable; 1 = Enable.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER2_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER2_MASK)\r
+#define SYSCON_AHBCLKCTRL_WWDT_MASK (0x400000U)\r
+#define SYSCON_AHBCLKCTRL_WWDT_SHIFT (22U)\r
+/*! WWDT - Enables the clock for the Watchdog Timer. 0 = Disable; 1 = Enable.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL_WWDT_MASK)\r
+#define SYSCON_AHBCLKCTRL_RTC_MASK (0x800000U)\r
+#define SYSCON_AHBCLKCTRL_RTC_SHIFT (23U)\r
+/*! RTC - Enables the bus clock for the RTC. 0 = Disable; 1 = Enable.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RTC_SHIFT)) & SYSCON_AHBCLKCTRL_RTC_MASK)\r
+#define SYSCON_AHBCLKCTRL_USB0D_MASK (0x2000000U)\r
+#define SYSCON_AHBCLKCTRL_USB0D_SHIFT (25U)\r
+/*! USB0D - Enables the clock for the USB0 device interface. 0 = Disable; 1 = Enable.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_USB0D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0D_SHIFT)) & SYSCON_AHBCLKCTRL_USB0D_MASK)\r
+#define SYSCON_AHBCLKCTRL_CTIMER0_MASK (0x4000000U)\r
+#define SYSCON_AHBCLKCTRL_CTIMER0_SHIFT (26U)\r
+/*! CTIMER0 - Enables the clock for timer CTIMER0. 0 = Disable; 1 = Enable.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER0_MASK)\r
+#define SYSCON_AHBCLKCTRL_ADC0_MASK (0x8000000U)\r
+#define SYSCON_AHBCLKCTRL_ADC0_SHIFT (27U)\r
+/*! ADC0 - Enables the clock for the ADC0 register interface.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL_ADC0_MASK)\r
+#define SYSCON_AHBCLKCTRL_CTIMER1_MASK (0x8000000U)\r
+#define SYSCON_AHBCLKCTRL_CTIMER1_SHIFT (27U)\r
+/*! CTIMER1 - Enables the clock for timer CTIMER1. 0 = Disable; 1 = Enable.\r
+ */\r
+#define SYSCON_AHBCLKCTRL_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER1_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER1_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_AHBCLKCTRL */\r
+#define SYSCON_AHBCLKCTRL_COUNT (3U)\r
+\r
+/*! @name AHBCLKCTRLSET - Set bits in AHBCLKCTRLn */\r
+/*! @{ */\r
+#define SYSCON_AHBCLKCTRLSET_CLK_SET_MASK (0xFFFFFFFFU)\r
+#define SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT (0U)\r
+/*! CLK_SET - Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRLn\r
+ * register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn\r
+ * are reserved and only zeroes should be written to them.\r
+ */\r
+#define SYSCON_AHBCLKCTRLSET_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET_CLK_SET_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_AHBCLKCTRLSET */\r
+#define SYSCON_AHBCLKCTRLSET_COUNT (3U)\r
+\r
+/*! @name AHBCLKCTRLCLR - Clear bits in AHBCLKCTRLn */\r
+/*! @{ */\r
+#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK (0xFFFFFFFFU)\r
+#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT (0U)\r
+/*! CLK_CLR - Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRLn\r
+ * register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn\r
+ * are reserved and only zeroes should be written to them.\r
+ */\r
+#define SYSCON_AHBCLKCTRLCLR_CLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT)) & SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_AHBCLKCTRLCLR */\r
+#define SYSCON_AHBCLKCTRLCLR_COUNT (3U)\r
+\r
+/*! @name STICKCLKSEL - Systick timer clock source selection */\r
+/*! @{ */\r
+#define SYSCON_STICKCLKSEL_SEL_MASK (0x7U)\r
+#define SYSCON_STICKCLKSEL_SEL_SHIFT (0U)\r
+/*! SEL - Systick timer clock source selection\r
+ * 0b000..Main clock (main_clk)\r
+ * 0b001..Watchdog oscillator (wdt_clk)\r
+ * 0b010..RTC oscillator 32 kHz output (32k_clk)\r
+ * 0b011..FRO 12 MHz (fro_12m)\r
+ * 0b100..Reserved setting\r
+ * 0b101..Reserved setting\r
+ * 0b110..Reserved setting\r
+ * 0b111..None, this may be selected to reduce power when no output is needed.\r
+ */\r
+#define SYSCON_STICKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STICKCLKSEL_SEL_SHIFT)) & SYSCON_STICKCLKSEL_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAINCLKSELA - Main clock source select A */\r
+/*! @{ */\r
+#define SYSCON_MAINCLKSELA_SEL_MASK (0x3U)\r
+#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U)\r
+/*! SEL - Clock source for main clock source selector A\r
+ * 0b00..FRO 12 MHz (fro_12m)\r
+ * 0b01..CLKIN (clk_in)\r
+ * 0b10..Watchdog oscillator (wdt_clk)\r
+ * 0b11..FRO 96 or 48 MHz (fro_hf)\r
+ */\r
+#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAINCLKSELB - Main clock source select B */\r
+/*! @{ */\r
+#define SYSCON_MAINCLKSELB_SEL_MASK (0x3U)\r
+#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U)\r
+/*! SEL - Clock source for main clock source selector B. Selects the clock source for the main clock.\r
+ * 0b00..MAINCLKSELA. Use the clock source selected in MAINCLKSELA register.\r
+ * 0b01..Reserved setting\r
+ * 0b10..System PLL output (pll_clk)\r
+ * 0b11..RTC oscillator 32 kHz output (32k_clk)\r
+ */\r
+#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name CLKOUTSELA - CLKOUT clock source select A */\r
+/*! @{ */\r
+#define SYSCON_CLKOUTSELA_SEL_MASK (0x7U)\r
+#define SYSCON_CLKOUTSELA_SEL_SHIFT (0U)\r
+/*! SEL - CLKOUT clock source selection\r
+ * 0b000..Main clock (main_clk)\r
+ * 0b001..CLKIN (clk_in)\r
+ * 0b010..Watchdog oscillator (wdt_clk)\r
+ * 0b011..FRO 96 or 48 MHz (fro_hf)\r
+ * 0b100..PLL output (pll_clk)\r
+ * 0b101..USB PLL clock (usb_pll_clk)\r
+ * 0b110..Audio PLL clock (audio_pll_clk)\r
+ * 0b111..RTC oscillator 32 kHz output (32k_clk)\r
+ */\r
+#define SYSCON_CLKOUTSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSELA_SEL_SHIFT)) & SYSCON_CLKOUTSELA_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name SYSPLLCLKSEL - PLL clock source select */\r
+/*! @{ */\r
+#define SYSCON_SYSPLLCLKSEL_SEL_MASK (0x7U)\r
+#define SYSCON_SYSPLLCLKSEL_SEL_SHIFT (0U)\r
+/*! SEL - System PLL clock source selection.\r
+ * 0b000..FRO 12 MHz (fro_12m)\r
+ * 0b001..CLKIN (clk_in)\r
+ * 0b011..RTC oscillator 32 kHz output (32k_clk)\r
+ * 0b111..None, this may be selected in order to reduce power when no output is needed.\r
+ */\r
+#define SYSCON_SYSPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCLKSEL_SEL_SHIFT)) & SYSCON_SYSPLLCLKSEL_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name AUDPLLCLKSEL - Audio PLL clock source select */\r
+/*! @{ */\r
+#define SYSCON_AUDPLLCLKSEL_SEL_MASK (0x7U)\r
+#define SYSCON_AUDPLLCLKSEL_SEL_SHIFT (0U)\r
+/*! SEL - Audio PLL clock source selection.\r
+ * 0b000..FRO 12 MHz (fro_12m)\r
+ * 0b001..CLKIN (clk_in)\r
+ * 0b111..None, this may be selected in order to reduce power when no output is needed.\r
+ */\r
+#define SYSCON_AUDPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCLKSEL_SEL_SHIFT)) & SYSCON_AUDPLLCLKSEL_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name SPIFICLKSEL - SPIFI clock source select */\r
+/*! @{ */\r
+#define SYSCON_SPIFICLKSEL_SEL_MASK (0x7U)\r
+#define SYSCON_SPIFICLKSEL_SEL_SHIFT (0U)\r
+/*! SEL - System PLL clock source selection\r
+ * 0b000..Main clock (main_clk)\r
+ * 0b001..System PLL output (pll_clk)\r
+ * 0b010..USB PLL clock (usb_pll_clk)\r
+ * 0b011..FRO 96 or 48 MHz (fro_hf)\r
+ * 0b100..Audio PLL clock (audio_pll_clk)\r
+ * 0b111..None, this may be selected in order to reduce power when no output is needed.\r
+ */\r
+#define SYSCON_SPIFICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKSEL_SEL_SHIFT)) & SYSCON_SPIFICLKSEL_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name ADCCLKSEL - ADC clock source select */\r
+/*! @{ */\r
+#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U)\r
+#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U)\r
+/*! SEL - ADC clock source selection\r
+ * 0b000..FRO 96 or 48 MHz (fro_hf)\r
+ * 0b001..System PLL output (pll_clk)\r
+ * 0b010..USB PLL clock (usb_pll_clk)\r
+ * 0b011..Audio PLL clock (audio_pll_clk)\r
+ * 0b111..None, this may be selected in order to reduce power when no output is needed.\r
+ */\r
+#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name USB0CLKSEL - USB0 clock source select */\r
+/*! @{ */\r
+#define SYSCON_USB0CLKSEL_SEL_MASK (0x7U)\r
+#define SYSCON_USB0CLKSEL_SEL_SHIFT (0U)\r
+/*! SEL - USB0 device clock source selection.\r
+ * 0b000..FRO 96 or 48 MHz (fro_hf)\r
+ * 0b001..System PLL output (pll_clk)\r
+ * 0b010..USB PLL clock (usb_pll_clk)\r
+ * 0b111..None, this may be selected in order to reduce power when no output is needed.\r
+ */\r
+#define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name USB1CLKSEL - USB1 clock source select */\r
+/*! @{ */\r
+#define SYSCON_USB1CLKSEL_SEL_MASK (0x7U)\r
+#define SYSCON_USB1CLKSEL_SEL_SHIFT (0U)\r
+/*! SEL - USB1 PHY clock source selection.\r
+ * 0b000..Main clock (main_clk)\r
+ * 0b001..System PLL output (pll_clk)\r
+ * 0b010..USB PLL clock (usb_pll_clk)\r
+ * 0b111..None, this may be selected in order to reduce power when no output is needed.\r
+ */\r
+#define SYSCON_USB1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSEL_SEL_SHIFT)) & SYSCON_USB1CLKSEL_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FCLKSEL - Flexcomm clock source select */\r
+/*! @{ */\r
+#define SYSCON_FCLKSEL_SEL_MASK (0x7U)\r
+#define SYSCON_FCLKSEL_SEL_SHIFT (0U)\r
+/*! SEL - Flexcomm clock source selection. One per Flexcomm.\r
+ * 0b000..FRO 12 MHz (fro_12m)\r
+ * 0b001..FRO HF DIV (fro_hf_div)\r
+ * 0b010..Audio PLL clock (audio_pll_clk)\r
+ * 0b011..MCLK pin input, when selected in IOCON (mclk_in)\r
+ * 0b100..FRG clock, the output of the fractional rate generator (frg_clk)\r
+ * 0b111..None, this may be selected in order to reduce power when no output is needed.\r
+ */\r
+#define SYSCON_FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCLKSEL_SEL_SHIFT)) & SYSCON_FCLKSEL_SEL_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_FCLKSEL */\r
+#define SYSCON_FCLKSEL_COUNT (10U)\r
+\r
+/*! @name FCLKSEL10 - Flexcomm 10 clock source select */\r
+/*! @{ */\r
+#define SYSCON_FCLKSEL10_SEL_MASK (0x7U)\r
+#define SYSCON_FCLKSEL10_SEL_SHIFT (0U)\r
+/*! SEL - Flexcomm clock source selection. One per Flexcomm.\r
+ * 0b000..Main clock (main_clk)\r
+ * 0b001..System PLL output (pll_clk)\r
+ * 0b010..USB PLL clock (usb_pll_clk)\r
+ * 0b011..FRO 96 or 48 MHz (fro_hf)\r
+ * 0b100..Audio PLL clock (audio_pll_clk)\r
+ * 0b111..None, this may be selected in order to reduce power when no output is needed.\r
+ */\r
+#define SYSCON_FCLKSEL10_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCLKSEL10_SEL_SHIFT)) & SYSCON_FCLKSEL10_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name MCLKCLKSEL - MCLK clock source select */\r
+/*! @{ */\r
+#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U)\r
+#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U)\r
+/*! SEL - MCLK source select. This may be used by Flexcomms that support I2S, and/or by the digital microphone subsystem.\r
+ * 0b000..FRO HF DIV (fro_hf_div)\r
+ * 0b001..Audio PLL clock (audio_pll_clk)\r
+ * 0b111..None, this may be selected in order to reduce power when no output is needed.\r
+ */\r
+#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FRGCLKSEL - Fractional Rate Generator clock source select */\r
+/*! @{ */\r
+#define SYSCON_FRGCLKSEL_SEL_MASK (0x7U)\r
+#define SYSCON_FRGCLKSEL_SEL_SHIFT (0U)\r
+/*! SEL - Fractional Rate Generator clock source select.\r
+ * 0b000..Main clock (main_clk)\r
+ * 0b001..System PLL output (pll_clk)\r
+ * 0b010..FRO 12 MHz (fro_12m)\r
+ * 0b011..FRO 96 or 48 MHz (fro_hf)\r
+ * 0b111..None, this may be selected in order to reduce power when no output is needed.\r
+ */\r
+#define SYSCON_FRGCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCLKSEL_SEL_SHIFT)) & SYSCON_FRGCLKSEL_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name DMICCLKSEL - Digital microphone (DMIC) subsystem clock select */\r
+/*! @{ */\r
+#define SYSCON_DMICCLKSEL_SEL_MASK (0x7U)\r
+#define SYSCON_DMICCLKSEL_SEL_SHIFT (0U)\r
+/*! SEL - DMIC (audio subsystem) clock source select.\r
+ * 0b000..FRO 12 MHz (fro_12m)\r
+ * 0b001..FRO HF DIV (fro_hf_div)\r
+ * 0b010..Audio PLL clock (audio_pll_clk)\r
+ * 0b011..MCLK pin input, when selected in IOCON (mclk_in)\r
+ * 0b100..Main clock (main_clk)\r
+ * 0b101..Watchdog oscillator (wdt_clk)\r
+ * 0b111..None, this may be selected in order to reduce power when no output is needed.\r
+ */\r
+#define SYSCON_DMICCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKSEL_SEL_SHIFT)) & SYSCON_DMICCLKSEL_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name SCTCLKSEL - SCTimer/PWM clock source select */\r
+/*! @{ */\r
+#define SYSCON_SCTCLKSEL_SEL_MASK (0x7U)\r
+#define SYSCON_SCTCLKSEL_SEL_SHIFT (0U)\r
+/*! SEL - SCT clock source select.\r
+ * 0b000..Main clock (main_clk)\r
+ * 0b001..System PLL output (pll_clk)\r
+ * 0b010..FRO 96 or 48 MHz (fro_hf)\r
+ * 0b011..Audio PLL clock (audio_pll_clk)\r
+ * 0b111..None, this may be selected in order to reduce power when no output is needed.\r
+ */\r
+#define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name LCDCLKSEL - LCD clock source select */\r
+/*! @{ */\r
+#define SYSCON_LCDCLKSEL_SEL_MASK (0x3U)\r
+#define SYSCON_LCDCLKSEL_SEL_SHIFT (0U)\r
+/*! SEL - LCD clock source select.\r
+ * 0b00..Main clock (main_clk)\r
+ * 0b01..LCDCLKIN (LCDCLK_EXT)\r
+ * 0b10..FRO 96 or 48 MHz (fro_hf)\r
+ * 0b11..None, this may be selected in order to reduce power when no output is needed.\r
+ */\r
+#define SYSCON_LCDCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKSEL_SEL_SHIFT)) & SYSCON_LCDCLKSEL_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name SDIOCLKSEL - SDIO clock source select */\r
+/*! @{ */\r
+#define SYSCON_SDIOCLKSEL_SEL_MASK (0x7U)\r
+#define SYSCON_SDIOCLKSEL_SEL_SHIFT (0U)\r
+/*! SEL - SDIO clock source select.\r
+ * 0b000..Main clock (main_clk)\r
+ * 0b001..System PLL output (pll_clk)\r
+ * 0b010..USB PLL clock (usb_pll_clk)\r
+ * 0b011..FRO 96 or 48 MHz (fro_hf)\r
+ * 0b100..Audio PLL clock (audio_pll_clk)\r
+ * 0b111..None, this may be selected in order to reduce power when no output is needed.\r
+ */\r
+#define SYSCON_SDIOCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name SYSTICKCLKDIV - SYSTICK clock divider */\r
+/*! @{ */\r
+#define SYSCON_SYSTICKCLKDIV_DIV_MASK (0xFFU)\r
+#define SYSCON_SYSTICKCLKDIV_DIV_SHIFT (0U)\r
+/*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256.\r
+ */\r
+#define SYSCON_SYSTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK)\r
+#define SYSCON_SYSTICKCLKDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_SYSTICKCLKDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right\r
+ * away rather than completing the previous count.\r
+ */\r
+#define SYSCON_SYSTICKCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK)\r
+#define SYSCON_SYSTICKCLKDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_SYSTICKCLKDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter.\r
+ */\r
+#define SYSCON_SYSTICKCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK)\r
+#define SYSCON_SYSTICKCLKDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_SYSTICKCLKDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ */\r
+#define SYSCON_SYSTICKCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name ARMTRACECLKDIV - ARM Trace clock divider */\r
+/*! @{ */\r
+#define SYSCON_ARMTRACECLKDIV_DIV_MASK (0xFFU)\r
+#define SYSCON_ARMTRACECLKDIV_DIV_SHIFT (0U)\r
+/*! DIV - Clock divider value.\r
+ */\r
+#define SYSCON_ARMTRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_DIV_SHIFT)) & SYSCON_ARMTRACECLKDIV_DIV_MASK)\r
+#define SYSCON_ARMTRACECLKDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_ARMTRACECLKDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter.\r
+ */\r
+#define SYSCON_ARMTRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_RESET_SHIFT)) & SYSCON_ARMTRACECLKDIV_RESET_MASK)\r
+#define SYSCON_ARMTRACECLKDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_ARMTRACECLKDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter.\r
+ */\r
+#define SYSCON_ARMTRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_HALT_SHIFT)) & SYSCON_ARMTRACECLKDIV_HALT_MASK)\r
+#define SYSCON_ARMTRACECLKDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_ARMTRACECLKDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ */\r
+#define SYSCON_ARMTRACECLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_ARMTRACECLKDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name CAN0CLKDIV - MCAN0 clock divider */\r
+/*! @{ */\r
+#define SYSCON_CAN0CLKDIV_DIV_MASK (0xFFU)\r
+#define SYSCON_CAN0CLKDIV_DIV_SHIFT (0U)\r
+/*! DIV - Clock divider value.\r
+ */\r
+#define SYSCON_CAN0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_DIV_SHIFT)) & SYSCON_CAN0CLKDIV_DIV_MASK)\r
+#define SYSCON_CAN0CLKDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_CAN0CLKDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter.\r
+ */\r
+#define SYSCON_CAN0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_RESET_SHIFT)) & SYSCON_CAN0CLKDIV_RESET_MASK)\r
+#define SYSCON_CAN0CLKDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_CAN0CLKDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter.\r
+ */\r
+#define SYSCON_CAN0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_HALT_SHIFT)) & SYSCON_CAN0CLKDIV_HALT_MASK)\r
+#define SYSCON_CAN0CLKDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_CAN0CLKDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ */\r
+#define SYSCON_CAN0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_REQFLAG_SHIFT)) & SYSCON_CAN0CLKDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name CAN1CLKDIV - MCAN1 clock divider */\r
+/*! @{ */\r
+#define SYSCON_CAN1CLKDIV_DIV_MASK (0xFFU)\r
+#define SYSCON_CAN1CLKDIV_DIV_SHIFT (0U)\r
+/*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256.\r
+ */\r
+#define SYSCON_CAN1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_DIV_SHIFT)) & SYSCON_CAN1CLKDIV_DIV_MASK)\r
+#define SYSCON_CAN1CLKDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_CAN1CLKDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right\r
+ * away rather than completing the previous count.\r
+ */\r
+#define SYSCON_CAN1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_RESET_SHIFT)) & SYSCON_CAN1CLKDIV_RESET_MASK)\r
+#define SYSCON_CAN1CLKDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_CAN1CLKDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter.\r
+ */\r
+#define SYSCON_CAN1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_HALT_SHIFT)) & SYSCON_CAN1CLKDIV_HALT_MASK)\r
+#define SYSCON_CAN1CLKDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_CAN1CLKDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ */\r
+#define SYSCON_CAN1CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_REQFLAG_SHIFT)) & SYSCON_CAN1CLKDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name SC0CLKDIV - Smartcard0 clock divider */\r
+/*! @{ */\r
+#define SYSCON_SC0CLKDIV_DIV_MASK (0xFFU)\r
+#define SYSCON_SC0CLKDIV_DIV_SHIFT (0U)\r
+/*! DIV - Clock divider value.\r
+ */\r
+#define SYSCON_SC0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_DIV_SHIFT)) & SYSCON_SC0CLKDIV_DIV_MASK)\r
+#define SYSCON_SC0CLKDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_SC0CLKDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter.\r
+ */\r
+#define SYSCON_SC0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_RESET_SHIFT)) & SYSCON_SC0CLKDIV_RESET_MASK)\r
+#define SYSCON_SC0CLKDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_SC0CLKDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter.\r
+ */\r
+#define SYSCON_SC0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_HALT_SHIFT)) & SYSCON_SC0CLKDIV_HALT_MASK)\r
+#define SYSCON_SC0CLKDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_SC0CLKDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ */\r
+#define SYSCON_SC0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_REQFLAG_SHIFT)) & SYSCON_SC0CLKDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name SC1CLKDIV - Smartcard1 clock divider */\r
+/*! @{ */\r
+#define SYSCON_SC1CLKDIV_DIV_MASK (0xFFU)\r
+#define SYSCON_SC1CLKDIV_DIV_SHIFT (0U)\r
+/*! DIV - Clock divider value.\r
+ */\r
+#define SYSCON_SC1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_DIV_SHIFT)) & SYSCON_SC1CLKDIV_DIV_MASK)\r
+#define SYSCON_SC1CLKDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_SC1CLKDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter.\r
+ */\r
+#define SYSCON_SC1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_RESET_SHIFT)) & SYSCON_SC1CLKDIV_RESET_MASK)\r
+#define SYSCON_SC1CLKDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_SC1CLKDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter.\r
+ */\r
+#define SYSCON_SC1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_HALT_SHIFT)) & SYSCON_SC1CLKDIV_HALT_MASK)\r
+#define SYSCON_SC1CLKDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_SC1CLKDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ */\r
+#define SYSCON_SC1CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_REQFLAG_SHIFT)) & SYSCON_SC1CLKDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name AHBCLKDIV - AHB clock divider */\r
+/*! @{ */\r
+#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU)\r
+#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U)\r
+/*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256.\r
+ */\r
+#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)\r
+#define SYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ */\r
+#define SYSCON_AHBCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name CLKOUTDIV - CLKOUT clock divider */\r
+/*! @{ */\r
+#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU)\r
+#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U)\r
+/*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256.\r
+ */\r
+#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK)\r
+#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right\r
+ * away rather than completing the previous count.\r
+ */\r
+#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK)\r
+#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed\r
+ * without the risk of a glitch at the output.\r
+ */\r
+#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK)\r
+#define SYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ */\r
+#define SYSCON_CLKOUTDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name FROHFDIV - FROHF clock divider */\r
+/*! @{ */\r
+#define SYSCON_FROHFDIV_DIV_MASK (0xFFU)\r
+#define SYSCON_FROHFDIV_DIV_SHIFT (0U)\r
+/*! DIV - Clock divider value.\r
+ */\r
+#define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK)\r
+#define SYSCON_FROHFDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_FROHFDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter.\r
+ */\r
+#define SYSCON_FROHFDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK)\r
+#define SYSCON_FROHFDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_FROHFDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter.\r
+ */\r
+#define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK)\r
+#define SYSCON_FROHFDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_FROHFDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ */\r
+#define SYSCON_FROHFDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_REQFLAG_SHIFT)) & SYSCON_FROHFDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name SPIFICLKDIV - SPIFI clock divider */\r
+/*! @{ */\r
+#define SYSCON_SPIFICLKDIV_DIV_MASK (0xFFU)\r
+#define SYSCON_SPIFICLKDIV_DIV_SHIFT (0U)\r
+/*! DIV - Clock divider value.\r
+ */\r
+#define SYSCON_SPIFICLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_DIV_SHIFT)) & SYSCON_SPIFICLKDIV_DIV_MASK)\r
+#define SYSCON_SPIFICLKDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_SPIFICLKDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right\r
+ * away rather than completing the previous count.\r
+ */\r
+#define SYSCON_SPIFICLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_RESET_SHIFT)) & SYSCON_SPIFICLKDIV_RESET_MASK)\r
+#define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_SPIFICLKDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed\r
+ * without the risk of a glitch at the output.\r
+ */\r
+#define SYSCON_SPIFICLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)\r
+#define SYSCON_SPIFICLKDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_SPIFICLKDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ */\r
+#define SYSCON_SPIFICLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_REQFLAG_SHIFT)) & SYSCON_SPIFICLKDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name ADCCLKDIV - ADC clock divider */\r
+/*! @{ */\r
+#define SYSCON_ADCCLKDIV_DIV_MASK (0xFFU)\r
+#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U)\r
+/*! DIV - Clock divider value.\r
+ */\r
+#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK)\r
+#define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_ADCCLKDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter.\r
+ */\r
+#define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK)\r
+#define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_ADCCLKDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter.\r
+ */\r
+#define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK)\r
+#define SYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ */\r
+#define SYSCON_ADCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name USB0CLKDIV - USB0 clock divider */\r
+/*! @{ */\r
+#define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU)\r
+#define SYSCON_USB0CLKDIV_DIV_SHIFT (0U)\r
+/*! DIV - Clock divider value.\r
+ */\r
+#define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK)\r
+#define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_USB0CLKDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter.\r
+ */\r
+#define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK)\r
+#define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_USB0CLKDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter.\r
+ */\r
+#define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK)\r
+#define SYSCON_USB0CLKDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_USB0CLKDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ */\r
+#define SYSCON_USB0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name USB1CLKDIV - USB1 clock divider */\r
+/*! @{ */\r
+#define SYSCON_USB1CLKDIV_DIV_MASK (0xFFU)\r
+#define SYSCON_USB1CLKDIV_DIV_SHIFT (0U)\r
+/*! DIV - Clock divider value.\r
+ */\r
+#define SYSCON_USB1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_DIV_SHIFT)) & SYSCON_USB1CLKDIV_DIV_MASK)\r
+#define SYSCON_USB1CLKDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_USB1CLKDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter.\r
+ */\r
+#define SYSCON_USB1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_RESET_SHIFT)) & SYSCON_USB1CLKDIV_RESET_MASK)\r
+#define SYSCON_USB1CLKDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_USB1CLKDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter.\r
+ */\r
+#define SYSCON_USB1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_HALT_SHIFT)) & SYSCON_USB1CLKDIV_HALT_MASK)\r
+#define SYSCON_USB1CLKDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_USB1CLKDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ */\r
+#define SYSCON_USB1CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB1CLKDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name FRGCTRL - Fractional rate divider */\r
+/*! @{ */\r
+#define SYSCON_FRGCTRL_DIV_MASK (0xFFU)\r
+#define SYSCON_FRGCTRL_DIV_SHIFT (0U)\r
+/*! DIV - Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set\r
+ * to 0xFF to use with the fractional baud rate generator.\r
+ */\r
+#define SYSCON_FRGCTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_DIV_SHIFT)) & SYSCON_FRGCTRL_DIV_MASK)\r
+#define SYSCON_FRGCTRL_MULT_MASK (0xFF00U)\r
+#define SYSCON_FRGCTRL_MULT_SHIFT (8U)\r
+/*! MULT - Numerator of the fractional divider. MULT is equal to the programmed value.\r
+ */\r
+#define SYSCON_FRGCTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_MULT_SHIFT)) & SYSCON_FRGCTRL_MULT_MASK)\r
+/*! @} */\r
+\r
+/*! @name DMICCLKDIV - DMIC clock divider */\r
+/*! @{ */\r
+#define SYSCON_DMICCLKDIV_DIV_MASK (0xFFU)\r
+#define SYSCON_DMICCLKDIV_DIV_SHIFT (0U)\r
+/*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256.\r
+ */\r
+#define SYSCON_DMICCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_DIV_SHIFT)) & SYSCON_DMICCLKDIV_DIV_MASK)\r
+#define SYSCON_DMICCLKDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_DMICCLKDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right\r
+ * away rather than completing the previous count.\r
+ */\r
+#define SYSCON_DMICCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_RESET_SHIFT)) & SYSCON_DMICCLKDIV_RESET_MASK)\r
+#define SYSCON_DMICCLKDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_DMICCLKDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed\r
+ * without the risk of a glitch at the output.\r
+ */\r
+#define SYSCON_DMICCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_HALT_SHIFT)) & SYSCON_DMICCLKDIV_HALT_MASK)\r
+#define SYSCON_DMICCLKDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_DMICCLKDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ */\r
+#define SYSCON_DMICCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_REQFLAG_SHIFT)) & SYSCON_DMICCLKDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name MCLKDIV - I2S MCLK clock divider */\r
+/*! @{ */\r
+#define SYSCON_MCLKDIV_DIV_MASK (0xFFU)\r
+#define SYSCON_MCLKDIV_DIV_SHIFT (0U)\r
+/*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256.\r
+ */\r
+#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK)\r
+#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_MCLKDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter.\r
+ */\r
+#define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK)\r
+#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_MCLKDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter.\r
+ */\r
+#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK)\r
+#define SYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_MCLKDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ */\r
+#define SYSCON_MCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name LCDCLKDIV - LCD clock divider */\r
+/*! @{ */\r
+#define SYSCON_LCDCLKDIV_DIV_MASK (0xFFU)\r
+#define SYSCON_LCDCLKDIV_DIV_SHIFT (0U)\r
+/*! DIV - Clock divider value.\r
+ */\r
+#define SYSCON_LCDCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_DIV_SHIFT)) & SYSCON_LCDCLKDIV_DIV_MASK)\r
+#define SYSCON_LCDCLKDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_LCDCLKDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter.\r
+ */\r
+#define SYSCON_LCDCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_RESET_SHIFT)) & SYSCON_LCDCLKDIV_RESET_MASK)\r
+#define SYSCON_LCDCLKDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_LCDCLKDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter.\r
+ */\r
+#define SYSCON_LCDCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_HALT_SHIFT)) & SYSCON_LCDCLKDIV_HALT_MASK)\r
+#define SYSCON_LCDCLKDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_LCDCLKDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ */\r
+#define SYSCON_LCDCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_REQFLAG_SHIFT)) & SYSCON_LCDCLKDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name SCTCLKDIV - SCT/PWM clock divider */\r
+/*! @{ */\r
+#define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU)\r
+#define SYSCON_SCTCLKDIV_DIV_SHIFT (0U)\r
+/*! DIV - Clock divider value.\r
+ */\r
+#define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK)\r
+#define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_SCTCLKDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter.\r
+ */\r
+#define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK)\r
+#define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_SCTCLKDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter.\r
+ */\r
+#define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK)\r
+#define SYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ */\r
+#define SYSCON_SCTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name EMCCLKDIV - EMC clock divider */\r
+/*! @{ */\r
+#define SYSCON_EMCCLKDIV_DIV_MASK (0xFFU)\r
+#define SYSCON_EMCCLKDIV_DIV_SHIFT (0U)\r
+/*! DIV - Clock divider value.\r
+ */\r
+#define SYSCON_EMCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_DIV_SHIFT)) & SYSCON_EMCCLKDIV_DIV_MASK)\r
+#define SYSCON_EMCCLKDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_EMCCLKDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter.\r
+ */\r
+#define SYSCON_EMCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_RESET_SHIFT)) & SYSCON_EMCCLKDIV_RESET_MASK)\r
+#define SYSCON_EMCCLKDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_EMCCLKDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter.\r
+ */\r
+#define SYSCON_EMCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_HALT_SHIFT)) & SYSCON_EMCCLKDIV_HALT_MASK)\r
+#define SYSCON_EMCCLKDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_EMCCLKDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ */\r
+#define SYSCON_EMCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_REQFLAG_SHIFT)) & SYSCON_EMCCLKDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name SDIOCLKDIV - SDIO clock divider */\r
+/*! @{ */\r
+#define SYSCON_SDIOCLKDIV_DIV_MASK (0xFFU)\r
+#define SYSCON_SDIOCLKDIV_DIV_SHIFT (0U)\r
+/*! DIV - Clock divider value.\r
+ */\r
+#define SYSCON_SDIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK)\r
+#define SYSCON_SDIOCLKDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_SDIOCLKDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter.\r
+ */\r
+#define SYSCON_SDIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK)\r
+#define SYSCON_SDIOCLKDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_SDIOCLKDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter.\r
+ */\r
+#define SYSCON_SDIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK)\r
+#define SYSCON_SDIOCLKDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ */\r
+#define SYSCON_SDIOCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name USB0CLKCTRL - USB0 clock control */\r
+/*! @{ */\r
+#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK (0x1U)\r
+#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT (0U)\r
+/*! AP_FS_DEV_CLK - USB0 Device USB0_NEEDCLK signal control.\r
+ */\r
+#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK)\r
+#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK (0x2U)\r
+#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT (1U)\r
+/*! POL_FS_DEV_CLK - USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt.\r
+ */\r
+#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK)\r
+#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK (0x4U)\r
+#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT (2U)\r
+/*! AP_FS_HOST_CLK - USB0 Host USB0_NEEDCLK signal control.\r
+ */\r
+#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK)\r
+#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK (0x8U)\r
+#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U)\r
+/*! POL_FS_HOST_CLK - USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt.\r
+ */\r
+#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK)\r
+#define SYSCON_USB0CLKCTRL_PU_DISABLE_MASK (0x10U)\r
+#define SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT (4U)\r
+/*! PU_DISABLE - Internal pull-up disable control.\r
+ */\r
+#define SYSCON_USB0CLKCTRL_PU_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT)) & SYSCON_USB0CLKCTRL_PU_DISABLE_MASK)\r
+/*! @} */\r
+\r
+/*! @name USB0CLKSTAT - USB0 clock status */\r
+/*! @{ */\r
+#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK (0x1U)\r
+#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT (0U)\r
+/*! DEV_NEED_CLKST - USB0 Device USB0_NEEDCLK signal status.\r
+ */\r
+#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK)\r
+#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK (0x2U)\r
+#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT (1U)\r
+/*! HOST_NEED_CLKST - USB0 Host USB0_NEEDCLK signal status.\r
+ */\r
+#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK)\r
+/*! @} */\r
+\r
+/*! @name FREQMECTRL - Frequency measure register */\r
+/*! @{ */\r
+#define SYSCON_FREQMECTRL_CAPVAL_MASK (0x3FFFU)\r
+#define SYSCON_FREQMECTRL_CAPVAL_SHIFT (0U)\r
+/*! CAPVAL - Stores the capture result which is used to calculate the frequency of the target clock. This field is read-only.\r
+ */\r
+#define SYSCON_FREQMECTRL_CAPVAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_CAPVAL_SHIFT)) & SYSCON_FREQMECTRL_CAPVAL_MASK)\r
+#define SYSCON_FREQMECTRL_PROG_MASK (0x80000000U)\r
+#define SYSCON_FREQMECTRL_PROG_SHIFT (31U)\r
+/*! PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit\r
+ * when the measurement cycle has completed and there is valid capture data in the CAPVAL field\r
+ * (bits 13:0).\r
+ */\r
+#define SYSCON_FREQMECTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_PROG_SHIFT)) & SYSCON_FREQMECTRL_PROG_MASK)\r
+/*! @} */\r
+\r
+/*! @name MCLKIO - MCLK input/output control */\r
+/*! @{ */\r
+#define SYSCON_MCLKIO_DIR_MASK (0x1U)\r
+#define SYSCON_MCLKIO_DIR_SHIFT (0U)\r
+/*! DIR - MCLK direction control.\r
+ */\r
+#define SYSCON_MCLKIO_DIR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_DIR_SHIFT)) & SYSCON_MCLKIO_DIR_MASK)\r
+/*! @} */\r
+\r
+/*! @name USB1CLKCTRL - USB1 clock control */\r
+/*! @{ */\r
+#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_MASK (0x1U)\r
+#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_SHIFT (0U)\r
+/*! AP_FS_DEV_CLK - USB1 Device need_clock signal control.\r
+ */\r
+#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_MASK)\r
+#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_MASK (0x2U)\r
+#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_SHIFT (1U)\r
+/*! POL_FS_DEV_CLK - USB1 Device need_clock polarity for triggering the USB1 wake-up interrupt.\r
+ */\r
+#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_MASK)\r
+#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_MASK (0x4U)\r
+#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_SHIFT (2U)\r
+/*! AP_FS_HOST_CLK - USB1 Host need_clock signal control.\r
+ */\r
+#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_MASK)\r
+#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_MASK (0x8U)\r
+#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U)\r
+/*! POL_FS_HOST_CLK - USB1 Host need_clock polarity for triggering the USB1 wake-up interrupt.\r
+ */\r
+#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_MASK)\r
+#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U)\r
+#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U)\r
+/*! HS_DEV_WAKEUP_N - External user wake-up signal for device mode; asserting this signal (active\r
+ * low) will result in exiting the low power mode; input to asynchronous control logic.\r
+ */\r
+#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK)\r
+/*! @} */\r
+\r
+/*! @name USB1CLKSTAT - USB1 clock status */\r
+/*! @{ */\r
+#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK (0x1U)\r
+#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT (0U)\r
+/*! DEV_NEED_CLKST - USB1 Device USB1_NEEDCLK signal status.\r
+ */\r
+#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK)\r
+#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK (0x2U)\r
+#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT (1U)\r
+/*! HOST_NEED_CLKST - USB1 Device host USB1_NEEDCLK signal status.\r
+ */\r
+#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK)\r
+/*! @} */\r
+\r
+/*! @name EMCSYSCTRL - EMC system control */\r
+/*! @{ */\r
+#define SYSCON_EMCSYSCTRL_EMCSC_MASK (0x1U)\r
+#define SYSCON_EMCSYSCTRL_EMCSC_SHIFT (0U)\r
+/*! EMCSC - EMC Shift Control.\r
+ */\r
+#define SYSCON_EMCSYSCTRL_EMCSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCSC_SHIFT)) & SYSCON_EMCSYSCTRL_EMCSC_MASK)\r
+#define SYSCON_EMCSYSCTRL_EMCRD_MASK (0x2U)\r
+#define SYSCON_EMCSYSCTRL_EMCRD_SHIFT (1U)\r
+/*! EMCRD - EMC Reset Disable.\r
+ */\r
+#define SYSCON_EMCSYSCTRL_EMCRD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCRD_SHIFT)) & SYSCON_EMCSYSCTRL_EMCRD_MASK)\r
+#define SYSCON_EMCSYSCTRL_EMCBC_MASK (0x4U)\r
+#define SYSCON_EMCSYSCTRL_EMCBC_SHIFT (2U)\r
+/*! EMCBC - External Memory Controller burst control.\r
+ */\r
+#define SYSCON_EMCSYSCTRL_EMCBC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCBC_SHIFT)) & SYSCON_EMCSYSCTRL_EMCBC_MASK)\r
+#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_MASK (0x8U)\r
+#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_SHIFT (3U)\r
+/*! EMCFBCLKINSEL - External Memory Controller clock select.\r
+ */\r
+#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_SHIFT)) & SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name EMCDYCTRL - EMC clock delay control */\r
+/*! @{ */\r
+#define SYSCON_EMCDYCTRL_CMD_DELAY_MASK (0x1FU)\r
+#define SYSCON_EMCDYCTRL_CMD_DELAY_SHIFT (0U)\r
+/*! CMD_DELAY - Programmable delay value for EMC outputs in command delayed mode.\r
+ */\r
+#define SYSCON_EMCDYCTRL_CMD_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDYCTRL_CMD_DELAY_SHIFT)) & SYSCON_EMCDYCTRL_CMD_DELAY_MASK)\r
+#define SYSCON_EMCDYCTRL_FBCLK_DELAY_MASK (0x1F00U)\r
+#define SYSCON_EMCDYCTRL_FBCLK_DELAY_SHIFT (8U)\r
+/*! FBCLK_DELAY - Programmable delay value for the feedback clock that controls input data sampling.\r
+ */\r
+#define SYSCON_EMCDYCTRL_FBCLK_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDYCTRL_FBCLK_DELAY_SHIFT)) & SYSCON_EMCDYCTRL_FBCLK_DELAY_MASK)\r
+/*! @} */\r
+\r
+/*! @name EMCCAL - EMC delay chain calibration control */\r
+/*! @{ */\r
+#define SYSCON_EMCCAL_CALVALUE_MASK (0xFFU)\r
+#define SYSCON_EMCCAL_CALVALUE_SHIFT (0U)\r
+/*! CALVALUE - Returns the count of the approximately 50 MHz ring oscillator that occur during 32 clocks of the FRO 12 MHz.\r
+ */\r
+#define SYSCON_EMCCAL_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCAL_CALVALUE_SHIFT)) & SYSCON_EMCCAL_CALVALUE_MASK)\r
+#define SYSCON_EMCCAL_START_MASK (0x4000U)\r
+#define SYSCON_EMCCAL_START_SHIFT (14U)\r
+/*! START - Start control bit for the EMC calibration counter.\r
+ */\r
+#define SYSCON_EMCCAL_START(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCAL_START_SHIFT)) & SYSCON_EMCCAL_START_MASK)\r
+#define SYSCON_EMCCAL_DONE_MASK (0x8000U)\r
+#define SYSCON_EMCCAL_DONE_SHIFT (15U)\r
+/*! DONE - Measurement completion flag.\r
+ */\r
+#define SYSCON_EMCCAL_DONE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCAL_DONE_SHIFT)) & SYSCON_EMCCAL_DONE_MASK)\r
+/*! @} */\r
+\r
+/*! @name ETHPHYSEL - Ethernet PHY Selection */\r
+/*! @{ */\r
+#define SYSCON_ETHPHYSEL_PHY_SEL_MASK (0x4U)\r
+#define SYSCON_ETHPHYSEL_PHY_SEL_SHIFT (2U)\r
+/*! PHY_SEL - PHY interface select.\r
+ */\r
+#define SYSCON_ETHPHYSEL_PHY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ETHPHYSEL_PHY_SEL_SHIFT)) & SYSCON_ETHPHYSEL_PHY_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name ETHSBDCTRL - Ethernet SBD flow control */\r
+/*! @{ */\r
+#define SYSCON_ETHSBDCTRL_SBD_CTRL_MASK (0x3U)\r
+#define SYSCON_ETHSBDCTRL_SBD_CTRL_SHIFT (0U)\r
+/*! SBD_CTRL - Sideband Flow Control.\r
+ */\r
+#define SYSCON_ETHSBDCTRL_SBD_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ETHSBDCTRL_SBD_CTRL_SHIFT)) & SYSCON_ETHSBDCTRL_SBD_CTRL_MASK)\r
+/*! @} */\r
+\r
+/*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */\r
+/*! @{ */\r
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U)\r
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT (0U)\r
+/*! CCLK_DRV_PHASE - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in.\r
+ */\r
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)\r
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU)\r
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U)\r
+/*! CCLK_SAMPLE_PHASE - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.\r
+ */\r
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)\r
+#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U)\r
+#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT (7U)\r
+/*! PHASE_ACTIVE - sdio_clk by 2, before feeding into ccl_in, cclk_in_sample, and cclk_in_drv.\r
+ */\r
+#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)\r
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK (0x1F0000U)\r
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT (16U)\r
+/*! CCLK_DRV_DELAY - Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in.\r
+ */\r
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK)\r
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U)\r
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U)\r
+/*! CCLK_DRV_DELAY_ACTIVE - Enables drive delay, as controlled by the CCLK_DRV_DELAY field.\r
+ */\r
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK)\r
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U)\r
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U)\r
+/*! CCLK_SAMPLE_DELAY - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.\r
+ */\r
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK)\r
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U)\r
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U)\r
+/*! CCLK_SAMPLE_DELAY_ACTIVE - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field.\r
+ */\r
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK)\r
+/*! @} */\r
+\r
+/*! @name KEYMUXSEL - AES key source selection */\r
+/*! @{ */\r
+#define SYSCON_KEYMUXSEL_SEL_MASK (0x3U)\r
+#define SYSCON_KEYMUXSEL_SEL_SHIFT (0U)\r
+/*! SEL - PHY interface select.\r
+ */\r
+#define SYSCON_KEYMUXSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEYMUXSEL_SEL_SHIFT)) & SYSCON_KEYMUXSEL_SEL_MASK)\r
+#define SYSCON_KEYMUXSEL_LOCK_MASK (0x80U)\r
+#define SYSCON_KEYMUXSEL_LOCK_SHIFT (7U)\r
+/*! LOCK - LOCK stat.\r
+ */\r
+#define SYSCON_KEYMUXSEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEYMUXSEL_LOCK_SHIFT)) & SYSCON_KEYMUXSEL_LOCK_MASK)\r
+/*! @} */\r
+\r
+/*! @name FROCTRL - FRO oscillator control */\r
+/*! @{ */\r
+#define SYSCON_FROCTRL_SEL_MASK (0x4000U)\r
+#define SYSCON_FROCTRL_SEL_SHIFT (14U)\r
+/*! SEL - Select the FRO HF output frequency.\r
+ */\r
+#define SYSCON_FROCTRL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_SEL_SHIFT)) & SYSCON_FROCTRL_SEL_MASK)\r
+#define SYSCON_FROCTRL_FREQTRIM_MASK (0xFF0000U)\r
+#define SYSCON_FROCTRL_FREQTRIM_SHIFT (16U)\r
+/*! FREQTRIM - Frequency trim.\r
+ */\r
+#define SYSCON_FROCTRL_FREQTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_FREQTRIM_SHIFT)) & SYSCON_FROCTRL_FREQTRIM_MASK)\r
+#define SYSCON_FROCTRL_USBCLKADJ_MASK (0x1000000U)\r
+#define SYSCON_FROCTRL_USBCLKADJ_SHIFT (24U)\r
+/*! USBCLKADJ - USB clock adjust mode.\r
+ */\r
+#define SYSCON_FROCTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBCLKADJ_SHIFT)) & SYSCON_FROCTRL_USBCLKADJ_MASK)\r
+#define SYSCON_FROCTRL_USBMODCHG_MASK (0x2000000U)\r
+#define SYSCON_FROCTRL_USBMODCHG_SHIFT (25U)\r
+/*! USBMODCHG - USB Mode value Change flag.\r
+ */\r
+#define SYSCON_FROCTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBMODCHG_SHIFT)) & SYSCON_FROCTRL_USBMODCHG_MASK)\r
+#define SYSCON_FROCTRL_HSPDCLK_MASK (0x40000000U)\r
+#define SYSCON_FROCTRL_HSPDCLK_SHIFT (30U)\r
+/*! HSPDCLK - High speed clock enable.\r
+ */\r
+#define SYSCON_FROCTRL_HSPDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_HSPDCLK_SHIFT)) & SYSCON_FROCTRL_HSPDCLK_MASK)\r
+/*! @} */\r
+\r
+/*! @name SYSOSCCTRL - System oscillator control */\r
+/*! @{ */\r
+#define SYSCON_SYSOSCCTRL_FREQRANGE_MASK (0x2U)\r
+#define SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT (1U)\r
+/*! FREQRANGE - Determines frequency range for system oscillator.\r
+ */\r
+#define SYSCON_SYSOSCCTRL_FREQRANGE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT)) & SYSCON_SYSOSCCTRL_FREQRANGE_MASK)\r
+/*! @} */\r
+\r
+/*! @name WDTOSCCTRL - Watchdog oscillator control */\r
+/*! @{ */\r
+#define SYSCON_WDTOSCCTRL_DIVSEL_MASK (0x1FU)\r
+#define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT (0U)\r
+/*! DIVSEL - Divider select.\r
+ */\r
+#define SYSCON_WDTOSCCTRL_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)) & SYSCON_WDTOSCCTRL_DIVSEL_MASK)\r
+#define SYSCON_WDTOSCCTRL_FREQSEL_MASK (0x3E0U)\r
+#define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT (5U)\r
+/*! FREQSEL - Frequency select.\r
+ */\r
+#define SYSCON_WDTOSCCTRL_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)) & SYSCON_WDTOSCCTRL_FREQSEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name RTCOSCCTRL - RTC oscillator 32 kHz output control */\r
+/*! @{ */\r
+#define SYSCON_RTCOSCCTRL_EN_MASK (0x1U)\r
+#define SYSCON_RTCOSCCTRL_EN_SHIFT (0U)\r
+/*! EN - RTC 32 kHz clock enable.\r
+ */\r
+#define SYSCON_RTCOSCCTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RTCOSCCTRL_EN_SHIFT)) & SYSCON_RTCOSCCTRL_EN_MASK)\r
+/*! @} */\r
+\r
+/*! @name USBPLLCTRL - USB PLL control */\r
+/*! @{ */\r
+#define SYSCON_USBPLLCTRL_MSEL_MASK (0xFFU)\r
+#define SYSCON_USBPLLCTRL_MSEL_SHIFT (0U)\r
+/*! MSEL - PLL feedback Divider value.\r
+ */\r
+#define SYSCON_USBPLLCTRL_MSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_MSEL_SHIFT)) & SYSCON_USBPLLCTRL_MSEL_MASK)\r
+#define SYSCON_USBPLLCTRL_PSEL_MASK (0x300U)\r
+#define SYSCON_USBPLLCTRL_PSEL_SHIFT (8U)\r
+/*! PSEL - PLL Divider value.\r
+ */\r
+#define SYSCON_USBPLLCTRL_PSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_PSEL_SHIFT)) & SYSCON_USBPLLCTRL_PSEL_MASK)\r
+#define SYSCON_USBPLLCTRL_NSEL_MASK (0xC00U)\r
+#define SYSCON_USBPLLCTRL_NSEL_SHIFT (10U)\r
+/*! NSEL - PLL feedback Divider value.\r
+ */\r
+#define SYSCON_USBPLLCTRL_NSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_NSEL_SHIFT)) & SYSCON_USBPLLCTRL_NSEL_MASK)\r
+#define SYSCON_USBPLLCTRL_DIRECT_MASK (0x1000U)\r
+#define SYSCON_USBPLLCTRL_DIRECT_SHIFT (12U)\r
+/*! DIRECT - Direct CCO clock output control.\r
+ * 0b0..CCO Clock signal goes through post divider.\r
+ * 0b1..CCO Clock signal goes directly to output(s)..\r
+ */\r
+#define SYSCON_USBPLLCTRL_DIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_DIRECT_SHIFT)) & SYSCON_USBPLLCTRL_DIRECT_MASK)\r
+#define SYSCON_USBPLLCTRL_BYPASS_MASK (0x2000U)\r
+#define SYSCON_USBPLLCTRL_BYPASS_SHIFT (13U)\r
+/*! BYPASS - Input clock bypass control.\r
+ * 0b0..CCO clock is sent to post dividers..\r
+ * 0b1..PLL input clock is sent to post dividers..\r
+ */\r
+#define SYSCON_USBPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_BYPASS_SHIFT)) & SYSCON_USBPLLCTRL_BYPASS_MASK)\r
+#define SYSCON_USBPLLCTRL_FBSEL_MASK (0x4000U)\r
+#define SYSCON_USBPLLCTRL_FBSEL_SHIFT (14U)\r
+/*! FBSEL - Feedback divider input clock control.\r
+ */\r
+#define SYSCON_USBPLLCTRL_FBSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_FBSEL_SHIFT)) & SYSCON_USBPLLCTRL_FBSEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name USBPLLSTAT - USB PLL status */\r
+/*! @{ */\r
+#define SYSCON_USBPLLSTAT_LOCK_MASK (0x1U)\r
+#define SYSCON_USBPLLSTAT_LOCK_SHIFT (0U)\r
+/*! LOCK - USBPLL lock indicator.\r
+ */\r
+#define SYSCON_USBPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLSTAT_LOCK_SHIFT)) & SYSCON_USBPLLSTAT_LOCK_MASK)\r
+/*! @} */\r
+\r
+/*! @name SYSPLLCTRL - System PLL control */\r
+/*! @{ */\r
+#define SYSCON_SYSPLLCTRL_SELR_MASK (0xFU)\r
+#define SYSCON_SYSPLLCTRL_SELR_SHIFT (0U)\r
+/*! SELR - Bandwidth select R value.\r
+ */\r
+#define SYSCON_SYSPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELR_SHIFT)) & SYSCON_SYSPLLCTRL_SELR_MASK)\r
+#define SYSCON_SYSPLLCTRL_SELI_MASK (0x3F0U)\r
+#define SYSCON_SYSPLLCTRL_SELI_SHIFT (4U)\r
+/*! SELI - Bandwidth select I value.\r
+ */\r
+#define SYSCON_SYSPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELI_SHIFT)) & SYSCON_SYSPLLCTRL_SELI_MASK)\r
+#define SYSCON_SYSPLLCTRL_SELP_MASK (0x7C00U)\r
+#define SYSCON_SYSPLLCTRL_SELP_SHIFT (10U)\r
+/*! SELP - Bandwidth select P value.\r
+ */\r
+#define SYSCON_SYSPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELP_SHIFT)) & SYSCON_SYSPLLCTRL_SELP_MASK)\r
+#define SYSCON_SYSPLLCTRL_BYPASS_MASK (0x8000U)\r
+#define SYSCON_SYSPLLCTRL_BYPASS_SHIFT (15U)\r
+/*! BYPASS - PLL bypass control.\r
+ * 0b0..Bypass disabled. PLL CCO is sent to the PLL post-dividers.\r
+ * 0b1..Bypass enabled. PLL input clock is sent directly to the PLL output (default).\r
+ */\r
+#define SYSCON_SYSPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASS_MASK)\r
+#define SYSCON_SYSPLLCTRL_UPLIMOFF_MASK (0x20000U)\r
+#define SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT (17U)\r
+/*! UPLIMOFF - Disable upper frequency limiter.\r
+ */\r
+#define SYSCON_SYSPLLCTRL_UPLIMOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_SYSPLLCTRL_UPLIMOFF_MASK)\r
+#define SYSCON_SYSPLLCTRL_DIRECTI_MASK (0x80000U)\r
+#define SYSCON_SYSPLLCTRL_DIRECTI_SHIFT (19U)\r
+/*! DIRECTI - PLL0 direct input enable.\r
+ */\r
+#define SYSCON_SYSPLLCTRL_DIRECTI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTI_MASK)\r
+#define SYSCON_SYSPLLCTRL_DIRECTO_MASK (0x100000U)\r
+#define SYSCON_SYSPLLCTRL_DIRECTO_SHIFT (20U)\r
+/*! DIRECTO - PLL0 direct output enable.\r
+ * 0b0..Disabled. The PLL output divider (P divider) is used to create the PLL output.\r
+ * 0b1..Enabled. The PLL output divider (P divider) is bypassed, the PLL CCO output is used as the PLL output.\r
+ */\r
+#define SYSCON_SYSPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTO_MASK)\r
+/*! @} */\r
+\r
+/*! @name SYSPLLSTAT - PLL status */\r
+/*! @{ */\r
+#define SYSCON_SYSPLLSTAT_LOCK_MASK (0x1U)\r
+#define SYSCON_SYSPLLSTAT_LOCK_SHIFT (0U)\r
+/*! LOCK - PLL lock indicator.\r
+ */\r
+#define SYSCON_SYSPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSTAT_LOCK_SHIFT)) & SYSCON_SYSPLLSTAT_LOCK_MASK)\r
+/*! @} */\r
+\r
+/*! @name SYSPLLNDEC - PLL N divider */\r
+/*! @{ */\r
+#define SYSCON_SYSPLLNDEC_NDEC_MASK (0x3FFU)\r
+#define SYSCON_SYSPLLNDEC_NDEC_SHIFT (0U)\r
+/*! NDEC - Decoded N-divider coefficient value.\r
+ */\r
+#define SYSCON_SYSPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NDEC_SHIFT)) & SYSCON_SYSPLLNDEC_NDEC_MASK)\r
+#define SYSCON_SYSPLLNDEC_NREQ_MASK (0x400U)\r
+#define SYSCON_SYSPLLNDEC_NREQ_SHIFT (10U)\r
+/*! NREQ - NDEC reload request.\r
+ */\r
+#define SYSCON_SYSPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NREQ_SHIFT)) & SYSCON_SYSPLLNDEC_NREQ_MASK)\r
+/*! @} */\r
+\r
+/*! @name SYSPLLPDEC - PLL P divider */\r
+/*! @{ */\r
+#define SYSCON_SYSPLLPDEC_PDEC_MASK (0x7FU)\r
+#define SYSCON_SYSPLLPDEC_PDEC_SHIFT (0U)\r
+/*! PDEC - Decoded P-divider coefficient value.\r
+ */\r
+#define SYSCON_SYSPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PDEC_SHIFT)) & SYSCON_SYSPLLPDEC_PDEC_MASK)\r
+#define SYSCON_SYSPLLPDEC_PREQ_MASK (0x80U)\r
+#define SYSCON_SYSPLLPDEC_PREQ_SHIFT (7U)\r
+/*! PREQ - .\r
+ */\r
+#define SYSCON_SYSPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PREQ_SHIFT)) & SYSCON_SYSPLLPDEC_PREQ_MASK)\r
+/*! @} */\r
+\r
+/*! @name SYSPLLMDEC - System PLL M divider */\r
+/*! @{ */\r
+#define SYSCON_SYSPLLMDEC_MDEC_MASK (0x1FFFFU)\r
+#define SYSCON_SYSPLLMDEC_MDEC_SHIFT (0U)\r
+/*! MDEC - Decoded M-divider coefficient value.\r
+ */\r
+#define SYSCON_SYSPLLMDEC_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLMDEC_MDEC_SHIFT)) & SYSCON_SYSPLLMDEC_MDEC_MASK)\r
+#define SYSCON_SYSPLLMDEC_MREQ_MASK (0x20000U)\r
+#define SYSCON_SYSPLLMDEC_MREQ_SHIFT (17U)\r
+/*! MREQ - MDEC reload request.\r
+ */\r
+#define SYSCON_SYSPLLMDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLMDEC_MREQ_SHIFT)) & SYSCON_SYSPLLMDEC_MREQ_MASK)\r
+/*! @} */\r
+\r
+/*! @name AUDPLLCTRL - Audio PLL control */\r
+/*! @{ */\r
+#define SYSCON_AUDPLLCTRL_SELR_MASK (0xFU)\r
+#define SYSCON_AUDPLLCTRL_SELR_SHIFT (0U)\r
+/*! SELR - Bandwidth select R value.\r
+ */\r
+#define SYSCON_AUDPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELR_SHIFT)) & SYSCON_AUDPLLCTRL_SELR_MASK)\r
+#define SYSCON_AUDPLLCTRL_SELI_MASK (0x3F0U)\r
+#define SYSCON_AUDPLLCTRL_SELI_SHIFT (4U)\r
+/*! SELI - Bandwidth select I value.\r
+ */\r
+#define SYSCON_AUDPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELI_SHIFT)) & SYSCON_AUDPLLCTRL_SELI_MASK)\r
+#define SYSCON_AUDPLLCTRL_SELP_MASK (0x7C00U)\r
+#define SYSCON_AUDPLLCTRL_SELP_SHIFT (10U)\r
+/*! SELP - .\r
+ */\r
+#define SYSCON_AUDPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELP_SHIFT)) & SYSCON_AUDPLLCTRL_SELP_MASK)\r
+#define SYSCON_AUDPLLCTRL_BYPASS_MASK (0x8000U)\r
+#define SYSCON_AUDPLLCTRL_BYPASS_SHIFT (15U)\r
+/*! BYPASS - PLL bypass control.\r
+ * 0b0..Bypass disabled. PLL CCO is sent to the PLL post-dividers.\r
+ * 0b1..Bypass enabled. PLL input clock is sent directly to the PLL output (default).\r
+ */\r
+#define SYSCON_AUDPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_BYPASS_SHIFT)) & SYSCON_AUDPLLCTRL_BYPASS_MASK)\r
+#define SYSCON_AUDPLLCTRL_UPLIMOFF_MASK (0x20000U)\r
+#define SYSCON_AUDPLLCTRL_UPLIMOFF_SHIFT (17U)\r
+/*! UPLIMOFF - Disable upper frequency limiter.\r
+ */\r
+#define SYSCON_AUDPLLCTRL_UPLIMOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_AUDPLLCTRL_UPLIMOFF_MASK)\r
+#define SYSCON_AUDPLLCTRL_DIRECTI_MASK (0x80000U)\r
+#define SYSCON_AUDPLLCTRL_DIRECTI_SHIFT (19U)\r
+/*! DIRECTI - PLL direct input enable.\r
+ */\r
+#define SYSCON_AUDPLLCTRL_DIRECTI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_DIRECTI_SHIFT)) & SYSCON_AUDPLLCTRL_DIRECTI_MASK)\r
+#define SYSCON_AUDPLLCTRL_DIRECTO_MASK (0x100000U)\r
+#define SYSCON_AUDPLLCTRL_DIRECTO_SHIFT (20U)\r
+/*! DIRECTO - PLL direct output enable\r
+ * 0b0..Disabled. The PLL output divider (P divider) is used to create the PLL output.\r
+ * 0b1..Enabled. The PLL output divider (P divider) is bypassed, the PLL CCO output is used as the PLL output.\r
+ */\r
+#define SYSCON_AUDPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_DIRECTO_SHIFT)) & SYSCON_AUDPLLCTRL_DIRECTO_MASK)\r
+/*! @} */\r
+\r
+/*! @name AUDPLLSTAT - Audio PLL status */\r
+/*! @{ */\r
+#define SYSCON_AUDPLLSTAT_LOCK_MASK (0x1U)\r
+#define SYSCON_AUDPLLSTAT_LOCK_SHIFT (0U)\r
+/*! LOCK - PLL lock indicator.\r
+ */\r
+#define SYSCON_AUDPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLSTAT_LOCK_SHIFT)) & SYSCON_AUDPLLSTAT_LOCK_MASK)\r
+/*! @} */\r
+\r
+/*! @name AUDPLLNDEC - Audio PLL N divider */\r
+/*! @{ */\r
+#define SYSCON_AUDPLLNDEC_NDEC_MASK (0x3FFU)\r
+#define SYSCON_AUDPLLNDEC_NDEC_SHIFT (0U)\r
+/*! NDEC - Decoded N-divider coefficient value.\r
+ */\r
+#define SYSCON_AUDPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLNDEC_NDEC_SHIFT)) & SYSCON_AUDPLLNDEC_NDEC_MASK)\r
+#define SYSCON_AUDPLLNDEC_NREQ_MASK (0x400U)\r
+#define SYSCON_AUDPLLNDEC_NREQ_SHIFT (10U)\r
+/*! NREQ - NDEC reload request.\r
+ */\r
+#define SYSCON_AUDPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLNDEC_NREQ_SHIFT)) & SYSCON_AUDPLLNDEC_NREQ_MASK)\r
+/*! @} */\r
+\r
+/*! @name AUDPLLPDEC - Audio PLL P divider */\r
+/*! @{ */\r
+#define SYSCON_AUDPLLPDEC_PDEC_MASK (0x7FU)\r
+#define SYSCON_AUDPLLPDEC_PDEC_SHIFT (0U)\r
+/*! PDEC - Decoded P-divider coefficient value.\r
+ */\r
+#define SYSCON_AUDPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLPDEC_PDEC_SHIFT)) & SYSCON_AUDPLLPDEC_PDEC_MASK)\r
+#define SYSCON_AUDPLLPDEC_PREQ_MASK (0x80U)\r
+#define SYSCON_AUDPLLPDEC_PREQ_SHIFT (7U)\r
+/*! PREQ - PDEC reload request.\r
+ */\r
+#define SYSCON_AUDPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLPDEC_PREQ_SHIFT)) & SYSCON_AUDPLLPDEC_PREQ_MASK)\r
+/*! @} */\r
+\r
+/*! @name AUDPLLMDEC - Audio PLL M divider */\r
+/*! @{ */\r
+#define SYSCON_AUDPLLMDEC_MDEC_MASK (0x1FFFFU)\r
+#define SYSCON_AUDPLLMDEC_MDEC_SHIFT (0U)\r
+/*! MDEC - Decoded M-divider coefficient value.\r
+ */\r
+#define SYSCON_AUDPLLMDEC_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLMDEC_MDEC_SHIFT)) & SYSCON_AUDPLLMDEC_MDEC_MASK)\r
+#define SYSCON_AUDPLLMDEC_MREQ_MASK (0x20000U)\r
+#define SYSCON_AUDPLLMDEC_MREQ_SHIFT (17U)\r
+/*! MREQ - MDEC reload request.\r
+ */\r
+#define SYSCON_AUDPLLMDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLMDEC_MREQ_SHIFT)) & SYSCON_AUDPLLMDEC_MREQ_MASK)\r
+/*! @} */\r
+\r
+/*! @name AUDPLLFRAC - Audio PLL fractional divider control */\r
+/*! @{ */\r
+#define SYSCON_AUDPLLFRAC_CTRL_MASK (0x3FFFFFU)\r
+#define SYSCON_AUDPLLFRAC_CTRL_SHIFT (0U)\r
+/*! CTRL - PLL fractional divider control word\r
+ */\r
+#define SYSCON_AUDPLLFRAC_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_CTRL_SHIFT)) & SYSCON_AUDPLLFRAC_CTRL_MASK)\r
+#define SYSCON_AUDPLLFRAC_REQ_MASK (0x400000U)\r
+#define SYSCON_AUDPLLFRAC_REQ_SHIFT (22U)\r
+/*! REQ - Writing 1 to REQ signal loads CTRL value into fractional wrapper modulator.\r
+ */\r
+#define SYSCON_AUDPLLFRAC_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_REQ_SHIFT)) & SYSCON_AUDPLLFRAC_REQ_MASK)\r
+#define SYSCON_AUDPLLFRAC_SEL_EXT_MASK (0x800000U)\r
+#define SYSCON_AUDPLLFRAC_SEL_EXT_SHIFT (23U)\r
+/*! SEL_EXT - Select fractional divider.\r
+ */\r
+#define SYSCON_AUDPLLFRAC_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_SEL_EXT_SHIFT)) & SYSCON_AUDPLLFRAC_SEL_EXT_MASK)\r
+/*! @} */\r
+\r
+/*! @name PDSLEEPCFG - Sleep configuration register */\r
+/*! @{ */\r
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_MASK (0x1U)\r
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_SHIFT (0U)\r
+/*! PDEN_USB1_PHY - USB1 high speed PHY (also, enable/disable bit 28 in PDRUNCFG0 register).\r
+ */\r
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_MASK)\r
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_MASK (0x2U)\r
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_SHIFT (1U)\r
+/*! PDEN_USB1_PLL - USB PLL (PLL1) power (also, enable/disable bit 26 in PDRUNCFG0 register).\r
+ */\r
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_MASK)\r
+#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_MASK (0x4U)\r
+#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_SHIFT (2U)\r
+/*! PDEN_AUD_PLL - Audio PLL (PLL2) power and fractional divider (also, enable/disable bit 26 in PDRUNCFG0 register).\r
+ */\r
+#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_MASK)\r
+#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC_MASK (0x8U)\r
+#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC_SHIFT (3U)\r
+/*! PDEN_SYSOSC - System Oscillator Power (also, enable/disable bit 9 in PDRUNCFG0 register).\r
+ */\r
+#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SYSOSC_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SYSOSC_MASK)\r
+#define SYSCON_PDSLEEPCFG_PDEN_FRO_MASK (0x10U)\r
+#define SYSCON_PDSLEEPCFG_PDEN_FRO_SHIFT (4U)\r
+/*! PDEN_FRO - FRO oscillator.\r
+ */\r
+#define SYSCON_PDSLEEPCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_FRO_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_FRO_MASK)\r
+#define SYSCON_PDSLEEPCFG_PDEN_TS_MASK (0x40U)\r
+#define SYSCON_PDSLEEPCFG_PDEN_TS_SHIFT (6U)\r
+/*! PDEN_TS - Temp sensor.\r
+ */\r
+#define SYSCON_PDSLEEPCFG_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_TS_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_TS_MASK)\r
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST_MASK (0x80U)\r
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST_SHIFT (7U)\r
+/*! PDEN_BOD_RST - Brown-out Detect reset.\r
+ */\r
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_BOD_RST_MASK)\r
+#define SYSCON_PDSLEEPCFG_PDEN_RNG_MASK (0x80U)\r
+#define SYSCON_PDSLEEPCFG_PDEN_RNG_SHIFT (7U)\r
+/*! PDEN_RNG - Random Number Generator Power.\r
+ */\r
+#define SYSCON_PDSLEEPCFG_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_RNG_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_RNG_MASK)\r
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_MASK (0x100U)\r
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_SHIFT (8U)\r
+/*! PDEN_BOD_INTR - Brown-out Detect interrupt.\r
+ */\r
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_MASK)\r
+#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_MASK (0x200U)\r
+#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_SHIFT (9U)\r
+/*! PDEN_VD2_ANA - Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1\r
+ * register), Temperature Sensor (also, enable/disable bit 6), ADC (also, enable/disable bits 10, 19,\r
+ * and 23).\r
+ */\r
+#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_MASK)\r
+#define SYSCON_PDSLEEPCFG_PDEN_ADC0_MASK (0x400U)\r
+#define SYSCON_PDSLEEPCFG_PDEN_ADC0_SHIFT (10U)\r
+/*! PDEN_ADC0 - ADC power.\r
+ */\r
+#define SYSCON_PDSLEEPCFG_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_ADC0_MASK)\r
+#define SYSCON_PDSLEEPCFG_PDEN_SRAMX_MASK (0x2000U)\r
+#define SYSCON_PDSLEEPCFG_PDEN_SRAMX_SHIFT (13U)\r
+/*! PDEN_SRAMX - PDEN_SRAMX controls SRAMX (also enable/disable bit 27).\r
+ */\r
+#define SYSCON_PDSLEEPCFG_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAMX_MASK)\r
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM0_MASK (0x4000U)\r
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM0_SHIFT (14U)\r
+/*! PDEN_SRAM0 - PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27).\r
+ */\r
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAM0_MASK)\r
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_MASK (0x8000U)\r
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_SHIFT (15U)\r
+/*! PDEN_SRAM1_2_3 - PDEN_SRAM1_2_3 controls SRAM1, SRAM2, and SRAM3 (also enable/disable bit 27).\r
+ */\r
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_MASK)\r
+#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM_MASK (0x10000U)\r
+#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM_SHIFT (16U)\r
+/*! PDEN_USB_RAM - PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27).\r
+ */\r
+#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB_RAM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB_RAM_MASK)\r
+#define SYSCON_PDSLEEPCFG_PDEN_ROM_MASK (0x20000U)\r
+#define SYSCON_PDSLEEPCFG_PDEN_ROM_SHIFT (17U)\r
+/*! PDEN_ROM - ROM (also enable/disable bit 27).\r
+ */\r
+#define SYSCON_PDSLEEPCFG_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_ROM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_ROM_MASK)\r
+#define SYSCON_PDSLEEPCFG_PDEN_VDDA_MASK (0x80000U)\r
+#define SYSCON_PDSLEEPCFG_PDEN_VDDA_SHIFT (19U)\r
+/*! PDEN_VDDA - Vdda to the ADC, must be enabled for the ADC to work (also enable/disable bit 9, 10, and 23).\r
+ */\r
+#define SYSCON_PDSLEEPCFG_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VDDA_MASK)\r
+#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_MASK (0x100000U)\r
+#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_SHIFT (20U)\r
+/*! PDEN_WDT_OSC - Watchdog oscillator.\r
+ */\r
+#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_MASK)\r
+#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_MASK (0x200000U)\r
+#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_SHIFT (21U)\r
+/*! PDEN_USB0_PHY - USB0 PHY power (also enable/disable bit 28).\r
+ */\r
+#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_MASK)\r
+#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_MASK (0x400000U)\r
+#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_SHIFT (22U)\r
+/*! PDEN_SYS_PLL - System PLL (PLL0) power (also enable/disable bit 26).\r
+ */\r
+#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_MASK)\r
+#define SYSCON_PDSLEEPCFG_PDEN_VREFP_MASK (0x800000U)\r
+#define SYSCON_PDSLEEPCFG_PDEN_VREFP_SHIFT (23U)\r
+/*! PDEN_VREFP - VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9, 10, and 19).\r
+ */\r
+#define SYSCON_PDSLEEPCFG_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VREFP_MASK)\r
+#define SYSCON_PDSLEEPCFG_PDEN_VD3_MASK (0x4000000U)\r
+#define SYSCON_PDSLEEPCFG_PDEN_VD3_SHIFT (26U)\r
+/*! PDEN_VD3 - Power control for all PLLs.\r
+ */\r
+#define SYSCON_PDSLEEPCFG_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD3_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD3_MASK)\r
+#define SYSCON_PDSLEEPCFG_PDEN_VD4_MASK (0x8000000U)\r
+#define SYSCON_PDSLEEPCFG_PDEN_VD4_SHIFT (27U)\r
+/*! PDEN_VD4 - Power control for all SRAMs and ROM.\r
+ */\r
+#define SYSCON_PDSLEEPCFG_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD4_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD4_MASK)\r
+#define SYSCON_PDSLEEPCFG_PDEN_VD5_MASK (0x10000000U)\r
+#define SYSCON_PDSLEEPCFG_PDEN_VD5_SHIFT (28U)\r
+/*! PDEN_VD5 - Power control both USB0 PHY and USB1 PHY.\r
+ */\r
+#define SYSCON_PDSLEEPCFG_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD5_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD5_MASK)\r
+#define SYSCON_PDSLEEPCFG_PDEN_VD6_MASK (0x20000000U)\r
+#define SYSCON_PDSLEEPCFG_PDEN_VD6_SHIFT (29U)\r
+/*! PDEN_VD6 - Power control for EEPROM.\r
+ */\r
+#define SYSCON_PDSLEEPCFG_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD6_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD6_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_PDSLEEPCFG */\r
+#define SYSCON_PDSLEEPCFG_COUNT (2U)\r
+\r
+/*! @name PDRUNCFG - Power configuration register */\r
+/*! @{ */\r
+#define SYSCON_PDRUNCFG_PDEN_USB1_PHY_MASK (0x1U)\r
+#define SYSCON_PDRUNCFG_PDEN_USB1_PHY_SHIFT (0U)\r
+/*! PDEN_USB1_PHY - USB1 high speed PHY (also, enable/disable bit 28 in PDRUNCFG0 register).\r
+ */\r
+#define SYSCON_PDRUNCFG_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB1_PHY_MASK)\r
+#define SYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK (0x2U)\r
+#define SYSCON_PDRUNCFG_PDEN_USB1_PLL_SHIFT (1U)\r
+/*! PDEN_USB1_PLL - USB PLL (PLL1) power (also, enable/disable bit 26 in PDRUNCFG0 register).\r
+ */\r
+#define SYSCON_PDRUNCFG_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK)\r
+#define SYSCON_PDRUNCFG_PDEN_AUD_PLL_MASK (0x4U)\r
+#define SYSCON_PDRUNCFG_PDEN_AUD_PLL_SHIFT (2U)\r
+/*! PDEN_AUD_PLL - Audio PLL (PLL2) power and fractional divider (also, enable/disable bit 26 in PDRUNCFG0 register).\r
+ */\r
+#define SYSCON_PDRUNCFG_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_AUD_PLL_MASK)\r
+#define SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK (0x8U)\r
+#define SYSCON_PDRUNCFG_PDEN_SYSOSC_SHIFT (3U)\r
+/*! PDEN_SYSOSC - System Oscillator Power (also, enable/disable bit 9 in PDRUNCFG0 register).\r
+ */\r
+#define SYSCON_PDRUNCFG_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK)\r
+#define SYSCON_PDRUNCFG_PDEN_FRO_MASK (0x10U)\r
+#define SYSCON_PDRUNCFG_PDEN_FRO_SHIFT (4U)\r
+/*! PDEN_FRO - FRO oscillator.\r
+ */\r
+#define SYSCON_PDRUNCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFG_PDEN_FRO_MASK)\r
+#define SYSCON_PDRUNCFG_PDEN_TS_MASK (0x40U)\r
+#define SYSCON_PDRUNCFG_PDEN_TS_SHIFT (6U)\r
+/*! PDEN_TS - Temp sensor.\r
+ */\r
+#define SYSCON_PDRUNCFG_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFG_PDEN_TS_MASK)\r
+#define SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK (0x80U)\r
+#define SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT (7U)\r
+/*! PDEN_BOD_RST - Brown-out Detect reset.\r
+ */\r
+#define SYSCON_PDRUNCFG_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK)\r
+#define SYSCON_PDRUNCFG_PDEN_RNG_MASK (0x80U)\r
+#define SYSCON_PDRUNCFG_PDEN_RNG_SHIFT (7U)\r
+/*! PDEN_RNG - Random Number Generator Power.\r
+ */\r
+#define SYSCON_PDRUNCFG_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFG_PDEN_RNG_MASK)\r
+#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK (0x100U)\r
+#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT (8U)\r
+/*! PDEN_BOD_INTR - Brown-out Detect interrupt.\r
+ */\r
+#define SYSCON_PDRUNCFG_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK)\r
+#define SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK (0x200U)\r
+#define SYSCON_PDRUNCFG_PDEN_VD2_ANA_SHIFT (9U)\r
+/*! PDEN_VD2_ANA - Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1\r
+ * register), Temperature Sensor (also, enable/disable bit 6), ADC (also, enable/disable bits 10, 19,\r
+ * and 23).\r
+ */\r
+#define SYSCON_PDRUNCFG_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK)\r
+#define SYSCON_PDRUNCFG_PDEN_ADC0_MASK (0x400U)\r
+#define SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT (10U)\r
+/*! PDEN_ADC0 - ADC power.\r
+ */\r
+#define SYSCON_PDRUNCFG_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ADC0_MASK)\r
+#define SYSCON_PDRUNCFG_PDEN_SRAMX_MASK (0x2000U)\r
+#define SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT (13U)\r
+/*! PDEN_SRAMX - PPDEN_SRAMX controls only SRAMX address 0x0 to 0x0000FFFF.Bit 29 (PDEN_VD6)\r
+ * controls SRAMX address 0x00010000 to 0x0002FFFF..\r
+ */\r
+#define SYSCON_PDRUNCFG_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAMX_MASK)\r
+#define SYSCON_PDRUNCFG_PDEN_SRAM0_MASK (0x4000U)\r
+#define SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT (14U)\r
+/*! PDEN_SRAM0 - PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27).\r
+ */\r
+#define SYSCON_PDRUNCFG_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM0_MASK)\r
+#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK (0x8000U)\r
+#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_SHIFT (15U)\r
+/*! PDEN_SRAM1_2_3 - PDEN_SRAM1_2_3 controls SRAM1, SRAM2, and SRAM3 (also enable/disable bit 27).\r
+ */\r
+#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK)\r
+#define SYSCON_PDRUNCFG_PDEN_USB_RAM_MASK (0x10000U)\r
+#define SYSCON_PDRUNCFG_PDEN_USB_RAM_SHIFT (16U)\r
+/*! PDEN_USB_RAM - PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27).\r
+ */\r
+#define SYSCON_PDRUNCFG_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB_RAM_MASK)\r
+#define SYSCON_PDRUNCFG_PDEN_ROM_MASK (0x20000U)\r
+#define SYSCON_PDRUNCFG_PDEN_ROM_SHIFT (17U)\r
+/*! PDEN_ROM - ROM (also enable/disable bit 27).\r
+ */\r
+#define SYSCON_PDRUNCFG_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ROM_MASK)\r
+#define SYSCON_PDRUNCFG_PDEN_VDDA_MASK (0x80000U)\r
+#define SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT (19U)\r
+/*! PDEN_VDDA - Vdda to the ADC, must be enabled for the ADC to work (also enable/disable bit 9, 10, and 23).\r
+ */\r
+#define SYSCON_PDRUNCFG_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VDDA_MASK)\r
+#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK (0x100000U)\r
+#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT (20U)\r
+/*! PDEN_WDT_OSC - Watchdog oscillator.\r
+ */\r
+#define SYSCON_PDRUNCFG_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)\r
+#define SYSCON_PDRUNCFG_PDEN_USB0_PHY_MASK (0x200000U)\r
+#define SYSCON_PDRUNCFG_PDEN_USB0_PHY_SHIFT (21U)\r
+/*! PDEN_USB0_PHY - USB0 PHY power (also enable/disable bit 28).\r
+ */\r
+#define SYSCON_PDRUNCFG_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB0_PHY_MASK)\r
+#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK (0x400000U)\r
+#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT (22U)\r
+/*! PDEN_SYS_PLL - System PLL (PLL0) power (also enable/disable bit 26).\r
+ */\r
+#define SYSCON_PDRUNCFG_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK)\r
+#define SYSCON_PDRUNCFG_PDEN_VREFP_MASK (0x800000U)\r
+#define SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT (23U)\r
+/*! PDEN_VREFP - VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9, 10, and 19).\r
+ */\r
+#define SYSCON_PDRUNCFG_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VREFP_MASK)\r
+#define SYSCON_PDRUNCFG_PDEN_VD3_MASK (0x4000000U)\r
+#define SYSCON_PDRUNCFG_PDEN_VD3_SHIFT (26U)\r
+/*! PDEN_VD3 - Power control for all PLLs.\r
+ */\r
+#define SYSCON_PDRUNCFG_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD3_MASK)\r
+#define SYSCON_PDRUNCFG_PDEN_VD4_MASK (0x8000000U)\r
+#define SYSCON_PDRUNCFG_PDEN_VD4_SHIFT (27U)\r
+/*! PDEN_VD4 - Power control for all SRAMs and ROM.\r
+ */\r
+#define SYSCON_PDRUNCFG_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD4_MASK)\r
+#define SYSCON_PDRUNCFG_PDEN_VD5_MASK (0x10000000U)\r
+#define SYSCON_PDRUNCFG_PDEN_VD5_SHIFT (28U)\r
+/*! PDEN_VD5 - Power control both USB0 PHY and USB1 PHY.\r
+ */\r
+#define SYSCON_PDRUNCFG_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD5_MASK)\r
+#define SYSCON_PDRUNCFG_PDEN_VD6_MASK (0x20000000U)\r
+#define SYSCON_PDRUNCFG_PDEN_VD6_SHIFT (29U)\r
+/*! PDEN_VD6 - Power control for OTP and SRAMX from address 0x00010000 to 0x0002FFFF.\r
+ */\r
+#define SYSCON_PDRUNCFG_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD6_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_PDRUNCFG */\r
+#define SYSCON_PDRUNCFG_COUNT (2U)\r
+\r
+/*! @name PDRUNCFGSET - Power configuration set register */\r
+/*! @{ */\r
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_MASK (0x1U)\r
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_SHIFT (0U)\r
+/*! PDEN_USB1_PHY - USB1 high speed PHY (also, enable/disable bit 28 in PDRUNCFG0 register).\r
+ */\r
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_MASK)\r
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_MASK (0x2U)\r
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_SHIFT (1U)\r
+/*! PDEN_USB1_PLL - USB PLL (PLL1) power (also, enable/disable bit 26 in PDRUNCFG0 register).\r
+ */\r
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_MASK)\r
+#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_MASK (0x4U)\r
+#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_SHIFT (2U)\r
+/*! PDEN_AUD_PLL - Audio PLL (PLL2) power and fractional divider (also, enable/disable bit 26 in PDRUNCFG0 register).\r
+ */\r
+#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_MASK)\r
+#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC_MASK (0x8U)\r
+#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC_SHIFT (3U)\r
+/*! PDEN_SYSOSC - System Oscillator Power (also, enable/disable bit 9 in PDRUNCFG0 register).\r
+ */\r
+#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SYSOSC_MASK)\r
+#define SYSCON_PDRUNCFGSET_PDEN_FRO_MASK (0x10U)\r
+#define SYSCON_PDRUNCFGSET_PDEN_FRO_SHIFT (4U)\r
+/*! PDEN_FRO - FRO oscillator.\r
+ */\r
+#define SYSCON_PDRUNCFGSET_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_FRO_MASK)\r
+#define SYSCON_PDRUNCFGSET_PDEN_TS_MASK (0x40U)\r
+#define SYSCON_PDRUNCFGSET_PDEN_TS_SHIFT (6U)\r
+/*! PDEN_TS - Temp sensor.\r
+ */\r
+#define SYSCON_PDRUNCFGSET_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_TS_MASK)\r
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST_MASK (0x80U)\r
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST_SHIFT (7U)\r
+/*! PDEN_BOD_RST - Brown-out Detect reset.\r
+ */\r
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_BOD_RST_MASK)\r
+#define SYSCON_PDRUNCFGSET_PDEN_RNG_MASK (0x80U)\r
+#define SYSCON_PDRUNCFGSET_PDEN_RNG_SHIFT (7U)\r
+/*! PDEN_RNG - Random Number Generator Power.\r
+ */\r
+#define SYSCON_PDRUNCFGSET_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_RNG_MASK)\r
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_MASK (0x100U)\r
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_SHIFT (8U)\r
+/*! PDEN_BOD_INTR - Brown-out Detect interrupt.\r
+ */\r
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_MASK)\r
+#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_MASK (0x200U)\r
+#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_SHIFT (9U)\r
+/*! PDEN_VD2_ANA - Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1\r
+ * register), Temperature Sensor (also, enable/disable bit 6), ADC (also, enable/disable bits 10, 19,\r
+ * and 23).\r
+ */\r
+#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_MASK)\r
+#define SYSCON_PDRUNCFGSET_PDEN_ADC0_MASK (0x400U)\r
+#define SYSCON_PDRUNCFGSET_PDEN_ADC0_SHIFT (10U)\r
+/*! PDEN_ADC0 - ADC power.\r
+ */\r
+#define SYSCON_PDRUNCFGSET_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_ADC0_MASK)\r
+#define SYSCON_PDRUNCFGSET_PDEN_SRAMX_MASK (0x2000U)\r
+#define SYSCON_PDRUNCFGSET_PDEN_SRAMX_SHIFT (13U)\r
+/*! PDEN_SRAMX - PDEN_SRAMX controls SRAMX (also enable/disable bit 27).\r
+ */\r
+#define SYSCON_PDRUNCFGSET_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAMX_MASK)\r
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM0_MASK (0x4000U)\r
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM0_SHIFT (14U)\r
+/*! PDEN_SRAM0 - PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27).\r
+ */\r
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAM0_MASK)\r
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_MASK (0x8000U)\r
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_SHIFT (15U)\r
+/*! PDEN_SRAM1_2_3 - PDEN_SRAM1_2_3 controls SRAM1, SRAM2, and SRAM3 (also enable/disable bit 27).\r
+ */\r
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_MASK)\r
+#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM_MASK (0x10000U)\r
+#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM_SHIFT (16U)\r
+/*! PDEN_USB_RAM - PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27).\r
+ */\r
+#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB_RAM_MASK)\r
+#define SYSCON_PDRUNCFGSET_PDEN_ROM_MASK (0x20000U)\r
+#define SYSCON_PDRUNCFGSET_PDEN_ROM_SHIFT (17U)\r
+/*! PDEN_ROM - ROM (also enable/disable bit 27).\r
+ */\r
+#define SYSCON_PDRUNCFGSET_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_ROM_MASK)\r
+#define SYSCON_PDRUNCFGSET_PDEN_VDDA_MASK (0x80000U)\r
+#define SYSCON_PDRUNCFGSET_PDEN_VDDA_SHIFT (19U)\r
+/*! PDEN_VDDA - Vdda to the ADC, must be enabled for the ADC to work (also enable/disable bit 9, 10, and 23).\r
+ */\r
+#define SYSCON_PDRUNCFGSET_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VDDA_MASK)\r
+#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_MASK (0x100000U)\r
+#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_SHIFT (20U)\r
+/*! PDEN_WDT_OSC - Watchdog oscillator.\r
+ */\r
+#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_MASK)\r
+#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_MASK (0x200000U)\r
+#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_SHIFT (21U)\r
+/*! PDEN_USB0_PHY - USB0 PHY power (also enable/disable bit 28).\r
+ */\r
+#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_MASK)\r
+#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_MASK (0x400000U)\r
+#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_SHIFT (22U)\r
+/*! PDEN_SYS_PLL - System PLL (PLL0) power (also enable/disable bit 26).\r
+ */\r
+#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_MASK)\r
+#define SYSCON_PDRUNCFGSET_PDEN_VREFP_MASK (0x800000U)\r
+#define SYSCON_PDRUNCFGSET_PDEN_VREFP_SHIFT (23U)\r
+/*! PDEN_VREFP - VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9, 10, and 19).\r
+ */\r
+#define SYSCON_PDRUNCFGSET_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VREFP_MASK)\r
+#define SYSCON_PDRUNCFGSET_PDEN_VD3_MASK (0x4000000U)\r
+#define SYSCON_PDRUNCFGSET_PDEN_VD3_SHIFT (26U)\r
+/*! PDEN_VD3 - Power control for all PLLs.\r
+ */\r
+#define SYSCON_PDRUNCFGSET_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD3_MASK)\r
+#define SYSCON_PDRUNCFGSET_PDEN_VD4_MASK (0x8000000U)\r
+#define SYSCON_PDRUNCFGSET_PDEN_VD4_SHIFT (27U)\r
+/*! PDEN_VD4 - Power control for all SRAMs and ROM.\r
+ */\r
+#define SYSCON_PDRUNCFGSET_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD4_MASK)\r
+#define SYSCON_PDRUNCFGSET_PDEN_VD5_MASK (0x10000000U)\r
+#define SYSCON_PDRUNCFGSET_PDEN_VD5_SHIFT (28U)\r
+/*! PDEN_VD5 - Power control both USB0 PHY and USB1 PHY.\r
+ */\r
+#define SYSCON_PDRUNCFGSET_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD5_MASK)\r
+#define SYSCON_PDRUNCFGSET_PDEN_VD6_MASK (0x20000000U)\r
+#define SYSCON_PDRUNCFGSET_PDEN_VD6_SHIFT (29U)\r
+/*! PDEN_VD6 - Power control for EEPROM.\r
+ */\r
+#define SYSCON_PDRUNCFGSET_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD6_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_PDRUNCFGSET */\r
+#define SYSCON_PDRUNCFGSET_COUNT (2U)\r
+\r
+/*! @name PDRUNCFGCLR - Power configuration clear register */\r
+/*! @{ */\r
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_MASK (0x1U)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_SHIFT (0U)\r
+/*! PDEN_USB1_PHY - USB1 high speed PHY (also, enable/disable bit 28 in PDRUNCFG0 register).\r
+ */\r
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_MASK)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_MASK (0x2U)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_SHIFT (1U)\r
+/*! PDEN_USB1_PLL - USB PLL (PLL1) power (also, enable/disable bit 26 in PDRUNCFG0 register).\r
+ */\r
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_MASK)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_MASK (0x4U)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_SHIFT (2U)\r
+/*! PDEN_AUD_PLL - Audio PLL (PLL2) power and fractional divider (also, enable/disable bit 26 in PDRUNCFG0 register).\r
+ */\r
+#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_MASK)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_MASK (0x8U)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_SHIFT (3U)\r
+/*! PDEN_SYSOSC - System Oscillator Power (also, enable/disable bit 9 in PDRUNCFG0 register).\r
+ */\r
+#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_MASK)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_FRO_MASK (0x10U)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_FRO_SHIFT (4U)\r
+/*! PDEN_FRO - FRO oscillator.\r
+ */\r
+#define SYSCON_PDRUNCFGCLR_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_FRO_MASK)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_TS_MASK (0x40U)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_TS_SHIFT (6U)\r
+/*! PDEN_TS - Temp sensor.\r
+ */\r
+#define SYSCON_PDRUNCFGCLR_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_TS_MASK)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_MASK (0x80U)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_SHIFT (7U)\r
+/*! PDEN_BOD_RST - Brown-out Detect reset.\r
+ */\r
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_MASK)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_RNG_MASK (0x80U)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_RNG_SHIFT (7U)\r
+/*! PDEN_RNG - Random Number Generator Power.\r
+ */\r
+#define SYSCON_PDRUNCFGCLR_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_RNG_MASK)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_MASK (0x100U)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_SHIFT (8U)\r
+/*! PDEN_BOD_INTR - Brown-out Detect interrupt.\r
+ */\r
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_MASK)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_MASK (0x200U)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_SHIFT (9U)\r
+/*! PDEN_VD2_ANA - Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1\r
+ * register), Temperature Sensor (also, enable/disable bit 6), ADC (also, enable/disable bits 10, 19,\r
+ * and 23).\r
+ */\r
+#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_MASK)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_ADC0_MASK (0x400U)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_ADC0_SHIFT (10U)\r
+/*! PDEN_ADC0 - ADC power.\r
+ */\r
+#define SYSCON_PDRUNCFGCLR_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_ADC0_MASK)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX_MASK (0x2000U)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX_SHIFT (13U)\r
+/*! PDEN_SRAMX - PDEN_SRAMX controls SRAMX (also enable/disable bit 27).\r
+ */\r
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAMX_MASK)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0_MASK (0x4000U)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0_SHIFT (14U)\r
+/*! PDEN_SRAM0 - PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27).\r
+ */\r
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAM0_MASK)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_MASK (0x8000U)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_SHIFT (15U)\r
+/*! PDEN_SRAM1_2_3 - PDEN_SRAM1_2_3 controls SRAM1, SRAM2, and SRAM3 (also enable/disable bit 27).\r
+ */\r
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_MASK)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_MASK (0x10000U)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_SHIFT (16U)\r
+/*! PDEN_USB_RAM - PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27).\r
+ */\r
+#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_MASK)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_ROM_MASK (0x20000U)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_ROM_SHIFT (17U)\r
+/*! PDEN_ROM - ROM (also enable/disable bit 27).\r
+ */\r
+#define SYSCON_PDRUNCFGCLR_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_ROM_MASK)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_VDDA_MASK (0x80000U)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_VDDA_SHIFT (19U)\r
+/*! PDEN_VDDA - Vdda to the ADC, must be enabled for the ADC to work (also enable/disable bit 9, 10, and 23).\r
+ */\r
+#define SYSCON_PDRUNCFGCLR_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VDDA_MASK)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_MASK (0x100000U)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_SHIFT (20U)\r
+/*! PDEN_WDT_OSC - Watchdog oscillator.\r
+ */\r
+#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_MASK)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_MASK (0x200000U)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_SHIFT (21U)\r
+/*! PDEN_USB0_PHY - USB0 PHY power (also enable/disable bit 28).\r
+ */\r
+#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_MASK)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_MASK (0x400000U)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_SHIFT (22U)\r
+/*! PDEN_SYS_PLL - System PLL (PLL0) power (also enable/disable bit 26).\r
+ */\r
+#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_MASK)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_VREFP_MASK (0x800000U)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_VREFP_SHIFT (23U)\r
+/*! PDEN_VREFP - VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9, 10, and 19).\r
+ */\r
+#define SYSCON_PDRUNCFGCLR_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VREFP_MASK)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_VD3_MASK (0x4000000U)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_VD3_SHIFT (26U)\r
+/*! PDEN_VD3 - Power control for all PLLs.\r
+ */\r
+#define SYSCON_PDRUNCFGCLR_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD3_MASK)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_VD4_MASK (0x8000000U)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_VD4_SHIFT (27U)\r
+/*! PDEN_VD4 - Power control for all SRAMs and ROM.\r
+ */\r
+#define SYSCON_PDRUNCFGCLR_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD4_MASK)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_VD5_MASK (0x10000000U)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_VD5_SHIFT (28U)\r
+/*! PDEN_VD5 - Power control both USB0 PHY and USB1 PHY.\r
+ */\r
+#define SYSCON_PDRUNCFGCLR_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD5_MASK)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_VD6_MASK (0x20000000U)\r
+#define SYSCON_PDRUNCFGCLR_PDEN_VD6_SHIFT (29U)\r
+/*! PDEN_VD6 - Power control for EEPROM.\r
+ */\r
+#define SYSCON_PDRUNCFGCLR_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD6_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_PDRUNCFGCLR */\r
+#define SYSCON_PDRUNCFGCLR_COUNT (2U)\r
+\r
+/*! @name STARTER - Start logic 0 wake-up enable register */\r
+/*! @{ */\r
+#define SYSCON_STARTER_PINT4_MASK (0x1U)\r
+#define SYSCON_STARTER_PINT4_SHIFT (0U)\r
+/*! PINT4 - GPIO pin interrupt 4 wake-up.\r
+ */\r
+#define SYSCON_STARTER_PINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT4_SHIFT)) & SYSCON_STARTER_PINT4_MASK)\r
+#define SYSCON_STARTER_WDT_BOD_MASK (0x1U)\r
+#define SYSCON_STARTER_WDT_BOD_SHIFT (0U)\r
+/*! WDT_BOD - WWDT and BOD interrupt wake-up.\r
+ */\r
+#define SYSCON_STARTER_WDT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WDT_BOD_SHIFT)) & SYSCON_STARTER_WDT_BOD_MASK)\r
+#define SYSCON_STARTER_DMA_MASK (0x2U)\r
+#define SYSCON_STARTER_DMA_SHIFT (1U)\r
+/*! DMA - DMA wake-up.\r
+ */\r
+#define SYSCON_STARTER_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMA_SHIFT)) & SYSCON_STARTER_DMA_MASK)\r
+#define SYSCON_STARTER_PINT5_MASK (0x2U)\r
+#define SYSCON_STARTER_PINT5_SHIFT (1U)\r
+/*! PINT5 - GPIO pin interrupt 5 wake-up.\r
+ */\r
+#define SYSCON_STARTER_PINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT5_SHIFT)) & SYSCON_STARTER_PINT5_MASK)\r
+#define SYSCON_STARTER_GINT0_MASK (0x4U)\r
+#define SYSCON_STARTER_GINT0_SHIFT (2U)\r
+/*! GINT0 - Group interrupt 0 wake-up.\r
+ */\r
+#define SYSCON_STARTER_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT0_SHIFT)) & SYSCON_STARTER_GINT0_MASK)\r
+#define SYSCON_STARTER_PINT6_MASK (0x4U)\r
+#define SYSCON_STARTER_PINT6_SHIFT (2U)\r
+/*! PINT6 - GPIO pin interrupt 6 wake-up.\r
+ */\r
+#define SYSCON_STARTER_PINT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT6_SHIFT)) & SYSCON_STARTER_PINT6_MASK)\r
+#define SYSCON_STARTER_GINT1_MASK (0x8U)\r
+#define SYSCON_STARTER_GINT1_SHIFT (3U)\r
+/*! GINT1 - Group interrupt 1 wake-up.\r
+ */\r
+#define SYSCON_STARTER_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT1_SHIFT)) & SYSCON_STARTER_GINT1_MASK)\r
+#define SYSCON_STARTER_PINT7_MASK (0x8U)\r
+#define SYSCON_STARTER_PINT7_SHIFT (3U)\r
+/*! PINT7 - GPIO pin interrupt 7 wake-up.\r
+ */\r
+#define SYSCON_STARTER_PINT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT7_SHIFT)) & SYSCON_STARTER_PINT7_MASK)\r
+#define SYSCON_STARTER_PIN_INT0_MASK (0x10U)\r
+#define SYSCON_STARTER_PIN_INT0_SHIFT (4U)\r
+/*! PIN_INT0 - GPIO pin interrupt 0 wake-up.\r
+ */\r
+#define SYSCON_STARTER_PIN_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT0_SHIFT)) & SYSCON_STARTER_PIN_INT0_MASK)\r
+#define SYSCON_STARTER_PIN_INT1_MASK (0x20U)\r
+#define SYSCON_STARTER_PIN_INT1_SHIFT (5U)\r
+/*! PIN_INT1 - GPIO pin interrupt 1 wake-up.\r
+ */\r
+#define SYSCON_STARTER_PIN_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT1_SHIFT)) & SYSCON_STARTER_PIN_INT1_MASK)\r
+#define SYSCON_STARTER_PIN_INT2_MASK (0x40U)\r
+#define SYSCON_STARTER_PIN_INT2_SHIFT (6U)\r
+/*! PIN_INT2 - GPIO pin interrupt 2 wake-up.\r
+ */\r
+#define SYSCON_STARTER_PIN_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT2_SHIFT)) & SYSCON_STARTER_PIN_INT2_MASK)\r
+#define SYSCON_STARTER_PIN_INT3_MASK (0x80U)\r
+#define SYSCON_STARTER_PIN_INT3_SHIFT (7U)\r
+/*! PIN_INT3 - GPIO pin interrupt 3 wake-up.\r
+ */\r
+#define SYSCON_STARTER_PIN_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT3_SHIFT)) & SYSCON_STARTER_PIN_INT3_MASK)\r
+#define SYSCON_STARTER_FLEXCOMM8_MASK (0x100U)\r
+#define SYSCON_STARTER_FLEXCOMM8_SHIFT (8U)\r
+/*! FLEXCOMM8 - Flexcomm Interface 8 wake-up.\r
+ */\r
+#define SYSCON_STARTER_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM8_SHIFT)) & SYSCON_STARTER_FLEXCOMM8_MASK)\r
+#define SYSCON_STARTER_UTICK_MASK (0x100U)\r
+#define SYSCON_STARTER_UTICK_SHIFT (8U)\r
+/*! UTICK - Micro-tick Timer wake-up.\r
+ */\r
+#define SYSCON_STARTER_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_UTICK_SHIFT)) & SYSCON_STARTER_UTICK_MASK)\r
+#define SYSCON_STARTER_FLEXCOMM9_MASK (0x200U)\r
+#define SYSCON_STARTER_FLEXCOMM9_SHIFT (9U)\r
+/*! FLEXCOMM9 - Flexcomm Interface 9 wake-up.\r
+ */\r
+#define SYSCON_STARTER_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM9_SHIFT)) & SYSCON_STARTER_FLEXCOMM9_MASK)\r
+#define SYSCON_STARTER_FLEXCOMM0_MASK (0x4000U)\r
+#define SYSCON_STARTER_FLEXCOMM0_SHIFT (14U)\r
+/*! FLEXCOMM0 - Flexcomm0 peripheral interrupt wake-up.\r
+ */\r
+#define SYSCON_STARTER_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM0_SHIFT)) & SYSCON_STARTER_FLEXCOMM0_MASK)\r
+#define SYSCON_STARTER_FLEXCOMM1_MASK (0x8000U)\r
+#define SYSCON_STARTER_FLEXCOMM1_SHIFT (15U)\r
+/*! FLEXCOMM1 - Flexcomm1 peripheral interrupt wake-up.\r
+ */\r
+#define SYSCON_STARTER_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM1_SHIFT)) & SYSCON_STARTER_FLEXCOMM1_MASK)\r
+#define SYSCON_STARTER_USB1_MASK (0x8000U)\r
+#define SYSCON_STARTER_USB1_SHIFT (15U)\r
+/*! USB1 - USB 1 wake-up.\r
+ */\r
+#define SYSCON_STARTER_USB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_SHIFT)) & SYSCON_STARTER_USB1_MASK)\r
+#define SYSCON_STARTER_FLEXCOMM2_MASK (0x10000U)\r
+#define SYSCON_STARTER_FLEXCOMM2_SHIFT (16U)\r
+/*! FLEXCOMM2 - Flexcomm2 peripheral interrupt wake-up.\r
+ */\r
+#define SYSCON_STARTER_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM2_SHIFT)) & SYSCON_STARTER_FLEXCOMM2_MASK)\r
+#define SYSCON_STARTER_USB1_ACT_MASK (0x10000U)\r
+#define SYSCON_STARTER_USB1_ACT_SHIFT (16U)\r
+/*! USB1_ACT - USB 1 activity wake-up.\r
+ */\r
+#define SYSCON_STARTER_USB1_ACT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_ACT_SHIFT)) & SYSCON_STARTER_USB1_ACT_MASK)\r
+#define SYSCON_STARTER_FLEXCOMM3_MASK (0x20000U)\r
+#define SYSCON_STARTER_FLEXCOMM3_SHIFT (17U)\r
+/*! FLEXCOMM3 - Flexcomm3 peripheral interrupt wake-up.\r
+ */\r
+#define SYSCON_STARTER_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM3_SHIFT)) & SYSCON_STARTER_FLEXCOMM3_MASK)\r
+#define SYSCON_STARTER_FLEXCOMM4_MASK (0x40000U)\r
+#define SYSCON_STARTER_FLEXCOMM4_SHIFT (18U)\r
+/*! FLEXCOMM4 - Flexcomm4 peripheral interrupt wake-up.\r
+ */\r
+#define SYSCON_STARTER_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM4_SHIFT)) & SYSCON_STARTER_FLEXCOMM4_MASK)\r
+#define SYSCON_STARTER_FLEXCOMM5_MASK (0x80000U)\r
+#define SYSCON_STARTER_FLEXCOMM5_SHIFT (19U)\r
+/*! FLEXCOMM5 - Flexcomm5 peripheral interrupt wake-up.\r
+ */\r
+#define SYSCON_STARTER_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM5_SHIFT)) & SYSCON_STARTER_FLEXCOMM5_MASK)\r
+#define SYSCON_STARTER_FLEXCOMM6_MASK (0x100000U)\r
+#define SYSCON_STARTER_FLEXCOMM6_SHIFT (20U)\r
+/*! FLEXCOMM6 - Flexcomm6 peripheral interrupt wake-up.\r
+ */\r
+#define SYSCON_STARTER_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM6_SHIFT)) & SYSCON_STARTER_FLEXCOMM6_MASK)\r
+#define SYSCON_STARTER_FLEXCOMM7_MASK (0x200000U)\r
+#define SYSCON_STARTER_FLEXCOMM7_SHIFT (21U)\r
+/*! FLEXCOMM7 - Flexcomm7 peripheral interrupt wake-up.\r
+ */\r
+#define SYSCON_STARTER_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM7_SHIFT)) & SYSCON_STARTER_FLEXCOMM7_MASK)\r
+#define SYSCON_STARTER_DMIC_MASK (0x2000000U)\r
+#define SYSCON_STARTER_DMIC_SHIFT (25U)\r
+/*! DMIC - Digital microphone interrupt wake-up.\r
+ */\r
+#define SYSCON_STARTER_DMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMIC_SHIFT)) & SYSCON_STARTER_DMIC_MASK)\r
+#define SYSCON_STARTER_HWVAD_MASK (0x4000000U)\r
+#define SYSCON_STARTER_HWVAD_SHIFT (26U)\r
+/*! HWVAD - Hardware voice activity detect interrupt wake-up.\r
+ */\r
+#define SYSCON_STARTER_HWVAD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_HWVAD_SHIFT)) & SYSCON_STARTER_HWVAD_MASK)\r
+#define SYSCON_STARTER_USB0_NEEDCLK_MASK (0x8000000U)\r
+#define SYSCON_STARTER_USB0_NEEDCLK_SHIFT (27U)\r
+/*! USB0_NEEDCLK - USB activity interrupt wake-up.\r
+ */\r
+#define SYSCON_STARTER_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB0_NEEDCLK_MASK)\r
+#define SYSCON_STARTER_USB0_MASK (0x10000000U)\r
+#define SYSCON_STARTER_USB0_SHIFT (28U)\r
+/*! USB0 - USB function interrupt wake-up.\r
+ */\r
+#define SYSCON_STARTER_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_SHIFT)) & SYSCON_STARTER_USB0_MASK)\r
+#define SYSCON_STARTER_RTC_MASK (0x20000000U)\r
+#define SYSCON_STARTER_RTC_SHIFT (29U)\r
+/*! RTC - RTC interrupt alarm and wake-up timer.\r
+ */\r
+#define SYSCON_STARTER_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_RTC_SHIFT)) & SYSCON_STARTER_RTC_MASK)\r
+#define SYSCON_STARTER_FLEXCOMM10_MASK (0x40000000U)\r
+#define SYSCON_STARTER_FLEXCOMM10_SHIFT (30U)\r
+/*! FLEXCOMM10 - Flexcomm10 peripheral interrupt wake-up.\r
+ */\r
+#define SYSCON_STARTER_FLEXCOMM10(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM10_SHIFT)) & SYSCON_STARTER_FLEXCOMM10_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_STARTER */\r
+#define SYSCON_STARTER_COUNT (2U)\r
+\r
+/*! @name STARTERSET - Set bits in STARTER */\r
+/*! @{ */\r
+#define SYSCON_STARTERSET_START_SET_MASK (0xFFFFFFFFU)\r
+#define SYSCON_STARTERSET_START_SET_SHIFT (0U)\r
+/*! START_SET - Writing ones to this register sets the corresponding bit or bits in the STARTER0 register, if they are implemented.\r
+ */\r
+#define SYSCON_STARTERSET_START_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_START_SET_SHIFT)) & SYSCON_STARTERSET_START_SET_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_STARTERSET */\r
+#define SYSCON_STARTERSET_COUNT (2U)\r
+\r
+/*! @name STARTERCLR - Clear bits in STARTER0 */\r
+/*! @{ */\r
+#define SYSCON_STARTERCLR_START_CLR_MASK (0xFFFFFFFFU)\r
+#define SYSCON_STARTERCLR_START_CLR_SHIFT (0U)\r
+/*! START_CLR - Writing ones to this register clears the corresponding bit or bits in the STARTER0 register, if they are implemented.\r
+ */\r
+#define SYSCON_STARTERCLR_START_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_START_CLR_SHIFT)) & SYSCON_STARTERCLR_START_CLR_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_STARTERCLR */\r
+#define SYSCON_STARTERCLR_COUNT (2U)\r
+\r
+/*! @name HWWAKE - Configures special cases of hardware wake-up */\r
+/*! @{ */\r
+#define SYSCON_HWWAKE_FORCEWAKE_MASK (0x1U)\r
+#define SYSCON_HWWAKE_FORCEWAKE_SHIFT (0U)\r
+/*! FORCEWAKE - Force peripheral clocking to stay on during Deep Sleep and Power-down modes. When 1,\r
+ * clocking to peripherals is prevented from being shut down when the CPU enters Deep Sleep and\r
+ * Power-down modes. This is intended to allow a coprocessor to continue operating while the main\r
+ * CPU(s) are shut down.\r
+ */\r
+#define SYSCON_HWWAKE_FORCEWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FORCEWAKE_SHIFT)) & SYSCON_HWWAKE_FORCEWAKE_MASK)\r
+#define SYSCON_HWWAKE_FCWAKE_MASK (0x2U)\r
+#define SYSCON_HWWAKE_FCWAKE_SHIFT (1U)\r
+/*! FCWAKE - Wake for Flexcomms. When 1, any Flexcomm FIFO reaching the level specified by its own\r
+ * TXLVL will cause peripheral clocking to wake up temporarily while the related status is\r
+ * asserted.\r
+ */\r
+#define SYSCON_HWWAKE_FCWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FCWAKE_SHIFT)) & SYSCON_HWWAKE_FCWAKE_MASK)\r
+#define SYSCON_HWWAKE_WAKEDMIC_MASK (0x4U)\r
+#define SYSCON_HWWAKE_WAKEDMIC_SHIFT (2U)\r
+/*! WAKEDMIC - Wake for Digital Microphone. When 1, the digital microphone input FIFO reaching the\r
+ * level specified by TRIGLVL of either channel will cause peripheral clocking to wake up\r
+ * temporarily while the related status is asserted.\r
+ */\r
+#define SYSCON_HWWAKE_WAKEDMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMIC_SHIFT)) & SYSCON_HWWAKE_WAKEDMIC_MASK)\r
+#define SYSCON_HWWAKE_WAKEDMA_MASK (0x8U)\r
+#define SYSCON_HWWAKE_WAKEDMA_SHIFT (3U)\r
+/*! WAKEDMA - Wake for DMA. When 1, DMA being busy will cause peripheral clocking to remain running\r
+ * until DMA completes. This is generally used in conjunction with bit 1 and/or 2 in order to\r
+ * prevent peripheral clocking from being shut down as soon as the cause of wake-up is cleared, but\r
+ * before DMA has completed its related activity.\r
+ */\r
+#define SYSCON_HWWAKE_WAKEDMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMA_SHIFT)) & SYSCON_HWWAKE_WAKEDMA_MASK)\r
+/*! @} */\r
+\r
+/*! @name AUTOCGOR - Auto Clock-Gate Override Register */\r
+/*! @{ */\r
+#define SYSCON_AUTOCGOR_RAM0X_MASK (0x2U)\r
+#define SYSCON_AUTOCGOR_RAM0X_SHIFT (1U)\r
+/*! RAM0X - When 1, automatic clock gating for RAMX and RAM0 are turned off.\r
+ */\r
+#define SYSCON_AUTOCGOR_RAM0X(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM0X_SHIFT)) & SYSCON_AUTOCGOR_RAM0X_MASK)\r
+#define SYSCON_AUTOCGOR_RAM1_MASK (0x4U)\r
+#define SYSCON_AUTOCGOR_RAM1_SHIFT (2U)\r
+/*! RAM1 - When 1, automatic clock gating for RAM1 are turned off.\r
+ */\r
+#define SYSCON_AUTOCGOR_RAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM1_SHIFT)) & SYSCON_AUTOCGOR_RAM1_MASK)\r
+#define SYSCON_AUTOCGOR_RAM2_MASK (0x8U)\r
+#define SYSCON_AUTOCGOR_RAM2_SHIFT (3U)\r
+/*! RAM2 - When 1, automatic clock gating for RAM1 are turned off.\r
+ */\r
+#define SYSCON_AUTOCGOR_RAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM2_SHIFT)) & SYSCON_AUTOCGOR_RAM2_MASK)\r
+#define SYSCON_AUTOCGOR_RAM3_MASK (0x10U)\r
+#define SYSCON_AUTOCGOR_RAM3_SHIFT (4U)\r
+/*! RAM3 - When 1, automatic clock gating for RAM1 are turned off.\r
+ */\r
+#define SYSCON_AUTOCGOR_RAM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM3_SHIFT)) & SYSCON_AUTOCGOR_RAM3_MASK)\r
+/*! @} */\r
+\r
+/*! @name JTAGIDCODE - JTAG ID code register */\r
+/*! @{ */\r
+#define SYSCON_JTAGIDCODE_JTAGID_MASK (0xFFFFFFFFU)\r
+#define SYSCON_JTAGIDCODE_JTAGID_SHIFT (0U)\r
+/*! JTAGID - JTAG ID code.\r
+ */\r
+#define SYSCON_JTAGIDCODE_JTAGID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAGIDCODE_JTAGID_SHIFT)) & SYSCON_JTAGIDCODE_JTAGID_MASK)\r
+/*! @} */\r
+\r
+/*! @name DEVICE_ID0 - Part ID register */\r
+/*! @{ */\r
+#define SYSCON_DEVICE_ID0_PARTID_MASK (0xFFFFFFFFU)\r
+#define SYSCON_DEVICE_ID0_PARTID_SHIFT (0U)\r
+/*! PARTID - Part ID\r
+ */\r
+#define SYSCON_DEVICE_ID0_PARTID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTID_SHIFT)) & SYSCON_DEVICE_ID0_PARTID_MASK)\r
+/*! @} */\r
+\r
+/*! @name DEVICE_ID1 - Boot ROM and die revision register */\r
+/*! @{ */\r
+#define SYSCON_DEVICE_ID1_REVID_MASK (0xFFFFFFFFU)\r
+#define SYSCON_DEVICE_ID1_REVID_SHIFT (0U)\r
+/*! REVID - Revision.\r
+ */\r
+#define SYSCON_DEVICE_ID1_REVID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID1_REVID_SHIFT)) & SYSCON_DEVICE_ID1_REVID_MASK)\r
+/*! @} */\r
+\r
+/*! @name BODCTRL - Brown-Out Detect control */\r
+/*! @{ */\r
+#define SYSCON_BODCTRL_BODRSTLEV_MASK (0x3U)\r
+#define SYSCON_BODCTRL_BODRSTLEV_SHIFT (0U)\r
+/*! BODRSTLEV - BOD reset level\r
+ * 0b00..Level 0: 1.5 V\r
+ * 0b01..Level 1: 1.85 V\r
+ * 0b10..Level 2: 2.0 V\r
+ * 0b11..Level 3: 2.3 V\r
+ */\r
+#define SYSCON_BODCTRL_BODRSTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTLEV_SHIFT)) & SYSCON_BODCTRL_BODRSTLEV_MASK)\r
+#define SYSCON_BODCTRL_BODRSTENA_MASK (0x4U)\r
+#define SYSCON_BODCTRL_BODRSTENA_SHIFT (2U)\r
+/*! BODRSTENA - BOD reset enable\r
+ * 0b0..Disable reset function.\r
+ * 0b1..Enable reset function.\r
+ */\r
+#define SYSCON_BODCTRL_BODRSTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTENA_SHIFT)) & SYSCON_BODCTRL_BODRSTENA_MASK)\r
+#define SYSCON_BODCTRL_BODINTLEV_MASK (0x18U)\r
+#define SYSCON_BODCTRL_BODINTLEV_SHIFT (3U)\r
+/*! BODINTLEV - BOD interrupt level\r
+ * 0b00..Level 0: 2.05 V\r
+ * 0b01..Level 1: 2.45 V\r
+ * 0b10..Level 2: 2.75 V\r
+ * 0b11..Level 3: 3.05 V\r
+ */\r
+#define SYSCON_BODCTRL_BODINTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTLEV_SHIFT)) & SYSCON_BODCTRL_BODINTLEV_MASK)\r
+#define SYSCON_BODCTRL_BODINTENA_MASK (0x20U)\r
+#define SYSCON_BODCTRL_BODINTENA_SHIFT (5U)\r
+/*! BODINTENA - BOD interrupt enable\r
+ * 0b0..Disable interrupt function.\r
+ * 0b1..Enable interrupt function.\r
+ */\r
+#define SYSCON_BODCTRL_BODINTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTENA_SHIFT)) & SYSCON_BODCTRL_BODINTENA_MASK)\r
+#define SYSCON_BODCTRL_BODRSTSTAT_MASK (0x40U)\r
+#define SYSCON_BODCTRL_BODRSTSTAT_SHIFT (6U)\r
+/*! BODRSTSTAT - BOD reset status. When 1, a BOD reset has occurred. Cleared by writing 1 to this bit.\r
+ */\r
+#define SYSCON_BODCTRL_BODRSTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTSTAT_SHIFT)) & SYSCON_BODCTRL_BODRSTSTAT_MASK)\r
+#define SYSCON_BODCTRL_BODINTSTAT_MASK (0x80U)\r
+#define SYSCON_BODCTRL_BODINTSTAT_SHIFT (7U)\r
+/*! BODINTSTAT - BOD interrupt status. When 1, a BOD interrupt has occurred. Cleared by writing 1 to this bit.\r
+ */\r
+#define SYSCON_BODCTRL_BODINTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTSTAT_SHIFT)) & SYSCON_BODCTRL_BODINTSTAT_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group SYSCON_Register_Masks */\r
+\r
+\r
+/* SYSCON - Peripheral instance base addresses */\r
+/** Peripheral SYSCON base address */\r
+#define SYSCON_BASE (0x40000000u)\r
+/** Peripheral SYSCON base pointer */\r
+#define SYSCON ((SYSCON_Type *)SYSCON_BASE)\r
+/** Array initializer of SYSCON peripheral base addresses */\r
+#define SYSCON_BASE_ADDRS { SYSCON_BASE }\r
+/** Array initializer of SYSCON peripheral base pointers */\r
+#define SYSCON_BASE_PTRS { SYSCON }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group SYSCON_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- USART Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** USART - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */\r
+ __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */\r
+ __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */\r
+ __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */\r
+ __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */\r
+ uint8_t RESERVED_0[12];\r
+ __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */\r
+ __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */\r
+ __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */\r
+ __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */\r
+ uint8_t RESERVED_1[3536];\r
+ __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */\r
+ __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */\r
+ __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */\r
+ uint8_t RESERVED_2[4];\r
+ __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */\r
+ __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */\r
+ __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */\r
+ uint8_t RESERVED_3[4];\r
+ __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */\r
+ uint8_t RESERVED_4[12];\r
+ __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */\r
+ uint8_t RESERVED_5[12];\r
+ __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */\r
+ uint8_t RESERVED_6[440];\r
+ __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */\r
+} USART_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- USART Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup USART_Register_Masks USART Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */\r
+/*! @{ */\r
+#define USART_CFG_ENABLE_MASK (0x1U)\r
+#define USART_CFG_ENABLE_SHIFT (0U)\r
+/*! ENABLE - USART Enable.\r
+ * 0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0,\r
+ * all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control\r
+ * bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the\r
+ * transmitter has been reset and is therefore available.\r
+ * 0b1..Enabled. The USART is enabled for operation.\r
+ */\r
+#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK)\r
+#define USART_CFG_DATALEN_MASK (0xCU)\r
+#define USART_CFG_DATALEN_SHIFT (2U)\r
+/*! DATALEN - Selects the data size for the USART.\r
+ * 0b00..7 bit Data length.\r
+ * 0b01..8 bit Data length.\r
+ * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register.\r
+ * 0b11..Reserved.\r
+ */\r
+#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK)\r
+#define USART_CFG_PARITYSEL_MASK (0x30U)\r
+#define USART_CFG_PARITYSEL_SHIFT (4U)\r
+/*! PARITYSEL - Selects what type of parity is used by the USART.\r
+ * 0b00..No parity.\r
+ * 0b01..Reserved.\r
+ * 0b10..Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even,\r
+ * and the number of 1s in a received character is expected to be even.\r
+ * 0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd,\r
+ * and the number of 1s in a received character is expected to be odd.\r
+ */\r
+#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK)\r
+#define USART_CFG_STOPLEN_MASK (0x40U)\r
+#define USART_CFG_STOPLEN_SHIFT (6U)\r
+/*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.\r
+ * 0b0..1 stop bit.\r
+ * 0b1..2 stop bits. This setting should only be used for asynchronous communication.\r
+ */\r
+#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK)\r
+#define USART_CFG_MODE32K_MASK (0x80U)\r
+#define USART_CFG_MODE32K_SHIFT (7U)\r
+/*! MODE32K - Selects standard or 32 kHz clocking mode.\r
+ * 0b0..Disabled. USART uses standard clocking.\r
+ * 0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme.\r
+ */\r
+#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK)\r
+#define USART_CFG_LINMODE_MASK (0x100U)\r
+#define USART_CFG_LINMODE_SHIFT (8U)\r
+/*! LINMODE - LIN break mode enable.\r
+ * 0b0..Disabled. Break detect and generate is configured for normal operation.\r
+ * 0b1..Enabled. Break detect and generate is configured for LIN bus operation.\r
+ */\r
+#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK)\r
+#define USART_CFG_CTSEN_MASK (0x200U)\r
+#define USART_CFG_CTSEN_SHIFT (9U)\r
+/*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input\r
+ * pin, or from the USART's own RTS if loopback mode is enabled.\r
+ * 0b0..No flow control. The transmitter does not receive any automatic flow control signal.\r
+ * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.\r
+ */\r
+#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK)\r
+#define USART_CFG_SYNCEN_MASK (0x800U)\r
+#define USART_CFG_SYNCEN_SHIFT (11U)\r
+/*! SYNCEN - Selects synchronous or asynchronous operation.\r
+ * 0b0..Asynchronous mode.\r
+ * 0b1..Synchronous mode.\r
+ */\r
+#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK)\r
+#define USART_CFG_CLKPOL_MASK (0x1000U)\r
+#define USART_CFG_CLKPOL_SHIFT (12U)\r
+/*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode.\r
+ * 0b0..Falling edge. Un_RXD is sampled on the falling edge of SCLK.\r
+ * 0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK.\r
+ */\r
+#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK)\r
+#define USART_CFG_SYNCMST_MASK (0x4000U)\r
+#define USART_CFG_SYNCMST_SHIFT (14U)\r
+/*! SYNCMST - Synchronous mode Master select.\r
+ * 0b0..Slave. When synchronous mode is enabled, the USART is a slave.\r
+ * 0b1..Master. When synchronous mode is enabled, the USART is a master.\r
+ */\r
+#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK)\r
+#define USART_CFG_LOOP_MASK (0x8000U)\r
+#define USART_CFG_LOOP_SHIFT (15U)\r
+/*! LOOP - Selects data loopback mode.\r
+ * 0b0..Normal operation.\r
+ * 0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial\r
+ * data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD\r
+ * and Un_RTS activity will also appear on external pins if these functions are configured to appear on device\r
+ * pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.\r
+ */\r
+#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK)\r
+#define USART_CFG_OETA_MASK (0x40000U)\r
+#define USART_CFG_OETA_SHIFT (18U)\r
+/*! OETA - Output Enable Turnaround time enable for RS-485 operation.\r
+ * 0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission.\r
+ * 0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the\r
+ * end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins\r
+ * before it is deasserted.\r
+ */\r
+#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK)\r
+#define USART_CFG_AUTOADDR_MASK (0x80000U)\r
+#define USART_CFG_AUTOADDR_SHIFT (19U)\r
+/*! AUTOADDR - Automatic Address matching enable.\r
+ * 0b0..Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the\r
+ * possibility of versatile addressing (e.g. respond to more than one address).\r
+ * 0b1..Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in\r
+ * the ADDR register as the address to match.\r
+ */\r
+#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK)\r
+#define USART_CFG_OESEL_MASK (0x100000U)\r
+#define USART_CFG_OESEL_SHIFT (20U)\r
+/*! OESEL - Output Enable Select.\r
+ * 0b0..Standard. The RTS signal is used as the standard flow control function.\r
+ * 0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver.\r
+ */\r
+#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK)\r
+#define USART_CFG_OEPOL_MASK (0x200000U)\r
+#define USART_CFG_OEPOL_SHIFT (21U)\r
+/*! OEPOL - Output Enable Polarity.\r
+ * 0b0..Low. If selected by OESEL, the output enable is active low.\r
+ * 0b1..High. If selected by OESEL, the output enable is active high.\r
+ */\r
+#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK)\r
+#define USART_CFG_RXPOL_MASK (0x400000U)\r
+#define USART_CFG_RXPOL_SHIFT (22U)\r
+/*! RXPOL - Receive data polarity.\r
+ * 0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start\r
+ * bit is 0, data is not inverted, and the stop bit is 1.\r
+ * 0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is\r
+ * 0, start bit is 1, data is inverted, and the stop bit is 0.\r
+ */\r
+#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK)\r
+#define USART_CFG_TXPOL_MASK (0x800000U)\r
+#define USART_CFG_TXPOL_SHIFT (23U)\r
+/*! TXPOL - Transmit data polarity.\r
+ * 0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is\r
+ * 0, data is not inverted, and the stop bit is 1.\r
+ * 0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value\r
+ * is 0, start bit is 1, data is inverted, and the stop bit is 0.\r
+ */\r
+#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK)\r
+/*! @} */\r
+\r
+/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */\r
+/*! @{ */\r
+#define USART_CTL_TXBRKEN_MASK (0x2U)\r
+#define USART_CTL_TXBRKEN_SHIFT (1U)\r
+/*! TXBRKEN - Break Enable.\r
+ * 0b0..Normal operation.\r
+ * 0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit\r
+ * is cleared. A break may be sent without danger of corrupting any currently transmitting character if the\r
+ * transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled\r
+ * (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.\r
+ */\r
+#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK)\r
+#define USART_CTL_ADDRDET_MASK (0x4U)\r
+#define USART_CTL_ADDRDET_SHIFT (2U)\r
+/*! ADDRDET - Enable address detect mode.\r
+ * 0b0..Disabled. The USART presents all incoming data.\r
+ * 0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data\r
+ * (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally,\r
+ * generating a received data interrupt. Software can then check the data to see if this is an address that\r
+ * should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled\r
+ * normally.\r
+ */\r
+#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK)\r
+#define USART_CTL_TXDIS_MASK (0x40U)\r
+#define USART_CTL_TXDIS_SHIFT (6U)\r
+/*! TXDIS - Transmit Disable.\r
+ * 0b0..Not disabled. USART transmitter is not disabled.\r
+ * 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This\r
+ * feature can be used to facilitate software flow control.\r
+ */\r
+#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK)\r
+#define USART_CTL_CC_MASK (0x100U)\r
+#define USART_CTL_CC_SHIFT (8U)\r
+/*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.\r
+ * 0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to\r
+ * complete a character that is being received.\r
+ * 0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on\r
+ * Un_RxD independently from transmission on Un_TXD).\r
+ */\r
+#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK)\r
+#define USART_CTL_CLRCCONRX_MASK (0x200U)\r
+#define USART_CTL_CLRCCONRX_SHIFT (9U)\r
+/*! CLRCCONRX - Clear Continuous Clock.\r
+ * 0b0..No effect. No effect on the CC bit.\r
+ * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time.\r
+ */\r
+#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK)\r
+#define USART_CTL_AUTOBAUD_MASK (0x10000U)\r
+#define USART_CTL_AUTOBAUD_SHIFT (16U)\r
+/*! AUTOBAUD - Autobaud enable.\r
+ * 0b0..Disabled. USART is in normal operating mode.\r
+ * 0b1..Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The\r
+ * first start bit of RX is measured and used the update the BRG register to match the received data rate.\r
+ * AUTOBAUD is cleared once this process is complete, or if there is an AERR.\r
+ */\r
+#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK)\r
+/*! @} */\r
+\r
+/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */\r
+/*! @{ */\r
+#define USART_STAT_RXIDLE_MASK (0x2U)\r
+#define USART_STAT_RXIDLE_SHIFT (1U)\r
+/*! RXIDLE - Receiver Idle. When 0, indicates that the receiver is currently in the process of\r
+ * receiving data. When 1, indicates that the receiver is not currently in the process of receiving\r
+ * data.\r
+ */\r
+#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK)\r
+#define USART_STAT_TXIDLE_MASK (0x8U)\r
+#define USART_STAT_TXIDLE_SHIFT (3U)\r
+/*! TXIDLE - Transmitter Idle. When 0, indicates that the transmitter is currently in the process of\r
+ * sending data.When 1, indicate that the transmitter is not currently in the process of sending\r
+ * data.\r
+ */\r
+#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK)\r
+#define USART_STAT_CTS_MASK (0x10U)\r
+#define USART_STAT_CTS_SHIFT (4U)\r
+/*! CTS - This bit reflects the current state of the CTS signal, regardless of the setting of the\r
+ * CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode\r
+ * is enabled.\r
+ */\r
+#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK)\r
+#define USART_STAT_DELTACTS_MASK (0x20U)\r
+#define USART_STAT_DELTACTS_SHIFT (5U)\r
+/*! DELTACTS - This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software.\r
+ */\r
+#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK)\r
+#define USART_STAT_TXDISSTAT_MASK (0x40U)\r
+#define USART_STAT_TXDISSTAT_SHIFT (6U)\r
+/*! TXDISSTAT - Transmitter Disabled Status flag. When 1, this bit indicates that the USART\r
+ * transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1).\r
+ */\r
+#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK)\r
+#define USART_STAT_RXBRK_MASK (0x400U)\r
+#define USART_STAT_RXBRK_SHIFT (10U)\r
+/*! RXBRK - Received Break. This bit reflects the current state of the receiver break detection\r
+ * logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also\r
+ * be set when this condition occurs because the stop bit(s) for the character would be missing.\r
+ * RXBRK is cleared when the Un_RXD pin goes high.\r
+ */\r
+#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK)\r
+#define USART_STAT_DELTARXBRK_MASK (0x800U)\r
+#define USART_STAT_DELTARXBRK_SHIFT (11U)\r
+/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. Cleared by software.\r
+ */\r
+#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK)\r
+#define USART_STAT_START_MASK (0x1000U)\r
+#define USART_STAT_START_SHIFT (12U)\r
+/*! START - This bit is set when a start is detected on the receiver input. Its purpose is primarily\r
+ * to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected.\r
+ * Cleared by software.\r
+ */\r
+#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK)\r
+#define USART_STAT_FRAMERRINT_MASK (0x2000U)\r
+#define USART_STAT_FRAMERRINT_SHIFT (13U)\r
+/*! FRAMERRINT - Framing Error interrupt flag. This flag is set when a character is received with a\r
+ * missing stop bit at the expected location. This could be an indication of a baud rate or\r
+ * configuration mismatch with the transmitting source.\r
+ */\r
+#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK)\r
+#define USART_STAT_PARITYERRINT_MASK (0x4000U)\r
+#define USART_STAT_PARITYERRINT_SHIFT (14U)\r
+/*! PARITYERRINT - Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.\r
+ */\r
+#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK)\r
+#define USART_STAT_RXNOISEINT_MASK (0x8000U)\r
+#define USART_STAT_RXNOISEINT_SHIFT (15U)\r
+/*! RXNOISEINT - Received Noise interrupt flag. Three samples of received data are taken in order to\r
+ * determine the value of each received data bit, except in synchronous mode. This acts as a\r
+ * noise filter if one sample disagrees. This flag is set when a received data bit contains one\r
+ * disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or\r
+ * loss of synchronization during data reception.\r
+ */\r
+#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK)\r
+#define USART_STAT_ABERR_MASK (0x10000U)\r
+#define USART_STAT_ABERR_SHIFT (16U)\r
+/*! ABERR - Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the\r
+ * end of the start bit that is being measured, essentially an auto baud time-out.\r
+ */\r
+#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */\r
+/*! @{ */\r
+#define USART_INTENSET_TXIDLEEN_MASK (0x8U)\r
+#define USART_INTENSET_TXIDLEEN_SHIFT (3U)\r
+/*! TXIDLEEN - When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1).\r
+ */\r
+#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK)\r
+#define USART_INTENSET_DELTACTSEN_MASK (0x20U)\r
+#define USART_INTENSET_DELTACTSEN_SHIFT (5U)\r
+/*! DELTACTSEN - When 1, enables an interrupt when there is a change in the state of the CTS input.\r
+ */\r
+#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK)\r
+#define USART_INTENSET_TXDISEN_MASK (0x40U)\r
+#define USART_INTENSET_TXDISEN_SHIFT (6U)\r
+/*! TXDISEN - When 1, enables an interrupt when the transmitter is fully disabled as indicated by\r
+ * the TXDISINT flag in STAT. See description of the TXDISINT bit for details.\r
+ */\r
+#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK)\r
+#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U)\r
+#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U)\r
+/*! DELTARXBRKEN - When 1, enables an interrupt when a change of state has occurred in the detection\r
+ * of a received break condition (break condition asserted or deasserted).\r
+ */\r
+#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK)\r
+#define USART_INTENSET_STARTEN_MASK (0x1000U)\r
+#define USART_INTENSET_STARTEN_SHIFT (12U)\r
+/*! STARTEN - When 1, enables an interrupt when a received start bit has been detected.\r
+ */\r
+#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK)\r
+#define USART_INTENSET_FRAMERREN_MASK (0x2000U)\r
+#define USART_INTENSET_FRAMERREN_SHIFT (13U)\r
+/*! FRAMERREN - When 1, enables an interrupt when a framing error has been detected.\r
+ */\r
+#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK)\r
+#define USART_INTENSET_PARITYERREN_MASK (0x4000U)\r
+#define USART_INTENSET_PARITYERREN_SHIFT (14U)\r
+/*! PARITYERREN - When 1, enables an interrupt when a parity error has been detected.\r
+ */\r
+#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK)\r
+#define USART_INTENSET_RXNOISEEN_MASK (0x8000U)\r
+#define USART_INTENSET_RXNOISEEN_SHIFT (15U)\r
+/*! RXNOISEEN - When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354.\r
+ */\r
+#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK)\r
+#define USART_INTENSET_ABERREN_MASK (0x10000U)\r
+#define USART_INTENSET_ABERREN_SHIFT (16U)\r
+/*! ABERREN - When 1, enables an interrupt when an auto baud error occurs.\r
+ */\r
+#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */\r
+/*! @{ */\r
+#define USART_INTENCLR_TXIDLECLR_MASK (0x8U)\r
+#define USART_INTENCLR_TXIDLECLR_SHIFT (3U)\r
+/*! TXIDLECLR - Writing 1 clears the corresponding bit in the INTENSET register.\r
+ */\r
+#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK)\r
+#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U)\r
+#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U)\r
+/*! DELTACTSCLR - Writing 1 clears the corresponding bit in the INTENSET register.\r
+ */\r
+#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK)\r
+#define USART_INTENCLR_TXDISCLR_MASK (0x40U)\r
+#define USART_INTENCLR_TXDISCLR_SHIFT (6U)\r
+/*! TXDISCLR - Writing 1 clears the corresponding bit in the INTENSET register.\r
+ */\r
+#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK)\r
+#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U)\r
+#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U)\r
+/*! DELTARXBRKCLR - Writing 1 clears the corresponding bit in the INTENSET register.\r
+ */\r
+#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK)\r
+#define USART_INTENCLR_STARTCLR_MASK (0x1000U)\r
+#define USART_INTENCLR_STARTCLR_SHIFT (12U)\r
+/*! STARTCLR - Writing 1 clears the corresponding bit in the INTENSET register.\r
+ */\r
+#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK)\r
+#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U)\r
+#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U)\r
+/*! FRAMERRCLR - Writing 1 clears the corresponding bit in the INTENSET register.\r
+ */\r
+#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK)\r
+#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U)\r
+#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U)\r
+/*! PARITYERRCLR - Writing 1 clears the corresponding bit in the INTENSET register.\r
+ */\r
+#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK)\r
+#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U)\r
+#define USART_INTENCLR_RXNOISECLR_SHIFT (15U)\r
+/*! RXNOISECLR - Writing 1 clears the corresponding bit in the INTENSET register.\r
+ */\r
+#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK)\r
+#define USART_INTENCLR_ABERRCLR_MASK (0x10000U)\r
+#define USART_INTENCLR_ABERRCLR_SHIFT (16U)\r
+/*! ABERRCLR - Writing 1 clears the corresponding bit in the INTENSET register.\r
+ */\r
+#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK)\r
+/*! @} */\r
+\r
+/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */\r
+/*! @{ */\r
+#define USART_BRG_BRGVAL_MASK (0xFFFFU)\r
+#define USART_BRG_BRGVAL_SHIFT (0U)\r
+/*! BRGVAL - This value is used to divide the USART input clock to determine the baud rate, based on\r
+ * the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is\r
+ * divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART\r
+ * function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function.\r
+ */\r
+#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */\r
+/*! @{ */\r
+#define USART_INTSTAT_TXIDLE_MASK (0x8U)\r
+#define USART_INTSTAT_TXIDLE_SHIFT (3U)\r
+/*! TXIDLE - Transmitter Idle status.\r
+ */\r
+#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK)\r
+#define USART_INTSTAT_DELTACTS_MASK (0x20U)\r
+#define USART_INTSTAT_DELTACTS_SHIFT (5U)\r
+/*! DELTACTS - This bit is set when a change in the state of the CTS input is detected.\r
+ */\r
+#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK)\r
+#define USART_INTSTAT_TXDISINT_MASK (0x40U)\r
+#define USART_INTSTAT_TXDISINT_SHIFT (6U)\r
+/*! TXDISINT - Transmitter Disabled Interrupt flag.\r
+ */\r
+#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK)\r
+#define USART_INTSTAT_DELTARXBRK_MASK (0x800U)\r
+#define USART_INTSTAT_DELTARXBRK_SHIFT (11U)\r
+/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs.\r
+ */\r
+#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK)\r
+#define USART_INTSTAT_START_MASK (0x1000U)\r
+#define USART_INTSTAT_START_SHIFT (12U)\r
+/*! START - This bit is set when a start is detected on the receiver input.\r
+ */\r
+#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK)\r
+#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U)\r
+#define USART_INTSTAT_FRAMERRINT_SHIFT (13U)\r
+/*! FRAMERRINT - Framing Error interrupt flag.\r
+ */\r
+#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK)\r
+#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U)\r
+#define USART_INTSTAT_PARITYERRINT_SHIFT (14U)\r
+/*! PARITYERRINT - Parity Error interrupt flag.\r
+ */\r
+#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK)\r
+#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U)\r
+#define USART_INTSTAT_RXNOISEINT_SHIFT (15U)\r
+/*! RXNOISEINT - Received Noise interrupt flag.\r
+ */\r
+#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK)\r
+#define USART_INTSTAT_ABERRINT_MASK (0x10000U)\r
+#define USART_INTSTAT_ABERRINT_SHIFT (16U)\r
+/*! ABERRINT - Auto baud Error Interrupt flag.\r
+ */\r
+#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK)\r
+/*! @} */\r
+\r
+/*! @name OSR - Oversample selection register for asynchronous communication. */\r
+/*! @{ */\r
+#define USART_OSR_OSRVAL_MASK (0xFU)\r
+#define USART_OSR_OSRVAL_SHIFT (0U)\r
+/*! OSRVAL - Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to\r
+ * transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive\r
+ * each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit.\r
+ */\r
+#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name ADDR - Address register for automatic address matching. */\r
+/*! @{ */\r
+#define USART_ADDR_ADDRESS_MASK (0xFFU)\r
+#define USART_ADDR_ADDRESS_SHIFT (0U)\r
+/*! ADDRESS - 8-bit address used with automatic address matching. Used when address detection is\r
+ * enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1).\r
+ */\r
+#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOCFG - FIFO configuration and enable register. */\r
+/*! @{ */\r
+#define USART_FIFOCFG_ENABLETX_MASK (0x1U)\r
+#define USART_FIFOCFG_ENABLETX_SHIFT (0U)\r
+/*! ENABLETX - Enable the transmit FIFO.\r
+ * 0b0..The transmit FIFO is not enabled.\r
+ * 0b1..The transmit FIFO is enabled.\r
+ */\r
+#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK)\r
+#define USART_FIFOCFG_ENABLERX_MASK (0x2U)\r
+#define USART_FIFOCFG_ENABLERX_SHIFT (1U)\r
+/*! ENABLERX - Enable the receive FIFO.\r
+ * 0b0..The receive FIFO is not enabled.\r
+ * 0b1..The receive FIFO is enabled.\r
+ */\r
+#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK)\r
+#define USART_FIFOCFG_SIZE_MASK (0x30U)\r
+#define USART_FIFOCFG_SIZE_SHIFT (4U)\r
+/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16\r
+ * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART.\r
+ */\r
+#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK)\r
+#define USART_FIFOCFG_DMATX_MASK (0x1000U)\r
+#define USART_FIFOCFG_DMATX_SHIFT (12U)\r
+/*! DMATX - DMA configuration for transmit.\r
+ * 0b0..DMA is not used for the transmit function.\r
+ * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.\r
+ */\r
+#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK)\r
+#define USART_FIFOCFG_DMARX_MASK (0x2000U)\r
+#define USART_FIFOCFG_DMARX_SHIFT (13U)\r
+/*! DMARX - DMA configuration for receive.\r
+ * 0b0..DMA is not used for the receive function.\r
+ * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.\r
+ */\r
+#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK)\r
+#define USART_FIFOCFG_WAKETX_MASK (0x4000U)\r
+#define USART_FIFOCFG_WAKETX_SHIFT (14U)\r
+/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power\r
+ * modes (up to power-down, as long as the peripheral function works in that power mode) without\r
+ * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The\r
+ * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware\r
+ * Wake-up control register.\r
+ * 0b0..Only enabled interrupts will wake up the device form reduced power modes.\r
+ * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in\r
+ * FIFOTRIG, even when the TXLVL interrupt is not enabled.\r
+ */\r
+#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK)\r
+#define USART_FIFOCFG_WAKERX_MASK (0x8000U)\r
+#define USART_FIFOCFG_WAKERX_SHIFT (15U)\r
+/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power\r
+ * modes (up to power-down, as long as the peripheral function works in that power mode) without\r
+ * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The\r
+ * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware\r
+ * Wake-up control register.\r
+ * 0b0..Only enabled interrupts will wake up the device form reduced power modes.\r
+ * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in\r
+ * FIFOTRIG, even when the RXLVL interrupt is not enabled.\r
+ */\r
+#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK)\r
+#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U)\r
+#define USART_FIFOCFG_EMPTYTX_SHIFT (16U)\r
+/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.\r
+ */\r
+#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK)\r
+#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U)\r
+#define USART_FIFOCFG_EMPTYRX_SHIFT (17U)\r
+/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.\r
+ */\r
+#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOSTAT - FIFO status register. */\r
+/*! @{ */\r
+#define USART_FIFOSTAT_TXERR_MASK (0x1U)\r
+#define USART_FIFOSTAT_TXERR_SHIFT (0U)\r
+/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow\r
+ * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is\r
+ * needed. Cleared by writing a 1 to this bit.\r
+ */\r
+#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK)\r
+#define USART_FIFOSTAT_RXERR_MASK (0x2U)\r
+#define USART_FIFOSTAT_RXERR_SHIFT (1U)\r
+/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA\r
+ * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit.\r
+ */\r
+#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK)\r
+#define USART_FIFOSTAT_PERINT_MASK (0x8U)\r
+#define USART_FIFOSTAT_PERINT_SHIFT (3U)\r
+/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted\r
+ * an interrupt. The details can be found by reading the peripheral's STAT register.\r
+ */\r
+#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK)\r
+#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U)\r
+#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U)\r
+/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data.\r
+ */\r
+#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK)\r
+#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U)\r
+#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U)\r
+/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be\r
+ * written. When 0, the transmit FIFO is full and another write would cause it to overflow.\r
+ */\r
+#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK)\r
+#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)\r
+#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)\r
+/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty.\r
+ */\r
+#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK)\r
+#define USART_FIFOSTAT_RXFULL_MASK (0x80U)\r
+#define USART_FIFOSTAT_RXFULL_SHIFT (7U)\r
+/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to\r
+ * prevent the peripheral from causing an overflow.\r
+ */\r
+#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK)\r
+#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U)\r
+#define USART_FIFOSTAT_TXLVL_SHIFT (8U)\r
+/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY\r
+ * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at\r
+ * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be\r
+ * 0.\r
+ */\r
+#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK)\r
+#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U)\r
+#define USART_FIFOSTAT_RXLVL_SHIFT (16U)\r
+/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and\r
+ * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the\r
+ * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be\r
+ * 1.\r
+ */\r
+#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */\r
+/*! @{ */\r
+#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U)\r
+#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U)\r
+/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled\r
+ * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.\r
+ * 0b0..Transmit FIFO level does not generate a FIFO level trigger.\r
+ * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.\r
+ */\r
+#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK)\r
+#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U)\r
+#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U)\r
+/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled\r
+ * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.\r
+ * 0b0..Receive FIFO level does not generate a FIFO level trigger.\r
+ * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.\r
+ */\r
+#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK)\r
+#define USART_FIFOTRIG_TXLVL_MASK (0xF00U)\r
+#define USART_FIFOTRIG_TXLVL_SHIFT (8U)\r
+/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled\r
+ * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to\r
+ * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO\r
+ * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX\r
+ * FIFO level decreases to 15 entries (is no longer full).\r
+ */\r
+#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK)\r
+#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U)\r
+#define USART_FIFOTRIG_RXLVL_SHIFT (16U)\r
+/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data\r
+ * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level\r
+ * can wake up the device just enough to perform DMA, then return to the reduced power mode. See\r
+ * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no\r
+ * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX\r
+ * FIFO has received 16 entries (has become full).\r
+ */\r
+#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */\r
+/*! @{ */\r
+#define USART_FIFOINTENSET_TXERR_MASK (0x1U)\r
+#define USART_FIFOINTENSET_TXERR_SHIFT (0U)\r
+/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.\r
+ * 0b0..No interrupt will be generated for a transmit error.\r
+ * 0b1..An interrupt will be generated when a transmit error occurs.\r
+ */\r
+#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK)\r
+#define USART_FIFOINTENSET_RXERR_MASK (0x2U)\r
+#define USART_FIFOINTENSET_RXERR_SHIFT (1U)\r
+/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.\r
+ * 0b0..No interrupt will be generated for a receive error.\r
+ * 0b1..An interrupt will be generated when a receive error occurs.\r
+ */\r
+#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK)\r
+#define USART_FIFOINTENSET_TXLVL_MASK (0x4U)\r
+#define USART_FIFOINTENSET_TXLVL_SHIFT (2U)\r
+/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level\r
+ * specified by the TXLVL field in the FIFOTRIG register.\r
+ * 0b0..No interrupt will be generated based on the TX FIFO level.\r
+ * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases\r
+ * to the level specified by TXLVL in the FIFOTRIG register.\r
+ */\r
+#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK)\r
+#define USART_FIFOINTENSET_RXLVL_MASK (0x8U)\r
+#define USART_FIFOINTENSET_RXLVL_SHIFT (3U)\r
+/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level\r
+ * specified by the TXLVL field in the FIFOTRIG register.\r
+ * 0b0..No interrupt will be generated based on the RX FIFO level.\r
+ * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level\r
+ * increases to the level specified by RXLVL in the FIFOTRIG register.\r
+ */\r
+#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */\r
+/*! @{ */\r
+#define USART_FIFOINTENCLR_TXERR_MASK (0x1U)\r
+#define USART_FIFOINTENCLR_TXERR_SHIFT (0U)\r
+/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.\r
+ */\r
+#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK)\r
+#define USART_FIFOINTENCLR_RXERR_MASK (0x2U)\r
+#define USART_FIFOINTENCLR_RXERR_SHIFT (1U)\r
+/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.\r
+ */\r
+#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK)\r
+#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U)\r
+#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U)\r
+/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.\r
+ */\r
+#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK)\r
+#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U)\r
+#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U)\r
+/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.\r
+ */\r
+#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOINTSTAT - FIFO interrupt status register. */\r
+/*! @{ */\r
+#define USART_FIFOINTSTAT_TXERR_MASK (0x1U)\r
+#define USART_FIFOINTSTAT_TXERR_SHIFT (0U)\r
+/*! TXERR - TX FIFO error.\r
+ */\r
+#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK)\r
+#define USART_FIFOINTSTAT_RXERR_MASK (0x2U)\r
+#define USART_FIFOINTSTAT_RXERR_SHIFT (1U)\r
+/*! RXERR - RX FIFO error.\r
+ */\r
+#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK)\r
+#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U)\r
+#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U)\r
+/*! TXLVL - Transmit FIFO level interrupt.\r
+ */\r
+#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK)\r
+#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U)\r
+#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U)\r
+/*! RXLVL - Receive FIFO level interrupt.\r
+ */\r
+#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK)\r
+#define USART_FIFOINTSTAT_PERINT_MASK (0x10U)\r
+#define USART_FIFOINTSTAT_PERINT_SHIFT (4U)\r
+/*! PERINT - Peripheral interrupt.\r
+ */\r
+#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOWR - FIFO write data. */\r
+/*! @{ */\r
+#define USART_FIFOWR_TXDATA_MASK (0x1FFU)\r
+#define USART_FIFOWR_TXDATA_SHIFT (0U)\r
+/*! TXDATA - Transmit data to the FIFO.\r
+ */\r
+#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFORD - FIFO read data. */\r
+/*! @{ */\r
+#define USART_FIFORD_RXDATA_MASK (0x1FFU)\r
+#define USART_FIFORD_RXDATA_SHIFT (0U)\r
+/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings.\r
+ */\r
+#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK)\r
+#define USART_FIFORD_FRAMERR_MASK (0x2000U)\r
+#define USART_FIFORD_FRAMERR_SHIFT (13U)\r
+/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along\r
+ * with from the FIFO, and indicates that the character was received with a missing stop bit at\r
+ * the expected location. This could be an indication of a baud rate or configuration mismatch\r
+ * with the transmitting source.\r
+ */\r
+#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK)\r
+#define USART_FIFORD_PARITYERR_MASK (0x4000U)\r
+#define USART_FIFORD_PARITYERR_SHIFT (14U)\r
+/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along\r
+ * with from the FIFO. This bit will be set when a parity error is detected in a received\r
+ * character.\r
+ */\r
+#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK)\r
+#define USART_FIFORD_RXNOISE_MASK (0x8000U)\r
+#define USART_FIFORD_RXNOISE_SHIFT (15U)\r
+/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354.\r
+ */\r
+#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */\r
+/*! @{ */\r
+#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU)\r
+#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U)\r
+/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings.\r
+ */\r
+#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK)\r
+#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U)\r
+#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U)\r
+/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along\r
+ * with from the FIFO, and indicates that the character was received with a missing stop bit at\r
+ * the expected location. This could be an indication of a baud rate or configuration mismatch\r
+ * with the transmitting source.\r
+ */\r
+#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK)\r
+#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U)\r
+#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U)\r
+/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along\r
+ * with from the FIFO. This bit will be set when a parity error is detected in a received\r
+ * character.\r
+ */\r
+#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK)\r
+#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U)\r
+#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U)\r
+/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354.\r
+ */\r
+#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK)\r
+/*! @} */\r
+\r
+/*! @name ID - Peripheral identification register. */\r
+/*! @{ */\r
+#define USART_ID_APERTURE_MASK (0xFFU)\r
+#define USART_ID_APERTURE_SHIFT (0U)\r
+/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.\r
+ */\r
+#define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK)\r
+#define USART_ID_MINOR_REV_MASK (0xF00U)\r
+#define USART_ID_MINOR_REV_SHIFT (8U)\r
+/*! MINOR_REV - Minor revision of module implementation.\r
+ */\r
+#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK)\r
+#define USART_ID_MAJOR_REV_MASK (0xF000U)\r
+#define USART_ID_MAJOR_REV_SHIFT (12U)\r
+/*! MAJOR_REV - Major revision of module implementation.\r
+ */\r
+#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK)\r
+#define USART_ID_ID_MASK (0xFFFF0000U)\r
+#define USART_ID_ID_SHIFT (16U)\r
+/*! ID - Module identifier for the selected function.\r
+ */\r
+#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group USART_Register_Masks */\r
+\r
+\r
+/* USART - Peripheral instance base addresses */\r
+/** Peripheral USART0 base address */\r
+#define USART0_BASE (0x40086000u)\r
+/** Peripheral USART0 base pointer */\r
+#define USART0 ((USART_Type *)USART0_BASE)\r
+/** Peripheral USART1 base address */\r
+#define USART1_BASE (0x40087000u)\r
+/** Peripheral USART1 base pointer */\r
+#define USART1 ((USART_Type *)USART1_BASE)\r
+/** Peripheral USART2 base address */\r
+#define USART2_BASE (0x40088000u)\r
+/** Peripheral USART2 base pointer */\r
+#define USART2 ((USART_Type *)USART2_BASE)\r
+/** Peripheral USART3 base address */\r
+#define USART3_BASE (0x40089000u)\r
+/** Peripheral USART3 base pointer */\r
+#define USART3 ((USART_Type *)USART3_BASE)\r
+/** Peripheral USART4 base address */\r
+#define USART4_BASE (0x4008A000u)\r
+/** Peripheral USART4 base pointer */\r
+#define USART4 ((USART_Type *)USART4_BASE)\r
+/** Peripheral USART5 base address */\r
+#define USART5_BASE (0x40096000u)\r
+/** Peripheral USART5 base pointer */\r
+#define USART5 ((USART_Type *)USART5_BASE)\r
+/** Peripheral USART6 base address */\r
+#define USART6_BASE (0x40097000u)\r
+/** Peripheral USART6 base pointer */\r
+#define USART6 ((USART_Type *)USART6_BASE)\r
+/** Peripheral USART7 base address */\r
+#define USART7_BASE (0x40098000u)\r
+/** Peripheral USART7 base pointer */\r
+#define USART7 ((USART_Type *)USART7_BASE)\r
+/** Peripheral USART8 base address */\r
+#define USART8_BASE (0x40099000u)\r
+/** Peripheral USART8 base pointer */\r
+#define USART8 ((USART_Type *)USART8_BASE)\r
+/** Peripheral USART9 base address */\r
+#define USART9_BASE (0x4009A000u)\r
+/** Peripheral USART9 base pointer */\r
+#define USART9 ((USART_Type *)USART9_BASE)\r
+/** Array initializer of USART peripheral base addresses */\r
+#define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE, USART8_BASE, USART9_BASE }\r
+/** Array initializer of USART peripheral base pointers */\r
+#define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7, USART8, USART9 }\r
+/** Interrupt vectors for the USART peripheral type */\r
+#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group USART_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- USB Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** USB - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */\r
+ __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */\r
+ __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */\r
+ __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */\r
+ __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */\r
+ __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */\r
+ __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */\r
+ __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */\r
+ __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */\r
+ __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */\r
+ __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */\r
+ uint8_t RESERVED_0[8];\r
+ __IO uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */\r
+} USB_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- USB Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup USB_Register_Masks USB Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name DEVCMDSTAT - USB Device Command/Status register */\r
+/*! @{ */\r
+#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU)\r
+#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U)\r
+/*! DEV_ADDR - USB device address. After bus reset, the address is reset to 0x00. If the enable bit\r
+ * is set, the device will respond on packets for function address DEV_ADDR. When receiving a\r
+ * SetAddress Control Request from the USB host, software must program the new address before\r
+ * completing the status phase of the SetAddress Control Request.\r
+ */\r
+#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK)\r
+#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U)\r
+#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U)\r
+/*! DEV_EN - USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR.\r
+ */\r
+#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK)\r
+#define USB_DEVCMDSTAT_SETUP_MASK (0x100U)\r
+#define USB_DEVCMDSTAT_SETUP_SHIFT (8U)\r
+/*! SETUP - SETUP token received. If a SETUP token is received and acknowledged by the device, this\r
+ * bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW\r
+ * must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the\r
+ * CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW.\r
+ */\r
+#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK)\r
+#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U)\r
+#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U)\r
+/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on:\r
+ * 0b0..USB_NEEDCLK has normal function.\r
+ * 0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend.\r
+ */\r
+#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK)\r
+#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U)\r
+#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U)\r
+/*! LPM_SUP - LPM Supported:\r
+ * 0b0..LPM not supported.\r
+ * 0b1..LPM supported.\r
+ */\r
+#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK)\r
+#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U)\r
+#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U)\r
+/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP\r
+ * 0b0..Only acknowledged packets generate an interrupt\r
+ * 0b1..Both acknowledged and NAKed packets generate interrupts.\r
+ */\r
+#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK)\r
+#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U)\r
+#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U)\r
+/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP\r
+ * 0b0..Only acknowledged packets generate an interrupt\r
+ * 0b1..Both acknowledged and NAKed packets generate interrupts.\r
+ */\r
+#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK)\r
+#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U)\r
+#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U)\r
+/*! INTONNAK_CO - Interrupt on NAK for control OUT EP\r
+ * 0b0..Only acknowledged packets generate an interrupt\r
+ * 0b1..Both acknowledged and NAKed packets generate interrupts.\r
+ */\r
+#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK)\r
+#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U)\r
+#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U)\r
+/*! INTONNAK_CI - Interrupt on NAK for control IN EP\r
+ * 0b0..Only acknowledged packets generate an interrupt\r
+ * 0b1..Both acknowledged and NAKed packets generate interrupts.\r
+ */\r
+#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK)\r
+#define USB_DEVCMDSTAT_DCON_MASK (0x10000U)\r
+#define USB_DEVCMDSTAT_DCON_SHIFT (16U)\r
+/*! DCON - Device status - connect. The connect bit must be set by SW to indicate that the device\r
+ * must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and\r
+ * the VBUSDEBOUNCED bit is one.\r
+ */\r
+#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK)\r
+#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U)\r
+#define USB_DEVCMDSTAT_DSUS_SHIFT (17U)\r
+/*! DSUS - Device status - suspend. The suspend bit indicates the current suspend state. It is set\r
+ * to 1 when the device hasn't seen any activity on its upstream port for more than 3\r
+ * milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and\r
+ * the software writes a 0 to it, the device will generate a remote wake-up. This will only happen\r
+ * when the device is connected (Connect bit = 1). When the device is not connected or not\r
+ * suspended, a writing a 0 has no effect. Writing a 1 never has an effect.\r
+ */\r
+#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK)\r
+#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U)\r
+#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U)\r
+/*! LPM_SUS - Device status - LPM Suspend. This bit represents the current LPM suspend state. It is\r
+ * set to 1 by HW when the device has acknowledged the LPM request from the USB host and the\r
+ * Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend\r
+ * bit = 1) and the software writes a zero to this bit, the device will generate a remote\r
+ * walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this\r
+ * bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the\r
+ * LPM_SUPP bit is equal to one.\r
+ */\r
+#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK)\r
+#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U)\r
+#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U)\r
+/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake\r
+ * bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the\r
+ * host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset\r
+ * is received. Software can use this bit to check if the remote wake-up feature is enabled by the\r
+ * host for the LPM transaction.\r
+ */\r
+#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK)\r
+#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U)\r
+#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U)\r
+/*! DCON_C - Device status - connect change. The Connect Change bit is set when the device's pull-up\r
+ * resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it.\r
+ */\r
+#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK)\r
+#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U)\r
+#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U)\r
+/*! DSUS_C - Device status - suspend change. The suspend change bit is set to 1 when the suspend bit\r
+ * toggles. The suspend bit can toggle because: - The device goes in the suspended state - The\r
+ * device is disconnected - The device receives resume signaling on its upstream port. The bit is\r
+ * reset by writing a one to it.\r
+ */\r
+#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK)\r
+#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U)\r
+#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U)\r
+/*! DRES_C - Device status - reset change. This bit is set when the device received a bus reset. On\r
+ * a bus reset the device will automatically go to the default state (unconfigured and responding\r
+ * to address 0). The bit is reset by writing a one to it.\r
+ */\r
+#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK)\r
+#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U)\r
+#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U)\r
+/*! VBUSDEBOUNCED - This bit indicates if Vbus is detected or not. The bit raises immediately when\r
+ * Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and\r
+ * the DCon bit is set, the HW will enable the pull-up resistor to signal a connect.\r
+ */\r
+#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK)\r
+/*! @} */\r
+\r
+/*! @name INFO - USB Info register */\r
+/*! @{ */\r
+#define USB_INFO_FRAME_NR_MASK (0x7FFU)\r
+#define USB_INFO_FRAME_NR_SHIFT (0U)\r
+/*! FRAME_NR - Frame number. This contains the frame number of the last successfully received SOF.\r
+ * In case no SOF was received by the device at the beginning of a frame, the frame number\r
+ * returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC\r
+ * error, the frame number returned will be the corrupted frame number as received by the device.\r
+ */\r
+#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK)\r
+#define USB_INFO_ERR_CODE_MASK (0x7800U)\r
+#define USB_INFO_ERR_CODE_SHIFT (11U)\r
+/*! ERR_CODE - The error code which last occurred:\r
+ * 0b0000..No error\r
+ * 0b0001..PID encoding error\r
+ * 0b0010..PID unknown\r
+ * 0b0011..Packet unexpected\r
+ * 0b0100..Token CRC error\r
+ * 0b0101..Data CRC error\r
+ * 0b0110..Time out\r
+ * 0b0111..Babble\r
+ * 0b1000..Truncated EOP\r
+ * 0b1001..Sent/Received NAK\r
+ * 0b1010..Sent Stall\r
+ * 0b1011..Overrun\r
+ * 0b1100..Sent empty packet\r
+ * 0b1101..Bitstuff error\r
+ * 0b1110..Sync error\r
+ * 0b1111..Wrong data toggle\r
+ */\r
+#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK)\r
+#define USB_INFO_MINREV_MASK (0xFF0000U)\r
+#define USB_INFO_MINREV_SHIFT (16U)\r
+/*! MINREV - Minor Revision.\r
+ */\r
+#define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK)\r
+#define USB_INFO_MAJREV_MASK (0xFF000000U)\r
+#define USB_INFO_MAJREV_SHIFT (24U)\r
+/*! MAJREV - Major Revision.\r
+ */\r
+#define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK)\r
+/*! @} */\r
+\r
+/*! @name EPLISTSTART - USB EP Command/Status List start address */\r
+/*! @{ */\r
+#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U)\r
+#define USB_EPLISTSTART_EP_LIST_SHIFT (8U)\r
+/*! EP_LIST - Start address of the USB EP Command/Status List.\r
+ */\r
+#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK)\r
+/*! @} */\r
+\r
+/*! @name DATABUFSTART - USB Data buffer start address */\r
+/*! @{ */\r
+#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U)\r
+#define USB_DATABUFSTART_DA_BUF_SHIFT (22U)\r
+/*! DA_BUF - Start address of the buffer pointer page where all endpoint data buffers are located.\r
+ */\r
+#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK)\r
+/*! @} */\r
+\r
+/*! @name LPM - USB Link Power Management register */\r
+/*! @{ */\r
+#define USB_LPM_HIRD_HW_MASK (0xFU)\r
+#define USB_LPM_HIRD_HW_SHIFT (0U)\r
+/*! HIRD_HW - Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token\r
+ */\r
+#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK)\r
+#define USB_LPM_HIRD_SW_MASK (0xF0U)\r
+#define USB_LPM_HIRD_SW_SHIFT (4U)\r
+/*! HIRD_SW - Host Initiated Resume Duration - SW. This is the time duration required by the USB\r
+ * device system to come out of LPM initiated suspend after receiving the host initiated LPM resume.\r
+ */\r
+#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK)\r
+#define USB_LPM_DATA_PENDING_MASK (0x100U)\r
+#define USB_LPM_DATA_PENDING_SHIFT (8U)\r
+/*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will\r
+ * return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and\r
+ * this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has\r
+ * still data pending and LPM is supported, it must set this bit to 1.\r
+ */\r
+#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK)\r
+/*! @} */\r
+\r
+/*! @name EPSKIP - USB Endpoint skip */\r
+/*! @{ */\r
+#define USB_EPSKIP_SKIP_MASK (0x3FFU)\r
+#define USB_EPSKIP_SKIP_SHIFT (0U)\r
+/*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must\r
+ * deactivate the buffer assigned to this endpoint and return control back to software. When HW has\r
+ * deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An\r
+ * interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering,\r
+ * HW will only clear the Active bit of the buffer indicated by the EPINUSE bit.\r
+ */\r
+#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK)\r
+/*! @} */\r
+\r
+/*! @name EPINUSE - USB Endpoint Buffer in use */\r
+/*! @{ */\r
+#define USB_EPINUSE_BUF_MASK (0x3FCU)\r
+#define USB_EPINUSE_BUF_SHIFT (2U)\r
+/*! BUF - Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer\r
+ * 0. 1: HW is accessing buffer 1.\r
+ */\r
+#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK)\r
+/*! @} */\r
+\r
+/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */\r
+/*! @{ */\r
+#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU)\r
+#define USB_EPBUFCFG_BUF_SB_SHIFT (2U)\r
+/*! BUF_SB - Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1:\r
+ * Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding\r
+ * EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle\r
+ * the EPINUSE bit when it clears the Active bit for the buffer.\r
+ */\r
+#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTSTAT - USB interrupt status register */\r
+/*! @{ */\r
+#define USB_INTSTAT_EP0OUT_MASK (0x1U)\r
+#define USB_INTSTAT_EP0OUT_SHIFT (0U)\r
+/*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. This bit will be set\r
+ * if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is\r
+ * successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a\r
+ * NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a\r
+ * one to it.\r
+ */\r
+#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK)\r
+#define USB_INTSTAT_EP0IN_MASK (0x2U)\r
+#define USB_INTSTAT_EP0IN_SHIFT (1U)\r
+/*! EP0IN - Interrupt status register bit for the Control EP0 IN direction. This bit will be set if\r
+ * NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this\r
+ * bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can\r
+ * clear this bit by writing a one to it.\r
+ */\r
+#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK)\r
+#define USB_INTSTAT_EP1OUT_MASK (0x4U)\r
+#define USB_INTSTAT_EP1OUT_SHIFT (2U)\r
+/*! EP1OUT - Interrupt status register bit for the EP1 OUT direction. This bit will be set if the\r
+ * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes\r
+ * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be\r
+ * set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by\r
+ * writing a one to it.\r
+ */\r
+#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK)\r
+#define USB_INTSTAT_EP1IN_MASK (0x8U)\r
+#define USB_INTSTAT_EP1IN_SHIFT (3U)\r
+/*! EP1IN - Interrupt status register bit for the EP1 IN direction. This bit will be set if the\r
+ * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions\r
+ * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be\r
+ * set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing\r
+ * a one to it.\r
+ */\r
+#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK)\r
+#define USB_INTSTAT_EP2OUT_MASK (0x10U)\r
+#define USB_INTSTAT_EP2OUT_SHIFT (4U)\r
+/*! EP2OUT - Interrupt status register bit for the EP2 OUT direction. This bit will be set if the\r
+ * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes\r
+ * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be\r
+ * set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by\r
+ * writing a one to it.\r
+ */\r
+#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK)\r
+#define USB_INTSTAT_EP2IN_MASK (0x20U)\r
+#define USB_INTSTAT_EP2IN_SHIFT (5U)\r
+/*! EP2IN - Interrupt status register bit for the EP2 IN direction. This bit will be set if the\r
+ * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions\r
+ * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be\r
+ * set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing\r
+ * a one to it.\r
+ */\r
+#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK)\r
+#define USB_INTSTAT_EP3OUT_MASK (0x40U)\r
+#define USB_INTSTAT_EP3OUT_SHIFT (6U)\r
+/*! EP3OUT - Interrupt status register bit for the EP3 OUT direction. This bit will be set if the\r
+ * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes\r
+ * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be\r
+ * set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by\r
+ * writing a one to it.\r
+ */\r
+#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK)\r
+#define USB_INTSTAT_EP3IN_MASK (0x80U)\r
+#define USB_INTSTAT_EP3IN_SHIFT (7U)\r
+/*! EP3IN - Interrupt status register bit for the EP3 IN direction. This bit will be set if the\r
+ * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions\r
+ * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be\r
+ * set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing\r
+ * a one to it.\r
+ */\r
+#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK)\r
+#define USB_INTSTAT_EP4OUT_MASK (0x100U)\r
+#define USB_INTSTAT_EP4OUT_SHIFT (8U)\r
+/*! EP4OUT - Interrupt status register bit for the EP4 OUT direction. This bit will be set if the\r
+ * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes\r
+ * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be\r
+ * set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by\r
+ * writing a one to it.\r
+ */\r
+#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK)\r
+#define USB_INTSTAT_EP4IN_MASK (0x200U)\r
+#define USB_INTSTAT_EP4IN_SHIFT (9U)\r
+/*! EP4IN - Interrupt status register bit for the EP4 IN direction. This bit will be set if the\r
+ * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions\r
+ * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be\r
+ * set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing\r
+ * a one to it.\r
+ */\r
+#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK)\r
+#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U)\r
+#define USB_INTSTAT_FRAME_INT_SHIFT (30U)\r
+/*! FRAME_INT - Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit\r
+ * and the DCON bit are set. This bit can be used by software when handling isochronous\r
+ * endpoints. Software can clear this bit by writing a one to it.\r
+ */\r
+#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK)\r
+#define USB_INTSTAT_DEV_INT_MASK (0x80000000U)\r
+#define USB_INTSTAT_DEV_INT_SHIFT (31U)\r
+/*! DEV_INT - Device status interrupt. This bit is set by HW when one of the bits in the Device\r
+ * Status Change register are set. Software can clear this bit by writing a one to it.\r
+ */\r
+#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTEN - USB interrupt enable register */\r
+/*! @{ */\r
+#define USB_INTEN_EP_INT_EN_MASK (0x3FFU)\r
+#define USB_INTEN_EP_INT_EN_SHIFT (0U)\r
+/*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW\r
+ * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing\r
+ * bit.\r
+ */\r
+#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK)\r
+#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U)\r
+#define USB_INTEN_FRAME_INT_EN_SHIFT (30U)\r
+/*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW\r
+ * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt\r
+ * routing bit.\r
+ */\r
+#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK)\r
+#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U)\r
+#define USB_INTEN_DEV_INT_EN_SHIFT (31U)\r
+/*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW\r
+ * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing\r
+ * bit.\r
+ */\r
+#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTSETSTAT - USB set interrupt status register */\r
+/*! @{ */\r
+#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU)\r
+#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U)\r
+/*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt\r
+ * status bit is set. When this register is read, the same value as the USB interrupt status register\r
+ * is returned.\r
+ */\r
+#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK)\r
+#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U)\r
+#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U)\r
+/*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt\r
+ * status bit is set. When this register is read, the same value as the USB interrupt status\r
+ * register is returned.\r
+ */\r
+#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK)\r
+#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U)\r
+#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U)\r
+/*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt\r
+ * status bit is set. When this register is read, the same value as the USB interrupt status\r
+ * register is returned.\r
+ */\r
+#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK)\r
+/*! @} */\r
+\r
+/*! @name EPTOGGLE - USB Endpoint toggle register */\r
+/*! @{ */\r
+#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU)\r
+#define USB_EPTOGGLE_TOGGLE_SHIFT (0U)\r
+/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint.\r
+ */\r
+#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group USB_Register_Masks */\r
+\r
+\r
+/* USB - Peripheral instance base addresses */\r
+/** Peripheral USB0 base address */\r
+#define USB0_BASE (0x40084000u)\r
+/** Peripheral USB0 base pointer */\r
+#define USB0 ((USB_Type *)USB0_BASE)\r
+/** Array initializer of USB peripheral base addresses */\r
+#define USB_BASE_ADDRS { USB0_BASE }\r
+/** Array initializer of USB peripheral base pointers */\r
+#define USB_BASE_PTRS { USB0 }\r
+/** Interrupt vectors for the USB peripheral type */\r
+#define USB_IRQS { USB0_IRQn }\r
+#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group USB_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- USBFSH Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** USBFSH - Register Layout Typedef */\r
+typedef struct {\r
+ __I uint32_t HCREVISION; /**< BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC), offset: 0x0 */\r
+ __IO uint32_t HCCONTROL; /**< Defines the operating modes of the HC, offset: 0x4 */\r
+ __IO uint32_t HCCOMMANDSTATUS; /**< This register is used to receive the commands from the Host Controller Driver (HCD), offset: 0x8 */\r
+ __IO uint32_t HCINTERRUPTSTATUS; /**< Indicates the status on various events that cause hardware interrupts by setting the appropriate bits, offset: 0xC */\r
+ __IO uint32_t HCINTERRUPTENABLE; /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */\r
+ __IO uint32_t HCINTERRUPTDISABLE; /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */\r
+ __IO uint32_t HCHCCA; /**< Contains the physical address of the host controller communication area, offset: 0x18 */\r
+ __I uint32_t HCPERIODCURRENTED; /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */\r
+ __IO uint32_t HCCONTROLHEADED; /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */\r
+ __IO uint32_t HCCONTROLCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */\r
+ __IO uint32_t HCBULKHEADED; /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */\r
+ __IO uint32_t HCBULKCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */\r
+ __I uint32_t HCDONEHEAD; /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */\r
+ __IO uint32_t HCFMINTERVAL; /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */\r
+ __I uint32_t HCFMREMAINING; /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */\r
+ __I uint32_t HCFMNUMBER; /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */\r
+ __IO uint32_t HCPERIODICSTART; /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */\r
+ __IO uint32_t HCLSTHRESHOLD; /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */\r
+ __IO uint32_t HCRHDESCRIPTORA; /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */\r
+ __IO uint32_t HCRHDESCRIPTORB; /**< Second of the two registers which describes the characteristics of the Root Hub, offset: 0x4C */\r
+ __IO uint32_t HCRHSTATUS; /**< This register is divided into two parts, offset: 0x50 */\r
+ __IO uint32_t HCRHPORTSTATUS; /**< Controls and reports the port events on a per-port basis, offset: 0x54 */\r
+ uint8_t RESERVED_0[4];\r
+ __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */\r
+} USBFSH_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- USBFSH Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup USBFSH_Register_Masks USBFSH Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */\r
+/*! @{ */\r
+#define USBFSH_HCREVISION_REV_MASK (0xFFU)\r
+#define USBFSH_HCREVISION_REV_SHIFT (0U)\r
+/*! REV - Revision.\r
+ */\r
+#define USBFSH_HCREVISION_REV(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCCONTROL - Defines the operating modes of the HC */\r
+/*! @{ */\r
+#define USBFSH_HCCONTROL_CBSR_MASK (0x3U)\r
+#define USBFSH_HCCONTROL_CBSR_SHIFT (0U)\r
+/*! CBSR - ControlBulkServiceRatio.\r
+ */\r
+#define USBFSH_HCCONTROL_CBSR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK)\r
+#define USBFSH_HCCONTROL_PLE_MASK (0x4U)\r
+#define USBFSH_HCCONTROL_PLE_SHIFT (2U)\r
+/*! PLE - PeriodicListEnable.\r
+ */\r
+#define USBFSH_HCCONTROL_PLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK)\r
+#define USBFSH_HCCONTROL_IE_MASK (0x8U)\r
+#define USBFSH_HCCONTROL_IE_SHIFT (3U)\r
+/*! IE - IsochronousEnable.\r
+ */\r
+#define USBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK)\r
+#define USBFSH_HCCONTROL_CLE_MASK (0x10U)\r
+#define USBFSH_HCCONTROL_CLE_SHIFT (4U)\r
+/*! CLE - ControlListEnable.\r
+ */\r
+#define USBFSH_HCCONTROL_CLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK)\r
+#define USBFSH_HCCONTROL_BLE_MASK (0x20U)\r
+#define USBFSH_HCCONTROL_BLE_SHIFT (5U)\r
+/*! BLE - BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame.\r
+ */\r
+#define USBFSH_HCCONTROL_BLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK)\r
+#define USBFSH_HCCONTROL_HCFS_MASK (0xC0U)\r
+#define USBFSH_HCCONTROL_HCFS_SHIFT (6U)\r
+/*! HCFS - HostControllerFunctionalState for USB 00b: USBRESET 01b: USBRESUME 10b: USBOPERATIONAL\r
+ * 11b: USBSUSPEND A transition to USBOPERATIONAL from another state causes SOFgeneration to begin\r
+ * 1 ms later.\r
+ */\r
+#define USBFSH_HCCONTROL_HCFS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK)\r
+#define USBFSH_HCCONTROL_IR_MASK (0x100U)\r
+#define USBFSH_HCCONTROL_IR_SHIFT (8U)\r
+/*! IR - InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus.\r
+ */\r
+#define USBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK)\r
+#define USBFSH_HCCONTROL_RWC_MASK (0x200U)\r
+#define USBFSH_HCCONTROL_RWC_SHIFT (9U)\r
+/*! RWC - RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling.\r
+ */\r
+#define USBFSH_HCCONTROL_RWC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK)\r
+#define USBFSH_HCCONTROL_RWE_MASK (0x400U)\r
+#define USBFSH_HCCONTROL_RWE_SHIFT (10U)\r
+/*! RWE - RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature\r
+ * upon the detection of upstream resume signaling.\r
+ */\r
+#define USBFSH_HCCONTROL_RWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */\r
+/*! @{ */\r
+#define USBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U)\r
+#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U)\r
+/*! HCR - HostControllerReset This bit is set by HCD to initiate a software reset of HC.\r
+ */\r
+#define USBFSH_HCCOMMANDSTATUS_HCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK)\r
+#define USBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U)\r
+#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U)\r
+/*! CLF - ControlListFilled This bit is used to indicate whether there are any TDs on the Control list.\r
+ */\r
+#define USBFSH_HCCOMMANDSTATUS_CLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK)\r
+#define USBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U)\r
+#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U)\r
+/*! BLF - BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list.\r
+ */\r
+#define USBFSH_HCCOMMANDSTATUS_BLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK)\r
+#define USBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U)\r
+#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U)\r
+/*! OCR - OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC.\r
+ */\r
+#define USBFSH_HCCOMMANDSTATUS_OCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK)\r
+#define USBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U)\r
+#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U)\r
+/*! SOC - SchedulingOverrunCount These bits are incremented on each scheduling overrun error.\r
+ */\r
+#define USBFSH_HCCOMMANDSTATUS_SOC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */\r
+/*! @{ */\r
+#define USBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U)\r
+#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U)\r
+/*! SO - SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and\r
+ * after the update of HccaFrameNumber.\r
+ */\r
+#define USBFSH_HCINTERRUPTSTATUS_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK)\r
+#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U)\r
+#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U)\r
+/*! WDH - WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead.\r
+ */\r
+#define USBFSH_HCINTERRUPTSTATUS_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK)\r
+#define USBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U)\r
+#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U)\r
+/*! SF - StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber.\r
+ */\r
+#define USBFSH_HCINTERRUPTSTATUS_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK)\r
+#define USBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U)\r
+#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U)\r
+/*! RD - ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling.\r
+ */\r
+#define USBFSH_HCINTERRUPTSTATUS_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK)\r
+#define USBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U)\r
+#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U)\r
+/*! UE - UnrecoverableError This bit is set when HC detects a system error not related to USB.\r
+ */\r
+#define USBFSH_HCINTERRUPTSTATUS_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK)\r
+#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U)\r
+#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U)\r
+/*! FNO - FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value,\r
+ * from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated.\r
+ */\r
+#define USBFSH_HCINTERRUPTSTATUS_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK)\r
+#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U)\r
+#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U)\r
+/*! RHSC - RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any\r
+ * of HcRhPortStatus[NumberofDownstreamPort] has changed.\r
+ */\r
+#define USBFSH_HCINTERRUPTSTATUS_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK)\r
+#define USBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U)\r
+#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U)\r
+/*! OC - OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus.\r
+ */\r
+#define USBFSH_HCINTERRUPTSTATUS_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */\r
+/*! @{ */\r
+#define USBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U)\r
+#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U)\r
+/*! SO - Scheduling Overrun interrupt.\r
+ */\r
+#define USBFSH_HCINTERRUPTENABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK)\r
+#define USBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U)\r
+#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U)\r
+/*! WDH - HcDoneHead Writeback interrupt.\r
+ */\r
+#define USBFSH_HCINTERRUPTENABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK)\r
+#define USBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U)\r
+#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U)\r
+/*! SF - Start of Frame interrupt.\r
+ */\r
+#define USBFSH_HCINTERRUPTENABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK)\r
+#define USBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U)\r
+#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U)\r
+/*! RD - Resume Detect interrupt.\r
+ */\r
+#define USBFSH_HCINTERRUPTENABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK)\r
+#define USBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U)\r
+#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U)\r
+/*! UE - Unrecoverable Error interrupt.\r
+ */\r
+#define USBFSH_HCINTERRUPTENABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK)\r
+#define USBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U)\r
+#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U)\r
+/*! FNO - Frame Number Overflow interrupt.\r
+ */\r
+#define USBFSH_HCINTERRUPTENABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK)\r
+#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U)\r
+#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U)\r
+/*! RHSC - Root Hub Status Change interrupt.\r
+ */\r
+#define USBFSH_HCINTERRUPTENABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK)\r
+#define USBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U)\r
+#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U)\r
+/*! OC - Ownership Change interrupt.\r
+ */\r
+#define USBFSH_HCINTERRUPTENABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK)\r
+#define USBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U)\r
+#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U)\r
+/*! MIE - Master Interrupt Enable.\r
+ */\r
+#define USBFSH_HCINTERRUPTENABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */\r
+/*! @{ */\r
+#define USBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U)\r
+#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U)\r
+/*! SO - Scheduling Overrun interrupt.\r
+ */\r
+#define USBFSH_HCINTERRUPTDISABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK)\r
+#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U)\r
+#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U)\r
+/*! WDH - HcDoneHead Writeback interrupt.\r
+ */\r
+#define USBFSH_HCINTERRUPTDISABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK)\r
+#define USBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U)\r
+#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U)\r
+/*! SF - Start of Frame interrupt.\r
+ */\r
+#define USBFSH_HCINTERRUPTDISABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK)\r
+#define USBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U)\r
+#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U)\r
+/*! RD - Resume Detect interrupt.\r
+ */\r
+#define USBFSH_HCINTERRUPTDISABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK)\r
+#define USBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U)\r
+#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U)\r
+/*! UE - Unrecoverable Error interrupt.\r
+ */\r
+#define USBFSH_HCINTERRUPTDISABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK)\r
+#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U)\r
+#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U)\r
+/*! FNO - Frame Number Overflow interrupt.\r
+ */\r
+#define USBFSH_HCINTERRUPTDISABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK)\r
+#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U)\r
+#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U)\r
+/*! RHSC - Root Hub Status Change interrupt.\r
+ */\r
+#define USBFSH_HCINTERRUPTDISABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK)\r
+#define USBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U)\r
+#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U)\r
+/*! OC - Ownership Change interrupt.\r
+ */\r
+#define USBFSH_HCINTERRUPTDISABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK)\r
+#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U)\r
+#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U)\r
+/*! MIE - A 0 written to this field is ignored by HC.\r
+ */\r
+#define USBFSH_HCINTERRUPTDISABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCHCCA - Contains the physical address of the host controller communication area */\r
+/*! @{ */\r
+#define USBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U)\r
+#define USBFSH_HCHCCA_HCCA_SHIFT (8U)\r
+/*! HCCA - Base address of the Host Controller Communication Area.\r
+ */\r
+#define USBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */\r
+/*! @{ */\r
+#define USBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U)\r
+#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U)\r
+/*! PCED - The content of this register is updated by HC after a periodic ED is processed.\r
+ */\r
+#define USBFSH_HCPERIODCURRENTED_PCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */\r
+/*! @{ */\r
+#define USBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U)\r
+#define USBFSH_HCCONTROLHEADED_CHED_SHIFT (4U)\r
+/*! CHED - HC traverses the Control list starting with the HcControlHeadED pointer.\r
+ */\r
+#define USBFSH_HCCONTROLHEADED_CHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */\r
+/*! @{ */\r
+#define USBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U)\r
+#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U)\r
+/*! CCED - ControlCurrentED.\r
+ */\r
+#define USBFSH_HCCONTROLCURRENTED_CCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */\r
+/*! @{ */\r
+#define USBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U)\r
+#define USBFSH_HCBULKHEADED_BHED_SHIFT (4U)\r
+/*! BHED - BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer.\r
+ */\r
+#define USBFSH_HCBULKHEADED_BHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */\r
+/*! @{ */\r
+#define USBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U)\r
+#define USBFSH_HCBULKCURRENTED_BCED_SHIFT (4U)\r
+/*! BCED - BulkCurrentED This is advanced to the next ED after the HC has served the current one.\r
+ */\r
+#define USBFSH_HCBULKCURRENTED_BCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */\r
+/*! @{ */\r
+#define USBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U)\r
+#define USBFSH_HCDONEHEAD_DH_SHIFT (4U)\r
+/*! DH - DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD.\r
+ */\r
+#define USBFSH_HCDONEHEAD_DH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */\r
+/*! @{ */\r
+#define USBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU)\r
+#define USBFSH_HCFMINTERVAL_FI_SHIFT (0U)\r
+/*! FI - FrameInterval This specifies the interval between two consecutive SOFs in bit times.\r
+ */\r
+#define USBFSH_HCFMINTERVAL_FI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK)\r
+#define USBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U)\r
+#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U)\r
+/*! FSMPS - FSLargestDataPacket This field specifies a value which is loaded into the Largest Data\r
+ * Packet Counter at the beginning of each frame.\r
+ */\r
+#define USBFSH_HCFMINTERVAL_FSMPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK)\r
+#define USBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U)\r
+#define USBFSH_HCFMINTERVAL_FIT_SHIFT (31U)\r
+/*! FIT - FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval.\r
+ */\r
+#define USBFSH_HCFMINTERVAL_FIT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */\r
+/*! @{ */\r
+#define USBFSH_HCFMREMAINING_FR_MASK (0x3FFFU)\r
+#define USBFSH_HCFMREMAINING_FR_SHIFT (0U)\r
+/*! FR - FrameRemaining This counter is decremented at each bit time.\r
+ */\r
+#define USBFSH_HCFMREMAINING_FR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK)\r
+#define USBFSH_HCFMREMAINING_FRT_MASK (0x80000000U)\r
+#define USBFSH_HCFMREMAINING_FRT_SHIFT (31U)\r
+/*! FRT - FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval\r
+ * whenever FrameRemaining reaches 0.\r
+ */\r
+#define USBFSH_HCFMREMAINING_FRT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */\r
+/*! @{ */\r
+#define USBFSH_HCFMNUMBER_FN_MASK (0xFFFFU)\r
+#define USBFSH_HCFMNUMBER_FN_SHIFT (0U)\r
+/*! FN - FrameNumber This is incremented when HcFmRemaining is re-loaded.\r
+ */\r
+#define USBFSH_HCFMNUMBER_FN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */\r
+/*! @{ */\r
+#define USBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU)\r
+#define USBFSH_HCPERIODICSTART_PS_SHIFT (0U)\r
+/*! PS - PeriodicStart After a hardware reset, this field is cleared and then set by HCD during the HC initialization.\r
+ */\r
+#define USBFSH_HCPERIODICSTART_PS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */\r
+/*! @{ */\r
+#define USBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU)\r
+#define USBFSH_HCLSTHRESHOLD_LST_SHIFT (0U)\r
+/*! LST - LSThreshold This field contains a value which is compared to the FrameRemaining field\r
+ * prior to initiating a Low Speed transaction.\r
+ */\r
+#define USBFSH_HCLSTHRESHOLD_LST(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */\r
+/*! @{ */\r
+#define USBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU)\r
+#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U)\r
+/*! NDP - NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub.\r
+ */\r
+#define USBFSH_HCRHDESCRIPTORA_NDP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK)\r
+#define USBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U)\r
+#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U)\r
+/*! PSM - PowerSwitchingMode This bit is used to specify how the power switching of the root hub ports is controlled.\r
+ */\r
+#define USBFSH_HCRHDESCRIPTORA_PSM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK)\r
+#define USBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U)\r
+#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U)\r
+/*! NPS - NoPowerSwitching These bits are used to specify whether power switching is supported or port are always powered.\r
+ */\r
+#define USBFSH_HCRHDESCRIPTORA_NPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK)\r
+#define USBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U)\r
+#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U)\r
+/*! DT - DeviceType This bit specifies that the root hub is not a compound device.\r
+ */\r
+#define USBFSH_HCRHDESCRIPTORA_DT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK)\r
+#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U)\r
+#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U)\r
+/*! OCPM - OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported.\r
+ */\r
+#define USBFSH_HCRHDESCRIPTORA_OCPM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK)\r
+#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U)\r
+#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U)\r
+/*! NOCP - NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported.\r
+ */\r
+#define USBFSH_HCRHDESCRIPTORA_NOCP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK)\r
+#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U)\r
+#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U)\r
+/*! POTPGT - PowerOnToPowerGoodTime This byte specifies the duration the HCD has to wait before\r
+ * accessing a powered-on port of the root hub.\r
+ */\r
+#define USBFSH_HCRHDESCRIPTORA_POTPGT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */\r
+/*! @{ */\r
+#define USBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU)\r
+#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U)\r
+/*! DR - DeviceRemovable Each bit is dedicated to a port of the Root Hub.\r
+ */\r
+#define USBFSH_HCRHDESCRIPTORB_DR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK)\r
+#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U)\r
+#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U)\r
+/*! PPCM - PortPowerControlMask Each bit indicates if a port is affected by a global power control\r
+ * command when PowerSwitchingMode is set.\r
+ */\r
+#define USBFSH_HCRHDESCRIPTORB_PPCM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCRHSTATUS - This register is divided into two parts */\r
+/*! @{ */\r
+#define USBFSH_HCRHSTATUS_LPS_MASK (0x1U)\r
+#define USBFSH_HCRHSTATUS_LPS_SHIFT (0U)\r
+/*! LPS - (read) LocalPowerStatus The Root Hub does not support the local power status feature;\r
+ * thus, this bit is always read as 0.\r
+ */\r
+#define USBFSH_HCRHSTATUS_LPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK)\r
+#define USBFSH_HCRHSTATUS_OCI_MASK (0x2U)\r
+#define USBFSH_HCRHSTATUS_OCI_SHIFT (1U)\r
+/*! OCI - OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented.\r
+ */\r
+#define USBFSH_HCRHSTATUS_OCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK)\r
+#define USBFSH_HCRHSTATUS_DRWE_MASK (0x8000U)\r
+#define USBFSH_HCRHSTATUS_DRWE_SHIFT (15U)\r
+/*! DRWE - (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume\r
+ * event, causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected\r
+ * interrupt.\r
+ */\r
+#define USBFSH_HCRHSTATUS_DRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK)\r
+#define USBFSH_HCRHSTATUS_LPSC_MASK (0x10000U)\r
+#define USBFSH_HCRHSTATUS_LPSC_SHIFT (16U)\r
+/*! LPSC - (read) LocalPowerStatusChange The root hub does not support the local power status feature.\r
+ */\r
+#define USBFSH_HCRHSTATUS_LPSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK)\r
+#define USBFSH_HCRHSTATUS_OCIC_MASK (0x20000U)\r
+#define USBFSH_HCRHSTATUS_OCIC_SHIFT (17U)\r
+/*! OCIC - OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register.\r
+ */\r
+#define USBFSH_HCRHSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK)\r
+#define USBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U)\r
+#define USBFSH_HCRHSTATUS_CRWE_SHIFT (31U)\r
+/*! CRWE - (write) ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable.\r
+ */\r
+#define USBFSH_HCRHSTATUS_CRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */\r
+/*! @{ */\r
+#define USBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U)\r
+#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U)\r
+/*! CCS - (read) CurrentConnectStatus This bit reflects the current state of the downstream port.\r
+ */\r
+#define USBFSH_HCRHPORTSTATUS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK)\r
+#define USBFSH_HCRHPORTSTATUS_PES_MASK (0x2U)\r
+#define USBFSH_HCRHPORTSTATUS_PES_SHIFT (1U)\r
+/*! PES - (read) PortEnableStatus This bit indicates whether the port is enabled or disabled.\r
+ */\r
+#define USBFSH_HCRHPORTSTATUS_PES(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK)\r
+#define USBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U)\r
+#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U)\r
+/*! PSS - (read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence.\r
+ */\r
+#define USBFSH_HCRHPORTSTATUS_PSS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK)\r
+#define USBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U)\r
+#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U)\r
+/*! POCI - (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in\r
+ * such a way that overcurrent conditions are reported on a per-port basis.\r
+ */\r
+#define USBFSH_HCRHPORTSTATUS_POCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK)\r
+#define USBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U)\r
+#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U)\r
+/*! PRS - (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted.\r
+ */\r
+#define USBFSH_HCRHPORTSTATUS_PRS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK)\r
+#define USBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U)\r
+#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U)\r
+/*! PPS - (read) PortPowerStatus This bit reflects the porta's power status, regardless of the type\r
+ * of power switching implemented.\r
+ */\r
+#define USBFSH_HCRHPORTSTATUS_PPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK)\r
+#define USBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U)\r
+#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U)\r
+/*! LSDA - (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port.\r
+ */\r
+#define USBFSH_HCRHPORTSTATUS_LSDA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK)\r
+#define USBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U)\r
+#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U)\r
+/*! CSC - ConnectStatusChange This bit is set whenever a connect or disconnect event occurs.\r
+ */\r
+#define USBFSH_HCRHPORTSTATUS_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK)\r
+#define USBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U)\r
+#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U)\r
+/*! PESC - PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared.\r
+ */\r
+#define USBFSH_HCRHPORTSTATUS_PESC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK)\r
+#define USBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U)\r
+#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U)\r
+/*! PSSC - PortSuspendStatusChange This bit is set when the full resume sequence is completed.\r
+ */\r
+#define USBFSH_HCRHPORTSTATUS_PSSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK)\r
+#define USBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U)\r
+#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U)\r
+/*! OCIC - PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis.\r
+ */\r
+#define USBFSH_HCRHPORTSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK)\r
+#define USBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U)\r
+#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U)\r
+/*! PRSC - PortResetStatusChange This bit is set at the end of the 10 ms port reset signal.\r
+ */\r
+#define USBFSH_HCRHPORTSTATUS_PRSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK)\r
+/*! @} */\r
+\r
+/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */\r
+/*! @{ */\r
+#define USBFSH_PORTMODE_ID_MASK (0x1U)\r
+#define USBFSH_PORTMODE_ID_SHIFT (0U)\r
+/*! ID - Port ID pin value.\r
+ */\r
+#define USBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK)\r
+#define USBFSH_PORTMODE_ID_EN_MASK (0x100U)\r
+#define USBFSH_PORTMODE_ID_EN_SHIFT (8U)\r
+/*! ID_EN - Port ID pin pull-up enable.\r
+ */\r
+#define USBFSH_PORTMODE_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK)\r
+#define USBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U)\r
+#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U)\r
+/*! DEV_ENABLE - 1: device 0: host.\r
+ */\r
+#define USBFSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group USBFSH_Register_Masks */\r
+\r
+\r
+/* USBFSH - Peripheral instance base addresses */\r
+/** Peripheral USBFSH base address */\r
+#define USBFSH_BASE (0x400A2000u)\r
+/** Peripheral USBFSH base pointer */\r
+#define USBFSH ((USBFSH_Type *)USBFSH_BASE)\r
+/** Array initializer of USBFSH peripheral base addresses */\r
+#define USBFSH_BASE_ADDRS { USBFSH_BASE }\r
+/** Array initializer of USBFSH peripheral base pointers */\r
+#define USBFSH_BASE_PTRS { USBFSH }\r
+/** Interrupt vectors for the USBFSH peripheral type */\r
+#define USBFSH_IRQS { USB0_IRQn }\r
+#define USBFSH_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group USBFSH_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- USBHSD Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup USBHSD_Peripheral_Access_Layer USBHSD Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** USBHSD - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */\r
+ __I uint32_t INFO; /**< USB Info register, offset: 0x4 */\r
+ __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */\r
+ __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */\r
+ __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */\r
+ __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */\r
+ __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */\r
+ __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */\r
+ __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */\r
+ __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */\r
+ __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */\r
+ uint8_t RESERVED_0[8];\r
+ __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */\r
+} USBHSD_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- USBHSD Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup USBHSD_Register_Masks USBHSD Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name DEVCMDSTAT - USB Device Command/Status register */\r
+/*! @{ */\r
+#define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU)\r
+#define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT (0U)\r
+/*! DEV_ADDR - USB device address.\r
+ */\r
+#define USBHSD_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK)\r
+#define USBHSD_DEVCMDSTAT_DEV_EN_MASK (0x80U)\r
+#define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT (7U)\r
+/*! DEV_EN - USB device enable.\r
+ */\r
+#define USBHSD_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK)\r
+#define USBHSD_DEVCMDSTAT_SETUP_MASK (0x100U)\r
+#define USBHSD_DEVCMDSTAT_SETUP_SHIFT (8U)\r
+/*! SETUP - SETUP token received.\r
+ */\r
+#define USBHSD_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK)\r
+#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U)\r
+#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U)\r
+/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on:.\r
+ */\r
+#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK)\r
+#define USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK (0x400U)\r
+#define USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT (10U)\r
+/*! FORCE_VBUS - If this bit is set to 1, the VBUS voltage indicators from the PHY are overruled.\r
+ */\r
+#define USBHSD_DEVCMDSTAT_FORCE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK)\r
+#define USBHSD_DEVCMDSTAT_LPM_SUP_MASK (0x800U)\r
+#define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT (11U)\r
+/*! LPM_SUP - LPM Supported:.\r
+ */\r
+#define USBHSD_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK)\r
+#define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U)\r
+#define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U)\r
+/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP:.\r
+ */\r
+#define USBHSD_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK)\r
+#define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U)\r
+#define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U)\r
+/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP:.\r
+ */\r
+#define USBHSD_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK)\r
+#define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U)\r
+#define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U)\r
+/*! INTONNAK_CO - Interrupt on NAK for control OUT EP:.\r
+ */\r
+#define USBHSD_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK)\r
+#define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U)\r
+#define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U)\r
+/*! INTONNAK_CI - Interrupt on NAK for control IN EP:.\r
+ */\r
+#define USBHSD_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK)\r
+#define USBHSD_DEVCMDSTAT_DCON_MASK (0x10000U)\r
+#define USBHSD_DEVCMDSTAT_DCON_SHIFT (16U)\r
+/*! DCON - Device status - connect.\r
+ */\r
+#define USBHSD_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK)\r
+#define USBHSD_DEVCMDSTAT_DSUS_MASK (0x20000U)\r
+#define USBHSD_DEVCMDSTAT_DSUS_SHIFT (17U)\r
+/*! DSUS - Device status - suspend.\r
+ */\r
+#define USBHSD_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK)\r
+#define USBHSD_DEVCMDSTAT_LPM_SUS_MASK (0x80000U)\r
+#define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT (19U)\r
+/*! LPM_SUS - Device status - LPM Suspend.\r
+ */\r
+#define USBHSD_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK)\r
+#define USBHSD_DEVCMDSTAT_LPM_REWP_MASK (0x100000U)\r
+#define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT (20U)\r
+/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host.\r
+ */\r
+#define USBHSD_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK)\r
+#define USBHSD_DEVCMDSTAT_Speed_MASK (0xC00000U)\r
+#define USBHSD_DEVCMDSTAT_Speed_SHIFT (22U)\r
+/*! Speed - This field indicates the speed at which the device operates: 00b: reserved 01b:\r
+ * full-speed 10b: high-speed 11b: super-speed (reserved for future use).\r
+ */\r
+#define USBHSD_DEVCMDSTAT_Speed(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK)\r
+#define USBHSD_DEVCMDSTAT_DCON_C_MASK (0x1000000U)\r
+#define USBHSD_DEVCMDSTAT_DCON_C_SHIFT (24U)\r
+/*! DCON_C - Device status - connect change.\r
+ */\r
+#define USBHSD_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK)\r
+#define USBHSD_DEVCMDSTAT_DSUS_C_MASK (0x2000000U)\r
+#define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT (25U)\r
+/*! DSUS_C - Device status - suspend change.\r
+ */\r
+#define USBHSD_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK)\r
+#define USBHSD_DEVCMDSTAT_DRES_C_MASK (0x4000000U)\r
+#define USBHSD_DEVCMDSTAT_DRES_C_SHIFT (26U)\r
+/*! DRES_C - Device status - reset change.\r
+ */\r
+#define USBHSD_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK)\r
+#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK (0x10000000U)\r
+#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT (28U)\r
+/*! VBUS_DEBOUNCED - This bit indicates if VBUS is detected or not.\r
+ */\r
+#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK)\r
+#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK (0xE0000000U)\r
+#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT (29U)\r
+/*! PHY_TEST_MODE - This field is written by firmware to put the PHY into a test mode as defined by the USB2.\r
+ */\r
+#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK)\r
+/*! @} */\r
+\r
+/*! @name INFO - USB Info register */\r
+/*! @{ */\r
+#define USBHSD_INFO_FRAME_NR_MASK (0x7FFU)\r
+#define USBHSD_INFO_FRAME_NR_SHIFT (0U)\r
+/*! FRAME_NR - Frame number.\r
+ */\r
+#define USBHSD_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK)\r
+#define USBHSD_INFO_ERR_CODE_MASK (0x7800U)\r
+#define USBHSD_INFO_ERR_CODE_SHIFT (11U)\r
+/*! ERR_CODE - The error code which last occurred:.\r
+ */\r
+#define USBHSD_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK)\r
+#define USBHSD_INFO_Minrev_MASK (0xFF0000U)\r
+#define USBHSD_INFO_Minrev_SHIFT (16U)\r
+/*! Minrev - Minor revision.\r
+ */\r
+#define USBHSD_INFO_Minrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Minrev_SHIFT)) & USBHSD_INFO_Minrev_MASK)\r
+#define USBHSD_INFO_Majrev_MASK (0xFF000000U)\r
+#define USBHSD_INFO_Majrev_SHIFT (24U)\r
+/*! Majrev - Major revision.\r
+ */\r
+#define USBHSD_INFO_Majrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Majrev_SHIFT)) & USBHSD_INFO_Majrev_MASK)\r
+/*! @} */\r
+\r
+/*! @name EPLISTSTART - USB EP Command/Status List start address */\r
+/*! @{ */\r
+#define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK (0xFFF00U)\r
+#define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT (8U)\r
+/*! EP_LIST_PRG - Programmable portion of the USB EP Command/Status List address.\r
+ */\r
+#define USBHSD_EPLISTSTART_EP_LIST_PRG(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK)\r
+#define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK (0xFFF00000U)\r
+#define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT (20U)\r
+/*! EP_LIST_FIXED - Fixed portion of USB EP Command/Status List address.\r
+ */\r
+#define USBHSD_EPLISTSTART_EP_LIST_FIXED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK)\r
+/*! @} */\r
+\r
+/*! @name DATABUFSTART - USB Data buffer start address */\r
+/*! @{ */\r
+#define USBHSD_DATABUFSTART_DA_BUF_MASK (0xFFFC0000U)\r
+#define USBHSD_DATABUFSTART_DA_BUF_SHIFT (18U)\r
+/*! DA_BUF - Start address of the memory page where all endpoint data buffers are located.\r
+ */\r
+#define USBHSD_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK)\r
+/*! @} */\r
+\r
+/*! @name LPM - USB Link Power Management register */\r
+/*! @{ */\r
+#define USBHSD_LPM_HIRD_HW_MASK (0xFU)\r
+#define USBHSD_LPM_HIRD_HW_SHIFT (0U)\r
+/*! HIRD_HW - Host Initiated Resume Duration - HW.\r
+ */\r
+#define USBHSD_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK)\r
+#define USBHSD_LPM_HIRD_SW_MASK (0xF0U)\r
+#define USBHSD_LPM_HIRD_SW_SHIFT (4U)\r
+/*! HIRD_SW - Host Initiated Resume Duration - SW.\r
+ */\r
+#define USBHSD_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK)\r
+#define USBHSD_LPM_DATA_PENDING_MASK (0x100U)\r
+#define USBHSD_LPM_DATA_PENDING_SHIFT (8U)\r
+/*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will\r
+ * return a NYET handshake on every LPM token it receives.\r
+ */\r
+#define USBHSD_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK)\r
+/*! @} */\r
+\r
+/*! @name EPSKIP - USB Endpoint skip */\r
+/*! @{ */\r
+#define USBHSD_EPSKIP_SKIP_MASK (0xFFFU)\r
+#define USBHSD_EPSKIP_SKIP_SHIFT (0U)\r
+/*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must\r
+ * deactivate the buffer assigned to this endpoint and return control back to software.\r
+ */\r
+#define USBHSD_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK)\r
+/*! @} */\r
+\r
+/*! @name EPINUSE - USB Endpoint Buffer in use */\r
+/*! @{ */\r
+#define USBHSD_EPINUSE_BUF_MASK (0xFFCU)\r
+#define USBHSD_EPINUSE_BUF_SHIFT (2U)\r
+/*! BUF - Buffer in use: This register has one bit per physical endpoint.\r
+ */\r
+#define USBHSD_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK)\r
+/*! @} */\r
+\r
+/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */\r
+/*! @{ */\r
+#define USBHSD_EPBUFCFG_BUF_SB_MASK (0xFFCU)\r
+#define USBHSD_EPBUFCFG_BUF_SB_SHIFT (2U)\r
+/*! BUF_SB - Buffer usage: This register has one bit per physical endpoint.\r
+ */\r
+#define USBHSD_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTSTAT - USB interrupt status register */\r
+/*! @{ */\r
+#define USBHSD_INTSTAT_EP0OUT_MASK (0x1U)\r
+#define USBHSD_INTSTAT_EP0OUT_SHIFT (0U)\r
+/*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction.\r
+ */\r
+#define USBHSD_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK)\r
+#define USBHSD_INTSTAT_EP0IN_MASK (0x2U)\r
+#define USBHSD_INTSTAT_EP0IN_SHIFT (1U)\r
+/*! EP0IN - Interrupt status register bit for the Control EP0 IN direction.\r
+ */\r
+#define USBHSD_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK)\r
+#define USBHSD_INTSTAT_EP1OUT_MASK (0x4U)\r
+#define USBHSD_INTSTAT_EP1OUT_SHIFT (2U)\r
+/*! EP1OUT - Interrupt status register bit for the EP1 OUT direction.\r
+ */\r
+#define USBHSD_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK)\r
+#define USBHSD_INTSTAT_EP1IN_MASK (0x8U)\r
+#define USBHSD_INTSTAT_EP1IN_SHIFT (3U)\r
+/*! EP1IN - Interrupt status register bit for the EP1 IN direction.\r
+ */\r
+#define USBHSD_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK)\r
+#define USBHSD_INTSTAT_EP2OUT_MASK (0x10U)\r
+#define USBHSD_INTSTAT_EP2OUT_SHIFT (4U)\r
+/*! EP2OUT - Interrupt status register bit for the EP2 OUT direction.\r
+ */\r
+#define USBHSD_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK)\r
+#define USBHSD_INTSTAT_EP2IN_MASK (0x20U)\r
+#define USBHSD_INTSTAT_EP2IN_SHIFT (5U)\r
+/*! EP2IN - Interrupt status register bit for the EP2 IN direction.\r
+ */\r
+#define USBHSD_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK)\r
+#define USBHSD_INTSTAT_EP3OUT_MASK (0x40U)\r
+#define USBHSD_INTSTAT_EP3OUT_SHIFT (6U)\r
+/*! EP3OUT - Interrupt status register bit for the EP3 OUT direction.\r
+ */\r
+#define USBHSD_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK)\r
+#define USBHSD_INTSTAT_EP3IN_MASK (0x80U)\r
+#define USBHSD_INTSTAT_EP3IN_SHIFT (7U)\r
+/*! EP3IN - Interrupt status register bit for the EP3 IN direction.\r
+ */\r
+#define USBHSD_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK)\r
+#define USBHSD_INTSTAT_EP4OUT_MASK (0x100U)\r
+#define USBHSD_INTSTAT_EP4OUT_SHIFT (8U)\r
+/*! EP4OUT - Interrupt status register bit for the EP4 OUT direction.\r
+ */\r
+#define USBHSD_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK)\r
+#define USBHSD_INTSTAT_EP4IN_MASK (0x200U)\r
+#define USBHSD_INTSTAT_EP4IN_SHIFT (9U)\r
+/*! EP4IN - Interrupt status register bit for the EP4 IN direction.\r
+ */\r
+#define USBHSD_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK)\r
+#define USBHSD_INTSTAT_EP5OUT_MASK (0x400U)\r
+#define USBHSD_INTSTAT_EP5OUT_SHIFT (10U)\r
+/*! EP5OUT - Interrupt status register bit for the EP5 OUT direction.\r
+ */\r
+#define USBHSD_INTSTAT_EP5OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK)\r
+#define USBHSD_INTSTAT_EP5IN_MASK (0x800U)\r
+#define USBHSD_INTSTAT_EP5IN_SHIFT (11U)\r
+/*! EP5IN - Interrupt status register bit for the EP5 IN direction.\r
+ */\r
+#define USBHSD_INTSTAT_EP5IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK)\r
+#define USBHSD_INTSTAT_FRAME_INT_MASK (0x40000000U)\r
+#define USBHSD_INTSTAT_FRAME_INT_SHIFT (30U)\r
+/*! FRAME_INT - Frame interrupt.\r
+ */\r
+#define USBHSD_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK)\r
+#define USBHSD_INTSTAT_DEV_INT_MASK (0x80000000U)\r
+#define USBHSD_INTSTAT_DEV_INT_SHIFT (31U)\r
+/*! DEV_INT - Device status interrupt.\r
+ */\r
+#define USBHSD_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTEN - USB interrupt enable register */\r
+/*! @{ */\r
+#define USBHSD_INTEN_EP_INT_EN_MASK (0xFFFU)\r
+#define USBHSD_INTEN_EP_INT_EN_SHIFT (0U)\r
+/*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW\r
+ * interrupt is generated on the interrupt line.\r
+ */\r
+#define USBHSD_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK)\r
+#define USBHSD_INTEN_FRAME_INT_EN_MASK (0x40000000U)\r
+#define USBHSD_INTEN_FRAME_INT_EN_SHIFT (30U)\r
+/*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW\r
+ * interrupt is generated on the interrupt line.\r
+ */\r
+#define USBHSD_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK)\r
+#define USBHSD_INTEN_DEV_INT_EN_MASK (0x80000000U)\r
+#define USBHSD_INTEN_DEV_INT_EN_SHIFT (31U)\r
+/*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW\r
+ * interrupt is generated on the interrupt line.\r
+ */\r
+#define USBHSD_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTSETSTAT - USB set interrupt status register */\r
+/*! @{ */\r
+#define USBHSD_INTSETSTAT_EP_SET_INT_MASK (0xFFFU)\r
+#define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT (0U)\r
+/*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.\r
+ */\r
+#define USBHSD_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK)\r
+#define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U)\r
+#define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT (30U)\r
+/*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.\r
+ */\r
+#define USBHSD_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK)\r
+#define USBHSD_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U)\r
+#define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT (31U)\r
+/*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.\r
+ */\r
+#define USBHSD_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK)\r
+/*! @} */\r
+\r
+/*! @name EPTOGGLE - USB Endpoint toggle register */\r
+/*! @{ */\r
+#define USBHSD_EPTOGGLE_TOGGLE_MASK (0x3FFFFFFFU)\r
+#define USBHSD_EPTOGGLE_TOGGLE_SHIFT (0U)\r
+/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint.\r
+ */\r
+#define USBHSD_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group USBHSD_Register_Masks */\r
+\r
+\r
+/* USBHSD - Peripheral instance base addresses */\r
+/** Peripheral USBHSD base address */\r
+#define USBHSD_BASE (0x40094000u)\r
+/** Peripheral USBHSD base pointer */\r
+#define USBHSD ((USBHSD_Type *)USBHSD_BASE)\r
+/** Array initializer of USBHSD peripheral base addresses */\r
+#define USBHSD_BASE_ADDRS { USBHSD_BASE }\r
+/** Array initializer of USBHSD peripheral base pointers */\r
+#define USBHSD_BASE_PTRS { USBHSD }\r
+/** Interrupt vectors for the USBHSD peripheral type */\r
+#define USBHSD_IRQS { USB1_IRQn }\r
+#define USBHSD_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group USBHSD_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- USBHSH Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup USBHSH_Peripheral_Access_Layer USBHSH Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** USBHSH - Register Layout Typedef */\r
+typedef struct {\r
+ __I uint32_t CAPLENGTH_CHIPID; /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */\r
+ __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x4 */\r
+ __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x8 */\r
+ __IO uint32_t FLADJ_FRINDEX; /**< Frame Length Adjustment, offset: 0xC */\r
+ __IO uint32_t ATL_PTD_BASE_ADDR; /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */\r
+ __IO uint32_t ISO_PTD_BASE_ADDR; /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */\r
+ __IO uint32_t INT_PTD_BASE_ADDR; /**< Memory base address where INT PTD0 is stored, offset: 0x18 */\r
+ __IO uint32_t DATA_PAYLOAD_BASE_ADDR; /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */\r
+ __IO uint32_t USBCMD; /**< USB Command register, offset: 0x20 */\r
+ __IO uint32_t USBSTS; /**< USB Interrupt Status register, offset: 0x24 */\r
+ __IO uint32_t USBINTR; /**< USB Interrupt Enable register, offset: 0x28 */\r
+ __IO uint32_t PORTSC1; /**< Port Status and Control register, offset: 0x2C */\r
+ __IO uint32_t ATL_PTD_DONE_MAP; /**< Done map for each ATL PTD, offset: 0x30 */\r
+ __IO uint32_t ATL_PTD_SKIP_MAP; /**< Skip map for each ATL PTD, offset: 0x34 */\r
+ __IO uint32_t ISO_PTD_DONE_MAP; /**< Done map for each ISO PTD, offset: 0x38 */\r
+ __IO uint32_t ISO_PTD_SKIP_MAP; /**< Skip map for each ISO PTD, offset: 0x3C */\r
+ __IO uint32_t INT_PTD_DONE_MAP; /**< Done map for each INT PTD, offset: 0x40 */\r
+ __IO uint32_t INT_PTD_SKIP_MAP; /**< Skip map for each INT PTD, offset: 0x44 */\r
+ __IO uint32_t LASTPTD; /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */\r
+ uint8_t RESERVED_0[4];\r
+ __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */\r
+} USBHSH_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- USBHSH Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup USBHSH_Register_Masks USBHSH Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */\r
+/*! @{ */\r
+#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK (0xFFU)\r
+#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT (0U)\r
+/*! CAPLENGTH - Capability Length: This is used as an offset.\r
+ */\r
+#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK)\r
+#define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK (0xFFFF0000U)\r
+#define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT (16U)\r
+/*! CHIPID - Chip identification: indicates major and minor revision of the IP: [31:24] = Major\r
+ * revision [23:16] = Minor revision Major revisions used: 0x01: USB2.\r
+ */\r
+#define USBHSH_CAPLENGTH_CHIPID_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCSPARAMS - Host Controller Structural Parameters */\r
+/*! @{ */\r
+#define USBHSH_HCSPARAMS_N_PORTS_MASK (0xFU)\r
+#define USBHSH_HCSPARAMS_N_PORTS_SHIFT (0U)\r
+/*! N_PORTS - This register specifies the number of physical downstream ports implemented on this host controller.\r
+ */\r
+#define USBHSH_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK)\r
+#define USBHSH_HCSPARAMS_PPC_MASK (0x10U)\r
+#define USBHSH_HCSPARAMS_PPC_SHIFT (4U)\r
+/*! PPC - This field indicates whether the host controller implementation includes port power control.\r
+ */\r
+#define USBHSH_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK)\r
+#define USBHSH_HCSPARAMS_P_INDICATOR_MASK (0x10000U)\r
+#define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT (16U)\r
+/*! P_INDICATOR - This bit indicates whether the ports support port indicator control.\r
+ */\r
+#define USBHSH_HCSPARAMS_P_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCCPARAMS - Host Controller Capability Parameters */\r
+/*! @{ */\r
+#define USBHSH_HCCPARAMS_LPMC_MASK (0x20000U)\r
+#define USBHSH_HCCPARAMS_LPMC_SHIFT (17U)\r
+/*! LPMC - Link Power Management Capability.\r
+ */\r
+#define USBHSH_HCCPARAMS_LPMC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCCPARAMS_LPMC_SHIFT)) & USBHSH_HCCPARAMS_LPMC_MASK)\r
+/*! @} */\r
+\r
+/*! @name FLADJ_FRINDEX - Frame Length Adjustment */\r
+/*! @{ */\r
+#define USBHSH_FLADJ_FRINDEX_FLADJ_MASK (0x3FU)\r
+#define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT (0U)\r
+/*! FLADJ - Frame Length Timing Value.\r
+ */\r
+#define USBHSH_FLADJ_FRINDEX_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK)\r
+#define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK (0x3FFF0000U)\r
+#define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT (16U)\r
+/*! FRINDEX - Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet.\r
+ */\r
+#define USBHSH_FLADJ_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK)\r
+/*! @} */\r
+\r
+/*! @name ATL_PTD_BASE_ADDR - Memory base address where ATL PTD0 is stored */\r
+/*! @{ */\r
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK (0x1F0U)\r
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT (4U)\r
+/*! ATL_CUR - This indicates the current PTD that is used by the hardware when it is processing the ATL list.\r
+ */\r
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK)\r
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK (0xFFFFFE00U)\r
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT (9U)\r
+/*! ATL_BASE - Base address to be used by the hardware to find the start of the ATL list.\r
+ */\r
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK)\r
+/*! @} */\r
+\r
+/*! @name ISO_PTD_BASE_ADDR - Memory base address where ISO PTD0 is stored */\r
+/*! @{ */\r
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK (0x3E0U)\r
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT (5U)\r
+/*! ISO_FIRST - This indicates the first PTD that is used by the hardware when it is processing the ISO list.\r
+ */\r
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK)\r
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK (0xFFFFFC00U)\r
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT (10U)\r
+/*! ISO_BASE - Base address to be used by the hardware to find the start of the ISO list.\r
+ */\r
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK)\r
+/*! @} */\r
+\r
+/*! @name INT_PTD_BASE_ADDR - Memory base address where INT PTD0 is stored */\r
+/*! @{ */\r
+#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK (0x3E0U)\r
+#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT (5U)\r
+/*! INT_FIRST - This indicates the first PTD that is used by the hardware when it is processing the INT list.\r
+ */\r
+#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK)\r
+#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK (0xFFFFFC00U)\r
+#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT (10U)\r
+/*! INT_BASE - Base address to be used by the hardware to find the start of the INT list.\r
+ */\r
+#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK)\r
+/*! @} */\r
+\r
+/*! @name DATA_PAYLOAD_BASE_ADDR - Memory base address that indicates the start of the data payload buffers */\r
+/*! @{ */\r
+#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK (0xFFFF0000U)\r
+#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT (16U)\r
+/*! DAT_BASE - Base address to be used by the hardware to find the start of the data payload section.\r
+ */\r
+#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT)) & USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK)\r
+/*! @} */\r
+\r
+/*! @name USBCMD - USB Command register */\r
+/*! @{ */\r
+#define USBHSH_USBCMD_RS_MASK (0x1U)\r
+#define USBHSH_USBCMD_RS_SHIFT (0U)\r
+/*! RS - Run/Stop: 1b = Run.\r
+ */\r
+#define USBHSH_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK)\r
+#define USBHSH_USBCMD_HCRESET_MASK (0x2U)\r
+#define USBHSH_USBCMD_HCRESET_SHIFT (1U)\r
+/*! HCRESET - Host Controller Reset: This control bit is used by the software to reset the host controller.\r
+ */\r
+#define USBHSH_USBCMD_HCRESET(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK)\r
+#define USBHSH_USBCMD_FLS_MASK (0xCU)\r
+#define USBHSH_USBCMD_FLS_SHIFT (2U)\r
+/*! FLS - Frame List Size: This field specifies the size of the frame list.\r
+ */\r
+#define USBHSH_USBCMD_FLS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK)\r
+#define USBHSH_USBCMD_LHCR_MASK (0x80U)\r
+#define USBHSH_USBCMD_LHCR_SHIFT (7U)\r
+/*! LHCR - Light Host Controller Reset: This bit allows the driver software to reset the host\r
+ * controller without affecting the state of the ports.\r
+ */\r
+#define USBHSH_USBCMD_LHCR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK)\r
+#define USBHSH_USBCMD_ATL_EN_MASK (0x100U)\r
+#define USBHSH_USBCMD_ATL_EN_SHIFT (8U)\r
+/*! ATL_EN - ATL List enabled.\r
+ */\r
+#define USBHSH_USBCMD_ATL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK)\r
+#define USBHSH_USBCMD_ISO_EN_MASK (0x200U)\r
+#define USBHSH_USBCMD_ISO_EN_SHIFT (9U)\r
+/*! ISO_EN - ISO List enabled.\r
+ */\r
+#define USBHSH_USBCMD_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK)\r
+#define USBHSH_USBCMD_INT_EN_MASK (0x400U)\r
+#define USBHSH_USBCMD_INT_EN_SHIFT (10U)\r
+/*! INT_EN - INT List enabled.\r
+ */\r
+#define USBHSH_USBCMD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK)\r
+#define USBHSH_USBCMD_HIRD_MASK (0xF000000U)\r
+#define USBHSH_USBCMD_HIRD_SHIFT (24U)\r
+/*! HIRD - Host-Initiated Resume Duration.\r
+ */\r
+#define USBHSH_USBCMD_HIRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HIRD_SHIFT)) & USBHSH_USBCMD_HIRD_MASK)\r
+/*! @} */\r
+\r
+/*! @name USBSTS - USB Interrupt Status register */\r
+/*! @{ */\r
+#define USBHSH_USBSTS_PCD_MASK (0x4U)\r
+#define USBHSH_USBSTS_PCD_SHIFT (2U)\r
+/*! PCD - Port Change Detect: The host controller sets this bit to logic 1 when any port has a\r
+ * change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a\r
+ * result of a J-K transition detected on a suspended port.\r
+ */\r
+#define USBHSH_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK)\r
+#define USBHSH_USBSTS_FLR_MASK (0x8U)\r
+#define USBHSH_USBSTS_FLR_SHIFT (3U)\r
+/*! FLR - Frame List Rollover: The host controller sets this bit to logic 1 when the frame list\r
+ * index rolls over its maximum value to 0.\r
+ */\r
+#define USBHSH_USBSTS_FLR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK)\r
+#define USBHSH_USBSTS_ATL_IRQ_MASK (0x10000U)\r
+#define USBHSH_USBSTS_ATL_IRQ_SHIFT (16U)\r
+/*! ATL_IRQ - ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed.\r
+ */\r
+#define USBHSH_USBSTS_ATL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK)\r
+#define USBHSH_USBSTS_ISO_IRQ_MASK (0x20000U)\r
+#define USBHSH_USBSTS_ISO_IRQ_SHIFT (17U)\r
+/*! ISO_IRQ - ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed.\r
+ */\r
+#define USBHSH_USBSTS_ISO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK)\r
+#define USBHSH_USBSTS_INT_IRQ_MASK (0x40000U)\r
+#define USBHSH_USBSTS_INT_IRQ_SHIFT (18U)\r
+/*! INT_IRQ - INT IRQ: Indicates that an INT PTD (with I-bit set) was completed.\r
+ */\r
+#define USBHSH_USBSTS_INT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK)\r
+#define USBHSH_USBSTS_SOF_IRQ_MASK (0x80000U)\r
+#define USBHSH_USBSTS_SOF_IRQ_SHIFT (19U)\r
+/*! SOF_IRQ - SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus, this bit is set.\r
+ */\r
+#define USBHSH_USBSTS_SOF_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK)\r
+/*! @} */\r
+\r
+/*! @name USBINTR - USB Interrupt Enable register */\r
+/*! @{ */\r
+#define USBHSH_USBINTR_PCDE_MASK (0x4U)\r
+#define USBHSH_USBINTR_PCDE_SHIFT (2U)\r
+/*! PCDE - Port Change Detect Interrupt Enable: 1: enable 0: disable.\r
+ */\r
+#define USBHSH_USBINTR_PCDE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK)\r
+#define USBHSH_USBINTR_FLRE_MASK (0x8U)\r
+#define USBHSH_USBINTR_FLRE_SHIFT (3U)\r
+/*! FLRE - Frame List Rollover Interrupt Enable: 1: enable 0: disable.\r
+ */\r
+#define USBHSH_USBINTR_FLRE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK)\r
+#define USBHSH_USBINTR_ATL_IRQ_E_MASK (0x10000U)\r
+#define USBHSH_USBINTR_ATL_IRQ_E_SHIFT (16U)\r
+/*! ATL_IRQ_E - ATL IRQ Enable bit: 1: enable 0: disable.\r
+ */\r
+#define USBHSH_USBINTR_ATL_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK)\r
+#define USBHSH_USBINTR_ISO_IRQ_E_MASK (0x20000U)\r
+#define USBHSH_USBINTR_ISO_IRQ_E_SHIFT (17U)\r
+/*! ISO_IRQ_E - ISO IRQ Enable bit: 1: enable 0: disable.\r
+ */\r
+#define USBHSH_USBINTR_ISO_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK)\r
+#define USBHSH_USBINTR_INT_IRQ_E_MASK (0x40000U)\r
+#define USBHSH_USBINTR_INT_IRQ_E_SHIFT (18U)\r
+/*! INT_IRQ_E - INT IRQ Enable bit: 1: enable 0: disable.\r
+ */\r
+#define USBHSH_USBINTR_INT_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK)\r
+#define USBHSH_USBINTR_SOF_E_MASK (0x80000U)\r
+#define USBHSH_USBINTR_SOF_E_SHIFT (19U)\r
+/*! SOF_E - SOF Interrupt Enable bit: 1: enable 0: disable.\r
+ */\r
+#define USBHSH_USBINTR_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK)\r
+/*! @} */\r
+\r
+/*! @name PORTSC1 - Port Status and Control register */\r
+/*! @{ */\r
+#define USBHSH_PORTSC1_CCS_MASK (0x1U)\r
+#define USBHSH_PORTSC1_CCS_SHIFT (0U)\r
+/*! CCS - Current Connect Status: Logic 1 indicates a device is present on the port.\r
+ */\r
+#define USBHSH_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK)\r
+#define USBHSH_PORTSC1_CSC_MASK (0x2U)\r
+#define USBHSH_PORTSC1_CSC_SHIFT (1U)\r
+/*! CSC - Connect Status Change: Logic 1 means that the value of CCS has changed.\r
+ */\r
+#define USBHSH_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK)\r
+#define USBHSH_PORTSC1_PED_MASK (0x4U)\r
+#define USBHSH_PORTSC1_PED_SHIFT (2U)\r
+/*! PED - Port Enabled/Disabled.\r
+ */\r
+#define USBHSH_PORTSC1_PED(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK)\r
+#define USBHSH_PORTSC1_PEDC_MASK (0x8U)\r
+#define USBHSH_PORTSC1_PEDC_SHIFT (3U)\r
+/*! PEDC - Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed.\r
+ */\r
+#define USBHSH_PORTSC1_PEDC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK)\r
+#define USBHSH_PORTSC1_OCA_MASK (0x10U)\r
+#define USBHSH_PORTSC1_OCA_SHIFT (4U)\r
+/*! OCA - Over-current active: Logic 1 means that this port has an over-current condition.\r
+ */\r
+#define USBHSH_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK)\r
+#define USBHSH_PORTSC1_OCC_MASK (0x20U)\r
+#define USBHSH_PORTSC1_OCC_SHIFT (5U)\r
+/*! OCC - Over-current change: Logic 1 means that the value of OCA has changed.\r
+ */\r
+#define USBHSH_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK)\r
+#define USBHSH_PORTSC1_FPR_MASK (0x40U)\r
+#define USBHSH_PORTSC1_FPR_SHIFT (6U)\r
+/*! FPR - Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port.\r
+ */\r
+#define USBHSH_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK)\r
+#define USBHSH_PORTSC1_SUSP_MASK (0x80U)\r
+#define USBHSH_PORTSC1_SUSP_SHIFT (7U)\r
+/*! SUSP - Suspend: Logic 1 means port is in the suspend state.\r
+ */\r
+#define USBHSH_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK)\r
+#define USBHSH_PORTSC1_PR_MASK (0x100U)\r
+#define USBHSH_PORTSC1_PR_SHIFT (8U)\r
+/*! PR - Port Reset: Logic 1 means the port is in the reset state.\r
+ */\r
+#define USBHSH_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK)\r
+#define USBHSH_PORTSC1_SUS_L1_MASK (0x200U)\r
+#define USBHSH_PORTSC1_SUS_L1_SHIFT (9U)\r
+/*! SUS_L1 - Suspend using L1 0b = Suspend using L2 1b = Suspend using L1 When this bit is set to a\r
+ * 1 and a non-zero value is specified in the Device Address field, the host controller will\r
+ * generate an LPM Token to enter the L1 state whenever software writes a one to the Suspend bit, as\r
+ * well as L1 exit timing during any device or host-initiated resume.\r
+ */\r
+#define USBHSH_PORTSC1_SUS_L1(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_L1_SHIFT)) & USBHSH_PORTSC1_SUS_L1_MASK)\r
+#define USBHSH_PORTSC1_LS_MASK (0xC00U)\r
+#define USBHSH_PORTSC1_LS_SHIFT (10U)\r
+/*! LS - Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines.\r
+ */\r
+#define USBHSH_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK)\r
+#define USBHSH_PORTSC1_PP_MASK (0x1000U)\r
+#define USBHSH_PORTSC1_PP_SHIFT (12U)\r
+/*! PP - Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register.\r
+ */\r
+#define USBHSH_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK)\r
+#define USBHSH_PORTSC1_PIC_MASK (0xC000U)\r
+#define USBHSH_PORTSC1_PIC_SHIFT (14U)\r
+/*! PIC - Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the\r
+ * HCSPARAMS register is logic 0.\r
+ */\r
+#define USBHSH_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK)\r
+#define USBHSH_PORTSC1_PTC_MASK (0xF0000U)\r
+#define USBHSH_PORTSC1_PTC_SHIFT (16U)\r
+/*! PTC - Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value.\r
+ */\r
+#define USBHSH_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK)\r
+#define USBHSH_PORTSC1_PSPD_MASK (0x300000U)\r
+#define USBHSH_PORTSC1_PSPD_SHIFT (20U)\r
+/*! PSPD - Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved.\r
+ */\r
+#define USBHSH_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK)\r
+#define USBHSH_PORTSC1_WOO_MASK (0x400000U)\r
+#define USBHSH_PORTSC1_WOO_SHIFT (22U)\r
+/*! WOO - Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to\r
+ * overcurrent conditions as wake-up events.\r
+ */\r
+#define USBHSH_PORTSC1_WOO(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK)\r
+#define USBHSH_PORTSC1_SUS_STAT_MASK (0x1800000U)\r
+#define USBHSH_PORTSC1_SUS_STAT_SHIFT (23U)\r
+/*! SUS_STAT - These two bits are used by software to determine whether the most recent L1 suspend\r
+ * request was successful: 00b: Success-state transition was successful (ACK) 01b: Not Yet -\r
+ * Device was unable to enter the L1 state at this time (NYET) 10b: Not supported - Device does not\r
+ * support the L1 state (STALL) 11b: Timeout/Error - Device failed to respond or an error occurred.\r
+ */\r
+#define USBHSH_PORTSC1_SUS_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_STAT_SHIFT)) & USBHSH_PORTSC1_SUS_STAT_MASK)\r
+#define USBHSH_PORTSC1_DEV_ADD_MASK (0xFE000000U)\r
+#define USBHSH_PORTSC1_DEV_ADD_SHIFT (25U)\r
+/*! DEV_ADD - Device Address for LPM tokens.\r
+ */\r
+#define USBHSH_PORTSC1_DEV_ADD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_DEV_ADD_SHIFT)) & USBHSH_PORTSC1_DEV_ADD_MASK)\r
+/*! @} */\r
+\r
+/*! @name ATL_PTD_DONE_MAP - Done map for each ATL PTD */\r
+/*! @{ */\r
+#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK (0xFFFFFFFFU)\r
+#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT (0U)\r
+/*! ATL_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.\r
+ */\r
+#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT)) & USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK)\r
+/*! @} */\r
+\r
+/*! @name ATL_PTD_SKIP_MAP - Skip map for each ATL PTD */\r
+/*! @{ */\r
+#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK (0xFFFFFFFFU)\r
+#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT (0U)\r
+/*! ATL_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be\r
+ * skipped, independent of the V bit setting.\r
+ */\r
+#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT)) & USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK)\r
+/*! @} */\r
+\r
+/*! @name ISO_PTD_DONE_MAP - Done map for each ISO PTD */\r
+/*! @{ */\r
+#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK (0xFFFFFFFFU)\r
+#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT (0U)\r
+/*! ISO_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.\r
+ */\r
+#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT)) & USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK)\r
+/*! @} */\r
+\r
+/*! @name ISO_PTD_SKIP_MAP - Skip map for each ISO PTD */\r
+/*! @{ */\r
+#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK (0xFFFFFFFFU)\r
+#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT (0U)\r
+/*! ISO_SKIP - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.\r
+ */\r
+#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT)) & USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK)\r
+/*! @} */\r
+\r
+/*! @name INT_PTD_DONE_MAP - Done map for each INT PTD */\r
+/*! @{ */\r
+#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK (0xFFFFFFFFU)\r
+#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT (0U)\r
+/*! INT_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.\r
+ */\r
+#define USBHSH_INT_PTD_DONE_MAP_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT)) & USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK)\r
+/*! @} */\r
+\r
+/*! @name INT_PTD_SKIP_MAP - Skip map for each INT PTD */\r
+/*! @{ */\r
+#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK (0xFFFFFFFFU)\r
+#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT (0U)\r
+/*! INT_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be\r
+ * skipped, independent of the V bit setting.\r
+ */\r
+#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT)) & USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK)\r
+/*! @} */\r
+\r
+/*! @name LASTPTD - Marks the last PTD in the list for ISO, INT and ATL */\r
+/*! @{ */\r
+#define USBHSH_LASTPTD_ATL_LAST_MASK (0x1FU)\r
+#define USBHSH_LASTPTD_ATL_LAST_SHIFT (0U)\r
+/*! ATL_LAST - If hardware has reached this PTD and the J bit is not set, it will go to PTD0 as the next PTD to be processed.\r
+ */\r
+#define USBHSH_LASTPTD_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ATL_LAST_SHIFT)) & USBHSH_LASTPTD_ATL_LAST_MASK)\r
+#define USBHSH_LASTPTD_ISO_LAST_MASK (0x1F00U)\r
+#define USBHSH_LASTPTD_ISO_LAST_SHIFT (8U)\r
+/*! ISO_LAST - This indicates the last PTD in the ISO list.\r
+ */\r
+#define USBHSH_LASTPTD_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ISO_LAST_SHIFT)) & USBHSH_LASTPTD_ISO_LAST_MASK)\r
+#define USBHSH_LASTPTD_INT_LAST_MASK (0x1F0000U)\r
+#define USBHSH_LASTPTD_INT_LAST_SHIFT (16U)\r
+/*! INT_LAST - This indicates the last PTD in the INT list.\r
+ */\r
+#define USBHSH_LASTPTD_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_INT_LAST_SHIFT)) & USBHSH_LASTPTD_INT_LAST_MASK)\r
+/*! @} */\r
+\r
+/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */\r
+/*! @{ */\r
+#define USBHSH_PORTMODE_ID0_MASK (0x1U)\r
+#define USBHSH_PORTMODE_ID0_SHIFT (0U)\r
+/*! ID0 - Port 0 ID pin value.\r
+ */\r
+#define USBHSH_PORTMODE_ID0(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_SHIFT)) & USBHSH_PORTMODE_ID0_MASK)\r
+#define USBHSH_PORTMODE_ID0_EN_MASK (0x100U)\r
+#define USBHSH_PORTMODE_ID0_EN_SHIFT (8U)\r
+/*! ID0_EN - Port 0 ID pin pull-up enable.\r
+ */\r
+#define USBHSH_PORTMODE_ID0_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_EN_SHIFT)) & USBHSH_PORTMODE_ID0_EN_MASK)\r
+#define USBHSH_PORTMODE_DEV_ENABLE_MASK (0x10000U)\r
+#define USBHSH_PORTMODE_DEV_ENABLE_SHIFT (16U)\r
+/*! DEV_ENABLE - If this bit is set to one, one of the ports will behave as a USB device.\r
+ */\r
+#define USBHSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK)\r
+#define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK (0x40000U)\r
+#define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT (18U)\r
+/*! SW_CTRL_PDCOM - This bit indicates if the PHY power-down input is controlled by software or by hardware.\r
+ */\r
+#define USBHSH_PORTMODE_SW_CTRL_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK)\r
+#define USBHSH_PORTMODE_SW_PDCOM_MASK (0x80000U)\r
+#define USBHSH_PORTMODE_SW_PDCOM_SHIFT (19U)\r
+/*! SW_PDCOM - This bit is only used when SW_CTRL_PDCOM is set to 1b.\r
+ */\r
+#define USBHSH_PORTMODE_SW_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group USBHSH_Register_Masks */\r
+\r
+\r
+/* USBHSH - Peripheral instance base addresses */\r
+/** Peripheral USBHSH base address */\r
+#define USBHSH_BASE (0x400A3000u)\r
+/** Peripheral USBHSH base pointer */\r
+#define USBHSH ((USBHSH_Type *)USBHSH_BASE)\r
+/** Array initializer of USBHSH peripheral base addresses */\r
+#define USBHSH_BASE_ADDRS { USBHSH_BASE }\r
+/** Array initializer of USBHSH peripheral base pointers */\r
+#define USBHSH_BASE_PTRS { USBHSH }\r
+/** Interrupt vectors for the USBHSH peripheral type */\r
+#define USBHSH_IRQS { USB1_IRQn }\r
+#define USBHSH_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group USBHSH_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- UTICK Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** UTICK - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t CTRL; /**< Control register., offset: 0x0 */\r
+ __IO uint32_t STAT; /**< Status register., offset: 0x4 */\r
+ __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */\r
+ __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */\r
+ __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */\r
+} UTICK_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- UTICK Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup UTICK_Register_Masks UTICK Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CTRL - Control register. */\r
+/*! @{ */\r
+#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU)\r
+#define UTICK_CTRL_DELAYVAL_SHIFT (0U)\r
+/*! DELAYVAL - Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer\r
+ * clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer.\r
+ */\r
+#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK)\r
+#define UTICK_CTRL_REPEAT_MASK (0x80000000U)\r
+#define UTICK_CTRL_REPEAT_SHIFT (31U)\r
+/*! REPEAT - Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously.\r
+ */\r
+#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK)\r
+/*! @} */\r
+\r
+/*! @name STAT - Status register. */\r
+/*! @{ */\r
+#define UTICK_STAT_INTR_MASK (0x1U)\r
+#define UTICK_STAT_INTR_SHIFT (0U)\r
+/*! INTR - Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any\r
+ * value to this register clears this flag.\r
+ */\r
+#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK)\r
+#define UTICK_STAT_ACTIVE_MASK (0x2U)\r
+#define UTICK_STAT_ACTIVE_SHIFT (1U)\r
+/*! ACTIVE - Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active.\r
+ */\r
+#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK)\r
+/*! @} */\r
+\r
+/*! @name CFG - Capture configuration register. */\r
+/*! @{ */\r
+#define UTICK_CFG_CAPEN0_MASK (0x1U)\r
+#define UTICK_CFG_CAPEN0_SHIFT (0U)\r
+/*! CAPEN0 - Enable Capture 0. 1 = Enabled, 0 = Disabled.\r
+ */\r
+#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK)\r
+#define UTICK_CFG_CAPEN1_MASK (0x2U)\r
+#define UTICK_CFG_CAPEN1_SHIFT (1U)\r
+/*! CAPEN1 - Enable Capture 1. 1 = Enabled, 0 = Disabled.\r
+ */\r
+#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK)\r
+#define UTICK_CFG_CAPEN2_MASK (0x4U)\r
+#define UTICK_CFG_CAPEN2_SHIFT (2U)\r
+/*! CAPEN2 - Enable Capture 2. 1 = Enabled, 0 = Disabled.\r
+ */\r
+#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK)\r
+#define UTICK_CFG_CAPEN3_MASK (0x8U)\r
+#define UTICK_CFG_CAPEN3_SHIFT (3U)\r
+/*! CAPEN3 - Enable Capture 3. 1 = Enabled, 0 = Disabled.\r
+ */\r
+#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK)\r
+#define UTICK_CFG_CAPPOL0_MASK (0x100U)\r
+#define UTICK_CFG_CAPPOL0_SHIFT (8U)\r
+/*! CAPPOL0 - Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture.\r
+ */\r
+#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK)\r
+#define UTICK_CFG_CAPPOL1_MASK (0x200U)\r
+#define UTICK_CFG_CAPPOL1_SHIFT (9U)\r
+/*! CAPPOL1 - Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture.\r
+ */\r
+#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK)\r
+#define UTICK_CFG_CAPPOL2_MASK (0x400U)\r
+#define UTICK_CFG_CAPPOL2_SHIFT (10U)\r
+/*! CAPPOL2 - Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture.\r
+ */\r
+#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK)\r
+#define UTICK_CFG_CAPPOL3_MASK (0x800U)\r
+#define UTICK_CFG_CAPPOL3_SHIFT (11U)\r
+/*! CAPPOL3 - Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture.\r
+ */\r
+#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK)\r
+/*! @} */\r
+\r
+/*! @name CAPCLR - Capture clear register. */\r
+/*! @{ */\r
+#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U)\r
+#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U)\r
+/*! CAPCLR0 - Clear capture 0. Writing 1 to this bit clears the CAP0 register value.\r
+ */\r
+#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK)\r
+#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U)\r
+#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U)\r
+/*! CAPCLR1 - Clear capture 1. Writing 1 to this bit clears the CAP1 register value.\r
+ */\r
+#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK)\r
+#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U)\r
+#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U)\r
+/*! CAPCLR2 - Clear capture 2. Writing 1 to this bit clears the CAP2 register value.\r
+ */\r
+#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK)\r
+#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U)\r
+#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U)\r
+/*! CAPCLR3 - Clear capture 3. Writing 1 to this bit clears the CAP3 register value.\r
+ */\r
+#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK)\r
+/*! @} */\r
+\r
+/*! @name CAP - Capture register . */\r
+/*! @{ */\r
+#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU)\r
+#define UTICK_CAP_CAP_VALUE_SHIFT (0U)\r
+/*! CAP_VALUE - Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower\r
+ * than the actual value of the Micro-tick Timer at the moment of the capture event.\r
+ */\r
+#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK)\r
+#define UTICK_CAP_VALID_MASK (0x80000000U)\r
+#define UTICK_CAP_VALID_SHIFT (31U)\r
+/*! VALID - Capture Valid. When 1, a value has been captured based on a transition of the related\r
+ * UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register.\r
+ */\r
+#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK)\r
+/*! @} */\r
+\r
+/* The count of UTICK_CAP */\r
+#define UTICK_CAP_COUNT (4U)\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group UTICK_Register_Masks */\r
+\r
+\r
+/* UTICK - Peripheral instance base addresses */\r
+/** Peripheral UTICK0 base address */\r
+#define UTICK0_BASE (0x4000E000u)\r
+/** Peripheral UTICK0 base pointer */\r
+#define UTICK0 ((UTICK_Type *)UTICK0_BASE)\r
+/** Array initializer of UTICK peripheral base addresses */\r
+#define UTICK_BASE_ADDRS { UTICK0_BASE }\r
+/** Array initializer of UTICK peripheral base pointers */\r
+#define UTICK_BASE_PTRS { UTICK0 }\r
+/** Interrupt vectors for the UTICK peripheral type */\r
+#define UTICK_IRQS { UTICK0_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group UTICK_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- WWDT Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** WWDT - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */\r
+ __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */\r
+ __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */\r
+ __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */\r
+ uint8_t RESERVED_0[4];\r
+ __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */\r
+ __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */\r
+} WWDT_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- WWDT Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup WWDT_Register_Masks WWDT Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */\r
+/*! @{ */\r
+#define WWDT_MOD_WDEN_MASK (0x1U)\r
+#define WWDT_MOD_WDEN_SHIFT (0U)\r
+/*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the\r
+ * watchdog timer will run permanently.\r
+ * 0b0..Stop. The watchdog timer is stopped.\r
+ * 0b1..Run. The watchdog timer is running.\r
+ */\r
+#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK)\r
+#define WWDT_MOD_WDRESET_MASK (0x2U)\r
+#define WWDT_MOD_WDRESET_SHIFT (1U)\r
+/*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0.\r
+ * 0b0..Interrupt. A watchdog time-out will not cause a chip reset.\r
+ * 0b1..Reset. A watchdog time-out will cause a chip reset.\r
+ */\r
+#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK)\r
+#define WWDT_MOD_WDTOF_MASK (0x4U)\r
+#define WWDT_MOD_WDTOF_SHIFT (2U)\r
+/*! WDTOF - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by\r
+ * events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a\r
+ * chip reset if WDRESET = 1.\r
+ */\r
+#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK)\r
+#define WWDT_MOD_WDINT_MASK (0x8U)\r
+#define WWDT_MOD_WDINT_SHIFT (3U)\r
+/*! WDINT - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT.\r
+ * Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the\r
+ * WARNINT value is equal to the value of the TV register. This can occur if the value of\r
+ * WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0.\r
+ */\r
+#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK)\r
+#define WWDT_MOD_WDPROTECT_MASK (0x10U)\r
+#define WWDT_MOD_WDPROTECT_SHIFT (4U)\r
+/*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset.\r
+ * 0b0..Flexible. The watchdog time-out value (TC) can be changed at any time.\r
+ * 0b1..Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW.\r
+ */\r
+#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK)\r
+#define WWDT_MOD_LOCK_MASK (0x20U)\r
+#define WWDT_MOD_LOCK_SHIFT (5U)\r
+/*! LOCK - Once this bit is set to one and a watchdog feed is performed, disabling or powering down\r
+ * the watchdog oscillator is prevented by hardware. This bit can be set once by software and is\r
+ * only cleared by any reset.\r
+ */\r
+#define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK)\r
+/*! @} */\r
+\r
+/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */\r
+/*! @{ */\r
+#define WWDT_TC_COUNT_MASK (0xFFFFFFU)\r
+#define WWDT_TC_COUNT_SHIFT (0U)\r
+/*! COUNT - Watchdog time-out value.\r
+ */\r
+#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK)\r
+/*! @} */\r
+\r
+/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */\r
+/*! @{ */\r
+#define WWDT_FEED_FEED_MASK (0xFFU)\r
+#define WWDT_FEED_FEED_SHIFT (0U)\r
+/*! FEED - Feed value should be 0xAA followed by 0x55.\r
+ */\r
+#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK)\r
+/*! @} */\r
+\r
+/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */\r
+/*! @{ */\r
+#define WWDT_TV_COUNT_MASK (0xFFFFFFU)\r
+#define WWDT_TV_COUNT_SHIFT (0U)\r
+/*! COUNT - Counter timer value.\r
+ */\r
+#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK)\r
+/*! @} */\r
+\r
+/*! @name WARNINT - Watchdog Warning Interrupt compare value. */\r
+/*! @{ */\r
+#define WWDT_WARNINT_WARNINT_MASK (0x3FFU)\r
+#define WWDT_WARNINT_WARNINT_SHIFT (0U)\r
+/*! WARNINT - Watchdog warning interrupt compare value.\r
+ */\r
+#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK)\r
+/*! @} */\r
+\r
+/*! @name WINDOW - Watchdog Window compare value. */\r
+/*! @{ */\r
+#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU)\r
+#define WWDT_WINDOW_WINDOW_SHIFT (0U)\r
+/*! WINDOW - Watchdog window value.\r
+ */\r
+#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group WWDT_Register_Masks */\r
+\r
+\r
+/* WWDT - Peripheral instance base addresses */\r
+/** Peripheral WWDT base address */\r
+#define WWDT_BASE (0x4000C000u)\r
+/** Peripheral WWDT base pointer */\r
+#define WWDT ((WWDT_Type *)WWDT_BASE)\r
+/** Array initializer of WWDT peripheral base addresses */\r
+#define WWDT_BASE_ADDRS { WWDT_BASE }\r
+/** Array initializer of WWDT peripheral base pointers */\r
+#define WWDT_BASE_PTRS { WWDT }\r
+/** Interrupt vectors for the WWDT peripheral type */\r
+#define WWDT_IRQS { WDT_BOD_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group WWDT_Peripheral_Access_Layer */\r
+\r
+\r
+/*\r
+** End of section using anonymous unions\r
+*/\r
+\r
+#if defined(__ARMCC_VERSION)\r
+ #if (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang diagnostic pop\r
+ #else\r
+ #pragma pop\r
+ #endif\r
+#elif defined(__GNUC__)\r
+ /* leave anonymous unions enabled */\r
+#elif defined(__IAR_SYSTEMS_ICC__)\r
+ #pragma language=default\r
+#else\r
+ #error Not supported compiler type\r
+#endif\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group Peripheral_access_layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).\r
+ * @{\r
+ */\r
+\r
+#if defined(__ARMCC_VERSION)\r
+ #if (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header\r
+ #endif\r
+#elif defined(__IAR_SYSTEMS_ICC__)\r
+ #pragma system_include\r
+#endif\r
+\r
+/**\r
+ * @brief Mask and left-shift a bit field value for use in a register bit range.\r
+ * @param field Name of the register bit field.\r
+ * @param value Value of the bit field.\r
+ * @return Masked and shifted value.\r
+ */\r
+#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))\r
+/**\r
+ * @brief Mask and right-shift a register value to extract a bit field value.\r
+ * @param field Name of the register bit field.\r
+ * @param value Value of the register.\r
+ * @return Masked and shifted bit field value.\r
+ */\r
+#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group Bit_Field_Generic_Macros */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SDK Compatibility\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup SDK_Compatibility_Symbols SDK Compatibility\r
+ * @{\r
+ */\r
+\r
+/** EMC CS base address */\r
+#define EMC_CS0_BASE (0x80000000u)\r
+#define EMC_CS1_BASE (0x88000000u)\r
+#define EMC_CS2_BASE (0x90000000u)\r
+#define EMC_CS3_BASE (0x98000000u)\r
+#define EMC_DYCS0_BASE (0xA0000000u)\r
+#define EMC_DYCS1_BASE (0xA8000000u)\r
+#define EMC_DYCS2_BASE (0xB0000000u)\r
+#define EMC_DYCS3_BASE (0xB8000000u)\r
+#define EMC_CS_ADDRESS {EMC_CS0_BASE, EMC_CS1_BASE, EMC_CS2_BASE, EMC_CS3_BASE}\r
+#define EMC_DYCS_ADDRESS {EMC_DYCS0_BASE, EMC_DYCS1_BASE, EMC_DYCS2_BASE, EMC_DYCS3_BASE}\r
+\r
+/** OTP API */\r
+typedef struct {\r
+ uint32_t (*otpInit)(void); /** Initializes OTP controller */\r
+ uint32_t (*otpEnableBankWriteMask)(uint32_t bankMask); /** Unlock one or more OTP banks for write access */\r
+ uint32_t (*otpDisableBankWriteMask)(uint32_t bankMask); /** Lock one or more OTP banks for write access */\r
+ uint32_t (*otpEnableBankWriteLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask,\r
+ uint32_t lockWrite); /** Locks or unlocks write access to a register of an OTP bank and the write lock */\r
+ uint32_t (*otpEnableBankReadLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask,\r
+ uint32_t lockWrite); /** Locks or unlocks read access to a register of an OTP bank and the write lock */\r
+ uint32_t (*otpProgramReg)(uint32_t bankIndex, uint32_t regIndex, uint32_t value); /** Program a single register in an OTP bank */\r
+ uint32_t RESERVED_0[5];\r
+ uint32_t (*rngRead)(void); /** Returns 32-bit number from hardware random number generator */\r
+ uint32_t (*otpGetDriverVersion)(void); /** Returns the version of the OTP driver in ROM */\r
+} OTP_API_Type;\r
+\r
+/** ROM API */\r
+typedef struct {\r
+ __I uint32_t usbdApiBase; /** USB API Base */\r
+ uint32_t RESERVED_0[13];\r
+ __I OTP_API_Type *otpApiBase; /** OTP API Base */\r
+ __I uint32_t aesApiBase; /** AES API Base */\r
+ __I uint32_t secureApiBase; /** Secure API Base */\r
+} ROM_API_Type;\r
+\r
+/** ROM API base address */\r
+#define ROM_API_BASE (0x03000200u)\r
+/** ROM API base pointer */\r
+#define ROM_API (*(ROM_API_Type**) ROM_API_BASE)\r
+/** OTP API base pointer */\r
+#define OTP_API (ROM_API->otpApiBase)\r
+\r
+/** Used for selecting the address of FROHF setting API in ROM */\r
+#define FSL_FROHF_SETTING_API_ADDRESS_DETERMINE_BY_ROM_VERSION 1U\r
+#define FSL_ROM_VERSION_0A 0U\r
+#define FSL_ROM_VERSION_1B 1U\r
+#define FSL_ROM_VERSION_0A_FRO_SETTING_ADDR 0x03007933U\r
+#define FSL_ROM_VERSION_1B_FRO_SETTING_ADDR 0x03008D9BU\r
+\r
+/*!\r
+ * @brief Get the chip value.\r
+ *\r
+ * @return chip version, 0x0: 0A version chip, 0x1: 1B version chip, 0xFF: invalid version.\r
+ */\r
+static inline uint32_t Chip_GetVersion(void)\r
+{\r
+ uint8_t romVersion = 0U;\r
+ uint32_t command[5] = {0U}, result[4] = {0U};\r
+ uint32_t syscon_iap_entry_location = 0x03000205;\r
+\r
+ command[0] = 55U;\r
+ result[0] = 0;\r
+ result[1] = 0;\r
+ ((void (*)(uint32_t cmd[5], uint32_t stat[4]))syscon_iap_entry_location)(command, result);\r
+\r
+ romVersion = (uint8_t)(result[1]);\r
+\r
+ if (0U == result[0])\r
+ {\r
+ if (romVersion == FSL_ROM_VERSION_1B)\r
+ {\r
+ return FSL_ROM_VERSION_1B;\r
+ }\r
+ else if (romVersion == FSL_ROM_VERSION_0A)\r
+ {\r
+ return FSL_ROM_VERSION_0A;\r
+ }\r
+ else\r
+ {\r
+ return 0xFF;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ return 0xFF;\r
+ }\r
+}\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group SDK_Compatibility_Symbols */\r
+\r
+\r
+#endif /* _LPC54018_H_ */\r
+\r
--- /dev/null
+/*\r
+** ###################################################################\r
+** Version: rev. 1.2, 2017-06-08\r
+** Build: b191115\r
+**\r
+** Abstract:\r
+** Chip specific module features.\r
+**\r
+** Copyright 2016 Freescale Semiconductor, Inc.\r
+** Copyright 2016-2019 NXP\r
+** All rights reserved.\r
+**\r
+** SPDX-License-Identifier: BSD-3-Clause\r
+**\r
+** http: www.nxp.com\r
+** mail: support@nxp.com\r
+**\r
+** Revisions:\r
+** - rev. 1.0 (2016-08-12)\r
+** Initial version.\r
+** - rev. 1.1 (2016-11-25)\r
+** Update CANFD and Classic CAN register.\r
+** Add MAC TIMERSTAMP registers.\r
+** - rev. 1.2 (2017-06-08)\r
+** Remove RTC_CTRL_RTC_OSC_BYPASS.\r
+** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.\r
+** Remove RESET and HALT from SYSCON_AHBCLKDIV.\r
+**\r
+** ###################################################################\r
+*/\r
+\r
+#ifndef _LPC54018_FEATURES_H_\r
+#define _LPC54018_FEATURES_H_\r
+\r
+/* SOC module features */\r
+\r
+/* @brief ADC availability on the SoC. */\r
+#define FSL_FEATURE_SOC_ADC_COUNT (1)\r
+/* @brief ASYNC_SYSCON availability on the SoC. */\r
+#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1)\r
+/* @brief CAN availability on the SoC. */\r
+#define FSL_FEATURE_SOC_LPC_CAN_COUNT (2)\r
+/* @brief CRC availability on the SoC. */\r
+#define FSL_FEATURE_SOC_CRC_COUNT (1)\r
+/* @brief CTIMER availability on the SoC. */\r
+#define FSL_FEATURE_SOC_CTIMER_COUNT (5)\r
+/* @brief DMA availability on the SoC. */\r
+#define FSL_FEATURE_SOC_DMA_COUNT (1)\r
+/* @brief DMIC availability on the SoC. */\r
+#define FSL_FEATURE_SOC_DMIC_COUNT (1)\r
+/* @brief EMC availability on the SoC. */\r
+#define FSL_FEATURE_SOC_EMC_COUNT (1)\r
+/* @brief ENET availability on the SoC. */\r
+#define FSL_FEATURE_SOC_LPC_ENET_COUNT (1)\r
+/* @brief FLEXCOMM availability on the SoC. */\r
+#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (11)\r
+/* @brief GINT availability on the SoC. */\r
+#define FSL_FEATURE_SOC_GINT_COUNT (2)\r
+/* @brief GPIO availability on the SoC. */\r
+#define FSL_FEATURE_SOC_GPIO_COUNT (1)\r
+/* @brief I2C availability on the SoC. */\r
+#define FSL_FEATURE_SOC_I2C_COUNT (10)\r
+/* @brief I2S availability on the SoC. */\r
+#define FSL_FEATURE_SOC_I2S_COUNT (2)\r
+/* @brief INPUTMUX availability on the SoC. */\r
+#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)\r
+/* @brief IOCON availability on the SoC. */\r
+#define FSL_FEATURE_SOC_IOCON_COUNT (1)\r
+/* @brief LCD availability on the SoC. */\r
+#define FSL_FEATURE_SOC_LCD_COUNT (1)\r
+/* @brief MRT availability on the SoC. */\r
+#define FSL_FEATURE_SOC_MRT_COUNT (1)\r
+/* @brief PINT availability on the SoC. */\r
+#define FSL_FEATURE_SOC_PINT_COUNT (1)\r
+/* @brief RIT availability on the SoC. */\r
+#define FSL_FEATURE_SOC_RIT_COUNT (1)\r
+/* @brief RNG availability on the SoC. */\r
+#define FSL_FEATURE_SOC_LPC_RNG_COUNT (1)\r
+/* @brief RTC availability on the SoC. */\r
+#define FSL_FEATURE_SOC_RTC_COUNT (1)\r
+/* @brief SCT availability on the SoC. */\r
+#define FSL_FEATURE_SOC_SCT_COUNT (1)\r
+/* @brief SDIF availability on the SoC. */\r
+#define FSL_FEATURE_SOC_SDIF_COUNT (1)\r
+/* @brief SHA availability on the SoC. */\r
+#define FSL_FEATURE_SOC_SHA_COUNT (1)\r
+/* @brief SMARTCARD availability on the SoC. */\r
+#define FSL_FEATURE_SOC_SMARTCARD_COUNT (2)\r
+/* @brief SPI availability on the SoC. */\r
+#define FSL_FEATURE_SOC_SPI_COUNT (11)\r
+/* @brief SPIFI availability on the SoC. */\r
+#define FSL_FEATURE_SOC_SPIFI_COUNT (1)\r
+/* @brief SYSCON availability on the SoC. */\r
+#define FSL_FEATURE_SOC_SYSCON_COUNT (1)\r
+/* @brief USART availability on the SoC. */\r
+#define FSL_FEATURE_SOC_USART_COUNT (10)\r
+/* @brief USB availability on the SoC. */\r
+#define FSL_FEATURE_SOC_USB_COUNT (1)\r
+/* @brief USBFSH availability on the SoC. */\r
+#define FSL_FEATURE_SOC_USBFSH_COUNT (1)\r
+/* @brief USBHSD availability on the SoC. */\r
+#define FSL_FEATURE_SOC_USBHSD_COUNT (1)\r
+/* @brief USBHSH availability on the SoC. */\r
+#define FSL_FEATURE_SOC_USBHSH_COUNT (1)\r
+/* @brief UTICK availability on the SoC. */\r
+#define FSL_FEATURE_SOC_UTICK_COUNT (1)\r
+/* @brief WWDT availability on the SoC. */\r
+#define FSL_FEATURE_SOC_WWDT_COUNT (1)\r
+\r
+/* ADC module features */\r
+\r
+/* @brief Do not has input select (register INSEL). */\r
+#define FSL_FEATURE_ADC_HAS_NO_INSEL (0)\r
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */\r
+#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1)\r
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */\r
+#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1)\r
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */\r
+#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (1)\r
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */\r
+#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1)\r
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */\r
+#define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (0)\r
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */\r
+#define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (0)\r
+/* @brief Has startup register. */\r
+#define FSL_FEATURE_ADC_HAS_STARTUP_REG (1)\r
+/* @brief Has ADTrim register */\r
+#define FSL_FEATURE_ADC_HAS_TRIM_REG (0)\r
+/* @brief Has Calibration register. */\r
+#define FSL_FEATURE_ADC_HAS_CALIB_REG (1)\r
+\r
+/* CAN module features */\r
+\r
+/* @brief Support CANFD or not */\r
+#define FSL_FEATURE_CAN_SUPPORT_CANFD (1)\r
+\r
+/* DMA module features */\r
+\r
+/* @brief Number of channels */\r
+#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30)\r
+/* @brief Align size of DMA descriptor */\r
+#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512)\r
+/* @brief DMA head link descriptor table align size */\r
+#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)\r
+\r
+/* FLEXCOMM module features */\r
+\r
+/* @brief FLEXCOMM0 USART INDEX 0 */\r
+#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0)\r
+/* @brief FLEXCOMM0 SPI INDEX 0 */\r
+#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0)\r
+/* @brief FLEXCOMM0 I2C INDEX 0 */\r
+#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0)\r
+/* @brief FLEXCOMM1 USART INDEX 1 */\r
+#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1)\r
+/* @brief FLEXCOMM1 SPI INDEX 1 */\r
+#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1)\r
+/* @brief FLEXCOMM1 I2C INDEX 1 */\r
+#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1)\r
+/* @brief FLEXCOMM2 USART INDEX 2 */\r
+#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2)\r
+/* @brief FLEXCOMM2 SPI INDEX 2 */\r
+#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2)\r
+/* @brief FLEXCOMM2 I2C INDEX 2 */\r
+#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2)\r
+/* @brief FLEXCOMM3 USART INDEX 3 */\r
+#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3)\r
+/* @brief FLEXCOMM3 SPI INDEX 3 */\r
+#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3)\r
+/* @brief FLEXCOMM3 I2C INDEX 3 */\r
+#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3)\r
+/* @brief FLEXCOMM4 USART INDEX 4 */\r
+#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4)\r
+/* @brief FLEXCOMM4 SPI INDEX 4 */\r
+#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4)\r
+/* @brief FLEXCOMM4 I2C INDEX 4 */\r
+#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4)\r
+/* @brief FLEXCOMM5 USART INDEX 5 */\r
+#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5)\r
+/* @brief FLEXCOMM5 SPI INDEX 5 */\r
+#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5)\r
+/* @brief FLEXCOMM5 I2C INDEX 5 */\r
+#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5)\r
+/* @brief FLEXCOMM6 USART INDEX 6 */\r
+#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6)\r
+/* @brief FLEXCOMM6 SPI INDEX 6 */\r
+#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6)\r
+/* @brief FLEXCOMM6 I2C INDEX 6 */\r
+#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6)\r
+/* @brief FLEXCOMM7 I2S INDEX 0 */\r
+#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (0)\r
+/* @brief FLEXCOMM7 USART INDEX 7 */\r
+#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7)\r
+/* @brief FLEXCOMM7 SPI INDEX 7 */\r
+#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7)\r
+/* @brief FLEXCOMM7 I2C INDEX 7 */\r
+#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7)\r
+/* @brief FLEXCOMM7 I2S INDEX 1 */\r
+#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (1)\r
+/* @brief FLEXCOMM4 USART INDEX 8 */\r
+#define FSL_FEATURE_FLEXCOMM8_USART_INDEX (8)\r
+/* @brief FLEXCOMM4 SPI INDEX 8 */\r
+#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8)\r
+/* @brief FLEXCOMM4 I2C INDEX 8 */\r
+#define FSL_FEATURE_FLEXCOMM8_I2C_INDEX (8)\r
+/* @brief FLEXCOMM5 USART INDEX 9 */\r
+#define FSL_FEATURE_FLEXCOMM9_USART_INDEX (9)\r
+/* @brief FLEXCOMM5 SPI INDEX 9 */\r
+#define FSL_FEATURE_FLEXCOMM9_SPI_INDEX (9)\r
+/* @brief FLEXCOMM5 I2C INDEX 9 */\r
+#define FSL_FEATURE_FLEXCOMM9_I2C_INDEX (9)\r
+/* @brief I2S has DMIC interconnection */\r
+#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) \\r
+ (((x) == FLEXCOMM0) ? (0) : \\r
+ (((x) == FLEXCOMM1) ? (0) : \\r
+ (((x) == FLEXCOMM2) ? (0) : \\r
+ (((x) == FLEXCOMM3) ? (0) : \\r
+ (((x) == FLEXCOMM4) ? (0) : \\r
+ (((x) == FLEXCOMM5) ? (0) : \\r
+ (((x) == FLEXCOMM6) ? (0) : \\r
+ (((x) == FLEXCOMM7) ? (1) : \\r
+ (((x) == FLEXCOMM8) ? (0) : \\r
+ (((x) == FLEXCOMM9) ? (0) : \\r
+ (((x) == FLEXCOMM10) ? (0) : (-1))))))))))))\r
+\r
+/* I2S module features */\r
+\r
+/* @brief I2S support dual channel transfer */\r
+#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1)\r
+/* @brief I2S has DMIC interconnection */\r
+#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (1)\r
+\r
+/* IOCON module features */\r
+\r
+/* @brief Func bit field width */\r
+#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4)\r
+\r
+/* MRT module features */\r
+\r
+/* @brief number of channels. */\r
+#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)\r
+\r
+/* interrupt module features */\r
+\r
+/* @brief Lowest interrupt request number. */\r
+#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)\r
+/* @brief Highest interrupt request number. */\r
+#define FSL_FEATURE_INTERRUPT_IRQ_MAX (105)\r
+\r
+/* PINT module features */\r
+\r
+/* @brief Number of connected outputs */\r
+#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)\r
+\r
+/* RIT module features */\r
+\r
+/* @brief RIT has no reset control */\r
+#define FSL_FEATURE_RIT_HAS_NO_RESET (1)\r
+\r
+/* RTC module features */\r
+\r
+/* @brief RTC has no reset control */\r
+#define FSL_FEATURE_RTC_HAS_NO_RESET (1)\r
+\r
+/* SCT module features */\r
+\r
+/* @brief Number of events */\r
+#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16)\r
+/* @brief Number of states */\r
+#define FSL_FEATURE_SCT_NUMBER_OF_STATES (16)\r
+/* @brief Number of match capture */\r
+#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16)\r
+/* @brief Number of outputs */\r
+#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10)\r
+\r
+/* SDIF module features */\r
+\r
+/* @brief FIFO depth, every location is a WORD */\r
+#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64)\r
+/* @brief Max DMA buffer size */\r
+#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096)\r
+/* @brief Max source clock in HZ */\r
+#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000)\r
+\r
+/* SPIFI module features */\r
+\r
+/* @brief SPIFI start address */\r
+#define FSL_FEATURE_SPIFI_START_ADDR (0x10000000)\r
+/* @brief SPIFI end address */\r
+#define FSL_FEATURE_SPIFI_END_ADDR (0x17FFFFFF)\r
+\r
+/* SYSCON module features */\r
+\r
+/* @brief Pointer to ROM IAP entry functions */\r
+#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)\r
+\r
+/* SysTick module features */\r
+\r
+/* @brief Systick has external reference clock. */\r
+#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)\r
+/* @brief Systick external reference clock is core clock divided by this value. */\r
+#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)\r
+\r
+/* USB module features */\r
+\r
+/* @brief Size of the USB dedicated RAM */\r
+#define FSL_FEATURE_USB_USB_RAM (0x00002000)\r
+/* @brief Base address of the USB dedicated RAM */\r
+#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000)\r
+/* @brief USB version */\r
+#define FSL_FEATURE_USB_VERSION (200)\r
+/* @brief Number of the endpoint in USB FS */\r
+#define FSL_FEATURE_USB_EP_NUM (5)\r
+\r
+/* USBFSH module features */\r
+\r
+/* @brief Size of the USB dedicated RAM */\r
+#define FSL_FEATURE_USBFSH_USB_RAM (0x00002000)\r
+/* @brief Base address of the USB dedicated RAM */\r
+#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000)\r
+/* @brief USBFSH version */\r
+#define FSL_FEATURE_USBFSH_VERSION (200)\r
+\r
+/* USBHSD module features */\r
+\r
+/* @brief Size of the USB dedicated RAM */\r
+#define FSL_FEATURE_USBHSD_USB_RAM (0x00002000)\r
+/* @brief Base address of the USB dedicated RAM */\r
+#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000)\r
+/* @brief USBHSD version */\r
+#define FSL_FEATURE_USBHSD_VERSION (300)\r
+/* @brief Number of the endpoint in USB HS */\r
+#define FSL_FEATURE_USBHSD_EP_NUM (6)\r
+/* @brief Resetting interrupt endpoint resets DATAx sequence to DATA.1 */\r
+#define FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK (1)\r
+\r
+/* USBHSH module features */\r
+\r
+/* @brief Size of the USB dedicated RAM */\r
+#define FSL_FEATURE_USBHSH_USB_RAM (0x00002000)\r
+/* @brief Base address of the USB dedicated RAM */\r
+#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000)\r
+/* @brief USBHSH version */\r
+#define FSL_FEATURE_USBHSH_VERSION (300)\r
+\r
+#endif /* _LPC54018_FEATURES_H_ */\r
+\r
--- /dev/null
+/*\r
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2018 NXP\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ *\r
+ */\r
+\r
+#ifndef __FSL_DEVICE_REGISTERS_H__\r
+#define __FSL_DEVICE_REGISTERS_H__\r
+\r
+/*\r
+ * Include the cpu specific register header files.\r
+ *\r
+ * The CPU macro should be declared in the project or makefile.\r
+ */\r
+#if (defined(CPU_LPC54018JBD208) || defined(CPU_LPC54018JET180))\r
+\r
+#define LPC54018_SERIES\r
+\r
+/* CMSIS-style register definitions */\r
+#include "LPC54018.h"\r
+/* CPU specific feature definitions */\r
+#include "LPC54018_features.h"\r
+\r
+#else\r
+ #error "No valid CPU defined!"\r
+#endif\r
+\r
+#endif /* __FSL_DEVICE_REGISTERS_H__ */\r
+\r
+/*******************************************************************************\r
+ * EOF\r
+ ******************************************************************************/\r
--- /dev/null
+/*\r
+** ###################################################################\r
+** Processors: LPC54018JBD208\r
+** LPC54018JET180\r
+**\r
+** Compilers: GNU C Compiler\r
+** IAR ANSI C/C++ Compiler for ARM\r
+** Keil ARM C/C++ Compiler\r
+** MCUXpresso Compiler\r
+**\r
+** Reference manual: LPC540xx/LPC54S0xx User manual Rev.0.8 5 June 2018\r
+** Version: rev. 1.2, 2017-06-08\r
+** Build: b191014\r
+**\r
+** Abstract:\r
+** Provides a system configuration function and a global variable that\r
+** contains the system frequency. It configures the device and initializes\r
+** the oscillator (PLL) that is part of the microcontroller device.\r
+**\r
+** Copyright 2016 Freescale Semiconductor, Inc.\r
+** Copyright 2016-2019 NXP\r
+** All rights reserved.\r
+**\r
+** SPDX-License-Identifier: BSD-3-Clause\r
+**\r
+** http: www.nxp.com\r
+** mail: support@nxp.com\r
+**\r
+** Revisions:\r
+** - rev. 1.0 (2016-08-12)\r
+** Initial version.\r
+** - rev. 1.1 (2016-11-25)\r
+** Update CANFD and Classic CAN register.\r
+** Add MAC TIMERSTAMP registers.\r
+** - rev. 1.2 (2017-06-08)\r
+** Remove RTC_CTRL_RTC_OSC_BYPASS.\r
+** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.\r
+** Remove RESET and HALT from SYSCON_AHBCLKDIV.\r
+**\r
+** ###################################################################\r
+*/\r
+\r
+/*!\r
+ * @file LPC54018\r
+ * @version 1.2\r
+ * @date 2017-06-08\r
+ * @brief Device specific configuration file for LPC54018 (implementation file)\r
+ *\r
+ * Provides a system configuration function and a global variable that contains\r
+ * the system frequency. It configures the device and initializes the oscillator\r
+ * (PLL) that is part of the microcontroller device.\r
+ */\r
+\r
+#include <stdint.h>\r
+#include "fsl_device_registers.h"\r
+\r
+#define NVALMAX (0x100)\r
+#define PVALMAX (0x20)\r
+#define MVALMAX (0x8000)\r
+#define PLL_MDEC_VAL_P (0) /* MDEC is in bits 16:0 */\r
+#define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P)\r
+#define PLL_NDEC_VAL_P (0) /* NDEC is in bits 9:0 */\r
+#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)\r
+#define PLL_PDEC_VAL_P (0) /* PDEC is in bits 6:0 */\r
+#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P)\r
+\r
+extern void *__Vectors;\r
+\r
+static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46,\r
+ 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};\r
+/* Get WATCH DOG Clk */\r
+static uint32_t getWdtOscFreq(void)\r
+{\r
+ uint8_t freq_sel, div_sel;\r
+ if (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)\r
+ {\r
+ return 0U;\r
+ }\r
+ else\r
+ {\r
+ div_sel = (uint8_t)((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1UL) << 1UL;\r
+ freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];\r
+ return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel);\r
+ }\r
+}\r
+/* Find decoded N value for raw NDEC value */\r
+static uint32_t pllDecodeN(uint32_t NDEC)\r
+{\r
+ uint32_t n, x, i;\r
+\r
+ /* Find NDec */\r
+ switch (NDEC)\r
+ {\r
+ case 0x3FF:\r
+ n = 0UL;\r
+ break;\r
+ case 0x302:\r
+ n = 1UL;\r
+ break;\r
+ case 0x202:\r
+ n = 2UL;\r
+ break;\r
+ default:\r
+ x = 0x080UL;\r
+ n = 0xFFFFFFFFUL;\r
+ for (i = NVALMAX; i >= 3UL; i--)\r
+ {\r
+ x = (((x ^ (x >> 2UL) ^ (x >> 3UL) ^ (x >> 4UL)) & 1UL) << 7UL) | ((x >> 1UL) & 0x7FUL);\r
+ if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)\r
+ {\r
+ /* Decoded value of NDEC */\r
+ n = i;\r
+ }\r
+ if (n != 0xFFFFFFFFUL)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ break;\r
+ }\r
+ return n;\r
+}\r
+\r
+/* Find decoded P value for raw PDEC value */\r
+static uint32_t pllDecodeP(uint32_t PDEC)\r
+{\r
+ uint32_t p, x, i;\r
+ /* Find PDec */\r
+ switch (PDEC)\r
+ {\r
+ case 0x7F:\r
+ p = 0UL;\r
+ break;\r
+ case 0x62:\r
+ p = 1UL;\r
+ break;\r
+ case 0x42:\r
+ p = 2UL;\r
+ break;\r
+ default:\r
+ x = 0x10UL;\r
+ p = 0xFFFFFFFFUL;\r
+ for (i = PVALMAX; i >= 3UL; i--)\r
+ {\r
+ x = (((x ^ (x >> 2UL)) & 1UL) << 4UL) | ((x >> 1UL) & 0xFUL);\r
+ if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)\r
+ {\r
+ /* Decoded value of PDEC */\r
+ p = i;\r
+ }\r
+ if (p != 0xFFFFFFFFUL)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ break;\r
+ }\r
+ return p;\r
+}\r
+\r
+/* Find decoded M value for raw MDEC value */\r
+static uint32_t pllDecodeM(uint32_t MDEC)\r
+{\r
+ uint32_t m, i, x;\r
+\r
+ /* Find MDec */\r
+ switch (MDEC)\r
+ {\r
+ case 0x1FFFF:\r
+ m = 0UL;\r
+ break;\r
+ case 0x18003:\r
+ m = 1UL;\r
+ break;\r
+ case 0x10003:\r
+ m = 2UL;\r
+ break;\r
+ default:\r
+ x = 0x04000UL;\r
+ m = 0xFFFFFFFFUL;\r
+ for (i = MVALMAX; i >= 3UL; i--)\r
+ {\r
+ x = (((x ^ (x >> 1UL)) & 1UL) << 14UL) | ((x >> 1UL) & 0x3FFFUL);\r
+ if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC)\r
+ {\r
+ /* Decoded value of MDEC */\r
+ m = i;\r
+ }\r
+ if (m != 0xFFFFFFFFUL)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ break;\r
+ }\r
+ return m;\r
+}\r
+\r
+/* Get predivider (N) from PLL NDEC setting */\r
+static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)\r
+{\r
+ uint32_t preDiv = 1;\r
+\r
+ /* Direct input is not used? */\r
+ if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0UL)\r
+ {\r
+ /* Decode NDEC value to get (N) pre divider */\r
+ preDiv = pllDecodeN(nDecReg & 0x3FFUL);\r
+ if (preDiv == 0UL)\r
+ {\r
+ preDiv = 1;\r
+ }\r
+ }\r
+ /* Adjusted by 1, directi is used to bypass */\r
+ return preDiv;\r
+}\r
+\r
+/* Get postdivider (P) from PLL PDEC setting */\r
+static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)\r
+{\r
+ uint32_t postDiv = 1;\r
+\r
+ /* Direct input is not used? */\r
+ if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0UL)\r
+ {\r
+ /* Decode PDEC value to get (P) post divider */\r
+ postDiv = 2UL * pllDecodeP(pDecReg & 0x7FUL);\r
+ if (postDiv == 0UL)\r
+ {\r
+ postDiv = 2;\r
+ }\r
+ }\r
+ /* Adjusted by 1, directo is used to bypass */\r
+ return postDiv;\r
+}\r
+\r
+/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */\r
+static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)\r
+{\r
+ uint32_t mMult = 1;\r
+\r
+ /* Decode MDEC value to get (M) multiplier */\r
+ mMult = pllDecodeM(mDecReg & 0x1FFFFUL);\r
+ if (mMult == 0UL)\r
+ {\r
+ mMult = 1;\r
+ }\r
+ return mMult;\r
+}\r
+\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- Core clock\r
+ ---------------------------------------------------------------------------- */\r
+\r
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SystemInit()\r
+ ---------------------------------------------------------------------------- */\r
+\r
+void SystemInit (void) {\r
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))\r
+ SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */\r
+#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */\r
+\r
+#if defined(__MCUXPRESSO)\r
+ extern void(*const g_pfnVectors[]) (void);\r
+ SCB->VTOR = (uint32_t) &g_pfnVectors;\r
+#else\r
+ extern void *__Vectors;\r
+ SCB->VTOR = (uint32_t) &__Vectors;\r
+#endif\r
+ SYSCON->ARMTRACECLKDIV = 0;\r
+/* Optionally enable RAM banks that may be off by default at reset */\r
+#if !defined(DONT_ENABLE_DISABLED_RAMBANKS)\r
+ SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM1_MASK | SYSCON_AHBCLKCTRL_SRAM2_MASK | SYSCON_AHBCLKCTRL_SRAM3_MASK;\r
+\r
+#endif\r
+ SYSCON->MAINCLKSELA = 0U;\r
+ SYSCON->MAINCLKSELB = 0U;\r
+ SystemInitHook();\r
+}\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SystemCoreClockUpdate()\r
+ ---------------------------------------------------------------------------- */\r
+\r
+void SystemCoreClockUpdate (void) {\r
+uint32_t clkRate = 0;\r
+ uint32_t prediv, postdiv;\r
+ uint64_t workRate;\r
+\r
+ switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)\r
+ {\r
+ case 0x00: /* MAINCLKSELA clock (main_clk_a)*/\r
+ switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)\r
+ {\r
+ case 0x00: /* FRO 12 MHz (fro_12m) */\r
+ clkRate = CLK_FRO_12MHZ;\r
+ break;\r
+ case 0x01: /* CLKIN Source (clk_in) */\r
+ clkRate = CLK_CLK_IN;\r
+ break;\r
+ case 0x02: /* Watchdog oscillator (wdt_clk) */\r
+ clkRate = getWdtOscFreq();\r
+ break;\r
+ default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */\r
+ if ((SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) == SYSCON_FROCTRL_SEL_MASK)\r
+ {\r
+ clkRate = CLK_FRO_96MHZ;\r
+ }\r
+ else\r
+ {\r
+ clkRate = CLK_FRO_48MHZ;\r
+ }\r
+ break;\r
+ }\r
+ break;\r
+ case 0x02: /* System PLL clock (pll_clk)*/\r
+ switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)\r
+ {\r
+ case 0x00: /* FRO 12 MHz (fro_12m) */\r
+ clkRate = CLK_FRO_12MHZ;\r
+ break;\r
+ case 0x01: /* CLKIN Source (clk_in) */\r
+ clkRate = CLK_CLK_IN;\r
+ break;\r
+ case 0x02: /* Watchdog oscillator (wdt_clk) */\r
+ clkRate = getWdtOscFreq();\r
+ break;\r
+ case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */\r
+ clkRate = CLK_RTC_32K_CLK;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0UL)\r
+ {\r
+ /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */\r
+ prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC);\r
+ postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC);\r
+ /* Adjust input clock */\r
+ clkRate = clkRate / prediv;\r
+\r
+ /* MDEC used for rate */\r
+ workRate = (uint64_t)(clkRate) * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLMDEC);\r
+ clkRate = (uint32_t)(workRate / ((uint64_t)postdiv));\r
+ clkRate = clkRate * 2; /* PLL CCO output is divided by 2 before to M-Divider */\r
+ }\r
+ break;\r
+ case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */\r
+ clkRate = CLK_RTC_32K_CLK;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL);\r
+}\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SystemInitHook()\r
+ ---------------------------------------------------------------------------- */\r
+\r
+__attribute__ ((weak)) void SystemInitHook (void) {\r
+ /* Void implementation of the weak function. */\r
+}\r
--- /dev/null
+/*\r
+** ###################################################################\r
+** Processors: LPC54018JBD208\r
+** LPC54018JET180\r
+**\r
+** Compilers: GNU C Compiler\r
+** IAR ANSI C/C++ Compiler for ARM\r
+** Keil ARM C/C++ Compiler\r
+** MCUXpresso Compiler\r
+**\r
+** Reference manual: LPC540xx/LPC54S0xx User manual Rev.0.8 5 June 2018\r
+** Version: rev. 1.2, 2017-06-08\r
+** Build: b191014\r
+**\r
+** Abstract:\r
+** Provides a system configuration function and a global variable that\r
+** contains the system frequency. It configures the device and initializes\r
+** the oscillator (PLL) that is part of the microcontroller device.\r
+**\r
+** Copyright 2016 Freescale Semiconductor, Inc.\r
+** Copyright 2016-2019 NXP\r
+** All rights reserved.\r
+**\r
+** SPDX-License-Identifier: BSD-3-Clause\r
+**\r
+** http: www.nxp.com\r
+** mail: support@nxp.com\r
+**\r
+** Revisions:\r
+** - rev. 1.0 (2016-08-12)\r
+** Initial version.\r
+** - rev. 1.1 (2016-11-25)\r
+** Update CANFD and Classic CAN register.\r
+** Add MAC TIMERSTAMP registers.\r
+** - rev. 1.2 (2017-06-08)\r
+** Remove RTC_CTRL_RTC_OSC_BYPASS.\r
+** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.\r
+** Remove RESET and HALT from SYSCON_AHBCLKDIV.\r
+**\r
+** ###################################################################\r
+*/\r
+\r
+/*!\r
+ * @file LPC54018\r
+ * @version 1.2\r
+ * @date 2017-06-08\r
+ * @brief Device specific configuration file for LPC54018 (header file)\r
+ *\r
+ * Provides a system configuration function and a global variable that contains\r
+ * the system frequency. It configures the device and initializes the oscillator\r
+ * (PLL) that is part of the microcontroller device.\r
+ */\r
+\r
+#ifndef _SYSTEM_LPC54018_H_\r
+#define _SYSTEM_LPC54018_H_ /**< Symbol preventing repeated inclusion */\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#include <stdint.h>\r
+\r
+#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */\r
+#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */\r
+#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */\r
+#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */\r
+#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */\r
+#define CLK_CLK_IN 0u /* Default CLK_IN pin clock */\r
+\r
+\r
+/**\r
+ * @brief System clock frequency (core clock)\r
+ *\r
+ * The system clock frequency supplied to the SysTick timer and the processor\r
+ * core clock. This variable can be used by the user application to setup the\r
+ * SysTick timer or configure other parameters. It may also be used by debugger to\r
+ * query the frequency of the debug timer or configure the trace clock speed\r
+ * SystemCoreClock is initialized with a correct predefined value.\r
+ */\r
+extern uint32_t SystemCoreClock;\r
+\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ *\r
+ * Typically this function configures the oscillator (PLL) that is part of the\r
+ * microcontroller device. For systems with variable clock speed it also updates\r
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.\r
+ */\r
+void SystemInit (void);\r
+\r
+/**\r
+ * @brief Updates the SystemCoreClock variable.\r
+ *\r
+ * It must be called whenever the core clock is changed during program\r
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates\r
+ * the current core clock.\r
+ */\r
+void SystemCoreClockUpdate (void);\r
+\r
+/**\r
+ * @brief SystemInit function hook.\r
+ *\r
+ * This weak function allows to call specific initialization code during the\r
+ * SystemInit() execution.This can be used when an application specific code needs\r
+ * to be called as close to the reset entry as possible (for example the Multicore\r
+ * Manager MCMGR_EarlyInit() function call).\r
+ * NOTE: No global r/w variables can be used in this hook function because the\r
+ * initialization of these variables happens after this function.\r
+ */\r
+void SystemInitHook (void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* _SYSTEM_LPC54018_H_ */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016 - 2019 , NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#include "fsl_clock.h"\r
+#include "fsl_power.h"\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+/* Component ID definition, used by tools. */\r
+#ifndef FSL_COMPONENT_ID\r
+#define FSL_COMPONENT_ID "platform.drivers.clock"\r
+#endif\r
+#define NVALMAX (0x100U)\r
+#define PVALMAX (0x20U)\r
+#define MVALMAX (0x8000U)\r
+\r
+#define USB_NVALMAX (0x4U)\r
+#define USB_PVALMAX (0x8U)\r
+#define USB_MVALMAX (0x100U)\r
+\r
+#define PLL_MAX_N_DIV 0x100U\r
+#define USB_PLL_MAX_N_DIV 0x100U\r
+\r
+#define PLL_MDEC_VAL_P (0U) /*!< MDEC is in bits 16 downto 0 */\r
+#define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P) /*!< NDEC is in bits 9 downto 0 */\r
+#define PLL_NDEC_VAL_P (0U) /*!< NDEC is in bits 9:0 */\r
+#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)\r
+#define PLL_PDEC_VAL_P (0U) /*!< PDEC is in bits 6:0 */\r
+#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P)\r
+\r
+#define PLL_MIN_CCO_FREQ_MHZ (275000000U)\r
+#define PLL_MAX_CCO_FREQ_MHZ (550000000U)\r
+#define PLL_LOWER_IN_LIMIT (4000U) /*!< Minimum PLL input rate */\r
+#define PLL_MIN_IN_SSMODE (2000000U)\r
+#define PLL_MAX_IN_SSMODE (4000000U)\r
+\r
+/*!< Middle of the range values for spread-spectrum */\r
+#define PLL_SSCG_MF_FREQ_VALUE 4U\r
+#define PLL_SSCG_MC_COMP_VALUE 2U\r
+#define PLL_SSCG_MR_DEPTH_VALUE 4U\r
+#define PLL_SSCG_DITHER_VALUE 0U\r
+\r
+/*!< USB PLL CCO MAX AND MIN FREQ */\r
+#define USB_PLL_MIN_CCO_FREQ_MHZ (156000000U)\r
+#define USB_PLL_MAX_CCO_FREQ_MHZ (320000000U)\r
+#define USB_PLL_LOWER_IN_LIMIT (1000000U) /*!< Minimum PLL input rate */\r
+\r
+#define USB_PLL_MSEL_VAL_P (0U) /*!< MSEL is in bits 7 downto 0 */\r
+#define USB_PLL_MSEL_VAL_M (0xFFU)\r
+#define USB_PLL_PSEL_VAL_P (8U) /*!< PDEC is in bits 9:8 */\r
+#define USB_PLL_PSEL_VAL_M (0x3U)\r
+#define USB_PLL_NSEL_VAL_P (10U) /*!< NDEC is in bits 11:10 */\r
+#define USB_PLL_NSEL_VAL_M (0x3U)\r
+\r
+/*!< SWITCH USB POSTDIVIDER FOR REGITSER WRITING */\r
+#define SWITCH_USB_PSEL(x) \\r
+ (((x) == 0x0U) ? 0x1U : ((x) == 0x1U) ? 0x02U : ((x) == 0x2U) ? 0x4U : ((x) == 3U) ? 0x8U : 0U)\r
+\r
+/*!< SYS PLL NDEC reg */\r
+#define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M)\r
+/*!< SYS PLL PDEC reg */\r
+#define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M)\r
+/*!< SYS PLL MDEC reg */\r
+#define PLL_MDEC_VAL_SET(value) (((unsigned long)(value) << PLL_MDEC_VAL_P) & PLL_MDEC_VAL_M)\r
+\r
+/*!< SYS PLL NSEL reg */\r
+#define USB_PLL_NSEL_VAL_SET(value) (((unsigned long)(value)&USB_PLL_NSEL_VAL_M) << USB_PLL_NSEL_VAL_P)\r
+/*!< SYS PLL PSEL reg */\r
+#define USB_PLL_PSEL_VAL_SET(value) (((unsigned long)(value)&USB_PLL_PSEL_VAL_M) << USB_PLL_PSEL_VAL_P)\r
+/*!< SYS PLL MSEL reg */\r
+#define USB_PLL_MSEL_VAL_SET(value) (((unsigned long)(value)&USB_PLL_MSEL_VAL_M) << USB_PLL_MSEL_VAL_P)\r
+\r
+/*!< FRAC control */\r
+#define AUDIO_PLL_FRACT_MD_P (0U)\r
+#define AUDIO_PLL_FRACT_MD_INT_P (15U)\r
+#define AUDIO_PLL_FRACT_MD_M (0x7FFFUL << AUDIO_PLL_FRACT_MD_P)\r
+#define AUDIO_PLL_FRACT_MD_INT_M (0x7FUL << AUDIO_PLL_FRACT_MD_INT_P)\r
+\r
+#define AUDIO_PLL_MD_FRACT_SET(value) (((unsigned long)(value) << AUDIO_PLL_FRACT_MD_P) & PLL_FRAC_MD_FRACT_M)\r
+#define AUDIO_PLL_MD_INT_SET(value) (((unsigned long)(value) << AUDIO_PLL_FRACT_MD_INT_P) & AUDIO_PLL_FRACT_MD_INT_M)\r
+\r
+/* Saved value of PLL output rate, computed whenever needed to save run-time\r
+ computation on each call to retrive the PLL rate. */\r
+static uint32_t s_Pll_Freq;\r
+static uint32_t s_Usb_Pll_Freq;\r
+static uint32_t s_Audio_Pll_Freq;\r
+\r
+/** External clock rate on the CLKIN pin in Hz. If not used,\r
+ set this to 0. Otherwise, set it to the exact rate in Hz this pin is\r
+ being driven at. */\r
+static const uint32_t g_I2S_Mclk_Freq = 0U;\r
+static const uint32_t g_Ext_Clk_Freq = 12000000U;\r
+static const uint32_t g_Lcd_Clk_In_Freq = 0U;\r
+\r
+/*******************************************************************************\r
+ * Variables\r
+ ******************************************************************************/\r
+\r
+/*******************************************************************************\r
+ * Prototypes\r
+ ******************************************************************************/\r
+/* Find encoded NDEC value for raw N value, max N = NVALMAX */\r
+static uint32_t pllEncodeN(uint32_t N);\r
+/* Find decoded N value for raw NDEC value */\r
+static uint32_t pllDecodeN(uint32_t NDEC);\r
+/* Find encoded PDEC value for raw P value, max P = PVALMAX */\r
+static uint32_t pllEncodeP(uint32_t P);\r
+/* Find decoded P value for raw PDEC value */\r
+static uint32_t pllDecodeP(uint32_t PDEC);\r
+/* Find encoded MDEC value for raw M value, max M = MVALMAX */\r
+static uint32_t pllEncodeM(uint32_t M);\r
+/* Find decoded M value for raw MDEC value */\r
+static uint32_t pllDecodeM(uint32_t MDEC);\r
+/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */\r
+static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR);\r
+/* Get predivider (N) from PLL NDEC setting */\r
+static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg);\r
+/* Get postdivider (P) from PLL PDEC setting */\r
+static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg);\r
+/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */\r
+static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg);\r
+/* Convert the binary to fractional part */\r
+static double Binary2Fractional(uint32_t binaryPart);\r
+/* Calculate the powerTimes' power of 2 */\r
+static uint32_t power2Cal(uint32_t powerTimes);\r
+/* Get the greatest common divisor */\r
+static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n);\r
+/* Set PLL output based on desired output rate */\r
+static pll_error_t CLOCK_GetPllConfig(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup);\r
+\r
+/* Update local PLL rate variable */\r
+static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup);\r
+static void CLOCK_GetAudioPLLOutFromSetupUpdate(pll_setup_t *pSetup);\r
+\r
+/*!\r
+ * @brief Set fro clock frequency.\r
+ * Due to LPC540xx 0A silicon and LPC540xx 1B silicon have different ROM addresses for set fro\r
+ * frequency api, so add this api to get rom version.\r
+ * @param base romVersion pointer to recieve rom version.\r
+ */\r
+#if defined(FSL_FROHF_SETTING_API_ADDRESS_DETERMINE_BY_ROM_VERSION) && \\r
+ (FSL_FROHF_SETTING_API_ADDRESS_DETERMINE_BY_ROM_VERSION)\r
+static uint32_t CLOCK_GetRomVersion(uint8_t *romVersion);\r
+#endif\r
+\r
+static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41,\r
+ 42, 44, 45, 46, 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};\r
+/*******************************************************************************\r
+ * Code\r
+ ******************************************************************************/\r
+#if defined(FSL_FROHF_SETTING_API_ADDRESS_DETERMINE_BY_ROM_VERSION) && \\r
+ (FSL_FROHF_SETTING_API_ADDRESS_DETERMINE_BY_ROM_VERSION)\r
+static uint32_t CLOCK_GetRomVersion(uint8_t *romVersion)\r
+{\r
+ uint32_t command[5] = {0U}, result[4] = {0U};\r
+\r
+ command[0] = 55U;\r
+ result[0] = 0;\r
+ result[1] = 0;\r
+ ((void (*)(uint32_t cmd[5], uint32_t stat[4]))FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION)(command, result);\r
+\r
+ *romVersion = (uint8_t)(result[1]);\r
+\r
+ return result[0];\r
+}\r
+#endif\r
+\r
+/**\r
+ * brief\r
+ * Initialize the Core clock to given frequency (12, 48 or 96 MHz), this API is implememnt in ROM code.\r
+ * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed\r
+ * output is enabled.\r
+ * Usage: CLOCK_SetupFROClocking(frequency), (frequency must be one of 12, 48 or 96 MHz)\r
+ * Note: Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U) before calling this API since this API is\r
+ * implemented in ROM code and the FROHF TRIM value is stored in OTP\r
+ *\r
+ * param froFreq target fro frequency.\r
+ * return Nothing\r
+ */\r
+\r
+void CLOCK_SetupFROClocking(uint32_t froFreq)\r
+{\r
+ uint32_t froRomAddr = 0U;\r
+#if defined(FSL_FROHF_SETTING_API_ADDRESS_DETERMINE_BY_ROM_VERSION) && \\r
+ (FSL_FROHF_SETTING_API_ADDRESS_DETERMINE_BY_ROM_VERSION)\r
+ uint8_t romVersion = 0U;\r
+\r
+ if (CLOCK_GetRomVersion(&romVersion) == (uint32_t)kStatus_Success)\r
+ {\r
+ if (romVersion == FSL_ROM_VERSION_1B)\r
+ {\r
+ froRomAddr = FSL_ROM_VERSION_1B_FRO_SETTING_ADDR;\r
+ }\r
+ else\r
+ {\r
+ froRomAddr = FSL_ROM_VERSION_0A_FRO_SETTING_ADDR;\r
+ }\r
+\r
+ (*((void (*)(uint32_t funcname))(froRomAddr)))(froFreq);\r
+ }\r
+#else\r
+ froRomAddr = FSL_ROM_VERSION_0A_FRO_SETTING_ADDR;\r
+\r
+ (*((void (*)(uint32_t))(froRomAddr)))(froFreq);\r
+#endif\r
+}\r
+\r
+/* Clock Selection for IP */\r
+/**\r
+ * brief Configure the clock selection muxes.\r
+ * param connection : Clock to be configured.\r
+ * return Nothing\r
+ */\r
+void CLOCK_AttachClk(clock_attach_id_t connection)\r
+{\r
+ uint8_t mux;\r
+ uint8_t sel;\r
+ uint16_t item;\r
+ uint32_t tmp32 = (uint32_t)connection;\r
+ uint32_t i;\r
+ volatile uint32_t *pClkSel;\r
+\r
+ pClkSel = &(SYSCON->STICKCLKSEL);\r
+\r
+ if (kNONE_to_NONE != connection)\r
+ {\r
+ for (i = 0U; i < 2U; i++)\r
+ {\r
+ if (tmp32 == 0U)\r
+ {\r
+ break;\r
+ }\r
+ item = (uint16_t)GET_ID_ITEM(tmp32);\r
+ if (item != 0UL)\r
+ {\r
+ mux = GET_ID_ITEM_MUX(item);\r
+ sel = GET_ID_ITEM_SEL(item);\r
+ if (mux == CM_ASYNCAPB)\r
+ {\r
+ SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(1);\r
+ ASYNC_SYSCON->ASYNCAPBCLKSELA = sel;\r
+ }\r
+ else\r
+ {\r
+ ((volatile uint32_t *)pClkSel)[mux] = sel;\r
+ }\r
+ }\r
+ tmp32 = GET_ID_NEXT_ITEM(tmp32); /* pick up next descriptor */\r
+ }\r
+ }\r
+}\r
+\r
+/* Return the actual clock attach id */\r
+/**\r
+ * brief Get the actual clock attach id.\r
+ * This fuction uses the offset in input attach id, then it reads the actual source value in\r
+ * the register and combine the offset to obtain an actual attach id.\r
+ * param attachId : Clock attach id to get.\r
+ * return Clock source value.\r
+ */\r
+clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId)\r
+{\r
+ uint8_t mux;\r
+ uint8_t actualSel;\r
+ uint32_t tmp32 = (uint32_t)attachId;\r
+ uint32_t i;\r
+ uint32_t actualAttachId = 0U;\r
+ uint32_t selector = GET_ID_SELECTOR(tmp32);\r
+ volatile uint32_t *pClkSel;\r
+\r
+ pClkSel = &(SYSCON->STICKCLKSEL);\r
+\r
+ if (kNONE_to_NONE == attachId)\r
+ {\r
+ return kNONE_to_NONE;\r
+ }\r
+\r
+ for (i = 0U; i < 2U; i++)\r
+ {\r
+ mux = GET_ID_ITEM_MUX(tmp32);\r
+ if (tmp32 != 0UL)\r
+ {\r
+ if (mux == CM_ASYNCAPB)\r
+ {\r
+ actualSel = (uint8_t)(ASYNC_SYSCON->ASYNCAPBCLKSELA);\r
+ }\r
+ else\r
+ {\r
+ actualSel = (uint8_t)(((volatile uint32_t *)pClkSel)[mux]);\r
+ }\r
+\r
+ /* Consider the combination of two registers */\r
+ actualAttachId |= CLK_ATTACH_ID(mux, actualSel, i);\r
+ }\r
+ tmp32 = GET_ID_NEXT_ITEM(tmp32); /*!< pick up next descriptor */\r
+ }\r
+\r
+ actualAttachId |= selector;\r
+\r
+ return (clock_attach_id_t)actualAttachId;\r
+}\r
+\r
+/* Set IP Clock Divider */\r
+/**\r
+ * brief Setup peripheral clock dividers.\r
+ * param div_name : Clock divider name\r
+ * param divided_by_value: Value to be divided\r
+ * param reset : Whether to reset the divider counter.\r
+ * return Nothing\r
+ */\r
+void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset)\r
+{\r
+ volatile uint32_t *pClkDiv;\r
+\r
+ pClkDiv = &(SYSCON->SYSTICKCLKDIV);\r
+ if (reset)\r
+ {\r
+ ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = 1UL << 29U;\r
+ }\r
+ if (divided_by_value == 0U) /*!< halt */\r
+ {\r
+ ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = 1UL << 30U;\r
+ }\r
+ else\r
+ {\r
+ ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = (divided_by_value - 1U);\r
+ }\r
+}\r
+\r
+/* Get CLOCK OUT Clk */\r
+/*! brief Return Frequency of ClockOut\r
+ * return Frequency of ClockOut\r
+ */\r
+uint32_t CLOCK_GetClockOutClkFreq(void)\r
+{\r
+ uint32_t freq = 0U;\r
+\r
+ switch (SYSCON->CLKOUTSELA)\r
+ {\r
+ case 0U:\r
+ freq = CLOCK_GetCoreSysClkFreq();\r
+ break;\r
+\r
+ case 1U:\r
+ freq = CLOCK_GetExtClkFreq();\r
+ break;\r
+\r
+ case 2U:\r
+ freq = CLOCK_GetWdtOscFreq();\r
+ break;\r
+\r
+ case 3U:\r
+ freq = CLOCK_GetFroHfFreq();\r
+ break;\r
+\r
+ case 4U:\r
+ freq = CLOCK_GetPllOutFreq();\r
+ break;\r
+\r
+ case 5U:\r
+ freq = CLOCK_GetUsbPllOutFreq();\r
+ break;\r
+\r
+ case 6U:\r
+ freq = CLOCK_GetAudioPllOutFreq();\r
+ break;\r
+\r
+ case 7U:\r
+ freq = CLOCK_GetOsc32KFreq();\r
+ break;\r
+\r
+ default:\r
+ freq = 0U;\r
+ break;\r
+ }\r
+ return freq / ((SYSCON->CLKOUTDIV & 0xffU) + 1U);\r
+}\r
+\r
+/* Get SPIFI Clk */\r
+/*! brief Return Frequency of Spifi Clock\r
+ * return Frequency of Spifi.\r
+ */\r
+uint32_t CLOCK_GetSpifiClkFreq(void)\r
+{\r
+ uint32_t freq = 0U;\r
+\r
+ switch (SYSCON->SPIFICLKSEL)\r
+ {\r
+ case 0U:\r
+ freq = CLOCK_GetCoreSysClkFreq();\r
+ break;\r
+ case 1U:\r
+ freq = CLOCK_GetPllOutFreq();\r
+ break;\r
+ case 2U:\r
+ freq = CLOCK_GetUsbPllOutFreq();\r
+ break;\r
+ case 3U:\r
+ freq = CLOCK_GetFroHfFreq();\r
+ break;\r
+ case 4U:\r
+ freq = CLOCK_GetAudioPllOutFreq();\r
+ break;\r
+ case 7U:\r
+ freq = 0U;\r
+ break;\r
+ default:\r
+ freq = 0U;\r
+ break;\r
+ }\r
+\r
+ return freq / ((SYSCON->SPIFICLKDIV & 0xffU) + 1U);\r
+}\r
+\r
+/* Get ADC Clk */\r
+/*! brief Return Frequency of Adc Clock\r
+ * return Frequency of Adc Clock.\r
+ */\r
+uint32_t CLOCK_GetAdcClkFreq(void)\r
+{\r
+ uint32_t freq = 0U;\r
+\r
+ switch (SYSCON->ADCCLKSEL)\r
+ {\r
+ case 0U:\r
+ freq = CLOCK_GetFroHfFreq();\r
+ break;\r
+ case 1U:\r
+ freq = CLOCK_GetPllOutFreq();\r
+ break;\r
+ case 2U:\r
+ freq = CLOCK_GetUsbPllOutFreq();\r
+ break;\r
+ case 3U:\r
+ freq = CLOCK_GetAudioPllOutFreq();\r
+ break;\r
+ case 7U:\r
+ freq = 0U;\r
+ break;\r
+ default:\r
+ freq = 0U;\r
+ break;\r
+ }\r
+\r
+ return freq / ((SYSCON->ADCCLKDIV & 0xffU) + 1U);\r
+}\r
+\r
+/* Get USB0 Clk */\r
+/*! brief Return Frequency of Usb0 Clock\r
+ * return Frequency of Usb0 Clock.\r
+ */\r
+uint32_t CLOCK_GetUsb0ClkFreq(void)\r
+{\r
+ uint32_t freq = 0U;\r
+\r
+ switch (SYSCON->USB0CLKSEL)\r
+ {\r
+ case 0U:\r
+ freq = CLOCK_GetFroHfFreq();\r
+ break;\r
+ case 1U:\r
+ freq = CLOCK_GetPllOutFreq();\r
+ break;\r
+ case 2U:\r
+ freq = CLOCK_GetUsbPllOutFreq();\r
+ break;\r
+ case 7U:\r
+ freq = 0U;\r
+ break;\r
+\r
+ default:\r
+ freq = 0U;\r
+ break;\r
+ }\r
+\r
+ return freq / ((SYSCON->USB0CLKDIV & 0xffU) + 1U);\r
+}\r
+\r
+/* Get USB1 Clk */\r
+/*! brief Return Frequency of Usb1 Clock\r
+ * return Frequency of Usb1 Clock.\r
+ */\r
+uint32_t CLOCK_GetUsb1ClkFreq(void)\r
+{\r
+ uint32_t freq = 0U;\r
+\r
+ switch (SYSCON->USB1CLKSEL)\r
+ {\r
+ case 0U:\r
+ freq = CLOCK_GetCoreSysClkFreq();\r
+ break;\r
+ case 1U:\r
+ freq = CLOCK_GetPllOutFreq();\r
+ break;\r
+ case 2U:\r
+ freq = CLOCK_GetUsbPllOutFreq();\r
+ break;\r
+ case 7U:\r
+ freq = 0U;\r
+ break;\r
+\r
+ default:\r
+ freq = 0U;\r
+ break;\r
+ }\r
+\r
+ return freq / ((SYSCON->USB1CLKDIV & 0xffU) + 1U);\r
+}\r
+\r
+/* Get MCLK Clk */\r
+/*! brief Return Frequency of MClk Clock\r
+ * return Frequency of MClk Clock.\r
+ */\r
+uint32_t CLOCK_GetMclkClkFreq(void)\r
+{\r
+ uint32_t freq = 0U;\r
+\r
+ switch (SYSCON->MCLKCLKSEL)\r
+ {\r
+ case 0U:\r
+ freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffu) + 1U);\r
+ break;\r
+ case 1U:\r
+ freq = CLOCK_GetAudioPllOutFreq();\r
+ break;\r
+ case 7U:\r
+ freq = 0U;\r
+ break;\r
+\r
+ default:\r
+ freq = 0U;\r
+ break;\r
+ }\r
+\r
+ return freq / ((SYSCON->MCLKDIV & 0xffU) + 1U);\r
+}\r
+\r
+/* Get SCTIMER Clk */\r
+/*! brief Return Frequency of SCTimer Clock\r
+ * return Frequency of SCTimer Clock.\r
+ */\r
+uint32_t CLOCK_GetSctClkFreq(void)\r
+{\r
+ uint32_t freq = 0U;\r
+\r
+ switch (SYSCON->SCTCLKSEL)\r
+ {\r
+ case 0U:\r
+ freq = CLOCK_GetCoreSysClkFreq();\r
+ break;\r
+ case 1U:\r
+ freq = CLOCK_GetPllOutFreq();\r
+ break;\r
+ case 2U:\r
+ freq = CLOCK_GetFroHfFreq();\r
+ break;\r
+ case 3U:\r
+ freq = CLOCK_GetAudioPllOutFreq();\r
+ break;\r
+ case 7U:\r
+ freq = 0U;\r
+ break;\r
+\r
+ default:\r
+ freq = 0U;\r
+ break;\r
+ }\r
+\r
+ return freq / ((SYSCON->SCTCLKDIV & 0xffU) + 1U);\r
+}\r
+\r
+/* Get SDIO Clk */\r
+/*! brief Return Frequency of SDIO Clock\r
+ * return Frequency of SDIO Clock.\r
+ */\r
+uint32_t CLOCK_GetSdioClkFreq(void)\r
+{\r
+ uint32_t freq = 0U;\r
+\r
+ switch (SYSCON->SDIOCLKSEL)\r
+ {\r
+ case 0U:\r
+ freq = CLOCK_GetCoreSysClkFreq();\r
+ break;\r
+ case 1U:\r
+ freq = CLOCK_GetPllOutFreq();\r
+ break;\r
+ case 2U:\r
+ freq = CLOCK_GetUsbPllOutFreq();\r
+ break;\r
+ case 3U:\r
+ freq = CLOCK_GetFroHfFreq();\r
+ break;\r
+ case 4U:\r
+ freq = CLOCK_GetAudioPllOutFreq();\r
+ break;\r
+ case 7U:\r
+ freq = 0U;\r
+ break;\r
+ default:\r
+ freq = 0U;\r
+ break;\r
+ }\r
+\r
+ return freq / ((SYSCON->SDIOCLKDIV & 0xffU) + 1U);\r
+}\r
+\r
+/* Get LCD Clk */\r
+/*! brief Return Frequency of LCD Clock\r
+ * return Frequency of LCD Clock.\r
+ */\r
+uint32_t CLOCK_GetLcdClkFreq(void)\r
+{\r
+ uint32_t freq = 0U;\r
+\r
+ switch (SYSCON->LCDCLKSEL)\r
+ {\r
+ case 0U:\r
+ freq = CLOCK_GetCoreSysClkFreq();\r
+ break;\r
+ case 1U:\r
+ freq = CLOCK_GetLcdClkIn();\r
+ break;\r
+ case 2U:\r
+ freq = CLOCK_GetFroHfFreq();\r
+ break;\r
+ case 3U:\r
+ freq = 0U;\r
+ break;\r
+\r
+ default:\r
+ freq = 0U;\r
+ break;\r
+ }\r
+\r
+ return freq / ((SYSCON->LCDCLKDIV & 0xffU) + 1U);\r
+}\r
+\r
+/* Get LCD CLK IN Clk */\r
+/*! brief Return Frequency of LCD CLKIN Clock\r
+ * return Frequency of LCD CLKIN Clock.\r
+ */\r
+uint32_t CLOCK_GetLcdClkIn(void)\r
+{\r
+ return g_Lcd_Clk_In_Freq;\r
+}\r
+\r
+/* Get FRO 12M Clk */\r
+/*! brief Return Frequency of FRO 12MHz\r
+ * return Frequency of FRO 12MHz\r
+ */\r
+uint32_t CLOCK_GetFro12MFreq(void)\r
+{\r
+ return ((SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) != 0UL) ? 0U : 12000000U;\r
+}\r
+\r
+/* Get EXT OSC Clk */\r
+/*! brief Return Frequency of External Clock\r
+ * return Frequency of External Clock. If no external clock is used returns 0.\r
+ */\r
+uint32_t CLOCK_GetExtClkFreq(void)\r
+{\r
+ return g_Ext_Clk_Freq;\r
+}\r
+\r
+/* Get WATCH DOG Clk */\r
+/*! brief Return Frequency of Watchdog Oscillator\r
+ * return Frequency of Watchdog Oscillator\r
+ */\r
+uint32_t CLOCK_GetWdtOscFreq(void)\r
+{\r
+ uint8_t freq_sel, div_sel;\r
+ if ((SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) != 0UL)\r
+ {\r
+ return 0U;\r
+ }\r
+ else\r
+ {\r
+ div_sel = (uint8_t)(((SYSCON->WDTOSCCTRL & 0x1fU) + 1U) << 1U);\r
+ freq_sel =\r
+ wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];\r
+ return ((uint32_t)freq_sel * 50000U) / ((uint32_t)div_sel);\r
+ }\r
+}\r
+\r
+/* Get HF FRO Clk */\r
+/*! brief Return Frequency of High-Freq output of FRO\r
+ * return Frequency of High-Freq output of FRO\r
+ */\r
+uint32_t CLOCK_GetFroHfFreq(void)\r
+{\r
+ if (((SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) != 0UL) ||\r
+ (0UL == (SYSCON->FROCTRL & SYSCON_FROCTRL_HSPDCLK_MASK)))\r
+ {\r
+ return 0U;\r
+ }\r
+\r
+ if ((SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) != 0UL)\r
+ {\r
+ return 96000000U;\r
+ }\r
+ else\r
+ {\r
+ return 48000000U;\r
+ }\r
+}\r
+\r
+/* Get SYSTEM PLL Clk */\r
+/*! brief Return Frequency of PLL\r
+ * return Frequency of PLL\r
+ */\r
+uint32_t CLOCK_GetPllOutFreq(void)\r
+{\r
+ return s_Pll_Freq;\r
+}\r
+\r
+/* Get AUDIO PLL Clk */\r
+/*! brief Return Frequency of AUDIO PLL\r
+ * return Frequency of PLL\r
+ */\r
+uint32_t CLOCK_GetAudioPllOutFreq(void)\r
+{\r
+ return s_Audio_Pll_Freq;\r
+}\r
+\r
+/* Get USB PLL Clk */\r
+/*! brief Return Frequency of USB PLL\r
+ * return Frequency of PLL\r
+ */\r
+uint32_t CLOCK_GetUsbPllOutFreq(void)\r
+{\r
+ return s_Usb_Pll_Freq;\r
+}\r
+\r
+/* Get RTC OSC Clk */\r
+/*! brief Return Frequency of 32kHz osc\r
+ * return Frequency of 32kHz osc\r
+ */\r
+uint32_t CLOCK_GetOsc32KFreq(void)\r
+{\r
+ return CLK_RTC_32K_CLK; /* Needs to be corrected to check that RTC Clock is enabled */\r
+}\r
+\r
+/* Get MAIN Clk */\r
+/*! brief Return Frequency of Core System\r
+ * return Frequency of Core System\r
+ */\r
+uint32_t CLOCK_GetCoreSysClkFreq(void)\r
+{\r
+ uint32_t freq = 0U;\r
+\r
+ switch (SYSCON->MAINCLKSELB)\r
+ {\r
+ case 0U:\r
+ if (SYSCON->MAINCLKSELA == 0U)\r
+ {\r
+ freq = CLOCK_GetFro12MFreq();\r
+ }\r
+ else if (SYSCON->MAINCLKSELA == 1U)\r
+ {\r
+ freq = CLOCK_GetExtClkFreq();\r
+ }\r
+ else if (SYSCON->MAINCLKSELA == 2U)\r
+ {\r
+ freq = CLOCK_GetWdtOscFreq();\r
+ }\r
+ else if (SYSCON->MAINCLKSELA == 3U)\r
+ {\r
+ freq = CLOCK_GetFroHfFreq();\r
+ }\r
+ else\r
+ {\r
+ /* Add comment to prevent the case of rule 15.7. */\r
+ }\r
+ break;\r
+ case 2U:\r
+ freq = CLOCK_GetPllOutFreq();\r
+ break;\r
+\r
+ case 3U:\r
+ freq = CLOCK_GetOsc32KFreq();\r
+ break;\r
+\r
+ default:\r
+ freq = 0U;\r
+ break;\r
+ }\r
+\r
+ return freq;\r
+}\r
+\r
+/* Get I2S MCLK Clk */\r
+/*! brief Return Frequency of I2S MCLK Clock\r
+ * return Frequency of I2S MCLK Clock\r
+ */\r
+uint32_t CLOCK_GetI2SMClkFreq(void)\r
+{\r
+ return g_I2S_Mclk_Freq;\r
+}\r
+\r
+/* Get ASYNC APB Clk */\r
+/*! brief Return Frequency of Asynchronous APB Clock\r
+ * return Frequency of Asynchronous APB Clock Clock\r
+ */\r
+uint32_t CLOCK_GetAsyncApbClkFreq(void)\r
+{\r
+ async_clock_src_t clkSrc;\r
+ uint32_t clkRate;\r
+\r
+ clkSrc = CLOCK_GetAsyncApbClkSrc();\r
+\r
+ switch (clkSrc)\r
+ {\r
+ case kCLOCK_AsyncMainClk:\r
+ clkRate = CLOCK_GetCoreSysClkFreq();\r
+ break;\r
+ case kCLOCK_AsyncFro12Mhz:\r
+ clkRate = CLK_FRO_12MHZ;\r
+ break;\r
+ default:\r
+ clkRate = 0U;\r
+ break;\r
+ }\r
+\r
+ return clkRate;\r
+}\r
+\r
+/* Get MCAN Clk */\r
+/*! brief Return Frequency of MCAN Clock\r
+ * param MCanSel : 0U: MCAN0; 1U: MCAN1\r
+ * return Frequency of MCAN Clock\r
+ */\r
+uint32_t CLOCK_GetMCanClkFreq(uint32_t MCanSel)\r
+{\r
+ uint32_t freq = 0U;\r
+ switch (MCanSel)\r
+ {\r
+ case 0U:\r
+ freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->CAN0CLKDIV & 0xffU) + 1U);\r
+ break;\r
+ case 1U:\r
+ freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->CAN1CLKDIV & 0xffU) + 1U);\r
+ break;\r
+\r
+ default:\r
+ freq = 0U;\r
+ break;\r
+ }\r
+\r
+ return freq;\r
+}\r
+\r
+/* Get FLEXCOMM Clk */\r
+/*! brief Return Frequency of Flexcomm functional Clock\r
+ * return Frequency of Flexcomm functional Clock\r
+ */\r
+uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id)\r
+{\r
+ uint32_t freq = 0U;\r
+\r
+ if (id != 10U)\r
+ {\r
+ switch (SYSCON->FCLKSEL[id])\r
+ {\r
+ case 0U:\r
+ freq = CLOCK_GetFro12MFreq();\r
+ break;\r
+ case 1U:\r
+ freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffu) + 1U);\r
+ break;\r
+ case 2U:\r
+ freq = CLOCK_GetAudioPllOutFreq();\r
+ break;\r
+ case 3U:\r
+ freq = CLOCK_GetI2SMClkFreq();\r
+ break;\r
+ case 4U:\r
+ freq = CLOCK_GetFrgClkFreq();\r
+ break;\r
+\r
+ default:\r
+ freq = 0U;\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ switch (SYSCON->FCLKSEL10)\r
+ {\r
+ case 0U:\r
+ freq = CLOCK_GetCoreSysClkFreq();\r
+ break;\r
+ case 1U:\r
+ freq = CLOCK_GetPllOutFreq();\r
+ break;\r
+ case 2U:\r
+ freq = CLOCK_GetUsbPllOutFreq();\r
+ break;\r
+ case 3U:\r
+ freq = CLOCK_GetFroHfFreq();\r
+ break;\r
+ case 4U:\r
+ freq = CLOCK_GetAudioPllOutFreq();\r
+ break;\r
+ default:\r
+ freq = 0U;\r
+ break;\r
+ }\r
+ }\r
+\r
+ return freq;\r
+}\r
+\r
+/* Get FRG Clk */\r
+uint32_t CLOCK_GetFRGInputClock(void)\r
+{\r
+ uint32_t freq = 0U;\r
+\r
+ switch (SYSCON->FRGCLKSEL)\r
+ {\r
+ case 0U:\r
+ freq = CLOCK_GetCoreSysClkFreq();\r
+ break;\r
+ case 1U:\r
+ freq = CLOCK_GetPllOutFreq();\r
+ break;\r
+ case 2U:\r
+ freq = CLOCK_GetFro12MFreq();\r
+ break;\r
+ case 3U:\r
+ freq = CLOCK_GetFroHfFreq();\r
+ break;\r
+\r
+ default:\r
+ freq = 0U;\r
+ break;\r
+ }\r
+\r
+ return freq;\r
+}\r
+\r
+/* Get FRG Clk */\r
+/*! brief Return Frequency of frg\r
+ * return Frequency of FRG\r
+ */\r
+uint32_t CLOCK_GetFrgClkFreq(void)\r
+{\r
+ uint32_t freq = 0U;\r
+\r
+ if ((SYSCON->FRGCTRL & SYSCON_FRGCTRL_DIV_MASK) == SYSCON_FRGCTRL_DIV_MASK)\r
+ {\r
+ freq = (uint32_t)(((uint64_t)CLOCK_GetFRGInputClock() * (SYSCON_FRGCTRL_DIV_MASK + 1U)) /\r
+ ((SYSCON_FRGCTRL_DIV_MASK + 1U) +\r
+ ((SYSCON->FRGCTRL & SYSCON_FRGCTRL_MULT_MASK) >> SYSCON_FRGCTRL_MULT_SHIFT)));\r
+ }\r
+ else\r
+ {\r
+ freq = 0U;\r
+ }\r
+\r
+ return freq;\r
+}\r
+\r
+/* Get FRG Clk */\r
+/*! brief Return Frequency of dmic\r
+ * return Frequency of DMIC\r
+ */\r
+uint32_t CLOCK_GetDmicClkFreq(void)\r
+{\r
+ uint32_t freq = 0U;\r
+\r
+ switch (SYSCON->DMICCLKSEL)\r
+ {\r
+ case 0U:\r
+ freq = CLOCK_GetFro12MFreq();\r
+ break;\r
+ case 1U:\r
+ freq = CLOCK_GetFroHfFreq();\r
+ break;\r
+ case 2U:\r
+ freq = CLOCK_GetPllOutFreq();\r
+ break;\r
+ case 3U:\r
+ freq = CLOCK_GetI2SMClkFreq();\r
+ break;\r
+ case 4U:\r
+ freq = CLOCK_GetCoreSysClkFreq();\r
+ break;\r
+ case 5U:\r
+ freq = CLOCK_GetWdtOscFreq();\r
+ break;\r
+ default:\r
+ freq = 0U;\r
+ break;\r
+ }\r
+\r
+ return freq / ((SYSCON->DMICCLKDIV & 0xffU) + 1U);\r
+ ;\r
+}\r
+\r
+/* Set FRG Clk */\r
+uint32_t CLOCK_SetFRGClock(uint32_t freq)\r
+{\r
+ assert(0UL != freq);\r
+\r
+ uint32_t input = CLOCK_GetFRGInputClock();\r
+ uint32_t mul;\r
+\r
+ if ((freq > 48000000U) || (freq > input) || (input / freq >= 2U))\r
+ {\r
+ /* FRG output frequency should be less than equal to 48MHz */\r
+ return 0U;\r
+ }\r
+ else\r
+ {\r
+ mul = (uint32_t)((((uint64_t)input - freq) * 256U) / ((uint64_t)freq));\r
+ SYSCON->FRGCTRL = (mul << SYSCON_FRGCTRL_MULT_SHIFT) | SYSCON_FRGCTRL_DIV_MASK;\r
+ return 1U;\r
+ }\r
+}\r
+\r
+/* Set IP Clk */\r
+/*! brief Return Frequency of selected clock\r
+ * return Frequency of selected clock\r
+ */\r
+uint32_t CLOCK_GetFreq(clock_name_t clockName)\r
+{\r
+ uint32_t freq;\r
+ switch (clockName)\r
+ {\r
+ case kCLOCK_CoreSysClk:\r
+ freq = CLOCK_GetCoreSysClkFreq();\r
+ break;\r
+ case kCLOCK_BusClk:\r
+ freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U);\r
+ break;\r
+ case kCLOCK_ClockOut:\r
+ freq = CLOCK_GetClockOutClkFreq();\r
+ break;\r
+ case kCLOCK_Mclk:\r
+ freq = CLOCK_GetMclkClkFreq();\r
+ break;\r
+ case kCLOCK_FroHf:\r
+ freq = CLOCK_GetFroHfFreq();\r
+ break;\r
+ case kCLOCK_Fro12M:\r
+ freq = CLOCK_GetFro12MFreq();\r
+ break;\r
+ case kCLOCK_ExtClk:\r
+ freq = CLOCK_GetExtClkFreq();\r
+ break;\r
+ case kCLOCK_PllOut:\r
+ freq = CLOCK_GetPllOutFreq();\r
+ break;\r
+ case kCLOCK_WdtOsc:\r
+ freq = CLOCK_GetWdtOscFreq();\r
+ break;\r
+ case kCLOCK_Frg:\r
+ freq = CLOCK_GetFrgClkFreq();\r
+ break;\r
+\r
+ case kCLOCK_AsyncApbClk:\r
+ freq = CLOCK_GetAsyncApbClkFreq();\r
+ break;\r
+ default:\r
+ freq = 0U;\r
+ break;\r
+ }\r
+\r
+ return freq;\r
+}\r
+\r
+/* Find encoded NDEC value for raw N value, max N = NVALMAX */\r
+static uint32_t pllEncodeN(uint32_t N)\r
+{\r
+ uint32_t x, i;\r
+\r
+ /* Find NDec */\r
+ switch (N)\r
+ {\r
+ case 0U:\r
+ x = 0x3FFU;\r
+ break;\r
+\r
+ case 1U:\r
+ x = 0x302U;\r
+ break;\r
+\r
+ case 2U:\r
+ x = 0x202U;\r
+ break;\r
+\r
+ default:\r
+ x = 0x080U;\r
+ for (i = N; i <= NVALMAX; i++)\r
+ {\r
+ x = (((x ^ (x >> 2U) ^ (x >> 3U) ^ (x >> 4U)) & 1U) << 7U) | ((x >> 1U) & 0x7FU);\r
+ }\r
+ break;\r
+ }\r
+\r
+ return x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P);\r
+}\r
+\r
+/* Find decoded N value for raw NDEC value */\r
+static uint32_t pllDecodeN(uint32_t NDEC)\r
+{\r
+ uint32_t n, x, i;\r
+\r
+ /* Find NDec */\r
+ switch (NDEC)\r
+ {\r
+ case 0x3FFU:\r
+ n = 0U;\r
+ break;\r
+\r
+ case 0x302U:\r
+ n = 1U;\r
+ break;\r
+\r
+ case 0x202U:\r
+ n = 2U;\r
+ break;\r
+\r
+ default:\r
+ x = 0x080U;\r
+ n = 0xFFFFFFFFU;\r
+ for (i = NVALMAX; i >= 3U; i--)\r
+ {\r
+ x = (((x ^ (x >> 2U) ^ (x >> 3U) ^ (x >> 4U)) & 1U) << 7U) | ((x >> 1U) & 0x7FU);\r
+ if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)\r
+ {\r
+ /* Decoded value of NDEC */\r
+ n = i;\r
+ break;\r
+ }\r
+ }\r
+ break;\r
+ }\r
+\r
+ return n;\r
+}\r
+\r
+/* Find encoded PDEC value for raw P value, max P = PVALMAX */\r
+static uint32_t pllEncodeP(uint32_t P)\r
+{\r
+ uint32_t x, i;\r
+\r
+ /* Find PDec */\r
+ switch (P)\r
+ {\r
+ case 0U:\r
+ x = 0x7FU;\r
+ break;\r
+\r
+ case 1U:\r
+ x = 0x62U;\r
+ break;\r
+\r
+ case 2U:\r
+ x = 0x42U;\r
+ break;\r
+\r
+ default:\r
+ x = 0x10U;\r
+ for (i = P; i <= PVALMAX; i++)\r
+ {\r
+ x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU);\r
+ }\r
+ break;\r
+ }\r
+\r
+ return x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P);\r
+}\r
+\r
+/* Find decoded P value for raw PDEC value */\r
+static uint32_t pllDecodeP(uint32_t PDEC)\r
+{\r
+ uint32_t p, x, i;\r
+\r
+ /* Find PDec */\r
+ switch (PDEC)\r
+ {\r
+ case 0x7FU:\r
+ p = 0U;\r
+ break;\r
+\r
+ case 0x62U:\r
+ p = 1U;\r
+ break;\r
+\r
+ case 0x42U:\r
+ p = 2U;\r
+ break;\r
+\r
+ default:\r
+ x = 0x10U;\r
+ p = 0xFFFFFFFFU;\r
+ for (i = PVALMAX; i >= 3U; i--)\r
+ {\r
+ x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU);\r
+ if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)\r
+ {\r
+ /* Decoded value of PDEC */\r
+ p = i;\r
+ break;\r
+ }\r
+ }\r
+ break;\r
+ }\r
+\r
+ return p;\r
+}\r
+\r
+/* Find encoded MDEC value for raw M value, max M = MVALMAX */\r
+static uint32_t pllEncodeM(uint32_t M)\r
+{\r
+ uint32_t i, x;\r
+\r
+ /* Find MDec */\r
+ switch (M)\r
+ {\r
+ case 0U:\r
+ x = 0x1FFFFU;\r
+ break;\r
+\r
+ case 1U:\r
+ x = 0x18003U;\r
+ break;\r
+\r
+ case 2U:\r
+ x = 0x10003U;\r
+ break;\r
+\r
+ default:\r
+ x = 0x04000U;\r
+ for (i = M; i <= MVALMAX; i++)\r
+ {\r
+ x = (((x ^ (x >> 1U)) & 1U) << 14U) | ((x >> 1U) & 0x3FFFU);\r
+ }\r
+ break;\r
+ }\r
+\r
+ return x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P);\r
+}\r
+\r
+/* Find decoded M value for raw MDEC value */\r
+static uint32_t pllDecodeM(uint32_t MDEC)\r
+{\r
+ uint32_t m, i, x;\r
+\r
+ /* Find MDec */\r
+ switch (MDEC)\r
+ {\r
+ case 0x1FFFFU:\r
+ m = 0U;\r
+ break;\r
+\r
+ case 0x18003U:\r
+ m = 1U;\r
+ break;\r
+\r
+ case 0x10003U:\r
+ m = 2U;\r
+ break;\r
+\r
+ default:\r
+ x = 0x04000U;\r
+ m = 0xFFFFFFFFU;\r
+ for (i = MVALMAX; i >= 3U; i--)\r
+ {\r
+ x = (((x ^ (x >> 1U)) & 1U) << 14U) | ((x >> 1U) & 0x3FFFU);\r
+ if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC)\r
+ {\r
+ /* Decoded value of MDEC */\r
+ m = i;\r
+ break;\r
+ }\r
+ }\r
+ break;\r
+ }\r
+\r
+ return m;\r
+}\r
+\r
+/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */\r
+static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR)\r
+{\r
+ /* bandwidth: compute selP from Multiplier */\r
+ if (M < 60U)\r
+ {\r
+ *pSelP = (M >> 1U) + 1U;\r
+ }\r
+ else\r
+ {\r
+ *pSelP = PVALMAX - 1U;\r
+ }\r
+\r
+ /* bandwidth: compute selI from Multiplier */\r
+ if (M > 16384U)\r
+ {\r
+ *pSelI = 1U;\r
+ }\r
+ else if (M > 8192U)\r
+ {\r
+ *pSelI = 2U;\r
+ }\r
+ else if (M > 2048U)\r
+ {\r
+ *pSelI = 4U;\r
+ }\r
+ else if (M >= 501U)\r
+ {\r
+ *pSelI = 8U;\r
+ }\r
+ else if (M >= 60U)\r
+ {\r
+ *pSelI = 4U * (1024U / (M + 9U));\r
+ }\r
+ else\r
+ {\r
+ *pSelI = (M & 0x3CU) + 4U;\r
+ }\r
+\r
+ if (*pSelI > ((0x3FUL << SYSCON_SYSPLLCTRL_SELI_SHIFT) >> SYSCON_SYSPLLCTRL_SELI_SHIFT))\r
+ {\r
+ *pSelI = ((0x3FUL << SYSCON_SYSPLLCTRL_SELI_SHIFT) >> SYSCON_SYSPLLCTRL_SELI_SHIFT);\r
+ }\r
+\r
+ *pSelR = 0U;\r
+}\r
+\r
+/* Get predivider (N) from PLL NDEC setting */\r
+static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)\r
+{\r
+ uint32_t preDiv = 1;\r
+\r
+ /* Direct input is not used? */\r
+ if ((ctrlReg & (1UL << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) == 0U)\r
+ {\r
+ /* Decode NDEC value to get (N) pre divider */\r
+ preDiv = pllDecodeN(nDecReg & 0x3FFU);\r
+ if (preDiv == 0U)\r
+ {\r
+ preDiv = 1U;\r
+ }\r
+ }\r
+\r
+ /* Adjusted by 1, directi is used to bypass */\r
+ return preDiv;\r
+}\r
+\r
+/* Get postdivider (P) from PLL PDEC setting */\r
+static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)\r
+{\r
+ uint32_t postDiv = 1U;\r
+\r
+ /* Direct input is not used? */\r
+ if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0U)\r
+ {\r
+ /* Decode PDEC value to get (P) post divider */\r
+ postDiv = 2U * pllDecodeP(pDecReg & 0x7FU);\r
+ if (postDiv == 0U)\r
+ {\r
+ postDiv = 2U;\r
+ }\r
+ }\r
+\r
+ /* Adjusted by 1, directo is used to bypass */\r
+ return postDiv;\r
+}\r
+\r
+/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */\r
+static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)\r
+{\r
+ uint32_t mMult = 1U;\r
+\r
+ /* Decode MDEC value to get (M) multiplier */\r
+ mMult = pllDecodeM(mDecReg & 0x1FFFFU);\r
+\r
+ if (mMult == 0U)\r
+ {\r
+ mMult = 1U;\r
+ }\r
+\r
+ return mMult;\r
+}\r
+\r
+/* Calculate the powerTimes' power of 2 */\r
+static uint32_t power2Cal(uint32_t powerTimes)\r
+{\r
+ uint32_t ret = 1U;\r
+ uint32_t i;\r
+ for (i = 0; i < powerTimes; i++)\r
+ {\r
+ ret *= 2U;\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
+/* Convert the binary to fractional part */\r
+static double Binary2Fractional(uint32_t binaryPart)\r
+{\r
+ double fractional = 0.0;\r
+ for (uint32_t i = 0U; i <= 14U; i++)\r
+ {\r
+ fractional += (double)(uint32_t)((binaryPart >> i) & 0x1U) / (double)(uint32_t)power2Cal(15U - i);\r
+ }\r
+ return fractional;\r
+}\r
+\r
+/* Find greatest common divisor between m and n */\r
+static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n)\r
+{\r
+ uint32_t tmp;\r
+\r
+ while (n != 0U)\r
+ {\r
+ tmp = n;\r
+ n = m % n;\r
+ m = tmp;\r
+ }\r
+\r
+ return m;\r
+}\r
+\r
+/*\r
+ * Set PLL output based on desired output rate.\r
+ * In this function, the it calculates the PLL setting for output frequency from input clock\r
+ * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently.\r
+ * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function.\r
+ */\r
+static pll_error_t CLOCK_GetPllConfigInternal(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup)\r
+{\r
+ uint32_t nDivOutHz, fccoHz, multFccoDiv;\r
+ uint32_t pllPreDivider, pllMultiplier, pllPostDivider;\r
+ uint32_t pllDirectInput, pllDirectOutput;\r
+ uint32_t pllSelP, pllSelI, pllSelR, uplimoff;\r
+\r
+ /* Baseline parameters (no input or output dividers) */\r
+ pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */\r
+ pllPostDivider = 0U; /* 0 implies post-divider will be disabled */\r
+ pllDirectOutput = 1U;\r
+ multFccoDiv = 2U;\r
+\r
+ /* Verify output rate parameter */\r
+ if (foutHz > PLL_MAX_CCO_FREQ_MHZ)\r
+ {\r
+ /* Maximum PLL output with post divider=1 cannot go above this frequency */\r
+ return kStatus_PLL_OutputTooHigh;\r
+ }\r
+ if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U)))\r
+ {\r
+ /* Minmum PLL output with maximum post divider cannot go below this frequency */\r
+ return kStatus_PLL_OutputTooLow;\r
+ }\r
+\r
+ /* Verify input rate parameter */\r
+ if (finHz < PLL_LOWER_IN_LIMIT)\r
+ {\r
+ /* Input clock into the PLL cannot be lower than this */\r
+ return kStatus_PLL_InputTooLow;\r
+ }\r
+\r
+ /* Find the optimal CCO frequency for the output and input that\r
+ will keep it inside the PLL CCO range. This may require\r
+ tweaking the post-divider for the PLL. */\r
+ fccoHz = foutHz;\r
+ while (fccoHz < PLL_MIN_CCO_FREQ_MHZ)\r
+ {\r
+ /* CCO output is less than minimum CCO range, so the CCO output\r
+ needs to be bumped up and the post-divider is used to bring\r
+ the PLL output back down. */\r
+ pllPostDivider++;\r
+ if (pllPostDivider > PVALMAX)\r
+ {\r
+ return kStatus_PLL_OutsideIntLimit;\r
+ }\r
+\r
+ /* Target CCO goes up, PLL output goes down */\r
+ fccoHz = foutHz * (pllPostDivider * 2U);\r
+ pllDirectOutput = 0U;\r
+ }\r
+\r
+ /* Determine if a pre-divider is needed to get the best frequency */\r
+ if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz))\r
+ {\r
+ uint32_t a = FindGreatestCommonDivisor(fccoHz, (multFccoDiv * finHz));\r
+\r
+ if (a > 20000U)\r
+ {\r
+ a = (multFccoDiv * finHz) / a;\r
+ if ((a != 0U) && (a < PLL_MAX_N_DIV))\r
+ {\r
+ pllPreDivider = a;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Bypass pre-divider hardware if pre-divider is 1 */\r
+ if (pllPreDivider > 1U)\r
+ {\r
+ pllDirectInput = 0U;\r
+ }\r
+ else\r
+ {\r
+ pllDirectInput = 1U;\r
+ }\r
+\r
+ /* Determine PLL multipler */\r
+ nDivOutHz = (finHz / pllPreDivider);\r
+ pllMultiplier = (fccoHz / nDivOutHz) / multFccoDiv;\r
+\r
+ /* Find optimal values for filter */\r
+ /* Will bumping up M by 1 get us closer to the desired CCO frequency? */\r
+ if ((nDivOutHz * ((multFccoDiv * pllMultiplier * 2U) + 1U)) < (fccoHz * 2U))\r
+ {\r
+ pllMultiplier++;\r
+ }\r
+\r
+ /* Setup filtering */\r
+ pllFindSel(pllMultiplier, &pllSelP, &pllSelI, &pllSelR);\r
+ uplimoff = 0U;\r
+\r
+ /* Get encoded value for M (mult) and use manual filter, disable SS mode */\r
+ pSetup->pllmdec = PLL_MDEC_VAL_SET(pllEncodeM(pllMultiplier));\r
+\r
+ /* Get encoded values for N (prediv) and P (postdiv) */\r
+ pSetup->pllndec = PLL_NDEC_VAL_SET(pllEncodeN(pllPreDivider));\r
+ pSetup->pllpdec = PLL_PDEC_VAL_SET(pllEncodeP(pllPostDivider));\r
+\r
+ /* PLL control */\r
+ pSetup->pllctrl = (pllSelR << SYSCON_SYSPLLCTRL_SELR_SHIFT) | /* Filter coefficient */\r
+ (pllSelI << SYSCON_SYSPLLCTRL_SELI_SHIFT) | /* Filter coefficient */\r
+ (pllSelP << SYSCON_SYSPLLCTRL_SELP_SHIFT) | /* Filter coefficient */\r
+ (0UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT) | /* PLL bypass mode disabled */\r
+ (uplimoff << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT) | /* SS/fractional mode disabled */\r
+ (pllDirectInput << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT) | /* Bypass pre-divider? */\r
+ (pllDirectOutput << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT); /* Bypass post-divider? */\r
+\r
+ return kStatus_PLL_Success;\r
+}\r
+\r
+#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)\r
+/* Alloct the static buffer for cache. */\r
+static pll_setup_t gPllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT];\r
+static uint32_t gFinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0};\r
+static uint32_t gFoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0};\r
+static uint32_t gPllSetupCacheIdx = 0U;\r
+#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */\r
+\r
+/*\r
+ * Calculate the PLL setting values from input clock freq to output freq.\r
+ */\r
+static pll_error_t CLOCK_GetPllConfig(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup)\r
+{\r
+ pll_error_t retErr;\r
+#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)\r
+ uint32_t i;\r
+\r
+ for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++)\r
+ {\r
+ if ((finHz == gFinHzCache[i]) && (foutHz == gFoutHzCache[i]))\r
+ {\r
+ /* Hit the target in cache buffer. */\r
+ pSetup->pllctrl = gPllSetupCacheStruct[i].pllctrl;\r
+ pSetup->pllndec = gPllSetupCacheStruct[i].pllndec;\r
+ pSetup->pllpdec = gPllSetupCacheStruct[i].pllpdec;\r
+ pSetup->pllmdec = gPllSetupCacheStruct[i].pllmdec;\r
+ retErr = kStatus_PLL_Success;\r
+ break;\r
+ }\r
+ }\r
+\r
+ if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)\r
+ {\r
+ return retErr;\r
+ }\r
+#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */\r
+\r
+ /* No cache or did not hit the cache. */\r
+ retErr = CLOCK_GetPllConfigInternal(finHz, foutHz, pSetup);\r
+\r
+#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)\r
+ if (kStatus_PLL_Success == retErr)\r
+ {\r
+ /* Cache the most recent calulation result into buffer. */\r
+ gFinHzCache[gPllSetupCacheIdx] = finHz;\r
+ gFoutHzCache[gPllSetupCacheIdx] = foutHz;\r
+\r
+ gPllSetupCacheStruct[gPllSetupCacheIdx].pllctrl = pSetup->pllctrl;\r
+ gPllSetupCacheStruct[gPllSetupCacheIdx].pllndec = pSetup->pllndec;\r
+ gPllSetupCacheStruct[gPllSetupCacheIdx].pllpdec = pSetup->pllpdec;\r
+ gPllSetupCacheStruct[gPllSetupCacheIdx].pllmdec = pSetup->pllmdec;\r
+ /* Update the index for next available buffer. */\r
+ gPllSetupCacheIdx = (gPllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT;\r
+ }\r
+#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */\r
+\r
+ return retErr;\r
+}\r
+\r
+/* Update SYSTEM PLL rate variable */\r
+static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup)\r
+{\r
+ s_Pll_Freq = CLOCK_GetSystemPLLOutFromSetup(pSetup);\r
+}\r
+\r
+/* Update AUDIO PLL rate variable */\r
+static void CLOCK_GetAudioPLLOutFromSetupUpdate(pll_setup_t *pSetup)\r
+{\r
+ s_Audio_Pll_Freq = CLOCK_GetAudioPLLOutFromSetup(pSetup);\r
+}\r
+\r
+/* Update AUDIO Fractional PLL rate variable */\r
+static void CLOCK_GetAudioPLLOutFromAudioFracSetupUpdate(pll_setup_t *pSetup)\r
+{\r
+ s_Audio_Pll_Freq = CLOCK_GetAudioPLLOutFromFractSetup(pSetup);\r
+}\r
+\r
+/* Update USB PLL rate variable */\r
+static void CLOCK_GetUsbPLLOutFromSetupUpdate(const usb_pll_setup_t *pSetup)\r
+{\r
+ s_Usb_Pll_Freq = CLOCK_GetUsbPLLOutFromSetup(pSetup);\r
+}\r
+\r
+/* Return System PLL input clock rate */\r
+/*! brief Return System PLL input clock rate\r
+ * return System PLL input clock rate\r
+ */\r
+uint32_t CLOCK_GetSystemPLLInClockRate(void)\r
+{\r
+ uint32_t clkRate = 0U;\r
+\r
+ switch ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK))\r
+ {\r
+ case 0x00U:\r
+ clkRate = CLK_FRO_12MHZ;\r
+ break;\r
+\r
+ case 0x01U:\r
+ clkRate = CLOCK_GetExtClkFreq();\r
+ break;\r
+\r
+ case 0x02U:\r
+ clkRate = CLOCK_GetWdtOscFreq();\r
+ break;\r
+\r
+ case 0x03U:\r
+ clkRate = CLOCK_GetOsc32KFreq();\r
+ break;\r
+\r
+ default:\r
+ clkRate = 0U;\r
+ break;\r
+ }\r
+\r
+ return clkRate;\r
+}\r
+\r
+/* Return Audio PLL input clock rate */\r
+/*! brief Return Audio PLL input clock rate\r
+ * return Audio PLL input clock rate\r
+ */\r
+uint32_t CLOCK_GetAudioPLLInClockRate(void)\r
+{\r
+ uint32_t clkRate = 0U;\r
+\r
+ switch ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK))\r
+ {\r
+ case 0x00U:\r
+ clkRate = CLK_FRO_12MHZ;\r
+ break;\r
+\r
+ case 0x01U:\r
+ clkRate = CLOCK_GetExtClkFreq();\r
+ break;\r
+\r
+ default:\r
+ clkRate = 0U;\r
+ break;\r
+ }\r
+\r
+ return clkRate;\r
+}\r
+\r
+/* Return System PLL output clock rate from setup structure */\r
+/*! brief Return System PLL output clock rate from setup structure\r
+ * param pSetup : Pointer to a PLL setup structure\r
+ * return System PLL output clock rate the setup structure will generate\r
+ */\r
+uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup)\r
+{\r
+ uint32_t prediv, postdiv, mMult, inPllRate;\r
+ uint64_t workRate;\r
+\r
+ inPllRate = CLOCK_GetSystemPLLInClockRate();\r
+ /* If the PLL is bypassed, PLL would not be used and the output of PLL module would just be the input clock*/\r
+ if ((pSetup->pllctrl & (SYSCON_SYSPLLCTRL_BYPASS_MASK)) == 0U)\r
+ {\r
+ /* PLL is not in bypass mode, get pre-divider, and M divider, post-divider. */\r
+ /*\r
+ * 1. Pre-divider\r
+ * Pre-divider is only available when the DIRECTI is disabled.\r
+ */\r
+ if (0U == (pSetup->pllctrl & SYSCON_SYSPLLCTRL_DIRECTI_MASK))\r
+ {\r
+ prediv = findPllPreDiv(pSetup->pllctrl, pSetup->pllndec);\r
+ }\r
+ else\r
+ {\r
+ prediv = 1U; /* The pre-divider is bypassed. */\r
+ }\r
+ /*\r
+ * 2. Post-divider\r
+ * Post-divider is only available when the DIRECTO is disabled.\r
+ */\r
+ if (0U == (pSetup->pllctrl & SYSCON_SYSPLLCTRL_DIRECTO_MASK))\r
+ {\r
+ postdiv = findPllPostDiv(pSetup->pllctrl, pSetup->pllpdec);\r
+ }\r
+ else\r
+ {\r
+ postdiv = 1U; /* The post-divider is bypassed. */\r
+ }\r
+ /* Adjust input clock */\r
+ inPllRate = inPllRate / prediv;\r
+\r
+ /* MDEC used for rate */\r
+ mMult = findPllMMult(pSetup->pllctrl, pSetup->pllmdec);\r
+ workRate = (uint64_t)inPllRate * (uint64_t)mMult;\r
+\r
+ workRate = workRate / ((uint64_t)postdiv);\r
+ workRate = workRate * 2U; /* SYS PLL hardware cco is divide by 2 before to M-DIVIDER*/\r
+ }\r
+ else\r
+ {\r
+ /* In bypass mode */\r
+ workRate = (uint64_t)inPllRate;\r
+ }\r
+\r
+ return (uint32_t)workRate;\r
+}\r
+\r
+/* Return Usb PLL output clock rate from setup structure */\r
+/*! brief Return System USB PLL output clock rate from setup structure\r
+ * param pSetup : Pointer to a PLL setup structure\r
+ * return System PLL output clock rate the setup structure will generate\r
+ */\r
+uint32_t CLOCK_GetUsbPLLOutFromSetup(const usb_pll_setup_t *pSetup)\r
+{\r
+ uint32_t nsel, psel, msel, inPllRate;\r
+ uint64_t workRate;\r
+ inPllRate = CLOCK_GetExtClkFreq();\r
+ msel = pSetup->msel;\r
+ psel = pSetup->psel;\r
+ nsel = pSetup->nsel;\r
+\r
+ /* Make sure the PSEL is correct. */\r
+ if (0U == SWITCH_USB_PSEL(psel))\r
+ {\r
+ return 0UL;\r
+ }\r
+\r
+ if (pSetup->fbsel)\r
+ {\r
+ /*integer_mode: Fout = M*(Fin/N), Fcco = 2*P*M*(Fin/N) */\r
+ workRate = ((uint64_t)inPllRate) * ((uint64_t)msel + 1U) / ((uint64_t)nsel + 1U);\r
+ }\r
+ else\r
+ {\r
+ /* non integer_mode: Fout = M*(Fin/N)/(2*P), Fcco = M * (Fin/N) */\r
+ workRate = ((uint64_t)inPllRate / ((uint64_t)nsel + 1U)) * (msel + 1U) / (2U * SWITCH_USB_PSEL(psel));\r
+ }\r
+\r
+ return (uint32_t)workRate;\r
+}\r
+\r
+/* Return Audio PLL output clock rate from setup structure */\r
+/*! brief Return System AUDIO PLL output clock rate from setup structure\r
+ * param pSetup : Pointer to a PLL setup structure\r
+ * return System PLL output clock rate the setup structure will generate\r
+ */\r
+uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup)\r
+{\r
+ uint32_t prediv, postdiv, mMult, inPllRate;\r
+ uint64_t workRate;\r
+\r
+ inPllRate = CLOCK_GetAudioPLLInClockRate();\r
+ if ((pSetup->pllctrl & (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) == 0U)\r
+ {\r
+ /* PLL is not in bypass mode, get pre-divider, and M divider, post-divider. */\r
+ /*\r
+ * 1. Pre-divider\r
+ * Pre-divider is only available when the DIRECTI is disabled.\r
+ */\r
+ if (0U == (pSetup->pllctrl & SYSCON_AUDPLLCTRL_DIRECTI_MASK))\r
+ {\r
+ prediv = findPllPreDiv(pSetup->pllctrl, pSetup->pllndec);\r
+ }\r
+ else\r
+ {\r
+ prediv = 1U; /* The pre-divider is bypassed. */\r
+ }\r
+ /*\r
+ * 2. Post-divider\r
+ * Post-divider is only available when the DIRECTO is disabled.\r
+ */\r
+ if (0U == (pSetup->pllctrl & SYSCON_AUDPLLCTRL_DIRECTO_MASK))\r
+ {\r
+ postdiv = findPllPostDiv(pSetup->pllctrl, pSetup->pllpdec);\r
+ }\r
+ else\r
+ {\r
+ postdiv = 1U; /* The post-divider is bypassed. */\r
+ }\r
+ /* Adjust input clock */\r
+ inPllRate = inPllRate / prediv;\r
+\r
+ /* MDEC used for rate */\r
+ mMult = findPllMMult(pSetup->pllctrl, pSetup->pllmdec);\r
+ workRate = (uint64_t)inPllRate * (uint64_t)mMult;\r
+\r
+ workRate = workRate / ((uint64_t)postdiv);\r
+ workRate = workRate * 2U; /* SYS PLL hardware cco is divide by 2 before to M-DIVIDER*/\r
+ }\r
+ else\r
+ {\r
+ /* In bypass mode */\r
+ workRate = (uint64_t)inPllRate;\r
+ }\r
+\r
+ return (uint32_t)workRate;\r
+}\r
+\r
+/* Return Audio PLL output clock rate from audio fractioanl setup structure */\r
+/*! brief Return System AUDIO PLL output clock rate from audio fractioanl setup structure\r
+ * param pSetup : Pointer to a PLL setup structure\r
+ * return System PLL output clock rate the setup structure will generate\r
+ */\r
+uint32_t CLOCK_GetAudioPLLOutFromFractSetup(pll_setup_t *pSetup)\r
+{\r
+ uint32_t prediv, postdiv, inPllRate;\r
+ double workRate, mMultFactional;\r
+\r
+ inPllRate = CLOCK_GetAudioPLLInClockRate();\r
+ if ((pSetup->pllctrl & (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) == 0U)\r
+ {\r
+ /* PLL is not in bypass mode, get pre-divider, and M divider, post-divider. */\r
+ /*\r
+ * 1. Pre-divider\r
+ * Pre-divider is only available when the DIRECTI is disabled.\r
+ */\r
+ if (0U == (pSetup->pllctrl & SYSCON_AUDPLLCTRL_DIRECTI_MASK))\r
+ {\r
+ prediv = findPllPreDiv(pSetup->pllctrl, pSetup->pllndec);\r
+ }\r
+ else\r
+ {\r
+ prediv = 1U; /* The pre-divider is bypassed. */\r
+ }\r
+ /*\r
+ * 2. Post-divider\r
+ * Post-divider is only available when the DIRECTO is disabled.\r
+ */\r
+ if (0U == (pSetup->pllctrl & SYSCON_AUDPLLCTRL_DIRECTO_MASK))\r
+ {\r
+ postdiv = findPllPostDiv(pSetup->pllctrl, pSetup->pllpdec);\r
+ }\r
+ else\r
+ {\r
+ postdiv = 1U; /* The post-divider is bypassed. */\r
+ }\r
+ /* Adjust input clock */\r
+ inPllRate = inPllRate / prediv;\r
+\r
+ mMultFactional = (double)(uint32_t)(pSetup->audpllfrac >> 15) +\r
+ (double)(uint32_t)Binary2Fractional(pSetup->audpllfrac & 0x7FFFU);\r
+ workRate = (double)inPllRate * (double)mMultFactional;\r
+\r
+ workRate = workRate / ((double)postdiv);\r
+ workRate = workRate * 2.0; /* SYS PLL hardware cco is divide by 2 before to M-DIVIDER*/\r
+ }\r
+ else\r
+ {\r
+ /* In bypass mode */\r
+ workRate = (double)(uint64_t)inPllRate;\r
+ }\r
+\r
+ return (uint32_t)workRate;\r
+}\r
+\r
+/* Set the current PLL Rate */\r
+/*! brief Store the current PLL rate\r
+ * param rate: Current rate of the PLL\r
+ * return Nothing\r
+ **/\r
+void CLOCK_SetStoredPLLClockRate(uint32_t rate)\r
+{\r
+ s_Pll_Freq = rate;\r
+}\r
+\r
+/* Set the current Audio PLL Rate */\r
+/*! brief Store the current AUDIO PLL rate\r
+ * param rate: Current rate of the PLL\r
+ * return Nothing\r
+ **/\r
+void CLOCK_SetStoredAudioPLLClockRate(uint32_t rate)\r
+{\r
+ s_Audio_Pll_Freq = rate;\r
+}\r
+\r
+/* Set the current Usb PLL Rate */\r
+void CLOCK_SetStoredUsbPLLClockRate(uint32_t rate)\r
+{\r
+ s_Usb_Pll_Freq = rate;\r
+}\r
+\r
+/* Return System PLL output clock rate */\r
+/*! brief Return System PLL output clock rate\r
+ * param recompute : Forces a PLL rate recomputation if true\r
+ * return System PLL output clock rate\r
+ * note The PLL rate is cached in the driver in a variable as\r
+ * the rate computation function can take some time to perform. It\r
+ * is recommended to use 'false' with the 'recompute' parameter.\r
+ */\r
+uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute)\r
+{\r
+ pll_setup_t Setup;\r
+ uint32_t rate;\r
+\r
+ if ((recompute) || (s_Pll_Freq == 0U))\r
+ {\r
+ Setup.pllctrl = SYSCON->SYSPLLCTRL;\r
+ Setup.pllndec = SYSCON->SYSPLLNDEC;\r
+ Setup.pllpdec = SYSCON->SYSPLLPDEC;\r
+ Setup.pllmdec = SYSCON->SYSPLLMDEC;\r
+\r
+ CLOCK_GetSystemPLLOutFromSetupUpdate(&Setup);\r
+ }\r
+\r
+ rate = s_Pll_Freq;\r
+\r
+ return rate;\r
+}\r
+\r
+/* Return AUDIO PLL output clock rate */\r
+/*! brief Return System AUDIO PLL output clock rate\r
+ * param recompute : Forces a AUDIO PLL rate recomputation if true\r
+ * return System AUDIO PLL output clock rate\r
+ * note The AUDIO PLL rate is cached in the driver in a variable as\r
+ * the rate computation function can take some time to perform. It\r
+ * is recommended to use 'false' with the 'recompute' parameter.\r
+ */\r
+uint32_t CLOCK_GetAudioPLLOutClockRate(bool recompute)\r
+{\r
+ pll_setup_t Setup;\r
+ uint32_t rate;\r
+\r
+ if ((recompute) || (s_Audio_Pll_Freq == 0U))\r
+ {\r
+ Setup.pllctrl = SYSCON->AUDPLLCTRL;\r
+ Setup.pllndec = SYSCON->AUDPLLNDEC;\r
+ Setup.pllpdec = SYSCON->AUDPLLPDEC;\r
+ Setup.pllmdec = SYSCON->AUDPLLMDEC;\r
+\r
+ CLOCK_GetAudioPLLOutFromSetupUpdate(&Setup);\r
+ }\r
+\r
+ rate = s_Audio_Pll_Freq;\r
+ return rate;\r
+}\r
+\r
+/* Return USB PLL output clock rate */\r
+uint32_t CLOCK_GetUsbPLLOutClockRate(bool recompute)\r
+{\r
+ usb_pll_setup_t Setup;\r
+ uint32_t rate;\r
+\r
+ if ((recompute) || (s_Usb_Pll_Freq == 0U))\r
+ {\r
+ Setup.msel = (uint8_t)((SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_MSEL_SHIFT) & SYSCON_USBPLLCTRL_MSEL_MASK);\r
+ Setup.psel = (uint8_t)((SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_PSEL_SHIFT) & SYSCON_USBPLLCTRL_PSEL_MASK);\r
+ Setup.nsel = (uint8_t)((SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_NSEL_SHIFT) & SYSCON_USBPLLCTRL_NSEL_MASK);\r
+ Setup.fbsel = (((SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_FBSEL_SHIFT) & SYSCON_USBPLLCTRL_FBSEL_MASK) != 0UL);\r
+ Setup.bypass =\r
+ (((SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_BYPASS_SHIFT) & SYSCON_USBPLLCTRL_BYPASS_MASK) != 0UL);\r
+ Setup.direct =\r
+ (((SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_DIRECT_SHIFT) & SYSCON_USBPLLCTRL_DIRECT_MASK) != 0UL);\r
+ CLOCK_GetUsbPLLOutFromSetupUpdate(&Setup);\r
+ }\r
+\r
+ rate = s_Usb_Pll_Freq;\r
+ return rate;\r
+}\r
+\r
+/* Set PLL output based on the passed PLL setup data */\r
+/*! brief Set PLL output based on the passed PLL setup data\r
+ * param pControl : Pointer to populated PLL control structure to generate setup with\r
+ * param pSetup : Pointer to PLL setup structure to be filled\r
+ * return PLL_ERROR_SUCCESS on success, or PLL setup error code\r
+ * note Actual frequency for setup may vary from the desired frequency based on the\r
+ * accuracy of input clocks, rounding, non-fractional PLL mode, etc.\r
+ */\r
+pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup)\r
+{\r
+ uint32_t inRate;\r
+ pll_error_t pllError;\r
+\r
+ /* Determine input rate for the PLL */\r
+ if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U)\r
+ {\r
+ inRate = pControl->inputRate;\r
+ }\r
+ else\r
+ {\r
+ inRate = CLOCK_GetSystemPLLInClockRate();\r
+ }\r
+\r
+ /* PLL flag options */\r
+ pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup);\r
+ pSetup->pllRate = pControl->desiredRate;\r
+ return pllError;\r
+}\r
+\r
+/* Set PLL output from PLL setup structure */\r
+/*! brief Set PLL output from PLL setup structure (precise frequency)\r
+ * param pSetup : Pointer to populated PLL setup structure\r
+ * param flagcfg : Flag configuration for PLL config structure\r
+ * return PLL_ERROR_SUCCESS on success, or PLL setup error code\r
+ * note This function will power off the PLL, setup the PLL with the\r
+ * new setup data, and then optionally powerup the PLL, wait for PLL lock,\r
+ * and adjust system voltages to the new PLL rate. The function will not\r
+ * alter any source clocks (ie, main systen clock) that may use the PLL,\r
+ * so these should be setup prior to and after exiting the function.\r
+ */\r
+pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg)\r
+{\r
+ if ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) == 0x01U)\r
+ {\r
+ /* Turn on the ext clock if system pll input select clk_in */\r
+ CLOCK_Enable_SysOsc(true);\r
+ }\r
+ /* Enable power for PLLs */\r
+ POWER_SetPLL();\r
+ /* Power off PLL during setup changes */\r
+ POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0);\r
+\r
+ pSetup->flags = flagcfg;\r
+\r
+ /* Write PLL setup data */\r
+ SYSCON->SYSPLLCTRL = pSetup->pllctrl;\r
+ SYSCON->SYSPLLNDEC = pSetup->pllndec;\r
+ SYSCON->SYSPLLNDEC = pSetup->pllndec | (1UL << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */\r
+ SYSCON->SYSPLLPDEC = pSetup->pllpdec;\r
+ SYSCON->SYSPLLPDEC = pSetup->pllpdec | (1UL << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */\r
+ SYSCON->SYSPLLMDEC = pSetup->pllmdec;\r
+ SYSCON->SYSPLLMDEC = pSetup->pllmdec | (1UL << SYSCON_SYSPLLMDEC_MREQ_SHIFT); /* latch */\r
+\r
+ /* Flags for lock or power on */\r
+ if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U)\r
+ {\r
+ /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */\r
+ uint32_t maxCCO = (1UL << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/\r
+ uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1UL << 17U);\r
+\r
+ /* Initialize and power up PLL */\r
+ SYSCON->SYSPLLMDEC = maxCCO;\r
+ POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0);\r
+\r
+ /* Set mreq to activate */\r
+ SYSCON->SYSPLLMDEC = maxCCO | (1UL << 17U);\r
+\r
+ /* Delay for 72 uSec @ 12Mhz */\r
+ SDK_DelayAtLeastUs(72U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);\r
+\r
+ /* clear mreq to prepare for restoring mreq */\r
+ SYSCON->SYSPLLMDEC = curSSCTRL;\r
+\r
+ /* set original value back and activate */\r
+ SYSCON->SYSPLLMDEC = curSSCTRL | (1UL << 17U);\r
+\r
+ /* Enable peripheral states by setting low */\r
+ POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0);\r
+ }\r
+ if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)\r
+ {\r
+ while (CLOCK_IsSystemPLLLocked() == false)\r
+ {\r
+ }\r
+ }\r
+\r
+ /* Update current programmed PLL rate var */\r
+ CLOCK_GetSystemPLLOutFromSetupUpdate(pSetup);\r
+\r
+ /* System voltage adjustment, occurs prior to setting main system clock */\r
+ if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0U)\r
+ {\r
+ POWER_SetVoltageForFreq(s_Pll_Freq);\r
+ }\r
+\r
+ return kStatus_PLL_Success;\r
+}\r
+\r
+/* Set AUDIO PLL output from AUDIO PLL setup structure */\r
+/*! brief Set AUDIO PLL output from AUDIOPLL setup structure (precise frequency)\r
+ * param pSetup : Pointer to populated PLL setup structure\r
+ * param flagcfg : Flag configuration for PLL config structure\r
+ * return PLL_ERROR_SUCCESS on success, or PLL setup error code\r
+ * note This function will power off the PLL, setup the PLL with the\r
+ * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,\r
+ * and adjust system voltages to the new AUDIOPLL rate. The function will not\r
+ * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,\r
+ * so these should be setup prior to and after exiting the function.\r
+ */\r
+pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg)\r
+{\r
+ if ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK) == 0x01U)\r
+ {\r
+ /* Turn on the ext clock if system pll input select clk_in */\r
+ CLOCK_Enable_SysOsc(true);\r
+ }\r
+ /* Enable power VD3 for PLLs */\r
+ POWER_SetPLL();\r
+ /* Power off PLL during setup changes */\r
+ POWER_EnablePD(kPDRUNCFG_PD_AUDIO_PLL);\r
+\r
+ pSetup->flags = flagcfg;\r
+\r
+ /* Write PLL setup data */\r
+ SYSCON->AUDPLLCTRL = pSetup->pllctrl;\r
+ SYSCON->AUDPLLNDEC = pSetup->pllndec;\r
+ SYSCON->AUDPLLNDEC = pSetup->pllndec | (1UL << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */\r
+ SYSCON->AUDPLLPDEC = pSetup->pllpdec;\r
+ SYSCON->AUDPLLPDEC = pSetup->pllpdec | (1UL << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */\r
+ SYSCON->AUDPLLMDEC = pSetup->pllmdec;\r
+ SYSCON->AUDPLLMDEC = pSetup->pllmdec | (1UL << SYSCON_SYSPLLMDEC_MREQ_SHIFT); /* latch */\r
+ SYSCON->AUDPLLFRAC = SYSCON_AUDPLLFRAC_SEL_EXT(1); /* disable fractional function */\r
+\r
+ /* Flags for lock or power on */\r
+ if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U)\r
+ {\r
+ /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */\r
+ uint32_t maxCCO = (1UL << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/\r
+ uint32_t curSSCTRL = SYSCON->AUDPLLMDEC & ~(1UL << 17U);\r
+\r
+ /* Initialize and power up PLL */\r
+ SYSCON->AUDPLLMDEC = maxCCO;\r
+ POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);\r
+\r
+ /* Set mreq to activate */\r
+ SYSCON->AUDPLLMDEC = maxCCO | (1UL << 17U);\r
+\r
+ /* Delay for 72 uSec @ 12Mhz */\r
+ SDK_DelayAtLeastUs(72U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);\r
+\r
+ /* clear mreq to prepare for restoring mreq */\r
+ SYSCON->AUDPLLMDEC = curSSCTRL;\r
+\r
+ /* set original value back and activate */\r
+ SYSCON->AUDPLLMDEC = curSSCTRL | (1UL << 17U);\r
+\r
+ /* Enable peripheral states by setting low */\r
+ POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);\r
+ }\r
+ if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)\r
+ {\r
+ while (CLOCK_IsAudioPLLLocked() == false)\r
+ {\r
+ }\r
+ }\r
+\r
+ /* Update current programmed PLL rate var */\r
+ CLOCK_GetAudioPLLOutFromSetupUpdate(pSetup);\r
+\r
+ return kStatus_PLL_Success;\r
+}\r
+\r
+/* Set AUDIO PLL output from AUDIO PLL fractional setup structure */\r
+/*! brief Set AUDIO PLL output from AUDIOPLL setup structure using the Audio Fractional divider register(precise\r
+ * frequency)\r
+ * param pSetup : Pointer to populated PLL setup structure\r
+ * param flagcfg : Flag configuration for PLL config structure\r
+ * return PLL_ERROR_SUCCESS on success, or PLL setup error code\r
+ * note This function will power off the PLL, setup the PLL with the\r
+ * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,\r
+ * and adjust system voltages to the new AUDIOPLL rate. The function will not\r
+ * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,\r
+ * so these should be setup prior to and after exiting the function.\r
+ */\r
+pll_error_t CLOCK_SetupAudioPLLPrecFract(pll_setup_t *pSetup, uint32_t flagcfg)\r
+{\r
+ if ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK) == 0x01U)\r
+ {\r
+ /* Turn on the ext clock if system pll input select clk_in */\r
+ CLOCK_Enable_SysOsc(true);\r
+ }\r
+ /* Enable power VD3 for PLLs */\r
+ POWER_SetPLL();\r
+ /* Power off PLL during setup changes */\r
+ POWER_EnablePD(kPDRUNCFG_PD_AUDIO_PLL);\r
+\r
+ pSetup->flags = flagcfg;\r
+\r
+ /* Write PLL setup data */\r
+ SYSCON->AUDPLLCTRL = pSetup->pllctrl;\r
+ SYSCON->AUDPLLNDEC = pSetup->pllndec;\r
+ SYSCON->AUDPLLNDEC = pSetup->pllndec | (1UL << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */\r
+ SYSCON->AUDPLLPDEC = pSetup->pllpdec;\r
+ SYSCON->AUDPLLPDEC = pSetup->pllpdec | (1UL << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */\r
+ SYSCON->AUDPLLMDEC = pSetup->pllmdec;\r
+ SYSCON->AUDPLLFRAC = SYSCON_AUDPLLFRAC_SEL_EXT(0); /* enable fractional function */\r
+ SYSCON->AUDPLLFRAC = pSetup->audpllfrac;\r
+ SYSCON->AUDPLLFRAC = pSetup->audpllfrac | (1UL << SYSCON_AUDPLLFRAC_REQ_SHIFT);\r
+\r
+ /* Enable peripheral states by setting low */\r
+ POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);\r
+\r
+ if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)\r
+ {\r
+ while (CLOCK_IsAudioPLLLocked() == false)\r
+ {\r
+ }\r
+ }\r
+\r
+ /* Update current programmed PLL rate var */\r
+ CLOCK_GetAudioPLLOutFromAudioFracSetupUpdate(pSetup);\r
+\r
+ return kStatus_PLL_Success;\r
+}\r
+\r
+/* Set Audio PLL output based on the passed Audio PLL setup data */\r
+/*! brief Set AUDIO PLL output based on the passed AUDIO PLL setup data\r
+ * param pControl : Pointer to populated PLL control structure to generate setup with\r
+ * param pSetup : Pointer to PLL setup structure to be filled\r
+ * return PLL_ERROR_SUCCESS on success, or PLL setup error code\r
+ * note Actual frequency for setup may vary from the desired frequency based on the\r
+ * accuracy of input clocks, rounding, non-fractional PLL mode, etc.\r
+ */\r
+pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup)\r
+{\r
+ uint32_t inRate;\r
+ pll_error_t pllError;\r
+\r
+ /* Determine input rate for the PLL */\r
+ if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U)\r
+ {\r
+ inRate = pControl->inputRate;\r
+ }\r
+ else\r
+ {\r
+ inRate = CLOCK_GetAudioPLLInClockRate();\r
+ }\r
+\r
+ /* PLL flag options */\r
+ pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup);\r
+ pSetup->pllRate = pControl->desiredRate;\r
+ return pllError;\r
+}\r
+\r
+/* Setup PLL Frequency from pre-calculated value */\r
+/**\r
+ * brief Set PLL output from PLL setup structure (precise frequency)\r
+ * param pSetup : Pointer to populated PLL setup structure\r
+ * return kStatus_PLL_Success on success, or PLL setup error code\r
+ * note This function will power off the PLL, setup the PLL with the\r
+ * new setup data, and then optionally powerup the PLL, wait for PLL lock,\r
+ * and adjust system voltages to the new PLL rate. The function will not\r
+ * alter any source clocks (ie, main systen clock) that may use the PLL,\r
+ * so these should be setup prior to and after exiting the function.\r
+ */\r
+pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup)\r
+{\r
+ if ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) == 0x01U)\r
+ {\r
+ /* Turn on the ext clock if system pll input select clk_in */\r
+ CLOCK_Enable_SysOsc(true);\r
+ }\r
+ /* Enable power VD3 for PLLs */\r
+ POWER_SetPLL();\r
+ /* Power off PLL during setup changes */\r
+ POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0);\r
+\r
+ /* Write PLL setup data */\r
+ SYSCON->SYSPLLCTRL = pSetup->pllctrl;\r
+ SYSCON->SYSPLLNDEC = pSetup->pllndec;\r
+ SYSCON->SYSPLLNDEC = pSetup->pllndec | (1UL << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */\r
+ SYSCON->SYSPLLPDEC = pSetup->pllpdec;\r
+ SYSCON->SYSPLLPDEC = pSetup->pllpdec | (1UL << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */\r
+ SYSCON->SYSPLLMDEC = pSetup->pllmdec;\r
+ SYSCON->SYSPLLMDEC = pSetup->pllmdec | (1UL << SYSCON_SYSPLLMDEC_MREQ_SHIFT); /* latch */\r
+\r
+ /* Flags for lock or power on */\r
+ if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U)\r
+ {\r
+ /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */\r
+ uint32_t maxCCO = (1UL << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/\r
+ uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1UL << 17U);\r
+\r
+ /* Initialize and power up PLL */\r
+ SYSCON->SYSPLLMDEC = maxCCO;\r
+ POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0);\r
+\r
+ /* Set mreq to activate */\r
+ SYSCON->SYSPLLMDEC = maxCCO | (1UL << 17U);\r
+\r
+ /* Delay for 72 uSec @ 12Mhz */\r
+ SDK_DelayAtLeastUs(72U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);\r
+\r
+ /* clear mreq to prepare for restoring mreq */\r
+ SYSCON->SYSPLLMDEC = curSSCTRL;\r
+\r
+ /* set original value back and activate */\r
+ SYSCON->SYSPLLMDEC = curSSCTRL | (1UL << 17U);\r
+\r
+ /* Enable peripheral states by setting low */\r
+ POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0);\r
+ }\r
+ if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)\r
+ {\r
+ while (CLOCK_IsSystemPLLLocked() == false)\r
+ {\r
+ }\r
+ }\r
+\r
+ /* Update current programmed PLL rate var */\r
+ s_Pll_Freq = pSetup->pllRate;\r
+\r
+ return kStatus_PLL_Success;\r
+}\r
+\r
+/* Setup Audio PLL Frequency from pre-calculated value */\r
+/**\r
+ * brief Set Audio PLL output from Audio PLL setup structure (precise frequency)\r
+ * param pSetup : Pointer to populated PLL setup structure\r
+ * return kStatus_PLL_Success on success, or Audio PLL setup error code\r
+ * note This function will power off the PLL, setup the Audio PLL with the\r
+ * new setup data, and then optionally powerup the PLL, wait for Audio PLL lock,\r
+ * and adjust system voltages to the new PLL rate. The function will not\r
+ * alter any source clocks (ie, main systen clock) that may use the Audio PLL,\r
+ * so these should be setup prior to and after exiting the function.\r
+ */\r
+pll_error_t CLOCK_SetAudioPLLFreq(const pll_setup_t *pSetup)\r
+{\r
+ if ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK) == 0x01U)\r
+ {\r
+ /* Turn on the ext clock if system pll input select clk_in */\r
+ CLOCK_Enable_SysOsc(true);\r
+ }\r
+ /* Enable power VD3 for PLLs */\r
+ POWER_SetPLL();\r
+ /* Power off Audio PLL during setup changes */\r
+ POWER_EnablePD(kPDRUNCFG_PD_AUDIO_PLL);\r
+\r
+ /* Write Audio PLL setup data */\r
+ SYSCON->AUDPLLCTRL = pSetup->pllctrl;\r
+ SYSCON->AUDPLLFRAC = pSetup->audpllfrac;\r
+ SYSCON->AUDPLLFRAC = pSetup->audpllfrac | (1UL << SYSCON_AUDPLLFRAC_REQ_SHIFT); /* latch */\r
+ SYSCON->AUDPLLNDEC = pSetup->pllndec;\r
+ SYSCON->AUDPLLNDEC = pSetup->pllndec | (1UL << SYSCON_AUDPLLNDEC_NREQ_SHIFT); /* latch */\r
+ SYSCON->AUDPLLPDEC = pSetup->pllpdec;\r
+ SYSCON->AUDPLLPDEC = pSetup->pllpdec | (1UL << SYSCON_AUDPLLPDEC_PREQ_SHIFT); /* latch */\r
+ SYSCON->AUDPLLMDEC = pSetup->pllmdec;\r
+ SYSCON->AUDPLLMDEC = pSetup->pllmdec | (1UL << SYSCON_AUDPLLMDEC_MREQ_SHIFT); /* latch */\r
+ SYSCON->AUDPLLFRAC = SYSCON_AUDPLLFRAC_SEL_EXT(1); /* disable fractional function */\r
+\r
+ /* Flags for lock or power on */\r
+ if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U)\r
+ {\r
+ /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */\r
+ uint32_t maxCCO = (1UL << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/\r
+ uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1UL << 17U);\r
+\r
+ /* Initialize and power up PLL */\r
+ SYSCON->SYSPLLMDEC = maxCCO;\r
+ POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);\r
+\r
+ /* Set mreq to activate */\r
+ SYSCON->SYSPLLMDEC = maxCCO | (1UL << 17U);\r
+\r
+ /* Delay for 72 uSec @ 12Mhz */\r
+ SDK_DelayAtLeastUs(72U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);\r
+\r
+ /* clear mreq to prepare for restoring mreq */\r
+ SYSCON->SYSPLLMDEC = curSSCTRL;\r
+\r
+ /* set original value back and activate */\r
+ SYSCON->SYSPLLMDEC = curSSCTRL | (1UL << 17U);\r
+\r
+ /* Enable peripheral states by setting low */\r
+ POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);\r
+ }\r
+ if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)\r
+ {\r
+ while (CLOCK_IsAudioPLLLocked() == false)\r
+ {\r
+ }\r
+ }\r
+\r
+ /* Update current programmed PLL rate var */\r
+ s_Audio_Pll_Freq = pSetup->pllRate;\r
+\r
+ return kStatus_PLL_Success;\r
+}\r
+\r
+/* Setup USB PLL Frequency from pre-calculated value */\r
+/**\r
+ * brief Set USB PLL output from USB PLL setup structure (precise frequency)\r
+ * param pSetup : Pointer to populated USB PLL setup structure\r
+ * return kStatus_PLL_Success on success, or USB PLL setup error code\r
+ * note This function will power off the USB PLL, setup the PLL with the\r
+ * new setup data, and then optionally powerup the USB PLL, wait for USB PLL lock,\r
+ * and adjust system voltages to the new USB PLL rate. The function will not\r
+ * alter any source clocks (ie, usb pll clock) that may use the USB PLL,\r
+ * so these should be setup prior to and after exiting the function.\r
+ */\r
+pll_error_t CLOCK_SetUsbPLLFreq(const usb_pll_setup_t *pSetup)\r
+{\r
+ uint32_t usbpllctrl, fccoHz;\r
+ uint8_t msel, psel, nsel;\r
+ bool pllDirectInput, pllDirectOutput, pllfbsel;\r
+\r
+ msel = pSetup->msel;\r
+ psel = pSetup->psel;\r
+ nsel = pSetup->nsel;\r
+ pllDirectOutput = pSetup->direct;\r
+ pllDirectInput = pSetup->bypass;\r
+ pllfbsel = pSetup->fbsel;\r
+\r
+ /* Input clock into the PLL cannot be lower than this */\r
+ if (pSetup->inputRate < USB_PLL_LOWER_IN_LIMIT)\r
+ {\r
+ return kStatus_PLL_InputTooLow;\r
+ }\r
+\r
+ if (pllfbsel)\r
+ {\r
+ /*integer_mode: Fout = M*(Fin/N), Fcco = 2*P*M*(Fin/N) */\r
+ fccoHz = (pSetup->inputRate / ((uint32_t)nsel + 1U)) * 2U * (msel + 1U) * SWITCH_USB_PSEL(psel);\r
+\r
+ /* USB PLL CCO out rate cannot be lower than this */\r
+ if (fccoHz < USB_PLL_MIN_CCO_FREQ_MHZ)\r
+ {\r
+ return kStatus_PLL_CCOTooLow;\r
+ }\r
+ /* USB PLL CCO out rate cannot be Higher than this */\r
+ if (fccoHz > USB_PLL_MAX_CCO_FREQ_MHZ)\r
+ {\r
+ return kStatus_PLL_CCOTooHigh;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* non integer_mode: Fout = M*(Fin/N)/(2*P), Fcco = M * (Fin/N) */\r
+ fccoHz = pSetup->inputRate / ((uint32_t)nsel + 1U) * (msel + 1U);\r
+\r
+ /* USB PLL CCO out rate cannot be lower than this */\r
+ if (fccoHz < USB_PLL_MIN_CCO_FREQ_MHZ)\r
+ {\r
+ return kStatus_PLL_CCOTooLow;\r
+ }\r
+ /* USB PLL CCO out rate cannot be Higher than this */\r
+ if (fccoHz > USB_PLL_MAX_CCO_FREQ_MHZ)\r
+ {\r
+ return kStatus_PLL_CCOTooHigh;\r
+ }\r
+ }\r
+\r
+ /* If configure the USB HOST clock, VD5 power for USB PHY should be enable\r
+ before the PLL is working */\r
+ /* Turn on the ext clock for usb pll input */\r
+ CLOCK_Enable_SysOsc(true);\r
+\r
+ /* Enable power VD3 for PLLs */\r
+ POWER_SetPLL();\r
+\r
+ /* Power on the VD5 for USB PHY */\r
+ POWER_SetUsbPhy();\r
+\r
+ /* Power off USB PLL during setup changes */\r
+ POWER_EnablePD(kPDRUNCFG_PD_USB_PLL);\r
+\r
+ /* Write USB PLL setup data */\r
+ usbpllctrl = USB_PLL_NSEL_VAL_SET(nsel) | /* NSEL VALUE */\r
+ USB_PLL_PSEL_VAL_SET(psel) | /* PSEL VALUE */\r
+ USB_PLL_MSEL_VAL_SET(msel) | /* MSEL VALUE */\r
+ (uint32_t)pllDirectInput << SYSCON_USBPLLCTRL_BYPASS_SHIFT | /* BYPASS DISABLE */\r
+ (uint32_t)pllDirectOutput << SYSCON_USBPLLCTRL_DIRECT_SHIFT | /* DIRECTO DISABLE */\r
+ (uint32_t)pllfbsel << SYSCON_USBPLLCTRL_FBSEL_SHIFT; /* FBSEL SELECT */\r
+\r
+ SYSCON->USBPLLCTRL = usbpllctrl;\r
+\r
+ POWER_DisablePD(kPDRUNCFG_PD_USB_PLL);\r
+\r
+ /* Delay for 72 uSec @ 12Mhz for the usb pll to lock */\r
+ SDK_DelayAtLeastUs(72U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);\r
+ if (false == pllDirectInput)\r
+ {\r
+ while (CLOCK_IsUsbPLLLocked() == false)\r
+ {\r
+ }\r
+ }\r
+ CLOCK_GetUsbPLLOutFromSetupUpdate(pSetup);\r
+ return kStatus_PLL_Success;\r
+}\r
+\r
+/* Set System PLL clock based on the input frequency and multiplier */\r
+/*! brief Set PLL output based on the multiplier and input frequency\r
+ * param multiply_by : multiplier\r
+ * param input_freq : Clock input frequency of the PLL\r
+ * return Nothing\r
+ * note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this\r
+ * function does not disable or enable PLL power, wait for PLL lock,\r
+ * or adjust system voltages. These must be done in the application.\r
+ * The function will not alter any source clocks (ie, main systen clock)\r
+ * that may use the PLL, so these should be setup prior to and after\r
+ * exiting the function.\r
+ */\r
+void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq)\r
+{\r
+ uint32_t cco_freq = input_freq * multiply_by;\r
+ uint32_t pdec = 1U;\r
+ uint32_t selr;\r
+ uint32_t seli;\r
+ uint32_t selp;\r
+ uint32_t mdec, ndec;\r
+\r
+ uint32_t directo = SYSCON_SYSPLLCTRL_DIRECTO(1);\r
+\r
+ while (cco_freq < 275000000U)\r
+ {\r
+ multiply_by <<= 1U; /* double value in each iteration */\r
+ pdec <<= 1U; /* correspondingly double pdec to cancel effect of double msel */\r
+ cco_freq = input_freq * multiply_by;\r
+ }\r
+ selr = 0U;\r
+ if (multiply_by < 60U)\r
+ {\r
+ seli = (multiply_by & 0x3cU) + 4U;\r
+ selp = (multiply_by >> 1U) + 1U;\r
+ }\r
+ else\r
+ {\r
+ selp = 31U;\r
+ if (multiply_by > 16384U)\r
+ {\r
+ seli = 1U;\r
+ }\r
+ else if (multiply_by > 8192U)\r
+ {\r
+ seli = 2U;\r
+ }\r
+ else if (multiply_by > 2048U)\r
+ {\r
+ seli = 4U;\r
+ }\r
+ else if (multiply_by >= 501U)\r
+ {\r
+ seli = 8U;\r
+ }\r
+ else\r
+ {\r
+ seli = 4U * (1024U / (multiply_by + 9U));\r
+ }\r
+ }\r
+\r
+ if (pdec > 1U)\r
+ {\r
+ directo = 0U; /* use post divider */\r
+ pdec = pdec / 2U; /* Account for minus 1 encoding */\r
+ /* Translate P value */\r
+ switch (pdec)\r
+ {\r
+ case 1U:\r
+ pdec = 0x62U; /* 1 * 2 */\r
+ break;\r
+ case 2U:\r
+ pdec = 0x42U; /* 2 * 2 */\r
+ break;\r
+ case 4U:\r
+ pdec = 0x02U; /* 4 * 2 */\r
+ break;\r
+ case 8U:\r
+ pdec = 0x0bU; /* 8 * 2 */\r
+ break;\r
+ case 16U:\r
+ pdec = 0x11U; /* 16 * 2 */\r
+ break;\r
+ case 32U:\r
+ pdec = 0x08U; /* 32 * 2 */\r
+ break;\r
+ default:\r
+ pdec = 0x08U;\r
+ break;\r
+ }\r
+ }\r
+\r
+ mdec = PLL_MDEC_VAL_SET(pllEncodeM(multiply_by));\r
+ ndec = 0x302U; /* pre divide by 1 (hardcoded) */\r
+\r
+ SYSCON->SYSPLLCTRL = directo | (selr << SYSCON_SYSPLLCTRL_SELR_SHIFT) | (seli << SYSCON_SYSPLLCTRL_SELI_SHIFT) |\r
+ (selp << SYSCON_SYSPLLCTRL_SELP_SHIFT);\r
+ SYSCON->SYSPLLPDEC = pdec | (1U << 7U); /* set Pdec value and assert preq */\r
+ SYSCON->SYSPLLNDEC = ndec | (1UL << 10U); /* set Pdec value and assert preq */\r
+ SYSCON->SYSPLLMDEC = (1UL << 17U) | mdec; /* select non sscg MDEC value, assert mreq and select mdec value */\r
+}\r
+\r
+/* Enable USB DEVICE FULL SPEED clock */\r
+/*! brief Enable USB Device FS clock.\r
+ * param src : clock source\r
+ * param freq: clock frequency\r
+ * Enable USB Device Full Speed clock.\r
+ */\r
+bool CLOCK_EnableUsbfs0DeviceClock(clock_usb_src_t src, uint32_t freq)\r
+{\r
+ bool ret = true;\r
+\r
+ CLOCK_DisableClock(kCLOCK_Usbd0);\r
+\r
+ if (kCLOCK_UsbSrcFro == src)\r
+ {\r
+ switch (freq)\r
+ {\r
+ case 96000000U:\r
+ CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */\r
+ break;\r
+\r
+ case 48000000U:\r
+ CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */\r
+ break;\r
+\r
+ default:\r
+ ret = false;\r
+ break;\r
+ }\r
+ /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */\r
+ SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01UL << 15U) | (0xFUL << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK |\r
+ SYSCON_FROCTRL_USBCLKADJ_MASK;\r
+ /* Select FRO 96 or 48 MHz */\r
+ CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);\r
+ }\r
+ else\r
+ {\r
+ /*Set the USB PLL as the Usb0 CLK*/\r
+ POWER_DisablePD(kPDRUNCFG_PD_USB_PLL);\r
+\r
+ usb_pll_setup_t pll_setup = {0x3FU, 0x01U, 0x03U, false, false, false, 12000000U};\r
+\r
+ (void)CLOCK_SetUsbPLLFreq(&pll_setup);\r
+ CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false);\r
+ CLOCK_AttachClk(kUSB_PLL_to_USB0_CLK);\r
+ SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);\r
+ }\r
+ CLOCK_EnableClock(kCLOCK_Usbd0);\r
+ CLOCK_EnableClock(kCLOCK_UsbRam1);\r
+\r
+ return ret;\r
+}\r
+\r
+/* Enable USB HOST FULL SPEED clock */\r
+/*! brief Enable USB HOST FS clock.\r
+ * param src : clock source\r
+ * param freq: clock frequency\r
+ * Enable USB HOST Full Speed clock.\r
+ */\r
+bool CLOCK_EnableUsbfs0HostClock(clock_usb_src_t src, uint32_t freq)\r
+{\r
+ bool ret = true;\r
+\r
+ CLOCK_DisableClock(kCLOCK_Usbhmr0);\r
+ CLOCK_DisableClock(kCLOCK_Usbhsl0);\r
+\r
+ if (kCLOCK_UsbSrcFro == src)\r
+ {\r
+ switch (freq)\r
+ {\r
+ case 96000000U:\r
+ CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */\r
+ break;\r
+\r
+ case 48000000U:\r
+ CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */\r
+ break;\r
+\r
+ default:\r
+ ret = false;\r
+ break;\r
+ }\r
+ /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */\r
+ SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01UL << 15U) | (0xFUL << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK |\r
+ SYSCON_FROCTRL_USBCLKADJ_MASK;\r
+ /* Select FRO 96 or 48 MHz */\r
+ CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);\r
+ }\r
+ else\r
+ {\r
+ /*Set the USB PLL as the Usb0 CLK*/\r
+ POWER_DisablePD(kPDRUNCFG_PD_USB_PLL);\r
+\r
+ usb_pll_setup_t pll_setup = {0x3FU, 0x01U, 0x03U, false, false, false, 12000000U};\r
+\r
+ (void)CLOCK_SetUsbPLLFreq(&pll_setup);\r
+ CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false);\r
+ CLOCK_AttachClk(kUSB_PLL_to_USB0_CLK);\r
+ SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);\r
+ }\r
+ CLOCK_EnableClock(kCLOCK_Usbhmr0);\r
+ CLOCK_EnableClock(kCLOCK_Usbhsl0);\r
+ CLOCK_EnableClock(kCLOCK_UsbRam1);\r
+\r
+ return ret;\r
+}\r
+\r
+/* Enable USB DEVICE HIGH SPEED clock */\r
+/*! brief Enable USB Device HS clock.\r
+ * param src : clock source\r
+ * param freq: clock frequency\r
+ * Enable USB Device High Speed clock.\r
+ */\r
+bool CLOCK_EnableUsbhs0DeviceClock(clock_usb_src_t src, uint32_t freq)\r
+{\r
+ bool ret = true;\r
+ CLOCK_DisableClock(kCLOCK_Usbd1);\r
+ /* Power on the VD5 for USB PHY */\r
+ POWER_SetUsbPhy();\r
+ if (kCLOCK_UsbSrcFro == src)\r
+ {\r
+ switch (freq)\r
+ {\r
+ case 96000000U:\r
+ CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */\r
+ break;\r
+\r
+ case 48000000U:\r
+ CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */\r
+ break;\r
+\r
+ default:\r
+ ret = false;\r
+ break;\r
+ }\r
+ /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */\r
+ SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01UL << 15U) | (0xFUL << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK |\r
+ SYSCON_FROCTRL_USBCLKADJ_MASK;\r
+ /* Select FRO 96 or 48 MHz */\r
+ CLOCK_AttachClk(kFRO_HF_to_USB1_CLK);\r
+ }\r
+ else\r
+ {\r
+ SDK_DelayAtLeastUs(50, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);\r
+ usb_pll_setup_t pll_setup = {0x3FU, 0x01U, 0x03U, false, false, false, 12000000U};\r
+\r
+ (void)CLOCK_SetUsbPLLFreq(&pll_setup);\r
+\r
+ /* Select USB PLL output as USB clock src */\r
+ CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false);\r
+ CLOCK_AttachClk(kUSB_PLL_to_USB1_CLK);\r
+ }\r
+\r
+ SDK_DelayAtLeastUs(50, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);\r
+ /* Enable USB1D and USB1RAM */\r
+ CLOCK_EnableClock(kCLOCK_Usbd1);\r
+ CLOCK_EnableClock(kCLOCK_UsbRam1);\r
+ POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /* Turn on power for USB PHY */\r
+ return ret;\r
+}\r
+\r
+/* Enable USB HOST HIGH SPEED clock */\r
+/*! brief Enable USB HOST HS clock.\r
+ * param src : clock source\r
+ * param freq: clock frequency\r
+ * Enable USB HOST High Speed clock.\r
+ */\r
+bool CLOCK_EnableUsbhs0HostClock(clock_usb_src_t src, uint32_t freq)\r
+{\r
+ bool ret = true;\r
+ CLOCK_DisableClock(kCLOCK_Usbh1);\r
+ /* Power on the VD5 for USB PHY */\r
+ POWER_SetUsbPhy();\r
+ if (kCLOCK_UsbSrcFro == src)\r
+ {\r
+ switch (freq)\r
+ {\r
+ case 96000000U:\r
+ CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */\r
+ break;\r
+\r
+ case 48000000U:\r
+ CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */\r
+ break;\r
+\r
+ default:\r
+ ret = false;\r
+ break;\r
+ }\r
+ /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */\r
+ SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01UL << 15U) | (0xFUL << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK |\r
+ SYSCON_FROCTRL_USBCLKADJ_MASK;\r
+ /* Select FRO 96 or 48 MHz */\r
+ CLOCK_AttachClk(kFRO_HF_to_USB1_CLK);\r
+ }\r
+ else\r
+ {\r
+ SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);\r
+ usb_pll_setup_t pll_setup = {0x3FU, 0x01U, 0x03U, false, false, false, 12000000U};\r
+\r
+ (void)CLOCK_SetUsbPLLFreq(&pll_setup);\r
+\r
+ /* Select USB PLL output as USB clock src */\r
+ CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false);\r
+ CLOCK_AttachClk(kUSB_PLL_to_USB1_CLK);\r
+ }\r
+\r
+ SDK_DelayAtLeastUs(50, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);\r
+ /* Enable USBh1 and USB1RAM */\r
+ CLOCK_EnableClock(kCLOCK_Usbh1);\r
+ CLOCK_EnableClock(kCLOCK_UsbRam1);\r
+ POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /* Turn on power for USB PHY */\r
+ return ret;\r
+}\r
--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016 - 2019 , NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#ifndef _FSL_CLOCK_H_\r
+#define _FSL_CLOCK_H_\r
+\r
+#include "fsl_common.h"\r
+\r
+/*! @addtogroup clock */\r
+/*! @{ */\r
+\r
+/*! @file */\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ *****************************************************************************/\r
+\r
+/*! @name Driver version */\r
+/*@{*/\r
+/*! @brief CLOCK driver version 2.3.1. */\r
+#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))\r
+/*@}*/\r
+\r
+/*! @brief Configure whether driver controls clock\r
+ *\r
+ * When set to 0, peripheral drivers will enable clock in initialize function\r
+ * and disable clock in de-initialize function. When set to 1, peripheral\r
+ * driver will not control the clock, application could control the clock out of\r
+ * the driver.\r
+ *\r
+ * @note All drivers share this feature switcher. If it is set to 1, application\r
+ * should handle clock enable and disable for all drivers.\r
+ */\r
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))\r
+#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0\r
+#endif\r
+\r
+/*!\r
+ * @brief User-defined the size of cache for CLOCK_PllGetConfig() function.\r
+ *\r
+ * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function\r
+ * would cache the recent calulation and accelerate the execution to get the\r
+ * right settings.\r
+ */\r
+#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT\r
+#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U\r
+#endif\r
+\r
+/* Definition for delay API in clock driver, users can redefine it to the real application. */\r
+#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY\r
+#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (180000000UL)\r
+#endif\r
+\r
+/*! @brief Clock ip name array for ADC. */\r
+#define ADC_CLOCKS \\r
+ { \\r
+ kCLOCK_Adc0 \\r
+ }\r
+/*! @brief Clock ip name array for ROM. */\r
+#define ROM_CLOCKS \\r
+ { \\r
+ kCLOCK_Rom \\r
+ }\r
+/*! @brief Clock ip name array for SRAM. */\r
+#define SRAM_CLOCKS \\r
+ { \\r
+ kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3 \\r
+ }\r
+/*! @brief Clock ip name array for FLASH. */\r
+#define FLASH_CLOCKS \\r
+ { \\r
+ kCLOCK_Flash \\r
+ }\r
+/*! @brief Clock ip name array for FMC. */\r
+#define FMC_CLOCKS \\r
+ { \\r
+ kCLOCK_Fmc \\r
+ }\r
+/*! @brief Clock ip name array for EEPROM. */\r
+#define EEPROM_CLOCKS \\r
+ { \\r
+ kCLOCK_Eeprom \\r
+ }\r
+/*! @brief Clock ip name array for SPIFI. */\r
+#define SPIFI_CLOCKS \\r
+ { \\r
+ kCLOCK_Spifi \\r
+ }\r
+/*! @brief Clock ip name array for INPUTMUX. */\r
+#define INPUTMUX_CLOCKS \\r
+ { \\r
+ kCLOCK_InputMux \\r
+ }\r
+/*! @brief Clock ip name array for IOCON. */\r
+#define IOCON_CLOCKS \\r
+ { \\r
+ kCLOCK_Iocon \\r
+ }\r
+/*! @brief Clock ip name array for GPIO. */\r
+#define GPIO_CLOCKS \\r
+ { \\r
+ kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \\r
+ }\r
+/*! @brief Clock ip name array for PINT. */\r
+#define PINT_CLOCKS \\r
+ { \\r
+ kCLOCK_Pint \\r
+ }\r
+/*! @brief Clock ip name array for GINT. */\r
+#define GINT_CLOCKS \\r
+ { \\r
+ kCLOCK_Gint, kCLOCK_Gint \\r
+ }\r
+/*! @brief Clock ip name array for DMA. */\r
+#define DMA_CLOCKS \\r
+ { \\r
+ kCLOCK_Dma \\r
+ }\r
+/*! @brief Clock ip name array for CRC. */\r
+#define CRC_CLOCKS \\r
+ { \\r
+ kCLOCK_Crc \\r
+ }\r
+/*! @brief Clock ip name array for WWDT. */\r
+#define WWDT_CLOCKS \\r
+ { \\r
+ kCLOCK_Wwdt \\r
+ }\r
+/*! @brief Clock ip name array for RTC. */\r
+#define RTC_CLOCKS \\r
+ { \\r
+ kCLOCK_Rtc \\r
+ }\r
+/*! @brief Clock ip name array for ADC0. */\r
+#define ADC0_CLOCKS \\r
+ { \\r
+ kCLOCK_Adc0 \\r
+ }\r
+/*! @brief Clock ip name array for MRT. */\r
+#define MRT_CLOCKS \\r
+ { \\r
+ kCLOCK_Mrt \\r
+ }\r
+/*! @brief Clock ip name array for RIT. */\r
+#define RIT_CLOCKS \\r
+ { \\r
+ kCLOCK_Rit \\r
+ }\r
+/*! @brief Clock ip name array for SCT0. */\r
+#define SCT_CLOCKS \\r
+ { \\r
+ kCLOCK_Sct0 \\r
+ }\r
+/*! @brief Clock ip name array for MCAN. */\r
+#define MCAN_CLOCKS \\r
+ { \\r
+ kCLOCK_Mcan0, kCLOCK_Mcan1 \\r
+ }\r
+/*! @brief Clock ip name array for UTICK. */\r
+#define UTICK_CLOCKS \\r
+ { \\r
+ kCLOCK_Utick \\r
+ }\r
+/*! @brief Clock ip name array for FLEXCOMM. */\r
+#define FLEXCOMM_CLOCKS \\r
+ { \\r
+ kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \\r
+ kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_FlexComm8, kCLOCK_FlexComm9, kCLOCK_FlexComm10 \\r
+ }\r
+/*! @brief Clock ip name array for LPUART. */\r
+#define LPUART_CLOCKS \\r
+ { \\r
+ kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \\r
+ kCLOCK_MinUart6, kCLOCK_MinUart7, kCLOCK_MinUart8, kCLOCK_MinUart9 \\r
+ }\r
+\r
+/*! @brief Clock ip name array for BI2C. */\r
+#define BI2C_CLOCKS \\r
+ { \\r
+ kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, \\r
+ kCLOCK_BI2c7, kCLOCK_BI2c8, kCLOCK_BI2c9 \\r
+ }\r
+/*! @brief Clock ip name array for LSPI. */\r
+#define LPSI_CLOCKS \\r
+ { \\r
+ kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, \\r
+ kCLOCK_LSpi7, kCLOCK_LSpi8, kCLOCK_LSpi9 \\r
+ }\r
+/*! @brief Clock ip name array for FLEXI2S. */\r
+#define FLEXI2S_CLOCKS \\r
+ { \\r
+ kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \\r
+ kCLOCK_FlexI2s6, kCLOCK_FlexI2s7, kCLOCK_FlexI2s8, kCLOCK_FlexI2s9 \\r
+ }\r
+/*! @brief Clock ip name array for DMIC. */\r
+#define DMIC_CLOCKS \\r
+ { \\r
+ kCLOCK_DMic \\r
+ }\r
+/*! @brief Clock ip name array for CT32B. */\r
+#define CTIMER_CLOCKS \\r
+ { \\r
+ kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \\r
+ }\r
+/*! @brief Clock ip name array for LCD. */\r
+#define LCD_CLOCKS \\r
+ { \\r
+ kCLOCK_Lcd \\r
+ }\r
+/*! @brief Clock ip name array for SDIO. */\r
+#define SDIO_CLOCKS \\r
+ { \\r
+ kCLOCK_Sdio \\r
+ }\r
+/*! @brief Clock ip name array for USBRAM. */\r
+#define USBRAM_CLOCKS \\r
+ { \\r
+ kCLOCK_UsbRam1 \\r
+ }\r
+/*! @brief Clock ip name array for EMC. */\r
+#define EMC_CLOCKS \\r
+ { \\r
+ kCLOCK_Emc \\r
+ }\r
+/*! @brief Clock ip name array for ETH. */\r
+#define ETH_CLOCKS \\r
+ { \\r
+ kCLOCK_Eth \\r
+ }\r
+/*! @brief Clock ip name array for AES. */\r
+#define AES_CLOCKS \\r
+ { \\r
+ kCLOCK_Aes \\r
+ }\r
+/*! @brief Clock ip name array for OTP. */\r
+#define OTP_CLOCKS \\r
+ { \\r
+ kCLOCK_Otp \\r
+ }\r
+/*! @brief Clock ip name array for RNG. */\r
+#define RNG_CLOCKS \\r
+ { \\r
+ kCLOCK_Rng \\r
+ }\r
+/*! @brief Clock ip name array for USBHMR0. */\r
+#define USBHMR0_CLOCKS \\r
+ { \\r
+ kCLOCK_Usbhmr0 \\r
+ }\r
+/*! @brief Clock ip name array for USBHSL0. */\r
+#define USBHSL0_CLOCKS \\r
+ { \\r
+ kCLOCK_Usbhsl0 \\r
+ }\r
+/*! @brief Clock ip name array for SHA0. */\r
+#define SHA0_CLOCKS \\r
+ { \\r
+ kCLOCK_Sha0 \\r
+ }\r
+/*! @brief Clock ip name array for SMARTCARD. */\r
+#define SMARTCARD_CLOCKS \\r
+ { \\r
+ kCLOCK_SmartCard0, kCLOCK_SmartCard1 \\r
+ }\r
+/*! @brief Clock ip name array for USBD. */\r
+#define USBD_CLOCKS \\r
+ { \\r
+ kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \\r
+ }\r
+/*! @brief Clock ip name array for USBH. */\r
+#define USBH_CLOCKS \\r
+ { \\r
+ kCLOCK_Usbh1 \\r
+ }\r
+/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */\r
+/*------------------------------------------------------------------------------\r
+ clock_ip_name_t definition:\r
+------------------------------------------------------------------------------*/\r
+\r
+#define CLK_GATE_REG_OFFSET_SHIFT 8U\r
+#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U\r
+#define CLK_GATE_BIT_SHIFT_SHIFT 0U\r
+#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU\r
+\r
+#define CLK_GATE_DEFINE(reg_offset, bit_shift) \\r
+ ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \\r
+ (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))\r
+\r
+#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)\r
+#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)\r
+\r
+#define AHB_CLK_CTRL0 0\r
+#define AHB_CLK_CTRL1 1\r
+#define AHB_CLK_CTRL2 2\r
+#define ASYNC_CLK_CTRL0 3\r
+\r
+/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */\r
+typedef enum _clock_ip_name\r
+{\r
+ kCLOCK_IpInvalid = 0U,\r
+ kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1),\r
+ kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3),\r
+ kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4),\r
+ kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5),\r
+ kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10),\r
+ kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11),\r
+ kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13),\r
+ kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14),\r
+ kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15),\r
+ kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16),\r
+ kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17),\r
+ kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18),\r
+ kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19),\r
+ kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20),\r
+ kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21),\r
+ kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22),\r
+ kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23),\r
+ kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27),\r
+ kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0),\r
+ kCLOCK_Rit = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1),\r
+ kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2),\r
+ kCLOCK_Mcan0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7),\r
+ kCLOCK_Mcan1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 8),\r
+ kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10),\r
+ kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),\r
+ kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),\r
+ kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),\r
+ kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),\r
+ kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),\r
+ kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),\r
+ kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),\r
+ kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),\r
+ kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),\r
+ kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),\r
+ kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),\r
+ kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),\r
+ kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),\r
+ kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),\r
+ kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),\r
+ kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),\r
+ kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),\r
+ kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),\r
+ kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),\r
+ kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),\r
+ kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),\r
+ kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),\r
+ kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),\r
+ kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),\r
+ kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),\r
+ kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),\r
+ kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),\r
+ kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),\r
+ kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),\r
+ kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),\r
+ kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),\r
+ kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),\r
+ kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),\r
+ kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),\r
+ kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),\r
+ kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),\r
+ kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),\r
+ kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),\r
+ kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),\r
+ kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),\r
+ kCLOCK_DMic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19),\r
+ kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22),\r
+ kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25),\r
+ kCLOCK_Ct32b0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26),\r
+ kCLOCK_Ct32b1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27),\r
+ kCLOCK_BodyBias0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29),\r
+ kCLOCK_EzhArchB0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31),\r
+ kCLOCK_Lcd = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2),\r
+ kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3),\r
+ kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4),\r
+ kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5),\r
+ kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6),\r
+ kCLOCK_Emc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7),\r
+ kCLOCK_Eth = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8),\r
+ kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 9),\r
+ kCLOCK_Gpio5 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 10),\r
+ kCLOCK_Aes = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11),\r
+ kCLOCK_Otp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 12),\r
+ kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13),\r
+ kCLOCK_FlexComm8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),\r
+ kCLOCK_FlexComm9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),\r
+ kCLOCK_MinUart8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),\r
+ kCLOCK_MinUart9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),\r
+ kCLOCK_LSpi8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),\r
+ kCLOCK_LSpi9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),\r
+ kCLOCK_BI2c8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),\r
+ kCLOCK_BI2c9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),\r
+ kCLOCK_FlexI2s8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),\r
+ kCLOCK_FlexI2s9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),\r
+ kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16),\r
+ kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17),\r
+ kCLOCK_Sha0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18),\r
+ kCLOCK_SmartCard0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19),\r
+ kCLOCK_SmartCard1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20),\r
+ kCLOCK_FlexComm10 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21),\r
+\r
+ kCLOCK_Ct32b3 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 13),\r
+ kCLOCK_Ct32b4 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 14)\r
+} clock_ip_name_t;\r
+\r
+/*! @brief Clock name used to get clock frequency. */\r
+typedef enum _clock_name\r
+{\r
+ kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */\r
+ kCLOCK_BusClk, /*!< Bus clock (AHB clock) */\r
+ kCLOCK_ClockOut, /*!< CLOCKOUT */\r
+ kCLOCK_FroHf, /*!< FRO48/96 */\r
+ kCLOCK_UsbPll, /*!< USB1 PLL */\r
+ kCLOCK_Mclk, /*!< MCLK */\r
+ kCLOCK_Fro12M, /*!< FRO12M */\r
+ kCLOCK_ExtClk, /*!< External Clock */\r
+ kCLOCK_PllOut, /*!< PLL Output */\r
+ kCLOCK_UsbClk, /*!< USB input */\r
+ kCLOCK_WdtOsc, /*!< Watchdog Oscillator */\r
+ kCLOCK_Frg, /*!< Frg Clock */\r
+ kCLOCK_AsyncApbClk, /*!< Async APB clock */\r
+} clock_name_t;\r
+\r
+/**\r
+ * Clock source selections for the asynchronous APB clock\r
+ */\r
+typedef enum _async_clock_src\r
+{\r
+ kCLOCK_AsyncMainClk = 0, /*!< Main System clock */\r
+ kCLOCK_AsyncFro12Mhz, /*!< 12MHz FRO */\r
+ kCLOCK_AsyncAudioPllClk,\r
+ kCLOCK_AsyncI2cClkFc6,\r
+\r
+} async_clock_src_t;\r
+\r
+/*! @brief Clock Mux Switches\r
+ * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable\r
+ * starting from LSB upwards\r
+ *\r
+ * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*\r
+ *\r
+ */\r
+\r
+#define CLK_ATTACH_ID(mux, sel, pos) ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((pos)*12U))\r
+#define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U)\r
+#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U))\r
+\r
+#define GET_ID_ITEM(connection) ((connection)&0xFFFU)\r
+#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U)\r
+#define GET_ID_ITEM_MUX(connection) ((uint8_t)((connection)&0xFFU))\r
+#define GET_ID_ITEM_SEL(connection) ((uint8_t)((((connection)&0xF00U) >> 8U) - 1U))\r
+#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U)\r
+\r
+#define CM_STICKCLKSEL 0\r
+#define CM_MAINCLKSELA 1\r
+#define CM_MAINCLKSELB 2\r
+#define CM_CLKOUTCLKSELA 3\r
+#define CM_SYSPLLCLKSEL 5\r
+#define CM_AUDPLLCLKSEL 7\r
+#define CM_SPIFICLKSEL 9\r
+#define CM_ADCASYNCCLKSEL 10\r
+#define CM_USB0CLKSEL 11\r
+#define CM_USB1CLKSEL 12\r
+#define CM_FXCOMCLKSEL0 13\r
+#define CM_FXCOMCLKSEL1 14\r
+#define CM_FXCOMCLKSEL2 15\r
+#define CM_FXCOMCLKSEL3 16\r
+#define CM_FXCOMCLKSEL4 17\r
+#define CM_FXCOMCLKSEL5 18\r
+#define CM_FXCOMCLKSEL6 19\r
+#define CM_FXCOMCLKSEL7 20\r
+#define CM_FXCOMCLKSEL8 21\r
+#define CM_FXCOMCLKSEL9 22\r
+#define CM_FXCOMCLKSEL10 23\r
+#define CM_MCLKCLKSEL 25\r
+#define CM_FRGCLKSEL 27\r
+#define CM_DMICCLKSEL 28\r
+#define CM_SCTCLKSEL 29\r
+#define CM_LCDCLKSEL 30\r
+#define CM_SDIOCLKSEL 31\r
+\r
+#define CM_ASYNCAPB 32U\r
+\r
+typedef enum _clock_attach_id\r
+{\r
+\r
+ kSYSTICK_DIV_CLK_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 0),\r
+ kWDT_OSC_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 1),\r
+ kOSC32K_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 2),\r
+ kFRO12M_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 3),\r
+ kNONE_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 7),\r
+\r
+ kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0),\r
+ kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0),\r
+ kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0),\r
+ kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0),\r
+ kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0),\r
+ kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0),\r
+\r
+ kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0),\r
+ kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1),\r
+ kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2),\r
+ kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3),\r
+ kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4),\r
+ kUSB_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5),\r
+ kAUDIO_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6),\r
+ kOSC32K_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7),\r
+\r
+ kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0),\r
+ kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1),\r
+ kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2),\r
+ kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3),\r
+ kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7),\r
+\r
+ kFRO12M_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 0),\r
+ kEXT_CLK_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 1),\r
+ kNONE_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 7),\r
+\r
+ kMAIN_CLK_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 0),\r
+ kSYS_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 1),\r
+ kUSB_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 2),\r
+ kFRO_HF_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 3),\r
+ kAUDIO_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 4),\r
+ kNONE_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 7),\r
+\r
+ kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0),\r
+ kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1),\r
+ kUSB_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2),\r
+ kAUDIO_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 3),\r
+ kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7),\r
+\r
+ kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0),\r
+ kSYS_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1),\r
+ kUSB_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 2),\r
+ kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7),\r
+\r
+ kFRO_HF_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 0),\r
+ kSYS_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 1),\r
+ kUSB_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 2),\r
+ kNONE_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 7),\r
+\r
+ kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0),\r
+ kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1),\r
+ kAUDIO_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2),\r
+ kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3),\r
+ kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4),\r
+ kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7),\r
+\r
+ kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0),\r
+ kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1),\r
+ kAUDIO_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2),\r
+ kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3),\r
+ kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4),\r
+ kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7),\r
+\r
+ kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0),\r
+ kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1),\r
+ kAUDIO_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2),\r
+ kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3),\r
+ kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4),\r
+ kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7),\r
+\r
+ kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0),\r
+ kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1),\r
+ kAUDIO_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2),\r
+ kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3),\r
+ kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4),\r
+ kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7),\r
+\r
+ kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0),\r
+ kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1),\r
+ kAUDIO_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2),\r
+ kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3),\r
+ kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4),\r
+ kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7),\r
+\r
+ kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0),\r
+ kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1),\r
+ kAUDIO_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2),\r
+ kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3),\r
+ kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4),\r
+ kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7),\r
+\r
+ kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0),\r
+ kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1),\r
+ kAUDIO_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2),\r
+ kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3),\r
+ kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4),\r
+ kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7),\r
+\r
+ kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0),\r
+ kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1),\r
+ kAUDIO_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2),\r
+ kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3),\r
+ kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4),\r
+ kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7),\r
+\r
+ kFRO12M_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 0),\r
+ kFRO_HF_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 1),\r
+ kAUDIO_PLL_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 2),\r
+ kMCLK_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 3),\r
+ kFRG_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 4),\r
+ kNONE_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 7),\r
+\r
+ kFRO12M_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 0),\r
+ kFRO_HF_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 1),\r
+ kAUDIO_PLL_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 2),\r
+ kMCLK_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 3),\r
+ kFRG_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 4),\r
+ kNONE_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 7),\r
+\r
+ kMAIN_CLK_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 0),\r
+ kSYS_PLL_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 1),\r
+ kUSB_PLL_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 2),\r
+ kFRO_HF_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 3),\r
+ kAUDIO_PLL_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 4),\r
+ kNONE_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 7),\r
+\r
+ kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0),\r
+ kAUDIO_PLL_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1),\r
+ kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7),\r
+\r
+ kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0),\r
+ kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1),\r
+ kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2),\r
+ kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3),\r
+ kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7),\r
+\r
+ kFRO12M_to_DMIC = MUX_A(CM_DMICCLKSEL, 0),\r
+ kFRO_HF_DIV_to_DMIC = MUX_A(CM_DMICCLKSEL, 1),\r
+ kAUDIO_PLL_to_DMIC = MUX_A(CM_DMICCLKSEL, 2),\r
+ kMCLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 3),\r
+ kMAIN_CLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 4),\r
+ kWDT_OSC_to_DMIC = MUX_A(CM_DMICCLKSEL, 5),\r
+ kNONE_to_DMIC = MUX_A(CM_DMICCLKSEL, 7),\r
+\r
+ kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0),\r
+ kSYS_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1),\r
+ kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2),\r
+ kAUDIO_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3),\r
+ kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7),\r
+\r
+ kMAIN_CLK_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 0),\r
+ kLCDCLKIN_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 1),\r
+ kFRO_HF_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 2),\r
+ kNONE_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 3),\r
+\r
+ kMAIN_CLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0),\r
+ kSYS_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1),\r
+ kUSB_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 2),\r
+ kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3),\r
+ kAUDIO_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 4),\r
+ kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7),\r
+\r
+ kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0),\r
+ kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1),\r
+ kAUDIO_PLL_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 2),\r
+ kI2C_CLK_FC6_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 3),\r
+ kNONE_to_NONE = (int)0x80000000U,\r
+} clock_attach_id_t;\r
+\r
+/* Clock dividers */\r
+typedef enum _clock_div_name\r
+{\r
+ kCLOCK_DivSystickClk = 0,\r
+ kCLOCK_DivArmTrClkDiv = 1,\r
+ kCLOCK_DivCan0Clk = 2,\r
+ kCLOCK_DivCan1Clk = 3,\r
+ kCLOCK_DivSmartCard0Clk = 4,\r
+ kCLOCK_DivSmartCard1Clk = 5,\r
+ kCLOCK_DivAhbClk = 32,\r
+ kCLOCK_DivClkOut = 33,\r
+ kCLOCK_DivFrohfClk = 34,\r
+ kCLOCK_DivSpifiClk = 36,\r
+ kCLOCK_DivAdcAsyncClk = 37,\r
+ kCLOCK_DivUsb0Clk = 38,\r
+ kCLOCK_DivUsb1Clk = 39,\r
+ kCLOCK_DivFrg = 40,\r
+ kCLOCK_DivDmicClk = 42,\r
+ kCLOCK_DivMClk = 43,\r
+ kCLOCK_DivLcdClk = 44,\r
+ kCLOCK_DivSctClk = 45,\r
+ kCLOCK_DivEmcClk = 46,\r
+ kCLOCK_DivSdioClk = 47\r
+} clock_div_name_t;\r
+\r
+/*******************************************************************************\r
+ * API\r
+ ******************************************************************************/\r
+\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif /* __cplusplus */\r
+\r
+static inline void CLOCK_EnableClock(clock_ip_name_t clk)\r
+{\r
+ uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);\r
+ if (index < 3UL)\r
+ {\r
+ SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));\r
+ }\r
+ else\r
+ {\r
+ SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(1);\r
+ ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));\r
+ }\r
+}\r
+\r
+static inline void CLOCK_DisableClock(clock_ip_name_t clk)\r
+{\r
+ uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);\r
+ if (index < 3UL)\r
+ {\r
+ SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));\r
+ }\r
+ else\r
+ {\r
+ ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));\r
+ SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(0);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief\r
+ * Initialize the Core clock to given frequency (12, 48 or 96 MHz), this API is implememnt in ROM code.\r
+ * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed\r
+ * output is enabled.\r
+ * Usage: CLOCK_SetupFROClocking(frequency), (frequency must be one of 12, 48 or 96 MHz)\r
+ * Note: Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U) before calling this API since this API is\r
+ * implemented in ROM code and the FROHF TRIM value is stored in OTP\r
+ *\r
+ * @param froFreq target fro frequency.\r
+ * @return Nothing\r
+ */\r
+\r
+void CLOCK_SetupFROClocking(uint32_t froFreq);\r
+\r
+/**\r
+ * @brief Configure the clock selection muxes.\r
+ * @param connection : Clock to be configured.\r
+ * @return Nothing\r
+ */\r
+void CLOCK_AttachClk(clock_attach_id_t connection);\r
+/**\r
+ * @brief Get the actual clock attach id.\r
+ * This fuction uses the offset in input attach id, then it reads the actual source value in\r
+ * the register and combine the offset to obtain an actual attach id.\r
+ * @param attachId : Clock attach id to get.\r
+ * @return Clock source value.\r
+ */\r
+clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId);\r
+/**\r
+ * @brief Setup peripheral clock dividers.\r
+ * @param div_name : Clock divider name\r
+ * @param divided_by_value: Value to be divided\r
+ * @param reset : Whether to reset the divider counter.\r
+ * @return Nothing\r
+ */\r
+void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);\r
+\r
+/*! @brief Return Frequency of selected clock\r
+ * @return Frequency of selected clock\r
+ */\r
+uint32_t CLOCK_GetFreq(clock_name_t clockName);\r
+/*! @brief Return Frequency of FRO 12MHz\r
+ * @return Frequency of FRO 12MHz\r
+ */\r
+uint32_t CLOCK_GetFro12MFreq(void);\r
+/*! @brief Return Frequency of ClockOut\r
+ * @return Frequency of ClockOut\r
+ */\r
+uint32_t CLOCK_GetClockOutClkFreq(void);\r
+/*! @brief Return Frequency of Spifi Clock\r
+ * @return Frequency of Spifi.\r
+ */\r
+uint32_t CLOCK_GetSpifiClkFreq(void);\r
+/*! @brief Return Frequency of Adc Clock\r
+ * @return Frequency of Adc Clock.\r
+ */\r
+uint32_t CLOCK_GetAdcClkFreq(void);\r
+/*! brief Return Frequency of MCAN Clock\r
+ * param MCanSel : 0U: MCAN0; 1U: MCAN1\r
+ * return Frequency of MCAN Clock\r
+ */\r
+uint32_t CLOCK_GetMCanClkFreq(uint32_t MCanSel);\r
+/*! @brief Return Frequency of Usb0 Clock\r
+ * @return Frequency of Usb0 Clock.\r
+ */\r
+uint32_t CLOCK_GetUsb0ClkFreq(void);\r
+/*! @brief Return Frequency of Usb1 Clock\r
+ * @return Frequency of Usb1 Clock.\r
+ */\r
+uint32_t CLOCK_GetUsb1ClkFreq(void);\r
+/*! @brief Return Frequency of MClk Clock\r
+ * @return Frequency of MClk Clock.\r
+ */\r
+uint32_t CLOCK_GetMclkClkFreq(void);\r
+/*! @brief Return Frequency of SCTimer Clock\r
+ * @return Frequency of SCTimer Clock.\r
+ */\r
+uint32_t CLOCK_GetSctClkFreq(void);\r
+/*! @brief Return Frequency of SDIO Clock\r
+ * @return Frequency of SDIO Clock.\r
+ */\r
+uint32_t CLOCK_GetSdioClkFreq(void);\r
+/*! @brief Return Frequency of LCD Clock\r
+ * @return Frequency of LCD Clock.\r
+ */\r
+uint32_t CLOCK_GetLcdClkFreq(void);\r
+/*! @brief Return Frequency of LCD CLKIN Clock\r
+ * @return Frequency of LCD CLKIN Clock.\r
+ */\r
+uint32_t CLOCK_GetLcdClkIn(void);\r
+/*! @brief Return Frequency of External Clock\r
+ * @return Frequency of External Clock. If no external clock is used returns 0.\r
+ */\r
+uint32_t CLOCK_GetExtClkFreq(void);\r
+/*! @brief Return Frequency of Watchdog Oscillator\r
+ * @return Frequency of Watchdog Oscillator\r
+ */\r
+uint32_t CLOCK_GetWdtOscFreq(void);\r
+/*! @brief Return Frequency of High-Freq output of FRO\r
+ * @return Frequency of High-Freq output of FRO\r
+ */\r
+uint32_t CLOCK_GetFroHfFreq(void);\r
+/*! @brief Return Frequency of frg\r
+ * @return Frequency of FRG\r
+ */\r
+uint32_t CLOCK_GetFrgClkFreq(void);\r
+/*! @brief Return Frequency of dmic\r
+ * @return Frequency of DMIC\r
+ */\r
+uint32_t CLOCK_GetDmicClkFreq(void);\r
+\r
+/*!\r
+ * @brief Set FRG Clk\r
+ * @return\r
+ * 1: if set FRG CLK successfully.\r
+ * 0: if set FRG CLK fail.\r
+ */\r
+uint32_t CLOCK_SetFRGClock(uint32_t freq);\r
+\r
+/*! @brief Return Frequency of PLL\r
+ * @return Frequency of PLL\r
+ */\r
+uint32_t CLOCK_GetPllOutFreq(void);\r
+/*! @brief Return Frequency of USB PLL\r
+ * @return Frequency of PLL\r
+ */\r
+uint32_t CLOCK_GetUsbPllOutFreq(void);\r
+/*! @brief Return Frequency of AUDIO PLL\r
+ * @return Frequency of PLL\r
+ */\r
+uint32_t CLOCK_GetAudioPllOutFreq(void);\r
+/*! @brief Return Frequency of 32kHz osc\r
+ * @return Frequency of 32kHz osc\r
+ */\r
+uint32_t CLOCK_GetOsc32KFreq(void);\r
+/*! @brief Return Frequency of Core System\r
+ * @return Frequency of Core System\r
+ */\r
+uint32_t CLOCK_GetCoreSysClkFreq(void);\r
+/*! @brief Return Frequency of I2S MCLK Clock\r
+ * @return Frequency of I2S MCLK Clock\r
+ */\r
+uint32_t CLOCK_GetI2SMClkFreq(void);\r
+/*! @brief Return Frequency of Flexcomm functional Clock\r
+ * @return Frequency of Flexcomm functional Clock\r
+ */\r
+uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);\r
+\r
+/*! @brief return FRG Clk\r
+ * @return Frequency of FRG CLK.\r
+ */\r
+uint32_t CLOCK_GetFRGInputClock(void);\r
+/*! @brief Return Asynchronous APB Clock source\r
+ * @return Asynchronous APB CLock source\r
+ */\r
+__STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc(void)\r
+{\r
+ return (async_clock_src_t)(uint32_t)(ASYNC_SYSCON->ASYNCAPBCLKSELA & 0x3U);\r
+}\r
+/*! @brief Return Frequency of Asynchronous APB Clock\r
+ * @return Frequency of Asynchronous APB Clock Clock\r
+ */\r
+uint32_t CLOCK_GetAsyncApbClkFreq(void);\r
+/*! @brief Return EMC source\r
+ * @return EMC source\r
+ */\r
+__STATIC_INLINE uint32_t CLOCK_GetEmcClkFreq(void)\r
+{\r
+ uint32_t freqtmp;\r
+\r
+ freqtmp = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U);\r
+ return freqtmp / ((SYSCON->EMCCLKDIV & 0xffU) + 1U);\r
+}\r
+/*! @brief Return Audio PLL input clock rate\r
+ * @return Audio PLL input clock rate\r
+ */\r
+uint32_t CLOCK_GetAudioPLLInClockRate(void);\r
+/*! @brief Return System PLL input clock rate\r
+ * @return System PLL input clock rate\r
+ */\r
+uint32_t CLOCK_GetSystemPLLInClockRate(void);\r
+\r
+/*! @brief Return System PLL output clock rate\r
+ * @param recompute : Forces a PLL rate recomputation if true\r
+ * @return System PLL output clock rate\r
+ * @note The PLL rate is cached in the driver in a variable as\r
+ * the rate computation function can take some time to perform. It\r
+ * is recommended to use 'false' with the 'recompute' parameter.\r
+ */\r
+uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute);\r
+\r
+/*! @brief Return System AUDIO PLL output clock rate\r
+ * @param recompute : Forces a AUDIO PLL rate recomputation if true\r
+ * @return System AUDIO PLL output clock rate\r
+ * @note The AUDIO PLL rate is cached in the driver in a variable as\r
+ * the rate computation function can take some time to perform. It\r
+ * is recommended to use 'false' with the 'recompute' parameter.\r
+ */\r
+uint32_t CLOCK_GetAudioPLLOutClockRate(bool recompute);\r
+\r
+/*! @brief Return System USB PLL output clock rate\r
+ * @param recompute : Forces a USB PLL rate recomputation if true\r
+ * @return System USB PLL output clock rate\r
+ * @note The USB PLL rate is cached in the driver in a variable as\r
+ * the rate computation function can take some time to perform. It\r
+ * is recommended to use 'false' with the 'recompute' parameter.\r
+ */\r
+uint32_t CLOCK_GetUsbPLLOutClockRate(bool recompute);\r
+\r
+/*! @brief Enables and disables PLL bypass mode\r
+ * @brief bypass : true to bypass PLL (PLL output = PLL input, false to disable bypass\r
+ * @return System PLL output clock rate\r
+ */\r
+__STATIC_INLINE void CLOCK_SetBypassPLL(bool bypass)\r
+{\r
+ if (bypass)\r
+ {\r
+ SYSCON->SYSPLLCTRL |= (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);\r
+ }\r
+ else\r
+ {\r
+ SYSCON->SYSPLLCTRL &= ~(1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);\r
+ }\r
+}\r
+\r
+/*! @brief Check if PLL is locked or not\r
+ * @return true if the PLL is locked, false if not locked\r
+ */\r
+__STATIC_INLINE bool CLOCK_IsSystemPLLLocked(void)\r
+{\r
+ return (bool)((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) != 0U);\r
+}\r
+\r
+/*! @brief Check if USB PLL is locked or not\r
+ * @return true if the USB PLL is locked, false if not locked\r
+ */\r
+__STATIC_INLINE bool CLOCK_IsUsbPLLLocked(void)\r
+{\r
+ return (bool)((SYSCON->USBPLLSTAT & SYSCON_USBPLLSTAT_LOCK_MASK) != 0U);\r
+}\r
+\r
+/*! @brief Check if AUDIO PLL is locked or not\r
+ * @return true if the AUDIO PLL is locked, false if not locked\r
+ */\r
+__STATIC_INLINE bool CLOCK_IsAudioPLLLocked(void)\r
+{\r
+ return (bool)((SYSCON->AUDPLLSTAT & SYSCON_AUDPLLSTAT_LOCK_MASK) != 0U);\r
+}\r
+\r
+/*! @brief Enables and disables SYS OSC\r
+ * @brief enable : true to enable SYS OSC, false to disable SYS OSC\r
+ */\r
+__STATIC_INLINE void CLOCK_Enable_SysOsc(bool enable)\r
+{\r
+ if (enable)\r
+ {\r
+ SYSCON->PDRUNCFGCLR[0] |= SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;\r
+ SYSCON->PDRUNCFGCLR[1] |= SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;\r
+ }\r
+\r
+ else\r
+ {\r
+ SYSCON->PDRUNCFGSET[0] = SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;\r
+ SYSCON->PDRUNCFGSET[1] = SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;\r
+ }\r
+}\r
+\r
+/*! @brief Store the current PLL rate\r
+ * @param rate: Current rate of the PLL\r
+ * @return Nothing\r
+ **/\r
+void CLOCK_SetStoredPLLClockRate(uint32_t rate);\r
+\r
+/*! @brief Store the current AUDIO PLL rate\r
+ * @param rate: Current rate of the PLL\r
+ * @return Nothing\r
+ **/\r
+void CLOCK_SetStoredAudioPLLClockRate(uint32_t rate);\r
+\r
+/*! @brief PLL configuration structure flags for 'flags' field\r
+ * These flags control how the PLL configuration function sets up the PLL setup structure.<br>\r
+ *\r
+ * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the\r
+ * configuration structure must be assigned with the expected PLL frequency. If the\r
+ * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration\r
+ * function and the driver will determine the PLL rate from the currently selected\r
+ * PLL source. This flag might be used to configure the PLL input clock more accurately\r
+ * when using the WDT oscillator or a more dyanmic CLKIN source.<br>\r
+ *\r
+ * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the\r
+ * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider\r
+ * are not used.<br>\r
+ */\r
+#define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */\r
+#define PLL_CONFIGFLAG_FORCENOFRACT \\r
+ (1U << 2U) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or \\r
+ SS hardware */\r
+\r
+/*! @brief PLL configuration structure\r
+ *\r
+ * This structure can be used to configure the settings for a PLL\r
+ * setup structure. Fill in the desired configuration for the PLL\r
+ * and call the PLL setup function to fill in a PLL setup structure.\r
+ */\r
+typedef struct _pll_config\r
+{\r
+ uint32_t desiredRate; /*!< Desired PLL rate in Hz */\r
+ uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */\r
+ uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */\r
+} pll_config_t;\r
+\r
+/*! @brief PLL setup structure flags for 'flags' field\r
+ * These flags control how the PLL setup function sets up the PLL\r
+ */\r
+#define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */\r
+#define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */\r
+#define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */\r
+\r
+/*! @brief PLL setup structure\r
+ * This structure can be used to pre-build a PLL setup configuration\r
+ * at run-time and quickly set the PLL to the configuration. It can be\r
+ * populated with the PLL setup function. If powering up or waiting\r
+ * for PLL lock, the PLL input clock source should be configured prior\r
+ * to PLL setup.\r
+ */\r
+typedef struct _pll_setup\r
+{\r
+ uint32_t pllctrl; /*!< PLL control register SYSPLLCTRL */\r
+ uint32_t pllndec; /*!< PLL NDEC register SYSPLLNDEC */\r
+ uint32_t pllpdec; /*!< PLL PDEC register SYSPLLPDEC */\r
+ uint32_t pllmdec; /*!< PLL MDEC registers SYSPLLPDEC */\r
+ uint32_t pllRate; /*!< Acutal PLL rate */\r
+ uint32_t audpllfrac; /*!< only aduio PLL has this function*/\r
+ uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */\r
+} pll_setup_t;\r
+\r
+/*! @brief PLL status definitions\r
+ */\r
+typedef enum _pll_error\r
+{\r
+ kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */\r
+ kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */\r
+ kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */\r
+ kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */\r
+ kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */\r
+ kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */\r
+ kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */\r
+ kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */\r
+} pll_error_t;\r
+\r
+/*! @brief USB clock source definition. */\r
+typedef enum _clock_usb_src\r
+{\r
+ kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 or 48 MHz. */\r
+ kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut, /*!< Use System PLL output. */\r
+ kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */\r
+ kCLOCK_UsbSrcUsbPll = (uint32_t)kCLOCK_UsbPll, /*!< Use USB PLL clock. */\r
+\r
+ kCLOCK_UsbSrcNone = SYSCON_USB0CLKSEL_SEL(\r
+ 7U) /*!< Use None, this may be selected in order to reduce power when no output is needed.. */\r
+} clock_usb_src_t;\r
+\r
+/*! @brief USB PDEL Divider. */\r
+typedef enum _usb_pll_psel\r
+{\r
+ pSel_Divide_1 = 0U,\r
+ pSel_Divide_2,\r
+ pSel_Divide_4,\r
+ pSel_Divide_8\r
+} usb_pll_psel;\r
+\r
+/*! @brief PLL setup structure\r
+ * This structure can be used to pre-build a USB PLL setup configuration\r
+ * at run-time and quickly set the usb PLL to the configuration. It can be\r
+ * populated with the USB PLL setup function. If powering up or waiting\r
+ * for USB PLL lock, the PLL input clock source should be configured prior\r
+ * to USB PLL setup.\r
+ */\r
+typedef struct _usb_pll_setup\r
+{\r
+ uint8_t msel; /*!< USB PLL control register msel:1U-256U */\r
+ uint8_t psel; /*!< USB PLL control register psel:only support inter 1U 2U 4U 8U */\r
+ uint8_t nsel; /*!< USB PLL control register nsel:only suppoet inter 1U 2U 3U 4U */\r
+ bool direct; /*!< USB PLL CCO output control */\r
+ bool bypass; /*!< USB PLL inout clock bypass control */\r
+ bool fbsel; /*!< USB PLL ineter mode and non-integer mode control*/\r
+ uint32_t inputRate; /*!< USB PLL input rate */\r
+} usb_pll_setup_t;\r
+\r
+/*! @brief Return System PLL output clock rate from setup structure\r
+ * @param pSetup : Pointer to a PLL setup structure\r
+ * @return System PLL output clock rate the setup structure will generate\r
+ */\r
+uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup);\r
+\r
+/*! @brief Return System AUDIO PLL output clock rate from setup structure\r
+ * @param pSetup : Pointer to a PLL setup structure\r
+ * @return System PLL output clock rate the setup structure will generate\r
+ */\r
+uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup);\r
+\r
+/*! @brief Return System AUDIO PLL output clock rate from audio fractioanl setup structure\r
+ * @param pSetup : Pointer to a PLL setup structure\r
+ * @return System PLL output clock rate the setup structure will generate\r
+ */\r
+uint32_t CLOCK_GetAudioPLLOutFromFractSetup(pll_setup_t *pSetup);\r
+\r
+/*! @brief Return System USB PLL output clock rate from setup structure\r
+ * @param pSetup : Pointer to a PLL setup structure\r
+ * @return System PLL output clock rate the setup structure will generate\r
+ */\r
+uint32_t CLOCK_GetUsbPLLOutFromSetup(const usb_pll_setup_t *pSetup);\r
+\r
+/*! @brief Set PLL output based on the passed PLL setup data\r
+ * @param pControl : Pointer to populated PLL control structure to generate setup with\r
+ * @param pSetup : Pointer to PLL setup structure to be filled\r
+ * @return PLL_ERROR_SUCCESS on success, or PLL setup error code\r
+ * @note Actual frequency for setup may vary from the desired frequency based on the\r
+ * accuracy of input clocks, rounding, non-fractional PLL mode, etc.\r
+ */\r
+pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup);\r
+\r
+/*! @brief Set AUDIO PLL output based on the passed AUDIO PLL setup data\r
+ * @param pControl : Pointer to populated PLL control structure to generate setup with\r
+ * @param pSetup : Pointer to PLL setup structure to be filled\r
+ * @return PLL_ERROR_SUCCESS on success, or PLL setup error code\r
+ * @note Actual frequency for setup may vary from the desired frequency based on the\r
+ * accuracy of input clocks, rounding, non-fractional PLL mode, etc.\r
+ */\r
+pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup);\r
+\r
+/*! @brief Set PLL output from PLL setup structure (precise frequency)\r
+ * @param pSetup : Pointer to populated PLL setup structure\r
+ * @param flagcfg : Flag configuration for PLL config structure\r
+ * @return PLL_ERROR_SUCCESS on success, or PLL setup error code\r
+ * @note This function will power off the PLL, setup the PLL with the\r
+ * new setup data, and then optionally powerup the PLL, wait for PLL lock,\r
+ * and adjust system voltages to the new PLL rate. The function will not\r
+ * alter any source clocks (ie, main systen clock) that may use the PLL,\r
+ * so these should be setup prior to and after exiting the function.\r
+ */\r
+pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);\r
+\r
+/*! @brief Set AUDIO PLL output from AUDIOPLL setup structure (precise frequency)\r
+ * @param pSetup : Pointer to populated PLL setup structure\r
+ * @param flagcfg : Flag configuration for PLL config structure\r
+ * @return PLL_ERROR_SUCCESS on success, or PLL setup error code\r
+ * @note This function will power off the PLL, setup the PLL with the\r
+ * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,\r
+ * and adjust system voltages to the new AUDIOPLL rate. The function will not\r
+ * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,\r
+ * so these should be setup prior to and after exiting the function.\r
+ */\r
+pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);\r
+\r
+/*! @brief Set AUDIO PLL output from AUDIOPLL setup structure using the Audio Fractional divider register(precise\r
+ * frequency)\r
+ * @param pSetup : Pointer to populated PLL setup structure\r
+ * @param flagcfg : Flag configuration for PLL config structure\r
+ * @return PLL_ERROR_SUCCESS on success, or PLL setup error code\r
+ * @note This function will power off the PLL, setup the PLL with the\r
+ * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,\r
+ * and adjust system voltages to the new AUDIOPLL rate. The function will not\r
+ * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,\r
+ * so these should be setup prior to and after exiting the function.\r
+ */\r
+pll_error_t CLOCK_SetupAudioPLLPrecFract(pll_setup_t *pSetup, uint32_t flagcfg);\r
+\r
+/**\r
+ * @brief Set PLL output from PLL setup structure (precise frequency)\r
+ * @param pSetup : Pointer to populated PLL setup structure\r
+ * @return kStatus_PLL_Success on success, or PLL setup error code\r
+ * @note This function will power off the PLL, setup the PLL with the\r
+ * new setup data, and then optionally powerup the PLL, wait for PLL lock,\r
+ * and adjust system voltages to the new PLL rate. The function will not\r
+ * alter any source clocks (ie, main systen clock) that may use the PLL,\r
+ * so these should be setup prior to and after exiting the function.\r
+ */\r
+pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup);\r
+\r
+/**\r
+ * @brief Set Audio PLL output from Audio PLL setup structure (precise frequency)\r
+ * @param pSetup : Pointer to populated PLL setup structure\r
+ * @return kStatus_PLL_Success on success, or Audio PLL setup error code\r
+ * @note This function will power off the PLL, setup the Audio PLL with the\r
+ * new setup data, and then optionally powerup the PLL, wait for Audio PLL lock,\r
+ * and adjust system voltages to the new PLL rate. The function will not\r
+ * alter any source clocks (ie, main systen clock) that may use the Audio PLL,\r
+ * so these should be setup prior to and after exiting the function.\r
+ */\r
+pll_error_t CLOCK_SetAudioPLLFreq(const pll_setup_t *pSetup);\r
+\r
+/**\r
+ * @brief Set USB PLL output from USB PLL setup structure (precise frequency)\r
+ * @param pSetup : Pointer to populated USB PLL setup structure\r
+ * @return kStatus_PLL_Success on success, or USB PLL setup error code\r
+ * @note This function will power off the USB PLL, setup the PLL with the\r
+ * new setup data, and then optionally powerup the USB PLL, wait for USB PLL lock,\r
+ * and adjust system voltages to the new USB PLL rate. The function will not\r
+ * alter any source clocks (ie, usb pll clock) that may use the USB PLL,\r
+ * so these should be setup prior to and after exiting the function.\r
+ */\r
+pll_error_t CLOCK_SetUsbPLLFreq(const usb_pll_setup_t *pSetup);\r
+\r
+/*! @brief Set PLL output based on the multiplier and input frequency\r
+ * @param multiply_by : multiplier\r
+ * @param input_freq : Clock input frequency of the PLL\r
+ * @return Nothing\r
+ * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this\r
+ * function does not disable or enable PLL power, wait for PLL lock,\r
+ * or adjust system voltages. These must be done in the application.\r
+ * The function will not alter any source clocks (ie, main systen clock)\r
+ * that may use the PLL, so these should be setup prior to and after\r
+ * exiting the function.\r
+ */\r
+void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq);\r
+\r
+/*! @brief Disable USB clock.\r
+ *\r
+ * Disable USB clock.\r
+ */\r
+static inline void CLOCK_DisableUsbDevicefs0Clock(clock_ip_name_t clk)\r
+{\r
+ CLOCK_DisableClock(clk);\r
+}\r
+\r
+/*! @brief Enable USB Device FS clock.\r
+ * @param src : clock source\r
+ * @param freq: clock frequency\r
+ * Enable USB Device Full Speed clock.\r
+ */\r
+bool CLOCK_EnableUsbfs0DeviceClock(clock_usb_src_t src, uint32_t freq);\r
+\r
+/*! @brief Enable USB HOST FS clock.\r
+ * @param src : clock source\r
+ * @param freq: clock frequency\r
+ * Enable USB HOST Full Speed clock.\r
+ */\r
+bool CLOCK_EnableUsbfs0HostClock(clock_usb_src_t src, uint32_t freq);\r
+\r
+/*! @brief Set the current Usb PLL Rate\r
+ */\r
+void CLOCK_SetStoredUsbPLLClockRate(uint32_t rate);\r
+\r
+/*! @brief Enable USB Device HS clock.\r
+ * @param src : clock source\r
+ * @param freq: clock frequency\r
+ * Enable USB Device High Speed clock.\r
+ */\r
+bool CLOCK_EnableUsbhs0DeviceClock(clock_usb_src_t src, uint32_t freq);\r
+\r
+/*! @brief Enable USB HOST HS clock.\r
+ * @param src : clock source\r
+ * @param freq: clock frequency\r
+ * Enable USB HOST High Speed clock.\r
+ */\r
+bool CLOCK_EnableUsbhs0HostClock(clock_usb_src_t src, uint32_t freq);\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif /* __cplusplus */\r
+\r
+/*! @} */\r
+\r
+#endif /* _FSL_CLOCK_H_ */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2019 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#include "fsl_common.h"\r
+#define SDK_MEM_MAGIC_NUMBER 12345U\r
+\r
+typedef struct _mem_align_control_block\r
+{\r
+ uint16_t identifier; /*!< Identifier for the memory control block. */\r
+ uint16_t offset; /*!< offset from aligned address to real address */\r
+} mem_align_cb_t;\r
+\r
+/* Component ID definition, used by tools. */\r
+#ifndef FSL_COMPONENT_ID\r
+#define FSL_COMPONENT_ID "platform.drivers.common"\r
+#endif\r
+\r
+#ifndef __GIC_PRIO_BITS\r
+#if defined(ENABLE_RAM_VECTOR_TABLE)\r
+uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)\r
+{\r
+/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */\r
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)\r
+ extern uint32_t Image$$VECTOR_ROM$$Base[];\r
+ extern uint32_t Image$$VECTOR_RAM$$Base[];\r
+ extern uint32_t Image$$RW_m_data$$Base[];\r
+\r
+#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base\r
+#define __VECTOR_RAM Image$$VECTOR_RAM$$Base\r
+#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))\r
+#elif defined(__ICCARM__)\r
+ extern uint32_t __RAM_VECTOR_TABLE_SIZE[];\r
+ extern uint32_t __VECTOR_TABLE[];\r
+ extern uint32_t __VECTOR_RAM[];\r
+#elif defined(__GNUC__)\r
+ extern uint32_t __VECTOR_TABLE[];\r
+ extern uint32_t __VECTOR_RAM[];\r
+ extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];\r
+ uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);\r
+#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */\r
+ uint32_t n;\r
+ uint32_t ret;\r
+ uint32_t irqMaskValue;\r
+\r
+ irqMaskValue = DisableGlobalIRQ();\r
+ if (SCB->VTOR != (uint32_t)__VECTOR_RAM)\r
+ {\r
+ /* Copy the vector table from ROM to RAM */\r
+ for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)\r
+ {\r
+ __VECTOR_RAM[n] = __VECTOR_TABLE[n];\r
+ }\r
+ /* Point the VTOR to the position of vector table */\r
+ SCB->VTOR = (uint32_t)__VECTOR_RAM;\r
+ }\r
+\r
+ ret = __VECTOR_RAM[irq + 16];\r
+ /* make sure the __VECTOR_RAM is noncachable */\r
+ __VECTOR_RAM[irq + 16] = irqHandler;\r
+\r
+ EnableGlobalIRQ(irqMaskValue);\r
+\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+\r
+ return ret;\r
+}\r
+#endif /* ENABLE_RAM_VECTOR_TABLE. */\r
+#endif /* __GIC_PRIO_BITS. */\r
+\r
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))\r
+#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)\r
+\r
+void EnableDeepSleepIRQ(IRQn_Type interrupt)\r
+{\r
+ uint32_t intNumber = (uint32_t)interrupt;\r
+\r
+ uint32_t index = 0;\r
+\r
+ while (intNumber >= 32u)\r
+ {\r
+ index++;\r
+ intNumber -= 32u;\r
+ }\r
+\r
+ SYSCON->STARTERSET[index] = 1u << intNumber;\r
+ EnableIRQ(interrupt); /* also enable interrupt at NVIC */\r
+}\r
+\r
+void DisableDeepSleepIRQ(IRQn_Type interrupt)\r
+{\r
+ uint32_t intNumber = (uint32_t)interrupt;\r
+\r
+ DisableIRQ(interrupt); /* also disable interrupt at NVIC */\r
+ uint32_t index = 0;\r
+\r
+ while (intNumber >= 32u)\r
+ {\r
+ index++;\r
+ intNumber -= 32u;\r
+ }\r
+\r
+ SYSCON->STARTERCLR[index] = 1u << intNumber;\r
+}\r
+#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */\r
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */\r
+\r
+void *SDK_Malloc(size_t size, size_t alignbytes)\r
+{\r
+ mem_align_cb_t *p_cb = NULL;\r
+ uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t);\r
+ union\r
+ {\r
+ void *pointer_value;\r
+ uint32_t unsigned_value;\r
+ } p_align_addr, p_addr;\r
+\r
+ p_addr.pointer_value = malloc(alignedsize);\r
+\r
+ if (p_addr.pointer_value == NULL)\r
+ {\r
+ return NULL;\r
+ }\r
+\r
+ p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes);\r
+\r
+ p_cb = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U);\r
+ p_cb->identifier = SDK_MEM_MAGIC_NUMBER;\r
+ p_cb->offset = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value);\r
+\r
+ return p_align_addr.pointer_value;\r
+}\r
+\r
+void SDK_Free(void *ptr)\r
+{\r
+ union\r
+ {\r
+ void *pointer_value;\r
+ uint32_t unsigned_value;\r
+ } p_free;\r
+ p_free.pointer_value = ptr;\r
+ mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U);\r
+\r
+ if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)\r
+ {\r
+ return;\r
+ }\r
+\r
+ p_free.unsigned_value = p_free.unsigned_value - p_cb->offset;\r
+\r
+ free(p_free.pointer_value);\r
+}\r
+\r
+/*!\r
+ * @brief Delay function bases on while loop, every loop includes three instructions.\r
+ *\r
+ * @param count Counts of loop needed for dalay.\r
+ */\r
+#ifndef __XCC__\r
+#if defined(__CC_ARM) /* This macro is arm v5 specific */\r
+/* clang-format off */\r
+__ASM static void DelayLoop(uint32_t count)\r
+{\r
+loop\r
+ SUBS R0, R0, #1\r
+ CMP R0, #0\r
+ BNE loop\r
+ BX LR\r
+}\r
+/* clang-format on */\r
+#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__)\r
+/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler,\r
+ * use SUB and CMP here for compatibility */\r
+static void DelayLoop(uint32_t count)\r
+{\r
+ __ASM volatile(" MOV R0, %0" : : "r"(count));\r
+ __ASM volatile(\r
+ "loop: \n"\r
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)\r
+ " SUB R0, R0, #1 \n"\r
+#else\r
+ " SUBS R0, R0, #1 \n"\r
+#endif\r
+ " CMP R0, #0 \n"\r
+\r
+ " BNE loop \n");\r
+}\r
+#endif /* defined(__CC_ARM) */\r
+\r
+/*!\r
+ * @brief Delay at least for some time.\r
+ * Please note that, this API uses while loop for delay, different run-time environments make the time not precise,\r
+ * if precise delay count was needed, please implement a new delay function with hardware timer.\r
+ *\r
+ * @param delay_us Delay time in unit of microsecond.\r
+ * @param coreClock_Hz Core clock frequency with Hz.\r
+ */\r
+void SDK_DelayAtLeastUs(uint32_t delay_us, uint32_t coreClock_Hz)\r
+{\r
+ assert(0U != delay_us);\r
+ uint64_t count = USEC_TO_COUNT(delay_us, coreClock_Hz);\r
+ assert(count <= UINT32_MAX);\r
+\r
+ /* Divide value may be different in various environment to ensure delay is precise.\r
+ * Every loop count includes three instructions, due to Cortex-M7 sometimes executes\r
+ * two instructions in one period, through test here set divide 2. Other M cores use\r
+ * divide 4. By the way, divide 2 or 4 could let odd count lost precision, but it does\r
+ * not matter because other instructions outside while loop is enough to fill the time.\r
+ */\r
+#if (__CORTEX_M == 7)\r
+ count = count / 2U;\r
+#else\r
+ count = count / 4U;\r
+#endif\r
+ DelayLoop((uint32_t)count);\r
+}\r
+#endif\r
--- /dev/null
+/*\r
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2019 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#ifndef _FSL_COMMON_H_\r
+#define _FSL_COMMON_H_\r
+\r
+#include <assert.h>\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include <string.h>\r
+#include <stdlib.h>\r
+\r
+#if defined(__ICCARM__)\r
+#include <stddef.h>\r
+#endif\r
+\r
+/*\r
+ * For CMSIS pack RTE.\r
+ * CMSIS pack RTE generates "RTC_Components.h" which contains the statements\r
+ * of the related <RTE_Components_h> element for all selected software components.\r
+ */\r
+#ifdef _RTE_\r
+#include "RTE_Components.h"\r
+#endif\r
+\r
+#include "fsl_device_registers.h"\r
+\r
+/*!\r
+ * @addtogroup ksdk_common\r
+ * @{\r
+ */\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/*! @brief Construct a status code value from a group and code number. */\r
+#define MAKE_STATUS(group, code) ((((group)*100) + (code)))\r
+\r
+/*! @brief Construct the version number for drivers. */\r
+#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))\r
+\r
+/*! @name Driver version */\r
+/*@{*/\r
+/*! @brief common driver version 2.2.2. */\r
+#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 2, 2))\r
+/*@}*/\r
+\r
+/* Debug console type definition. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */\r
+\r
+/*! @brief Status group numbers. */\r
+enum _status_groups\r
+{\r
+ kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */\r
+ kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */\r
+ kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */\r
+ kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */\r
+ kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */\r
+ kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */\r
+ kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */\r
+ kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */\r
+ kStatusGroup_UART = 10, /*!< Group number for UART status codes. */\r
+ kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */\r
+ kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */\r
+ kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */\r
+ kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/\r
+ kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/\r
+ kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/\r
+ kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */\r
+ kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */\r
+ kStatusGroup_SAI = 19, /*!< Group number for SAI status code */\r
+ kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */\r
+ kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */\r
+ kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */\r
+ kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */\r
+ kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */\r
+ kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */\r
+ kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */\r
+ kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */\r
+ kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */\r
+ kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */\r
+ kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */\r
+ kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */\r
+ kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */\r
+ kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */\r
+ kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */\r
+ kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */\r
+ kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */\r
+ kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */\r
+ kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */\r
+ kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */\r
+ kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */\r
+ kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */\r
+ kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */\r
+ kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */\r
+ kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */\r
+ kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */\r
+ kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */\r
+ kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */\r
+ kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/\r
+ kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */\r
+ kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */\r
+ kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */\r
+ kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */\r
+ kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */\r
+ kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/\r
+ kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/\r
+ kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/\r
+ kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/\r
+ kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */\r
+ kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */\r
+ kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */\r
+ kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */\r
+ kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */\r
+ kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */\r
+ kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */\r
+ kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */\r
+ kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */\r
+ kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */\r
+ kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */\r
+ kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */\r
+ kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */\r
+ kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */\r
+ kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */\r
+ kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */\r
+ kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */\r
+\r
+ kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */\r
+ kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */\r
+ kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */\r
+ kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */\r
+ kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */\r
+ kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */\r
+ kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */\r
+ kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */\r
+ kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */\r
+ kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */\r
+ kStatusGroup_LED = 137, /*!< Group number for LED status codes. */\r
+ kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */\r
+ kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */\r
+ kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */\r
+ kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */\r
+ kStatusGroup_LIST = 142, /*!< Group number for List status codes. */\r
+ kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */\r
+ kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */\r
+ kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */\r
+ kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */\r
+ kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/\r
+ kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */\r
+ kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */\r
+ kStatusGroup_OTFAD = 150, /*!< Group number for codec status codes. */\r
+};\r
+\r
+/*! @brief Generic status return codes. */\r
+enum\r
+{\r
+ kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),\r
+ kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),\r
+ kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),\r
+ kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),\r
+ kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),\r
+ kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),\r
+ kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),\r
+};\r
+\r
+/*! @brief Type used for all status and error return values. */\r
+typedef int32_t status_t;\r
+\r
+/*\r
+ * Macro guard for whether to use default weak IRQ implementation in drivers\r
+ */\r
+#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ\r
+#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1\r
+#endif\r
+\r
+/*! @name Min/max macros */\r
+/* @{ */\r
+#if !defined(MIN)\r
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))\r
+#endif\r
+\r
+#if !defined(MAX)\r
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))\r
+#endif\r
+/* @} */\r
+\r
+/*! @brief Computes the number of elements in an array. */\r
+#if !defined(ARRAY_SIZE)\r
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))\r
+#endif\r
+\r
+/*! @name UINT16_MAX/UINT32_MAX value */\r
+/* @{ */\r
+#if !defined(UINT16_MAX)\r
+#define UINT16_MAX ((uint16_t)-1)\r
+#endif\r
+\r
+#if !defined(UINT32_MAX)\r
+#define UINT32_MAX ((uint32_t)-1)\r
+#endif\r
+/* @} */\r
+\r
+/*! @name Timer utilities */\r
+/* @{ */\r
+/*! Macro to convert a microsecond period to raw count value */\r
+#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U)\r
+/*! Macro to convert a raw count value to microsecond */\r
+#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)\r
+\r
+/*! Macro to convert a millisecond period to raw count value */\r
+#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)\r
+/*! Macro to convert a raw count value to millisecond */\r
+#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)\r
+/* @} */\r
+\r
+/*! @name Alignment variable definition macros */\r
+/* @{ */\r
+#if (defined(__ICCARM__))\r
+/**\r
+ * Workaround to disable MISRA C message suppress warnings for IAR compiler.\r
+ * http:/ /supp.iar.com/Support/?note=24725\r
+ */\r
+_Pragma("diag_suppress=Pm120")\r
+#define SDK_PRAGMA(x) _Pragma(#x)\r
+ _Pragma("diag_error=Pm120")\r
+/*! Macro to define a variable with alignbytes alignment */\r
+#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var\r
+/*! Macro to define a variable with L1 d-cache line size alignment */\r
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)\r
+#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var\r
+#endif\r
+/*! Macro to define a variable with L2 cache line size alignment */\r
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)\r
+#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var\r
+#endif\r
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)\r
+/*! Macro to define a variable with alignbytes alignment */\r
+#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var\r
+/*! Macro to define a variable with L1 d-cache line size alignment */\r
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)\r
+#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var\r
+#endif\r
+/*! Macro to define a variable with L2 cache line size alignment */\r
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)\r
+#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var\r
+#endif\r
+#elif defined(__GNUC__)\r
+/*! Macro to define a variable with alignbytes alignment */\r
+#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))\r
+/*! Macro to define a variable with L1 d-cache line size alignment */\r
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)\r
+#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))\r
+#endif\r
+/*! Macro to define a variable with L2 cache line size alignment */\r
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)\r
+#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)))\r
+#endif\r
+#else\r
+#error Toolchain not supported\r
+#define SDK_ALIGN(var, alignbytes) var\r
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)\r
+#define SDK_L1DCACHE_ALIGN(var) var\r
+#endif\r
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)\r
+#define SDK_L2CACHE_ALIGN(var) var\r
+#endif\r
+#endif\r
+\r
+/*! Macro to change a value to a given size aligned value */\r
+#define SDK_SIZEALIGN(var, alignbytes) \\r
+ ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U)))\r
+/* @} */\r
+\r
+/*! @name Non-cacheable region definition macros */\r
+/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or\r
+ * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables,\r
+ * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables\r
+ * will be initialized to zero in system startup.\r
+ */\r
+/* @{ */\r
+#if (defined(__ICCARM__))\r
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))\r
+#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"\r
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"\r
+#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"\r
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"\r
+#else\r
+#define AT_NONCACHEABLE_SECTION(var) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var\r
+#define AT_NONCACHEABLE_SECTION_INIT(var) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var\r
+#endif\r
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))\r
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))\r
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \\r
+ __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var\r
+#if(defined(__CC_ARM))\r
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \\r
+ __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var\r
+#else\r
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \\r
+ __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var\r
+#endif\r
+#else\r
+#define AT_NONCACHEABLE_SECTION(var) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var\r
+#define AT_NONCACHEABLE_SECTION_INIT(var) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var\r
+#endif\r
+#elif(defined(__XCC__))\r
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \\r
+ __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))\r
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \\r
+ __attribute__((section("NonCacheable"))) var __attribute__((aligned(alignbytes)))\r
+#elif(defined(__GNUC__))\r
+/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"\r
+ * in your projects to make sure the non-cacheable section variables will be initialized in system startup.\r
+ */\r
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))\r
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \\r
+ __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))\r
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \\r
+ __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))\r
+#else\r
+#define AT_NONCACHEABLE_SECTION(var) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))\r
+#define AT_NONCACHEABLE_SECTION_INIT(var) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes)))\r
+#endif\r
+#else\r
+#error Toolchain not supported.\r
+#define AT_NONCACHEABLE_SECTION(var) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var\r
+#define AT_NONCACHEABLE_SECTION_INIT(var) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var\r
+#endif\r
+/* @} */\r
+\r
+/*! @name Time sensitive region */\r
+/* @{ */\r
+#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE\r
+#if (defined(__ICCARM__))\r
+#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"\r
+#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess"\r
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))\r
+#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func\r
+#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func\r
+#elif(defined(__GNUC__))\r
+#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func\r
+#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func\r
+#else\r
+#error Toolchain not supported.\r
+#endif /* defined(__ICCARM__) */\r
+#else\r
+#if (defined(__ICCARM__))\r
+#define AT_QUICKACCESS_SECTION_CODE(func) func\r
+#define AT_QUICKACCESS_SECTION_DATA(func) func\r
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))\r
+#define AT_QUICKACCESS_SECTION_CODE(func) func\r
+#define AT_QUICKACCESS_SECTION_DATA(func) func\r
+#elif(defined(__GNUC__))\r
+#define AT_QUICKACCESS_SECTION_CODE(func) func\r
+#define AT_QUICKACCESS_SECTION_DATA(func) func\r
+#else\r
+#error Toolchain not supported.\r
+#endif\r
+#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */\r
+/* @} */\r
+\r
+/*! @name Ram Function */\r
+#if (defined(__ICCARM__))\r
+#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"\r
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))\r
+#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func\r
+#elif(defined(__GNUC__))\r
+#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func\r
+#else\r
+#error Toolchain not supported.\r
+#endif /* defined(__ICCARM__) */\r
+/* @} */\r
+\r
+/*! @name Suppress fallthrough warning macro */\r
+/* For switch case code block, if case section ends without "break;" statement, there wil be\r
+ fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc.\r
+ To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each\r
+ case section which misses "break;"statement.\r
+ */\r
+/* @{ */\r
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)\r
+#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__ ((fallthrough))\r
+#else\r
+#define SUPPRESS_FALL_THROUGH_WARNING()\r
+#endif\r
+/* @} */\r
+\r
+#if defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )\r
+void DefaultISR(void);\r
+#endif\r
+/*\r
+ * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t\r
+ * defined in previous of this file.\r
+ */\r
+#include "fsl_clock.h"\r
+\r
+/*\r
+ * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral\r
+ */\r
+#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \\r
+ (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))\r
+#include "fsl_reset.h"\r
+#endif\r
+\r
+/*******************************************************************************\r
+ * API\r
+ ******************************************************************************/\r
+\r
+#if defined(__cplusplus)\r
+ extern "C"\r
+{\r
+#endif\r
+\r
+ /*!\r
+ * @brief Enable specific interrupt.\r
+ *\r
+ * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt\r
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected\r
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.\r
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed\r
+ * to NVIC first then routed to core.\r
+ *\r
+ * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts\r
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.\r
+ *\r
+ * @param interrupt The IRQ number.\r
+ * @retval kStatus_Success Interrupt enabled successfully\r
+ * @retval kStatus_Fail Failed to enable the interrupt\r
+ */\r
+ static inline status_t EnableIRQ(IRQn_Type interrupt)\r
+ {\r
+ if (NotAvail_IRQn == interrupt)\r
+ {\r
+ return kStatus_Fail;\r
+ }\r
+\r
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)\r
+ if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)\r
+ {\r
+ return kStatus_Fail;\r
+ }\r
+#endif\r
+\r
+#if defined(__GIC_PRIO_BITS)\r
+ GIC_EnableIRQ(interrupt);\r
+#else\r
+ NVIC_EnableIRQ(interrupt);\r
+#endif\r
+ return kStatus_Success;\r
+ }\r
+\r
+ /*!\r
+ * @brief Disable specific interrupt.\r
+ *\r
+ * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt\r
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected\r
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.\r
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed\r
+ * to NVIC first then routed to core.\r
+ *\r
+ * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts\r
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.\r
+ *\r
+ * @param interrupt The IRQ number.\r
+ * @retval kStatus_Success Interrupt disabled successfully\r
+ * @retval kStatus_Fail Failed to disable the interrupt\r
+ */\r
+ static inline status_t DisableIRQ(IRQn_Type interrupt)\r
+ {\r
+ if (NotAvail_IRQn == interrupt)\r
+ {\r
+ return kStatus_Fail;\r
+ }\r
+\r
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)\r
+ if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)\r
+ {\r
+ return kStatus_Fail;\r
+ }\r
+#endif\r
+\r
+#if defined(__GIC_PRIO_BITS)\r
+ GIC_DisableIRQ(interrupt);\r
+#else\r
+ NVIC_DisableIRQ(interrupt);\r
+#endif\r
+ return kStatus_Success;\r
+ }\r
+\r
+ /*!\r
+ * @brief Disable the global IRQ\r
+ *\r
+ * Disable the global interrupt and return the current primask register. User is required to provided the primask\r
+ * register for the EnableGlobalIRQ().\r
+ *\r
+ * @return Current primask value.\r
+ */\r
+ static inline uint32_t DisableGlobalIRQ(void)\r
+ {\r
+#if defined (__XCC__)\r
+ return 0;\r
+#else\r
+#if defined(CPSR_I_Msk)\r
+ uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;\r
+\r
+ __disable_irq();\r
+\r
+ return cpsr;\r
+#else\r
+ uint32_t regPrimask = __get_PRIMASK();\r
+\r
+ __disable_irq();\r
+\r
+ return regPrimask;\r
+#endif\r
+#endif\r
+ }\r
+\r
+ /*!\r
+ * @brief Enable the global IRQ\r
+ *\r
+ * Set the primask register with the provided primask value but not just enable the primask. The idea is for the\r
+ * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to\r
+ * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.\r
+ *\r
+ * @param primask value of primask register to be restored. The primask value is supposed to be provided by the\r
+ * DisableGlobalIRQ().\r
+ */\r
+ static inline void EnableGlobalIRQ(uint32_t primask)\r
+ {\r
+#if defined (__XCC__)\r
+#else\r
+#if defined(CPSR_I_Msk)\r
+ __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);\r
+#else\r
+ __set_PRIMASK(primask);\r
+#endif\r
+#endif\r
+ }\r
+\r
+#if defined(ENABLE_RAM_VECTOR_TABLE)\r
+ /*!\r
+ * @brief install IRQ handler\r
+ *\r
+ * @param irq IRQ number\r
+ * @param irqHandler IRQ handler address\r
+ * @return The old IRQ handler address\r
+ */\r
+ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);\r
+#endif /* ENABLE_RAM_VECTOR_TABLE. */\r
+\r
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))\r
+ /*!\r
+ * @brief Enable specific interrupt for wake-up from deep-sleep mode.\r
+ *\r
+ * Enable the interrupt for wake-up from deep sleep mode.\r
+ * Some interrupts are typically used in sleep mode only and will not occur during\r
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable\r
+ * those clocks (significantly increasing power consumption in the reduced power mode),\r
+ * making these wake-ups possible.\r
+ *\r
+ * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly).\r
+ *\r
+ * @param interrupt The IRQ number.\r
+ */\r
+ void EnableDeepSleepIRQ(IRQn_Type interrupt);\r
+\r
+ /*!\r
+ * @brief Disable specific interrupt for wake-up from deep-sleep mode.\r
+ *\r
+ * Disable the interrupt for wake-up from deep sleep mode.\r
+ * Some interrupts are typically used in sleep mode only and will not occur during\r
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable\r
+ * those clocks (significantly increasing power consumption in the reduced power mode),\r
+ * making these wake-ups possible.\r
+ *\r
+ * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly).\r
+ *\r
+ * @param interrupt The IRQ number.\r
+ */\r
+ void DisableDeepSleepIRQ(IRQn_Type interrupt);\r
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */\r
+\r
+ /*!\r
+ * @brief Allocate memory with given alignment and aligned size.\r
+ *\r
+ * This is provided to support the dynamically allocated memory\r
+ * used in cache-able region.\r
+ * @param size The length required to malloc.\r
+ * @param alignbytes The alignment size.\r
+ * @retval The allocated memory.\r
+ */\r
+ void *SDK_Malloc(size_t size, size_t alignbytes);\r
+\r
+ /*!\r
+ * @brief Free memory.\r
+ *\r
+ * @param ptr The memory to be release.\r
+ */\r
+ void SDK_Free(void *ptr);\r
+\r
+ /*!\r
+ * @brief Delay at least for some time.\r
+ * Please note that, this API uses while loop for delay, different run-time environments make the time not precise,\r
+ * if precise delay count was needed, please implement a new delay function with hardware timer.\r
+ *\r
+ * @param delay_us Delay time in unit of microsecond.\r
+ * @param coreClock_Hz Core clock frequency with Hz.\r
+ */\r
+ void SDK_DelayAtLeastUs(uint32_t delay_us, uint32_t coreClock_Hz);\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif\r
+\r
+/*! @} */\r
+\r
+#endif /* _FSL_COMMON_H_ */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2019 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#include "fsl_emc.h"\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/* Component ID definition, used by tools. */\r
+#ifndef FSL_COMPONENT_ID\r
+#define FSL_COMPONENT_ID "platform.drivers.emc"\r
+#endif\r
+\r
+/*! @brief Define macros for EMC driver. */\r
+#define EMC_REFRESH_CLOCK_PARAM (16U)\r
+#define EMC_SDRAM_WAIT_CYCLES (2000U)\r
+#define EMC_DYNCTL_COLUMNBASE_OFFSET (0U)\r
+#define EMC_DYNCTL_COLUMNBASE_MASK (0x3U)\r
+#define EMC_DYNCTL_COLUMNPLUS_OFFSET (3U)\r
+#define EMC_DYNCTL_COLUMNPLUS_MASK (0x18U)\r
+#define EMC_DYNCTL_BUSWIDTH_MASK (0x80U)\r
+#define EMC_DYNCTL_BUSADDRMAP_MASK (0x20U)\r
+#define EMC_DYNCTL_DEVBANKS_BITS_MASK (0x1cU)\r
+#define EMC_SDRAM_BANKCS_BA0_MASK (uint32_t)(0x2000)\r
+#define EMC_SDRAM_BANKCS_BA1_MASK (uint32_t)(0x4000)\r
+#define EMC_SDRAM_BANKCS_BA_MASK (EMC_SDRAM_BANKCS_BA0_MASK | EMC_SDRAM_BANKCS_BA1_MASK)\r
+#define EMC_DIV_ROUND_UP(n, m) (((n) + (m)-1U) / (m))\r
+\r
+/*******************************************************************************\r
+ * Prototypes\r
+ ******************************************************************************/\r
+/*!\r
+ * @brief Get instance number for EMC module.\r
+ *\r
+ * @param base EMC peripheral base address\r
+ */\r
+static uint32_t EMC_GetInstance(EMC_Type *base);\r
+\r
+/*!\r
+ * @brief Get the clock cycles of EMC clock.\r
+ * The function is used to calculate the multiple of the\r
+ * 16 EMCCLKs between the timer_Ns period.\r
+ *\r
+ * @param base EMC peripheral base address\r
+ * @param timer_Ns The timer/period in unit of nanosecond\r
+ * @param plus The plus added to the register settings to reach the calculated cycles.\r
+ * @return The calculated cycles.\r
+ */\r
+static uint32_t EMC_CalculateTimerCycles(EMC_Type *base, uint32_t timer_Ns, uint32_t plus);\r
+\r
+/*!\r
+ * @brief Get the shift value to shift the mode register content by.\r
+ *\r
+ * @param addrMap EMC address map for the dynamic memory configuration.\r
+ * It is the bit 14 ~ bit 7 of the EMC_DYNAMICCONFIG.\r
+ * @return The offset value to shift the mode register content by.\r
+ */\r
+static uint32_t EMC_ModeOffset(uint32_t addrMap);\r
+\r
+/*******************************************************************************\r
+ * Variables\r
+ ******************************************************************************/\r
+\r
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)\r
+/*! @brief Pointers to EMC clocks for each instance. */\r
+static const clock_ip_name_t s_EMCClock[FSL_FEATURE_SOC_EMC_COUNT] = EMC_CLOCKS;\r
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */\r
+\r
+#if !(defined(FSL_FEATURE_EMC_HAS_NO_RESET) && FSL_FEATURE_EMC_HAS_NO_RESET)\r
+/*! @brief Pointers to EMC resets for each instance. */\r
+static const reset_ip_name_t s_emcResets[] = EMC_RSTS;\r
+#endif\r
+\r
+/*! @brief Pointers to EMC bases for each instance. */\r
+static const EMC_Type *const s_EMCBases[] = EMC_BASE_PTRS;\r
+\r
+/*! @brief Define the start address for each chip controlled by EMC. */\r
+static const uint32_t s_EMCDYCSBases[] = EMC_DYCS_ADDRESS;\r
+/*******************************************************************************\r
+ * Code\r
+ ******************************************************************************/\r
+\r
+static uint32_t EMC_GetInstance(EMC_Type *base)\r
+{\r
+ uint32_t instance;\r
+\r
+ /* Find the instance index from base address mappings. */\r
+ for (instance = 0; instance < ARRAY_SIZE(s_EMCBases); instance++)\r
+ {\r
+ if (s_EMCBases[instance] == base)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ assert(instance < ARRAY_SIZE(s_EMCBases));\r
+\r
+ return instance;\r
+}\r
+\r
+static uint32_t EMC_CalculateTimerCycles(EMC_Type *base, uint32_t timer_Ns, uint32_t plus)\r
+{\r
+ uint32_t cycles;\r
+\r
+ cycles = CLOCK_GetEmcClkFreq() / EMC_HZ_ONEMHZ * timer_Ns;\r
+ cycles = EMC_DIV_ROUND_UP(cycles, EMC_MILLISECS_ONESEC); /* Round up. */\r
+\r
+ /* Decrese according to the plus. */\r
+ if (cycles >= plus)\r
+ {\r
+ cycles = cycles - plus;\r
+ }\r
+ else\r
+ {\r
+ cycles = 0;\r
+ }\r
+\r
+ return cycles;\r
+}\r
+\r
+static uint32_t EMC_ModeOffset(uint32_t addrMap)\r
+{\r
+ uint8_t offset = 0;\r
+ uint32_t columbase = addrMap & EMC_DYNCTL_COLUMNBASE_MASK;\r
+\r
+ /* First calculate the column length. */\r
+ if (columbase == 2U)\r
+ {\r
+ offset = 8;\r
+ }\r
+ else\r
+ {\r
+ if (0U == columbase)\r
+ {\r
+ offset = 9;\r
+ }\r
+ else\r
+ {\r
+ offset = 8;\r
+ }\r
+\r
+ /* Add column length increase check. */\r
+ offset += (uint8_t)((addrMap & EMC_DYNCTL_COLUMNPLUS_MASK) >> EMC_DYNCTL_COLUMNPLUS_OFFSET);\r
+ }\r
+\r
+ /* Add Buswidth/16. */\r
+ if (0U != (addrMap & EMC_DYNCTL_BUSWIDTH_MASK))\r
+ {\r
+ offset += 2U;\r
+ }\r
+ else\r
+ {\r
+ offset += 1U;\r
+ }\r
+\r
+ /* Add bank select bit if the sdram address map mode is RBC(row-bank-column) mode. */\r
+ if (0U == (addrMap & EMC_DYNCTL_BUSADDRMAP_MASK))\r
+ {\r
+ if (0U == (addrMap & EMC_DYNCTL_DEVBANKS_BITS_MASK))\r
+ {\r
+ offset += 1U;\r
+ }\r
+ else\r
+ {\r
+ offset += 2U;\r
+ }\r
+ }\r
+\r
+ return offset;\r
+}\r
+\r
+/*!\r
+ * brief Initializes the basic for EMC.\r
+ * This function ungates the EMC clock, initializes the emc system configure\r
+ * and enable the EMC module. This function must be called in the first step to initialize\r
+ * the external memory.\r
+ *\r
+ * param base EMC peripheral base address.\r
+ * param config The EMC basic configuration.\r
+ */\r
+void EMC_Init(EMC_Type *base, emc_basic_config_t *config)\r
+{\r
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)\r
+ /* Enable the clock. */\r
+ CLOCK_EnableClock((s_EMCClock[EMC_GetInstance(base)]));\r
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */\r
+\r
+#if !(defined(FSL_FEATURE_EMC_HAS_NO_RESET) && FSL_FEATURE_EMC_HAS_NO_RESET)\r
+ /* Reset the EMC module */\r
+ RESET_PeripheralReset(s_emcResets[EMC_GetInstance(base)]);\r
+#endif\r
+\r
+ /* Reset the EMC. */\r
+ SYSCON->PRESETCTRL[2] |= SYSCON_PRESETCTRL_EMC_RESET_MASK;\r
+ SYSCON->PRESETCTRL[2] &= ~SYSCON_PRESETCTRL_EMC_RESET_MASK;\r
+\r
+ /* Set the EMC sytem configure. */\r
+ SYSCON->EMCCLKDIV = SYSCON_EMCCLKDIV_DIV(config->emcClkDiv);\r
+\r
+ SYSCON->EMCSYSCTRL = SYSCON_EMCSYSCTRL_EMCFBCLKINSEL(config->fbClkSrc);\r
+\r
+ /* Set the endian mode. */\r
+ base->CONFIG = (uint32_t)config->endian;\r
+ /* Enable the EMC module with normal memory map mode and normal work mode. */\r
+ base->CONTROL = EMC_CONTROL_E_MASK;\r
+}\r
+\r
+/*!\r
+ * brief Initializes the dynamic memory controller.\r
+ * This function initializes the dynamic memory controller in external memory controller.\r
+ * This function must be called after EMC_Init and before accessing the external dynamic memory.\r
+ *\r
+ * param base EMC peripheral base address.\r
+ * param timing The timing and latency for dynamica memory controller setting. It shall\r
+ * be used for all dynamica memory chips, threfore the worst timing value for all\r
+ * used chips must be given.\r
+ * param configure The EMC dynamic memory controller chip independent configuration pointer.\r
+ * This configuration pointer is actually pointer to a configration array. the array number\r
+ * depends on the "totalChips".\r
+ * param totalChips The total dynamic memory chip numbers been used or the length of the\r
+ * "emc_dynamic_chip_config_t" type memory.\r
+ */\r
+void EMC_DynamicMemInit(EMC_Type *base,\r
+ emc_dynamic_timing_config_t *timing,\r
+ emc_dynamic_chip_config_t *config,\r
+ uint32_t totalChips)\r
+{\r
+ assert(NULL != config);\r
+ assert(NULL != timing);\r
+ assert(totalChips <= EMC_DYNAMIC_MEMDEV_NUM);\r
+\r
+ uint32_t count;\r
+ uint32_t casLatency;\r
+ uint32_t addr;\r
+ uint32_t offset;\r
+ uint32_t data;\r
+ emc_dynamic_chip_config_t *dynamicConfig = config;\r
+\r
+ /* Setting for dynamic memory controller chip independent configuration. */\r
+ for (count = 0; (count < totalChips); count++)\r
+ {\r
+ if (NULL == dynamicConfig)\r
+ {\r
+ break;\r
+ }\r
+ else\r
+ {\r
+ base->DYNAMIC[dynamicConfig->chipIndex].DYNAMICCONFIG =\r
+ EMC_DYNAMIC_DYNAMICCONFIG_MD(dynamicConfig->dynamicDevice) | EMC_ADDRMAP(dynamicConfig->devAddrMap);\r
+ /* Abstract CAS latency from the sdram mode reigster setting values. */\r
+ casLatency = ((uint32_t)dynamicConfig->sdramModeReg & EMC_SDRAM_MODE_CL_MASK) >> EMC_SDRAM_MODE_CL_SHIFT;\r
+ base->DYNAMIC[dynamicConfig->chipIndex].DYNAMICRASCAS =\r
+ EMC_DYNAMIC_DYNAMICRASCAS_RAS(dynamicConfig->rAS_Nclk) | EMC_DYNAMIC_DYNAMICRASCAS_CAS(casLatency);\r
+\r
+ dynamicConfig++;\r
+ }\r
+ }\r
+\r
+ /* Configure the Dynamic Memory controller timing/latency for all chips. */\r
+ base->DYNAMICREADCONFIG = EMC_DYNAMICREADCONFIG_RD(timing->readConfig);\r
+ base->DYNAMICRP = EMC_CalculateTimerCycles(base, timing->tRp_Ns, 1) & EMC_DYNAMICRP_TRP_MASK;\r
+ base->DYNAMICRAS = EMC_CalculateTimerCycles(base, timing->tRas_Ns, 1) & EMC_DYNAMICRAS_TRAS_MASK;\r
+ base->DYNAMICSREX = EMC_CalculateTimerCycles(base, timing->tSrex_Ns, 1) & EMC_DYNAMICSREX_TSREX_MASK;\r
+ base->DYNAMICAPR = EMC_CalculateTimerCycles(base, timing->tApr_Ns, 1) & EMC_DYNAMICAPR_TAPR_MASK;\r
+ base->DYNAMICDAL = EMC_CalculateTimerCycles(base, timing->tDal_Ns, 0) & EMC_DYNAMICDAL_TDAL_MASK;\r
+ base->DYNAMICWR = EMC_CalculateTimerCycles(base, timing->tWr_Ns, 1) & EMC_DYNAMICWR_TWR_MASK;\r
+ base->DYNAMICRC = EMC_CalculateTimerCycles(base, timing->tRc_Ns, 1) & EMC_DYNAMICRC_TRC_MASK;\r
+ base->DYNAMICRFC = EMC_CalculateTimerCycles(base, timing->tRfc_Ns, 1) & EMC_DYNAMICRFC_TRFC_MASK;\r
+ base->DYNAMICXSR = EMC_CalculateTimerCycles(base, timing->tXsr_Ns, 1) & EMC_DYNAMICXSR_TXSR_MASK;\r
+ base->DYNAMICRRD = EMC_CalculateTimerCycles(base, timing->tRrd_Ns, 1) & EMC_DYNAMICRRD_TRRD_MASK;\r
+ base->DYNAMICMRD = EMC_DYNAMICMRD_TMRD((timing->tMrd_Nclk > 0U) ? timing->tMrd_Nclk - 1UL : 0UL);\r
+\r
+ SDK_DelayAtLeastUs(EMC_SDRAM_NOP_DELAY_US, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);\r
+ /* Step 2. issue nop command. */\r
+ base->DYNAMICCONTROL = 0x00000183;\r
+\r
+ SDK_DelayAtLeastUs(EMC_SDRAM_PRECHARGE_DELAY_US, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);\r
+ /* Step 3. issue precharge all command. */\r
+ base->DYNAMICCONTROL = 0x00000103;\r
+\r
+ /* Step 4. issue two auto-refresh command. */\r
+ base->DYNAMICREFRESH = 2;\r
+ SDK_DelayAtLeastUs(EMC_SDRAM_AUTO_REFRESH_DELAY_US, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);\r
+\r
+ base->DYNAMICREFRESH = EMC_CalculateTimerCycles(base, timing->refreshPeriod_Nanosec, 0) / EMC_REFRESH_CLOCK_PARAM;\r
+\r
+ /* Step 5. issue a mode command and set the mode value. */\r
+ base->DYNAMICCONTROL = 0x00000083;\r
+\r
+ /* Calculate the mode settings here and to reach the 8 auto-refresh time requirement. */\r
+ dynamicConfig = config;\r
+ for (count = 0; (count < totalChips); count++)\r
+ {\r
+ if (NULL == dynamicConfig)\r
+ {\r
+ break;\r
+ }\r
+ else\r
+ {\r
+ /* Get the shift value first. */\r
+ offset = EMC_ModeOffset(dynamicConfig->devAddrMap);\r
+ addr = (s_EMCDYCSBases[dynamicConfig->chipIndex] |\r
+ ((uint32_t)(dynamicConfig->sdramModeReg & ~EMC_SDRAM_BANKCS_BA_MASK) << offset));\r
+ /* Set the right mode setting value. */\r
+ data = *(volatile uint32_t *)addr;\r
+ data = data;\r
+ dynamicConfig++;\r
+ }\r
+ }\r
+\r
+ if (kEMC_Sdram != config->dynamicDevice)\r
+ {\r
+ /* Add extended mode register if the low-power sdram is used. */\r
+ base->DYNAMICCONTROL = 0x00000083;\r
+ /* Calculate the mode settings for extended mode register. */\r
+ dynamicConfig = config;\r
+ for (count = 0; (count < totalChips); count++)\r
+ {\r
+ if (NULL == dynamicConfig)\r
+ {\r
+ break;\r
+ }\r
+ else\r
+ {\r
+ /* Get the shift value first. */\r
+ offset = EMC_ModeOffset(dynamicConfig->devAddrMap);\r
+ addr = (s_EMCDYCSBases[dynamicConfig->chipIndex] |\r
+ (((uint32_t)(dynamicConfig->sdramExtModeReg & ~EMC_SDRAM_BANKCS_BA_MASK) |\r
+ EMC_SDRAM_BANKCS_BA1_MASK)\r
+ << offset));\r
+ /* Set the right mode setting value. */\r
+ data = *(volatile uint32_t *)addr;\r
+ data = data;\r
+ dynamicConfig++;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Step 6. issue normal operation command. */\r
+ base->DYNAMICCONTROL = 0x00000000; /* Issue NORMAL command */\r
+\r
+ /* The buffer shall be disabled when do the sdram initialization and\r
+ * enabled after the initialization during normal opeation.\r
+ */\r
+ dynamicConfig = config;\r
+ for (count = 0; (count < totalChips); count++)\r
+ {\r
+ if (NULL == dynamicConfig)\r
+ {\r
+ break;\r
+ }\r
+ else\r
+ {\r
+ base->DYNAMIC[dynamicConfig->chipIndex].DYNAMICCONFIG |= EMC_DYNAMIC_DYNAMICCONFIG_B_MASK;\r
+ dynamicConfig++;\r
+ }\r
+ }\r
+}\r
+\r
+/*!\r
+ * brief Initializes the static memory controller.\r
+ * This function initializes the static memory controller in external memory controller.\r
+ * This function must be called after EMC_Init and before accessing the external static memory.\r
+ *\r
+ * param base EMC peripheral base address.\r
+ * param extWait_Ns The extended wait timeout or the read/write transfer time.\r
+ * This is common for all static memory chips and set with NULL if not required.\r
+ * param configure The EMC static memory controller chip independent configuration pointer.\r
+ * This configuration pointer is actually pointer to a configration array. the array number\r
+ * depends on the "totalChips".\r
+ * param totalChips The total static memory chip numbers been used or the length of the\r
+ * "emc_static_chip_config_t" type memory.\r
+ */\r
+void EMC_StaticMemInit(EMC_Type *base, uint32_t *extWait_Ns, emc_static_chip_config_t *config, uint32_t totalChips)\r
+{\r
+ assert(NULL != config);\r
+\r
+ uint32_t count;\r
+ emc_static_chip_config_t *staticConfig = config;\r
+\r
+ /* Initialize extended wait. */\r
+ if (NULL != extWait_Ns)\r
+ {\r
+ for (count = 0; (count < totalChips) && (staticConfig != NULL); count++)\r
+ {\r
+ assert(0U != (staticConfig->specailConfig & (uint32_t)kEMC_AsynchronosPageEnable));\r
+ }\r
+\r
+ base->STATICEXTENDEDWAIT = EMC_CalculateTimerCycles(base, *extWait_Ns, 1);\r
+ staticConfig++;\r
+ }\r
+\r
+ /* Initialize the static memory chip specific configure. */\r
+ staticConfig = config;\r
+ for (count = 0; (count < totalChips); count++)\r
+ {\r
+ if (NULL == staticConfig)\r
+ {\r
+ break;\r
+ }\r
+ else\r
+ {\r
+ base->STATIC[staticConfig->chipIndex].STATICCONFIG =\r
+ (staticConfig->specailConfig | (uint32_t)staticConfig->memWidth);\r
+ base->STATIC[staticConfig->chipIndex].STATICWAITWEN =\r
+ EMC_CalculateTimerCycles(base, staticConfig->tWaitWriteEn_Ns, 1);\r
+ base->STATIC[staticConfig->chipIndex].STATICWAITOEN =\r
+ EMC_CalculateTimerCycles(base, staticConfig->tWaitOutEn_Ns, 0);\r
+ base->STATIC[staticConfig->chipIndex].STATICWAITRD =\r
+ EMC_CalculateTimerCycles(base, staticConfig->tWaitReadNoPage_Ns, 1);\r
+ base->STATIC[staticConfig->chipIndex].STATICWAITPAGE =\r
+ EMC_CalculateTimerCycles(base, staticConfig->tWaitReadPage_Ns, 1);\r
+ base->STATIC[staticConfig->chipIndex].STATICWAITWR =\r
+ EMC_CalculateTimerCycles(base, staticConfig->tWaitWrite_Ns, 2);\r
+ base->STATIC[staticConfig->chipIndex].STATICWAITTURN =\r
+ EMC_CalculateTimerCycles(base, staticConfig->tWaitTurn_Ns, 1);\r
+\r
+ staticConfig++;\r
+ }\r
+ }\r
+}\r
+\r
+/*!\r
+ * brief Deinitializes the EMC module and gates the clock.\r
+ * This function gates the EMC controller clock. As a result, the EMC\r
+ * module doesn't work after calling this function.\r
+ *\r
+ * param base EMC peripheral base address.\r
+ */\r
+void EMC_Deinit(EMC_Type *base)\r
+{\r
+ /* Deinit the EMC. */\r
+ base->CONTROL &= ~EMC_CONTROL_E_MASK;\r
+\r
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)\r
+ /* Disable the clock. */\r
+ CLOCK_DisableClock(s_EMCClock[EMC_GetInstance(base)]);\r
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */\r
+}\r
--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2019 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+#ifndef _FSL_EMC_H_\r
+#define _FSL_EMC_H_\r
+\r
+#include "fsl_common.h"\r
+\r
+/*!\r
+ * @addtogroup emc\r
+ * @{\r
+ */\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/*! @name Driver version */\r
+/*@{*/\r
+/*! @brief EMC driver version. */\r
+#define FSL_EMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))\r
+/*@}*/\r
+\r
+/*! @brief Define the chip numbers for dynamic and static memory devices. */\r
+#define EMC_STATIC_MEMDEV_NUM (4U)\r
+#define EMC_DYNAMIC_MEMDEV_NUM (4U)\r
+#define EMC_ADDRMAP_SHIFT EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT\r
+#define EMC_ADDRMAP_MASK (EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK | EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK)\r
+#define EMC_ADDRMAP(x) (((uint32_t)(((uint32_t)(x)) << EMC_ADDRMAP_SHIFT)) & EMC_ADDRMAP_MASK)\r
+#define EMC_HZ_ONEMHZ (1000000U)\r
+#define EMC_MILLISECS_ONESEC (1000U)\r
+#define EMC_SDRAM_MODE_CL_SHIFT (4U)\r
+#define EMC_SDRAM_MODE_CL_MASK (0x70U)\r
+/*! @brief EDMA_SDRAM NOP command wait us */\r
+#ifndef EMC_SDRAM_NOP_DELAY_US\r
+#define EMC_SDRAM_NOP_DELAY_US (100U)\r
+#endif\r
+/*! @brief EDMA_SDRAM precharge command wait us */\r
+#ifndef EMC_SDRAM_PRECHARGE_DELAY_US\r
+#define EMC_SDRAM_PRECHARGE_DELAY_US (100U)\r
+#endif\r
+/*! @brief EDMA_SDRAM auto refresh wait us */\r
+#ifndef EMC_SDRAM_AUTO_REFRESH_DELAY_US\r
+#define EMC_SDRAM_AUTO_REFRESH_DELAY_US (50U)\r
+#endif\r
+/*!\r
+ * @brief Define EMC memory width for static memory device.\r
+ */\r
+typedef enum _emc_static_memwidth\r
+{\r
+ kEMC_8BitWidth = 0x0U, /*!< 8 bit memory width. */\r
+ kEMC_16BitWidth, /*!< 16 bit memory width. */\r
+ kEMC_32BitWidth /*!< 32 bit memory width. */\r
+} emc_static_memwidth_t;\r
+\r
+/*!\r
+ * @brief Define EMC static configuration.\r
+ */\r
+typedef enum _emc_static_special_config\r
+{\r
+ kEMC_AsynchronosPageEnable = 0x0008U, /*!< Enable the asynchronous page mode. page length four. */\r
+ kEMC_ActiveHighChipSelect = 0x0040U, /*!< Chip select active high. */\r
+ kEMC_ByteLaneStateAllLow = 0x0080U, /*!< Reads/writes the respective valuie bits in BLS3:0 are low. */\r
+ kEMC_ExtWaitEnable = 0x0100U, /*!< Extended wait enable. */\r
+ kEMC_BufferEnable = 0x80000U /*!< Buffer enable. */\r
+} emc_static_special_config_t;\r
+\r
+/*! @brief EMC dynamic memory device. */\r
+typedef enum _emc_dynamic_device\r
+{\r
+ kEMC_Sdram = 0x0U, /*!< Dynamic memory device: SDRAM. */\r
+ kEMC_Lpsdram, /*!< Dynamic memory device: Low-power SDRAM. */\r
+} emc_dynamic_device_t;\r
+\r
+/*! @brief EMC dynamic read strategy. */\r
+typedef enum _emc_dynamic_read\r
+{\r
+ kEMC_NoDelay = 0x0U, /*!< No delay. */\r
+ kEMC_Cmddelay, /*!< Command delayed strategy, using EMCCLKDELAY. */\r
+ kEMC_CmdDelayPulseOneclk, /*!< Command delayed strategy pluse one clock cycle using EMCCLKDELAY. */\r
+ kEMC_CmddelayPulsetwoclk, /*!< Command delayed strategy pulse two clock cycle using EMCCLKDELAY. */\r
+} emc_dynamic_read_t;\r
+\r
+/*! @brief EMC endian mode. */\r
+typedef enum _emc_endian_mode\r
+{\r
+ kEMC_LittleEndian = 0x0U, /*!< Little endian mode. */\r
+ kEMC_BigEndian, /*!< Big endian mode. */\r
+} emc_endian_mode_t;\r
+\r
+/*! @brief EMC Feedback clock input source select. */\r
+typedef enum _emc_fbclk_src\r
+{\r
+ kEMC_IntloopbackEmcclk = 0U, /*!< Use the internal loop back from EMC_CLK output. */\r
+ kEMC_EMCFbclkInput /*!< Use the external EMC_FBCLK input. */\r
+} emc_fbclk_src_t;\r
+\r
+/*! @brief EMC dynamic timing/delay configure structure. */\r
+typedef struct _emc_dynamic_timing_config\r
+{\r
+ emc_dynamic_read_t readConfig; /* Dynamic read strategy. */\r
+ uint32_t refreshPeriod_Nanosec; /*!< The refresh period in unit of nanosecond. */\r
+ uint32_t tRp_Ns; /*!< Precharge command period in unit of nanosecond. */\r
+ uint32_t tRas_Ns; /*!< Active to precharge command period in unit of nanosecond. */\r
+ uint32_t tSrex_Ns; /*!< Self-refresh exit time in unit of nanosecond. */\r
+ uint32_t tApr_Ns; /*!< Last data out to active command time in unit of nanosecond. */\r
+ uint32_t tDal_Ns; /*!< Data-in to active command in unit of nanosecond. */\r
+ uint32_t tWr_Ns; /*!< Write recovery time in unit of nanosecond. */\r
+ uint32_t tRc_Ns; /*!< Active to active command period in unit of nanosecond. */\r
+ uint32_t tRfc_Ns; /*!< Auto-refresh period and auto-refresh to active command period in unit of nanosecond. */\r
+ uint32_t tXsr_Ns; /*!< Exit self-refresh to active command time in unit of nanosecond. */\r
+ uint32_t tRrd_Ns; /*!< Active bank A to active bank B latency in unit of nanosecond. */\r
+ uint8_t tMrd_Nclk; /*!< Load mode register to active command time in unit of EMCCLK cycles.*/\r
+} emc_dynamic_timing_config_t;\r
+\r
+/*!\r
+ * @brief EMC dynamic memory controller independent chip configuration structure.\r
+ * Please take refer to the address mapping table in the RM in EMC chapter when you\r
+ * set the "devAddrMap". Choose the right Bit 14 Bit12 ~ Bit 7 group in the table\r
+ * according to the bus width/banks/row/colum length for you device.\r
+ * Set devAddrMap with the value make up with the seven bits (bit14 bit12 ~ bit 7)\r
+ * and inset the bit 13 with 0.\r
+ * for example, if the bit 14 and bit12 ~ bit7 is 1000001 is choosen according to the\r
+ * 32bit high-performance bus width with 2 banks, 11 row lwngth, 8 column length.\r
+ * Set devAddrMap with 0x81.\r
+ */\r
+typedef struct _emc_dynamic_chip_config\r
+{\r
+ uint8_t chipIndex; /*!< Chip Index, range from 0 ~ EMC_DYNAMIC_MEMDEV_NUM - 1. */\r
+ emc_dynamic_device_t\r
+ dynamicDevice; /*!< All chips shall use the same device setting. mixed use are not supported. */\r
+ uint8_t rAS_Nclk; /*!< Active to read/write delay tRCD. */\r
+ uint16_t sdramModeReg; /*!< Sdram mode register setting. */\r
+ uint16_t sdramExtModeReg; /*!< Used for low-power sdram device. The extended mode register. */\r
+ uint8_t devAddrMap; /*!< dynamic device address mapping, choose the address mapping for your specific device. */\r
+} emc_dynamic_chip_config_t;\r
+\r
+/*!\r
+ * @brief EMC static memory controller independent chip configuration structure.\r
+ */\r
+typedef struct _emc_static_chip_config\r
+{\r
+ uint8_t chipIndex;\r
+ emc_static_memwidth_t memWidth; /*!< Memory width. */\r
+ uint32_t specailConfig; /*!< Static configuration,a logical OR of "emc_static_special_config_t". */\r
+ uint32_t tWaitWriteEn_Ns; /*!< The delay form chip select to write enable in unit of nanosecond. */\r
+ uint32_t tWaitOutEn_Ns; /*!< The delay from chip selcet to output enable in unit of nanosecond. */\r
+ uint32_t\r
+ tWaitReadNoPage_Ns; /*!< In No-page mode, the delay from chip select to read access in unit of nanosecond. */\r
+ uint32_t tWaitReadPage_Ns; /*!< In page mode, the read after the first read wait states in unit of nanosecond. */\r
+ uint32_t tWaitWrite_Ns; /*!< The delay from chip select to write access in unit of nanosecond. */\r
+ uint32_t tWaitTurn_Ns; /*!< The Bus turn-around time in unit of nanosecond. */\r
+} emc_static_chip_config_t;\r
+\r
+/*!\r
+ * @brief EMC module basic configuration structure.\r
+ *\r
+ * Defines the static memory controller configure structure and\r
+ * uses the EMC_Init() function to make necessary initializations.\r
+ *\r
+ */\r
+typedef struct _emc_basic_config\r
+{\r
+ emc_endian_mode_t endian; /*!< Endian mode . */\r
+ emc_fbclk_src_t fbClkSrc; /*!< The feedback clock source. */\r
+ uint8_t emcClkDiv; /*!< EMC_CLK = AHB_CLK / (emc_clkDiv + 1). */\r
+} emc_basic_config_t;\r
+\r
+/*******************************************************************************\r
+ * API\r
+ ******************************************************************************/\r
+\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif\r
+\r
+/*!\r
+ * @name EMC Initialize and de-initialize opeartion\r
+ * @{\r
+ */\r
+/*!\r
+ * @brief Initializes the basic for EMC.\r
+ * This function ungates the EMC clock, initializes the emc system configure\r
+ * and enable the EMC module. This function must be called in the first step to initialize\r
+ * the external memory.\r
+ *\r
+ * @param base EMC peripheral base address.\r
+ * @param config The EMC basic configuration.\r
+ */\r
+void EMC_Init(EMC_Type *base, emc_basic_config_t *config);\r
+\r
+/*!\r
+ * @brief Initializes the dynamic memory controller.\r
+ * This function initializes the dynamic memory controller in external memory controller.\r
+ * This function must be called after EMC_Init and before accessing the external dynamic memory.\r
+ *\r
+ * @param base EMC peripheral base address.\r
+ * @param timing The timing and latency for dynamica memory controller setting. It shall\r
+ * be used for all dynamica memory chips, threfore the worst timing value for all\r
+ * used chips must be given.\r
+ * @param configure The EMC dynamic memory controller chip independent configuration pointer.\r
+ * This configuration pointer is actually pointer to a configration array. the array number\r
+ * depends on the "totalChips".\r
+ * @param totalChips The total dynamic memory chip numbers been used or the length of the\r
+ * "emc_dynamic_chip_config_t" type memory.\r
+ */\r
+void EMC_DynamicMemInit(EMC_Type *base,\r
+ emc_dynamic_timing_config_t *timing,\r
+ emc_dynamic_chip_config_t *config,\r
+ uint32_t totalChips);\r
+\r
+/*!\r
+ * @brief Initializes the static memory controller.\r
+ * This function initializes the static memory controller in external memory controller.\r
+ * This function must be called after EMC_Init and before accessing the external static memory.\r
+ *\r
+ * @param base EMC peripheral base address.\r
+ * @param extWait_Ns The extended wait timeout or the read/write transfer time.\r
+ * This is common for all static memory chips and set with NULL if not required.\r
+ * @param configure The EMC static memory controller chip independent configuration pointer.\r
+ * This configuration pointer is actually pointer to a configration array. the array number\r
+ * depends on the "totalChips".\r
+ * @param totalChips The total static memory chip numbers been used or the length of the\r
+ * "emc_static_chip_config_t" type memory.\r
+ */\r
+void EMC_StaticMemInit(EMC_Type *base, uint32_t *extWait_Ns, emc_static_chip_config_t *config, uint32_t totalChips);\r
+\r
+/*!\r
+ * @brief Deinitializes the EMC module and gates the clock.\r
+ * This function gates the EMC controller clock. As a result, the EMC\r
+ * module doesn't work after calling this function.\r
+ *\r
+ * @param base EMC peripheral base address.\r
+ */\r
+void EMC_Deinit(EMC_Type *base);\r
+\r
+/* @} */\r
+\r
+/*!\r
+ * @name EMC Basic Operation\r
+ * @{\r
+ */\r
+\r
+/*!\r
+ * @brief Enables/disables the EMC module.\r
+ *\r
+ * @param base EMC peripheral base address.\r
+ * @param enable True enable EMC module, false disable.\r
+ */\r
+static inline void EMC_Enable(EMC_Type *base, bool enable)\r
+{\r
+ if (enable)\r
+ {\r
+ base->CONTROL |= EMC_CONTROL_E_MASK;\r
+ }\r
+ else\r
+ {\r
+ base->CONTROL &= ~EMC_CONTROL_E_MASK;\r
+ }\r
+}\r
+\r
+/*!\r
+ * @brief Enables/disables the EMC Dynaimc memory controller.\r
+ *\r
+ * @param base EMC peripheral base address.\r
+ * @param enable True enable EMC dynamic memory controller, false disable.\r
+ */\r
+static inline void EMC_EnableDynamicMemControl(EMC_Type *base, bool enable)\r
+{\r
+ if (enable)\r
+ {\r
+ base->DYNAMICCONTROL |= (EMC_DYNAMICCONTROL_CE_MASK | EMC_DYNAMICCONTROL_CS_MASK);\r
+ }\r
+ else\r
+ {\r
+ base->DYNAMICCONTROL &= ~(EMC_DYNAMICCONTROL_CE_MASK | EMC_DYNAMICCONTROL_CS_MASK);\r
+ }\r
+}\r
+\r
+/*!\r
+ * @brief Enables/disables the EMC address mirror.\r
+ * Enable the address mirror the EMC_CS1is mirrored to both EMC_CS0\r
+ * and EMC_DYCS0 memory areas. Disable the address mirror enables\r
+ * EMC_cS0 and EMC_DYCS0 memory to be accessed.\r
+ *\r
+ * @param base EMC peripheral base address.\r
+ * @param enable True enable the address mirror, false disable the address mirror.\r
+ */\r
+static inline void EMC_MirrorChipAddr(EMC_Type *base, bool enable)\r
+{\r
+ if (enable)\r
+ {\r
+ base->CONTROL |= EMC_CONTROL_M_MASK;\r
+ }\r
+ else\r
+ {\r
+ base->CONTROL &= ~EMC_CONTROL_M_MASK;\r
+ }\r
+}\r
+\r
+/*!\r
+ * @brief Enter the self-refresh mode for dynamic memory controller.\r
+ * This function provided self-refresh mode enter or exit for application.\r
+ *\r
+ * @param base EMC peripheral base address.\r
+ * @param enable True enter the self-refresh mode, false to exit self-refresh\r
+ * and enter the normal mode.\r
+ */\r
+static inline void EMC_EnterSelfRefreshCommand(EMC_Type *base, bool enable)\r
+{\r
+ if (enable)\r
+ {\r
+ base->DYNAMICCONTROL |= EMC_DYNAMICCONTROL_SR_MASK;\r
+ }\r
+ else\r
+ {\r
+ base->DYNAMICCONTROL &= ~EMC_DYNAMICCONTROL_SR_MASK;\r
+ }\r
+}\r
+\r
+/*!\r
+ * @brief Get the operating mode of the EMC.\r
+ * This function can be used to get the operating mode of the EMC.\r
+ *\r
+ * @param base EMC peripheral base address.\r
+ * @return The EMC in self-refresh mode if true, else in normal mode.\r
+ */\r
+static inline bool EMC_IsInSelfrefreshMode(EMC_Type *base)\r
+{\r
+ return (0U != (base->STATUS & EMC_STATUS_SA_MASK));\r
+}\r
+\r
+/*!\r
+ * @brief Enter/exit the low-power mode.\r
+ *\r
+ * @param base EMC peripheral base address.\r
+ * @param enable True Enter the low-power mode, false exit low-power mode\r
+ * and return to normal mode.\r
+ */\r
+static inline void EMC_EnterLowPowerMode(EMC_Type *base, bool enable)\r
+{\r
+ if (enable)\r
+ {\r
+ base->CONTROL |= EMC_CONTROL_L_MASK;\r
+ }\r
+ else\r
+ {\r
+ base->CONTROL &= ~EMC_CONTROL_L_MASK;\r
+ }\r
+}\r
+\r
+/* @} */\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif\r
+\r
+/*! @}*/\r
+\r
+#endif /* _FSL_EMC_H_*/\r
--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2019 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#include "fsl_common.h"\r
+#include "fsl_flexcomm.h"\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/* Component ID definition, used by tools. */\r
+#ifndef FSL_COMPONENT_ID\r
+#define FSL_COMPONENT_ID "platform.drivers.flexcomm"\r
+#endif\r
+\r
+/*!\r
+ * @brief Used for conversion between `void*` and `uint32_t`.\r
+ */\r
+typedef union pvoid_to_u32\r
+{\r
+ void *pvoid;\r
+ uint32_t u32;\r
+} pvoid_to_u32_t;\r
+\r
+/*******************************************************************************\r
+ * Prototypes\r
+ ******************************************************************************/\r
+/*! @brief Set the FLEXCOMM mode . */\r
+static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock);\r
+\r
+/*! @brief check whether flexcomm supports peripheral type */\r
+static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph);\r
+\r
+/*******************************************************************************\r
+ * Variables\r
+ ******************************************************************************/\r
+\r
+/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */\r
+static flexcomm_irq_handler_t s_flexcommIrqHandler[FSL_FEATURE_SOC_FLEXCOMM_COUNT];\r
+\r
+/*! @brief Pointers to handles for each instance to provide context to interrupt routines */\r
+static void *s_flexcommHandle[FSL_FEATURE_SOC_FLEXCOMM_COUNT];\r
+\r
+/*! @brief Array to map FLEXCOMM instance number to IRQ number. */\r
+IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS;\r
+\r
+/*! @brief Array to map FLEXCOMM instance number to base address. */\r
+static const uint32_t s_flexcommBaseAddrs[FSL_FEATURE_SOC_FLEXCOMM_COUNT] = FLEXCOMM_BASE_ADDRS;\r
+\r
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)\r
+/*! @brief IDs of clock for each FLEXCOMM module */\r
+static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS;\r
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */\r
+\r
+#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET)\r
+/*! @brief Pointers to FLEXCOMM resets for each instance. */\r
+static const reset_ip_name_t s_flexcommResets[] = FLEXCOMM_RSTS;\r
+#endif\r
+\r
+/*******************************************************************************\r
+ * Code\r
+ ******************************************************************************/\r
+\r
+/* check whether flexcomm supports peripheral type */\r
+static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph)\r
+{\r
+ if (periph == FLEXCOMM_PERIPH_NONE)\r
+ {\r
+ return true;\r
+ }\r
+ else if (periph <= FLEXCOMM_PERIPH_I2S_TX)\r
+ {\r
+ return (base->PSELID & (1UL << ((uint32_t)periph + 3U))) > 0UL ? true : false;\r
+ }\r
+ else if (periph == FLEXCOMM_PERIPH_I2S_RX)\r
+ {\r
+ return (base->PSELID & (1U << 7U)) > (uint32_t)0U ? true : false;\r
+ }\r
+ else\r
+ {\r
+ return false;\r
+ }\r
+}\r
+\r
+/* Get the index corresponding to the FLEXCOMM */\r
+/*! brief Returns instance number for FLEXCOMM module with given base address. */\r
+uint32_t FLEXCOMM_GetInstance(void *base)\r
+{\r
+ uint32_t i;\r
+ pvoid_to_u32_t BaseAddr;\r
+ BaseAddr.pvoid = base;\r
+\r
+ for (i = 0U; i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++)\r
+ {\r
+ if (BaseAddr.u32 == s_flexcommBaseAddrs[i])\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ assert(i < FSL_FEATURE_SOC_FLEXCOMM_COUNT);\r
+ return i;\r
+}\r
+\r
+/* Changes FLEXCOMM mode */\r
+static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock)\r
+{\r
+ /* Check whether peripheral type is present */\r
+ if (!FLEXCOMM_PeripheralIsPresent(base, periph))\r
+ {\r
+ return kStatus_OutOfRange;\r
+ }\r
+\r
+ /* Flexcomm is locked to different peripheral type than expected */\r
+ if (((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) != 0U) &&\r
+ ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != (uint32_t)periph))\r
+ {\r
+ return kStatus_Fail;\r
+ }\r
+\r
+ /* Check if we are asked to lock */\r
+ if (lock != 0)\r
+ {\r
+ base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK;\r
+ }\r
+ else\r
+ {\r
+ base->PSELID = (uint32_t)periph;\r
+ }\r
+\r
+ return kStatus_Success;\r
+}\r
+\r
+/*! brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */\r
+status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph)\r
+{\r
+ uint32_t idx = FLEXCOMM_GetInstance(base);\r
+\r
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)\r
+ /* Enable the peripheral clock */\r
+ CLOCK_EnableClock(s_flexcommClocks[idx]);\r
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */\r
+\r
+#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET)\r
+ /* Reset the FLEXCOMM module */\r
+ RESET_PeripheralReset(s_flexcommResets[idx]);\r
+#endif\r
+\r
+ /* Set the FLEXCOMM to given peripheral */\r
+ return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0);\r
+}\r
+\r
+/*! brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM\r
+ * mode */\r
+void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle)\r
+{\r
+ uint32_t instance;\r
+\r
+ /* Look up instance number */\r
+ instance = FLEXCOMM_GetInstance(base);\r
+\r
+ /* Clear handler first to avoid execution of the handler with wrong handle */\r
+ s_flexcommIrqHandler[instance] = NULL;\r
+ s_flexcommHandle[instance] = handle;\r
+ s_flexcommIrqHandler[instance] = handler;\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+\r
+/* IRQ handler functions overloading weak symbols in the startup */\r
+#if defined(FLEXCOMM0)\r
+void FLEXCOMM0_DriverIRQHandler(void)\r
+{\r
+ assert(s_flexcommIrqHandler[0]);\r
+ s_flexcommIrqHandler[0]((uint32_t *)s_flexcommBaseAddrs[0], s_flexcommHandle[0]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+#endif\r
+\r
+#if defined(FLEXCOMM1)\r
+void FLEXCOMM1_DriverIRQHandler(void)\r
+{\r
+ assert(s_flexcommIrqHandler[1]);\r
+ s_flexcommIrqHandler[1]((uint32_t *)s_flexcommBaseAddrs[1], s_flexcommHandle[1]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+#endif\r
+\r
+#if defined(FLEXCOMM2)\r
+void FLEXCOMM2_DriverIRQHandler(void)\r
+{\r
+ assert(s_flexcommIrqHandler[2]);\r
+ s_flexcommIrqHandler[2]((uint32_t *)s_flexcommBaseAddrs[2], s_flexcommHandle[2]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+#endif\r
+\r
+#if defined(FLEXCOMM3)\r
+void FLEXCOMM3_DriverIRQHandler(void)\r
+{\r
+ assert(s_flexcommIrqHandler[3]);\r
+ s_flexcommIrqHandler[3]((uint32_t *)s_flexcommBaseAddrs[3], s_flexcommHandle[3]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+#endif\r
+\r
+#if defined(FLEXCOMM4)\r
+void FLEXCOMM4_DriverIRQHandler(void)\r
+{\r
+ assert(s_flexcommIrqHandler[4]);\r
+ s_flexcommIrqHandler[4]((uint32_t *)s_flexcommBaseAddrs[4], s_flexcommHandle[4]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+\r
+#endif\r
+\r
+#if defined(FLEXCOMM5)\r
+void FLEXCOMM5_DriverIRQHandler(void)\r
+{\r
+ assert(s_flexcommIrqHandler[5]);\r
+ s_flexcommIrqHandler[5]((uint32_t *)s_flexcommBaseAddrs[5], s_flexcommHandle[5]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+#endif\r
+\r
+#if defined(FLEXCOMM6)\r
+void FLEXCOMM6_DriverIRQHandler(void)\r
+{\r
+ assert(s_flexcommIrqHandler[6]);\r
+ s_flexcommIrqHandler[6]((uint32_t *)s_flexcommBaseAddrs[6], s_flexcommHandle[6]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+#endif\r
+\r
+#if defined(FLEXCOMM7)\r
+void FLEXCOMM7_DriverIRQHandler(void)\r
+{\r
+ assert(s_flexcommIrqHandler[7]);\r
+ s_flexcommIrqHandler[7]((uint32_t *)s_flexcommBaseAddrs[7], s_flexcommHandle[7]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+#endif\r
+\r
+#if defined(FLEXCOMM8)\r
+void FLEXCOMM8_DriverIRQHandler(void)\r
+{\r
+ assert(s_flexcommIrqHandler[8]);\r
+ s_flexcommIrqHandler[8]((uint32_t *)s_flexcommBaseAddrs[8], s_flexcommHandle[8]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+#endif\r
+\r
+#if defined(FLEXCOMM9)\r
+void FLEXCOMM9_DriverIRQHandler(void)\r
+{\r
+ assert(s_flexcommIrqHandler[9]);\r
+ s_flexcommIrqHandler[9]((uint32_t *)s_flexcommBaseAddrs[9], s_flexcommHandle[9]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+#endif\r
+\r
+#if defined(FLEXCOMM10)\r
+void FLEXCOMM10_DriverIRQHandler(void)\r
+{\r
+ assert(s_flexcommIrqHandler[10]);\r
+ s_flexcommIrqHandler[10]((uint32_t *)s_flexcommBaseAddrs[10], s_flexcommHandle[10]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+#endif\r
+\r
+#if defined(FLEXCOMM11)\r
+void FLEXCOMM11_DriverIRQHandler(void)\r
+{\r
+ assert(s_flexcommIrqHandler[11]);\r
+ s_flexcommIrqHandler[11]((uint32_t *)s_flexcommBaseAddrs[11], s_flexcommHandle[11]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+#endif\r
+\r
+#if defined(FLEXCOMM12)\r
+void FLEXCOMM12_DriverIRQHandler(void)\r
+{\r
+ assert(s_flexcommIrqHandler[12]);\r
+ s_flexcommIrqHandler[12]((uint32_t *)s_flexcommBaseAddrs[12], s_flexcommHandle[12]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+#endif\r
+\r
+#if defined(FLEXCOMM13)\r
+void FLEXCOMM13_DriverIRQHandler(void)\r
+{\r
+ assert(s_flexcommIrqHandler[13]);\r
+ s_flexcommIrqHandler[13]((uint32_t *)s_flexcommBaseAddrs[13], s_flexcommHandle[13]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+#endif\r
+\r
+#if defined(FLEXCOMM14)\r
+void FLEXCOMM14_DriverIRQHandler(void)\r
+{\r
+ uint32_t instance;\r
+\r
+ /* Look up instance number */\r
+ instance = FLEXCOMM_GetInstance(FLEXCOMM14);\r
+ assert(s_flexcommIrqHandler[instance]);\r
+ s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+#endif\r
+\r
+#if defined(FLEXCOMM15)\r
+void FLEXCOMM15_DriverIRQHandler(void)\r
+{\r
+ uint32_t instance;\r
+\r
+ /* Look up instance number */\r
+ instance = FLEXCOMM_GetInstance(FLEXCOMM15);\r
+ assert(s_flexcommIrqHandler[instance]);\r
+ s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+#endif\r
+\r
+#if defined(FLEXCOMM16)\r
+void FLEXCOMM16_DriverIRQHandler(void)\r
+{\r
+ uint32_t instance;\r
+\r
+ /* Look up instance number */\r
+ instance = FLEXCOMM_GetInstance(FLEXCOMM16);\r
+ assert(s_flexcommIrqHandler[instance]);\r
+ s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+#endif\r
--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2019 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+#ifndef _FSL_FLEXCOMM_H_\r
+#define _FSL_FLEXCOMM_H_\r
+\r
+#include "fsl_common.h"\r
+\r
+/*!\r
+ * @addtogroup flexcomm_driver\r
+ * @{\r
+ */\r
+\r
+/*! @name Driver version */\r
+/*@{*/\r
+/*! @brief FlexCOMM driver version 2.0.2. */\r
+#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))\r
+/*@}*/\r
+\r
+/*! @brief FLEXCOMM peripheral modes. */\r
+typedef enum\r
+{\r
+ FLEXCOMM_PERIPH_NONE, /*!< No peripheral */\r
+ FLEXCOMM_PERIPH_USART, /*!< USART peripheral */\r
+ FLEXCOMM_PERIPH_SPI, /*!< SPI Peripheral */\r
+ FLEXCOMM_PERIPH_I2C, /*!< I2C Peripheral */\r
+ FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */\r
+ FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */\r
+} FLEXCOMM_PERIPH_T;\r
+\r
+/*! @brief Typedef for interrupt handler. */\r
+typedef void (*flexcomm_irq_handler_t)(void *base, void *handle);\r
+\r
+/*! @brief Array with IRQ number for each FLEXCOMM module. */\r
+extern IRQn_Type const kFlexcommIrqs[];\r
+\r
+/*******************************************************************************\r
+ * API\r
+ ******************************************************************************/\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif\r
+\r
+/*! @brief Returns instance number for FLEXCOMM module with given base address. */\r
+uint32_t FLEXCOMM_GetInstance(void *base);\r
+\r
+/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */\r
+status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph);\r
+\r
+/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM\r
+ * mode */\r
+void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle);\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _FSL_FLEXCOMM_H_*/\r
--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2019 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#include "fsl_gpio.h"\r
+\r
+/* Component ID definition, used by tools. */\r
+#ifndef FSL_COMPONENT_ID\r
+#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio"\r
+#endif\r
+\r
+/*******************************************************************************\r
+ * Variables\r
+ ******************************************************************************/\r
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)\r
+/*! @brief Array to map FGPIO instance number to clock name. */\r
+static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS;\r
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */\r
+\r
+#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET)\r
+/*! @brief Pointers to GPIO resets for each instance. */\r
+static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N;\r
+#endif\r
+/*******************************************************************************\r
+ * Prototypes\r
+ ************ ******************************************************************/\r
+\r
+/*******************************************************************************\r
+ * Code\r
+ ******************************************************************************/\r
+/*!\r
+ * brief Initializes the GPIO peripheral.\r
+ *\r
+ * This function ungates the GPIO clock.\r
+ *\r
+ * param base GPIO peripheral base pointer.\r
+ * param port GPIO port number.\r
+ */\r
+void GPIO_PortInit(GPIO_Type *base, uint32_t port)\r
+{\r
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)\r
+ assert(port < ARRAY_SIZE(s_gpioClockName));\r
+\r
+ /* Upgate the GPIO clock */\r
+ CLOCK_EnableClock(s_gpioClockName[port]);\r
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */\r
+#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET)\r
+ /* Reset the GPIO module */\r
+ RESET_PeripheralReset(s_gpioResets[port]);\r
+#endif\r
+}\r
+\r
+/*!\r
+ * brief Initializes a GPIO pin used by the board.\r
+ *\r
+ * To initialize the GPIO, define a pin configuration, either input or output, in the user file.\r
+ * Then, call the GPIO_PinInit() function.\r
+ *\r
+ * This is an example to define an input pin or output pin configuration:\r
+ * code\r
+ * Define a digital input pin configuration,\r
+ * gpio_pin_config_t config =\r
+ * {\r
+ * kGPIO_DigitalInput,\r
+ * 0,\r
+ * }\r
+ * Define a digital output pin configuration,\r
+ * gpio_pin_config_t config =\r
+ * {\r
+ * kGPIO_DigitalOutput,\r
+ * 0,\r
+ * }\r
+ * endcode\r
+ *\r
+ * param base GPIO peripheral base pointer(Typically GPIO)\r
+ * param port GPIO port number\r
+ * param pin GPIO pin number\r
+ * param config GPIO pin configuration pointer\r
+ */\r
+void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config)\r
+{\r
+ if (config->pinDirection == kGPIO_DigitalInput)\r
+ {\r
+#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR)\r
+ base->DIRCLR[port] = 1UL << pin;\r
+#else\r
+ base->DIR[port] &= ~(1UL << pin);\r
+#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/\r
+ }\r
+ else\r
+ {\r
+ /* Set default output value */\r
+ if (config->outputLogic == 0U)\r
+ {\r
+ base->CLR[port] = (1UL << pin);\r
+ }\r
+ else\r
+ {\r
+ base->SET[port] = (1UL << pin);\r
+ }\r
+/* Set pin direction */\r
+#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR)\r
+ base->DIRSET[port] = 1UL << pin;\r
+#else\r
+ base->DIR[port] |= 1UL << pin;\r
+#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/\r
+ }\r
+}\r
+\r
+#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT\r
+/*!\r
+ * @brief Configures the gpio pin interrupt.\r
+ *\r
+ * @param base GPIO base pointer.\r
+ * @param port GPIO port number\r
+ * @param pin GPIO pin number.\r
+ * @param config GPIO pin interrupt configuration..\r
+ */\r
+void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config)\r
+{\r
+ base->INTEDG[port] = base->INTEDG[port] | ((uint32_t)config->mode << pin);\r
+\r
+ base->INTPOL[port] = base->INTPOL[port] | ((uint32_t)config->polarity << pin);\r
+}\r
+\r
+/*!\r
+ * @brief Enables multiple pins interrupt.\r
+ *\r
+ * @param base GPIO base pointer.\r
+ * @param port GPIO port number.\r
+ * @param index GPIO interrupt number.\r
+ * @param mask GPIO pin number macro.\r
+ */\r
+void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask)\r
+{\r
+ if ((uint32_t)kGPIO_InterruptA == index)\r
+ {\r
+ base->INTENA[port] = base->INTENA[port] | mask;\r
+ }\r
+ else if ((uint32_t)kGPIO_InterruptB == index)\r
+ {\r
+ base->INTENB[port] = base->INTENB[port] | mask;\r
+ }\r
+ else\r
+ {\r
+ /*Should not enter here*/\r
+ }\r
+}\r
+\r
+/*!\r
+ * @brief Disables multiple pins interrupt.\r
+ *\r
+ * @param base GPIO base pointer.\r
+ * @param port GPIO port number.\r
+ * @param index GPIO interrupt number.\r
+ * @param mask GPIO pin number macro.\r
+ */\r
+void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask)\r
+{\r
+ if ((uint32_t)kGPIO_InterruptA == index)\r
+ {\r
+ base->INTENA[port] = base->INTENA[port] & ~mask;\r
+ }\r
+ else if ((uint32_t)kGPIO_InterruptB == index)\r
+ {\r
+ base->INTENB[port] = base->INTENB[port] & ~mask;\r
+ }\r
+ else\r
+ {\r
+ /*Should not enter here*/\r
+ }\r
+}\r
+\r
+/*!\r
+ * @brief Clears multiple pins interrupt flag. Status flags are cleared by\r
+ * writing a 1 to the corresponding bit position.\r
+ *\r
+ * @param base GPIO base pointer.\r
+ * @param port GPIO port number.\r
+ * @param index GPIO interrupt number.\r
+ * @param mask GPIO pin number macro.\r
+ */\r
+void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask)\r
+{\r
+ if ((uint32_t)kGPIO_InterruptA == index)\r
+ {\r
+ base->INTSTATA[port] = mask;\r
+ }\r
+ else if ((uint32_t)kGPIO_InterruptB == index)\r
+ {\r
+ base->INTSTATB[port] = mask;\r
+ }\r
+ else\r
+ {\r
+ /*Should not enter here*/\r
+ }\r
+}\r
+\r
+/*!\r
+ * @ Read port interrupt status.\r
+ *\r
+ * @param base GPIO base pointer.\r
+ * @param port GPIO port number\r
+ * @param index GPIO interrupt number.\r
+ * @retval masked GPIO status value\r
+ */\r
+uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index)\r
+{\r
+ uint32_t status = 0U;\r
+\r
+ if ((uint32_t)kGPIO_InterruptA == index)\r
+ {\r
+ status = base->INTSTATA[port];\r
+ }\r
+ else if ((uint32_t)kGPIO_InterruptB == index)\r
+ {\r
+ status = base->INTSTATB[port];\r
+ }\r
+ else\r
+ {\r
+ /*Should not enter here*/\r
+ }\r
+ return status;\r
+}\r
+\r
+/*!\r
+ * @brief Enables the specific pin interrupt.\r
+ *\r
+ * @param base GPIO base pointer.\r
+ * @param port GPIO port number.\r
+ * @param pin GPIO pin number.\r
+ * @param index GPIO interrupt number.\r
+ */\r
+void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index)\r
+{\r
+ if ((uint32_t)kGPIO_InterruptA == index)\r
+ {\r
+ base->INTENA[port] = base->INTENA[port] | (1UL << pin);\r
+ }\r
+ else if ((uint32_t)kGPIO_InterruptB == index)\r
+ {\r
+ base->INTENB[port] = base->INTENB[port] | (1UL << pin);\r
+ }\r
+ else\r
+ {\r
+ /*Should not enter here*/\r
+ }\r
+}\r
+\r
+/*!\r
+ * @brief Disables the specific pin interrupt.\r
+ *\r
+ * @param base GPIO base pointer.\r
+ * @param port GPIO port number.\r
+ * @param pin GPIO pin number.\r
+ * @param index GPIO interrupt number.\r
+ */\r
+void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index)\r
+{\r
+ if ((uint32_t)kGPIO_InterruptA == index)\r
+ {\r
+ base->INTENA[port] = base->INTENA[port] & ~(1UL << pin);\r
+ }\r
+ else if ((uint32_t)kGPIO_InterruptB == index)\r
+ {\r
+ base->INTENB[port] = base->INTENB[port] & ~(1UL << pin);\r
+ }\r
+ else\r
+ {\r
+ /*Should not enter here*/\r
+ }\r
+}\r
+\r
+/*!\r
+ * @brief Clears the specific pin interrupt flag. Status flags are cleared by\r
+ * writing a 1 to the corresponding bit position.\r
+ *\r
+ * @param base GPIO base pointer.\r
+ * @param port GPIO port number.\r
+ * @param index GPIO interrupt number.\r
+ * @param mask GPIO pin number macro.\r
+ */\r
+void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index)\r
+{\r
+ if ((uint32_t)kGPIO_InterruptA == index)\r
+ {\r
+ base->INTSTATA[port] = 1UL << pin;\r
+ }\r
+ else if ((uint32_t)kGPIO_InterruptB == index)\r
+ {\r
+ base->INTSTATB[port] = 1UL << pin;\r
+ }\r
+ else\r
+ {\r
+ /*Should not enter here*/\r
+ }\r
+}\r
+#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2019 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#ifndef _LPC_GPIO_H_\r
+#define _LPC_GPIO_H_\r
+\r
+#include "fsl_common.h"\r
+\r
+/*!\r
+ * @addtogroup lpc_gpio\r
+ * @{\r
+ */\r
+\r
+/*! @file */\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/*! @name Driver version */\r
+/*@{*/\r
+/*! @brief LPC GPIO driver version. */\r
+#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 5))\r
+/*@}*/\r
+\r
+/*! @brief LPC GPIO direction definition */\r
+typedef enum _gpio_pin_direction\r
+{\r
+ kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/\r
+ kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/\r
+} gpio_pin_direction_t;\r
+\r
+/*!\r
+ * @brief The GPIO pin configuration structure.\r
+ *\r
+ * Every pin can only be configured as either output pin or input pin at a time.\r
+ * If configured as a input pin, then leave the outputConfig unused.\r
+ */\r
+typedef struct _gpio_pin_config\r
+{\r
+ gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */\r
+ /* Output configurations, please ignore if configured as a input one */\r
+ uint8_t outputLogic; /*!< Set default output logic, no use in input */\r
+} gpio_pin_config_t;\r
+\r
+#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT)\r
+#define GPIO_PIN_INT_LEVEL 0x00U\r
+#define GPIO_PIN_INT_EDGE 0x01U\r
+\r
+#define PINT_PIN_INT_HIGH_OR_RISE_TRIGGER 0x00U\r
+#define PINT_PIN_INT_LOW_OR_FALL_TRIGGER 0x01U\r
+\r
+/*! @brief GPIO Pin Interrupt enable mode */\r
+typedef enum _gpio_pin_enable_mode\r
+{\r
+ kGPIO_PinIntEnableLevel = GPIO_PIN_INT_LEVEL, /*!< Generate Pin Interrupt on level mode */\r
+ kGPIO_PinIntEnableEdge = GPIO_PIN_INT_EDGE /*!< Generate Pin Interrupt on edge mode */\r
+} gpio_pin_enable_mode_t;\r
+\r
+/*! @brief GPIO Pin Interrupt enable polarity */\r
+typedef enum _gpio_pin_enable_polarity\r
+{\r
+ kGPIO_PinIntEnableHighOrRise =\r
+ PINT_PIN_INT_HIGH_OR_RISE_TRIGGER, /*!< Generate Pin Interrupt on high level or rising edge */\r
+ kGPIO_PinIntEnableLowOrFall =\r
+ PINT_PIN_INT_LOW_OR_FALL_TRIGGER /*!< Generate Pin Interrupt on low level or falling edge */\r
+} gpio_pin_enable_polarity_t;\r
+\r
+/*! @brief LPC GPIO interrupt index definition */\r
+typedef enum _gpio_interrupt_index\r
+{\r
+ kGPIO_InterruptA = 0U, /*!< Set current pin as interrupt A*/\r
+ kGPIO_InterruptB = 1U, /*!< Set current pin as interrupt B*/\r
+} gpio_interrupt_index_t;\r
+\r
+/*! @brief Configures the interrupt generation condition. */\r
+typedef struct _gpio_interrupt_config\r
+{\r
+ uint8_t mode; /* The trigger mode of GPIO interrupts */\r
+ uint8_t polarity; /* The polarity of GPIO interrupts */\r
+} gpio_interrupt_config_t;\r
+#endif\r
+\r
+/*******************************************************************************\r
+ * API\r
+ ******************************************************************************/\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif\r
+\r
+/*! @name GPIO Configuration */\r
+/*@{*/\r
+\r
+/*!\r
+ * @brief Initializes the GPIO peripheral.\r
+ *\r
+ * This function ungates the GPIO clock.\r
+ *\r
+ * @param base GPIO peripheral base pointer.\r
+ * @param port GPIO port number.\r
+ */\r
+void GPIO_PortInit(GPIO_Type *base, uint32_t port);\r
+\r
+/*!\r
+ * @brief Initializes a GPIO pin used by the board.\r
+ *\r
+ * To initialize the GPIO, define a pin configuration, either input or output, in the user file.\r
+ * Then, call the GPIO_PinInit() function.\r
+ *\r
+ * This is an example to define an input pin or output pin configuration:\r
+ * @code\r
+ * Define a digital input pin configuration,\r
+ * gpio_pin_config_t config =\r
+ * {\r
+ * kGPIO_DigitalInput,\r
+ * 0,\r
+ * }\r
+ * Define a digital output pin configuration,\r
+ * gpio_pin_config_t config =\r
+ * {\r
+ * kGPIO_DigitalOutput,\r
+ * 0,\r
+ * }\r
+ * @endcode\r
+ *\r
+ * @param base GPIO peripheral base pointer(Typically GPIO)\r
+ * @param port GPIO port number\r
+ * @param pin GPIO pin number\r
+ * @param config GPIO pin configuration pointer\r
+ */\r
+void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config);\r
+\r
+/*@}*/\r
+\r
+/*! @name GPIO Output Operations */\r
+/*@{*/\r
+\r
+/*!\r
+ * @brief Sets the output level of the one GPIO pin to the logic 1 or 0.\r
+ *\r
+ * @param base GPIO peripheral base pointer(Typically GPIO)\r
+ * @param port GPIO port number\r
+ * @param pin GPIO pin number\r
+ * @param output GPIO pin output logic level.\r
+ * - 0: corresponding pin output low-logic level.\r
+ * - 1: corresponding pin output high-logic level.\r
+ */\r
+static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output)\r
+{\r
+ base->B[port][pin] = output;\r
+}\r
+\r
+/*@}*/\r
+/*! @name GPIO Input Operations */\r
+/*@{*/\r
+\r
+/*!\r
+ * @brief Reads the current input value of the GPIO PIN.\r
+ *\r
+ * @param base GPIO peripheral base pointer(Typically GPIO)\r
+ * @param port GPIO port number\r
+ * @param pin GPIO pin number\r
+ * @retval GPIO port input value\r
+ * - 0: corresponding pin input low-logic level.\r
+ * - 1: corresponding pin input high-logic level.\r
+ */\r
+static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin)\r
+{\r
+ return (uint32_t)base->B[port][pin];\r
+}\r
+\r
+/*@}*/\r
+\r
+/*!\r
+ * @brief Sets the output level of the multiple GPIO pins to the logic 1.\r
+ *\r
+ * @param base GPIO peripheral base pointer(Typically GPIO)\r
+ * @param port GPIO port number\r
+ * @param mask GPIO pin number macro\r
+ */\r
+static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask)\r
+{\r
+ base->SET[port] = mask;\r
+}\r
+\r
+/*!\r
+ * @brief Sets the output level of the multiple GPIO pins to the logic 0.\r
+ *\r
+ * @param base GPIO peripheral base pointer(Typically GPIO)\r
+ * @param port GPIO port number\r
+ * @param mask GPIO pin number macro\r
+ */\r
+static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask)\r
+{\r
+ base->CLR[port] = mask;\r
+}\r
+\r
+/*!\r
+ * @brief Reverses current output logic of the multiple GPIO pins.\r
+ *\r
+ * @param base GPIO peripheral base pointer(Typically GPIO)\r
+ * @param port GPIO port number\r
+ * @param mask GPIO pin number macro\r
+ */\r
+static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask)\r
+{\r
+ base->NOT[port] = mask;\r
+}\r
+\r
+/*@}*/\r
+\r
+/*!\r
+ * @brief Reads the current input value of the whole GPIO port.\r
+ *\r
+ * @param base GPIO peripheral base pointer(Typically GPIO)\r
+ * @param port GPIO port number\r
+ */\r
+static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port)\r
+{\r
+ return (uint32_t)base->PIN[port];\r
+}\r
+\r
+/*@}*/\r
+/*! @name GPIO Mask Operations */\r
+/*@{*/\r
+\r
+/*!\r
+ * @brief Sets port mask, 0 - enable pin, 1 - disable pin.\r
+ *\r
+ * @param base GPIO peripheral base pointer(Typically GPIO)\r
+ * @param port GPIO port number\r
+ * @param mask GPIO pin number macro\r
+ */\r
+static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask)\r
+{\r
+ base->MASK[port] = mask;\r
+}\r
+\r
+/*!\r
+ * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected.\r
+ *\r
+ * @param base GPIO peripheral base pointer(Typically GPIO)\r
+ * @param port GPIO port number\r
+ * @param output GPIO port output value.\r
+ */\r
+static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output)\r
+{\r
+ base->MPIN[port] = output;\r
+}\r
+\r
+/*!\r
+ * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be\r
+ * affected.\r
+ *\r
+ * @param base GPIO peripheral base pointer(Typically GPIO)\r
+ * @param port GPIO port number\r
+ * @retval masked GPIO port value\r
+ */\r
+static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port)\r
+{\r
+ return (uint32_t)base->MPIN[port];\r
+}\r
+\r
+#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT\r
+/*!\r
+ * @brief Configures the gpio pin interrupt.\r
+ *\r
+ * @param base GPIO base pointer.\r
+ * @param port GPIO port number\r
+ * @param pin GPIO pin number.\r
+ * @param config GPIO pin interrupt configuration..\r
+ */\r
+void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config);\r
+\r
+/*!\r
+ * @brief Enables multiple pins interrupt.\r
+ *\r
+ * @param base GPIO base pointer.\r
+ * @param port GPIO port number.\r
+ * @param index GPIO interrupt number.\r
+ * @param mask GPIO pin number macro.\r
+ */\r
+void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask);\r
+\r
+/*!\r
+ * @brief Disables multiple pins interrupt.\r
+ *\r
+ * @param base GPIO base pointer.\r
+ * @param port GPIO port number.\r
+ * @param index GPIO interrupt number.\r
+ * @param mask GPIO pin number macro.\r
+ */\r
+void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask);\r
+\r
+/*!\r
+ * @brief Clears pin interrupt flag. Status flags are cleared by\r
+ * writing a 1 to the corresponding bit position.\r
+ *\r
+ * @param base GPIO base pointer.\r
+ * @param port GPIO port number.\r
+ * @param index GPIO interrupt number.\r
+ * @param mask GPIO pin number macro.\r
+ */\r
+void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask);\r
+\r
+/*!\r
+ * @ Read port interrupt status.\r
+ *\r
+ * @param base GPIO base pointer.\r
+ * @param port GPIO port number\r
+ * @param index GPIO interrupt number.\r
+ * @retval masked GPIO status value\r
+ */\r
+uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index);\r
+\r
+/*!\r
+ * @brief Enables the specific pin interrupt.\r
+ *\r
+ * @param base GPIO base pointer.\r
+ * @param port GPIO port number.\r
+ * @param pin GPIO pin number.\r
+ * @param index GPIO interrupt number.\r
+ */\r
+void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index);\r
+\r
+/*!\r
+ * @brief Disables the specific pin interrupt.\r
+ *\r
+ * @param base GPIO base pointer.\r
+ * @param port GPIO port number.\r
+ * @param pin GPIO pin number.\r
+ * @param index GPIO interrupt number.\r
+ */\r
+void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index);\r
+\r
+/*!\r
+ * @brief Clears the specific pin interrupt flag. Status flags are cleared by\r
+ * writing a 1 to the corresponding bit position.\r
+ *\r
+ * @param base GPIO base pointer.\r
+ * @param port GPIO port number.\r
+ * @param pin GPIO pin number.\r
+ * @param index GPIO interrupt number.\r
+ */\r
+void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index);\r
+\r
+#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */\r
+\r
+/*@}*/\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif\r
+\r
+/*!\r
+ * @}\r
+ */\r
+\r
+#endif /* _LPC_GPIO_H_*/\r
--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2019 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#ifndef _FSL_IOCON_H_\r
+#define _FSL_IOCON_H_\r
+\r
+#include "fsl_common.h"\r
+\r
+/*!\r
+ * @addtogroup lpc_iocon\r
+ * @{\r
+ */\r
+\r
+/*! @file */\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/* Component ID definition, used by tools. */\r
+#ifndef FSL_COMPONENT_ID\r
+#define FSL_COMPONENT_ID "platform.drivers.lpc_iocon"\r
+#endif\r
+\r
+/*! @name Driver version */\r
+/*@{*/\r
+/*! @brief IOCON driver version 2.1.1. */\r
+#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))\r
+/*@}*/\r
+\r
+/**\r
+ * @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format\r
+ */\r
+typedef struct _iocon_group\r
+{\r
+ uint32_t port : 8; /* Pin port */\r
+ uint32_t pin : 8; /* Pin number */\r
+ uint32_t ionumber : 8; /* IO number */\r
+ uint32_t modefunc : 16; /* Function and mode */\r
+} iocon_group_t;\r
+\r
+/**\r
+ * @brief IOCON function and mode selection definitions\r
+ * @note See the User Manual for specific modes and functions supported by the various pins.\r
+ */\r
+#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4)\r
+#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */\r
+#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */\r
+#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */\r
+#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */\r
+#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */\r
+#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */\r
+#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */\r
+#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */\r
+#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */\r
+#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */\r
+#define IOCON_FUNC10 0xA /*!< Selects pin function 10 */\r
+#define IOCON_FUNC11 0xB /*!< Selects pin function 11 */\r
+#define IOCON_FUNC12 0xC /*!< Selects pin function 12 */\r
+#define IOCON_FUNC13 0xD /*!< Selects pin function 13 */\r
+#define IOCON_FUNC14 0xE /*!< Selects pin function 14 */\r
+#define IOCON_FUNC15 0xF /*!< Selects pin function 15 */\r
+#if defined(IOCON_PIO_MODE_SHIFT)\r
+#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */\r
+#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */\r
+#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */\r
+#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_I2CSLEW_SHIFT)\r
+#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */\r
+#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_EGP_SHIFT)\r
+#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */\r
+#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_SLEW_SHIFT)\r
+#define IOCON_SLEW_STANDARD (0x0 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */\r
+#define IOCON_SLEW_FAST (0x1 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_INVERT_SHIFT)\r
+#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_DIGIMODE_SHIFT)\r
+#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */\r
+#define IOCON_DIGITAL_EN \\r
+ (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_FILTEROFF_SHIFT)\r
+#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */\r
+#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_I2CDRIVE_SHIFT)\r
+#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */\r
+#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_OD_SHIFT)\r
+#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_I2CFILTER_SHIFT)\r
+#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */\r
+#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled, */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_ASW_SHIFT)\r
+#define IOCON_AWS_EN (0x1 << IOCON_PIO_ASW_SHIFT) /*!< Enables analog switch function */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_SSEL_SHIFT)\r
+#define IOCON_SSEL_3V3 (0x0 << IOCON_PIO_SSEL_SHIFT) /*!< 3V3 signaling in I2C mode */\r
+#define IOCON_SSEL_1V8 (0x1 << IOCON_PIO_SSEL_SHIFT) /*!< 1V8 signaling in I2C mode */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_ECS_SHIFT)\r
+#define IOCON_ECS_OFF (0x0 << IOCON_PIO_ECS_SHIFT) /*!< IO is an open drain cell */\r
+#define IOCON_ECS_ON (0x1 << IOCON_PIO_ECS_SHIFT) /*!< Pull-up resistor is connected */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_S_MODE_SHIFT)\r
+#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */\r
+#define IOCON_S_MODE_1CLK \\r
+ (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \\r
+ */\r
+#define IOCON_S_MODE_2CLK \\r
+ (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \\r
+ */\r
+#define IOCON_S_MODE_3CLK \\r
+ (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \\r
+ */\r
+#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_CLK_DIV_SHIFT)\r
+#define IOCON_CLKDIV(div) \\r
+ ((div) \\r
+ << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */\r
+#endif\r
+\r
+#else\r
+#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */\r
+#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */\r
+#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */\r
+#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */\r
+#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */\r
+#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */\r
+#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */\r
+#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */\r
+\r
+#if defined(IOCON_PIO_MODE_SHIFT)\r
+#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */\r
+#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */\r
+#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */\r
+#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_I2CSLEW_SHIFT)\r
+#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */\r
+#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_EGP_SHIFT)\r
+#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */\r
+#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_INVERT_SHIFT)\r
+#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_DIGIMODE_SHIFT)\r
+#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */\r
+#define IOCON_DIGITAL_EN \\r
+ (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_FILTEROFF_SHIFT)\r
+#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */\r
+#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_I2CDRIVE_SHIFT)\r
+#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */\r
+#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_OD_SHIFT)\r
+#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_I2CFILTER_SHIFT)\r
+#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */\r
+#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_S_MODE_SHIFT)\r
+#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */\r
+#define IOCON_S_MODE_1CLK \\r
+ (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \\r
+ */\r
+#define IOCON_S_MODE_2CLK \\r
+ (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \\r
+ */\r
+#define IOCON_S_MODE_3CLK \\r
+ (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \\r
+ */\r
+#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_CLK_DIV_SHIFT)\r
+#define IOCON_CLKDIV(div) \\r
+ ((div) \\r
+ << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */\r
+#endif\r
+\r
+#endif\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif\r
+\r
+#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1))\r
+/**\r
+ * @brief Sets I/O Control pin mux\r
+ * @param base : The base of IOCON peripheral on the chip\r
+ * @param ionumber : GPIO number to mux\r
+ * @param modefunc : OR'ed values of type IOCON_*\r
+ * @return Nothing\r
+ */\r
+__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t ionumber, uint32_t modefunc)\r
+{\r
+ base->PIO[ionumber] = modefunc;\r
+}\r
+#else\r
+/**\r
+ * @brief Sets I/O Control pin mux\r
+ * @param base : The base of IOCON peripheral on the chip\r
+ * @param port : GPIO port to mux\r
+ * @param pin : GPIO pin to mux\r
+ * @param modefunc : OR'ed values of type IOCON_*\r
+ * @return Nothing\r
+ */\r
+__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc)\r
+{\r
+ base->PIO[port][pin] = modefunc;\r
+}\r
+#endif\r
+\r
+/**\r
+ * @brief Set all I/O Control pin muxing\r
+ * @param base : The base of IOCON peripheral on the chip\r
+ * @param pinArray : Pointer to array of pin mux selections\r
+ * @param arrayLength : Number of entries in pinArray\r
+ * @return Nothing\r
+ */\r
+__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength)\r
+{\r
+ uint32_t i;\r
+\r
+ for (i = 0; i < arrayLength; i++)\r
+ {\r
+#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1))\r
+ IOCON_PinMuxSet(base, pinArray[i].ionumber, pinArray[i].modefunc);\r
+#else\r
+ IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc);\r
+#endif /* FSL_FEATURE_IOCON_ONE_DIMENSION */\r
+ }\r
+}\r
+\r
+/* @} */\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif\r
+\r
+#endif /* _FSL_IOCON_H_ */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016, NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+#include "fsl_common.h"\r
+#include "fsl_power.h"\r
+/* Component ID definition, used by tools. */\r
+#ifndef FSL_COMPONENT_ID\r
+#define FSL_COMPONENT_ID "platform.drivers.power"\r
+#endif\r
+\r
+/*******************************************************************************\r
+ * Code\r
+ ******************************************************************************/\r
+\r
+/* Empty file since implementation is in header file and power library */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016, NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+#ifndef _FSL_POWER_H_\r
+#define _FSL_POWER_H_\r
+\r
+#include "fsl_common.h"\r
+\r
+/*! @addtogroup power */\r
+/*! @{ */\r
+\r
+/*! @file */\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/*! @name Driver version */\r
+/*@{*/\r
+/*! @brief power driver version 2.0.0. */\r
+#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))\r
+/*@}*/\r
+\r
+#define MAKE_PD_BITS(reg, slot) (((reg) << 8) | (slot))\r
+#define PDRCFG0 0x0U\r
+#define PDRCFG1 0x1U\r
+\r
+typedef enum pd_bits\r
+{\r
+ kPDRUNCFG_LP_REG = MAKE_PD_BITS(PDRCFG0, 2U),\r
+ kPDRUNCFG_PD_FRO_EN = MAKE_PD_BITS(PDRCFG0, 4U),\r
+ kPDRUNCFG_PD_TS = MAKE_PD_BITS(PDRCFG0, 6U),\r
+ kPDRUNCFG_PD_BOD_RESET = MAKE_PD_BITS(PDRCFG0, 7U),\r
+ kPDRUNCFG_PD_BOD_INTR = MAKE_PD_BITS(PDRCFG0, 8U),\r
+ kPDRUNCFG_PD_VD2_ANA = MAKE_PD_BITS(PDRCFG0, 9U),\r
+ kPDRUNCFG_PD_ADC0 = MAKE_PD_BITS(PDRCFG0, 10U),\r
+ kPDRUNCFG_PD_RAM0 = MAKE_PD_BITS(PDRCFG0, 13U),\r
+ kPDRUNCFG_PD_RAM1 = MAKE_PD_BITS(PDRCFG0, 14U),\r
+ kPDRUNCFG_PD_RAM2 = MAKE_PD_BITS(PDRCFG0, 15U),\r
+ kPDRUNCFG_PD_RAM3 = MAKE_PD_BITS(PDRCFG0, 16U),\r
+ kPDRUNCFG_PD_ROM = MAKE_PD_BITS(PDRCFG0, 17U),\r
+ kPDRUNCFG_PD_VDDA = MAKE_PD_BITS(PDRCFG0, 19U),\r
+ kPDRUNCFG_PD_WDT_OSC = MAKE_PD_BITS(PDRCFG0, 20U),\r
+ kPDRUNCFG_PD_USB0_PHY = MAKE_PD_BITS(PDRCFG0, 21U),\r
+ kPDRUNCFG_PD_SYS_PLL0 = MAKE_PD_BITS(PDRCFG0, 22U),\r
+ kPDRUNCFG_PD_VREFP = MAKE_PD_BITS(PDRCFG0, 23U),\r
+ kPDRUNCFG_PD_FLASH_BG = MAKE_PD_BITS(PDRCFG0, 25U),\r
+ kPDRUNCFG_PD_VD3 = MAKE_PD_BITS(PDRCFG0, 26U),\r
+ kPDRUNCFG_PD_VD4 = MAKE_PD_BITS(PDRCFG0, 27U),\r
+ kPDRUNCFG_PD_VD5 = MAKE_PD_BITS(PDRCFG0, 28U),\r
+ kPDRUNCFG_PD_VD6 = MAKE_PD_BITS(PDRCFG0, 29U),\r
+ kPDRUNCFG_REQ_DELAY = MAKE_PD_BITS(PDRCFG0, 30U),\r
+ kPDRUNCFG_FORCE_RBB = MAKE_PD_BITS(PDRCFG0, 31U),\r
+\r
+ kPDRUNCFG_PD_USB1_PHY = MAKE_PD_BITS(PDRCFG1, 0U),\r
+ kPDRUNCFG_PD_USB_PLL = MAKE_PD_BITS(PDRCFG1, 1U),\r
+ kPDRUNCFG_PD_AUDIO_PLL = MAKE_PD_BITS(PDRCFG1, 2U),\r
+ kPDRUNCFG_PD_SYS_OSC = MAKE_PD_BITS(PDRCFG1, 3U),\r
+ kPDRUNCFG_PD_EEPROM = MAKE_PD_BITS(PDRCFG1, 5U),\r
+ kPDRUNCFG_PD_rng = MAKE_PD_BITS(PDRCFG1, 6U),\r
+\r
+ /*\r
+ This enum member has no practical meaning,it is used to avoid MISRA issue,\r
+ user should not trying to use it.\r
+ */\r
+ kPDRUNCFG_ForceUnsigned = (int)0x80000000U,\r
+} pd_bit_t;\r
+\r
+/* Power mode configuration API parameter */\r
+typedef enum _power_mode_config\r
+{\r
+ kPmu_Sleep = 0U,\r
+ kPmu_Deep_Sleep = 1U,\r
+ kPmu_Deep_PowerDown = 2U,\r
+} power_mode_cfg_t;\r
+\r
+/*******************************************************************************\r
+ * API\r
+ ******************************************************************************/\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*!\r
+* @name Power Configuration\r
+* @{\r
+*/\r
+\r
+/*!\r
+ * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral\r
+ *\r
+ * @param en peripheral for which to enable the PDRUNCFG bit\r
+ * @return none\r
+ */\r
+static inline void POWER_EnablePD(pd_bit_t en)\r
+{\r
+ /* PDRUNCFGSET */\r
+ SYSCON->PDRUNCFGSET[((uint32_t)en >> 8UL)] = (1UL << ((uint32_t)en & 0xffU));\r
+}\r
+\r
+/*!\r
+ * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral\r
+ *\r
+ * @param en peripheral for which to disable the PDRUNCFG bit\r
+ * @return none\r
+ */\r
+static inline void POWER_DisablePD(pd_bit_t en)\r
+{\r
+ /* PDRUNCFGCLR */\r
+ SYSCON->PDRUNCFGCLR[((uint32_t)en >> 8UL)] = (1UL << ((uint32_t)en & 0xffU));\r
+}\r
+\r
+/*!\r
+ * @brief API to enable deep sleep bit in the ARM Core.\r
+ *\r
+ * @param none\r
+ * @return none\r
+ */\r
+static inline void POWER_EnableDeepSleep(void)\r
+{\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
+}\r
+\r
+/*!\r
+ * @brief API to disable deep sleep bit in the ARM Core.\r
+ *\r
+ * @param none\r
+ * @return none\r
+ */\r
+static inline void POWER_DisableDeepSleep(void)\r
+{\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
+}\r
+\r
+/*!\r
+ * @brief Power Library API to reload OTP.\r
+ * This API must be called if VD6 is power down\r
+ * and power back again since FROHF TRIM value\r
+ * is store in OTP. If not, when calling FROHF settng\r
+ * API in clock driver then the FROHF clock out put\r
+ * will be inaccurate.\r
+ * @return none\r
+ */\r
+void POWER_OtpReload(void);\r
+\r
+/*!\r
+ * @brief Power Library API to power the PLLs.\r
+ *\r
+ * @param none\r
+ * @return none\r
+ */\r
+void POWER_SetPLL(void);\r
+\r
+/*!\r
+ * @brief Power Library API to power the USB PHY.\r
+ *\r
+ * @param none\r
+ * @return none\r
+ */\r
+void POWER_SetUsbPhy(void);\r
+\r
+/*!\r
+ * @brief Power Library API to enter different power mode.\r
+ *\r
+ * @param exclude_from_pd Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) that needs to be powered on\r
+ * during power mode selected.\r
+ * @return none\r
+ */\r
+void POWER_EnterPowerMode(power_mode_cfg_t mode, uint64_t exclude_from_pd);\r
+\r
+/*!\r
+ * @brief Power Library API to enter sleep mode.\r
+ *\r
+ * @return none\r
+ */\r
+void POWER_EnterSleep(void);\r
+\r
+/*!\r
+ * @brief Power Library API to enter deep sleep mode.\r
+ *\r
+ * @param exclude_from_pd Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) bits that needs to be\r
+ * powered on during deep sleep\r
+ * @return none\r
+ */\r
+void POWER_EnterDeepSleep(uint64_t exclude_from_pd);\r
+\r
+/*!\r
+ * @brief Power Library API to enter deep power down mode.\r
+ *\r
+ * @param exclude_from_pd Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) that needs to be powered on\r
+ during deep power\r
+ * down mode, but this is has no effect as the voltages are cut off.\r
+\r
+ * @return none\r
+ */\r
+void POWER_EnterDeepPowerDown(uint64_t exclude_from_pd);\r
+\r
+/*!\r
+ * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency.\r
+ *\r
+ * @param freq - The desired frequency at which the part would like to operate,\r
+ * note that the voltage and flash wait states should be set before changing frequency\r
+ * @return none\r
+ */\r
+void POWER_SetVoltageForFreq(uint32_t freq);\r
+\r
+/*!\r
+ * @brief Power Library API to return the library version.\r
+ *\r
+ * @param none\r
+ * @return version number of the power library\r
+ */\r
+uint32_t POWER_GetLibVersion(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* _FSL_POWER_H_ */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016, NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#include "fsl_common.h"\r
+#include "fsl_reset.h"\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+/* Component ID definition, used by tools. */\r
+#ifndef FSL_COMPONENT_ID\r
+#define FSL_COMPONENT_ID "platform.drivers.reset"\r
+#endif\r
+\r
+/*******************************************************************************\r
+ * Variables\r
+ ******************************************************************************/\r
+\r
+/*******************************************************************************\r
+ * Prototypes\r
+ ******************************************************************************/\r
+\r
+/*******************************************************************************\r
+ * Code\r
+ ******************************************************************************/\r
+\r
+#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \\r
+ (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))\r
+\r
+/*!\r
+ * brief Assert reset to peripheral.\r
+ *\r
+ * Asserts reset signal to specified peripheral module.\r
+ *\r
+ * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register\r
+ * and reset bit position in the reset register.\r
+ */\r
+void RESET_SetPeripheralReset(reset_ip_name_t peripheral)\r
+{\r
+ const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;\r
+ const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);\r
+ const uint32_t bitMask = 1UL << bitPos;\r
+\r
+ assert(bitPos < 32UL);\r
+\r
+ /* ASYNC_SYSCON registers have offset 1024 */\r
+ if (regIndex >= SYSCON_PRESETCTRL_COUNT)\r
+ {\r
+ /* reset register is in ASYNC_SYSCON */\r
+\r
+ /* set bit */\r
+ ASYNC_SYSCON->ASYNCPRESETCTRLSET = bitMask;\r
+ /* wait until it reads 0b1 */\r
+ while (0u == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask))\r
+ {\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* reset register is in SYSCON */\r
+\r
+ /* set bit */\r
+ SYSCON->PRESETCTRLSET[regIndex] = bitMask;\r
+ /* wait until it reads 0b1 */\r
+ while (0u == (SYSCON->PRESETCTRL[regIndex] & bitMask))\r
+ {\r
+ }\r
+ }\r
+}\r
+\r
+/*!\r
+ * brief Clear reset to peripheral.\r
+ *\r
+ * Clears reset signal to specified peripheral module, allows it to operate.\r
+ *\r
+ * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register\r
+ * and reset bit position in the reset register.\r
+ */\r
+void RESET_ClearPeripheralReset(reset_ip_name_t peripheral)\r
+{\r
+ const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;\r
+ const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);\r
+ const uint32_t bitMask = 1UL << bitPos;\r
+\r
+ assert(bitPos < 32UL);\r
+\r
+ /* ASYNC_SYSCON registers have offset 1024 */\r
+ if (regIndex >= SYSCON_PRESETCTRL_COUNT)\r
+ {\r
+ /* reset register is in ASYNC_SYSCON */\r
+\r
+ /* clear bit */\r
+ ASYNC_SYSCON->ASYNCPRESETCTRLCLR = bitMask;\r
+ /* wait until it reads 0b0 */\r
+ while (bitMask == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask))\r
+ {\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* reset register is in SYSCON */\r
+\r
+ /* clear bit */\r
+ SYSCON->PRESETCTRLCLR[regIndex] = bitMask;\r
+ /* wait until it reads 0b0 */\r
+ while (bitMask == (SYSCON->PRESETCTRL[regIndex] & bitMask))\r
+ {\r
+ }\r
+ }\r
+}\r
+\r
+/*!\r
+ * brief Reset peripheral module.\r
+ *\r
+ * Reset peripheral module.\r
+ *\r
+ * param peripheral Peripheral to reset. The enum argument contains encoding of reset register\r
+ * and reset bit position in the reset register.\r
+ */\r
+void RESET_PeripheralReset(reset_ip_name_t peripheral)\r
+{\r
+ RESET_SetPeripheralReset(peripheral);\r
+ RESET_ClearPeripheralReset(peripheral);\r
+}\r
+\r
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016, NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#ifndef _FSL_RESET_H_\r
+#define _FSL_RESET_H_\r
+\r
+#include <assert.h>\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include <string.h>\r
+#include "fsl_device_registers.h"\r
+\r
+/*! @addtogroup reset */\r
+/*! @{ */\r
+\r
+/*! @file */\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/*! @name Driver version */\r
+/*@{*/\r
+/*! @brief reset driver version 2.0.1. */\r
+#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))\r
+/*@}*/\r
+\r
+/*!\r
+ * @brief Enumeration for peripheral reset control bits\r
+ *\r
+ * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers\r
+ */\r
+typedef enum _SYSCON_RSTn\r
+{\r
+ kSPIFI_RST_SHIFT_RSTn = 0 | 10U, /**< SPIFI reset control */\r
+ kMUX_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux reset control */\r
+ kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */\r
+ kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */\r
+ kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */\r
+ kGPIO2_RST_SHIFT_RSTn = 0 | 16U, /**< GPIO2 reset control */\r
+ kGPIO3_RST_SHIFT_RSTn = 0 | 17U, /**< GPIO3 reset control */\r
+ kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */\r
+ kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */\r
+ kDMA_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */\r
+ kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */\r
+ kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */\r
+ kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */\r
+\r
+ kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */\r
+ kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */\r
+ kMCAN0_RST_SHIFT_RSTn = 65536 | 7U, /**< MCAN0 reset control */\r
+ kMCAN1_RST_SHIFT_RSTn = 65536 | 8U, /**< MCAN1 reset control */\r
+ kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */\r
+ kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */\r
+ kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */\r
+ kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */\r
+ kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */\r
+ kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */\r
+ kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */\r
+ kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */\r
+ kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */\r
+ kDMIC_RST_SHIFT_RSTn = 65536 | 19U, /**< Digital microphone interface reset control */\r
+ kCT32B2_RST_SHIFT_RSTn = 65536 | 22U, /**< CT32B2 reset control */\r
+ kUSB0D_RST_SHIFT_RSTn = 65536 | 25U, /**< USB0D reset control */\r
+ kCT32B0_RST_SHIFT_RSTn = 65536 | 26U, /**< CT32B0 reset control */\r
+ kCT32B1_RST_SHIFT_RSTn = 65536 | 27U, /**< CT32B1 reset control */\r
+\r
+ kLCD_RST_SHIFT_RSTn = 131072 | 2U, /**< LCD reset control */\r
+ kSDIO_RST_SHIFT_RSTn = 131072 | 3U, /**< SDIO reset control */\r
+ kUSB1H_RST_SHIFT_RSTn = 131072 | 4U, /**< USB1H reset control */\r
+ kUSB1D_RST_SHIFT_RSTn = 131072 | 5U, /**< USB1D reset control */\r
+ kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U, /**< USB1RAM reset control */\r
+ kEMC_RST_SHIFT_RSTn = 131072 | 7U, /**< EMC reset control */\r
+ kETH_RST_SHIFT_RSTn = 131072 | 8U, /**< ETH reset control */\r
+ kGPIO4_RST_SHIFT_RSTn = 131072 | 9U, /**< GPIO4 reset control */\r
+ kGPIO5_RST_SHIFT_RSTn = 131072 | 10U, /**< GPIO5 reset control */\r
+ kAES_RST_SHIFT_RSTn = 131072 | 11U, /**< AES reset control */\r
+ kOTP_RST_SHIFT_RSTn = 131072 | 12U, /**< OTP reset control */\r
+ kRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< RNG reset control */\r
+ kFC8_RST_SHIFT_RSTn = 131072 | 14U, /**< Flexcomm Interface 8 reset control */\r
+ kFC9_RST_SHIFT_RSTn = 131072 | 15U, /**< Flexcomm Interface 9 reset control */\r
+ kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U, /**< USB0HMR reset control */\r
+ kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U, /**< USB0HSL reset control */\r
+ kSHA_RST_SHIFT_RSTn = 131072 | 18U, /**< SHA reset control */\r
+ kSC0_RST_SHIFT_RSTn = 131072 | 19U, /**< SC0 reset control */\r
+ kSC1_RST_SHIFT_RSTn = 131072 | 20U, /**< SC1 reset control */\r
+ kFC10_RST_SHIFT_RSTn = 131072 | 21U, /**< Flexcomm Interface 10 reset control */\r
+\r
+ kCT32B3_RST_SHIFT_RSTn = 67108864 | 13U, /**< CT32B3 reset control */\r
+ kCT32B4_RST_SHIFT_RSTn = 67108864 | 14U, /**< CT32B4 reset control */\r
+} SYSCON_RSTn_t;\r
+\r
+/** Array initializers with peripheral reset bits **/\r
+#define ADC_RSTS \\r
+ { \\r
+ kADC0_RST_SHIFT_RSTn \\r
+ } /* Reset bits for ADC peripheral */\r
+#define AES_RSTS \\r
+ { \\r
+ kAES_RST_SHIFT_RSTn \\r
+ } /* Reset bits for AES peripheral */\r
+#define CRC_RSTS \\r
+ { \\r
+ kCRC_RST_SHIFT_RSTn \\r
+ } /* Reset bits for CRC peripheral */\r
+#define CTIMER_RSTS \\r
+ { \\r
+ kCT32B0_RST_SHIFT_RSTn, kCT32B1_RST_SHIFT_RSTn, kCT32B2_RST_SHIFT_RSTn, kCT32B3_RST_SHIFT_RSTn, \\r
+ kCT32B4_RST_SHIFT_RSTn \\r
+ } /* Reset bits for CTIMER peripheral */\r
+#define DMA_RSTS_N \\r
+ { \\r
+ kDMA_RST_SHIFT_RSTn \\r
+ } /* Reset bits for DMA peripheral */\r
+#define DMIC_RSTS \\r
+ { \\r
+ kDMIC_RST_SHIFT_RSTn \\r
+ } /* Reset bits for DMIC peripheral */\r
+#define EMC_RSTS \\r
+ { \\r
+ kEMC_RST_SHIFT_RSTn \\r
+ } /* Reset bits for EMC peripheral */\r
+#define ETH_RST \\r
+ { \\r
+ kETH_RST_SHIFT_RSTn \\r
+ } /* Reset bits for EMC peripheral */\r
+#define FLEXCOMM_RSTS \\r
+ { \\r
+ kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \\r
+ kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kFC8_RST_SHIFT_RSTn, kFC9_RST_SHIFT_RSTn, kFC9_RST_SHIFT_RSTn \\r
+ } /* Reset bits for FLEXCOMM peripheral */\r
+#define GINT_RSTS \\r
+ { \\r
+ kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \\r
+ } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */\r
+#define GPIO_RSTS_N \\r
+ { \\r
+ kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \\r
+ kGPIO4_RST_SHIFT_RSTn, kGPIO5_RST_SHIFT_RSTn \\r
+ } /* Reset bits for GPIO peripheral */\r
+#define INPUTMUX_RSTS \\r
+ { \\r
+ kMUX_RST_SHIFT_RSTn \\r
+ } /* Reset bits for INPUTMUX peripheral */\r
+#define IOCON_RSTS \\r
+ { \\r
+ kIOCON_RST_SHIFT_RSTn \\r
+ } /* Reset bits for IOCON peripheral */\r
+#define FLASH_RSTS \\r
+ { \\r
+ kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \\r
+ } /* Reset bits for Flash peripheral */\r
+#define LCD_RSTS \\r
+ { \\r
+ kLCD_RST_SHIFT_RSTn \\r
+ } /* Reset bits for LCD peripheral */\r
+#define MRT_RSTS \\r
+ { \\r
+ kMRT_RST_SHIFT_RSTn \\r
+ } /* Reset bits for MRT peripheral */\r
+#define MCAN_RSTS \\r
+ { \\r
+ kMCAN0_RST_SHIFT_RSTn,kMCAN1_RST_SHIFT_RSTn \\r
+ } /* Reset bits for MCAN0&MACN1 peripheral */\r
+#define OTP_RSTS \\r
+ { \\r
+ kOTP_RST_SHIFT_RSTn \\r
+ } /* Reset bits for OTP peripheral */\r
+#define PINT_RSTS \\r
+ { \\r
+ kPINT_RST_SHIFT_RSTn \\r
+ } /* Reset bits for PINT peripheral */\r
+#define RNG_RSTS \\r
+ { \\r
+ kRNG_RST_SHIFT_RSTn \\r
+ } /* Reset bits for RNG peripheral */\r
+#define SDIO_RST \\r
+ { \\r
+ kSDIO_RST_SHIFT_RSTn \\r
+ } /* Reset bits for SDIO peripheral */\r
+#define SCT_RSTS \\r
+ { \\r
+ kSCT0_RST_SHIFT_RSTn \\r
+ } /* Reset bits for SCT peripheral */\r
+#define SHA_RST \\r
+ { \\r
+ kSHA_RST_SHIFT_RSTn \\r
+ } /* Reset bits for SHA peripheral */\r
+#define SPIFI_RSTS \\r
+ { \\r
+ kSPIFI_RST_SHIFT_RSTn \\r
+ } /* Reset bits for SPIFI peripheral */\r
+#define USB0D_RST \\r
+ { \\r
+ kUSB0D_RST_SHIFT_RSTn \\r
+ } /* Reset bits for USB0D peripheral */\r
+#define USB0HMR_RST \\r
+ { \\r
+ kUSB0HMR_RST_SHIFT_RSTn \\r
+ } /* Reset bits for USB0HMR peripheral */\r
+#define USB0HSL_RST \\r
+ { \\r
+ kUSB0HSL_RST_SHIFT_RSTn \\r
+ } /* Reset bits for USB0HSL peripheral */\r
+#define USB1H_RST \\r
+ { \\r
+ kUSB1H_RST_SHIFT_RSTn \\r
+ } /* Reset bits for USB1H peripheral */\r
+#define USB1D_RST \\r
+ { \\r
+ kUSB1D_RST_SHIFT_RSTn \\r
+ } /* Reset bits for USB1D peripheral */\r
+#define USB1RAM_RST \\r
+ { \\r
+ kUSB1RAM_RST_SHIFT_RSTn \\r
+ } /* Reset bits for USB1RAM peripheral */\r
+#define UTICK_RSTS \\r
+ { \\r
+ kUTICK_RST_SHIFT_RSTn \\r
+ } /* Reset bits for UTICK peripheral */\r
+#define WWDT_RSTS \\r
+ { \\r
+ kWWDT_RST_SHIFT_RSTn \\r
+ } /* Reset bits for WWDT peripheral */\r
+\r
+typedef SYSCON_RSTn_t reset_ip_name_t;\r
+\r
+/*******************************************************************************\r
+ * API\r
+ ******************************************************************************/\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif\r
+\r
+/*!\r
+ * @brief Assert reset to peripheral.\r
+ *\r
+ * Asserts reset signal to specified peripheral module.\r
+ *\r
+ * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register\r
+ * and reset bit position in the reset register.\r
+ */\r
+void RESET_SetPeripheralReset(reset_ip_name_t peripheral);\r
+\r
+/*!\r
+ * @brief Clear reset to peripheral.\r
+ *\r
+ * Clears reset signal to specified peripheral module, allows it to operate.\r
+ *\r
+ * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register\r
+ * and reset bit position in the reset register.\r
+ */\r
+void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);\r
+\r
+/*!\r
+ * @brief Reset peripheral module.\r
+ *\r
+ * Reset peripheral module.\r
+ *\r
+ * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register\r
+ * and reset bit position in the reset register.\r
+ */\r
+void RESET_PeripheralReset(reset_ip_name_t peripheral);\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif\r
+\r
+/*! @} */\r
+\r
+#endif /* _FSL_RESET_H_ */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2019 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#include "fsl_usart.h"\r
+#include "fsl_device_registers.h"\r
+#include "fsl_flexcomm.h"\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/* Component ID definition, used by tools. */\r
+#ifndef FSL_COMPONENT_ID\r
+#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart"\r
+#endif\r
+\r
+/*!\r
+ * @brief Used for conversion from `flexcomm_usart_irq_handler_t` to `flexcomm_irq_handler_t`\r
+ */\r
+typedef union usart_to_flexcomm\r
+{\r
+ flexcomm_usart_irq_handler_t usart_master_handler;\r
+ flexcomm_irq_handler_t flexcomm_handler;\r
+} usart_to_flexcomm_t;\r
+\r
+enum\r
+{\r
+ kUSART_TxIdle, /* TX idle. */\r
+ kUSART_TxBusy, /* TX busy. */\r
+ kUSART_RxIdle, /* RX idle. */\r
+ kUSART_RxBusy /* RX busy. */\r
+};\r
+\r
+/*******************************************************************************\r
+ * Variables\r
+ ******************************************************************************/\r
+\r
+/*! @brief IRQ name array */\r
+static const IRQn_Type s_usartIRQ[] = USART_IRQS;\r
+\r
+/*! @brief Array to map USART instance number to base address. */\r
+static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS;\r
+\r
+/*******************************************************************************\r
+ * Code\r
+ ******************************************************************************/\r
+\r
+/* Get the index corresponding to the USART */\r
+/*! brief Returns instance number for USART peripheral base address. */\r
+uint32_t USART_GetInstance(USART_Type *base)\r
+{\r
+ uint32_t i;\r
+\r
+ for (i = 0; i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT; i++)\r
+ {\r
+ if ((uint32_t)base == s_usartBaseAddrs[i])\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ assert(i < FSL_FEATURE_SOC_USART_COUNT);\r
+ return i;\r
+}\r
+\r
+/*!\r
+ * brief Get the length of received data in RX ring buffer.\r
+ *\r
+ * param handle USART handle pointer.\r
+ * return Length of received data in RX ring buffer.\r
+ */\r
+size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle)\r
+{\r
+ size_t size;\r
+\r
+ /* Check arguments */\r
+ assert(NULL != handle);\r
+ uint16_t rxRingBufferHead = handle->rxRingBufferHead;\r
+ uint16_t rxRingBufferTail = handle->rxRingBufferTail;\r
+\r
+ if (rxRingBufferTail > rxRingBufferHead)\r
+ {\r
+ size = (size_t)rxRingBufferHead + handle->rxRingBufferSize - (size_t)rxRingBufferTail;\r
+ }\r
+ else\r
+ {\r
+ size = (size_t)rxRingBufferHead - (size_t)rxRingBufferTail;\r
+ }\r
+ return size;\r
+}\r
+\r
+static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle)\r
+{\r
+ bool full;\r
+\r
+ /* Check arguments */\r
+ assert(NULL != handle);\r
+\r
+ if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U))\r
+ {\r
+ full = true;\r
+ }\r
+ else\r
+ {\r
+ full = false;\r
+ }\r
+ return full;\r
+}\r
+\r
+/*!\r
+ * brief Sets up the RX ring buffer.\r
+ *\r
+ * This function sets up the RX ring buffer to a specific USART handle.\r
+ *\r
+ * When the RX ring buffer is used, data received are stored into the ring buffer even when the\r
+ * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received\r
+ * in the ring buffer, the user can get the received data from the ring buffer directly.\r
+ *\r
+ * note When using the RX ring buffer, one byte is reserved for internal use. In other\r
+ * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data.\r
+ *\r
+ * param base USART peripheral base address.\r
+ * param handle USART handle pointer.\r
+ * param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.\r
+ * param ringBufferSize size of the ring buffer.\r
+ */\r
+void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)\r
+{\r
+ /* Check arguments */\r
+ assert(NULL != base);\r
+ assert(NULL != handle);\r
+ assert(NULL != ringBuffer);\r
+\r
+ /* Setup the ringbuffer address */\r
+ handle->rxRingBuffer = ringBuffer;\r
+ handle->rxRingBufferSize = ringBufferSize;\r
+ handle->rxRingBufferHead = 0U;\r
+ handle->rxRingBufferTail = 0U;\r
+ /* ring buffer is ready we can start receiving data */\r
+ base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;\r
+}\r
+\r
+/*!\r
+ * brief Aborts the background transfer and uninstalls the ring buffer.\r
+ *\r
+ * This function aborts the background transfer and uninstalls the ring buffer.\r
+ *\r
+ * param base USART peripheral base address.\r
+ * param handle USART handle pointer.\r
+ */\r
+void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle)\r
+{\r
+ /* Check arguments */\r
+ assert(NULL != base);\r
+ assert(NULL != handle);\r
+\r
+ if (handle->rxState == (uint8_t)kUSART_RxIdle)\r
+ {\r
+ base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK;\r
+ }\r
+ handle->rxRingBuffer = NULL;\r
+ handle->rxRingBufferSize = 0U;\r
+ handle->rxRingBufferHead = 0U;\r
+ handle->rxRingBufferTail = 0U;\r
+}\r
+\r
+/*!\r
+ * brief Initializes a USART instance with user configuration structure and peripheral clock.\r
+ *\r
+ * This function configures the USART module with the user-defined settings. The user can configure the configuration\r
+ * structure and also get the default configuration by using the USART_GetDefaultConfig() function.\r
+ * Example below shows how to use this API to configure USART.\r
+ * code\r
+ * usart_config_t usartConfig;\r
+ * usartConfig.baudRate_Bps = 115200U;\r
+ * usartConfig.parityMode = kUSART_ParityDisabled;\r
+ * usartConfig.stopBitCount = kUSART_OneStopBit;\r
+ * USART_Init(USART1, &usartConfig, 20000000U);\r
+ * endcode\r
+ *\r
+ * param base USART peripheral base address.\r
+ * param config Pointer to user-defined configuration structure.\r
+ * param srcClock_Hz USART clock source frequency in HZ.\r
+ * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.\r
+ * retval kStatus_InvalidArgument USART base address is not valid\r
+ * retval kStatus_Success Status USART initialize succeed\r
+ */\r
+status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz)\r
+{\r
+ int result;\r
+\r
+ /* check arguments */\r
+ assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz)));\r
+ if ((NULL == base) || (NULL == config) || (0U == srcClock_Hz))\r
+ {\r
+ return kStatus_InvalidArgument;\r
+ }\r
+\r
+ /* initialize flexcomm to USART mode */\r
+ result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART);\r
+ if (kStatus_Success != result)\r
+ {\r
+ return result;\r
+ }\r
+\r
+ if (config->enableTx)\r
+ {\r
+ /* empty and enable txFIFO */\r
+ base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK;\r
+ /* setup trigger level */\r
+ base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK);\r
+ base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark);\r
+ /* enable trigger interrupt */\r
+ base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK;\r
+ }\r
+\r
+ /* empty and enable rxFIFO */\r
+ if (config->enableRx)\r
+ {\r
+ base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK;\r
+ /* setup trigger level */\r
+ base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK);\r
+ base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark);\r
+ /* enable trigger interrupt */\r
+ base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK;\r
+ }\r
+ /* setup configuration and enable USART */\r
+ base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) |\r
+ USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) |\r
+ USART_CFG_SYNCEN((uint32_t)config->syncMode >> 1) | USART_CFG_SYNCMST((uint8_t)config->syncMode) |\r
+ USART_CFG_CLKPOL(config->clockPolarity) | USART_CFG_ENABLE_MASK;\r
+\r
+ /* Setup baudrate */\r
+ result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz);\r
+ if (kStatus_Success != result)\r
+ {\r
+ return result;\r
+ }\r
+ /* Setting continuous Clock configuration. used for synchronous mode. */\r
+ USART_EnableContinuousSCLK(base, config->enableContinuousSCLK);\r
+\r
+ return kStatus_Success;\r
+}\r
+\r
+/*!\r
+ * brief Deinitializes a USART instance.\r
+ *\r
+ * This function waits for TX complete, disables TX and RX, and disables the USART clock.\r
+ *\r
+ * param base USART peripheral base address.\r
+ */\r
+void USART_Deinit(USART_Type *base)\r
+{\r
+ /* Check arguments */\r
+ assert(NULL != base);\r
+ while (0U == (base->STAT & USART_STAT_TXIDLE_MASK))\r
+ {\r
+ }\r
+ /* Disable interrupts, disable dma requests, disable peripheral */\r
+ base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK |\r
+ USART_FIFOINTENCLR_RXLVL_MASK;\r
+ base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK);\r
+ base->CFG &= ~(USART_CFG_ENABLE_MASK);\r
+}\r
+\r
+/*!\r
+ * brief Gets the default configuration structure.\r
+ *\r
+ * This function initializes the USART configuration structure to a default value. The default\r
+ * values are:\r
+ * usartConfig->baudRate_Bps = 115200U;\r
+ * usartConfig->parityMode = kUSART_ParityDisabled;\r
+ * usartConfig->stopBitCount = kUSART_OneStopBit;\r
+ * usartConfig->bitCountPerChar = kUSART_8BitsPerChar;\r
+ * usartConfig->loopback = false;\r
+ * usartConfig->enableTx = false;\r
+ * usartConfig->enableRx = false;\r
+ *\r
+ * param config Pointer to configuration structure.\r
+ */\r
+void USART_GetDefaultConfig(usart_config_t *config)\r
+{\r
+ /* Check arguments */\r
+ assert(NULL != config);\r
+\r
+ /* Initializes the configure structure to zero. */\r
+ (void)memset(config, 0, sizeof(*config));\r
+\r
+ /* Set always all members ! */\r
+ config->baudRate_Bps = 115200U;\r
+ config->parityMode = kUSART_ParityDisabled;\r
+ config->stopBitCount = kUSART_OneStopBit;\r
+ config->bitCountPerChar = kUSART_8BitsPerChar;\r
+ config->loopback = false;\r
+ config->enableRx = false;\r
+ config->enableTx = false;\r
+ config->txWatermark = kUSART_TxFifo0;\r
+ config->rxWatermark = kUSART_RxFifo1;\r
+ config->syncMode = kUSART_SyncModeDisabled;\r
+ config->enableContinuousSCLK = false;\r
+ config->clockPolarity = kUSART_RxSampleOnFallingEdge;\r
+}\r
+\r
+/*!\r
+ * brief Sets the USART instance baud rate.\r
+ *\r
+ * This function configures the USART module baud rate. This function is used to update\r
+ * the USART module baud rate after the USART module is initialized by the USART_Init.\r
+ * code\r
+ * USART_SetBaudRate(USART1, 115200U, 20000000U);\r
+ * endcode\r
+ *\r
+ * param base USART peripheral base address.\r
+ * param baudrate_Bps USART baudrate to be set.\r
+ * param srcClock_Hz USART clock source frequency in HZ.\r
+ * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.\r
+ * retval kStatus_Success Set baudrate succeed.\r
+ * retval kStatus_InvalidArgument One or more arguments are invalid.\r
+ */\r
+status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz)\r
+{\r
+ uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1;\r
+ uint32_t osrval, brgval, diff, baudrate;\r
+\r
+ /* check arguments */\r
+ assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)));\r
+ if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))\r
+ {\r
+ return kStatus_InvalidArgument;\r
+ }\r
+\r
+ /* If synchronous master mode is enabled, only configure the BRG value. */\r
+ if ((base->CFG & USART_CFG_SYNCEN_MASK) != 0U)\r
+ {\r
+ if ((base->CFG & USART_CFG_SYNCMST_MASK) != 0U)\r
+ {\r
+ brgval = srcClock_Hz / baudrate_Bps;\r
+ base->BRG = brgval - 1U;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /*\r
+ * Smaller values of OSR can make the sampling position within a data bit less accurate and may\r
+ * potentially cause more noise errors or incorrect data.\r
+ */\r
+ for (osrval = best_osrval; osrval >= 8U; osrval--)\r
+ {\r
+ brgval = (((srcClock_Hz * 10U) / ((osrval + 1U) * baudrate_Bps)) - 5U) / 10U;\r
+ if (brgval > 0xFFFFU)\r
+ {\r
+ continue;\r
+ }\r
+ baudrate = srcClock_Hz / ((osrval + 1U) * (brgval + 1U));\r
+ diff = baudrate_Bps < baudrate ? baudrate - baudrate_Bps : baudrate_Bps - baudrate;\r
+ if (diff < best_diff)\r
+ {\r
+ best_diff = diff;\r
+ best_osrval = osrval;\r
+ best_brgval = brgval;\r
+ }\r
+ }\r
+\r
+ /* value over range */\r
+ if (best_brgval > 0xFFFFU)\r
+ {\r
+ return kStatus_USART_BaudrateNotSupport;\r
+ }\r
+\r
+ base->OSR = best_osrval;\r
+ base->BRG = best_brgval;\r
+ }\r
+\r
+ return kStatus_Success;\r
+}\r
+\r
+/*!\r
+ * brief Writes to the TX register using a blocking method.\r
+ *\r
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO\r
+ * to have room and writes data to the TX buffer.\r
+ *\r
+ * param base USART peripheral base address.\r
+ * param data Start address of the data to write.\r
+ * param length Size of the data to write.\r
+ */\r
+void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length)\r
+{\r
+ /* Check arguments */\r
+ assert(!((NULL == base) || (NULL == data)));\r
+ if ((NULL == base) || (NULL == data))\r
+ {\r
+ return;\r
+ }\r
+ /* Check whether txFIFO is enabled */\r
+ if (0U == (base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK))\r
+ {\r
+ return;\r
+ }\r
+ for (; length > 0U; length--)\r
+ {\r
+ /* Loop until txFIFO get some space for new data */\r
+ while (0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))\r
+ {\r
+ }\r
+ base->FIFOWR = *data;\r
+ data++;\r
+ }\r
+ /* Wait to finish transfer */\r
+ while (0U == (base->STAT & USART_STAT_TXIDLE_MASK))\r
+ {\r
+ }\r
+}\r
+\r
+/*!\r
+ * brief Read RX data register using a blocking method.\r
+ *\r
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to\r
+ * have data and read data from the TX register.\r
+ *\r
+ * param base USART peripheral base address.\r
+ * param data Start address of the buffer to store the received data.\r
+ * param length Size of the buffer.\r
+ * retval kStatus_USART_FramingError Receiver overrun happened while receiving data.\r
+ * retval kStatus_USART_ParityError Noise error happened while receiving data.\r
+ * retval kStatus_USART_NoiseError Framing error happened while receiving data.\r
+ * retval kStatus_USART_RxError Overflow or underflow rxFIFO happened.\r
+ * retval kStatus_Success Successfully received all data.\r
+ */\r
+status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length)\r
+{\r
+ uint32_t statusFlag;\r
+ status_t status = kStatus_Success;\r
+\r
+ /* check arguments */\r
+ assert(!((NULL == base) || (NULL == data)));\r
+ if ((NULL == base) || (NULL == data))\r
+ {\r
+ return kStatus_InvalidArgument;\r
+ }\r
+\r
+ /* Check whether rxFIFO is enabled */\r
+ if ((base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK) == 0U)\r
+ {\r
+ return kStatus_Fail;\r
+ }\r
+ for (; length > 0U; length--)\r
+ {\r
+ /* loop until rxFIFO have some data to read */\r
+ while ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U)\r
+ {\r
+ }\r
+ /* check rxFIFO statusFlag */\r
+ if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U)\r
+ {\r
+ base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;\r
+ base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK;\r
+ status = kStatus_USART_RxError;\r
+ break;\r
+ }\r
+ /* check receive statusFlag */\r
+ statusFlag = base->STAT;\r
+ /* Clear all status flags */\r
+ base->STAT |= statusFlag;\r
+ if ((statusFlag & USART_STAT_PARITYERRINT_MASK) != 0U)\r
+ {\r
+ status = kStatus_USART_ParityError;\r
+ }\r
+ if ((statusFlag & USART_STAT_FRAMERRINT_MASK) != 0U)\r
+ {\r
+ status = kStatus_USART_FramingError;\r
+ }\r
+ if ((statusFlag & USART_STAT_RXNOISEINT_MASK) != 0U)\r
+ {\r
+ status = kStatus_USART_NoiseError;\r
+ }\r
+\r
+ if (kStatus_Success == status)\r
+ {\r
+ *data = (uint8_t)base->FIFORD;\r
+ data++;\r
+ }\r
+ else\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ return status;\r
+}\r
+\r
+/*!\r
+ * brief Initializes the USART handle.\r
+ *\r
+ * This function initializes the USART handle which can be used for other USART\r
+ * transactional APIs. Usually, for a specified USART instance,\r
+ * call this API once to get the initialized handle.\r
+ *\r
+ * param base USART peripheral base address.\r
+ * param handle USART handle pointer.\r
+ * param callback The callback function.\r
+ * param userData The parameter of the callback function.\r
+ */\r
+status_t USART_TransferCreateHandle(USART_Type *base,\r
+ usart_handle_t *handle,\r
+ usart_transfer_callback_t callback,\r
+ void *userData)\r
+{\r
+ /* Check 'base' */\r
+ assert(!((NULL == base) || (NULL == handle)));\r
+\r
+ uint32_t instance = 0;\r
+ usart_to_flexcomm_t handler;\r
+ handler.usart_master_handler = USART_TransferHandleIRQ;\r
+\r
+ if ((NULL == base) || (NULL == handle))\r
+ {\r
+ return kStatus_InvalidArgument;\r
+ }\r
+\r
+ instance = USART_GetInstance(base);\r
+\r
+ (void)memset(handle, 0, sizeof(*handle));\r
+ /* Set the TX/RX state. */\r
+ handle->rxState = (uint8_t)kUSART_RxIdle;\r
+ handle->txState = (uint8_t)kUSART_TxIdle;\r
+ /* Set the callback and user data. */\r
+ handle->callback = callback;\r
+ handle->userData = userData;\r
+ handle->rxWatermark = (uint8_t)USART_FIFOTRIG_RXLVL_GET(base);\r
+ handle->txWatermark = (uint8_t)USART_FIFOTRIG_TXLVL_GET(base);\r
+\r
+ FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle);\r
+\r
+ /* Enable interrupt in NVIC. */\r
+ (void)EnableIRQ(s_usartIRQ[instance]);\r
+\r
+ return kStatus_Success;\r
+}\r
+\r
+/*!\r
+ * brief Transmits a buffer of data using the interrupt method.\r
+ *\r
+ * This function sends data using an interrupt method. This is a non-blocking function, which\r
+ * returns directly without waiting for all data to be written to the TX register. When\r
+ * all data is written to the TX register in the IRQ handler, the USART driver calls the callback\r
+ * function and passes the ref kStatus_USART_TxIdle as status parameter.\r
+ *\r
+ * note The kStatus_USART_TxIdle is passed to the upper layer when all data is written\r
+ * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX,\r
+ * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished.\r
+ *\r
+ * param base USART peripheral base address.\r
+ * param handle USART handle pointer.\r
+ * param xfer USART transfer structure. See #usart_transfer_t.\r
+ * retval kStatus_Success Successfully start the data transmission.\r
+ * retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet.\r
+ * retval kStatus_InvalidArgument Invalid argument.\r
+ */\r
+status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer)\r
+{\r
+ /* Check arguments */\r
+ assert(!((NULL == base) || (NULL == handle) || (NULL == xfer)));\r
+ if ((NULL == base) || (NULL == handle) || (NULL == xfer))\r
+ {\r
+ return kStatus_InvalidArgument;\r
+ }\r
+ /* Check xfer members */\r
+ assert(!((0 == xfer->dataSize) || (NULL == xfer->data)));\r
+ if ((0U == xfer->dataSize) || (NULL == xfer->data))\r
+ {\r
+ return kStatus_InvalidArgument;\r
+ }\r
+\r
+ /* Return error if current TX busy. */\r
+ if ((uint8_t)kUSART_TxBusy == handle->txState)\r
+ {\r
+ return kStatus_USART_TxBusy;\r
+ }\r
+ else\r
+ {\r
+ handle->txData = xfer->data;\r
+ handle->txDataSize = xfer->dataSize;\r
+ handle->txDataSizeAll = xfer->dataSize;\r
+ handle->txState = (uint8_t)kUSART_TxBusy;\r
+ /* Enable transmiter interrupt. */\r
+ base->FIFOINTENSET |= USART_FIFOINTENSET_TXLVL_MASK;\r
+ }\r
+ return kStatus_Success;\r
+}\r
+\r
+/*!\r
+ * brief Aborts the interrupt-driven data transmit.\r
+ *\r
+ * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out\r
+ * how many bytes are still not sent out.\r
+ *\r
+ * param base USART peripheral base address.\r
+ * param handle USART handle pointer.\r
+ */\r
+void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle)\r
+{\r
+ assert(NULL != handle);\r
+\r
+ /* Disable interrupts */\r
+ USART_DisableInterrupts(base, (uint32_t)kUSART_TxLevelInterruptEnable);\r
+ /* Empty txFIFO */\r
+ base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK;\r
+\r
+ handle->txDataSize = 0U;\r
+ handle->txState = (uint8_t)kUSART_TxIdle;\r
+}\r
+\r
+/*!\r
+ * brief Get the number of bytes that have been written to USART TX register.\r
+ *\r
+ * This function gets the number of bytes that have been written to USART TX\r
+ * register by interrupt method.\r
+ *\r
+ * param base USART peripheral base address.\r
+ * param handle USART handle pointer.\r
+ * param count Send bytes count.\r
+ * retval kStatus_NoTransferInProgress No send in progress.\r
+ * retval kStatus_InvalidArgument Parameter is invalid.\r
+ * retval kStatus_Success Get successfully through the parameter \p count;\r
+ */\r
+status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count)\r
+{\r
+ assert(NULL != handle);\r
+ assert(NULL != count);\r
+\r
+ if ((uint8_t)kUSART_TxIdle == handle->txState)\r
+ {\r
+ return kStatus_NoTransferInProgress;\r
+ }\r
+\r
+ *count = handle->txDataSizeAll - handle->txDataSize;\r
+\r
+ return kStatus_Success;\r
+}\r
+\r
+/*!\r
+ * brief Receives a buffer of data using an interrupt method.\r
+ *\r
+ * This function receives data using an interrupt method. This is a non-blocking function, which\r
+ * returns without waiting for all data to be received.\r
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and\r
+ * the parameter p receivedBytes shows how many bytes are copied from the ring buffer.\r
+ * After copying, if the data in the ring buffer is not enough to read, the receive\r
+ * request is saved by the USART driver. When the new data arrives, the receive request\r
+ * is serviced first. When all data is received, the USART driver notifies the upper layer\r
+ * through a callback function and passes the status parameter ref kStatus_USART_RxIdle.\r
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer.\r
+ * The 5 bytes are copied to the xfer->data and this function returns with the\r
+ * parameter p receivedBytes set to 5. For the left 5 bytes, newly arrived data is\r
+ * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer.\r
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt\r
+ * to receive data to the xfer->data. When all data is received, the upper layer is notified.\r
+ *\r
+ * param base USART peripheral base address.\r
+ * param handle USART handle pointer.\r
+ * param xfer USART transfer structure, see #usart_transfer_t.\r
+ * param receivedBytes Bytes received from the ring buffer directly.\r
+ * retval kStatus_Success Successfully queue the transfer into transmit queue.\r
+ * retval kStatus_USART_RxBusy Previous receive request is not finished.\r
+ * retval kStatus_InvalidArgument Invalid argument.\r
+ */\r
+status_t USART_TransferReceiveNonBlocking(USART_Type *base,\r
+ usart_handle_t *handle,\r
+ usart_transfer_t *xfer,\r
+ size_t *receivedBytes)\r
+{\r
+ uint32_t i;\r
+ /* How many bytes to copy from ring buffer to user memory. */\r
+ size_t bytesToCopy = 0U;\r
+ /* How many bytes to receive. */\r
+ size_t bytesToReceive;\r
+ /* How many bytes currently have received. */\r
+ size_t bytesCurrentReceived;\r
+ uint32_t regPrimask = 0U;\r
+\r
+ /* Check arguments */\r
+ assert(!((NULL == base) || (NULL == handle) || (NULL == xfer)));\r
+ if ((NULL == base) || (NULL == handle) || (NULL == xfer))\r
+ {\r
+ return kStatus_InvalidArgument;\r
+ }\r
+ /* Check xfer members */\r
+ assert(!((0 == xfer->dataSize) || (NULL == xfer->data)));\r
+ if ((0U == xfer->dataSize) || (NULL == xfer->data))\r
+ {\r
+ return kStatus_InvalidArgument;\r
+ }\r
+\r
+ /* How to get data:\r
+ 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize\r
+ to uart handle, enable interrupt to store received data to xfer->data. When\r
+ all data received, trigger callback.\r
+ 2. If RX ring buffer is enabled and not empty, get data from ring buffer first.\r
+ If there are enough data in ring buffer, copy them to xfer->data and return.\r
+ If there are not enough data in ring buffer, copy all of them to xfer->data,\r
+ save the xfer->data remained empty space to uart handle, receive data\r
+ to this empty space and trigger callback when finished. */\r
+ if ((uint8_t)kUSART_RxBusy == handle->rxState)\r
+ {\r
+ return kStatus_USART_RxBusy;\r
+ }\r
+ else\r
+ {\r
+ bytesToReceive = xfer->dataSize;\r
+ bytesCurrentReceived = 0U;\r
+ /* If RX ring buffer is used. */\r
+ if (handle->rxRingBuffer != NULL)\r
+ {\r
+ /* Disable IRQ, protect ring buffer. */\r
+ regPrimask = DisableGlobalIRQ();\r
+ /* How many bytes in RX ring buffer currently. */\r
+ bytesToCopy = USART_TransferGetRxRingBufferLength(handle);\r
+ if (bytesToCopy != 0U)\r
+ {\r
+ bytesToCopy = MIN(bytesToReceive, bytesToCopy);\r
+ bytesToReceive -= bytesToCopy;\r
+ /* Copy data from ring buffer to user memory. */\r
+ for (i = 0U; i < bytesToCopy; i++)\r
+ {\r
+ xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];\r
+ /* Wrap to 0. Not use modulo (%) because it might be large and slow. */\r
+ if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)\r
+ {\r
+ handle->rxRingBufferTail = 0U;\r
+ }\r
+ else\r
+ {\r
+ handle->rxRingBufferTail++;\r
+ }\r
+ }\r
+ }\r
+ /* If ring buffer does not have enough data, still need to read more data. */\r
+ if (bytesToReceive != 0U)\r
+ {\r
+ /* No data in ring buffer, save the request to UART handle. */\r
+ handle->rxData = xfer->data + bytesCurrentReceived;\r
+ handle->rxDataSize = bytesToReceive;\r
+ handle->rxDataSizeAll = bytesToReceive;\r
+ handle->rxState = (uint8_t)kUSART_RxBusy;\r
+ }\r
+ /* Enable IRQ if previously enabled. */\r
+ EnableGlobalIRQ(regPrimask);\r
+ /* Call user callback since all data are received. */\r
+ if (0U == bytesToReceive)\r
+ {\r
+ if (handle->callback != NULL)\r
+ {\r
+ handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData);\r
+ }\r
+ }\r
+ }\r
+ /* Ring buffer not used. */\r
+ else\r
+ {\r
+ handle->rxData = xfer->data + bytesCurrentReceived;\r
+ handle->rxDataSize = bytesToReceive;\r
+ handle->rxDataSizeAll = bytesToReceive;\r
+ handle->rxState = (uint8_t)kUSART_RxBusy;\r
+\r
+ /* Enable RX interrupt. */\r
+ base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK;\r
+ }\r
+ /* Return the how many bytes have read. */\r
+ if (receivedBytes != NULL)\r
+ {\r
+ *receivedBytes = bytesCurrentReceived;\r
+ }\r
+ }\r
+ return kStatus_Success;\r
+}\r
+\r
+/*!\r
+ * brief Aborts the interrupt-driven data receiving.\r
+ *\r
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out\r
+ * how many bytes not received yet.\r
+ *\r
+ * param base USART peripheral base address.\r
+ * param handle USART handle pointer.\r
+ */\r
+void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle)\r
+{\r
+ assert(NULL != handle);\r
+\r
+ /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */\r
+ if (NULL == handle->rxRingBuffer)\r
+ {\r
+ /* Disable interrupts */\r
+ USART_DisableInterrupts(base, (uint32_t)kUSART_RxLevelInterruptEnable);\r
+ /* Empty rxFIFO */\r
+ base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;\r
+ }\r
+\r
+ handle->rxDataSize = 0U;\r
+ handle->rxState = (uint8_t)kUSART_RxIdle;\r
+}\r
+\r
+/*!\r
+ * brief Get the number of bytes that have been received.\r
+ *\r
+ * This function gets the number of bytes that have been received.\r
+ *\r
+ * param base USART peripheral base address.\r
+ * param handle USART handle pointer.\r
+ * param count Receive bytes count.\r
+ * retval kStatus_NoTransferInProgress No receive in progress.\r
+ * retval kStatus_InvalidArgument Parameter is invalid.\r
+ * retval kStatus_Success Get successfully through the parameter \p count;\r
+ */\r
+status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count)\r
+{\r
+ assert(NULL != handle);\r
+ assert(NULL != count);\r
+\r
+ if ((uint8_t)kUSART_RxIdle == handle->rxState)\r
+ {\r
+ return kStatus_NoTransferInProgress;\r
+ }\r
+\r
+ *count = handle->rxDataSizeAll - handle->rxDataSize;\r
+\r
+ return kStatus_Success;\r
+}\r
+\r
+/*!\r
+ * brief USART IRQ handle function.\r
+ *\r
+ * This function handles the USART transmit and receive IRQ request.\r
+ *\r
+ * param base USART peripheral base address.\r
+ * param handle USART handle pointer.\r
+ */\r
+void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle)\r
+{\r
+ /* Check arguments */\r
+ assert((NULL != base) && (NULL != handle));\r
+\r
+ bool receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL));\r
+ bool sendEnabled = (handle->txDataSize != 0U);\r
+ uint8_t rxdata;\r
+ size_t tmpsize;\r
+\r
+ /* If RX overrun. */\r
+ if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U)\r
+ {\r
+ /* Clear rx error state. */\r
+ base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK;\r
+ /* clear rxFIFO */\r
+ base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;\r
+ /* Trigger callback. */\r
+ if (handle->callback != NULL)\r
+ {\r
+ handle->callback(base, handle, kStatus_USART_RxError, handle->userData);\r
+ }\r
+ }\r
+ while ((receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) ||\r
+ (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U)))\r
+ {\r
+ /* Receive data */\r
+ if (receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U))\r
+ {\r
+ /* Receive to app bufffer if app buffer is present */\r
+ if (handle->rxDataSize != 0U)\r
+ {\r
+ rxdata = (uint8_t)base->FIFORD;\r
+ *handle->rxData = rxdata;\r
+ handle->rxDataSize--;\r
+ handle->rxData++;\r
+ receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL));\r
+ if (0U == handle->rxDataSize)\r
+ {\r
+ if (NULL == handle->rxRingBuffer)\r
+ {\r
+ base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;\r
+ }\r
+ handle->rxState = (uint8_t)kUSART_RxIdle;\r
+ if (handle->callback != NULL)\r
+ {\r
+ handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData);\r
+ }\r
+ }\r
+ }\r
+ /* Otherwise receive to ring buffer if ring buffer is present */\r
+ else\r
+ {\r
+ if (handle->rxRingBuffer != NULL)\r
+ {\r
+ /* If RX ring buffer is full, trigger callback to notify over run. */\r
+ if (USART_TransferIsRxRingBufferFull(handle))\r
+ {\r
+ if (handle->callback != NULL)\r
+ {\r
+ handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData);\r
+ }\r
+ }\r
+ /* If ring buffer is still full after callback function, the oldest data is overridden. */\r
+ if (USART_TransferIsRxRingBufferFull(handle))\r
+ {\r
+ /* Increase handle->rxRingBufferTail to make room for new data. */\r
+ if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)\r
+ {\r
+ handle->rxRingBufferTail = 0U;\r
+ }\r
+ else\r
+ {\r
+ handle->rxRingBufferTail++;\r
+ }\r
+ }\r
+ /* Read data. */\r
+ rxdata = (uint8_t)base->FIFORD;\r
+ handle->rxRingBuffer[handle->rxRingBufferHead] = rxdata;\r
+ /* Increase handle->rxRingBufferHead. */\r
+ if ((size_t)handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)\r
+ {\r
+ handle->rxRingBufferHead = 0U;\r
+ }\r
+ else\r
+ {\r
+ handle->rxRingBufferHead++;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /* Send data */\r
+ if (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U))\r
+ {\r
+ base->FIFOWR = *handle->txData;\r
+ handle->txDataSize--;\r
+ handle->txData++;\r
+ sendEnabled = handle->txDataSize != 0U;\r
+ if (!sendEnabled)\r
+ {\r
+ base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK;\r
+ handle->txState = (uint8_t)kUSART_TxIdle;\r
+\r
+ base->INTENSET |= USART_INTENSET_TXIDLEEN_MASK;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Tx idle and the interrupt is enabled. */\r
+ if ((0U != (base->INTENSET & USART_INTENSET_TXIDLEEN_MASK)) &&\r
+ (0U != (base->INTSTAT & USART_INTSTAT_TXIDLE_MASK)) && (handle->txState == (uint8_t)kUSART_TxIdle))\r
+ {\r
+ /* Disable tx idle interrupt */\r
+ base->INTENCLR |= USART_INTENCLR_TXIDLECLR_MASK;\r
+ /* Trigger callback. */\r
+ if (handle->callback != NULL)\r
+ {\r
+ handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData);\r
+ }\r
+ }\r
+\r
+ /* ring buffer is not used */\r
+ if (NULL == handle->rxRingBuffer)\r
+ {\r
+ tmpsize = handle->rxDataSize;\r
+\r
+ /* restore if rx transfer ends and rxLevel is different from default value */\r
+ if ((tmpsize == 0U) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark))\r
+ {\r
+ base->FIFOTRIG =\r
+ (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark);\r
+ }\r
+ /* decrease level if rx transfer is bellow */\r
+ if ((tmpsize != 0U) && (tmpsize < (USART_FIFOTRIG_RXLVL_GET(base) + 1U)))\r
+ {\r
+ base->FIFOTRIG = (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(tmpsize - 1U));\r
+ }\r
+ }\r
+}\r
--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2019 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+#ifndef _FSL_USART_H_\r
+#define _FSL_USART_H_\r
+\r
+#include "fsl_common.h"\r
+\r
+/*!\r
+ * @addtogroup usart_driver\r
+ * @{\r
+ */\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/*! @name Driver version */\r
+/*@{*/\r
+/*! @brief USART driver version 2.1.1. */\r
+#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))\r
+/*@}*/\r
+\r
+#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT)\r
+#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT)\r
+\r
+/*! @brief Error codes for the USART driver. */\r
+enum\r
+{\r
+ kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0), /*!< Transmitter is busy. */\r
+ kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1), /*!< Receiver is busy. */\r
+ kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2), /*!< USART transmitter is idle. */\r
+ kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3), /*!< USART receiver is idle. */\r
+ kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7), /*!< Error happens on txFIFO. */\r
+ kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9), /*!< Error happens on rxFIFO. */\r
+ kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */\r
+ kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10), /*!< USART noise error. */\r
+ kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11), /*!< USART framing error. */\r
+ kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */\r
+ kStatus_USART_BaudrateNotSupport =\r
+ MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */\r
+};\r
+\r
+/*! @brief USART synchronous mode. */\r
+typedef enum _usart_sync_mode\r
+{\r
+ kUSART_SyncModeDisabled = 0x0U, /*!< Asynchronous mode. */\r
+ kUSART_SyncModeSlave = 0x2U, /*!< Synchronous slave mode. */\r
+ kUSART_SyncModeMaster = 0x3U, /*!< Synchronous master mode. */\r
+} usart_sync_mode_t;\r
+\r
+/*! @brief USART parity mode. */\r
+typedef enum _usart_parity_mode\r
+{\r
+ kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */\r
+ kUSART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */\r
+ kUSART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */\r
+} usart_parity_mode_t;\r
+\r
+/*! @brief USART stop bit count. */\r
+typedef enum _usart_stop_bit_count\r
+{\r
+ kUSART_OneStopBit = 0U, /*!< One stop bit */\r
+ kUSART_TwoStopBit = 1U, /*!< Two stop bits */\r
+} usart_stop_bit_count_t;\r
+\r
+/*! @brief USART data size. */\r
+typedef enum _usart_data_len\r
+{\r
+ kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */\r
+ kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */\r
+} usart_data_len_t;\r
+\r
+/*! @brief USART clock polarity configuration, used in sync mode.*/\r
+typedef enum _usart_clock_polarity\r
+{\r
+ kUSART_RxSampleOnFallingEdge = 0x0U, /*!< Un_RXD is sampled on the falling edge of SCLK. */\r
+ kUSART_RxSampleOnRisingEdge = 0x1U, /*!< Un_RXD is sampled on the rising edge of SCLK. */\r
+} usart_clock_polarity_t;\r
+\r
+/*! @brief txFIFO watermark values */\r
+typedef enum _usart_txfifo_watermark\r
+{\r
+ kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */\r
+ kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */\r
+ kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */\r
+ kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */\r
+ kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */\r
+ kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */\r
+ kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */\r
+ kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */\r
+} usart_txfifo_watermark_t;\r
+\r
+/*! @brief rxFIFO watermark values */\r
+typedef enum _usart_rxfifo_watermark\r
+{\r
+ kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */\r
+ kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */\r
+ kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */\r
+ kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */\r
+ kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */\r
+ kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */\r
+ kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */\r
+ kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */\r
+} usart_rxfifo_watermark_t;\r
+\r
+/*!\r
+ * @brief USART interrupt configuration structure, default settings all disabled.\r
+ */\r
+enum _usart_interrupt_enable\r
+{\r
+ kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK),\r
+ kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK),\r
+ kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK),\r
+ kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK),\r
+};\r
+\r
+/*!\r
+ * @brief USART status flags.\r
+ *\r
+ * This provides constants for the USART status flags for use in the USART functions.\r
+ */\r
+enum _usart_flags\r
+{\r
+ kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK), /*!< TEERR bit, sets if TX buffer is error */\r
+ kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK), /*!< RXERR bit, sets if RX buffer is error */\r
+ kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK), /*!< TXEMPTY bit, sets if TX buffer is empty */\r
+ kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK), /*!< TXNOTFULL bit, sets if TX buffer is not full */\r
+ kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */\r
+ kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK), /*!< RXFULL bit, sets if RX buffer is full */\r
+};\r
+\r
+/*! @brief USART configuration structure. */\r
+typedef struct _usart_config\r
+{\r
+ uint32_t baudRate_Bps; /*!< USART baud rate */\r
+ usart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */\r
+ usart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */\r
+ usart_data_len_t bitCountPerChar; /*!< Data length - 7 bit, 8 bit */\r
+ bool loopback; /*!< Enable peripheral loopback */\r
+ bool enableRx; /*!< Enable RX */\r
+ bool enableTx; /*!< Enable TX */\r
+ bool enableContinuousSCLK; /*!< USART continuous Clock generation enable in synchronous master mode. */\r
+ usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */\r
+ usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */\r
+ usart_sync_mode_t syncMode; /*!< Transfer mode select - asynchronous, synchronous master, synchronous slave. */\r
+ usart_clock_polarity_t clockPolarity; /*!< Selects the clock polarity and sampling edge in synchronous mode. */\r
+} usart_config_t;\r
+\r
+/*! @brief USART transfer structure. */\r
+typedef struct _usart_transfer\r
+{\r
+ uint8_t *data; /*!< The buffer of data to be transfer.*/\r
+ size_t dataSize; /*!< The byte count to be transfer. */\r
+} usart_transfer_t;\r
+\r
+/* Forward declaration of the handle typedef. */\r
+typedef struct _usart_handle usart_handle_t;\r
+\r
+/*! @brief USART transfer callback function. */\r
+typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData);\r
+\r
+/*! @brief USART handle structure. */\r
+struct _usart_handle\r
+{\r
+ uint8_t *volatile txData; /*!< Address of remaining data to send. */\r
+ volatile size_t txDataSize; /*!< Size of the remaining data to send. */\r
+ size_t txDataSizeAll; /*!< Size of the data to send out. */\r
+ uint8_t *volatile rxData; /*!< Address of remaining data to receive. */\r
+ volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */\r
+ size_t rxDataSizeAll; /*!< Size of the data to receive. */\r
+\r
+ uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */\r
+ size_t rxRingBufferSize; /*!< Size of the ring buffer. */\r
+ volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */\r
+ volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */\r
+\r
+ usart_transfer_callback_t callback; /*!< Callback function. */\r
+ void *userData; /*!< USART callback function parameter.*/\r
+\r
+ volatile uint8_t txState; /*!< TX transfer state. */\r
+ volatile uint8_t rxState; /*!< RX transfer state */\r
+\r
+ uint8_t txWatermark; /*!< txFIFO watermark */\r
+ uint8_t rxWatermark; /*!< rxFIFO watermark */\r
+};\r
+\r
+/*! @brief Typedef for usart interrupt handler. */\r
+typedef void (*flexcomm_usart_irq_handler_t)(USART_Type *base, usart_handle_t *handle);\r
+\r
+/*******************************************************************************\r
+ * API\r
+ ******************************************************************************/\r
+\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif /* _cplusplus */\r
+\r
+/*! @brief Returns instance number for USART peripheral base address. */\r
+uint32_t USART_GetInstance(USART_Type *base);\r
+\r
+/*!\r
+ * @name Initialization and deinitialization\r
+ * @{\r
+ */\r
+\r
+/*!\r
+ * @brief Initializes a USART instance with user configuration structure and peripheral clock.\r
+ *\r
+ * This function configures the USART module with the user-defined settings. The user can configure the configuration\r
+ * structure and also get the default configuration by using the USART_GetDefaultConfig() function.\r
+ * Example below shows how to use this API to configure USART.\r
+ * @code\r
+ * usart_config_t usartConfig;\r
+ * usartConfig.baudRate_Bps = 115200U;\r
+ * usartConfig.parityMode = kUSART_ParityDisabled;\r
+ * usartConfig.stopBitCount = kUSART_OneStopBit;\r
+ * USART_Init(USART1, &usartConfig, 20000000U);\r
+ * @endcode\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param config Pointer to user-defined configuration structure.\r
+ * @param srcClock_Hz USART clock source frequency in HZ.\r
+ * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.\r
+ * @retval kStatus_InvalidArgument USART base address is not valid\r
+ * @retval kStatus_Success Status USART initialize succeed\r
+ */\r
+status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz);\r
+\r
+/*!\r
+ * @brief Deinitializes a USART instance.\r
+ *\r
+ * This function waits for TX complete, disables TX and RX, and disables the USART clock.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ */\r
+void USART_Deinit(USART_Type *base);\r
+\r
+/*!\r
+ * @brief Gets the default configuration structure.\r
+ *\r
+ * This function initializes the USART configuration structure to a default value. The default\r
+ * values are:\r
+ * usartConfig->baudRate_Bps = 115200U;\r
+ * usartConfig->parityMode = kUSART_ParityDisabled;\r
+ * usartConfig->stopBitCount = kUSART_OneStopBit;\r
+ * usartConfig->bitCountPerChar = kUSART_8BitsPerChar;\r
+ * usartConfig->loopback = false;\r
+ * usartConfig->enableTx = false;\r
+ * usartConfig->enableRx = false;\r
+ *\r
+ * @param config Pointer to configuration structure.\r
+ */\r
+void USART_GetDefaultConfig(usart_config_t *config);\r
+\r
+/*!\r
+ * @brief Sets the USART instance baud rate.\r
+ *\r
+ * This function configures the USART module baud rate. This function is used to update\r
+ * the USART module baud rate after the USART module is initialized by the USART_Init.\r
+ * @code\r
+ * USART_SetBaudRate(USART1, 115200U, 20000000U);\r
+ * @endcode\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param baudrate_Bps USART baudrate to be set.\r
+ * @param srcClock_Hz USART clock source frequency in HZ.\r
+ * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.\r
+ * @retval kStatus_Success Set baudrate succeed.\r
+ * @retval kStatus_InvalidArgument One or more arguments are invalid.\r
+ */\r
+status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz);\r
+\r
+/* @} */\r
+\r
+/*!\r
+ * @name Status\r
+ * @{\r
+ */\r
+\r
+/*!\r
+ * @brief Get USART status flags.\r
+ *\r
+ * This function get all USART status flags, the flags are returned as the logical\r
+ * OR value of the enumerators @ref _usart_flags. To check a specific status,\r
+ * compare the return value with enumerators in @ref _usart_flags.\r
+ * For example, to check whether the TX is empty:\r
+ * @code\r
+ * if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1))\r
+ * {\r
+ * ...\r
+ * }\r
+ * @endcode\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @return USART status flags which are ORed by the enumerators in the _usart_flags.\r
+ */\r
+static inline uint32_t USART_GetStatusFlags(USART_Type *base)\r
+{\r
+ return base->FIFOSTAT;\r
+}\r
+\r
+/*!\r
+ * @brief Clear USART status flags.\r
+ *\r
+ * This function clear supported USART status flags\r
+ * Flags that can be cleared or set are:\r
+ * kUSART_TxError\r
+ * kUSART_RxError\r
+ * For example:\r
+ * @code\r
+ * USART_ClearStatusFlags(USART1, kUSART_TxError | kUSART_RxError)\r
+ * @endcode\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param mask status flags to be cleared.\r
+ */\r
+static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask)\r
+{\r
+ /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */\r
+ base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK);\r
+}\r
+\r
+/* @} */\r
+\r
+/*!\r
+ * @name Interrupts\r
+ * @{\r
+ */\r
+\r
+/*!\r
+ * @brief Enables USART interrupts according to the provided mask.\r
+ *\r
+ * This function enables the USART interrupts according to the provided mask. The mask\r
+ * is a logical OR of enumeration members. See @ref _usart_interrupt_enable.\r
+ * For example, to enable TX empty interrupt and RX full interrupt:\r
+ * @code\r
+ * USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable);\r
+ * @endcode\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable.\r
+ */\r
+static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask)\r
+{\r
+ base->FIFOINTENSET = mask & 0xFUL;\r
+}\r
+\r
+/*!\r
+ * @brief Disables USART interrupts according to a provided mask.\r
+ *\r
+ * This function disables the USART interrupts according to a provided mask. The mask\r
+ * is a logical OR of enumeration members. See @ref _usart_interrupt_enable.\r
+ * This example shows how to disable the TX empty interrupt and RX full interrupt:\r
+ * @code\r
+ * USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable);\r
+ * @endcode\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable.\r
+ */\r
+static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask)\r
+{\r
+ base->FIFOINTENCLR = mask & 0xFUL;\r
+}\r
+\r
+/*!\r
+ * @brief Returns enabled USART interrupts.\r
+ *\r
+ * This function returns the enabled USART interrupts.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ */\r
+static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base)\r
+{\r
+ return base->FIFOINTENSET;\r
+}\r
+\r
+/*!\r
+ * @brief Enable DMA for Tx\r
+ */\r
+static inline void USART_EnableTxDMA(USART_Type *base, bool enable)\r
+{\r
+ if (enable)\r
+ {\r
+ base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK;\r
+ }\r
+ else\r
+ {\r
+ base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK);\r
+ }\r
+}\r
+\r
+/*!\r
+ * @brief Enable DMA for Rx\r
+ */\r
+static inline void USART_EnableRxDMA(USART_Type *base, bool enable)\r
+{\r
+ if (enable)\r
+ {\r
+ base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK;\r
+ }\r
+ else\r
+ {\r
+ base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK);\r
+ }\r
+}\r
+\r
+/*!\r
+ * @brief Enable CTS.\r
+ * This function will determine whether CTS is used for flow control.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param enable Enable CTS or not, true for enable and false for disable.\r
+ */\r
+static inline void USART_EnableCTS(USART_Type *base, bool enable)\r
+{\r
+ if (enable)\r
+ {\r
+ base->CFG |= USART_CFG_CTSEN_MASK;\r
+ }\r
+ else\r
+ {\r
+ base->CFG &= ~USART_CFG_CTSEN_MASK;\r
+ }\r
+}\r
+\r
+/*!\r
+ * @brief Continuous Clock generation.\r
+ * By default, SCLK is only output while data is being transmitted in synchronous mode.\r
+ * Enable this funciton, SCLK will run continuously in synchronous mode, allowing\r
+ * characters to be received on Un_RxD independently from transmission on Un_TXD).\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param enable Enable Continuous Clock generation mode or not, true for enable and false for disable.\r
+ */\r
+static inline void USART_EnableContinuousSCLK(USART_Type *base, bool enable)\r
+{\r
+ if (enable)\r
+ {\r
+ base->CTL |= USART_CTL_CC_MASK;\r
+ }\r
+ else\r
+ {\r
+ base->CTL &= ~USART_CTL_CC_MASK;\r
+ }\r
+}\r
+\r
+/*!\r
+ * @brief Enable Continuous Clock generation bit auto clear.\r
+ * While enable this cuntion, the Continuous Clock bit is automatically cleared when a complete\r
+ * character has been received. This bit is cleared at the same time.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param enable Enable auto clear or not, true for enable and false for disable.\r
+ */\r
+static inline void USART_EnableAutoClearSCLK(USART_Type *base, bool enable)\r
+{\r
+ if (enable)\r
+ {\r
+ base->CTL |= USART_CTL_CLRCCONRX_MASK;\r
+ }\r
+ else\r
+ {\r
+ base->CTL &= ~USART_CTL_CLRCCONRX_MASK;\r
+ }\r
+}\r
+/* @} */\r
+\r
+/*!\r
+ * @name Bus Operations\r
+ * @{\r
+ */\r
+\r
+/*!\r
+ * @brief Writes to the FIFOWR register.\r
+ *\r
+ * This function writes data to the txFIFO directly. The upper layer must ensure\r
+ * that txFIFO has space for data to write before calling this function.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param data The byte to write.\r
+ */\r
+static inline void USART_WriteByte(USART_Type *base, uint8_t data)\r
+{\r
+ base->FIFOWR = data;\r
+}\r
+\r
+/*!\r
+ * @brief Reads the FIFORD register directly.\r
+ *\r
+ * This function reads data from the rxFIFO directly. The upper layer must\r
+ * ensure that the rxFIFO is not empty before calling this function.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @return The byte read from USART data register.\r
+ */\r
+static inline uint8_t USART_ReadByte(USART_Type *base)\r
+{\r
+ return (uint8_t)base->FIFORD;\r
+}\r
+\r
+/*!\r
+ * @brief Writes to the TX register using a blocking method.\r
+ *\r
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO\r
+ * to have room and writes data to the TX buffer.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param data Start address of the data to write.\r
+ * @param length Size of the data to write.\r
+ */\r
+void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length);\r
+\r
+/*!\r
+ * @brief Read RX data register using a blocking method.\r
+ *\r
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to\r
+ * have data and read data from the TX register.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param data Start address of the buffer to store the received data.\r
+ * @param length Size of the buffer.\r
+ * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data.\r
+ * @retval kStatus_USART_ParityError Noise error happened while receiving data.\r
+ * @retval kStatus_USART_NoiseError Framing error happened while receiving data.\r
+ * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened.\r
+ * @retval kStatus_Success Successfully received all data.\r
+ */\r
+status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length);\r
+\r
+/* @} */\r
+\r
+/*!\r
+ * @name Transactional\r
+ * @{\r
+ */\r
+\r
+/*!\r
+ * @brief Initializes the USART handle.\r
+ *\r
+ * This function initializes the USART handle which can be used for other USART\r
+ * transactional APIs. Usually, for a specified USART instance,\r
+ * call this API once to get the initialized handle.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param handle USART handle pointer.\r
+ * @param callback The callback function.\r
+ * @param userData The parameter of the callback function.\r
+ */\r
+status_t USART_TransferCreateHandle(USART_Type *base,\r
+ usart_handle_t *handle,\r
+ usart_transfer_callback_t callback,\r
+ void *userData);\r
+\r
+/*!\r
+ * @brief Transmits a buffer of data using the interrupt method.\r
+ *\r
+ * This function sends data using an interrupt method. This is a non-blocking function, which\r
+ * returns directly without waiting for all data to be written to the TX register. When\r
+ * all data is written to the TX register in the IRQ handler, the USART driver calls the callback\r
+ * function and passes the @ref kStatus_USART_TxIdle as status parameter.\r
+ *\r
+ * @note The kStatus_USART_TxIdle is passed to the upper layer when all data is written\r
+ * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX,\r
+ * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param handle USART handle pointer.\r
+ * @param xfer USART transfer structure. See #usart_transfer_t.\r
+ * @retval kStatus_Success Successfully start the data transmission.\r
+ * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet.\r
+ * @retval kStatus_InvalidArgument Invalid argument.\r
+ */\r
+status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer);\r
+\r
+/*!\r
+ * @brief Sets up the RX ring buffer.\r
+ *\r
+ * This function sets up the RX ring buffer to a specific USART handle.\r
+ *\r
+ * When the RX ring buffer is used, data received are stored into the ring buffer even when the\r
+ * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received\r
+ * in the ring buffer, the user can get the received data from the ring buffer directly.\r
+ *\r
+ * @note When using the RX ring buffer, one byte is reserved for internal use. In other\r
+ * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param handle USART handle pointer.\r
+ * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.\r
+ * @param ringBufferSize size of the ring buffer.\r
+ */\r
+void USART_TransferStartRingBuffer(USART_Type *base,\r
+ usart_handle_t *handle,\r
+ uint8_t *ringBuffer,\r
+ size_t ringBufferSize);\r
+\r
+/*!\r
+ * @brief Aborts the background transfer and uninstalls the ring buffer.\r
+ *\r
+ * This function aborts the background transfer and uninstalls the ring buffer.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param handle USART handle pointer.\r
+ */\r
+void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle);\r
+\r
+/*!\r
+ * @brief Get the length of received data in RX ring buffer.\r
+ *\r
+ * @param handle USART handle pointer.\r
+ * @return Length of received data in RX ring buffer.\r
+ */\r
+size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle);\r
+\r
+/*!\r
+ * @brief Aborts the interrupt-driven data transmit.\r
+ *\r
+ * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out\r
+ * how many bytes are still not sent out.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param handle USART handle pointer.\r
+ */\r
+void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle);\r
+\r
+/*!\r
+ * @brief Get the number of bytes that have been written to USART TX register.\r
+ *\r
+ * This function gets the number of bytes that have been written to USART TX\r
+ * register by interrupt method.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param handle USART handle pointer.\r
+ * @param count Send bytes count.\r
+ * @retval kStatus_NoTransferInProgress No send in progress.\r
+ * @retval kStatus_InvalidArgument Parameter is invalid.\r
+ * @retval kStatus_Success Get successfully through the parameter \p count;\r
+ */\r
+status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count);\r
+\r
+/*!\r
+ * @brief Receives a buffer of data using an interrupt method.\r
+ *\r
+ * This function receives data using an interrupt method. This is a non-blocking function, which\r
+ * returns without waiting for all data to be received.\r
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and\r
+ * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer.\r
+ * After copying, if the data in the ring buffer is not enough to read, the receive\r
+ * request is saved by the USART driver. When the new data arrives, the receive request\r
+ * is serviced first. When all data is received, the USART driver notifies the upper layer\r
+ * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle.\r
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer.\r
+ * The 5 bytes are copied to the xfer->data and this function returns with the\r
+ * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is\r
+ * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer.\r
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt\r
+ * to receive data to the xfer->data. When all data is received, the upper layer is notified.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param handle USART handle pointer.\r
+ * @param xfer USART transfer structure, see #usart_transfer_t.\r
+ * @param receivedBytes Bytes received from the ring buffer directly.\r
+ * @retval kStatus_Success Successfully queue the transfer into transmit queue.\r
+ * @retval kStatus_USART_RxBusy Previous receive request is not finished.\r
+ * @retval kStatus_InvalidArgument Invalid argument.\r
+ */\r
+status_t USART_TransferReceiveNonBlocking(USART_Type *base,\r
+ usart_handle_t *handle,\r
+ usart_transfer_t *xfer,\r
+ size_t *receivedBytes);\r
+\r
+/*!\r
+ * @brief Aborts the interrupt-driven data receiving.\r
+ *\r
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out\r
+ * how many bytes not received yet.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param handle USART handle pointer.\r
+ */\r
+void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle);\r
+\r
+/*!\r
+ * @brief Get the number of bytes that have been received.\r
+ *\r
+ * This function gets the number of bytes that have been received.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param handle USART handle pointer.\r
+ * @param count Receive bytes count.\r
+ * @retval kStatus_NoTransferInProgress No receive in progress.\r
+ * @retval kStatus_InvalidArgument Parameter is invalid.\r
+ * @retval kStatus_Success Get successfully through the parameter \p count;\r
+ */\r
+status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count);\r
+\r
+/*!\r
+ * @brief USART IRQ handle function.\r
+ *\r
+ * This function handles the USART transmit and receive IRQ request.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param handle USART handle pointer.\r
+ */\r
+void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle);\r
+\r
+/* @} */\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif\r
+\r
+/*! @}*/\r
+\r
+#endif /* _FSL_USART_H_ */\r
--- /dev/null
+/*\r
+ * Copyright 2017-2019 NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+/* freertos_tasks_c_additions.h Rev. 1.3 */\r
+#ifndef FREERTOS_TASKS_C_ADDITIONS_H\r
+#define FREERTOS_TASKS_C_ADDITIONS_H\r
+\r
+#include <stdint.h>\r
+\r
+#if (configUSE_TRACE_FACILITY == 0)\r
+#error "configUSE_TRACE_FACILITY must be enabled"\r
+#endif\r
+\r
+#define FREERTOS_DEBUG_CONFIG_MAJOR_VERSION 1\r
+#define FREERTOS_DEBUG_CONFIG_MINOR_VERSION 3\r
+\r
+/* NOTE!!\r
+ * Default to a FreeRTOS version which didn't include these macros. FreeRTOS\r
+ * v7.5.3 is used here.\r
+ */\r
+#ifndef tskKERNEL_VERSION_BUILD\r
+#define tskKERNEL_VERSION_BUILD 3\r
+#endif\r
+#ifndef tskKERNEL_VERSION_MINOR\r
+#define tskKERNEL_VERSION_MINOR 5\r
+#endif\r
+#ifndef tskKERNEL_VERSION_MAJOR\r
+#define tskKERNEL_VERSION_MAJOR 7\r
+#endif\r
+\r
+/* NOTE!!\r
+ * The configFRTOS_MEMORY_SCHEME macro describes the heap scheme using a value\r
+ * 1 - 5 which corresponds to the following schemes:\r
+ *\r
+ * heap_1 - the very simplest, does not permit memory to be freed\r
+ * heap_2 - permits memory to be freed, but not does coalescence adjacent free\r
+ * blocks.\r
+ * heap_3 - simply wraps the standard malloc() and free() for thread safety\r
+ * heap_4 - coalesces adjacent free blocks to avoid fragmentation. Includes\r
+ * absolute address placement option\r
+ * heap_5 - as per heap_4, with the ability to span the heap across\r
+ * multiple nonOadjacent memory areas\r
+ */\r
+#ifndef configFRTOS_MEMORY_SCHEME\r
+#define configFRTOS_MEMORY_SCHEME 3 /* thread safe malloc */\r
+#endif\r
+\r
+#if ((configFRTOS_MEMORY_SCHEME > 5) || (configFRTOS_MEMORY_SCHEME < 1))\r
+#error "Invalid configFRTOS_MEMORY_SCHEME setting!"\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+extern const uint8_t FreeRTOSDebugConfig[];\r
+\r
+/* NOTES!!\r
+ * IAR documentation is confusing. It suggests the data must be statically\r
+ * linked, and the #pragma placed immediately before the symbol definition.\r
+ * The IAR supplied examples violate both "rules", so this is a best guess.\r
+ */\r
+\r
+#if (tskKERNEL_VERSION_MAJOR >= 10) && (tskKERNEL_VERSION_MINOR >= 2)\r
+#if defined(__GNUC__)\r
+char *const portArch_Name __attribute__((section(".rodata"))) = portARCH_NAME;\r
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)\r
+char *const portArch_Name __attribute__((used)) = portARCH_NAME;\r
+#elif defined(__IAR_SYSTEMS_ICC__)\r
+char *const portArch_Name = portARCH_NAME;\r
+#pragma required=portArch_Name\r
+#endif\r
+#else\r
+char *const portArch_Name = NULL;\r
+#endif // tskKERNEL_VERSION_MAJOR\r
+\r
+#if defined(__GNUC__)\r
+const uint8_t FreeRTOSDebugConfig[] __attribute__((section(".rodata"))) =\r
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)\r
+const uint8_t FreeRTOSDebugConfig[] __attribute__((used)) =\r
+#elif defined(__IAR_SYSTEMS_ICC__)\r
+#pragma required=FreeRTOSDebugConfig\r
+const uint8_t FreeRTOSDebugConfig[] =\r
+#endif\r
+{\r
+ FREERTOS_DEBUG_CONFIG_MAJOR_VERSION,\r
+ FREERTOS_DEBUG_CONFIG_MINOR_VERSION,\r
+ tskKERNEL_VERSION_MAJOR,\r
+ tskKERNEL_VERSION_MINOR,\r
+ tskKERNEL_VERSION_BUILD,\r
+ configFRTOS_MEMORY_SCHEME,\r
+ offsetof(struct tskTaskControlBlock, pxTopOfStack),\r
+#if (tskKERNEL_VERSION_MAJOR > 8)\r
+ offsetof(struct tskTaskControlBlock, xStateListItem),\r
+#else\r
+ offsetof(struct tskTaskControlBlock, xGenericListItem),\r
+#endif\r
+ offsetof(struct tskTaskControlBlock, xEventListItem),\r
+ offsetof(struct tskTaskControlBlock, pxStack),\r
+ offsetof(struct tskTaskControlBlock, pcTaskName),\r
+ offsetof(struct tskTaskControlBlock, uxTCBNumber),\r
+ offsetof(struct tskTaskControlBlock, uxTaskNumber),\r
+ configMAX_TASK_NAME_LEN,\r
+ configMAX_PRIORITIES,\r
+ configENABLE_MPU,\r
+ configENABLE_FPU,\r
+ configENABLE_TRUSTZONE,\r
+ configRUN_FREERTOS_SECURE_ONLY,\r
+ 0, // 32-bit align\r
+ 0, 0, 0, 0 // padding\r
+};\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // FREERTOS_TASKS_C_ADDITIONS_H\r
--- /dev/null
+/*\r
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2017 NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#include "fsl_common.h"\r
+#include "fsl_debug_console.h"\r
+\r
+#ifndef NDEBUG\r
+#if (defined(__CC_ARM)) || (defined(__ARMCC_VERSION)) || (defined(__ICCARM__))\r
+void __aeabi_assert(const char *failedExpr, const char *file, int line)\r
+{\r
+ PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);\r
+ for (;;)\r
+ {\r
+ __BKPT(0);\r
+ }\r
+}\r
+#elif (defined(__GNUC__))\r
+#if defined(__REDLIB__)\r
+void __assertion_failed(char *failedExpr)\r
+{\r
+ PRINTF("ASSERT ERROR \" %s \n", failedExpr);\r
+ for (;;)\r
+ {\r
+ __BKPT(0);\r
+ }\r
+}\r
+#else\r
+void __assert_func(const char *file, int line, const char *func, const char *failedExpr)\r
+{\r
+ PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);\r
+ for (;;)\r
+ {\r
+ __BKPT(0);\r
+ }\r
+}\r
+#endif /* defined(__REDLIB__) */\r
+#endif /* (defined(__CC_ARM) || (defined(__ICCARM__)) || (defined(__ARMCC_VERSION)) */\r
+#endif /* NDEBUG */\r
--- /dev/null
+/*\r
+ * This is a modified version of the file printf.c, which was distributed\r
+ * by Motorola as part of the M5407C3BOOT.zip package used to initialize\r
+ * the M5407C3 evaluation board.\r
+ *\r
+ * Copyright:\r
+ * 1999-2000 MOTOROLA, INC. All Rights Reserved.\r
+ * You are hereby granted a copyright license to use, modify, and\r
+ * distribute the SOFTWARE so long as this entire notice is\r
+ * retained without alteration in any modified and/or redistributed\r
+ * versions, and that such modified versions are clearly identified\r
+ * as such. No licenses are granted by implication, estoppel or\r
+ * otherwise under any patents or trademarks of Motorola, Inc. This\r
+ * software is provided on an "AS IS" basis and without warranty.\r
+ *\r
+ * To the maximum extent permitted by applicable law, MOTOROLA\r
+ * DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR\r
+ * PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE\r
+ * SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY\r
+ * ACCOMPANYING WRITTEN MATERIALS.\r
+ *\r
+ * To the maximum extent permitted by applicable law, IN NO EVENT\r
+ * SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING\r
+ * WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS\r
+ * INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY\r
+ * LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.\r
+ *\r
+ * Motorola assumes no responsibility for the maintenance and support\r
+ * of this software\r
+\r
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2019 NXP\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#include <stdarg.h>\r
+#include <stdlib.h>\r
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)\r
+#include <stdio.h>\r
+#endif\r
+\r
+#ifdef FSL_RTOS_FREE_RTOS\r
+#include "FreeRTOS.h"\r
+#include "semphr.h"\r
+#include "task.h"\r
+#endif\r
+\r
+#include "fsl_debug_console_conf.h"\r
+#include "fsl_str.h"\r
+\r
+#include "fsl_common.h"\r
+#include "serial_manager.h"\r
+\r
+#include "fsl_debug_console.h"\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+#ifndef NDEBUG\r
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))\r
+#undef assert\r
+#define assert(n)\r
+#endif\r
+#endif\r
+\r
+#if SDK_DEBUGCONSOLE\r
+#define DEBUG_CONSOLE_FUNCTION_PREFIX\r
+#else\r
+#define DEBUG_CONSOLE_FUNCTION_PREFIX static\r
+#endif\r
+\r
+/*! @brief character backspace ASCII value */\r
+#define DEBUG_CONSOLE_BACKSPACE 127U\r
+\r
+/* lock definition */\r
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)\r
+\r
+static SemaphoreHandle_t s_debugConsoleReadSemaphore;\r
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))\r
+static SemaphoreHandle_t s_debugConsoleReadWaitSemaphore;\r
+#endif\r
+\r
+#elif (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM)\r
+\r
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))\r
+static volatile uint8_t s_debugConsoleReadWaitSemaphore;\r
+#endif\r
+\r
+#else\r
+\r
+#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */\r
+\r
+/*! @brief get current runing environment is ISR or not */\r
+#ifdef __CA7_REV\r
+#define IS_RUNNING_IN_ISR() SystemGetIRQNestingLevel()\r
+#else\r
+#define IS_RUNNING_IN_ISR() __get_IPSR()\r
+#endif /* __CA7_REV */\r
+\r
+/* semaphore definition */\r
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)\r
+\r
+/* mutex semaphore */\r
+/* clang-format off */\r
+#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex) ((mutex) = xSemaphoreCreateMutex())\r
+#define DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(mutex) \\r
+ do \\r
+ { \\r
+ if(NULL != mutex) \\r
+ { \\r
+ vSemaphoreDelete(mutex); \\r
+ mutex = NULL; \\r
+ } \\r
+ } while(0)\r
+\r
+#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex) \\r
+{ \\r
+ if (IS_RUNNING_IN_ISR() == 0U) \\r
+ { \\r
+ (void)xSemaphoreGive(mutex); \\r
+ } \\r
+}\r
+\r
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) \\r
+{ \\r
+ if (IS_RUNNING_IN_ISR() == 0U) \\r
+ { \\r
+ (void)xSemaphoreTake(mutex, portMAX_DELAY); \\r
+ } \\r
+}\r
+\r
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) \\r
+{ \\r
+ if (IS_RUNNING_IN_ISR() == 0U) \\r
+ { \\r
+ result = xSemaphoreTake(mutex, 0U); \\r
+ } \\r
+ else \\r
+ { \\r
+ result = 1U; \\r
+ } \\r
+}\r
+\r
+/* Binary semaphore */\r
+#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary) ((binary) = xSemaphoreCreateBinary())\r
+#define DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(binary) \\r
+ do \\r
+ { \\r
+ if(NULL != binary) \\r
+ { \\r
+ vSemaphoreDelete(binary); \\r
+ binary = NULL; \\r
+ } \\r
+ } while(0)\r
+#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) ((void)xSemaphoreTake(binary, portMAX_DELAY))\r
+#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) ((void)xSemaphoreGiveFromISR(binary, NULL))\r
+\r
+#elif (DEBUG_CONSOLE_SYNCHRONIZATION_BM == DEBUG_CONSOLE_SYNCHRONIZATION_MODE)\r
+\r
+#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex)\r
+#define DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(mutex)\r
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex)\r
+#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex)\r
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) (result = 1U)\r
+\r
+#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary)\r
+#define DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(binary)\r
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING\r
+#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) \\r
+ { \\r
+ while (!binary) \\r
+ { \\r
+ } \\r
+ binary = false; \\r
+ }\r
+#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) (binary = true)\r
+#else\r
+#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary)\r
+#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary)\r
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */\r
+/* clang-format on */\r
+\r
+/* add other implementation here\r
+ *such as :\r
+ * #elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DDEBUG_CONSOLE_SYNCHRONIZATION_xxx)\r
+ */\r
+\r
+#else\r
+\r
+#error RTOS type is not defined by DEBUG_CONSOLE_SYNCHRONIZATION_MODE.\r
+\r
+#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */\r
+\r
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING\r
+/* receive state structure */\r
+typedef struct _debug_console_write_ring_buffer\r
+{\r
+ uint32_t ringBufferSize;\r
+ volatile uint32_t ringHead;\r
+ volatile uint32_t ringTail;\r
+ uint8_t ringBuffer[DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN];\r
+} debug_console_write_ring_buffer_t;\r
+#endif\r
+\r
+typedef struct _debug_console_state_struct\r
+{\r
+ uint8_t serialHandleBuffer[SERIAL_MANAGER_HANDLE_SIZE];\r
+ serial_handle_t serialHandle; /*!< serial manager handle */\r
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING\r
+ debug_console_write_ring_buffer_t writeRingBuffer;\r
+ uint8_t readRingBuffer[DEBUG_CONSOLE_RECEIVE_BUFFER_LEN];\r
+#endif\r
+ uint8_t serialWriteHandleBuffer[SERIAL_MANAGER_WRITE_HANDLE_SIZE];\r
+ uint8_t serialReadHandleBuffer[SERIAL_MANAGER_READ_HANDLE_SIZE];\r
+} debug_console_state_struct_t;\r
+\r
+/*******************************************************************************\r
+ * Variables\r
+ ******************************************************************************/\r
+\r
+/*! @brief Debug console state information. */\r
+#if (defined(DATA_SECTION_IS_CACHEABLE) && (DATA_SECTION_IS_CACHEABLE > 0))\r
+AT_NONCACHEABLE_SECTION(static debug_console_state_struct_t s_debugConsoleState);\r
+#else\r
+static debug_console_state_struct_t s_debugConsoleState;\r
+#endif\r
+serial_handle_t g_serialHandle; /*!< serial manager handle */\r
+\r
+/*******************************************************************************\r
+ * Prototypes\r
+ ******************************************************************************/\r
+/*!\r
+ * @brief This is a printf call back function which is used to relocate the log to buffer\r
+ * or print the log immediately when the local buffer is full.\r
+ *\r
+ * @param[in] buf Buffer to store log.\r
+ * @param[in] indicator Buffer index.\r
+ * @param[in] val Target character to store.\r
+ * @param[in] len length of the character\r
+ *\r
+ */\r
+#if SDK_DEBUGCONSOLE\r
+static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, int len);\r
+#endif\r
+\r
+status_t DbgConsole_ReadOneCharacter(uint8_t *ch);\r
+int DbgConsole_SendData(uint8_t *ch, size_t size);\r
+int DbgConsole_SendDataReliable(uint8_t *ch, size_t size);\r
+int DbgConsole_ReadLine(uint8_t *buf, size_t size);\r
+int DbgConsole_ReadCharacter(uint8_t *ch);\r
+\r
+#if ((SDK_DEBUGCONSOLE > 0U) || \\r
+ ((SDK_DEBUGCONSOLE == 0U) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \\r
+ (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))))\r
+DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void);\r
+#endif\r
+/*******************************************************************************\r
+ * Code\r
+ ******************************************************************************/\r
+\r
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)\r
+\r
+static void DbgConsole_SerialManagerTxCallback(void *callbackParam,\r
+ serial_manager_callback_message_t *message,\r
+ serial_manager_status_t status)\r
+{\r
+ debug_console_state_struct_t *ioState;\r
+ uint32_t sendDataLength;\r
+\r
+ if ((NULL == callbackParam) || (NULL == message))\r
+ {\r
+ return;\r
+ }\r
+\r
+ ioState = (debug_console_state_struct_t *)callbackParam;\r
+\r
+ ioState->writeRingBuffer.ringTail += message->length;\r
+ if (ioState->writeRingBuffer.ringTail >= ioState->writeRingBuffer.ringBufferSize)\r
+ {\r
+ ioState->writeRingBuffer.ringTail = 0U;\r
+ }\r
+\r
+ if (kStatus_SerialManager_Success == status)\r
+ {\r
+ if (ioState->writeRingBuffer.ringTail != ioState->writeRingBuffer.ringHead)\r
+ {\r
+ if (ioState->writeRingBuffer.ringHead > ioState->writeRingBuffer.ringTail)\r
+ {\r
+ sendDataLength = ioState->writeRingBuffer.ringHead - ioState->writeRingBuffer.ringTail;\r
+ }\r
+ else\r
+ {\r
+ sendDataLength = ioState->writeRingBuffer.ringBufferSize - ioState->writeRingBuffer.ringTail;\r
+ }\r
+\r
+ (void)SerialManager_WriteNonBlocking(\r
+ ((serial_write_handle_t)&ioState->serialWriteHandleBuffer[0]),\r
+ &ioState->writeRingBuffer.ringBuffer[ioState->writeRingBuffer.ringTail], sendDataLength);\r
+ }\r
+ }\r
+ else if (kStatus_SerialManager_Canceled == status)\r
+ {\r
+ ioState->writeRingBuffer.ringTail = 0U;\r
+ ioState->writeRingBuffer.ringHead = 0U;\r
+ }\r
+ else\r
+ {\r
+ /*MISRA rule 16.4*/\r
+ }\r
+}\r
+\r
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))\r
+\r
+static void DbgConsole_SerialManagerRxCallback(void *callbackParam,\r
+ serial_manager_callback_message_t *message,\r
+ serial_manager_status_t status)\r
+{\r
+ if ((NULL == callbackParam) || (NULL == message))\r
+ {\r
+ return;\r
+ }\r
+\r
+ if (kStatus_SerialManager_Notify == status)\r
+ {\r
+ }\r
+ else if (kStatus_SerialManager_Success == status)\r
+ {\r
+ /* release s_debugConsoleReadWaitSemaphore from RX callback */\r
+ DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(s_debugConsoleReadWaitSemaphore);\r
+ }\r
+ else\r
+ {\r
+ /*MISRA rule 16.4*/\r
+ }\r
+}\r
+#endif\r
+\r
+#endif\r
+\r
+status_t DbgConsole_ReadOneCharacter(uint8_t *ch)\r
+{\r
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))\r
+\r
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \\r
+ (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)\r
+ return kStatus_Fail;\r
+#else\r
+ status_t status = (status_t)kStatus_SerialManager_Error;\r
+\r
+/* recieve one char every time */\r
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)\r
+ status = (status_t)SerialManager_ReadNonBlocking(\r
+ ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1);\r
+#else\r
+ status = (status_t)SerialManager_ReadBlocking(\r
+ ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1);\r
+#endif\r
+ if ((status_t)kStatus_SerialManager_Success != status)\r
+ {\r
+ return (status_t)kStatus_Fail;\r
+ }\r
+ /* wait s_debugConsoleReadWaitSemaphore from RX callback */\r
+ DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(s_debugConsoleReadWaitSemaphore);\r
+\r
+ return (status_t)kStatus_Success;\r
+#endif\r
+\r
+#else\r
+\r
+ return (status_t)kStatus_Fail;\r
+\r
+#endif\r
+}\r
+\r
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION\r
+static status_t DbgConsole_EchoCharacter(uint8_t *ch, bool isGetChar, int *index)\r
+{\r
+ /* Due to scanf take \n and \r as end of string,should not echo */\r
+ if (((*ch != (uint8_t)'\r') && (*ch != (uint8_t)'\n')) || (isGetChar))\r
+ {\r
+ /* recieve one char every time */\r
+ if (1 != DbgConsole_SendDataReliable(ch, 1U))\r
+ {\r
+ return (status_t)kStatus_Fail;\r
+ }\r
+ }\r
+\r
+ if ((!isGetChar) && (index != NULL))\r
+ {\r
+ if (DEBUG_CONSOLE_BACKSPACE == *ch)\r
+ {\r
+ if ((*index >= 2))\r
+ {\r
+ *index -= 2;\r
+ }\r
+ else\r
+ {\r
+ *index = 0;\r
+ }\r
+ }\r
+ }\r
+\r
+ return (status_t)kStatus_Success;\r
+}\r
+#endif\r
+\r
+int DbgConsole_SendData(uint8_t *ch, size_t size)\r
+{\r
+ status_t status = (status_t)kStatus_SerialManager_Error;\r
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)\r
+ uint32_t sendDataLength;\r
+ int txBusy = 0;\r
+#endif\r
+ assert(NULL != ch);\r
+ assert(0 != size);\r
+\r
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)\r
+ uint32_t regPrimask = DisableGlobalIRQ();\r
+ if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)\r
+ {\r
+ txBusy = 1;\r
+ sendDataLength =\r
+ (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize -\r
+ s_debugConsoleState.writeRingBuffer.ringTail) %\r
+ s_debugConsoleState.writeRingBuffer.ringBufferSize;\r
+ }\r
+ else\r
+ {\r
+ sendDataLength = 0U;\r
+ }\r
+ sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength - 1;\r
+ if (sendDataLength < size)\r
+ {\r
+ EnableGlobalIRQ(regPrimask);\r
+ return -1;\r
+ }\r
+ for (int i = 0; i < (int)size; i++)\r
+ {\r
+ s_debugConsoleState.writeRingBuffer.ringBuffer[s_debugConsoleState.writeRingBuffer.ringHead++] = ch[i];\r
+ if (s_debugConsoleState.writeRingBuffer.ringHead >= s_debugConsoleState.writeRingBuffer.ringBufferSize)\r
+ {\r
+ s_debugConsoleState.writeRingBuffer.ringHead = 0U;\r
+ }\r
+ }\r
+\r
+ status = (status_t)kStatus_SerialManager_Success;\r
+\r
+ if (txBusy == 0)\r
+ {\r
+ if (s_debugConsoleState.writeRingBuffer.ringHead > s_debugConsoleState.writeRingBuffer.ringTail)\r
+ {\r
+ sendDataLength =\r
+ s_debugConsoleState.writeRingBuffer.ringHead - s_debugConsoleState.writeRingBuffer.ringTail;\r
+ }\r
+ else\r
+ {\r
+ sendDataLength =\r
+ s_debugConsoleState.writeRingBuffer.ringBufferSize - s_debugConsoleState.writeRingBuffer.ringTail;\r
+ }\r
+\r
+ status = (status_t)SerialManager_WriteNonBlocking(\r
+ ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]),\r
+ &s_debugConsoleState.writeRingBuffer.ringBuffer[s_debugConsoleState.writeRingBuffer.ringTail],\r
+ sendDataLength);\r
+ }\r
+ EnableGlobalIRQ(regPrimask);\r
+#else\r
+ status = (status_t)SerialManager_WriteBlocking(\r
+ ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size);\r
+#endif\r
+ return (((status_t)kStatus_Success == status) ? (int)size : -1);\r
+}\r
+\r
+int DbgConsole_SendDataReliable(uint8_t *ch, size_t size)\r
+{\r
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)\r
+#if (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))\r
+ status_t status = kStatus_SerialManager_Error;\r
+ uint32_t sendDataLength;\r
+ uint32_t totalLength = size;\r
+ int sentLength;\r
+#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */\r
+#else\r
+ status_t status = kStatus_SerialManager_Error;\r
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */\r
+\r
+ assert(NULL != ch);\r
+ assert(0 != size);\r
+\r
+ if (NULL == g_serialHandle)\r
+ {\r
+ return 0;\r
+ }\r
+\r
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)\r
+\r
+#if (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))\r
+ do\r
+ {\r
+ uint32_t regPrimask = DisableGlobalIRQ();\r
+ if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)\r
+ {\r
+ sendDataLength =\r
+ (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize -\r
+ s_debugConsoleState.writeRingBuffer.ringTail) %\r
+ s_debugConsoleState.writeRingBuffer.ringBufferSize;\r
+ }\r
+ else\r
+ {\r
+ sendDataLength = 0U;\r
+ }\r
+ sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength - 1U;\r
+\r
+ if (sendDataLength > 0U)\r
+ {\r
+ if (sendDataLength > totalLength)\r
+ {\r
+ sendDataLength = totalLength;\r
+ }\r
+\r
+ sentLength = DbgConsole_SendData(&ch[size - totalLength], sendDataLength);\r
+ if (sentLength > 0)\r
+ {\r
+ totalLength = totalLength - (uint32_t)sentLength;\r
+ }\r
+ }\r
+ EnableGlobalIRQ(regPrimask);\r
+\r
+ if (totalLength != 0U)\r
+ {\r
+ status = DbgConsole_Flush();\r
+ if ((status_t)kStatus_Success != status)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ } while (totalLength != 0U);\r
+ return (status_t)(uint32_t)((uint32_t)size - totalLength);\r
+#else\r
+ return DbgConsole_SendData(ch, size);\r
+#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */\r
+\r
+#else\r
+ status = (status_t)SerialManager_WriteBlocking(\r
+ ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size);\r
+ return (((status_t)kStatus_Success == status) ? (int)size : -1);\r
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */\r
+}\r
+\r
+int DbgConsole_ReadLine(uint8_t *buf, size_t size)\r
+{\r
+ int i = 0;\r
+\r
+ assert(buf != NULL);\r
+\r
+ if (NULL == g_serialHandle)\r
+ {\r
+ return -1;\r
+ }\r
+\r
+ /* take mutex lock function */\r
+ DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore);\r
+\r
+ do\r
+ {\r
+ /* recieve one char every time */\r
+ if ((status_t)kStatus_Success != DbgConsole_ReadOneCharacter(&buf[i]))\r
+ {\r
+ /* release mutex lock function */\r
+ DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);\r
+ i = -1;\r
+ break;\r
+ }\r
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION\r
+ (void)DbgConsole_EchoCharacter(&buf[i], false, &i);\r
+#endif\r
+ /* analysis data */\r
+ if (((uint8_t)'\r' == buf[i]) || ((uint8_t)'\n' == buf[i]))\r
+ {\r
+ /* End of Line. */\r
+ if (0 == i)\r
+ {\r
+ buf[i] = (uint8_t)'\0';\r
+ continue;\r
+ }\r
+ else\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ i++;\r
+ } while (i < (int)size);\r
+\r
+ /* get char should not add '\0'*/\r
+ if (i == (int)size)\r
+ {\r
+ buf[i] = (uint8_t)'\0';\r
+ }\r
+ else\r
+ {\r
+ buf[i + 1] = (uint8_t)'\0';\r
+ }\r
+\r
+ /* release mutex lock function */\r
+ DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);\r
+\r
+ return i;\r
+}\r
+\r
+int DbgConsole_ReadCharacter(uint8_t *ch)\r
+{\r
+ int ret;\r
+\r
+ assert(ch);\r
+\r
+ if (NULL == g_serialHandle)\r
+ {\r
+ return -1;\r
+ }\r
+\r
+ /* take mutex lock function */\r
+ DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore);\r
+ /* read one character */\r
+ if ((status_t)kStatus_Success == DbgConsole_ReadOneCharacter(ch))\r
+ {\r
+ ret = 1;\r
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION\r
+ (void)DbgConsole_EchoCharacter(ch, true, NULL);\r
+#endif\r
+ }\r
+ else\r
+ {\r
+ ret = -1;\r
+ }\r
+\r
+ /* release mutex lock function */\r
+ DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);\r
+\r
+ return ret;\r
+}\r
+\r
+#if SDK_DEBUGCONSOLE\r
+static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, int len)\r
+{\r
+ int i = 0;\r
+\r
+ for (i = 0; i < len; i++)\r
+ {\r
+ if (((uint32_t)*indicator + 1UL) >= DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN)\r
+ {\r
+ (void)DbgConsole_SendDataReliable((uint8_t *)buf, (uint32_t)(*indicator));\r
+ *indicator = 0;\r
+ }\r
+\r
+ buf[*indicator] = dbgVal;\r
+ (*indicator)++;\r
+ }\r
+}\r
+#endif\r
+\r
+/*************Code for DbgConsole Init, Deinit, Printf, Scanf *******************************/\r
+\r
+#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART))\r
+/* See fsl_debug_console.h for documentation of this function. */\r
+status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq)\r
+{\r
+ serial_manager_config_t serialConfig;\r
+ status_t status = (status_t)kStatus_SerialManager_Error;\r
+\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+ serial_port_uart_config_t uartConfig = {\r
+ .instance = instance,\r
+ .clockRate = clkSrcFreq,\r
+ .baudRate = baudRate,\r
+ .parityMode = kSerialManager_UartParityDisabled,\r
+ .stopBitCount = kSerialManager_UartOneStopBit,\r
+ .enableRx = 1,\r
+ .enableTx = 1,\r
+ };\r
+#endif\r
+\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+ serial_port_usb_cdc_config_t usbCdcConfig = {\r
+ .controllerIndex = (serial_port_usb_cdc_controller_index_t)instance,\r
+ };\r
+#endif\r
+\r
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))\r
+ serial_port_swo_config_t swoConfig = {\r
+ .clockRate = clkSrcFreq,\r
+ .baudRate = baudRate,\r
+ .port = instance,\r
+ .protocol = kSerialManager_SwoProtocolNrz,\r
+ };\r
+#endif\r
+\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))\r
+ serial_port_usb_cdc_virtual_config_t usbCdcVirtualConfig = {\r
+ .controllerIndex = (serial_port_usb_cdc_virtual_controller_index_t)instance,\r
+ };\r
+#endif\r
+ serialConfig.type = device;\r
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)\r
+ serialConfig.ringBuffer = &s_debugConsoleState.readRingBuffer[0];\r
+ serialConfig.ringBufferSize = DEBUG_CONSOLE_RECEIVE_BUFFER_LEN;\r
+#endif\r
+\r
+ if (kSerialPort_Uart == device)\r
+ {\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+ serialConfig.portConfig = &uartConfig;\r
+#else\r
+ return status;\r
+#endif\r
+ }\r
+ else if (kSerialPort_UsbCdc == device)\r
+ {\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+ serialConfig.portConfig = &usbCdcConfig;\r
+#else\r
+ return status;\r
+#endif\r
+ }\r
+ else if (kSerialPort_Swo == device)\r
+ {\r
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))\r
+ serialConfig.portConfig = &swoConfig;\r
+#else\r
+ return status;\r
+#endif\r
+ }\r
+ else if (kSerialPort_UsbCdcVirtual == device)\r
+ {\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))\r
+ serialConfig.portConfig = &usbCdcVirtualConfig;\r
+#else\r
+ return status;\r
+#endif\r
+ }\r
+ else\r
+ {\r
+ return status;\r
+ }\r
+\r
+ (void)memset(&s_debugConsoleState, 0, sizeof(s_debugConsoleState));\r
+\r
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)\r
+ s_debugConsoleState.writeRingBuffer.ringBufferSize = DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN;\r
+#endif\r
+\r
+ s_debugConsoleState.serialHandle = (serial_handle_t)&s_debugConsoleState.serialHandleBuffer[0];\r
+ status = (status_t)SerialManager_Init(s_debugConsoleState.serialHandle, &serialConfig);\r
+\r
+ assert(kStatus_SerialManager_Success == status);\r
+\r
+ DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);\r
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))\r
+ DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore);\r
+#endif\r
+\r
+ {\r
+ status = (status_t)SerialManager_OpenWriteHandle(\r
+ s_debugConsoleState.serialHandle, ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]));\r
+ assert(kStatus_SerialManager_Success == status);\r
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)\r
+ (void)SerialManager_InstallTxCallback(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]),\r
+ DbgConsole_SerialManagerTxCallback, &s_debugConsoleState);\r
+#endif\r
+ }\r
+\r
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))\r
+ {\r
+ status = (status_t)SerialManager_OpenReadHandle(\r
+ s_debugConsoleState.serialHandle, ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]));\r
+ assert(kStatus_SerialManager_Success == status);\r
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)\r
+ (void)SerialManager_InstallRxCallback(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]),\r
+ DbgConsole_SerialManagerRxCallback, &s_debugConsoleState);\r
+#endif\r
+ }\r
+#endif\r
+\r
+ g_serialHandle = s_debugConsoleState.serialHandle;\r
+\r
+ return kStatus_Success;\r
+}\r
+\r
+/* See fsl_debug_console.h for documentation of this function. */\r
+status_t DbgConsole_Deinit(void)\r
+{\r
+ {\r
+ if (s_debugConsoleState.serialHandle != NULL)\r
+ {\r
+ (void)SerialManager_CloseWriteHandle(\r
+ ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]));\r
+ }\r
+ }\r
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))\r
+ {\r
+ if (s_debugConsoleState.serialHandle != NULL)\r
+ {\r
+ (void)SerialManager_CloseReadHandle(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]));\r
+ }\r
+ }\r
+#endif\r
+ if (s_debugConsoleState.serialHandle)\r
+ {\r
+ if (kStatus_SerialManager_Success == SerialManager_Deinit(s_debugConsoleState.serialHandle))\r
+ {\r
+ s_debugConsoleState.serialHandle = NULL;\r
+ g_serialHandle = NULL;\r
+ }\r
+ }\r
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))\r
+ DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore);\r
+#endif\r
+ DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);\r
+\r
+ return (status_t)kStatus_Success;\r
+}\r
+#endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */\r
+\r
+#if ((SDK_DEBUGCONSOLE > 0U) || \\r
+ ((SDK_DEBUGCONSOLE == 0U) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \\r
+ (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))))\r
+DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void)\r
+{\r
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)\r
+\r
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)\r
+\r
+ if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)\r
+ {\r
+ return (status_t)kStatus_Fail;\r
+ }\r
+\r
+#else\r
+\r
+ while (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)\r
+ {\r
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)\r
+ if (0U == IS_RUNNING_IN_ISR())\r
+ {\r
+ if (taskSCHEDULER_RUNNING == xTaskGetSchedulerState())\r
+ {\r
+ vTaskDelay(1);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ return (status_t)kStatus_Fail;\r
+ }\r
+#endif\r
+ }\r
+\r
+#endif\r
+\r
+#endif\r
+ return (status_t)kStatus_Success;\r
+}\r
+#endif\r
+\r
+#if SDK_DEBUGCONSOLE\r
+/* See fsl_debug_console.h for documentation of this function. */\r
+int DbgConsole_Printf(const char *formatString, ...)\r
+{\r
+ va_list ap;\r
+ int logLength = 0, dbgResult = 0;\r
+ char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {'\0'};\r
+\r
+ if (NULL == g_serialHandle)\r
+ {\r
+ return 0;\r
+ }\r
+\r
+ va_start(ap, formatString);\r
+ /* format print log first */\r
+ logLength = StrFormatPrintf(formatString, ap, printBuf, DbgConsole_PrintCallback);\r
+ /* print log */\r
+ dbgResult = DbgConsole_SendDataReliable((uint8_t *)printBuf, (size_t)logLength);\r
+\r
+ va_end(ap);\r
+\r
+ return dbgResult;\r
+}\r
+\r
+/* See fsl_debug_console.h for documentation of this function. */\r
+int DbgConsole_Putchar(int ch)\r
+{\r
+ /* print char */\r
+ return DbgConsole_SendDataReliable((uint8_t *)&ch, 1U);\r
+}\r
+\r
+/* See fsl_debug_console.h for documentation of this function. */\r
+int DbgConsole_Scanf(char *formatString, ...)\r
+{\r
+ va_list ap;\r
+ int formatResult;\r
+ char scanfBuf[DEBUG_CONSOLE_SCANF_MAX_LOG_LEN + 1U] = {'\0'};\r
+\r
+ /* scanf log */\r
+ (void)DbgConsole_ReadLine((uint8_t *)scanfBuf, DEBUG_CONSOLE_SCANF_MAX_LOG_LEN);\r
+ /* get va_list */\r
+ va_start(ap, formatString);\r
+ /* format scanf log */\r
+ formatResult = StrFormatScanf(scanfBuf, formatString, ap);\r
+\r
+ va_end(ap);\r
+\r
+ return formatResult;\r
+}\r
+/* See fsl_debug_console.h for documentation of this function. */\r
+int DbgConsole_BlockingPrintf(const char *formatString, ...)\r
+{\r
+ va_list ap;\r
+ status_t status = (status_t)kStatus_SerialManager_Error;\r
+ int logLength = 0, dbgResult = 0;\r
+ char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {'\0'};\r
+\r
+ if (NULL == g_serialHandle)\r
+ {\r
+ return 0;\r
+ }\r
+\r
+ va_start(ap, formatString);\r
+ /* format print log first */\r
+ logLength = StrFormatPrintf(formatString, ap, printBuf, DbgConsole_PrintCallback);\r
+\r
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)\r
+ SerialManager_CancelWriting(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]));\r
+#endif\r
+ /* print log */\r
+ status =\r
+ (status_t)SerialManager_WriteBlocking(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]),\r
+ (uint8_t *)printBuf, (size_t)logLength);\r
+ dbgResult = (((status_t)kStatus_Success == status) ? (int)logLength : -1);\r
+ va_end(ap);\r
+\r
+ return dbgResult;\r
+}\r
+\r
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING\r
+status_t DbgConsole_TryGetchar(char *ch)\r
+{\r
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))\r
+ uint32_t length = 0;\r
+ status_t status = (status_t)kStatus_Fail;\r
+\r
+ assert(ch);\r
+\r
+ if (NULL == g_serialHandle)\r
+ {\r
+ return kStatus_Fail;\r
+ }\r
+\r
+ /* take mutex lock function */\r
+ DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore);\r
+\r
+ if (kStatus_SerialManager_Success ==\r
+ SerialManager_TryRead(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), (uint8_t *)ch, 1,\r
+ &length))\r
+ {\r
+ if (length != 0U)\r
+ {\r
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION\r
+ (void)DbgConsole_EchoCharacter((uint8_t *)ch, true, NULL);\r
+#endif\r
+ status = (status_t)kStatus_Success;\r
+ }\r
+ }\r
+ /* release mutex lock function */\r
+ DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);\r
+ return status;\r
+#else\r
+ return (status_t)kStatus_Fail;\r
+#endif\r
+}\r
+#endif\r
+\r
+/* See fsl_debug_console.h for documentation of this function. */\r
+int DbgConsole_Getchar(void)\r
+{\r
+ uint8_t ch = 0U;\r
+\r
+ /* Get char */\r
+ (void)DbgConsole_ReadCharacter(&ch);\r
+\r
+ return (int)ch;\r
+}\r
+\r
+#endif /* SDK_DEBUGCONSOLE */\r
+\r
+/*************Code to support toolchain's printf, scanf *******************************/\r
+/* These function __write and __read is used to support IAR toolchain to printf and scanf*/\r
+#if (defined(__ICCARM__))\r
+#if defined(SDK_DEBUGCONSOLE_UART)\r
+#pragma weak __write\r
+size_t __write(int handle, const unsigned char *buffer, size_t size)\r
+{\r
+ if (buffer == 0)\r
+ {\r
+ /*\r
+ * This means that we should flush internal buffers. Since we don't we just return.\r
+ * (Remember, "handle" == -1 means that all handles should be flushed.)\r
+ */\r
+ return 0;\r
+ }\r
+\r
+ /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */\r
+ if ((handle != 1) && (handle != 2))\r
+ {\r
+ return ((size_t)-1);\r
+ }\r
+\r
+ /* Send data. */\r
+ DbgConsole_SendDataReliable((uint8_t *)buffer, size);\r
+\r
+ return size;\r
+}\r
+\r
+#pragma weak __read\r
+size_t __read(int handle, unsigned char *buffer, size_t size)\r
+{\r
+ uint8_t ch = 0U;\r
+ int actualSize = 0U;\r
+\r
+ /* This function only reads from "standard in", for all other file handles it returns failure. */\r
+ if (handle != 0)\r
+ {\r
+ return ((size_t)-1);\r
+ }\r
+\r
+ /* Receive data.*/\r
+ for (; size > 0; size--)\r
+ {\r
+ DbgConsole_ReadCharacter(&ch);\r
+ if (ch == 0)\r
+ {\r
+ break;\r
+ }\r
+\r
+ *buffer++ = ch;\r
+ actualSize++;\r
+ }\r
+\r
+ return actualSize;\r
+}\r
+#endif /* SDK_DEBUGCONSOLE_UART */\r
+\r
+/* support LPC Xpresso with RedLib */\r
+#elif (defined(__REDLIB__))\r
+\r
+#if (defined(SDK_DEBUGCONSOLE_UART))\r
+int __attribute__((weak)) __sys_write(int handle, char *buffer, int size)\r
+{\r
+ if (buffer == 0)\r
+ {\r
+ /* return -1 if error. */\r
+ return -1;\r
+ }\r
+\r
+ /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */\r
+ if ((handle != 1) && (handle != 2))\r
+ {\r
+ return -1;\r
+ }\r
+\r
+ /* Send data. */\r
+ DbgConsole_SendDataReliable((uint8_t *)buffer, size);\r
+\r
+ return 0;\r
+}\r
+\r
+int __attribute__((weak)) __sys_readc(void)\r
+{\r
+ char tmp;\r
+\r
+ /* Receive data. */\r
+ DbgConsole_ReadCharacter((uint8_t *)&tmp);\r
+\r
+ return tmp;\r
+}\r
+#endif\r
+\r
+/* These function fputc and fgetc is used to support KEIL toolchain to printf and scanf*/\r
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)\r
+#if defined(SDK_DEBUGCONSOLE_UART)\r
+#if defined(__CC_ARM)\r
+struct __FILE\r
+{\r
+ int handle;\r
+ /*\r
+ * Whatever you require here. If the only file you are using is standard output using printf() for debugging,\r
+ * no file handling is required.\r
+ */\r
+};\r
+#endif\r
+\r
+/* FILE is typedef in stdio.h. */\r
+#pragma weak __stdout\r
+#pragma weak __stdin\r
+FILE __stdout;\r
+FILE __stdin;\r
+\r
+#pragma weak fputc\r
+int fputc(int ch, FILE *f)\r
+{\r
+ /* Send data. */\r
+ return DbgConsole_SendDataReliable((uint8_t *)(&ch), 1);\r
+}\r
+\r
+#pragma weak fgetc\r
+int fgetc(FILE *f)\r
+{\r
+ char ch;\r
+\r
+ /* Receive data. */\r
+ DbgConsole_ReadCharacter((uint8_t *)&ch);\r
+\r
+ return ch;\r
+}\r
+\r
+/*\r
+ * Terminate the program, passing a return code back to the user.\r
+ * This function may not return.\r
+ */\r
+void _sys_exit(int returncode)\r
+{\r
+ while (1)\r
+ {\r
+ }\r
+}\r
+\r
+/*\r
+ * Writes a character to the output channel. This function is used\r
+ * for last-resort error message output.\r
+ */\r
+void _ttywrch(int ch)\r
+{\r
+ char ench = ch;\r
+ DbgConsole_SendDataReliable((uint8_t *)(&ench), 1);\r
+}\r
+\r
+char *_sys_command_string(char *cmd, int len)\r
+{\r
+ return (cmd);\r
+}\r
+#endif /* SDK_DEBUGCONSOLE_UART */\r
+\r
+/* These function __write and __read is used to support ARM_GCC, KDS, Atollic toolchains to printf and scanf*/\r
+#elif (defined(__GNUC__))\r
+\r
+#if ((defined(__GNUC__) && (!defined(__MCUXPRESSO)) && (defined(SDK_DEBUGCONSOLE_UART))) || \\r
+ (defined(__MCUXPRESSO) && (defined(SDK_DEBUGCONSOLE_UART))))\r
+int __attribute__((weak)) _write(int handle, char *buffer, int size);\r
+int __attribute__((weak)) _write(int handle, char *buffer, int size)\r
+{\r
+ if (buffer == NULL)\r
+ {\r
+ /* return -1 if error. */\r
+ return -1;\r
+ }\r
+\r
+ /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */\r
+ if ((handle != 1) && (handle != 2))\r
+ {\r
+ return -1;\r
+ }\r
+\r
+ /* Send data. */\r
+ (void)DbgConsole_SendDataReliable((uint8_t *)buffer, (size_t)size);\r
+\r
+ return size;\r
+}\r
+\r
+int __attribute__((weak)) _read(int handle, char *buffer, int size);\r
+int __attribute__((weak)) _read(int handle, char *buffer, int size)\r
+{\r
+ uint8_t ch = 0U;\r
+ int actualSize = 0;\r
+\r
+ /* This function only reads from "standard in", for all other file handles it returns failure. */\r
+ if (handle != 0)\r
+ {\r
+ return -1;\r
+ }\r
+\r
+ /* Receive data. */\r
+ for (; size > 0; size--)\r
+ {\r
+ if (DbgConsole_ReadCharacter(&ch) < 0)\r
+ {\r
+ break;\r
+ }\r
+\r
+ *buffer++ = (char)ch;\r
+ actualSize++;\r
+\r
+ if ((ch == 0U) || (ch == (uint8_t)'\n') || (ch == (uint8_t)'\r'))\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ return (actualSize > 0) ? actualSize : -1;\r
+}\r
+#endif\r
+\r
+#endif /* __ICCARM__ */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ *\r
+ * Debug console shall provide input and output functions to scan and print formatted data.\r
+ * o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier"\r
+ * - [flags] :'-', '+', '#', ' ', '0'\r
+ * - [width]: number (0,1...)\r
+ * - [.precision]: number (0,1...)\r
+ * - [length]: do not support\r
+ * - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n'\r
+ * o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier"\r
+ * - [*]: is supported.\r
+ * - [width]: number (0,1...)\r
+ * - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t')\r
+ * - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's'\r
+ */\r
+\r
+#ifndef _FSL_DEBUGCONSOLE_H_\r
+#define _FSL_DEBUGCONSOLE_H_\r
+\r
+#include "fsl_common.h"\r
+#include "serial_manager.h"\r
+\r
+/*!\r
+ * @addtogroup debugconsole\r
+ * @{\r
+ */\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+extern serial_handle_t g_serialHandle; /*!< serial manager handle */\r
+\r
+/*! @brief Definition select redirect toolchain printf, scanf to uart or not. */\r
+#define DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN 0U /*!< Select toolchain printf and scanf. */\r
+#define DEBUGCONSOLE_REDIRECT_TO_SDK 1U /*!< Select SDK version printf, scanf. */\r
+#define DEBUGCONSOLE_DISABLE 2U /*!< Disable debugconsole function. */\r
+\r
+/*! @brief Definition to select sdk or toolchain printf, scanf. The macro only support\r
+ * to be redefined in project setting.\r
+ */\r
+#ifndef SDK_DEBUGCONSOLE\r
+#define SDK_DEBUGCONSOLE 1U\r
+#endif\r
+\r
+#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE)\r
+#include <stdio.h>\r
+#endif\r
+\r
+/*! @brief Definition to select redirect toolchain printf, scanf to uart or not.\r
+ *\r
+ * if SDK_DEBUGCONSOLE defined to 0,it represents select toolchain printf, scanf.\r
+ * if SDK_DEBUGCONSOLE defined to 1,it represents select SDK version printf, scanf.\r
+ * if SDK_DEBUGCONSOLE defined to 2,it represents disable debugconsole function.\r
+ */\r
+#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE /* Disable debug console */\r
+#define PRINTF\r
+#define SCANF\r
+#define PUTCHAR\r
+#define GETCHAR\r
+#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK /* Select printf, scanf, putchar, getchar of SDK version. */\r
+#define PRINTF DbgConsole_Printf\r
+#define SCANF DbgConsole_Scanf\r
+#define PUTCHAR DbgConsole_Putchar\r
+#define GETCHAR DbgConsole_Getchar\r
+#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN /* Select printf, scanf, putchar, getchar of toolchain. \ \\r
+ */\r
+#define PRINTF printf\r
+#define SCANF scanf\r
+#define PUTCHAR putchar\r
+#define GETCHAR getchar\r
+#endif /* SDK_DEBUGCONSOLE */\r
+\r
+/*******************************************************************************\r
+ * Prototypes\r
+ ******************************************************************************/\r
+\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif /* __cplusplus */\r
+\r
+/*! @name Initialization*/\r
+/* @{ */\r
+\r
+#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART))\r
+/*!\r
+ * @brief Initializes the peripheral used for debug messages.\r
+ *\r
+ * Call this function to enable debug log messages to be output via the specified peripheral\r
+ * initialized by the serial manager module.\r
+ * After this function has returned, stdout and stdin are connected to the selected peripheral.\r
+ *\r
+ * @param instance The instance of the module.\r
+ * @param baudRate The desired baud rate in bits per second.\r
+ * @param device Low level device type for the debug console, can be one of the following.\r
+ * @arg kSerialPort_Uart,\r
+ * @arg kSerialPort_UsbCdc\r
+ * @arg kSerialPort_UsbCdcVirtual.\r
+ * @param clkSrcFreq Frequency of peripheral source clock.\r
+ *\r
+ * @return Indicates whether initialization was successful or not.\r
+ * @retval kStatus_Success Execution successfully\r
+ */\r
+status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq);\r
+\r
+/*!\r
+ * @brief De-initializes the peripheral used for debug messages.\r
+ *\r
+ * Call this function to disable debug log messages to be output via the specified peripheral\r
+ * initialized by the serial manager module.\r
+ *\r
+ * @return Indicates whether de-initialization was successful or not.\r
+ */\r
+status_t DbgConsole_Deinit(void);\r
+#else\r
+/*!\r
+ * Use an error to replace the DbgConsole_Init when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and\r
+ * SDK_DEBUGCONSOLE_UART is not defined.\r
+ */\r
+static inline status_t DbgConsole_Init(uint8_t instance,\r
+ uint32_t baudRate,\r
+ serial_port_type_t device,\r
+ uint32_t clkSrcFreq)\r
+{\r
+ (void)instance;\r
+ (void)baudRate;\r
+ (void)device;\r
+ (void)clkSrcFreq;\r
+ return (status_t)kStatus_Fail;\r
+}\r
+/*!\r
+ * Use an error to replace the DbgConsole_Deinit when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and\r
+ * SDK_DEBUGCONSOLE_UART is not defined.\r
+ */\r
+static inline status_t DbgConsole_Deinit(void)\r
+{\r
+ return (status_t)kStatus_Fail;\r
+}\r
+#endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */\r
+\r
+#if SDK_DEBUGCONSOLE\r
+/*!\r
+ * @brief Writes formatted output to the standard output stream.\r
+ *\r
+ * Call this function to write a formatted output to the standard output stream.\r
+ *\r
+ * @param formatString Format control string.\r
+ * @return Returns the number of characters printed or a negative value if an error occurs.\r
+ */\r
+int DbgConsole_Printf(const char *formatString, ...);\r
+\r
+/*!\r
+ * @brief Writes a character to stdout.\r
+ *\r
+ * Call this function to write a character to stdout.\r
+ *\r
+ * @param ch Character to be written.\r
+ * @return Returns the character written.\r
+ */\r
+int DbgConsole_Putchar(int ch);\r
+\r
+/*!\r
+ * @brief Reads formatted data from the standard input stream.\r
+ *\r
+ * Call this function to read formatted data from the standard input stream.\r
+ *\r
+ * @note Due the limitation in the BM OSA environment (CPU is blocked in the function,\r
+ * other tasks will not be scheduled), the function cannot be used when the\r
+ * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment.\r
+ * And an error is returned when the function called in this case. The suggestion\r
+ * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char.\r
+ *\r
+ * @param formatString Format control string.\r
+ * @return Returns the number of fields successfully converted and assigned.\r
+ */\r
+int DbgConsole_Scanf(char *formatString, ...);\r
+\r
+/*!\r
+ * @brief Reads a character from standard input.\r
+ *\r
+ * Call this function to read a character from standard input.\r
+ *\r
+ * @note Due the limitation in the BM OSA environment (CPU is blocked in the function,\r
+ * other tasks will not be scheduled), the function cannot be used when the\r
+ * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment.\r
+ * And an error is returned when the function called in this case. The suggestion\r
+ * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char.\r
+ *\r
+ * @return Returns the character read.\r
+ */\r
+int DbgConsole_Getchar(void);\r
+\r
+/*!\r
+ * @brief Writes formatted output to the standard output stream with the blocking mode.\r
+ *\r
+ * Call this function to write a formatted output to the standard output stream with the blocking mode.\r
+ * The function will send data with blocking mode no matter the DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set\r
+ * or not.\r
+ * The function could be used in system ISR mode with DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set.\r
+ *\r
+ * @param formatString Format control string.\r
+ * @return Returns the number of characters printed or a negative value if an error occurs.\r
+ */\r
+int DbgConsole_BlockingPrintf(const char *formatString, ...);\r
+\r
+/*!\r
+ * @brief Debug console flush.\r
+ *\r
+ * Call this function to wait the tx buffer empty.\r
+ * If interrupt transfer is using, make sure the global IRQ is enable before call this function\r
+ * This function should be called when\r
+ * 1, before enter power down mode\r
+ * 2, log is required to print to terminal immediately\r
+ * @return Indicates whether wait idle was successful or not.\r
+ */\r
+status_t DbgConsole_Flush(void);\r
+\r
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING\r
+/*!\r
+ * @brief Debug console try to get char\r
+ * This function provides a API which will not block current task, if character is\r
+ * available return it, otherwise return fail.\r
+ * @param ch the address of char to receive\r
+ * @return Indicates get char was successful or not.\r
+ */\r
+status_t DbgConsole_TryGetchar(char *ch);\r
+#endif\r
+\r
+#endif /* SDK_DEBUGCONSOLE */\r
+\r
+/*! @} */\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif /* __cplusplus */\r
+\r
+/*! @} */\r
+\r
+#endif /* _FSL_DEBUGCONSOLE_H_ */\r
--- /dev/null
+/*\r
+ * Copyright 2017 - 2019 NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+#ifndef _FSL_DEBUG_CONSOLE_CONF_H_\r
+#define _FSL_DEBUG_CONSOLE_CONF_H_\r
+\r
+/****************Debug console configuration********************/\r
+\r
+/*! @brief If Non-blocking mode is needed, please define it at project setting,\r
+ * otherwise blocking mode is the default transfer mode.\r
+ * Warning: If you want to use non-blocking transfer,please make sure the corresponding\r
+ * IO interrupt is enable, otherwise there is no output.\r
+ * And non-blocking is combine with buffer, no matter bare-metal or rtos.\r
+ * Below shows how to configure in your project if you want to use non-blocking mode.\r
+ * For IAR, right click project and select "Options", define it in "C/C++ Compiler->Preprocessor->Defined symbols".\r
+ * For KEIL, click "Options for Target…", define it in "C/C++->Preprocessor Symbols->Define".\r
+ * For ARMGCC, open CmakeLists.txt and add the following lines,\r
+ * "SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for debug target.\r
+ * "SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for release target.\r
+ * For MCUxpresso, right click project and select "Properties", define it in "C/C++ Build->Settings->MCU C\r
+ * Complier->Preprocessor".\r
+ *\r
+ */\r
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING\r
+/*! @brief define the transmit buffer length which is used to store the multi task log, buffer is enabled automatically\r
+ * when\r
+ * non-blocking transfer is using,\r
+ * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.\r
+ * If it is configured too small, log maybe missed , because the log will not be\r
+ * buffered if the buffer is full, and the print will return immediately with -1.\r
+ * And this value should be multiple of 4 to meet memory alignment.\r
+ *\r
+ */\r
+#ifndef DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN\r
+#define DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN (512U)\r
+#endif /* DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN */\r
+\r
+/*! @brief define the receive buffer length which is used to store the user input, buffer is enabled automatically when\r
+ * non-blocking transfer is using,\r
+ * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.\r
+ * If it is configured too small, log maybe missed, because buffer will be overwrited if buffer is too small.\r
+ * And this value should be multiple of 4 to meet memory alignment.\r
+ *\r
+ */\r
+#ifndef DEBUG_CONSOLE_RECEIVE_BUFFER_LEN\r
+#define DEBUG_CONSOLE_RECEIVE_BUFFER_LEN (1024U)\r
+#endif /* DEBUG_CONSOLE_RECEIVE_BUFFER_LEN */\r
+\r
+/*!@ brief Whether enable the reliable TX function\r
+ * If the macro is zero, the reliable TX function of the debug console is disabled.\r
+ * When the macro is zero, the string of PRINTF will be thrown away after the transmit buffer is full.\r
+ */\r
+#ifndef DEBUG_CONSOLE_TX_RELIABLE_ENABLE\r
+#define DEBUG_CONSOLE_TX_RELIABLE_ENABLE (1U)\r
+#endif /* DEBUG_CONSOLE_RX_ENABLE */\r
+\r
+#else\r
+#define DEBUG_CONSOLE_TRANSFER_BLOCKING\r
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */\r
+\r
+/*!@ brief Whether enable the RX function\r
+ * If the macro is zero, the receive function of the debug console is disabled.\r
+ */\r
+#ifndef DEBUG_CONSOLE_RX_ENABLE\r
+#define DEBUG_CONSOLE_RX_ENABLE (1U)\r
+#endif /* DEBUG_CONSOLE_RX_ENABLE */\r
+\r
+/*!@ brief define the MAX log length debug console support , that is when you call printf("log", x);, the log\r
+ * length can not bigger than this value.\r
+ * This macro decide the local log buffer length, the buffer locate at stack, the stack maybe overflow if\r
+ * the buffer is too big and current task stack size not big enough.\r
+ */\r
+#ifndef DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN\r
+#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN (128U)\r
+#endif /* DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN */\r
+\r
+/*!@ brief define the buffer support buffer scanf log length, that is when you call scanf("log", &x);, the log\r
+ * length can not bigger than this value.\r
+ * As same as the DEBUG_CONSOLE_BUFFER_PRINTF_MAX_LOG_LEN.\r
+ */\r
+#ifndef DEBUG_CONSOLE_SCANF_MAX_LOG_LEN\r
+#define DEBUG_CONSOLE_SCANF_MAX_LOG_LEN (20U)\r
+#endif /* DEBUG_CONSOLE_SCANF_MAX_LOG_LEN */\r
+\r
+/*! @brief Debug console synchronization\r
+ * User should not change these macro for synchronization mode, but add the\r
+ * corresponding synchronization mechanism per different software environment.\r
+ * Such as, if another RTOS is used,\r
+ * add:\r
+ * #define DEBUG_CONSOLE_SYNCHRONIZATION_XXXX 3\r
+ * in this configuration file and implement the synchronization in fsl.log.c.\r
+ */\r
+/*! @brief synchronization for baremetal software */\r
+#define DEBUG_CONSOLE_SYNCHRONIZATION_BM 0\r
+/*! @brief synchronization for freertos software */\r
+#define DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS 1\r
+\r
+/*! @brief RTOS synchronization mechanism disable\r
+ * If not defined, default is enable, to avoid multitask log print mess.\r
+ * If other RTOS is used, you can implement the RTOS's specific synchronization mechanism in fsl.log.c\r
+ * If synchronization is disabled, log maybe messed on terminal.\r
+ */\r
+#ifndef DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION\r
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING\r
+#ifdef FSL_RTOS_FREE_RTOS\r
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS\r
+#else\r
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM\r
+#endif /* FSL_RTOS_FREE_RTOS */\r
+#else\r
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM\r
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */\r
+#endif /* DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION */\r
+\r
+/*! @brief echo function support\r
+ * If you want to use the echo function,please define DEBUG_CONSOLE_ENABLE_ECHO\r
+ * at your project setting.\r
+ */\r
+#ifndef DEBUG_CONSOLE_ENABLE_ECHO\r
+#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 0\r
+#else\r
+#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 1\r
+#endif /* DEBUG_CONSOLE_ENABLE_ECHO */\r
+\r
+/*********************************************************************/\r
+\r
+/***************Debug console other configuration*********************/\r
+/*! @brief Definition to printf the float number. */\r
+#ifndef PRINTF_FLOAT_ENABLE\r
+#define PRINTF_FLOAT_ENABLE 0U\r
+#endif /* PRINTF_FLOAT_ENABLE */\r
+\r
+/*! @brief Definition to scanf the float number. */\r
+#ifndef SCANF_FLOAT_ENABLE\r
+#define SCANF_FLOAT_ENABLE 0U\r
+#endif /* SCANF_FLOAT_ENABLE */\r
+\r
+/*! @brief Definition to support advanced format specifier for printf. */\r
+#ifndef PRINTF_ADVANCED_ENABLE\r
+#define PRINTF_ADVANCED_ENABLE 0U\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+\r
+/*! @brief Definition to support advanced format specifier for scanf. */\r
+#ifndef SCANF_ADVANCED_ENABLE\r
+#define SCANF_ADVANCED_ENABLE 0U\r
+#endif /* SCANF_ADVANCED_ENABLE */\r
+\r
+/*! @brief Definition to select virtual com(USB CDC) as the debug console. */\r
+#ifndef BOARD_USE_VIRTUALCOM\r
+#define BOARD_USE_VIRTUALCOM 0U\r
+#endif\r
+/*******************************************************************/\r
+\r
+#endif /* _FSL_DEBUG_CONSOLE_CONF_H_ */\r
--- /dev/null
+/*\r
+ * Copyright 2017 NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ *\r
+ */\r
+#include <math.h>\r
+#include <stdarg.h>\r
+#include <stdlib.h>\r
+#include "fsl_str.h"\r
+#include "fsl_debug_console_conf.h"\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/*! @brief The overflow value.*/\r
+#ifndef HUGE_VAL\r
+#define HUGE_VAL (99.e99)\r
+#endif /* HUGE_VAL */\r
+\r
+#if PRINTF_ADVANCED_ENABLE\r
+/*! @brief Specification modifier flags for printf. */\r
+enum _debugconsole_printf_flag\r
+{\r
+ kPRINTF_Minus = 0x01U, /*!< Minus FLag. */\r
+ kPRINTF_Plus = 0x02U, /*!< Plus Flag. */\r
+ kPRINTF_Space = 0x04U, /*!< Space Flag. */\r
+ kPRINTF_Zero = 0x08U, /*!< Zero Flag. */\r
+ kPRINTF_Pound = 0x10U, /*!< Pound Flag. */\r
+ kPRINTF_LengthChar = 0x20U, /*!< Length: Char Flag. */\r
+ kPRINTF_LengthShortInt = 0x40U, /*!< Length: Short Int Flag. */\r
+ kPRINTF_LengthLongInt = 0x80U, /*!< Length: Long Int Flag. */\r
+ kPRINTF_LengthLongLongInt = 0x100U, /*!< Length: Long Long Int Flag. */\r
+};\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+\r
+/*! @brief Specification modifier flags for scanf. */\r
+enum _debugconsole_scanf_flag\r
+{\r
+ kSCANF_Suppress = 0x2U, /*!< Suppress Flag. */\r
+ kSCANF_DestMask = 0x7cU, /*!< Destination Mask. */\r
+ kSCANF_DestChar = 0x4U, /*!< Destination Char Flag. */\r
+ kSCANF_DestString = 0x8U, /*!< Destination String FLag. */\r
+ kSCANF_DestSet = 0x10U, /*!< Destination Set Flag. */\r
+ kSCANF_DestInt = 0x20U, /*!< Destination Int Flag. */\r
+ kSCANF_DestFloat = 0x30U, /*!< Destination Float Flag. */\r
+ kSCANF_LengthMask = 0x1f00U, /*!< Length Mask Flag. */\r
+#if SCANF_ADVANCED_ENABLE\r
+ kSCANF_LengthChar = 0x100U, /*!< Length Char Flag. */\r
+ kSCANF_LengthShortInt = 0x200U, /*!< Length ShortInt Flag. */\r
+ kSCANF_LengthLongInt = 0x400U, /*!< Length LongInt Flag. */\r
+ kSCANF_LengthLongLongInt = 0x800U, /*!< Length LongLongInt Flag. */\r
+#endif /* SCANF_ADVANCED_ENABLE */\r
+#if SCANF_FLOAT_ENABLE\r
+ kSCANF_LengthLongLongDouble = 0x1000U, /*!< Length LongLongDuoble Flag. */\r
+#endif /*PRINTF_FLOAT_ENABLE */\r
+ kSCANF_TypeSinged = 0x2000U, /*!< TypeSinged Flag. */\r
+};\r
+\r
+/*! @brief Keil: suppress ellipsis warning in va_arg usage below. */\r
+#if defined(__CC_ARM)\r
+#pragma diag_suppress 1256\r
+#endif /* __CC_ARM */\r
+\r
+/*******************************************************************************\r
+ * Prototypes\r
+ ******************************************************************************/\r
+/*!\r
+ * @brief Scanline function which ignores white spaces.\r
+ *\r
+ * @param[in] s The address of the string pointer to update.\r
+ * @return String without white spaces.\r
+ */\r
+static uint32_t ScanIgnoreWhiteSpace(const char **s);\r
+\r
+/*!\r
+ * @brief Converts a radix number to a string and return its length.\r
+ *\r
+ * @param[in] numstr Converted string of the number.\r
+ * @param[in] nump Pointer to the number.\r
+ * @param[in] neg Polarity of the number.\r
+ * @param[in] radix The radix to be converted to.\r
+ * @param[in] use_caps Used to identify %x/X output format.\r
+\r
+ * @return Length of the converted string.\r
+ */\r
+static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps);\r
+\r
+#if PRINTF_FLOAT_ENABLE\r
+/*!\r
+ * @brief Converts a floating radix number to a string and return its length.\r
+ *\r
+ * @param[in] numstr Converted string of the number.\r
+ * @param[in] nump Pointer to the number.\r
+ * @param[in] radix The radix to be converted to.\r
+ * @param[in] precision_width Specify the precision width.\r
+\r
+ * @return Length of the converted string.\r
+ */\r
+static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width);\r
+#endif /* PRINTF_FLOAT_ENABLE */\r
+\r
+/*!\r
+ *\r
+ */\r
+double modf(double input_dbl, double *intpart_ptr);\r
+\r
+/*************Code for process formatted data*******************************/\r
+\r
+static uint32_t ScanIgnoreWhiteSpace(const char **s)\r
+{\r
+ uint8_t count = 0;\r
+ uint8_t c;\r
+\r
+ c = **s;\r
+ while ((c == ' ') || (c == '\t') || (c == '\n') || (c == '\r') || (c == '\v') || (c == '\f'))\r
+ {\r
+ count++;\r
+ (*s)++;\r
+ c = **s;\r
+ }\r
+ return count;\r
+}\r
+\r
+static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps)\r
+{\r
+#if PRINTF_ADVANCED_ENABLE\r
+ int64_t a;\r
+ int64_t b;\r
+ int64_t c;\r
+\r
+ uint64_t ua;\r
+ uint64_t ub;\r
+ uint64_t uc;\r
+#else\r
+ int32_t a;\r
+ int32_t b;\r
+ int32_t c;\r
+\r
+ uint32_t ua;\r
+ uint32_t ub;\r
+ uint32_t uc;\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+\r
+ int32_t nlen;\r
+ char *nstrp;\r
+\r
+ nlen = 0;\r
+ nstrp = numstr;\r
+ *nstrp++ = '\0';\r
+\r
+ if (neg)\r
+ {\r
+#if PRINTF_ADVANCED_ENABLE\r
+ a = *(int64_t *)nump;\r
+#else\r
+ a = *(int32_t *)nump;\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ if (a == 0)\r
+ {\r
+ *nstrp = '0';\r
+ ++nlen;\r
+ return nlen;\r
+ }\r
+ while (a != 0)\r
+ {\r
+#if PRINTF_ADVANCED_ENABLE\r
+ b = (int64_t)a / (int64_t)radix;\r
+ c = (int64_t)a - ((int64_t)b * (int64_t)radix);\r
+ if (c < 0)\r
+ {\r
+ uc = (uint64_t)c;\r
+ c = (int64_t)(~uc) + 1 + '0';\r
+ }\r
+#else\r
+ b = a / radix;\r
+ c = a - (b * radix);\r
+ if (c < 0)\r
+ {\r
+ uc = (uint32_t)c;\r
+ c = (uint32_t)(~uc) + 1 + '0';\r
+ }\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ else\r
+ {\r
+ c = c + '0';\r
+ }\r
+ a = b;\r
+ *nstrp++ = (char)c;\r
+ ++nlen;\r
+ }\r
+ }\r
+ else\r
+ {\r
+#if PRINTF_ADVANCED_ENABLE\r
+ ua = *(uint64_t *)nump;\r
+#else\r
+ ua = *(uint32_t *)nump;\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ if (ua == 0)\r
+ {\r
+ *nstrp = '0';\r
+ ++nlen;\r
+ return nlen;\r
+ }\r
+ while (ua != 0)\r
+ {\r
+#if PRINTF_ADVANCED_ENABLE\r
+ ub = (uint64_t)ua / (uint64_t)radix;\r
+ uc = (uint64_t)ua - ((uint64_t)ub * (uint64_t)radix);\r
+#else\r
+ ub = ua / (uint32_t)radix;\r
+ uc = ua - (ub * (uint32_t)radix);\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+\r
+ if (uc < 10)\r
+ {\r
+ uc = uc + '0';\r
+ }\r
+ else\r
+ {\r
+ uc = uc - 10 + (use_caps ? 'A' : 'a');\r
+ }\r
+ ua = ub;\r
+ *nstrp++ = (char)uc;\r
+ ++nlen;\r
+ }\r
+ }\r
+ return nlen;\r
+}\r
+\r
+#if PRINTF_FLOAT_ENABLE\r
+static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width)\r
+{\r
+ int32_t a;\r
+ int32_t b;\r
+ int32_t c;\r
+ int32_t i;\r
+ uint32_t uc;\r
+ double fa;\r
+ double dc;\r
+ double fb;\r
+ double r;\r
+ double fractpart;\r
+ double intpart;\r
+\r
+ int32_t nlen;\r
+ char *nstrp;\r
+ nlen = 0;\r
+ nstrp = numstr;\r
+ *nstrp++ = '\0';\r
+ r = *(double *)nump;\r
+ if (!r)\r
+ {\r
+ *nstrp = '0';\r
+ ++nlen;\r
+ return nlen;\r
+ }\r
+ fractpart = modf((double)r, (double *)&intpart);\r
+ /* Process fractional part. */\r
+ for (i = 0; i < precision_width; i++)\r
+ {\r
+ fractpart *= radix;\r
+ }\r
+ if (r >= 0)\r
+ {\r
+ fa = fractpart + (double)0.5;\r
+ if (fa >= pow(10, precision_width))\r
+ {\r
+ intpart++;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ fa = fractpart - (double)0.5;\r
+ if (fa <= -pow(10, precision_width))\r
+ {\r
+ intpart--;\r
+ }\r
+ }\r
+ for (i = 0; i < precision_width; i++)\r
+ {\r
+ fb = fa / (int32_t)radix;\r
+ dc = (fa - (int64_t)fb * (int32_t)radix);\r
+ c = (int32_t)dc;\r
+ if (c < 0)\r
+ {\r
+ uc = (uint32_t)c;\r
+ c = (int32_t)(~uc) + 1 + '0';\r
+ }\r
+ else\r
+ {\r
+ c = c + '0';\r
+ }\r
+ fa = fb;\r
+ *nstrp++ = (char)c;\r
+ ++nlen;\r
+ }\r
+ *nstrp++ = (char)'.';\r
+ ++nlen;\r
+ a = (int32_t)intpart;\r
+ if (a == 0)\r
+ {\r
+ *nstrp++ = '0';\r
+ ++nlen;\r
+ }\r
+ else\r
+ {\r
+ while (a != 0)\r
+ {\r
+ b = (int32_t)a / (int32_t)radix;\r
+ c = (int32_t)a - ((int32_t)b * (int32_t)radix);\r
+ if (c < 0)\r
+ {\r
+ uc = (uint32_t)c;\r
+ c = (int32_t)(~uc) + 1 + '0';\r
+ }\r
+ else\r
+ {\r
+ c = c + '0';\r
+ }\r
+ a = b;\r
+ *nstrp++ = (char)c;\r
+ ++nlen;\r
+ }\r
+ }\r
+ return nlen;\r
+}\r
+#endif /* PRINTF_FLOAT_ENABLE */\r
+\r
+/*!\r
+ * brief This function outputs its parameters according to a formatted string.\r
+ *\r
+ * note I/O is performed by calling given function pointer using following\r
+ * (*func_ptr)(c);\r
+ *\r
+ * param[in] fmt_ptr Format string for printf.\r
+ * param[in] args_ptr Arguments to printf.\r
+ * param[in] buf pointer to the buffer\r
+ * param cb print callback function pointer\r
+ *\r
+ * return Number of characters to be print\r
+ */\r
+int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb)\r
+{\r
+ /* va_list ap; */\r
+ char *p;\r
+ int32_t c;\r
+\r
+ char vstr[33];\r
+ char *vstrp = NULL;\r
+ int32_t vlen = 0;\r
+\r
+ int32_t done;\r
+ int32_t count = 0;\r
+\r
+ uint32_t field_width;\r
+ uint32_t precision_width;\r
+ char *sval;\r
+ int32_t cval;\r
+ bool use_caps;\r
+ uint8_t radix = 0;\r
+\r
+#if PRINTF_ADVANCED_ENABLE\r
+ uint32_t flags_used;\r
+ int32_t schar, dschar;\r
+ int64_t ival;\r
+ uint64_t uval = 0;\r
+ bool valid_precision_width;\r
+#else\r
+ int32_t ival;\r
+ uint32_t uval = 0;\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+\r
+#if PRINTF_FLOAT_ENABLE\r
+ double fval;\r
+#endif /* PRINTF_FLOAT_ENABLE */\r
+\r
+ /* Start parsing apart the format string and display appropriate formats and data. */\r
+ for (p = (char *)fmt; (c = *p) != 0; p++)\r
+ {\r
+ /*\r
+ * All formats begin with a '%' marker. Special chars like\r
+ * '\n' or '\t' are normally converted to the appropriate\r
+ * character by the __compiler__. Thus, no need for this\r
+ * routine to account for the '\' character.\r
+ */\r
+ if (c != '%')\r
+ {\r
+ cb(buf, &count, c, 1);\r
+ /* By using 'continue', the next iteration of the loop is used, skipping the code that follows. */\r
+ continue;\r
+ }\r
+\r
+ use_caps = true;\r
+\r
+#if PRINTF_ADVANCED_ENABLE\r
+ /* First check for specification modifier flags. */\r
+ flags_used = 0;\r
+ done = false;\r
+ while (!done)\r
+ {\r
+ switch (*++p)\r
+ {\r
+ case '-':\r
+ flags_used |= kPRINTF_Minus;\r
+ break;\r
+ case '+':\r
+ flags_used |= kPRINTF_Plus;\r
+ break;\r
+ case ' ':\r
+ flags_used |= kPRINTF_Space;\r
+ break;\r
+ case '0':\r
+ flags_used |= kPRINTF_Zero;\r
+ break;\r
+ case '#':\r
+ flags_used |= kPRINTF_Pound;\r
+ break;\r
+ default:\r
+ /* We've gone one char too far. */\r
+ --p;\r
+ done = true;\r
+ break;\r
+ }\r
+ }\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+\r
+ /* Next check for minimum field width. */\r
+ field_width = 0;\r
+ done = false;\r
+ while (!done)\r
+ {\r
+ c = *++p;\r
+ if ((c >= '0') && (c <= '9'))\r
+ {\r
+ field_width = (field_width * 10) + (c - '0');\r
+ }\r
+#if PRINTF_ADVANCED_ENABLE\r
+ else if (c == '*')\r
+ {\r
+ field_width = (uint32_t)va_arg(ap, uint32_t);\r
+ }\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ else\r
+ {\r
+ /* We've gone one char too far. */\r
+ --p;\r
+ done = true;\r
+ }\r
+ }\r
+ /* Next check for the width and precision field separator. */\r
+ precision_width = 6;\r
+#if PRINTF_ADVANCED_ENABLE\r
+ valid_precision_width = false;\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ if (*++p == '.')\r
+ {\r
+ /* Must get precision field width, if present. */\r
+ precision_width = 0;\r
+ done = false;\r
+ while (!done)\r
+ {\r
+ c = *++p;\r
+ if ((c >= '0') && (c <= '9'))\r
+ {\r
+ precision_width = (precision_width * 10) + (c - '0');\r
+#if PRINTF_ADVANCED_ENABLE\r
+ valid_precision_width = true;\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ }\r
+#if PRINTF_ADVANCED_ENABLE\r
+ else if (c == '*')\r
+ {\r
+ precision_width = (uint32_t)va_arg(ap, uint32_t);\r
+ valid_precision_width = true;\r
+ }\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ else\r
+ {\r
+ /* We've gone one char too far. */\r
+ --p;\r
+ done = true;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* We've gone one char too far. */\r
+ --p;\r
+ }\r
+#if PRINTF_ADVANCED_ENABLE\r
+ /*\r
+ * Check for the length modifier.\r
+ */\r
+ switch (/* c = */ *++p)\r
+ {\r
+ case 'h':\r
+ if (*++p != 'h')\r
+ {\r
+ flags_used |= kPRINTF_LengthShortInt;\r
+ --p;\r
+ }\r
+ else\r
+ {\r
+ flags_used |= kPRINTF_LengthChar;\r
+ }\r
+ break;\r
+ case 'l':\r
+ if (*++p != 'l')\r
+ {\r
+ flags_used |= kPRINTF_LengthLongInt;\r
+ --p;\r
+ }\r
+ else\r
+ {\r
+ flags_used |= kPRINTF_LengthLongLongInt;\r
+ }\r
+ break;\r
+ default:\r
+ /* we've gone one char too far */\r
+ --p;\r
+ break;\r
+ }\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ /* Now we're ready to examine the format. */\r
+ c = *++p;\r
+ {\r
+ if ((c == 'd') || (c == 'i') || (c == 'f') || (c == 'F') || (c == 'x') || (c == 'X') || (c == 'o') ||\r
+ (c == 'b') || (c == 'p') || (c == 'u'))\r
+ {\r
+ if ((c == 'd') || (c == 'i'))\r
+ {\r
+#if PRINTF_ADVANCED_ENABLE\r
+ if (flags_used & kPRINTF_LengthLongLongInt)\r
+ {\r
+ ival = (int64_t)va_arg(ap, int64_t);\r
+ }\r
+ else\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ {\r
+ ival = (int32_t)va_arg(ap, int32_t);\r
+ }\r
+ vlen = ConvertRadixNumToString(vstr, &ival, true, 10, use_caps);\r
+ vstrp = &vstr[vlen];\r
+#if PRINTF_ADVANCED_ENABLE\r
+ if (ival < 0)\r
+ {\r
+ schar = '-';\r
+ ++vlen;\r
+ }\r
+ else\r
+ {\r
+ if (flags_used & kPRINTF_Plus)\r
+ {\r
+ schar = '+';\r
+ ++vlen;\r
+ }\r
+ else\r
+ {\r
+ if (flags_used & kPRINTF_Space)\r
+ {\r
+ schar = ' ';\r
+ ++vlen;\r
+ }\r
+ else\r
+ {\r
+ schar = 0;\r
+ }\r
+ }\r
+ }\r
+ dschar = false;\r
+ /* Do the ZERO pad. */\r
+ if (flags_used & kPRINTF_Zero)\r
+ {\r
+ if (schar)\r
+ {\r
+ cb(buf, &count, schar, 1);\r
+ }\r
+ dschar = true;\r
+\r
+ cb(buf, &count, '0', field_width - vlen);\r
+ vlen = field_width;\r
+ }\r
+ else\r
+ {\r
+ if (!(flags_used & kPRINTF_Minus))\r
+ {\r
+ cb(buf, &count, ' ', field_width - vlen);\r
+ if (schar)\r
+ {\r
+ cb(buf, &count, schar, 1);\r
+ }\r
+ dschar = true;\r
+ }\r
+ }\r
+ /* The string was built in reverse order, now display in correct order. */\r
+ if ((!dschar) && schar)\r
+ {\r
+ cb(buf, &count, schar, 1);\r
+ }\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ }\r
+\r
+#if PRINTF_FLOAT_ENABLE\r
+ if ((c == 'f') || (c == 'F'))\r
+ {\r
+ fval = (double)va_arg(ap, double);\r
+ vlen = ConvertFloatRadixNumToString(vstr, &fval, 10, precision_width);\r
+ vstrp = &vstr[vlen];\r
+\r
+#if PRINTF_ADVANCED_ENABLE\r
+ if (fval < 0)\r
+ {\r
+ schar = '-';\r
+ ++vlen;\r
+ }\r
+ else\r
+ {\r
+ if (flags_used & kPRINTF_Plus)\r
+ {\r
+ schar = '+';\r
+ ++vlen;\r
+ }\r
+ else\r
+ {\r
+ if (flags_used & kPRINTF_Space)\r
+ {\r
+ schar = ' ';\r
+ ++vlen;\r
+ }\r
+ else\r
+ {\r
+ schar = 0;\r
+ }\r
+ }\r
+ }\r
+ dschar = false;\r
+ if (flags_used & kPRINTF_Zero)\r
+ {\r
+ if (schar)\r
+ {\r
+ cb(buf, &count, schar, 1);\r
+ }\r
+ dschar = true;\r
+ cb(buf, &count, '0', field_width - vlen);\r
+ vlen = field_width;\r
+ }\r
+ else\r
+ {\r
+ if (!(flags_used & kPRINTF_Minus))\r
+ {\r
+ cb(buf, &count, ' ', field_width - vlen);\r
+ if (schar)\r
+ {\r
+ cb(buf, &count, schar, 1);\r
+ }\r
+ dschar = true;\r
+ }\r
+ }\r
+ if ((!dschar) && schar)\r
+ {\r
+ cb(buf, &count, schar, 1);\r
+ }\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ }\r
+#endif /* PRINTF_FLOAT_ENABLE */\r
+ if ((c == 'X') || (c == 'x'))\r
+ {\r
+ if (c == 'x')\r
+ {\r
+ use_caps = false;\r
+ }\r
+#if PRINTF_ADVANCED_ENABLE\r
+ if (flags_used & kPRINTF_LengthLongLongInt)\r
+ {\r
+ uval = (uint64_t)va_arg(ap, uint64_t);\r
+ }\r
+ else\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ {\r
+ uval = (uint32_t)va_arg(ap, uint32_t);\r
+ }\r
+ vlen = ConvertRadixNumToString(vstr, &uval, false, 16, use_caps);\r
+ vstrp = &vstr[vlen];\r
+\r
+#if PRINTF_ADVANCED_ENABLE\r
+ dschar = false;\r
+ if (flags_used & kPRINTF_Zero)\r
+ {\r
+ if (flags_used & kPRINTF_Pound)\r
+ {\r
+ cb(buf, &count, '0', 1);\r
+ cb(buf, &count, (use_caps ? 'X' : 'x'), 1);\r
+ dschar = true;\r
+ }\r
+ cb(buf, &count, '0', field_width - vlen);\r
+ vlen = field_width;\r
+ }\r
+ else\r
+ {\r
+ if (!(flags_used & kPRINTF_Minus))\r
+ {\r
+ if (flags_used & kPRINTF_Pound)\r
+ {\r
+ vlen += 2;\r
+ }\r
+ cb(buf, &count, ' ', field_width - vlen);\r
+ if (flags_used & kPRINTF_Pound)\r
+ {\r
+ cb(buf, &count, '0', 1);\r
+ cb(buf, &count, (use_caps ? 'X' : 'x'), 1);\r
+ dschar = true;\r
+ }\r
+ }\r
+ }\r
+\r
+ if ((flags_used & kPRINTF_Pound) && (!dschar))\r
+ {\r
+ cb(buf, &count, '0', 1);\r
+ cb(buf, &count, (use_caps ? 'X' : 'x'), 1);\r
+ vlen += 2;\r
+ }\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ }\r
+ if ((c == 'o') || (c == 'b') || (c == 'p') || (c == 'u'))\r
+ {\r
+#if PRINTF_ADVANCED_ENABLE\r
+ if (flags_used & kPRINTF_LengthLongLongInt)\r
+ {\r
+ uval = (uint64_t)va_arg(ap, uint64_t);\r
+ }\r
+ else\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ {\r
+ uval = (uint32_t)va_arg(ap, uint32_t);\r
+ }\r
+\r
+ if (c == 'o')\r
+ {\r
+ radix = 8;\r
+ }\r
+ else if (c == 'b')\r
+ {\r
+ radix = 2;\r
+ }\r
+ else if (c == 'p')\r
+ {\r
+ radix = 16;\r
+ }\r
+ else\r
+ {\r
+ radix = 10;\r
+ }\r
+\r
+ vlen = ConvertRadixNumToString(vstr, &uval, false, radix, use_caps);\r
+ vstrp = &vstr[vlen];\r
+#if PRINTF_ADVANCED_ENABLE\r
+ if (flags_used & kPRINTF_Zero)\r
+ {\r
+ cb(buf, &count, '0', field_width - vlen);\r
+ vlen = field_width;\r
+ }\r
+ else\r
+ {\r
+ if (!(flags_used & kPRINTF_Minus))\r
+ {\r
+ cb(buf, &count, ' ', field_width - vlen);\r
+ }\r
+ }\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ }\r
+#if !PRINTF_ADVANCED_ENABLE\r
+ cb(buf, &count, ' ', field_width - vlen);\r
+#endif /* !PRINTF_ADVANCED_ENABLE */\r
+ if (vstrp != NULL)\r
+ {\r
+ while (*vstrp)\r
+ {\r
+ cb(buf, &count, *vstrp--, 1);\r
+ }\r
+ }\r
+#if PRINTF_ADVANCED_ENABLE\r
+ if (flags_used & kPRINTF_Minus)\r
+ {\r
+ cb(buf, &count, ' ', field_width - vlen);\r
+ }\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ }\r
+ else if (c == 'c')\r
+ {\r
+ cval = (char)va_arg(ap, uint32_t);\r
+ cb(buf, &count, cval, 1);\r
+ }\r
+ else if (c == 's')\r
+ {\r
+ sval = (char *)va_arg(ap, char *);\r
+ if (sval)\r
+ {\r
+#if PRINTF_ADVANCED_ENABLE\r
+ if (valid_precision_width)\r
+ {\r
+ vlen = precision_width;\r
+ }\r
+ else\r
+ {\r
+ vlen = strlen(sval);\r
+ }\r
+#else\r
+ vlen = strlen(sval);\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+#if PRINTF_ADVANCED_ENABLE\r
+ if (!(flags_used & kPRINTF_Minus))\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ {\r
+ cb(buf, &count, ' ', field_width - vlen);\r
+ }\r
+\r
+#if PRINTF_ADVANCED_ENABLE\r
+ if (valid_precision_width)\r
+ {\r
+ while ((*sval) && (vlen > 0))\r
+ {\r
+ cb(buf, &count, *sval++, 1);\r
+ vlen--;\r
+ }\r
+ /* In case that vlen sval is shorter than vlen */\r
+ vlen = precision_width - vlen;\r
+ }\r
+ else\r
+ {\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ while (*sval)\r
+ {\r
+ cb(buf, &count, *sval++, 1);\r
+ }\r
+#if PRINTF_ADVANCED_ENABLE\r
+ }\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+\r
+#if PRINTF_ADVANCED_ENABLE\r
+ if (flags_used & kPRINTF_Minus)\r
+ {\r
+ cb(buf, &count, ' ', field_width - vlen);\r
+ }\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ }\r
+ }\r
+ else\r
+ {\r
+ cb(buf, &count, c, 1);\r
+ }\r
+ }\r
+ }\r
+\r
+ return count;\r
+}\r
+\r
+/*!\r
+ * brief Converts an input line of ASCII characters based upon a provided\r
+ * string format.\r
+ *\r
+ * param[in] line_ptr The input line of ASCII data.\r
+ * param[in] format Format first points to the format string.\r
+ * param[in] args_ptr The list of parameters.\r
+ *\r
+ * return Number of input items converted and assigned.\r
+ * retval IO_EOF When line_ptr is empty string "".\r
+ */\r
+int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr)\r
+{\r
+ uint8_t base;\r
+ int8_t neg;\r
+ /* Identifier for the format string. */\r
+ char *c = format;\r
+ char temp;\r
+ char *buf;\r
+ /* Flag telling the conversion specification. */\r
+ uint32_t flag = 0;\r
+ /* Filed width for the matching input streams. */\r
+ uint32_t field_width;\r
+ /* How many arguments are assigned except the suppress. */\r
+ uint32_t nassigned = 0;\r
+ /* How many characters are read from the input streams. */\r
+ uint32_t n_decode = 0;\r
+\r
+ int32_t val;\r
+\r
+ const char *s;\r
+ /* Identifier for the input string. */\r
+ const char *p = line_ptr;\r
+\r
+#if SCANF_FLOAT_ENABLE\r
+ double fnum = 0.0;\r
+#endif /* SCANF_FLOAT_ENABLE */\r
+ /* Return EOF error before any conversion. */\r
+ if (*p == '\0')\r
+ {\r
+ return -1;\r
+ }\r
+\r
+ /* Decode directives. */\r
+ while ((*c) && (*p))\r
+ {\r
+ /* Ignore all white-spaces in the format strings. */\r
+ if (ScanIgnoreWhiteSpace((const char **)&c))\r
+ {\r
+ n_decode += ScanIgnoreWhiteSpace(&p);\r
+ }\r
+ else if ((*c != '%') || ((*c == '%') && (*(c + 1) == '%')))\r
+ {\r
+ /* Ordinary characters. */\r
+ c++;\r
+ if (*p == *c)\r
+ {\r
+ n_decode++;\r
+ p++;\r
+ c++;\r
+ }\r
+ else\r
+ {\r
+ /* Match failure. Misalignment with C99, the unmatched characters need to be pushed back to stream.\r
+ * However, it is deserted now. */\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* convernsion specification */\r
+ c++;\r
+ /* Reset. */\r
+ flag = 0;\r
+ field_width = 0;\r
+ base = 0;\r
+\r
+ /* Loop to get full conversion specification. */\r
+ while ((*c) && (!(flag & kSCANF_DestMask)))\r
+ {\r
+ switch (*c)\r
+ {\r
+#if SCANF_ADVANCED_ENABLE\r
+ case '*':\r
+ if (flag & kSCANF_Suppress)\r
+ {\r
+ /* Match failure. */\r
+ return nassigned;\r
+ }\r
+ flag |= kSCANF_Suppress;\r
+ c++;\r
+ break;\r
+ case 'h':\r
+ if (flag & kSCANF_LengthMask)\r
+ {\r
+ /* Match failure. */\r
+ return nassigned;\r
+ }\r
+\r
+ if (c[1] == 'h')\r
+ {\r
+ flag |= kSCANF_LengthChar;\r
+ c++;\r
+ }\r
+ else\r
+ {\r
+ flag |= kSCANF_LengthShortInt;\r
+ }\r
+ c++;\r
+ break;\r
+ case 'l':\r
+ if (flag & kSCANF_LengthMask)\r
+ {\r
+ /* Match failure. */\r
+ return nassigned;\r
+ }\r
+\r
+ if (c[1] == 'l')\r
+ {\r
+ flag |= kSCANF_LengthLongLongInt;\r
+ c++;\r
+ }\r
+ else\r
+ {\r
+ flag |= kSCANF_LengthLongInt;\r
+ }\r
+ c++;\r
+ break;\r
+#endif /* SCANF_ADVANCED_ENABLE */\r
+#if SCANF_FLOAT_ENABLE\r
+ case 'L':\r
+ if (flag & kSCANF_LengthMask)\r
+ {\r
+ /* Match failure. */\r
+ return nassigned;\r
+ }\r
+ flag |= kSCANF_LengthLongLongDouble;\r
+ c++;\r
+ break;\r
+#endif /* SCANF_FLOAT_ENABLE */\r
+ case '0':\r
+ case '1':\r
+ case '2':\r
+ case '3':\r
+ case '4':\r
+ case '5':\r
+ case '6':\r
+ case '7':\r
+ case '8':\r
+ case '9':\r
+ if (field_width)\r
+ {\r
+ /* Match failure. */\r
+ return nassigned;\r
+ }\r
+ do\r
+ {\r
+ field_width = field_width * 10 + *c - '0';\r
+ c++;\r
+ } while ((*c >= '0') && (*c <= '9'));\r
+ break;\r
+ case 'd':\r
+ base = 10;\r
+ flag |= kSCANF_TypeSinged;\r
+ flag |= kSCANF_DestInt;\r
+ c++;\r
+ break;\r
+ case 'u':\r
+ base = 10;\r
+ flag |= kSCANF_DestInt;\r
+ c++;\r
+ break;\r
+ case 'o':\r
+ base = 8;\r
+ flag |= kSCANF_DestInt;\r
+ c++;\r
+ break;\r
+ case 'x':\r
+ case 'X':\r
+ base = 16;\r
+ flag |= kSCANF_DestInt;\r
+ c++;\r
+ break;\r
+ case 'i':\r
+ base = 0;\r
+ flag |= kSCANF_DestInt;\r
+ c++;\r
+ break;\r
+#if SCANF_FLOAT_ENABLE\r
+ case 'a':\r
+ case 'A':\r
+ case 'e':\r
+ case 'E':\r
+ case 'f':\r
+ case 'F':\r
+ case 'g':\r
+ case 'G':\r
+ flag |= kSCANF_DestFloat;\r
+ c++;\r
+ break;\r
+#endif /* SCANF_FLOAT_ENABLE */\r
+ case 'c':\r
+ flag |= kSCANF_DestChar;\r
+ if (!field_width)\r
+ {\r
+ field_width = 1;\r
+ }\r
+ c++;\r
+ break;\r
+ case 's':\r
+ flag |= kSCANF_DestString;\r
+ c++;\r
+ break;\r
+ default:\r
+ return nassigned;\r
+ }\r
+ }\r
+\r
+ if (!(flag & kSCANF_DestMask))\r
+ {\r
+ /* Format strings are exhausted. */\r
+ return nassigned;\r
+ }\r
+\r
+ if (!field_width)\r
+ {\r
+ /* Large than length of a line. */\r
+ field_width = 99;\r
+ }\r
+\r
+ /* Matching strings in input streams and assign to argument. */\r
+ switch (flag & kSCANF_DestMask)\r
+ {\r
+ case kSCANF_DestChar:\r
+ s = (const char *)p;\r
+ buf = va_arg(args_ptr, char *);\r
+ while ((field_width--) && (*p))\r
+ {\r
+ if (!(flag & kSCANF_Suppress))\r
+ {\r
+ *buf++ = *p++;\r
+ }\r
+ else\r
+ {\r
+ p++;\r
+ }\r
+ n_decode++;\r
+ }\r
+\r
+ if ((!(flag & kSCANF_Suppress)) && (s != p))\r
+ {\r
+ nassigned++;\r
+ }\r
+ break;\r
+ case kSCANF_DestString:\r
+ n_decode += ScanIgnoreWhiteSpace(&p);\r
+ s = p;\r
+ buf = va_arg(args_ptr, char *);\r
+ while ((field_width--) && (*p != '\0') && (*p != ' ') && (*p != '\t') && (*p != '\n') &&\r
+ (*p != '\r') && (*p != '\v') && (*p != '\f'))\r
+ {\r
+ if (flag & kSCANF_Suppress)\r
+ {\r
+ p++;\r
+ }\r
+ else\r
+ {\r
+ *buf++ = *p++;\r
+ }\r
+ n_decode++;\r
+ }\r
+\r
+ if ((!(flag & kSCANF_Suppress)) && (s != p))\r
+ {\r
+ /* Add NULL to end of string. */\r
+ *buf = '\0';\r
+ nassigned++;\r
+ }\r
+ break;\r
+ case kSCANF_DestInt:\r
+ n_decode += ScanIgnoreWhiteSpace(&p);\r
+ s = p;\r
+ val = 0;\r
+ if ((base == 0) || (base == 16))\r
+ {\r
+ if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X')))\r
+ {\r
+ base = 16;\r
+ if (field_width >= 1)\r
+ {\r
+ p += 2;\r
+ n_decode += 2;\r
+ field_width -= 2;\r
+ }\r
+ }\r
+ }\r
+\r
+ if (base == 0)\r
+ {\r
+ if (s[0] == '0')\r
+ {\r
+ base = 8;\r
+ }\r
+ else\r
+ {\r
+ base = 10;\r
+ }\r
+ }\r
+\r
+ neg = 1;\r
+ switch (*p)\r
+ {\r
+ case '-':\r
+ neg = -1;\r
+ n_decode++;\r
+ p++;\r
+ field_width--;\r
+ break;\r
+ case '+':\r
+ neg = 1;\r
+ n_decode++;\r
+ p++;\r
+ field_width--;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ while ((*p) && (field_width--))\r
+ {\r
+ if ((*p <= '9') && (*p >= '0'))\r
+ {\r
+ temp = *p - '0';\r
+ }\r
+ else if ((*p <= 'f') && (*p >= 'a'))\r
+ {\r
+ temp = *p - 'a' + 10;\r
+ }\r
+ else if ((*p <= 'F') && (*p >= 'A'))\r
+ {\r
+ temp = *p - 'A' + 10;\r
+ }\r
+ else\r
+ {\r
+ temp = base;\r
+ }\r
+\r
+ if (temp >= base)\r
+ {\r
+ break;\r
+ }\r
+ else\r
+ {\r
+ val = base * val + temp;\r
+ }\r
+ p++;\r
+ n_decode++;\r
+ }\r
+ val *= neg;\r
+ if (!(flag & kSCANF_Suppress))\r
+ {\r
+#if SCANF_ADVANCED_ENABLE\r
+ switch (flag & kSCANF_LengthMask)\r
+ {\r
+ case kSCANF_LengthChar:\r
+ if (flag & kSCANF_TypeSinged)\r
+ {\r
+ *va_arg(args_ptr, signed char *) = (signed char)val;\r
+ }\r
+ else\r
+ {\r
+ *va_arg(args_ptr, unsigned char *) = (unsigned char)val;\r
+ }\r
+ break;\r
+ case kSCANF_LengthShortInt:\r
+ if (flag & kSCANF_TypeSinged)\r
+ {\r
+ *va_arg(args_ptr, signed short *) = (signed short)val;\r
+ }\r
+ else\r
+ {\r
+ *va_arg(args_ptr, unsigned short *) = (unsigned short)val;\r
+ }\r
+ break;\r
+ case kSCANF_LengthLongInt:\r
+ if (flag & kSCANF_TypeSinged)\r
+ {\r
+ *va_arg(args_ptr, signed long int *) = (signed long int)val;\r
+ }\r
+ else\r
+ {\r
+ *va_arg(args_ptr, unsigned long int *) = (unsigned long int)val;\r
+ }\r
+ break;\r
+ case kSCANF_LengthLongLongInt:\r
+ if (flag & kSCANF_TypeSinged)\r
+ {\r
+ *va_arg(args_ptr, signed long long int *) = (signed long long int)val;\r
+ }\r
+ else\r
+ {\r
+ *va_arg(args_ptr, unsigned long long int *) = (unsigned long long int)val;\r
+ }\r
+ break;\r
+ default:\r
+ /* The default type is the type int. */\r
+ if (flag & kSCANF_TypeSinged)\r
+ {\r
+ *va_arg(args_ptr, signed int *) = (signed int)val;\r
+ }\r
+ else\r
+ {\r
+ *va_arg(args_ptr, unsigned int *) = (unsigned int)val;\r
+ }\r
+ break;\r
+ }\r
+#else\r
+ /* The default type is the type int. */\r
+ if (flag & kSCANF_TypeSinged)\r
+ {\r
+ *va_arg(args_ptr, signed int *) = (signed int)val;\r
+ }\r
+ else\r
+ {\r
+ *va_arg(args_ptr, unsigned int *) = (unsigned int)val;\r
+ }\r
+#endif /* SCANF_ADVANCED_ENABLE */\r
+ nassigned++;\r
+ }\r
+ break;\r
+#if SCANF_FLOAT_ENABLE\r
+ case kSCANF_DestFloat:\r
+ n_decode += ScanIgnoreWhiteSpace(&p);\r
+ fnum = strtod(p, (char **)&s);\r
+\r
+ if ((fnum >= HUGE_VAL) || (fnum <= -HUGE_VAL))\r
+ {\r
+ break;\r
+ }\r
+\r
+ n_decode += (int)(s) - (int)(p);\r
+ p = s;\r
+ if (!(flag & kSCANF_Suppress))\r
+ {\r
+ if (flag & kSCANF_LengthLongLongDouble)\r
+ {\r
+ *va_arg(args_ptr, double *) = fnum;\r
+ }\r
+ else\r
+ {\r
+ *va_arg(args_ptr, float *) = (float)fnum;\r
+ }\r
+ nassigned++;\r
+ }\r
+ break;\r
+#endif /* SCANF_FLOAT_ENABLE */\r
+ default:\r
+ return nassigned;\r
+ }\r
+ }\r
+ }\r
+ return nassigned;\r
+}\r
--- /dev/null
+/*\r
+ * Copyright 2017 NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ *\r
+ */\r
+\r
+#ifndef _FSL_STR_H\r
+#define _FSL_STR_H\r
+\r
+#include "fsl_common.h"\r
+\r
+/*!\r
+ * @addtogroup debugconsole\r
+ * @{\r
+ */\r
+\r
+/*******************************************************************************\r
+ * Prototypes\r
+ ******************************************************************************/\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif /* __cplusplus */\r
+\r
+/*!\r
+ * @brief A function pointer which is used when format printf log.\r
+ */\r
+typedef void (*printfCb)(char *buf, int32_t *indicator, char val, int len);\r
+\r
+/*!\r
+ * @brief This function outputs its parameters according to a formatted string.\r
+ *\r
+ * @note I/O is performed by calling given function pointer using following\r
+ * (*func_ptr)(c);\r
+ *\r
+ * @param[in] fmt Format string for printf.\r
+ * @param[in] ap Arguments to printf.\r
+ * @param[in] buf pointer to the buffer\r
+ * @param cb print callbck function pointer\r
+ *\r
+ * @return Number of characters to be print\r
+ */\r
+int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb);\r
+\r
+/*!\r
+ * @brief Converts an input line of ASCII characters based upon a provided\r
+ * string format.\r
+ *\r
+ * @param[in] line_ptr The input line of ASCII data.\r
+ * @param[in] format Format first points to the format string.\r
+ * @param[in] args_ptr The list of parameters.\r
+ *\r
+ * @return Number of input items converted and assigned.\r
+ * @retval IO_EOF When line_ptr is empty string "".\r
+ */\r
+int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr);\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif /* __cplusplus */\r
+\r
+/*! @} */\r
+\r
+#endif /* _FSL_STR_H */\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">\r
+ <storageModule moduleId="org.eclipse.cdt.core.settings">\r
+ <cconfiguration id="com.crt.advproject.config.exe.debug.1736457840">\r
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.exe.debug.1736457840" moduleId="org.eclipse.cdt.core.settings" name="Debug">\r
+ <externalSettings/>\r
+ <extensions>\r
+ <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>\r
+ <extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>\r
+ <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+ <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+ <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+ <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>\r
+ <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+ </extensions>\r
+ </storageModule>\r
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
+ <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="Debug build" errorParsers="org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.config.exe.debug.1736457840" name="Debug" parent="com.crt.advproject.config.exe.debug" postannouncebuildStep="Performing post-build steps" postbuildStep="arm-none-eabi-size "${BuildArtifactFileName}"; # arm-none-eabi-objcopy -v -O binary "${BuildArtifactFileName}" "${BuildArtifactFileBaseName}.bin" ; # checksum -p ${TargetChip} -d "${BuildArtifactFileBaseName}.bin"; ">\r
+ <folderInfo id="com.crt.advproject.config.exe.debug.1736457840." name="/" resourcePath="">\r
+ <toolChain id="com.crt.advproject.toolchain.exe.debug.240336044" name="NXP MCU Tools" superClass="com.crt.advproject.toolchain.exe.debug">\r
+ <targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.exe.debug.1779853764" name="ARM-based MCU (Debug)" superClass="com.crt.advproject.platform.exe.debug"/>\r
+ <builder buildPath="${workspace_loc:/FreeRTOSDemo}/Debug" id="com.crt.advproject.builder.exe.debug.1263695098" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.debug"/>\r
+ <tool id="com.crt.advproject.cpp.exe.debug.1728072488" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.debug">\r
+ <option id="com.crt.advproject.cpp.arch.1175296083" name="Architecture" superClass="com.crt.advproject.cpp.arch" useByScannerDiscovery="true" value="com.crt.advproject.cpp.target.cm4" valueType="enumerated"/>\r
+ <option id="com.crt.advproject.cpp.misc.dialect.1590244997" name="Language standard" superClass="com.crt.advproject.cpp.misc.dialect" useByScannerDiscovery="true"/>\r
+ <option id="gnu.cpp.compiler.option.dialect.flags.1629555862" name="Other dialect flags" superClass="gnu.cpp.compiler.option.dialect.flags" useByScannerDiscovery="true"/>\r
+ <option id="gnu.cpp.compiler.option.preprocessor.nostdinc.602726906" name="Do not search system directories (-nostdinc)" superClass="gnu.cpp.compiler.option.preprocessor.nostdinc" useByScannerDiscovery="false"/>\r
+ <option id="gnu.cpp.compiler.option.preprocessor.preprocess.1961578482" name="Preprocess only (-E)" superClass="gnu.cpp.compiler.option.preprocessor.preprocess" useByScannerDiscovery="false"/>\r
+ <option id="gnu.cpp.compiler.option.preprocessor.def.1002107014" name="Defined symbols (-D)" superClass="gnu.cpp.compiler.option.preprocessor.def" useByScannerDiscovery="false"/>\r
+ <option id="gnu.cpp.compiler.option.preprocessor.undef.638012443" name="Undefined symbols (-U)" superClass="gnu.cpp.compiler.option.preprocessor.undef" useByScannerDiscovery="false"/>\r
+ <option id="gnu.cpp.compiler.option.include.paths.983001089" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" useByScannerDiscovery="false"/>\r
+ <option id="gnu.cpp.compiler.option.include.files.804685852" name="Include files (-include)" superClass="gnu.cpp.compiler.option.include.files" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.cpp.exe.debug.option.optimization.level.1649848490" name="Optimization Level" superClass="com.crt.advproject.cpp.exe.debug.option.optimization.level" useByScannerDiscovery="true"/>\r
+ <option id="gnu.cpp.compiler.option.optimization.flags.677012392" name="Other optimization flags" superClass="gnu.cpp.compiler.option.optimization.flags" useByScannerDiscovery="false" value="-fno-common" valueType="string"/>\r
+ <option id="com.crt.advproject.cpp.exe.debug.option.debugging.level.1417587731" name="Debug Level" superClass="com.crt.advproject.cpp.exe.debug.option.debugging.level" useByScannerDiscovery="false"/>\r
+ <option id="gnu.cpp.compiler.option.debugging.other.559941603" name="Other debugging flags" superClass="gnu.cpp.compiler.option.debugging.other" useByScannerDiscovery="false"/>\r
+ <option id="gnu.cpp.compiler.option.debugging.prof.564795725" name="Generate prof information (-p)" superClass="gnu.cpp.compiler.option.debugging.prof" useByScannerDiscovery="false"/>\r
+ <option id="gnu.cpp.compiler.option.debugging.gprof.815932622" name="Generate gprof information (-pg)" superClass="gnu.cpp.compiler.option.debugging.gprof" useByScannerDiscovery="false"/>\r
+ <option id="gnu.cpp.compiler.option.debugging.codecov.790181683" name="Generate gcov information (-ftest-coverage -fprofile-arcs)" superClass="gnu.cpp.compiler.option.debugging.codecov" useByScannerDiscovery="false"/>\r
+ <option id="gnu.cpp.compiler.option.warnings.syntax.88112652" name="Check syntax only (-fsyntax-only)" superClass="gnu.cpp.compiler.option.warnings.syntax" useByScannerDiscovery="false"/>\r
+ <option id="gnu.cpp.compiler.option.warnings.pedantic.881300834" name="Pedantic (-pedantic)" superClass="gnu.cpp.compiler.option.warnings.pedantic" useByScannerDiscovery="false"/>\r
+ <option id="gnu.cpp.compiler.option.warnings.pedantic.error.1725242808" name="Pedantic warnings as errors (-pedantic-errors)" superClass="gnu.cpp.compiler.option.warnings.pedantic.error" useByScannerDiscovery="false"/>\r
+ <option id="gnu.cpp.compiler.option.warnings.nowarn.1002132921" name="Inhibit all warnings (-w)" superClass="gnu.cpp.compiler.option.warnings.nowarn" useByScannerDiscovery="false"/>\r
+ <option id="gnu.cpp.compiler.option.warnings.allwarn.1620754777" name="All warnings (-Wall)" superClass="gnu.cpp.compiler.option.warnings.allwarn" useByScannerDiscovery="false"/>\r
+ <option id="gnu.cpp.compiler.option.warnings.extrawarn.306762746" name="Extra warnings (-Wextra)" superClass="gnu.cpp.compiler.option.warnings.extrawarn" useByScannerDiscovery="false"/>\r
+ <option id="gnu.cpp.compiler.option.warnings.toerrors.566950003" name="Warnings as errors (-Werror)" superClass="gnu.cpp.compiler.option.warnings.toerrors" useByScannerDiscovery="false"/>\r
+ <option id="gnu.cpp.compiler.option.warnings.wconversion.704369576" name="Implicit conversion warnings (-Wconversion)" superClass="gnu.cpp.compiler.option.warnings.wconversion" useByScannerDiscovery="false"/>\r
+ <option id="gnu.cpp.compiler.option.other.other.2132215552" name="Other flags" superClass="gnu.cpp.compiler.option.other.other" useByScannerDiscovery="false"/>\r
+ <option id="gnu.cpp.compiler.option.other.verbose.1872876346" name="Verbose (-v)" superClass="gnu.cpp.compiler.option.other.verbose" useByScannerDiscovery="false"/>\r
+ <option id="gnu.cpp.compiler.option.other.pic.1826951272" name="Position Independent Code (-fPIC)" superClass="gnu.cpp.compiler.option.other.pic" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.cpp.lto.1861915514" name="Enable Link-time optimization (-flto)" superClass="com.crt.advproject.cpp.lto" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.cpp.lto.fat.486980577" name="Fat lto objects (-ffat-lto-objects)" superClass="com.crt.advproject.cpp.lto.fat" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.cpp.merge.constants.249495250" name="Merge Identical Constants (-fmerge-constants)" superClass="com.crt.advproject.cpp.merge.constants" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.cpp.prefixmap.110171675" name="Remove path from __FILE__ (-fmacro-prefix-map)" superClass="com.crt.advproject.cpp.prefixmap" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.cpp.fpu.1380190083" name="Floating point" superClass="com.crt.advproject.cpp.fpu" useByScannerDiscovery="true" value="com.crt.advproject.cpp.fpu.fpv4.hard" valueType="enumerated"/>\r
+ <option id="com.crt.advproject.cpp.thumb.87730734" name="Thumb mode" superClass="com.crt.advproject.cpp.thumb" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.cpp.thumbinterwork.149757268" name="Enable Thumb interworking" superClass="com.crt.advproject.cpp.thumbinterwork" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.cpp.securestate.1982530234" name="TrustZone Project Type" superClass="com.crt.advproject.cpp.securestate" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.cpp.hdrlib.926137618" name="Library headers" superClass="com.crt.advproject.cpp.hdrlib" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.cpp.stackusage.140442899" name="Generate Stack Usage Info (-fstack-usage)" superClass="com.crt.advproject.cpp.stackusage" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.cpp.specs.14407963" name="Specs" superClass="com.crt.advproject.cpp.specs" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.cpp.config.1666925" name="Obsolete (Config)" superClass="com.crt.advproject.cpp.config" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.cpp.store.10625467" name="Obsolete (Store)" superClass="com.crt.advproject.cpp.store" useByScannerDiscovery="false"/>\r
+ </tool>\r
+ <tool id="com.crt.advproject.gcc.exe.debug.1970139153" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.debug">\r
+ <option id="com.crt.advproject.gcc.thumb.1105729438" name="Thumb mode" superClass="com.crt.advproject.gcc.thumb" useByScannerDiscovery="false" value="true" valueType="boolean"/>\r
+ <option id="com.crt.advproject.gcc.arch.1614152875" name="Architecture" superClass="com.crt.advproject.gcc.arch" useByScannerDiscovery="true" value="com.crt.advproject.gcc.target.cm4" valueType="enumerated"/>\r
+ <option id="com.crt.advproject.c.misc.dialect.61301729" name="Language standard" superClass="com.crt.advproject.c.misc.dialect" useByScannerDiscovery="true" value="com.crt.advproject.misc.dialect.gnu99" valueType="enumerated"/>\r
+ <option id="gnu.c.compiler.option.dialect.flags.356693735" name="Other dialect flags" superClass="gnu.c.compiler.option.dialect.flags" useByScannerDiscovery="true"/>\r
+ <option id="gnu.c.compiler.option.preprocessor.nostdinc.221833775" name="Do not search system directories (-nostdinc)" superClass="gnu.c.compiler.option.preprocessor.nostdinc" useByScannerDiscovery="false"/>\r
+ <option id="gnu.c.compiler.option.preprocessor.preprocess.1943460156" name="Preprocess only (-E)" superClass="gnu.c.compiler.option.preprocessor.preprocess" useByScannerDiscovery="false"/>\r
+ <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.c.compiler.option.preprocessor.def.symbols.581612319" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" useByScannerDiscovery="false" valueType="definedSymbols">\r
+ <listOptionValue builtIn="false" value="CPU_LPC54018JET180=1"/>\r
+ <listOptionValue builtIn="false" value="CPU_LPC54018JET180_cm4"/>\r
+ <listOptionValue builtIn="false" value="XIP_IMAGE"/>\r
+ <listOptionValue builtIn="false" value="W25Q128JVFM"/>\r
+ <listOptionValue builtIn="false" value="CPU_LPC54018"/>\r
+ <listOptionValue builtIn="false" value="__USE_CMSIS"/>\r
+ <listOptionValue builtIn="false" value="MXL12835F"/>\r
+ <listOptionValue builtIn="false" value="SERIAL_PORT_TYPE_UART=1"/>\r
+ <listOptionValue builtIn="false" value="FSL_RTOS_FREE_RTOS"/>\r
+ <listOptionValue builtIn="false" value="SDK_DEBUGCONSOLE=0"/>\r
+ <listOptionValue builtIn="false" value="CR_INTEGER_PRINTF"/>\r
+ <listOptionValue builtIn="false" value="PRINTF_FLOAT_ENABLE=0"/>\r
+ <listOptionValue builtIn="false" value="__MCUXPRESSO"/>\r
+ <listOptionValue builtIn="false" value="DEBUG"/>\r
+ <listOptionValue builtIn="false" value="__REDLIB__"/>\r
+ </option>\r
+ <option id="gnu.c.compiler.option.preprocessor.undef.symbol.1347678265" name="Undefined symbols (-U)" superClass="gnu.c.compiler.option.preprocessor.undef.symbol" useByScannerDiscovery="false"/>\r
+ <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.c.compiler.option.include.paths.1527135388" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/NXP_Code/board}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/NXP_Code/drivers}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/NXP_Code/device}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/NXP_Code/CMSIS}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/NXP_Code/utilities}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/NXP_Code/component/serial_manager}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/NXP_Code/component/lists}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/NXP_Code/component/uart}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Config}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Demo}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS/include}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS/portable/GCC/ARM_CM4_MPU}""/>\r
+ </option>\r
+ <option id="gnu.c.compiler.option.include.files.1633401450" name="Include files (-include)" superClass="gnu.c.compiler.option.include.files" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.gcc.exe.debug.option.optimization.level.1718806940" name="Optimization Level" superClass="com.crt.advproject.gcc.exe.debug.option.optimization.level" useByScannerDiscovery="true"/>\r
+ <option id="gnu.c.compiler.option.optimization.flags.1201874316" name="Other optimization flags" superClass="gnu.c.compiler.option.optimization.flags" useByScannerDiscovery="false" value="-fno-common" valueType="string"/>\r
+ <option id="com.crt.advproject.gcc.exe.debug.option.debugging.level.1042826050" name="Debug Level" superClass="com.crt.advproject.gcc.exe.debug.option.debugging.level" useByScannerDiscovery="false"/>\r
+ <option id="gnu.c.compiler.option.debugging.other.1014019160" name="Other debugging flags" superClass="gnu.c.compiler.option.debugging.other" useByScannerDiscovery="false"/>\r
+ <option id="gnu.c.compiler.option.debugging.prof.451745226" name="Generate prof information (-p)" superClass="gnu.c.compiler.option.debugging.prof" useByScannerDiscovery="false"/>\r
+ <option id="gnu.c.compiler.option.debugging.gprof.1439287771" name="Generate gprof information (-pg)" superClass="gnu.c.compiler.option.debugging.gprof" useByScannerDiscovery="false"/>\r
+ <option id="gnu.c.compiler.option.debugging.codecov.721867846" name="Generate gcov information (-ftest-coverage -fprofile-arcs)" superClass="gnu.c.compiler.option.debugging.codecov" useByScannerDiscovery="false"/>\r
+ <option id="gnu.c.compiler.option.warnings.syntax.187338404" name="Check syntax only (-fsyntax-only)" superClass="gnu.c.compiler.option.warnings.syntax" useByScannerDiscovery="false"/>\r
+ <option id="gnu.c.compiler.option.warnings.pedantic.647919284" name="Pedantic (-pedantic)" superClass="gnu.c.compiler.option.warnings.pedantic" useByScannerDiscovery="false"/>\r
+ <option id="gnu.c.compiler.option.warnings.pedantic.error.1676517576" name="Pedantic warnings as errors (-pedantic-errors)" superClass="gnu.c.compiler.option.warnings.pedantic.error" useByScannerDiscovery="false"/>\r
+ <option id="gnu.c.compiler.option.warnings.nowarn.304135482" name="Inhibit all warnings (-w)" superClass="gnu.c.compiler.option.warnings.nowarn" useByScannerDiscovery="false"/>\r
+ <option id="gnu.c.compiler.option.warnings.allwarn.1611226404" name="All warnings (-Wall)" superClass="gnu.c.compiler.option.warnings.allwarn" useByScannerDiscovery="false"/>\r
+ <option id="gnu.c.compiler.option.warnings.extrawarn.1201734336" name="Extra warnings (-Wextra)" superClass="gnu.c.compiler.option.warnings.extrawarn" useByScannerDiscovery="false"/>\r
+ <option id="gnu.c.compiler.option.warnings.toerrors.1850215729" name="Warnings as errors (-Werror)" superClass="gnu.c.compiler.option.warnings.toerrors" useByScannerDiscovery="false"/>\r
+ <option id="gnu.c.compiler.option.warnings.wconversion.2031332653" name="Implicit conversion warnings (-Wconversion)" superClass="gnu.c.compiler.option.warnings.wconversion" useByScannerDiscovery="false"/>\r
+ <option id="gnu.c.compiler.option.misc.other.552564654" name="Other flags" superClass="gnu.c.compiler.option.misc.other" useByScannerDiscovery="false" value="-c -ffunction-sections -fdata-sections -ffreestanding -fno-builtin" valueType="string"/>\r
+ <option id="gnu.c.compiler.option.misc.verbose.1861014715" name="Verbose (-v)" superClass="gnu.c.compiler.option.misc.verbose" useByScannerDiscovery="false"/>\r
+ <option id="gnu.c.compiler.option.misc.ansi.1425557981" name="Support ANSI programs (-ansi)" superClass="gnu.c.compiler.option.misc.ansi" useByScannerDiscovery="false"/>\r
+ <option id="gnu.c.compiler.option.misc.pic.1997513529" name="Position Independent Code (-fPIC)" superClass="gnu.c.compiler.option.misc.pic" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.gcc.lto.495354563" name="Enable Link-time optimization (-flto)" superClass="com.crt.advproject.gcc.lto" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.gcc.lto.fat.1429637975" name="Fat lto objects (-ffat-lto-objects)" superClass="com.crt.advproject.gcc.lto.fat" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.gcc.merge.constants.2144524488" name="Merge Identical Constants (-fmerge-constants)" superClass="com.crt.advproject.gcc.merge.constants" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.gcc.prefixmap.72414569" name="Remove path from __FILE__ (-fmacro-prefix-map)" superClass="com.crt.advproject.gcc.prefixmap" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.gcc.fpu.574740811" name="Floating point" superClass="com.crt.advproject.gcc.fpu" useByScannerDiscovery="true" value="com.crt.advproject.gcc.fpu.fpv4.hard" valueType="enumerated"/>\r
+ <option id="com.crt.advproject.gcc.thumbinterwork.69036773" name="Enable Thumb interworking" superClass="com.crt.advproject.gcc.thumbinterwork" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.gcc.securestate.718028118" name="TrustZone Project Type" superClass="com.crt.advproject.gcc.securestate" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.gcc.hdrlib.1084824936" name="Library headers" superClass="com.crt.advproject.gcc.hdrlib" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.gcc.stackusage.498146456" name="Generate Stack Usage Info (-fstack-usage)" superClass="com.crt.advproject.gcc.stackusage" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.gcc.specs.1658292762" name="Specs" superClass="com.crt.advproject.gcc.specs" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.gcc.config.1464370851" name="Obsolete (Config)" superClass="com.crt.advproject.gcc.config" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.gcc.store.1462187297" name="Obsolete (Store)" superClass="com.crt.advproject.gcc.store" useByScannerDiscovery="false"/>\r
+ <inputType id="com.crt.advproject.compiler.input.376371565" superClass="com.crt.advproject.compiler.input"/>\r
+ </tool>\r
+ <tool id="com.crt.advproject.gas.exe.debug.232366964" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.debug">\r
+ <option id="com.crt.advproject.gas.thumb.508465339" name="Thumb mode" superClass="com.crt.advproject.gas.thumb" useByScannerDiscovery="false" value="true" valueType="boolean"/>\r
+ <option id="com.crt.advproject.gas.arch.1442555343" name="Architecture" superClass="com.crt.advproject.gas.arch" useByScannerDiscovery="false" value="com.crt.advproject.gas.target.cm4" valueType="enumerated"/>\r
+ <option id="gnu.both.asm.option.flags.crt.414346265" name="Assembler flags" superClass="gnu.both.asm.option.flags.crt" useByScannerDiscovery="false" value="-c -x assembler-with-cpp -D__REDLIB__" valueType="string"/>\r
+ <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.both.asm.option.include.paths.1198095644" name="Include paths (-I)" superClass="gnu.both.asm.option.include.paths" useByScannerDiscovery="false" valueType="includePath">\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/NXP_Code/board}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/NXP_Code/drivers}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/NXP_Code/device}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/NXP_Code/CMSIS}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/NXP_Code/utilities}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/NXP_Code/component/serial_manager}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/NXP_Code/component/lists}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/NXP_Code/component/uart}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Config}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Demo}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS/include}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS/portable/GCC/ARM_CM4_MPU}""/>\r
+ </option>\r
+ <option id="gnu.both.asm.option.warnings.nowarn.1118988451" name="Suppress warnings (-W)" superClass="gnu.both.asm.option.warnings.nowarn" useByScannerDiscovery="false"/>\r
+ <option id="gnu.both.asm.option.version.243519415" name="Announce version (-v)" superClass="gnu.both.asm.option.version" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.gas.exe.debug.option.debugging.level.1183104583" name="Debug level" superClass="com.crt.advproject.gas.exe.debug.option.debugging.level" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.gas.fpu.201100762" name="Floating point" superClass="com.crt.advproject.gas.fpu" useByScannerDiscovery="false" value="com.crt.advproject.gas.fpu.fpv4.hard" valueType="enumerated"/>\r
+ <option id="com.crt.advproject.gas.thumbinterwork.2139771195" name="Enable Thumb interworking" superClass="com.crt.advproject.gas.thumbinterwork" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.gas.hdrlib.1781682919" name="Library headers" superClass="com.crt.advproject.gas.hdrlib" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.gas.specs.20766936" name="Specs" superClass="com.crt.advproject.gas.specs" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.gas.config.1936625602" name="Obsolete (Config)" superClass="com.crt.advproject.gas.config" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.gas.store.2044928625" name="Obsolete (Store)" superClass="com.crt.advproject.gas.store" useByScannerDiscovery="false"/>\r
+ <inputType id="cdt.managedbuild.tool.gnu.assembler.input.518347860" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>\r
+ <inputType id="com.crt.advproject.assembler.input.1598241085" name="Additional Assembly Source Files" superClass="com.crt.advproject.assembler.input"/>\r
+ </tool>\r
+ <tool id="com.crt.advproject.link.cpp.exe.debug.954394348" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.debug">\r
+ <option id="com.crt.advproject.link.cpp.arch.79930041" name="Architecture" superClass="com.crt.advproject.link.cpp.arch" value="com.crt.advproject.link.cpp.target.cm4" valueType="enumerated"/>\r
+ <option id="gnu.cpp.link.option.nostart.1526270418" name="Do not use standard start files (-nostartfiles)" superClass="gnu.cpp.link.option.nostart"/>\r
+ <option id="gnu.cpp.link.option.nodeflibs.1123106397" name="Do not use default libraries (-nodefaultlibs)" superClass="gnu.cpp.link.option.nodeflibs"/>\r
+ <option id="gnu.cpp.link.option.nostdlibs.1271825831" name="No startup or default libs (-nostdlib)" superClass="gnu.cpp.link.option.nostdlibs" value="true" valueType="boolean"/>\r
+ <option id="gnu.cpp.link.option.strip.1226567945" name="Omit all symbol information (-s)" superClass="gnu.cpp.link.option.strip"/>\r
+ <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.cpp.link.option.libs.546881884" name="Libraries (-l)" superClass="gnu.cpp.link.option.libs" valueType="libs">\r
+ <listOptionValue builtIn="false" value="power_hardabi"/>\r
+ </option>\r
+ <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.cpp.link.option.paths.1281361528" name="Library search path (-L)" superClass="gnu.cpp.link.option.paths" valueType="libPaths">\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/NXP_Code/libs}""/>\r
+ </option>\r
+ <option id="gnu.cpp.link.option.flags.1910216190" name="Linker flags" superClass="gnu.cpp.link.option.flags"/>\r
+ <option id="gnu.cpp.link.option.other.468789820" name="Other options (-Xlinker [option])" superClass="gnu.cpp.link.option.other"/>\r
+ <option id="gnu.cpp.link.option.userobjs.1106092448" name="Other objects" superClass="gnu.cpp.link.option.userobjs"/>\r
+ <option id="gnu.cpp.link.option.shared.2033156219" name="Shared (-shared)" superClass="gnu.cpp.link.option.shared"/>\r
+ <option id="gnu.cpp.link.option.soname.1852338686" name="Shared object name (-Wl,-soname=)" superClass="gnu.cpp.link.option.soname"/>\r
+ <option id="gnu.cpp.link.option.implname.1917463940" name="Import Library name (-Wl,--out-implib=)" superClass="gnu.cpp.link.option.implname"/>\r
+ <option id="gnu.cpp.link.option.defname.2110006287" name="DEF file name (-Wl,--output-def=)" superClass="gnu.cpp.link.option.defname"/>\r
+ <option id="gnu.cpp.link.option.debugging.prof.780973193" name="Generate prof information (-p)" superClass="gnu.cpp.link.option.debugging.prof"/>\r
+ <option id="gnu.cpp.link.option.debugging.gprof.461845632" name="Generate gprof information (-pg)" superClass="gnu.cpp.link.option.debugging.gprof"/>\r
+ <option id="gnu.cpp.link.option.debugging.codecov.847067807" name="Generate gcov information (-ftest-coverage -fprofile-arcs)" superClass="gnu.cpp.link.option.debugging.codecov"/>\r
+ <option id="com.crt.advproject.link.cpp.lto.1929871411" name="Enable Link-time optimization (-flto)" superClass="com.crt.advproject.link.cpp.lto"/>\r
+ <option id="com.crt.advproject.link.cpp.lto.optmization.level.1183253597" name="Link-time optimization level" superClass="com.crt.advproject.link.cpp.lto.optmization.level"/>\r
+ <option id="com.crt.advproject.link.cpp.fpu.1798703829" name="Floating point" superClass="com.crt.advproject.link.cpp.fpu" value="com.crt.advproject.link.cpp.fpu.fpv4.hard" valueType="enumerated"/>\r
+ <option id="com.crt.advproject.link.cpp.thumb.58205290" name="Thumb mode" superClass="com.crt.advproject.link.cpp.thumb"/>\r
+ <option id="com.crt.advproject.link.cpp.manage.17690161" name="Manage linker script" superClass="com.crt.advproject.link.cpp.manage"/>\r
+ <option id="com.crt.advproject.link.cpp.script.1619962145" name="Linker script" superClass="com.crt.advproject.link.cpp.script"/>\r
+ <option id="com.crt.advproject.link.cpp.scriptdir.83294990" name="Script path" superClass="com.crt.advproject.link.cpp.scriptdir"/>\r
+ <option id="com.crt.advproject.link.cpp.crpenable.1720063411" name="Enable automatic placement of Code Read Protection field in image" superClass="com.crt.advproject.link.cpp.crpenable"/>\r
+ <option id="com.crt.advproject.link.cpp.flashconfigenable.1416205990" name="Enable automatic placement of Flash Configuration field in image" superClass="com.crt.advproject.link.cpp.flashconfigenable" value="true" valueType="boolean"/>\r
+ <option id="com.crt.advproject.link.cpp.ecrp.1286282871" name="Enhanced CRP" superClass="com.crt.advproject.link.cpp.ecrp"/>\r
+ <option id="com.crt.advproject.link.cpp.hdrlib.1686324205" name="Library" superClass="com.crt.advproject.link.cpp.hdrlib"/>\r
+ <option id="com.crt.advproject.link.cpp.nanofloat.136841965" name="Enable printf float " superClass="com.crt.advproject.link.cpp.nanofloat"/>\r
+ <option id="com.crt.advproject.link.cpp.nanofloat.scanf.1521712693" name="Enable scanf float " superClass="com.crt.advproject.link.cpp.nanofloat.scanf"/>\r
+ <option id="com.crt.advproject.link.cpp.toram.1625707651" name="Link application to RAM" superClass="com.crt.advproject.link.cpp.toram"/>\r
+ <option id="com.crt.advproject.link.memory.load.image.cpp.1481323376" name="Plain load image" superClass="com.crt.advproject.link.memory.load.image.cpp"/>\r
+ <option id="com.crt.advproject.link.memory.heapAndStack.style.cpp.178619048" name="Heap and Stack placement" superClass="com.crt.advproject.link.memory.heapAndStack.style.cpp"/>\r
+ <option id="com.crt.advproject.link.cpp.stackOffset.971599184" name="Stack offset" superClass="com.crt.advproject.link.cpp.stackOffset"/>\r
+ <option id="com.crt.advproject.link.memory.heapAndStack.cpp.833529442" name="Heap and Stack options" superClass="com.crt.advproject.link.memory.heapAndStack.cpp"/>\r
+ <option id="com.crt.advproject.link.memory.data.cpp.1778405209" name="Global data placement" superClass="com.crt.advproject.link.memory.data.cpp"/>\r
+ <option id="com.crt.advproject.link.memory.sections.cpp.1993238170" name="Extra linker script input sections" superClass="com.crt.advproject.link.memory.sections.cpp"/>\r
+ <option id="com.crt.advproject.link.cpp.multicore.slave.2027409717" name="Multicore configuration" superClass="com.crt.advproject.link.cpp.multicore.slave"/>\r
+ <option id="com.crt.advproject.link.cpp.multicore.master.1488779522" name="Multicore master" superClass="com.crt.advproject.link.cpp.multicore.master"/>\r
+ <option id="com.crt.advproject.link.cpp.multicore.empty.861920854" name="No Multicore options for this project" superClass="com.crt.advproject.link.cpp.multicore.empty"/>\r
+ <option id="com.crt.advproject.link.cpp.multicore.master.userobjs.1495488545" name="Slave Objects (not visible)" superClass="com.crt.advproject.link.cpp.multicore.master.userobjs"/>\r
+ <option id="com.crt.advproject.link.cpp.config.926506335" name="Obsolete (Config)" superClass="com.crt.advproject.link.cpp.config"/>\r
+ <option id="com.crt.advproject.link.cpp.store.940562340" name="Obsolete (Store)" superClass="com.crt.advproject.link.cpp.store"/>\r
+ <option id="com.crt.advproject.link.cpp.securestate.769885353" name="TrustZone Project Type" superClass="com.crt.advproject.link.cpp.securestate"/>\r
+ <option id="com.crt.advproject.link.cpp.sgstubs.placement.875652002" name="Secure Gateway Placement" superClass="com.crt.advproject.link.cpp.sgstubs.placement"/>\r
+ <option id="com.crt.advproject.link.cpp.sgstubenable.992803253" name="Enable generation of Secure Gateway Import Library" superClass="com.crt.advproject.link.cpp.sgstubenable"/>\r
+ <option id="com.crt.advproject.link.cpp.nonsecureobject.882116138" name="Secure Gateway Import Library" superClass="com.crt.advproject.link.cpp.nonsecureobject"/>\r
+ <option id="com.crt.advproject.link.cpp.inimplib.1943791199" name="Input Secure Gateway Import Library" superClass="com.crt.advproject.link.cpp.inimplib"/>\r
+ </tool>\r
+ <tool id="com.crt.advproject.link.exe.debug.1377892473" name="MCU Linker" superClass="com.crt.advproject.link.exe.debug">\r
+ <option id="com.crt.advproject.link.thumb.1824663771" name="Thumb mode" superClass="com.crt.advproject.link.thumb" useByScannerDiscovery="false" value="true" valueType="boolean"/>\r
+ <option id="com.crt.advproject.link.memory.load.image.558349136" name="Plain load image" superClass="com.crt.advproject.link.memory.load.image" useByScannerDiscovery="false" value="true;SRAMX" valueType="string"/>\r
+ <option defaultValue="com.crt.advproject.heapAndStack.mcuXpressoStyle" id="com.crt.advproject.link.memory.heapAndStack.style.1318181182" name="Heap and Stack placement" superClass="com.crt.advproject.link.memory.heapAndStack.style" useByScannerDiscovery="false" valueType="enumerated"/>\r
+ <option id="com.crt.advproject.link.memory.heapAndStack.1059234943" name="Heap and Stack options" superClass="com.crt.advproject.link.memory.heapAndStack" useByScannerDiscovery="false" value="&Heap:Default;Post Data;Default&Stack:Default;End;Default" valueType="string"/>\r
+ <option id="com.crt.advproject.link.memory.data.851042339" name="Global data placement" superClass="com.crt.advproject.link.memory.data" useByScannerDiscovery="false" value="SRAM_0_1_2_3" valueType="string"/>\r
+ <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="com.crt.advproject.link.memory.sections.30529004" name="Extra linker script input sections" superClass="com.crt.advproject.link.memory.sections" useByScannerDiscovery="false" valueType="stringList"/>\r
+ <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="com.crt.advproject.link.gcc.multicore.master.userobjs.1457180455" name="Slave Objects (not visible)" superClass="com.crt.advproject.link.gcc.multicore.master.userobjs" useByScannerDiscovery="false" valueType="userObjs"/>\r
+ <option id="com.crt.advproject.link.arch.302870297" name="Architecture" superClass="com.crt.advproject.link.arch" useByScannerDiscovery="false" value="com.crt.advproject.link.target.cm4" valueType="enumerated"/>\r
+ <option id="gnu.c.link.option.nostart.130997344" name="Do not use standard start files (-nostartfiles)" superClass="gnu.c.link.option.nostart" useByScannerDiscovery="false"/>\r
+ <option id="gnu.c.link.option.nodeflibs.513286166" name="Do not use default libraries (-nodefaultlibs)" superClass="gnu.c.link.option.nodeflibs" useByScannerDiscovery="false"/>\r
+ <option id="gnu.c.link.option.nostdlibs.184113888" name="No startup or default libs (-nostdlib)" superClass="gnu.c.link.option.nostdlibs" useByScannerDiscovery="false" value="true" valueType="boolean"/>\r
+ <option id="gnu.c.link.option.strip.1699207811" name="Omit all symbol information (-s)" superClass="gnu.c.link.option.strip" useByScannerDiscovery="false"/>\r
+ <option id="gnu.c.link.option.noshared.1811362499" name="No shared libraries (-static)" superClass="gnu.c.link.option.noshared" useByScannerDiscovery="false"/>\r
+ <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.c.link.option.libs.1319534926" name="Libraries (-l)" superClass="gnu.c.link.option.libs" useByScannerDiscovery="false" valueType="libs">\r
+ <listOptionValue builtIn="false" value="power_hardabi"/>\r
+ </option>\r
+ <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.c.link.option.paths.718525159" name="Library search path (-L)" superClass="gnu.c.link.option.paths" useByScannerDiscovery="false" valueType="libPaths">\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/NXP_Code/libs}""/>\r
+ </option>\r
+ <option id="gnu.c.link.option.ldflags.760660943" name="Linker flags" superClass="gnu.c.link.option.ldflags" useByScannerDiscovery="false"/>\r
+ <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.c.link.option.other.719404017" name="Other options (-Xlinker [option])" superClass="gnu.c.link.option.other" useByScannerDiscovery="false" valueType="stringList">\r
+ <listOptionValue builtIn="false" value="-Map="${BuildArtifactFileBaseName}.map""/>\r
+ <listOptionValue builtIn="false" value="--gc-sections"/>\r
+ <listOptionValue builtIn="false" value="-print-memory-usage"/>\r
+ <listOptionValue builtIn="false" value="--sort-section=alignment"/>\r
+ <listOptionValue builtIn="false" value="--cref"/>\r
+ </option>\r
+ <option id="gnu.c.link.option.userobjs.1411804971" name="Other objects" superClass="gnu.c.link.option.userobjs" useByScannerDiscovery="false"/>\r
+ <option id="gnu.c.link.option.shared.1311734214" name="Shared (-shared)" superClass="gnu.c.link.option.shared" useByScannerDiscovery="false"/>\r
+ <option id="gnu.c.link.option.soname.1154964079" name="Shared object name (-Wl,-soname=)" superClass="gnu.c.link.option.soname" useByScannerDiscovery="false"/>\r
+ <option id="gnu.c.link.option.implname.1486483013" name="Import Library name (-Wl,--out-implib=)" superClass="gnu.c.link.option.implname" useByScannerDiscovery="false"/>\r
+ <option id="gnu.c.link.option.defname.804399135" name="DEF file name (-Wl,--output-def=)" superClass="gnu.c.link.option.defname" useByScannerDiscovery="false"/>\r
+ <option id="gnu.c.link.option.debugging.prof.699682390" name="Generate prof information (-p)" superClass="gnu.c.link.option.debugging.prof" useByScannerDiscovery="false"/>\r
+ <option id="gnu.c.link.option.debugging.gprof.1465979208" name="Generate gprof information (-pg)" superClass="gnu.c.link.option.debugging.gprof" useByScannerDiscovery="false"/>\r
+ <option id="gnu.c.link.option.debugging.codecov.1165703681" name="Generate gcov information (-ftest-coverage -fprofile-arcs)" superClass="gnu.c.link.option.debugging.codecov" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.link.gcc.lto.128207414" name="Enable Link-time optimization (-flto)" superClass="com.crt.advproject.link.gcc.lto" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.link.gcc.lto.optmization.level.2050759852" name="Link-time optimization level" superClass="com.crt.advproject.link.gcc.lto.optmization.level" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.link.fpu.1624232115" name="Floating point" superClass="com.crt.advproject.link.fpu" useByScannerDiscovery="false" value="com.crt.advproject.link.fpu.fpv4.hard" valueType="enumerated"/>\r
+ <option id="com.crt.advproject.link.manage.1883987729" name="Manage linker script" superClass="com.crt.advproject.link.manage" useByScannerDiscovery="false" value="false" valueType="boolean"/>\r
+ <option id="com.crt.advproject.link.script.1712620045" name="Linker script" superClass="com.crt.advproject.link.script" useByScannerDiscovery="false" value="FreeRTOSDemo.ld" valueType="string"/>\r
+ <option id="com.crt.advproject.link.scriptdir.1776047271" name="Script path" superClass="com.crt.advproject.link.scriptdir" useByScannerDiscovery="false" value="../" valueType="string"/>\r
+ <option id="com.crt.advproject.link.crpenable.454979384" name="Enable automatic placement of Code Read Protection field in image" superClass="com.crt.advproject.link.crpenable" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.link.flashconfigenable.1315063676" name="Enable automatic placement of Flash Configuration field in image" superClass="com.crt.advproject.link.flashconfigenable" useByScannerDiscovery="false" value="true" valueType="boolean"/>\r
+ <option id="com.crt.advproject.link.ecrp.1292274236" name="Enhanced CRP" superClass="com.crt.advproject.link.ecrp" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.link.gcc.hdrlib.959913482" name="Library" superClass="com.crt.advproject.link.gcc.hdrlib" useByScannerDiscovery="false" value="com.crt.advproject.gcc.link.hdrlib.codered.semihost_nf" valueType="enumerated"/>\r
+ <option id="com.crt.advproject.link.gcc.nanofloat.107690637" name="Enable printf float " superClass="com.crt.advproject.link.gcc.nanofloat" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.link.gcc.nanofloat.scanf.1889181136" name="Enable scanf float " superClass="com.crt.advproject.link.gcc.nanofloat.scanf" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.link.toram.454075824" name="Link application to RAM" superClass="com.crt.advproject.link.toram" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.link.stackOffset.380466158" name="Stack offset" superClass="com.crt.advproject.link.stackOffset" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.link.gcc.multicore.slave.529501453" name="Multicore configuration" superClass="com.crt.advproject.link.gcc.multicore.slave" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.link.gcc.multicore.master.292232186" name="Multicore master" superClass="com.crt.advproject.link.gcc.multicore.master" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.link.gcc.multicore.empty.965063611" name="No Multicore options for this project" superClass="com.crt.advproject.link.gcc.multicore.empty" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.link.config.1081721194" name="Obsolete (Config)" superClass="com.crt.advproject.link.config" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.link.store.1571893346" name="Obsolete (Store)" superClass="com.crt.advproject.link.store" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.link.securestate.1516768621" name="TrustZone Project Type" superClass="com.crt.advproject.link.securestate" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.link.sgstubs.placement.185951968" name="Secure Gateway Placement" superClass="com.crt.advproject.link.sgstubs.placement" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.link.sgstubenable.1797053478" name="Enable generation of Secure Gateway Import Library" superClass="com.crt.advproject.link.sgstubenable" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.link.nonsecureobject.1171352109" name="Secure Gateway Import Library" superClass="com.crt.advproject.link.nonsecureobject" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.link.inimplib.810999894" name="Input Secure Gateway Import Library" superClass="com.crt.advproject.link.inimplib" useByScannerDiscovery="false"/>\r
+ <inputType id="cdt.managedbuild.tool.gnu.c.linker.input.1748396116" superClass="cdt.managedbuild.tool.gnu.c.linker.input">\r
+ <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>\r
+ <additionalInput kind="additionalinput" paths="$(LIBS)"/>\r
+ </inputType>\r
+ </tool>\r
+ <tool id="com.crt.advproject.tool.debug.debug.1356436549" name="MCU Debugger" superClass="com.crt.advproject.tool.debug.debug">\r
+ <option id="com.crt.advproject.linkserver.debug.prevent.debug.1251553097" name="Prevent Debugging" superClass="com.crt.advproject.linkserver.debug.prevent.debug" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.miscellaneous.end_of_heap.586705874" name="Last used address of the heap" superClass="com.crt.advproject.miscellaneous.end_of_heap" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.miscellaneous.pvHeapStart.24161347" name="First address of the heap" superClass="com.crt.advproject.miscellaneous.pvHeapStart" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.miscellaneous.pvHeapLimit.1198762046" name="Maximum extent of heap" superClass="com.crt.advproject.miscellaneous.pvHeapLimit" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.debugger.security.nonsecureimageenable.526210663" name="Enable pre-programming of Non-Secure Image" superClass="com.crt.advproject.debugger.security.nonsecureimageenable" useByScannerDiscovery="false"/>\r
+ <option id="com.crt.advproject.debugger.security.nonsecureimage.1974267144" name="Non-Secure Project" superClass="com.crt.advproject.debugger.security.nonsecureimage" useByScannerDiscovery="false"/>\r
+ </tool>\r
+ </toolChain>\r
+ </folderInfo>\r
+ </configuration>\r
+ </storageModule>\r
+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>\r
+ </cconfiguration>\r
+ </storageModule>\r
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
+ <project id="FreeRTOSDemo.null.1072149409" name="FreeRTOSDemo" projectType="com.crt.advproject.projecttype.exe"/>\r
+ </storageModule>\r
+ <storageModule moduleId="scannerConfiguration">\r
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>\r
+ <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.debug.1736457840;com.crt.advproject.config.exe.debug.1736457840.;com.crt.advproject.gas.exe.debug.232366964;com.crt.advproject.assembler.input.1598241085">\r
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>\r
+ </scannerConfigBuildInfo>\r
+ <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.debug.1736457840;com.crt.advproject.config.exe.debug.1736457840.;com.crt.advproject.gcc.exe.debug.1970139153;com.crt.advproject.compiler.input.376371565">\r
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>\r
+ </scannerConfigBuildInfo>\r
+ <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1833812586;com.crt.advproject.config.exe.release.1833812586.;com.crt.advproject.gas.exe.release.1656888725;com.crt.advproject.assembler.input.1464252272">\r
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>\r
+ </scannerConfigBuildInfo>\r
+ <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1833812586;com.crt.advproject.config.exe.release.1833812586.;com.crt.advproject.gcc.exe.release.1615587634;com.crt.advproject.compiler.input.254355885">\r
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>\r
+ </scannerConfigBuildInfo>\r
+ </storageModule>\r
+ <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>\r
+ <storageModule moduleId="com.nxp.mcuxpresso.core.datamodels">\r
+ <sdkName>SDK_2.x_LPC54018-IoT-Module</sdkName>\r
+ <sdkExample>lpc54018iotmodule_freertos_hello</sdkExample>\r
+ <sdkVersion>2.7.0</sdkVersion>\r
+ <sdkComponents>platform.drivers.clock.LPC54018;platform.drivers.power.LPC54018;platform.drivers.common.LPC54018;device.LPC54018_CMSIS.LPC54018;platform.Include_core_cm4.LPC54018;platform.Include_common.LPC54018;platform.Include_dsp.LPC54018;platform.drivers.reset.LPC54018;middleware.amazon_freertos-kernel.heap_4.LPC54018;middleware.amazon_freertos-kernel.LPC54018;middleware.amazon_freertos-kernel.extension.LPC54018;utility.debug_console.LPC54018;component.serial_manager.LPC54018;component.lists.LPC54018;component.usart_adapter.LPC54018;platform.drivers.flexcomm_usart.LPC54018;platform.drivers.flexcomm.LPC54018;component.serial_manager_uart.LPC54018;device.LPC54018_startup.LPC54018;platform.drivers.lpc_iocon.LPC54018;platform.drivers.lpc_gpio.LPC54018;platform.drivers.emc.LPC54018;platform.utilities.assert.LPC54018;platform.utilities.misc_utilities.LPC54018;lpc54018iotmodule_freertos_hello;</sdkComponents>\r
+ <boardId>lpc54018iotmodule</boardId>\r
+ <package>LPC54018JET180</package>\r
+ <core>cm4</core>\r
+ <coreId>core0_LPC54018</coreId>\r
+ </storageModule>\r
+ <storageModule moduleId="com.crt.config">\r
+ <projectStorage><?xml version="1.0" encoding="UTF-8"?> \r
+<TargetConfig> \r
+<Properties property_3="NXP" property_4="LPC54018" property_count="5" version="100300"/> \r
+<infoList vendor="NXP"> \r
+<info chip="LPC54018" name="LPC54018"> \r
+<chip> \r
+<name>LPC54018</name> \r
+<family>LPC540xx</family> \r
+<vendor>NXP</vendor> \r
+<memory can_program="true" id="Flash" is_ro="true" size="0" type="Flash"/> \r
+<memory id="RAM" size="352" type="RAM"/> \r
+<memoryInstance derived_from="Flash" driver="LPC540xx_SPIFI_SFDP.cfx" edited="true" id="BOARD_FLASH" location="0x10000000" size="0x1000000"/> \r
+<memoryInstance derived_from="RAM" edited="true" id="SRAMX" location="0x0" size="0x30000"/> \r
+<memoryInstance derived_from="RAM" edited="true" id="SRAM_0_1_2_3" location="0x20000000" size="0x28000"/> \r
+<memoryInstance derived_from="RAM" edited="true" id="USB_RAM" location="0x40100000" size="0x2000"/> \r
+</chip> \r
+<processor> \r
+<name gcc_name="cortex-m4">Cortex-M4</name> \r
+<family>Cortex-M</family> \r
+</processor> \r
+</info> \r
+</infoList> \r
+</TargetConfig></projectStorage>\r
+ </storageModule>\r
+ <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>\r
+ <storageModule moduleId="refreshScope"/>\r
+</cproject>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<projectDescription>\r
+ <name>FreeRTOSDemo</name>\r
+ <comment></comment>\r
+ <projects>\r
+ </projects>\r
+ <buildSpec>\r
+ <buildCommand>\r
+ <name>org.eclipse.xtext.ui.shared.xtextBuilder</name>\r
+ <arguments>\r
+ </arguments>\r
+ </buildCommand>\r
+ <buildCommand>\r
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>\r
+ <triggers>clean,full,incremental,</triggers>\r
+ <arguments>\r
+ </arguments>\r
+ </buildCommand>\r
+ <buildCommand>\r
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>\r
+ <triggers>full,incremental,</triggers>\r
+ <arguments>\r
+ </arguments>\r
+ </buildCommand>\r
+ </buildSpec>\r
+ <natures>\r
+ <nature>org.eclipse.cdt.core.cnature</nature>\r
+ <nature>com.nxp.mcuxpresso.core.datamodels.sdkNature</nature>\r
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\r
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>\r
+ <nature>org.eclipse.xtext.ui.shared.xtextNature</nature>\r
+ </natures>\r
+ <linkedResources>\r
+ <link>\r
+ <name>Config</name>\r
+ <type>2</type>\r
+ <locationURI>PARENT-2-PROJECT_LOC/Config</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Demo</name>\r
+ <type>2</type>\r
+ <locationURI>PARENT-2-PROJECT_LOC/Demo</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS</name>\r
+ <type>2</type>\r
+ <locationURI>PARENT-4-PROJECT_LOC/Source</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>NXP_Code</name>\r
+ <type>2</type>\r
+ <locationURI>PARENT-2-PROJECT_LOC/NXP_Code</locationURI>\r
+ </link>\r
+ </linkedResources>\r
+ <filteredResources>\r
+ <filter>\r
+ <id>1578832143838</id>\r
+ <name>FreeRTOS/portable</name>\r
+ <type>9</type>\r
+ <matcher>\r
+ <id>org.eclipse.ui.ide.multiFilter</id>\r
+ <arguments>1.0-name-matches-false-false-GCC</arguments>\r
+ </matcher>\r
+ </filter>\r
+ <filter>\r
+ <id>1578832143844</id>\r
+ <name>FreeRTOS/portable</name>\r
+ <type>9</type>\r
+ <matcher>\r
+ <id>org.eclipse.ui.ide.multiFilter</id>\r
+ <arguments>1.0-name-matches-false-false-MemMang</arguments>\r
+ </matcher>\r
+ </filter>\r
+ <filter>\r
+ <id>1578832143849</id>\r
+ <name>FreeRTOS/portable</name>\r
+ <type>9</type>\r
+ <matcher>\r
+ <id>org.eclipse.ui.ide.multiFilter</id>\r
+ <arguments>1.0-name-matches-false-false-Common</arguments>\r
+ </matcher>\r
+ </filter>\r
+ <filter>\r
+ <id>1578832168749</id>\r
+ <name>FreeRTOS/portable/GCC</name>\r
+ <type>9</type>\r
+ <matcher>\r
+ <id>org.eclipse.ui.ide.multiFilter</id>\r
+ <arguments>1.0-name-matches-false-false-ARM_CM4_MPU</arguments>\r
+ </matcher>\r
+ </filter>\r
+ <filter>\r
+ <id>1578832213951</id>\r
+ <name>FreeRTOS/portable/MemMang</name>\r
+ <type>5</type>\r
+ <matcher>\r
+ <id>org.eclipse.ui.ide.multiFilter</id>\r
+ <arguments>1.0-name-matches-false-false-heap_4.c</arguments>\r
+ </matcher>\r
+ </filter>\r
+ </filteredResources>\r
+</projectDescription>\r
--- /dev/null
+GROUP (\r
+ "libcr_semihost_nf.a"\r
+ "libcr_c.a"\r
+ "libcr_eabihelpers.a"\r
+ "libgcc.a"\r
+)\r
+\r
+/*\r
+ * LPC54018 does not execute from Flash but from RAM (SRAMX). As a result, the\r
+ * MPU needs to be programmed to set the portion of SRAMX containing kernel\r
+ * code as privileged Read Only and the portion of SRAMX containing remaining\r
+ * of the code as Read Only. To facilitate this, SRAMX is divided into two\r
+ * parts:\r
+ * 1. SRAMX_CODE - 128KB. Contains code.\r
+ * 2. SRAMX_DATA - 64 KB. Contains data (only stack and heap as of now).\r
+ *\r
+ * SRAM_0_1_2_3 is of size 160 KB which is not a power of 2. ARM v7 MPU requires\r
+ * the size of an MPU region to be a power of two. Since FreeRTOS Cortex M4 MPU\r
+ * port programs MPU to grant access to all SRAM (for tasks created using\r
+ * xTaskCreate), we need to ensure that the size of SRAM region is a power of\r
+ * two. This is why SRAM_0_1_2_3 is divided into two parts:\r
+ * 1. SRAM_0_1_2_3 - 128 KB. Contains data. Since the size is now a power\r
+ * of two, an MPU region can be used to grant access to it.\r
+ * 2. SRAM_0_1_2_3_UNUSED - 32 KB. Unused.\r
+ */\r
+MEMORY\r
+{\r
+ /* Define each memory region. */\r
+ BOARD_FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x1000000 /* 16M bytes (alias Flash). */\r
+ SRAMX_CODE (rwx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K bytes. */\r
+ SRAMX_DATA (rwx) : ORIGIN = 0x20000, LENGTH = 0x10000 /* 64K bytes (alias RAM). */\r
+ SRAM_0_1_2_3 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x20000 /* 128K bytes (alias RAM2). */\r
+ SRAM_0_1_2_3_UNUSED (rwx) : ORIGIN = 0x20020000, LENGTH = 0x8000 /* 32K bytes. */\r
+ USB_RAM (rwx) : ORIGIN = 0x40100000, LENGTH = 0x2000 /* 8K bytes (alias RAM3). */\r
+}\r
+\r
+/* Initial 32K SRAMX_CODE is used to store kernel functions and\r
+ * initial 512 bytes of SRAM_0_1_2_3 is used to store kernel data. */\r
+__privileged_functions_region_size__ = 32K;\r
+__privileged_data_region_size__ = 512;\r
+\r
+/* Symbols needed by the MPU setup code. */\r
+__FLASH_segment_start__ = ORIGIN( SRAMX_CODE );\r
+__FLASH_segment_end__ = __FLASH_segment_start__ + LENGTH( SRAMX_CODE );\r
+__SRAM_segment_start__ = ORIGIN( SRAM_0_1_2_3 );\r
+__SRAM_segment_end__ = __SRAM_segment_start__ + LENGTH( SRAM_0_1_2_3 );\r
+\r
+/* Entry point. */\r
+ENTRY(ResetISR)\r
+\r
+/* Sections. */\r
+SECTIONS\r
+{\r
+ /* The startup code and FreeRTOS kernel code are placed at the beginning\r
+ * of SRAMX_CODE. */\r
+ .privileged_functions : ALIGN(4)\r
+ {\r
+ FILL(0xff)\r
+ __vectors_start__ = ABSOLUTE(.);\r
+ __FLASH_segment_start__ = __vectors_start__;\r
+ __privileged_functions_start__ = __vectors_start__;\r
+ KEEP(*(.isr_vector))\r
+\r
+ /* Global Section Table. */\r
+ . = ALIGN(4);\r
+ __section_table_start = .;\r
+\r
+ __data_section_table = .;\r
+ LONG((LOADADDR(.data_RAM) - LOADADDR(.privileged_functions)) + ORIGIN(SRAMX_CODE));\r
+ LONG( ADDR(.data_RAM));\r
+ LONG( SIZEOF(.data_RAM));\r
+\r
+ LONG((LOADADDR(.data) - LOADADDR(.privileged_functions)) + ORIGIN(SRAMX_CODE));\r
+ LONG( ADDR(.data));\r
+ LONG( SIZEOF(.data));\r
+\r
+ LONG((LOADADDR(.data_RAM3) - LOADADDR(.privileged_functions)) + ORIGIN(SRAMX_CODE));\r
+ LONG( ADDR(.data_RAM3));\r
+ LONG( SIZEOF(.data_RAM3));\r
+ __data_section_table_end = .;\r
+\r
+ __bss_section_table = .;\r
+ LONG( ADDR(.bss_RAM));\r
+ LONG( SIZEOF(.bss_RAM));\r
+\r
+ LONG( ADDR(.bss));\r
+ LONG( SIZEOF(.bss));\r
+\r
+ LONG( ADDR(.bss_RAM3));\r
+ LONG( SIZEOF(.bss_RAM3));\r
+ __bss_section_table_end = .;\r
+\r
+ __section_table_end = .;\r
+ /* End of Global Section Table. */\r
+\r
+ /* Functions placed after vector table. */\r
+ *(.after_vectors*)\r
+\r
+ /* Kernel code. */\r
+ *(privileged_functions)\r
+\r
+ FILL(0xDEAD);\r
+ /* Ensure that non-privileged code is placed after the region reserved for\r
+ * privileged kernel code. */\r
+ /* Note that dot (.) actually refers to the byte offset from the start of\r
+ * the current section (.privileged_functions in this case). As a result,\r
+ * setting dot (.) to a value sets the size of the section. */\r
+ . = __privileged_functions_region_size__;\r
+ __privileged_functions_end__ = .;\r
+ } > SRAMX_CODE AT> BOARD_FLASH\r
+\r
+ /* Text Section. */\r
+ .text : ALIGN(4)\r
+ {\r
+ /* Place the FreeRTOS System Calls first in the unprivileged region. */\r
+ __syscalls_flash_start__ = .;\r
+ *(freertos_system_calls)\r
+ __syscalls_flash_end__ = .;\r
+\r
+ /* Unprivileged code and RO data. */\r
+ *(.text*)\r
+ KEEP(*freertos*/tasks.o(.rodata*)) /* FreeRTOS Debug Config. */\r
+ *(.rodata .rodata.* .constdata .constdata.*)\r
+ . = ALIGN(4);\r
+ } > SRAMX_CODE AT> BOARD_FLASH\r
+\r
+ /* For exception handling/unwind - some Newlib functions (in common\r
+ * with C++ and STDC++) use this. */\r
+ .ARM.extab : ALIGN(4)\r
+ {\r
+ *(.ARM.extab* .gnu.linkonce.armextab.*)\r
+ } > SRAMX_CODE AT> BOARD_FLASH\r
+\r
+ __exidx_start = .;\r
+\r
+ .ARM.exidx : ALIGN(4)\r
+ {\r
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r
+ } > SRAMX_CODE AT> BOARD_FLASH\r
+\r
+ __exidx_end = .;\r
+\r
+ /* End of text section. */\r
+ _etext = .;\r
+\r
+ /* USB_RAM. */\r
+ .m_usb_data (NOLOAD) :\r
+ {\r
+ *(m_usb_global)\r
+ } > USB_RAM AT> USB_RAM\r
+\r
+ /* Data section for SRAMX_DATA. */\r
+ .data_RAM : ALIGN(4)\r
+ {\r
+ FILL(0xff)\r
+ PROVIDE(__start_data_RAM = .);\r
+ PROVIDE(__start_data_SRAMX_DATA = .);\r
+ *(.ramfunc.$RAM)\r
+ *(.ramfunc.$SRAMX)\r
+ *(.data.$RAM)\r
+ *(.data.$SRAMX)\r
+ *(.data.$RAM.*)\r
+ *(.data.$SRAMX.*)\r
+ . = ALIGN(4);\r
+ PROVIDE(__end_data_RAM = .);\r
+ PROVIDE(__end_data_SRAMX_DATA = .);\r
+ } > SRAMX_DATA AT>BOARD_FLASH\r
+\r
+ /* Data section for USB_RAM. */\r
+ .data_RAM3 : ALIGN(4)\r
+ {\r
+ FILL(0xff)\r
+ PROVIDE(__start_data_RAM3 = .);\r
+ PROVIDE(__start_data_USB_RAM = .);\r
+ *(.ramfunc.$RAM3)\r
+ *(.ramfunc.$USB_RAM)\r
+ *(.data.$RAM3)\r
+ *(.data.$USB_RAM)\r
+ *(.data.$RAM3.*)\r
+ *(.data.$USB_RAM.*)\r
+ . = ALIGN(4);\r
+ PROVIDE(__end_data_RAM3 = .);\r
+ PROVIDE(__end_data_USB_RAM = .);\r
+ } > USB_RAM AT>BOARD_FLASH\r
+\r
+ /* Main Data Section - Reserved. */\r
+ .uninit_RESERVED (NOLOAD) : ALIGN(4)\r
+ {\r
+ _start_uninit_RESERVED = .;\r
+ __privileged_data_start__ = _start_uninit_RESERVED;\r
+\r
+ KEEP(*(.bss.$RESERVED*))\r
+ . = ALIGN(4);\r
+\r
+ _end_uninit_RESERVED = .;\r
+ } > SRAM_0_1_2_3 AT> SRAM_0_1_2_3\r
+\r
+ /* Main DATA section (SRAM_0_1_2_3). */\r
+ .data : ALIGN(4)\r
+ {\r
+ _data = .;\r
+ PROVIDE(__start_data_RAM2 = .);\r
+ PROVIDE(__start_data_SRAM_0_1_2_3 = .);\r
+\r
+ /* FreeRTOS kernel data. */\r
+ *(privileged_data)\r
+ FILL(0xDEAD);\r
+ /* Ensure that non-privileged data is placed after the region reserved for\r
+ * privileged kernel data. */\r
+ /* Note that dot (.) actually refers to the byte offset from the start of\r
+ * the current section (.data in this case). As a result, setting\r
+ * dot (.) to a value extends the size of the section. */\r
+ . = __privileged_data_region_size__;\r
+ __privileged_data_end__ = .;\r
+\r
+ FILL(0xff)\r
+ *(vtable)\r
+ *(.ramfunc*)\r
+ KEEP(*(CodeQuickAccess))\r
+ KEEP(*(DataQuickAccess))\r
+ *(RamFunction)\r
+ *(.data*)\r
+ . = ALIGN(4);\r
+ _edata = .;\r
+ PROVIDE(__end_data_RAM2 = .);\r
+ PROVIDE(__end_data_SRAM_0_1_2_3 = .);\r
+ } > SRAM_0_1_2_3 AT>BOARD_FLASH\r
+\r
+ /* BSS section for SRAMX_DATA. */\r
+ .bss_RAM : ALIGN(4)\r
+ {\r
+ PROVIDE(__start_bss_RAM = .);\r
+ PROVIDE(__start_bss_SRAMX_DATA = .);\r
+ *(.bss.$RAM)\r
+ *(.bss.$SRAMX)\r
+ *(.bss.$RAM.*)\r
+ *(.bss.$SRAMX.*)\r
+ . = ALIGN (. != 0 ? 4 : 1); /* Avoid empty segment. */\r
+ PROVIDE(__end_bss_RAM = .);\r
+ PROVIDE(__end_bss_SRAMX_DATA = .);\r
+ } > SRAMX_DATA AT> SRAMX_DATA\r
+\r
+ /* BSS section for USB_RAM. */\r
+ .bss_RAM3 : ALIGN(4)\r
+ {\r
+ PROVIDE(__start_bss_RAM3 = .);\r
+ PROVIDE(__start_bss_USB_RAM = .);\r
+ *(.bss.$RAM3)\r
+ *(.bss.$USB_RAM)\r
+ *(.bss.$RAM3.*)\r
+ *(.bss.$USB_RAM.*)\r
+ . = ALIGN (. != 0 ? 4 : 1); /* Avoid empty segment. */\r
+ PROVIDE(__end_bss_RAM3 = .);\r
+ PROVIDE(__end_bss_USB_RAM = .);\r
+ } > USB_RAM AT> USB_RAM\r
+\r
+ /* Main BSS Section. */\r
+ .bss : ALIGN(4)\r
+ {\r
+ _bss = .;\r
+ PROVIDE(__start_bss_RAM2 = .);\r
+ PROVIDE(__start_bss_SRAM_0_1_2_3 = .);\r
+ *(.bss*)\r
+ *(COMMON)\r
+ . = ALIGN(4);\r
+ _ebss = .;\r
+ PROVIDE(__end_bss_RAM2 = .);\r
+ PROVIDE(__end_bss_SRAM_0_1_2_3 = .);\r
+ PROVIDE(end = .);\r
+ } > SRAM_0_1_2_3 AT> SRAM_0_1_2_3\r
+\r
+ /* NOINIT section for SRAMX_DATA. */\r
+ .noinit_RAM (NOLOAD) : ALIGN(4)\r
+ {\r
+ PROVIDE(__start_noinit_RAM = .);\r
+ PROVIDE(__start_noinit_SRAMX_DATA = .);\r
+ *(.noinit.$RAM)\r
+ *(.noinit.$SRAMX)\r
+ *(.noinit.$RAM.*)\r
+ *(.noinit.$SRAMX.*)\r
+ . = ALIGN(4);\r
+ PROVIDE(__end_noinit_RAM = .);\r
+ PROVIDE(__end_noinit_SRAMX_DATA = .);\r
+ } > SRAMX_DATA AT> SRAMX_DATA\r
+\r
+ /* NOINIT section for USB_RAM. */\r
+ .noinit_RAM3 (NOLOAD) : ALIGN(4)\r
+ {\r
+ PROVIDE(__start_noinit_RAM3 = .);\r
+ PROVIDE(__start_noinit_USB_RAM = .);\r
+ *(.noinit.$RAM3)\r
+ *(.noinit.$USB_RAM)\r
+ *(.noinit.$RAM3.*)\r
+ *(.noinit.$USB_RAM.*)\r
+ . = ALIGN(4);\r
+ PROVIDE(__end_noinit_RAM3 = .);\r
+ PROVIDE(__end_noinit_USB_RAM = .);\r
+ } > USB_RAM AT> USB_RAM\r
+\r
+ /* Default NOINIT Section. */\r
+ .noinit (NOLOAD): ALIGN(4)\r
+ {\r
+ _noinit = .;\r
+ PROVIDE(__start_noinit_RAM2 = .);\r
+ PROVIDE(__start_noinit_SRAM_0_1_2_3 = .);\r
+ *(.noinit*)\r
+ . = ALIGN(4);\r
+ _end_noinit = .;\r
+ PROVIDE(__end_noinit_RAM2 = .);\r
+ PROVIDE(__end_noinit_SRAM_0_1_2_3 = .);\r
+ } > SRAM_0_1_2_3 AT> SRAM_0_1_2_3\r
+\r
+ /* Reserve and place Heap within memory map. */\r
+ _HeapSize = 0x1000;\r
+ .heap : ALIGN(4)\r
+ {\r
+ _pvHeapStart = .;\r
+ . += _HeapSize;\r
+ . = ALIGN(4);\r
+ _pvHeapLimit = .;\r
+ } > SRAMX_DATA\r
+\r
+ /* Reserve space in memory for Stack. */\r
+ _StackSize = 0x1000;\r
+ .heap2stackfill :\r
+ {\r
+ . += _StackSize;\r
+ } > SRAMX_DATA\r
+\r
+ /* Locate actual Stack in memory map. */\r
+ .stack ORIGIN(SRAMX_DATA) + LENGTH(SRAMX_DATA) - _StackSize - 0: ALIGN(4)\r
+ {\r
+ _vStackBase = .;\r
+ . = ALIGN(4);\r
+ _vStackTop = . + _StackSize;\r
+ } > SRAMX_DATA\r
+\r
+ /* ## Create checksum value (used in startup). ## */\r
+ PROVIDE(__valid_user_code_checksum = 0 -\r
+ (_vStackTop\r
+ + (ResetISR + 1)\r
+ + (NMI_Handler + 1)\r
+ + (HardFault_Handler + 1)\r
+ + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined. */\r
+ + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined. */\r
+ + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined. */\r
+ ) );\r
+\r
+ /* Provide basic symbols giving location and size of main text\r
+ * block, including initial values of RW data sections. Note that\r
+ * these will need extending to give a complete picture with\r
+ * complex images (e.g multiple Flash banks). */\r
+ _image_start = LOADADDR(.privileged_functions);\r
+ _image_end = LOADADDR(.data) + SIZEOF(.data);\r
+ _image_size = _image_end - _image_start;\r
+\r
+ /* Provide symbols for LPC540xx parts for startup code to use\r
+ * to set image to be plain load image or XIP.\r
+ * Config : Plain load image = true. */\r
+ __imghdr_loadaddress = ADDR(.privileged_functions);\r
+ __imghdr_imagetype = 1;\r
+}
\ No newline at end of file
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/**\r
+ * @brief Mem fault handler.\r
+ */\r
+void MemManage_Handler( void ) __attribute__ (( naked ));\r
+/*-----------------------------------------------------------*/\r
+\r
+void MemManage_Handler( void )\r
+{\r
+ __asm volatile\r
+ (\r
+ " tst lr, #4 \n"\r
+ " ite eq \n"\r
+ " mrseq r0, msp \n"\r
+ " mrsne r0, psp \n"\r
+ " ldr r1, handler_address_const \n"\r
+ " bx r1 \n"\r
+ " \n"\r
+ " handler_address_const: .word vHandleMemoryFault \n"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+// ****************************************************************************
+// semihost_hardfault.c
+// - Provides hard fault handler to allow semihosting code not
+// to hang application when debugger not connected.
+//
+// ****************************************************************************
+// Copyright 2017-2020 NXP
+// All rights reserved.
+//
+// Software that is described herein is for illustrative purposes only
+// which provides customers with programming information regarding the
+// NXP Cortex-M based MCUs. This software is supplied "AS IS" without any
+// warranties of any kind, and NXP Semiconductors and its licensor disclaim any
+// and all warranties, express or implied, including all implied warranties of
+// merchantability, fitness for a particular purpose and non-infringement of
+// intellectual property rights. NXP Semiconductors assumes no responsibility
+// or liability for the use of the software, conveys no license or rights under
+// any patent, copyright, mask work right, or any other intellectual property
+// rights in or to any products. NXP Semiconductors reserves the right to make
+// changes in the software without notification. NXP Semiconductors also makes
+// no representation or warranty that such application will be suitable for the
+// specified use without further testing or modification.
+//
+// Permission to use, copy, modify, and distribute this software and its
+// documentation is hereby granted, under NXP Semiconductors' and its
+// licensor's relevant copyrights in the software, without fee, provided that it
+// is used in conjunction with NXP Semiconductors microcontrollers. This
+// copyright, permission, and disclaimer notice must appear in all copies of
+// this code.
+// ****************************************************************************
+//
+// ===== DESCRIPTION =====
+//
+// One of the issues with applications that make use of semihosting operations
+// (such as printf calls) is that the code will not execute correctly when the
+// debugger is not connected. Generally this will show up with the application
+// appearing to just hang. This may include the application running from reset
+// or powering up the board (with the application already in FLASH), and also
+// as the application failing to continue to execute after a debug session is
+// terminated.
+//
+// The problem here is that the "bottom layer" of the semihosted variants of
+// the C library, semihosting is implemented by a "BKPT 0xAB" instruction.
+// When the debug tools are not connected, this instruction triggers a hard
+// fault - and the default hard fault handler within an application will
+// typically just contains an infinite loop - causing the application to
+// appear to have hang when no debugger is connected.
+//
+// The below code provides an example hard fault handler which instead looks
+// to see what the instruction that caused the hard fault was - and if it
+// was a "BKPT 0xAB", then it instead returns back to the user application.
+//
+// In most cases this will allow applications containing semihosting
+// operations to execute (to some degree) when the debugger is not connected.
+//
+// == NOTE ==
+//
+// Correct execution of the application containing semihosted operations
+// which are vectored onto this hard fault handler cannot be guaranteed. This
+// is because the handler may not return data or return codes that the higher
+// level C library code or application code expects. This hard fault handler
+// is meant as a development aid, and it is not recommended to leave
+// semihosted code in a production build of your application!
+//
+// ****************************************************************************
+
+// Allow handler to be removed by setting a define (via command line)
+#if !defined (__SEMIHOST_HARDFAULT_DISABLE)
+
+__attribute__((naked))
+void HardFault_Handler(void){
+ __asm( ".syntax unified\n"
+ // Check which stack is in use
+ "MOVS R0, #4 \n"
+ "MOV R1, LR \n"
+ "TST R0, R1 \n"
+ "BEQ _MSP \n"
+ "MRS R0, PSP \n"
+ "B _process \n"
+ "_MSP: \n"
+ "MRS R0, MSP \n"
+ // Load the instruction that triggered hard fault
+ "_process: \n"
+ "LDR R1,[R0,#24] \n"
+ "LDRH R2,[r1] \n"
+ // Semihosting instruction is "BKPT 0xAB" (0xBEAB)
+ "LDR R3,=0xBEAB \n"
+ "CMP R2,R3 \n"
+ "BEQ _semihost_return \n"
+ // Wasn't semihosting instruction so enter infinite loop
+ "B . \n"
+ // Was semihosting instruction, so adjust location to
+ // return to by 1 instruction (2 bytes), then exit function
+ "_semihost_return: \n"
+ "ADDS R1,#2 \n"
+ "STR R1,[R0,#24] \n"
+ // Set a return value from semihosting operation.
+ // 32 is slightly arbitrary, but appears to allow most
+ // C Library IO functions sitting on top of semihosting to
+ // continue to operate to some degree
+ "MOVS R1,#32 \n"
+ "STR R1,[ R0,#0 ] \n" // R0 is at location 0 on stack
+ // Return from hard fault handler to application
+ "BX LR \n"
+ ".syntax divided\n") ;
+}
+
+#endif
+
--- /dev/null
+//*****************************************************************************\r
+// LPC54018 startup code for use with MCUXpresso IDE\r
+//\r
+// Version : 101019\r
+//*****************************************************************************\r
+//\r
+// Copyright 2016-2019 NXP\r
+// All rights reserved.\r
+//\r
+// SPDX-License-Identifier: BSD-3-Clause\r
+//*****************************************************************************\r
+\r
+#if defined (DEBUG)\r
+#pragma GCC push_options\r
+#pragma GCC optimize ("Og")\r
+#endif // (DEBUG)\r
+\r
+#if defined (__cplusplus)\r
+#ifdef __REDLIB__\r
+#error Redlib does not support C++\r
+#else\r
+//*****************************************************************************\r
+//\r
+// The entry point for the C++ library startup\r
+//\r
+//*****************************************************************************\r
+extern "C" {\r
+ extern void __libc_init_array(void);\r
+}\r
+#endif\r
+#endif\r
+\r
+#define WEAK __attribute__ ((weak))\r
+#define WEAK_AV __attribute__ ((weak, section(".after_vectors")))\r
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))\r
+\r
+//*****************************************************************************\r
+#if defined (__cplusplus)\r
+extern "C" {\r
+#endif\r
+\r
+//*****************************************************************************\r
+// Variable to store CRP value in. Will be placed automatically\r
+// by the linker when "Enable Code Read Protect" selected.\r
+// See crp.h header for more information\r
+//*****************************************************************************\r
+#include <NXP/crp.h>\r
+__CRP const unsigned int CRP_WORD = CRP_NO_CRP ;\r
+\r
+//*****************************************************************************\r
+// Declaration of external SystemInit function\r
+//*****************************************************************************\r
+#if defined (__USE_CMSIS)\r
+extern void SystemInit(void);\r
+#endif // (__USE_CMSIS)\r
+\r
+//*****************************************************************************\r
+// Forward declaration of the core exception handlers.\r
+// When the application defines a handler (with the same name), this will\r
+// automatically take precedence over these weak definitions.\r
+// If your application is a C++ one, then any interrupt handlers defined\r
+// in C++ files within in your main application will need to have C linkage\r
+// rather than C++ linkage. To do this, make sure that you are using extern "C"\r
+// { .... } around the interrupt handler within your main application code.\r
+//*****************************************************************************\r
+ void ResetISR(void);\r
+WEAK void NMI_Handler(void);\r
+WEAK void HardFault_Handler(void);\r
+WEAK void MemManage_Handler(void);\r
+WEAK void BusFault_Handler(void);\r
+WEAK void UsageFault_Handler(void);\r
+WEAK void SVC_Handler(void);\r
+WEAK void DebugMon_Handler(void);\r
+WEAK void PendSV_Handler(void);\r
+WEAK void SysTick_Handler(void);\r
+WEAK void IntDefaultHandler(void);\r
+\r
+//*****************************************************************************\r
+// Forward declaration of the application IRQ handlers. When the application\r
+// defines a handler (with the same name), this will automatically take\r
+// precedence over weak definitions below\r
+//*****************************************************************************\r
+WEAK void WDT_BOD_IRQHandler(void);\r
+WEAK void DMA0_IRQHandler(void);\r
+WEAK void GINT0_IRQHandler(void);\r
+WEAK void GINT1_IRQHandler(void);\r
+WEAK void PIN_INT0_IRQHandler(void);\r
+WEAK void PIN_INT1_IRQHandler(void);\r
+WEAK void PIN_INT2_IRQHandler(void);\r
+WEAK void PIN_INT3_IRQHandler(void);\r
+WEAK void UTICK0_IRQHandler(void);\r
+WEAK void MRT0_IRQHandler(void);\r
+WEAK void CTIMER0_IRQHandler(void);\r
+WEAK void CTIMER1_IRQHandler(void);\r
+WEAK void SCT0_IRQHandler(void);\r
+WEAK void CTIMER3_IRQHandler(void);\r
+WEAK void FLEXCOMM0_IRQHandler(void);\r
+WEAK void FLEXCOMM1_IRQHandler(void);\r
+WEAK void FLEXCOMM2_IRQHandler(void);\r
+WEAK void FLEXCOMM3_IRQHandler(void);\r
+WEAK void FLEXCOMM4_IRQHandler(void);\r
+WEAK void FLEXCOMM5_IRQHandler(void);\r
+WEAK void FLEXCOMM6_IRQHandler(void);\r
+WEAK void FLEXCOMM7_IRQHandler(void);\r
+WEAK void ADC0_SEQA_IRQHandler(void);\r
+WEAK void ADC0_SEQB_IRQHandler(void);\r
+WEAK void ADC0_THCMP_IRQHandler(void);\r
+WEAK void DMIC0_IRQHandler(void);\r
+WEAK void HWVAD0_IRQHandler(void);\r
+WEAK void USB0_NEEDCLK_IRQHandler(void);\r
+WEAK void USB0_IRQHandler(void);\r
+WEAK void RTC_IRQHandler(void);\r
+WEAK void FLEXCOMM10_IRQHandler(void);\r
+WEAK void Reserved47_IRQHandler(void);\r
+WEAK void PIN_INT4_IRQHandler(void);\r
+WEAK void PIN_INT5_IRQHandler(void);\r
+WEAK void PIN_INT6_IRQHandler(void);\r
+WEAK void PIN_INT7_IRQHandler(void);\r
+WEAK void CTIMER2_IRQHandler(void);\r
+WEAK void CTIMER4_IRQHandler(void);\r
+WEAK void RIT_IRQHandler(void);\r
+WEAK void SPIFI0_IRQHandler(void);\r
+WEAK void FLEXCOMM8_IRQHandler(void);\r
+WEAK void FLEXCOMM9_IRQHandler(void);\r
+WEAK void SDIO_IRQHandler(void);\r
+WEAK void CAN0_IRQ0_IRQHandler(void);\r
+WEAK void CAN0_IRQ1_IRQHandler(void);\r
+WEAK void CAN1_IRQ0_IRQHandler(void);\r
+WEAK void CAN1_IRQ1_IRQHandler(void);\r
+WEAK void USB1_IRQHandler(void);\r
+WEAK void USB1_NEEDCLK_IRQHandler(void);\r
+WEAK void ETHERNET_IRQHandler(void);\r
+WEAK void ETHERNET_PMT_IRQHandler(void);\r
+WEAK void ETHERNET_MACLP_IRQHandler(void);\r
+WEAK void Reserved68_IRQHandler(void);\r
+WEAK void LCD_IRQHandler(void);\r
+WEAK void SHA_IRQHandler(void);\r
+WEAK void SMARTCARD0_IRQHandler(void);\r
+WEAK void SMARTCARD1_IRQHandler(void);\r
+\r
+//*****************************************************************************\r
+// Forward declaration of the driver IRQ handlers. These are aliased\r
+// to the IntDefaultHandler, which is a 'forever' loop. When the driver\r
+// defines a handler (with the same name), this will automatically take\r
+// precedence over these weak definitions\r
+//*****************************************************************************\r
+void WDT_BOD_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void DMA0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void GINT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void GINT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void PIN_INT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void PIN_INT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void PIN_INT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void PIN_INT3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void UTICK0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void MRT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void CTIMER0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void CTIMER1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void SCT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void CTIMER3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void FLEXCOMM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void FLEXCOMM1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void FLEXCOMM2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void FLEXCOMM3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void FLEXCOMM4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void FLEXCOMM5_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void FLEXCOMM6_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void FLEXCOMM7_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void ADC0_SEQA_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void ADC0_SEQB_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void ADC0_THCMP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void DMIC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void HWVAD0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void USB0_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void USB0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void RTC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void FLEXCOMM10_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void Reserved47_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void PIN_INT4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void PIN_INT5_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void PIN_INT6_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void PIN_INT7_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void CTIMER2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void CTIMER4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void RIT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void SPIFI0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void FLEXCOMM8_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void FLEXCOMM9_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void SDIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void CAN0_IRQ0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void CAN0_IRQ1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void CAN1_IRQ0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void CAN1_IRQ1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void USB1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void USB1_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void ETHERNET_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void ETHERNET_PMT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void ETHERNET_MACLP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void Reserved68_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void LCD_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void SHA_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void SMARTCARD0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void SMARTCARD1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+\r
+//*****************************************************************************\r
+// The entry point for the application.\r
+// __main() is the entry point for Redlib based applications\r
+// main() is the entry point for Newlib based applications\r
+//*****************************************************************************\r
+#if defined (__REDLIB__)\r
+extern void __main(void);\r
+#endif\r
+extern int main(void);\r
+\r
+//*****************************************************************************\r
+// External declaration for the pointer to the stack top from the Linker Script\r
+//*****************************************************************************\r
+extern void _vStackTop(void);\r
+extern void _image_size(void);\r
+//*****************************************************************************\r
+// External declaration for LPC MCU vector table checksum from Linker Script\r
+//*****************************************************************************\r
+WEAK extern void __valid_user_code_checksum();\r
+\r
+//*****************************************************************************\r
+// External declaration for image type and load address from Linker Script\r
+//*****************************************************************************\r
+WEAK extern void __imghdr_loadaddress();\r
+WEAK extern void __imghdr_imagetype();\r
+\r
+//*****************************************************************************\r
+#if defined (__cplusplus)\r
+} // extern "C"\r
+#endif\r
+#ifndef IMG_BAUDRATE\r
+#define IMG_BAUDRATE 0\r
+#endif\r
+//*****************************************************************************\r
+// The vector table.\r
+// This relies on the linker script to place at correct location in memory.\r
+//*****************************************************************************\r
+extern void (* const g_pfnVectors[])(void);\r
+extern void * __Vectors __attribute__ ((alias ("g_pfnVectors")));\r
+\r
+__attribute__ ((used, section(".isr_vector")))\r
+void (* const g_pfnVectors[])(void) = {\r
+ // Core Level - CM4\r
+ &_vStackTop, // The initial stack pointer\r
+ ResetISR, // The reset handler\r
+ NMI_Handler, // The NMI handler\r
+ HardFault_Handler, // The hard fault handler\r
+ MemManage_Handler, // The MPU fault handler\r
+ BusFault_Handler, // The bus fault handler\r
+ UsageFault_Handler, // The usage fault handler\r
+ __valid_user_code_checksum, // LPC MCU checksum\r
+ 0, // ECRP\r
+ (void (*)(void))0xEDDC94BD, // Reserved\r
+ (void (*)(void))0x160, // Reserved\r
+ SVC_Handler, // SVCall handler\r
+ DebugMon_Handler, // Debug monitor handler\r
+ 0, // Reserved\r
+ PendSV_Handler, // The PendSV handler\r
+ SysTick_Handler, // The SysTick handler\r
+\r
+ // Chip Level - LPC54018\r
+ WDT_BOD_IRQHandler, // 16: Windowed watchdog timer, Brownout detect\r
+ DMA0_IRQHandler, // 17: DMA controller\r
+ GINT0_IRQHandler, // 18: GPIO group 0\r
+ GINT1_IRQHandler, // 19: GPIO group 1\r
+ PIN_INT0_IRQHandler, // 20: Pin interrupt 0 or pattern match engine slice 0\r
+ PIN_INT1_IRQHandler, // 21: Pin interrupt 1or pattern match engine slice 1\r
+ PIN_INT2_IRQHandler, // 22: Pin interrupt 2 or pattern match engine slice 2\r
+ PIN_INT3_IRQHandler, // 23: Pin interrupt 3 or pattern match engine slice 3\r
+ UTICK0_IRQHandler, // 24: Micro-tick Timer\r
+ MRT0_IRQHandler, // 25: Multi-rate timer\r
+ CTIMER0_IRQHandler, // 26: Standard counter/timer CTIMER0\r
+ CTIMER1_IRQHandler, // 27: Standard counter/timer CTIMER1\r
+ SCT0_IRQHandler, // 28: SCTimer/PWM\r
+ CTIMER3_IRQHandler, // 29: Standard counter/timer CTIMER3\r
+ FLEXCOMM0_IRQHandler, // 30: Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM)\r
+ FLEXCOMM1_IRQHandler, // 31: Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM)\r
+ FLEXCOMM2_IRQHandler, // 32: Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM)\r
+ FLEXCOMM3_IRQHandler, // 33: Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM)\r
+ FLEXCOMM4_IRQHandler, // 34: Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM)\r
+ FLEXCOMM5_IRQHandler, // 35: Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM)\r
+ FLEXCOMM6_IRQHandler, // 36: Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM)\r
+ FLEXCOMM7_IRQHandler, // 37: Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM)\r
+ ADC0_SEQA_IRQHandler, // 38: ADC0 sequence A completion.\r
+ ADC0_SEQB_IRQHandler, // 39: ADC0 sequence B completion.\r
+ ADC0_THCMP_IRQHandler, // 40: ADC0 threshold compare and error.\r
+ DMIC0_IRQHandler, // 41: Digital microphone and DMIC subsystem\r
+ HWVAD0_IRQHandler, // 42: Hardware Voice Activity Detector\r
+ USB0_NEEDCLK_IRQHandler, // 43: USB Activity Wake-up Interrupt\r
+ USB0_IRQHandler, // 44: USB device\r
+ RTC_IRQHandler, // 45: RTC alarm and wake-up interrupts\r
+ FLEXCOMM10_IRQHandler, // 46: Flexcomm Interface 10 (SPI, FLEXCOMM)\r
+ Reserved47_IRQHandler, // 47: Reserved interrupt\r
+ PIN_INT4_IRQHandler, // 48: Pin interrupt 4 or pattern match engine slice 4 int\r
+ PIN_INT5_IRQHandler, // 49: Pin interrupt 5 or pattern match engine slice 5 int\r
+ PIN_INT6_IRQHandler, // 50: Pin interrupt 6 or pattern match engine slice 6 int\r
+ PIN_INT7_IRQHandler, // 51: Pin interrupt 7 or pattern match engine slice 7 int\r
+ CTIMER2_IRQHandler, // 52: Standard counter/timer CTIMER2\r
+ CTIMER4_IRQHandler, // 53: Standard counter/timer CTIMER4\r
+ RIT_IRQHandler, // 54: Repetitive Interrupt Timer\r
+ SPIFI0_IRQHandler, // 55: SPI flash interface\r
+ FLEXCOMM8_IRQHandler, // 56: Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM)\r
+ FLEXCOMM9_IRQHandler, // 57: Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM)\r
+ SDIO_IRQHandler, // 58: SD/MMC\r
+ CAN0_IRQ0_IRQHandler, // 59: CAN0 interrupt0\r
+ CAN0_IRQ1_IRQHandler, // 60: CAN0 interrupt1\r
+ CAN1_IRQ0_IRQHandler, // 61: CAN1 interrupt0\r
+ CAN1_IRQ1_IRQHandler, // 62: CAN1 interrupt1\r
+ USB1_IRQHandler, // 63: USB1 interrupt\r
+ USB1_NEEDCLK_IRQHandler, // 64: USB1 activity\r
+ ETHERNET_IRQHandler, // 65: Ethernet\r
+ ETHERNET_PMT_IRQHandler, // 66: Ethernet power management interrupt\r
+ ETHERNET_MACLP_IRQHandler, // 67: Ethernet MAC interrupt\r
+ Reserved68_IRQHandler, // 68: Reserved interrupt\r
+ LCD_IRQHandler, // 69: LCD interrupt\r
+ SHA_IRQHandler, // 70: SHA interrupt\r
+ SMARTCARD0_IRQHandler, // 71: Smart card 0 interrupt\r
+ SMARTCARD1_IRQHandler, // 72: Smart card 1 interrupt\r
+\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ (void (*)(void))0xFEEDA5A5, // Header Marker\r
+\r
+#if defined (ADD_CRC)\r
+ (__imghdr_imagetype - 1), // (0x04) Image Type\r
+ __imghdr_loadaddress, // (0x08) Load_address\r
+#else\r
+ __imghdr_imagetype, // (0x04) Image Type\r
+ __imghdr_loadaddress, // (0x08) Load_address\r
+#endif\r
+ (void (*)(void))(((unsigned)_image_size) - 4), // (0x0C) load_length, exclude 4 bytes CRC field.\r
+ 0, // (0x10) CRC value (only applicable to NON Non-secure images).\r
+ 0, // (0x14) Version (only applicable to DUAL_ENH image type.\r
+ 0, // (0x18) EMC static memory configuration settings, required for EMC boot\r
+ (void (*)(void))IMG_BAUDRATE, // (0x1C) image baudrate\r
+ 0, // (0x20) reserved\r
+ (void (*)(void))0xEDDC94BD, // (0x24) Image_marker\r
+ 0, // (0x28) SBZ\r
+ 0, // (0x2C) reserved\r
+ #ifdef W25Q128JVFM\r
+ /* SPIFI Descriptor - W25Q128JVFM */\r
+ (void (*)(void))0x00000000, // 0xFFFFFFFF to default 1-bit SPI mode ；DevStrAdr\r
+ (void (*)(void))0x001870EF, // mfgId + extCount\r
+ (void (*)(void))0x00000000, // extid 0-3\r
+ (void (*)(void))0x00000000, // extid 4-7\r
+ (void (*)(void))0x0001001D, // caps\r
+ (void (*)(void))0x00000100, // Blks + RESV1\r
+ (void (*)(void))0x00010000, // blkSize\r
+ (void (*)(void))0x00000000, // subBlks + subBlkSize\r
+ (void (*)(void))0x00000100, // pageSize + RESV2\r
+ (void (*)(void))0x00003F00, // maxReadSize\r
+ (void (*)(void))0x68506850, // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate\r
+ (void (*)(void))0x04030050, // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId,\r
+ (void (*)(void))0x14110D09, // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId\r
+ #endif\r
+\r
+ #ifdef MXL12835F\r
+ /* SPI Descriptor - MXL12835F */\r
+ (void (*)(void))0x00000000, // 0xFFFFFFFF to default 1-bit SPI mode ;DevStrAdr\r
+ (void (*)(void))0x001820C2, // mfgId + extCount\r
+ (void (*)(void))0x00000000, // extid 0-3\r
+ (void (*)(void))0x00000000, // extid 4-7\r
+ (void (*)(void))0x0001001D, // caps\r
+ (void (*)(void))0x00000100, // Blks + RESV1\r
+ (void (*)(void))0x00010000, // blkSize\r
+ (void (*)(void))0x00000000, // subBlks + subBlkSize\r
+ (void (*)(void))0x00000100, // pageSize + RESV2\r
+ (void (*)(void))0x00003F00, // maxReadSize\r
+ (void (*)(void))0x68506850, // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate\r
+ (void (*)(void))0x06030050, // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId\r
+ (void (*)(void))0x14110F0B, // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId\r
+ #endif\r
+\r
+}; /* End of g_pfnVectors */\r
+\r
+//*****************************************************************************\r
+// Functions to carry out the initialization of RW and BSS data sections. These\r
+// are written as separate functions rather than being inlined within the\r
+// ResetISR() function in order to cope with MCUs with multiple banks of\r
+// memory.\r
+//*****************************************************************************\r
+__attribute__ ((section(".after_vectors.init_data")))\r
+void data_init(unsigned int romstart, unsigned int start, unsigned int len) {\r
+ unsigned int *pulDest = (unsigned int*) start;\r
+ unsigned int *pulSrc = (unsigned int*) romstart;\r
+ unsigned int loop;\r
+ for (loop = 0; loop < len; loop = loop + 4)\r
+ *pulDest++ = *pulSrc++;\r
+}\r
+\r
+__attribute__ ((section(".after_vectors.init_bss")))\r
+void bss_init(unsigned int start, unsigned int len) {\r
+ unsigned int *pulDest = (unsigned int*) start;\r
+ unsigned int loop;\r
+ for (loop = 0; loop < len; loop = loop + 4)\r
+ *pulDest++ = 0;\r
+}\r
+\r
+//*****************************************************************************\r
+// The following symbols are constructs generated by the linker, indicating\r
+// the location of various points in the "Global Section Table". This table is\r
+// created by the linker via the Code Red managed linker script mechanism. It\r
+// contains the load address, execution address and length of each RW data\r
+// section and the execution and length of each BSS (zero initialized) section.\r
+//*****************************************************************************\r
+extern unsigned int __data_section_table;\r
+extern unsigned int __data_section_table_end;\r
+extern unsigned int __bss_section_table;\r
+extern unsigned int __bss_section_table_end;\r
+\r
+//*****************************************************************************\r
+// Reset entry point for your code.\r
+// Sets up a simple runtime environment and initializes the C/C++\r
+// library.\r
+//*****************************************************************************\r
+__attribute__ ((section(".after_vectors.reset")))\r
+void ResetISR(void) {\r
+\r
+ // Disable interrupts\r
+ __asm volatile ("cpsid i");\r
+\r
+\r
+ // Enable SRAM clock used by Stack\r
+ __asm volatile ("LDR R0, =0x40000220\n\t"\r
+ "MOV R1, #56\n\t"\r
+ "STR R1, [R0]");\r
+\r
+#if defined (__USE_CMSIS)\r
+// If __USE_CMSIS defined, then call CMSIS SystemInit code\r
+ SystemInit();\r
+\r
+#endif // (__USE_CMSIS)\r
+\r
+ //\r
+ // Copy the data sections from flash to SRAM.\r
+ //\r
+ unsigned int LoadAddr, ExeAddr, SectionLen;\r
+ unsigned int *SectionTableAddr;\r
+\r
+ // Load base address of Global Section Table\r
+ SectionTableAddr = &__data_section_table;\r
+\r
+ // Copy the data sections from flash to SRAM.\r
+ while (SectionTableAddr < &__data_section_table_end) {\r
+ LoadAddr = *SectionTableAddr++;\r
+ ExeAddr = *SectionTableAddr++;\r
+ SectionLen = *SectionTableAddr++;\r
+ data_init(LoadAddr, ExeAddr, SectionLen);\r
+ }\r
+\r
+ // At this point, SectionTableAddr = &__bss_section_table;\r
+ // Zero fill the bss segment\r
+ while (SectionTableAddr < &__bss_section_table_end) {\r
+ ExeAddr = *SectionTableAddr++;\r
+ SectionLen = *SectionTableAddr++;\r
+ bss_init(ExeAddr, SectionLen);\r
+ }\r
+\r
+#if !defined (__USE_CMSIS)\r
+// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code\r
+// will enable the FPU\r
+#if defined (__VFP_FP__) && !defined (__SOFTFP__)\r
+ //\r
+ // Code to enable the Cortex-M4 FPU only included\r
+ // if appropriate build options have been selected.\r
+ // Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)\r
+ //\r
+ // Read CPACR (located at address 0xE000ED88)\r
+ // Set bits 20-23 to enable CP10 and CP11 coprocessors\r
+ // Write back the modified value to the CPACR\r
+ asm volatile ("LDR.W R0, =0xE000ED88\n\t"\r
+ "LDR R1, [R0]\n\t"\r
+ "ORR R1, R1, #(0xF << 20)\n\t"\r
+ "STR R1, [R0]");\r
+#endif // (__VFP_FP__) && !(__SOFTFP__)\r
+#endif // (__USE_CMSIS)\r
+\r
+\r
+#if !defined (__USE_CMSIS)\r
+// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code\r
+// will setup the VTOR register\r
+\r
+ // Check to see if we are running the code from a non-zero\r
+ // address (eg RAM, external flash), in which case we need\r
+ // to modify the VTOR register to tell the CPU that the\r
+ // vector table is located at a non-0x0 address.\r
+ unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;\r
+ if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) {\r
+ *pSCB_VTOR = (unsigned int)g_pfnVectors;\r
+ }\r
+#endif // (__USE_CMSIS)\r
+#if defined (__cplusplus)\r
+ //\r
+ // Call C++ library initialisation\r
+ //\r
+ __libc_init_array();\r
+#endif\r
+\r
+ // Reenable interrupts\r
+ __asm volatile ("cpsie i");\r
+\r
+#if defined (__REDLIB__)\r
+ // Call the Redlib library, which in turn calls main()\r
+ __main();\r
+#else\r
+ main();\r
+#endif\r
+\r
+ //\r
+ // main() shouldn't return, but if it does, we'll just enter an infinite loop\r
+ //\r
+ while (1) {\r
+ ;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+// Default core exception handlers. Override the ones here by defining your own\r
+// handler routines in your application code.\r
+//*****************************************************************************\r
+WEAK_AV void NMI_Handler(void)\r
+{ while(1) {}\r
+}\r
+\r
+WEAK_AV void HardFault_Handler(void)\r
+{ while(1) {}\r
+}\r
+\r
+WEAK_AV void MemManage_Handler(void)\r
+{ while(1) {}\r
+}\r
+\r
+WEAK_AV void BusFault_Handler(void)\r
+{ while(1) {}\r
+}\r
+\r
+WEAK_AV void UsageFault_Handler(void)\r
+{ while(1) {}\r
+}\r
+\r
+WEAK_AV void SVC_Handler(void)\r
+{ while(1) {}\r
+}\r
+\r
+WEAK_AV void DebugMon_Handler(void)\r
+{ while(1) {}\r
+}\r
+\r
+WEAK_AV void PendSV_Handler(void)\r
+{ while(1) {}\r
+}\r
+\r
+WEAK_AV void SysTick_Handler(void)\r
+{ while(1) {}\r
+}\r
+\r
+//*****************************************************************************\r
+// Processor ends up here if an unexpected interrupt occurs or a specific\r
+// handler is not present in the application code.\r
+//*****************************************************************************\r
+WEAK_AV void IntDefaultHandler(void)\r
+{ while(1) {}\r
+}\r
+\r
+//*****************************************************************************\r
+// Default application exception handlers. Override the ones here by defining\r
+// your own handler routines in your application code. These routines call\r
+// driver exception handlers or IntDefaultHandler() if no driver exception\r
+// handler is included.\r
+//*****************************************************************************\r
+WEAK void WDT_BOD_IRQHandler(void)\r
+{ WDT_BOD_DriverIRQHandler();\r
+}\r
+\r
+WEAK void DMA0_IRQHandler(void)\r
+{ DMA0_DriverIRQHandler();\r
+}\r
+\r
+WEAK void GINT0_IRQHandler(void)\r
+{ GINT0_DriverIRQHandler();\r
+}\r
+\r
+WEAK void GINT1_IRQHandler(void)\r
+{ GINT1_DriverIRQHandler();\r
+}\r
+\r
+WEAK void PIN_INT0_IRQHandler(void)\r
+{ PIN_INT0_DriverIRQHandler();\r
+}\r
+\r
+WEAK void PIN_INT1_IRQHandler(void)\r
+{ PIN_INT1_DriverIRQHandler();\r
+}\r
+\r
+WEAK void PIN_INT2_IRQHandler(void)\r
+{ PIN_INT2_DriverIRQHandler();\r
+}\r
+\r
+WEAK void PIN_INT3_IRQHandler(void)\r
+{ PIN_INT3_DriverIRQHandler();\r
+}\r
+\r
+WEAK void UTICK0_IRQHandler(void)\r
+{ UTICK0_DriverIRQHandler();\r
+}\r
+\r
+WEAK void MRT0_IRQHandler(void)\r
+{ MRT0_DriverIRQHandler();\r
+}\r
+\r
+WEAK void CTIMER0_IRQHandler(void)\r
+{ CTIMER0_DriverIRQHandler();\r
+}\r
+\r
+WEAK void CTIMER1_IRQHandler(void)\r
+{ CTIMER1_DriverIRQHandler();\r
+}\r
+\r
+WEAK void SCT0_IRQHandler(void)\r
+{ SCT0_DriverIRQHandler();\r
+}\r
+\r
+WEAK void CTIMER3_IRQHandler(void)\r
+{ CTIMER3_DriverIRQHandler();\r
+}\r
+\r
+WEAK void FLEXCOMM0_IRQHandler(void)\r
+{ FLEXCOMM0_DriverIRQHandler();\r
+}\r
+\r
+WEAK void FLEXCOMM1_IRQHandler(void)\r
+{ FLEXCOMM1_DriverIRQHandler();\r
+}\r
+\r
+WEAK void FLEXCOMM2_IRQHandler(void)\r
+{ FLEXCOMM2_DriverIRQHandler();\r
+}\r
+\r
+WEAK void FLEXCOMM3_IRQHandler(void)\r
+{ FLEXCOMM3_DriverIRQHandler();\r
+}\r
+\r
+WEAK void FLEXCOMM4_IRQHandler(void)\r
+{ FLEXCOMM4_DriverIRQHandler();\r
+}\r
+\r
+WEAK void FLEXCOMM5_IRQHandler(void)\r
+{ FLEXCOMM5_DriverIRQHandler();\r
+}\r
+\r
+WEAK void FLEXCOMM6_IRQHandler(void)\r
+{ FLEXCOMM6_DriverIRQHandler();\r
+}\r
+\r
+WEAK void FLEXCOMM7_IRQHandler(void)\r
+{ FLEXCOMM7_DriverIRQHandler();\r
+}\r
+\r
+WEAK void ADC0_SEQA_IRQHandler(void)\r
+{ ADC0_SEQA_DriverIRQHandler();\r
+}\r
+\r
+WEAK void ADC0_SEQB_IRQHandler(void)\r
+{ ADC0_SEQB_DriverIRQHandler();\r
+}\r
+\r
+WEAK void ADC0_THCMP_IRQHandler(void)\r
+{ ADC0_THCMP_DriverIRQHandler();\r
+}\r
+\r
+WEAK void DMIC0_IRQHandler(void)\r
+{ DMIC0_DriverIRQHandler();\r
+}\r
+\r
+WEAK void HWVAD0_IRQHandler(void)\r
+{ HWVAD0_DriverIRQHandler();\r
+}\r
+\r
+WEAK void USB0_NEEDCLK_IRQHandler(void)\r
+{ USB0_NEEDCLK_DriverIRQHandler();\r
+}\r
+\r
+WEAK void USB0_IRQHandler(void)\r
+{ USB0_DriverIRQHandler();\r
+}\r
+\r
+WEAK void RTC_IRQHandler(void)\r
+{ RTC_DriverIRQHandler();\r
+}\r
+\r
+WEAK void FLEXCOMM10_IRQHandler(void)\r
+{ FLEXCOMM10_DriverIRQHandler();\r
+}\r
+\r
+WEAK void Reserved47_IRQHandler(void)\r
+{ Reserved47_DriverIRQHandler();\r
+}\r
+\r
+WEAK void PIN_INT4_IRQHandler(void)\r
+{ PIN_INT4_DriverIRQHandler();\r
+}\r
+\r
+WEAK void PIN_INT5_IRQHandler(void)\r
+{ PIN_INT5_DriverIRQHandler();\r
+}\r
+\r
+WEAK void PIN_INT6_IRQHandler(void)\r
+{ PIN_INT6_DriverIRQHandler();\r
+}\r
+\r
+WEAK void PIN_INT7_IRQHandler(void)\r
+{ PIN_INT7_DriverIRQHandler();\r
+}\r
+\r
+WEAK void CTIMER2_IRQHandler(void)\r
+{ CTIMER2_DriverIRQHandler();\r
+}\r
+\r
+WEAK void CTIMER4_IRQHandler(void)\r
+{ CTIMER4_DriverIRQHandler();\r
+}\r
+\r
+WEAK void RIT_IRQHandler(void)\r
+{ RIT_DriverIRQHandler();\r
+}\r
+\r
+WEAK void SPIFI0_IRQHandler(void)\r
+{ SPIFI0_DriverIRQHandler();\r
+}\r
+\r
+WEAK void FLEXCOMM8_IRQHandler(void)\r
+{ FLEXCOMM8_DriverIRQHandler();\r
+}\r
+\r
+WEAK void FLEXCOMM9_IRQHandler(void)\r
+{ FLEXCOMM9_DriverIRQHandler();\r
+}\r
+\r
+WEAK void SDIO_IRQHandler(void)\r
+{ SDIO_DriverIRQHandler();\r
+}\r
+\r
+WEAK void CAN0_IRQ0_IRQHandler(void)\r
+{ CAN0_IRQ0_DriverIRQHandler();\r
+}\r
+\r
+WEAK void CAN0_IRQ1_IRQHandler(void)\r
+{ CAN0_IRQ1_DriverIRQHandler();\r
+}\r
+\r
+WEAK void CAN1_IRQ0_IRQHandler(void)\r
+{ CAN1_IRQ0_DriverIRQHandler();\r
+}\r
+\r
+WEAK void CAN1_IRQ1_IRQHandler(void)\r
+{ CAN1_IRQ1_DriverIRQHandler();\r
+}\r
+\r
+WEAK void USB1_IRQHandler(void)\r
+{ USB1_DriverIRQHandler();\r
+}\r
+\r
+WEAK void USB1_NEEDCLK_IRQHandler(void)\r
+{ USB1_NEEDCLK_DriverIRQHandler();\r
+}\r
+\r
+WEAK void ETHERNET_IRQHandler(void)\r
+{ ETHERNET_DriverIRQHandler();\r
+}\r
+\r
+WEAK void ETHERNET_PMT_IRQHandler(void)\r
+{ ETHERNET_PMT_DriverIRQHandler();\r
+}\r
+\r
+WEAK void ETHERNET_MACLP_IRQHandler(void)\r
+{ ETHERNET_MACLP_DriverIRQHandler();\r
+}\r
+\r
+WEAK void Reserved68_IRQHandler(void)\r
+{ Reserved68_DriverIRQHandler();\r
+}\r
+\r
+WEAK void LCD_IRQHandler(void)\r
+{ LCD_DriverIRQHandler();\r
+}\r
+\r
+WEAK void SHA_IRQHandler(void)\r
+{ SHA_DriverIRQHandler();\r
+}\r
+\r
+WEAK void SMARTCARD0_IRQHandler(void)\r
+{ SMARTCARD0_DriverIRQHandler();\r
+}\r
+\r
+WEAK void SMARTCARD1_IRQHandler(void)\r
+{ SMARTCARD1_DriverIRQHandler();\r
+}\r
+\r
+//*****************************************************************************\r
+\r
+#if defined (DEBUG)\r
+#pragma GCC pop_options\r
+#endif // (DEBUG)\r
projects / freertos / commitdiff