#include <linux/types.h>
#include <api_public.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define DEBUG
#undef DEBUG
#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
#define GPTCR_TEN 1 /* Timer enable */
-DECLARE_GLOBAL_DATA_PTR;
-
/* The 32768Hz 32-bit timer overruns in 131072 seconds */
int timer_init(void)
{
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* General purpose timers bitfields */
#define GPTCR_SWR (1<<15) /* Software reset */
#define GPTCR_FRR (1<<9) /* Freerun / restart */
#endif
#include <fsl_immap.h>
-DECLARE_GLOBAL_DATA_PTR;
-
bool soc_has_dp_ddr(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
#include <asm/arch/mc_me_regs.h>
#include "cpu.h"
-DECLARE_GLOBAL_DATA_PTR;
-
u32 cpu_mask(void)
{
return readl(MC_ME_CS);
#include <common.h>
#include <asm/io.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int timer_init(void)
{
writel(0, CONFIG_SYS_TIMER_COUNTER);
#include <asm/arch/mux_omap4.h>
#include <asm/ti-common/sys_proto.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
extern const struct emif_regs emif_regs_elpida_200_mhz_2cs;
extern const struct emif_regs emif_regs_elpida_380_mhz_1cs;
#include <asm/arch/clock.h>
#include <asm/ti-common/sys_proto.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Structure for Iodelay configuration registers.
* Theoretical max for g_delay is 21560 ps.
#include <common.h>
#include <command.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* ARMv7M does not support ARM instruction mode. However, the
* interworking BLX and BX instructions do encode the ARM/Thumb
#include <asm/arch/clk.h>
#include <spl.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static void switch_to_main_crystal_osc(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
#include <spi_flash.h>
#include <mmc.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifndef CONFIG_SPL_LIBCOMMON_SUPPORT
void puts(const char *str)
{
#define FSYS1_MMC0_DIV_MASK 0xff0f
#define FSYS1_MMC0_DIV_VAL 0x0701
-DECLARE_GLOBAL_DATA_PTR;
-
struct arm_clk_ratios arm_clk_ratios[] = {
#ifdef CONFIG_EXYNOS5420
{
#include <common.h>
#include <asm/armv8/mmu.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_EXYNOS7420
static struct mm_region exynos7420_mem_map[] = {
{
#include <asm/arch/clock.h>
#include <mapmem.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/**
* blob_dek() - Encapsulate the DEK as a blob using CAM's Key
* @src: - Address of data to be encapsulated
#include <asm/arch/pcc.h>
#include <asm/arch/sys_proto.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define PCC_CLKSRC_TYPES 2
#define PCC_CLKSRC_NUM 7
#include <asm/arch/pcc.h>
#include <asm/arch/sys_proto.h>
-DECLARE_GLOBAL_DATA_PTR;
-
scg_p scg1_regs = (scg_p)SCG1_RBASE;
static u32 scg_src_get_rate(enum scg_clk clksrc)
#include <errno.h>
#include <linux/iopoll.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
static u32 decode_frac_pll(enum clk_root_src frac_pll)
#include <asm/io.h>
#include <errno.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
static struct clk_root_map root_array[] = {
#define GPTPR_PRESCALER24M_SHIFT 12
#define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT)
-DECLARE_GLOBAL_DATA_PTR;
-
static inline int gpt_has_clk_source_osc(void)
{
#if defined(CONFIG_MX6)
#include <asm/arch/soc.h>
#include <asm/armv8/mmu.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Armada 3700 */
#define MVEBU_GPIO_NB_REG_BASE (MVEBU_REGISTER(0x13800))
#include <asm/arch/soc.h>
#include <asm/armv8/mmu.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Armada 7k/8k */
#define MVEBU_RFU_BASE (MVEBU_REGISTER(0x6f0000))
#define RFU_GLOBAL_SW_RST (MVEBU_RFU_BASE + 0x84)
#include <ahci.h>
#include <dm.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Dummy implementation that can be overwritten by a board
* specific function
#include <asm/io.h>
#include <asm/arch/soc.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define TIMER_LOAD_VAL 0xffffffff
static int init_done __attribute__((section(".data"))) = 0;
#include <asm/omap_common.h>
#include <linux/compiler.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Declarations */
extern omap3_sysinfo sysinfo;
#ifndef CONFIG_SYS_L2CACHE_OFF
#include <asm/arch/gpio.h>
#include <asm/omap_common.h>
-DECLARE_GLOBAL_DATA_PTR;
-
u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
static const struct gpio_bank gpio_bank_44xx[6] = {
#include <asm/emif.h>
#include <asm/omap_common.h>
-DECLARE_GLOBAL_DATA_PTR;
-
u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
#ifndef CONFIG_DM_GPIO
#include <asm/arch/timer.h>
#include <asm/arch/uart.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define GRF_BASE 0x20008000
#define DEBUG_UART_BASE 0x20068000
#include <asm/gpio.h>
#include <dm/pinctrl.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int board_late_init(void)
{
struct rk3188_grf *grf;
{
return BOOT_DEVICE_MMC1;
}
-DECLARE_GLOBAL_DATA_PTR;
-
#define GRF_BASE 0x11000000
#define SGRF_BASE 0x10140000
#include <asm/arch/sys_proto.h>
#include <asm/arch/timer.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define GRF_BASE 0xff770000
void board_init_f(ulong dummy)
{
#include <asm/arch/periph.h>
#include <asm/arch/timer.h>
-DECLARE_GLOBAL_DATA_PTR;
-
void board_debug_uart_init(void)
{
}
#include <asm/arch/timer.h>
#include <syscon.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* The SPL (and also the full U-Boot stage on the RK3368) will run in
* secure mode (i.e. EL3) and an ATF will eventually be booted before
#include <spl.h>
#include <syscon.h>
-DECLARE_GLOBAL_DATA_PTR;
-
void board_return_to_bootrom(void)
{
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
#include <dm.h>
#include <asm/arch/clock_manager.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static u32 eosc1_hz;
static u32 cb_intosc_hz;
static u32 f2s_free_hz;
#include <asm/arch/clock_manager.h>
#include <wait_bit.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct socfpga_clock_manager *clock_manager_base =
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Timeout count */
#define FPGA_TIMEOUT_CNT 0x1000000
#include <asm/arch/freeze_controller.h>
#include <linux/errno.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct socfpga_freeze_controller *freeze_controller_base =
(void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78
#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98
-DECLARE_GLOBAL_DATA_PTR;
-
#if defined(CONFIG_SPL_BUILD)
static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
#include <asm/io.h>
#include <asm/arch/reset_manager.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS;
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS;
static const struct socfpga_system_manager *sysmgr_regs =
#define SCANMGR_STAT_ACTIVE (1 << 31)
#define SCANMGR_STAT_WFIFOCNT_MASK 0x70000000
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct socfpga_scan_manager *scan_manager_base =
(void *)(SOCFPGA_SCANMGR_ADDRESS);
static const struct socfpga_freeze_controller *freeze_controller_base =
#include <asm/arch/system_manager.h>
#include <asm/arch/fpga_manager.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
}
#ifdef CONFIG_SPL_BUILD
-DECLARE_GLOBAL_DATA_PTR;
#endif
/* The sunxi internal brom will try to loader external bootloader
#include <asm/arch/dram.h>
#include <asm/arch/sys_proto.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define DRAM_CLK (CONFIG_DRAM_CLK * 1000000)
/*
#include <common.h>
#include <asm/arch/tegra.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int board_early_init_f(void)
{
return 0;
#include <asm/arch/tegra.h>
#include <asm/armv8/mmu.h>
-DECLARE_GLOBAL_DATA_PTR;
-
extern unsigned long nvtboot_boot_x0;
/*
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifndef CONFIG_ZYNQ_DDRC_INIT
void zynq_ddrc_init(void) {}
#else
#include <asm/arch/sys_proto.h>
#include <asm/arch/ps7_init_gpl.h>
-DECLARE_GLOBAL_DATA_PTR;
-
void board_init_f(ulong dummy)
{
ps7_init();
#include <asm/io.h>
#include <asm/u-boot.h>
-DECLARE_GLOBAL_DATA_PTR;
-
bool boot_linux;
u32 spl_boot_device(void)
#include <u-boot/zlib.h>
#include <asm/byteorder.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int do_bootm_linux(int flag, int argc, char * const argv[],
bootm_headers_t *images)
{
#include <mach/ar71xx_regs.h>
#include <mach/ath79.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define DDR_CTRL_UPD_EMR3S BIT(5)
#define DDR_CTRL_UPD_EMR2S BIT(4)
#define DDR_CTRL_PRECHARGE BIT(3)
#include <mach/ar71xx_regs.h>
#include <mach/ath79.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define DDR_CTRL_UPD_EMR3S BIT(5)
#define DDR_CTRL_UPD_EMR2S BIT(4)
#define DDR_CTRL_PRECHARGE BIT(3)
#include <common.h>
#include <command.h>
-DECLARE_GLOBAL_DATA_PTR;
-
unsigned long do_go_exec(ulong (*entry)(int, char * const []),
int argc, char * const argv[])
{
#include <fsl_qe.h>
#endif
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
/*
* For deriving usb clock from 100MHz sysclk, reference divisor is set
#include <fdt_support.h>
#include <asm/mp.h>
-DECLARE_GLOBAL_DATA_PTR;
-
extern void ft_fixup_num_cores(void *blob);
extern void ft_srio_setup(void *blob);
* on our cache or tlb entries.
*/
-DECLARE_GLOBAL_DATA_PTR;
-
struct exception_table_entry
{
unsigned long insn, fixup;
#include <image.h>
#include <linux/compiler.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* This function jumps to an image with argument. Normally an FDT or ATAGS
* image.
#include <common.h>
#include <command.h>
-DECLARE_GLOBAL_DATA_PTR;
-
unsigned long do_go_exec(ulong (*entry)(int, char * const []),
int argc, char * const argv[])
{
#include <common.h>
#include <asm/io.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define LINUX_ARM_ZIMAGE_MAGIC 0x016f2818
struct arm_z_header {
#include <asm/io.h>
#include <asm/pci.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset,
ulong *valuep, enum pci_size_t size)
{
#include <qfw.h>
#include <asm/cpu.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int cpu_qemu_get_desc(struct udevice *dev, char *buf, int size)
{
if (size < CPU_MAX_NAME_LEN)
#include <asm/scu.h>
#include <asm/u-boot-x86.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Miscellaneous platform dependent initializations
*/
#include <common.h>
#include <debug_uart.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Global declaration of gd */
struct global_data *global_data_ptr;
#include <common.h>
#include <dm.h>
-DECLARE_GLOBAL_DATA_PTR;
-
UCLASS_DRIVER(lpc) = {
.id = UCLASS_LPC,
.name = "lpc",
#include <linux/compiler.h>
#include <linux/libfdt.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Memory lay-out:
*
#include <asm/io.h>
#include <common.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_VIDEO_MXS
#define LCD_PAD_CTRL ( \
PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
#include <asm/io.h>
#include "fpga.h"
-DECLARE_GLOBAL_DATA_PTR;
-
int altera_pre_fn(int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
#include <spl.h>
#include <asm/arch/mx6-ddr.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Configure MX6Q/DUAL mmdc DDR io registers */
static struct mx6dq_iomux_ddr_regs ot1200_ddr_ioregs = {
/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 48ohm */
#include "platinum.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
/* Configure MX6Q/DUAL mmdc DDR io registers */
#include "platinum.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
/* Configure MX6Q/DUAL mmdc DDR io registers */
#include <malloc.h>
-DECLARE_GLOBAL_DATA_PTR;
-
ssize_t atf_read_mmc(uintptr_t offset, void *buffer, size_t size)
{
struct pt_regs regs;
#include "pinmux-config-cei-tk1-som.h"
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Routine: pinmux_init
* Description: Do individual peripheral pinmux configs
#include <fsl_esdhc.h>
#include "common.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_FSL_ESDHC
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
#include <fsl_esdhc.h>
#include "common.h"
-DECLARE_GLOBAL_DATA_PTR;
-
enum ddr_config {
DDR_16BIT_256MB,
DDR_32BIT_512MB,
#include <power/tps65218.h>
#include "board.h"
-DECLARE_GLOBAL_DATA_PTR;
-
const struct dpll_params dpll_mpu = { 800, 24, 1, -1, -1, -1, -1 };
const struct dpll_params dpll_core = { 1000, 24, -1, -1, 10, 8, 4 };
const struct dpll_params dpll_per = { 960, 24, 5, -1, -1, -1, -1 };
#include <scf0403_lcd.h>
#include <asm/arch-omap3/dss.h>
-DECLARE_GLOBAL_DATA_PTR;
-
enum display_type {
NONE,
DVI,
(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct mx6dq_iomux_ddr_regs dhcom6dq_ddr_ioregs = {
.dram_sdclk_0 = 0x00020030,
.dram_sdclk_1 = 0x00020030,
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/video.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#include "../common/board.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_NAND_MXS
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
#include "../common/board.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_NAND_MXS
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
#include <asm/fsl_i2c.h>
#include "vme8349pin.h"
-DECLARE_GLOBAL_DATA_PTR;
-
static struct pci_region pci1_regions[] = {
{
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
#include <asm/io.h>
#include <asm/fsl_law.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifndef CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_SYS_DRAM_SIZE 1024
#include <asm/io.h>
#include <asm/fsl_law.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifndef CONFIG_SYS_DDR_RAW_TIMING
fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
#endif
#include "vid.h"
-DECLARE_GLOBAL_DATA_PTR;
-
int __weak i2c_multiplexer_select_vid_channel(u8 channel)
{
return 0;
#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value)
#define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
-DECLARE_GLOBAL_DATA_PTR;
-
enum {
MUX_TYPE_CAN,
MUX_TYPE_IIC2,
#include <fsl-mc/fsl_mc.h>
#include <fsl-mc/ldpaa_wriop.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FSL_MC_ENET)
#include <asm/io.h>
#include <asm/immap.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#if defined(CONFIG_CMD_NAND)
#include <nand.h>
#include <linux/mtd/mtd.h>
#include <asm/io.h>
#include <asm/immap.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#if defined(CONFIG_CMD_NAND)
#include <nand.h>
#include <linux/mtd/mtd.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_mpc83xx_serdes.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* The following are used to control the SPI chip selects for the SPI command.
*/
#include <asm/fsl_i2c.h>
#include "../common/pq-mds-pib.h"
-DECLARE_GLOBAL_DATA_PTR;
-
static struct pci_region pci1_regions[] = {
{
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
#include <i2c.h>
#include <asm/fsl_i2c.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static struct pci_region pci1_regions[] = {
{
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
#include <i2c.h>
#include <asm/fsl_i2c.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static struct pci_region pci1_regions[] = {
{
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
#include "../common/ngpixis.h"
-DECLARE_GLOBAL_DATA_PTR;
-
int board_early_init_f(void)
{
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
#include <asm/io.h>
#include <asm/fsl_law.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* CONFIG_SYS_DDR_RAW_TIMING */
/*
* Hynix H5TQ1G83TFR-H9C
#include "gsc.h"
#include "common.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
#define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */
#define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */
#include <miiphy.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define MAX_MUX_CHANNELS 2
enum {
#include <miiphy.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define MAX_MUX_CHANNELS 2
enum {
#include "../common/dp501.h"
#include "controlcenterd-id.h"
-DECLARE_GLOBAL_DATA_PTR;
-
enum {
HWVER_100 = 0,
HWVER_110 = 1,
#include <common.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int board_init(void)
{
return 0;
#include <asm/scu.h>
#include <asm/u-boot-x86.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static struct dwc3_device dwc3_device_data = {
.maximum_speed = USB_SPEED_HIGH,
.base = CONFIG_SYS_USB_OTG_BASE,
#include "../common/common.h"
#include "kmp204x.h"
-DECLARE_GLOBAL_DATA_PTR;
-
static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
int checkboard(void)
#include "novena.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#define UART_PAD_CTRL \
(PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
#include <asm/arch/sys_proto.h>
#include <spl.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#if defined(CONFIG_SPL_BUILD)
#include <asm/arch/mx6-ddr.h>
/*
#include <asm/fsl_serdes.h>
#include <asm/fsl_mpc83xx_serdes.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int checkboard(void)
{
printf("Board: MPC8308 P1M\n");
#include "pinmux-config-jetson-tk1.h"
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Routine: pinmux_init
* Description: Do individual peripheral pinmux configs
#include <asm/ehci-omap.h>
#endif
-DECLARE_GLOBAL_DATA_PTR;
-
#define TWL4030_I2C_BUS 0
#define EXPANSION_EEPROM_I2C_BUS 2
#define EXPANSION_EEPROM_I2C_ADDRESS 0x51
#include <mach/ath79.h>
#include <debug_uart.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
void board_debug_uart_init(void)
{
#include <mach/ath79.h>
#include <debug_uart.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
void board_debug_uart_init(void)
{
#include <asm/arch/uart.h>
#include <asm/arch/sdram_rk3036.h>
-DECLARE_GLOBAL_DATA_PTR;
-
void get_ddr_config(struct rk3036_ddr_config *config)
{
/* K4B4G1646Q config */
#include <asm/io.h>
#include <asm/arch/uart.h>
-DECLARE_GLOBAL_DATA_PTR;
#include <power/regulator.h>
#include <spl.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int board_init(void)
{
struct udevice *pinctrl, *regulator;
#include <asm/arch/sdram_rk3036.h>
#include <asm/gpio.h>
-DECLARE_GLOBAL_DATA_PTR;
-
void get_ddr_config(struct rk3036_ddr_config *config)
{
/* K4B4G1646Q config */
#include <asm/arch/grf_rk3368.h>
#include <syscon.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int mach_cpu_init(void)
{
return 0;
#include <common.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int exynos_init(void)
{
return 0;
#include <asm/arch/pinmux.h>
#include <usb.h>
-DECLARE_GLOBAL_DATA_PTR;
-
u32 get_board_rev(void)
{
return 0;
#include "setup.h"
-DECLARE_GLOBAL_DATA_PTR;
-
unsigned int board_rev;
#ifdef CONFIG_REVISION_TAG
#include <usb/dwc2_udc.h>
#include <usb_mass_storage.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static unsigned int board_rev = -1;
static inline u32 get_model_rev(void);
#include <i2c.h>
#include <asm/fsl_i2c.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static struct pci_region pci1_regions[] = {
{
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
#include <linux/libfdt.h>
#include <fdt_support.h>
-DECLARE_GLOBAL_DATA_PTR;
-
void local_bus_init(void);
int board_early_init_f (void)
#include "../common/factoryset.h"
#include <nand.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_SPL_BUILD
static struct draco_baseboard_id __attribute__((section(".data"))) settings;
#include <nand.h>
#include <bmp_layout.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_SPL_BUILD
static void board_init_ddr(void)
{
#include "../common/factoryset.h"
#include "../../../drivers/video/da8xx-fb.h"
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Read header information from EEPROM into global structure.
*/
#include <asm/arch/timer.h>
#include <syscon.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int mach_cpu_init(void)
{
return 0;
#include <power/regulator.h>
#include <u-boot/sha256.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int board_init(void)
{
int ret;
#include <asm/arch/hardware.h>
#include <asm/ti-common/keystone_net.h>
-DECLARE_GLOBAL_DATA_PTR;
-
unsigned int get_external_clk(u32 clk)
{
unsigned int clk_freq;
#include <asm/arch/hardware.h>
#include <asm/ti-common/keystone_net.h>
-DECLARE_GLOBAL_DATA_PTR;
-
unsigned int external_clk[ext_clk_count] = {
[sys_clk] = 122880000,
[alt_core_clk] = 125000000,
#include <asm/arch/hardware.h>
#include <asm/ti-common/keystone_net.h>
-DECLARE_GLOBAL_DATA_PTR;
-
unsigned int get_external_clk(u32 clk)
{
unsigned int clk_freq;
#include <fsl_dcu_fb.h>
#include "div64.h"
-DECLARE_GLOBAL_DATA_PTR;
-
unsigned int dcu_set_pixel_clock(unsigned int pixclock)
{
struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
#include <mach/ddr.h>
#include <debug_uart.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_USB
static void wdr4300_usb_start(void)
{
#include <i2c.h>
#include <asm/fsl_i2c.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static struct pci_region pci1_regions[] = {
{
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
#include "tqma6_bb.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#include <asm/arch/sys_proto.h>
#include <spl.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#if defined(CONFIG_SPL_BUILD)
#include <asm/arch/mx6-ddr.h>
#include "cyrus.h"
#include "../common/eeprom.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#define GPIO_OPENDRAIN 0x30000000
#define GPIO_DIR 0x3c000004
#define GPIO_INITIAL 0x30000000
#include <asm/arch/sys_proto.h>
#include <spl.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#if defined(CONFIG_SPL_BUILD)
#include <asm/arch/mx6-ddr.h>
/*
#include <fdt_support.h>
#include <pca953x.h>
-DECLARE_GLOBAL_DATA_PTR;
-
extern void ft_board_pci_setup(void *blob, bd_t *bd);
static void flash_cs_fixup(void)
#include <fdt_support.h>
#include <pca953x.h>
-DECLARE_GLOBAL_DATA_PTR;
-
extern void ft_board_pci_setup(void *blob, bd_t *bd);
static void flash_cs_fixup(void)
#include <asm/byteorder.h>
#include <linux/compiler.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/**
* do_aes() - Handle the "aes" command-line command
* @cmdtp: Command data struct pointer
#include <asm/byteorder.h>
#include <linux/compiler.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/**
* blob_decap() - Decapsulate the data as a blob
* @key_mod: - Pointer to key modifier/key
#include <linux/kernel.h>
#include <linux/sizes.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Image booting support
*/
/* Note: depends on enum ec_current_image */
static const char * const ec_current_image_name[] = {"unknown", "RO", "RW"};
-DECLARE_GLOBAL_DATA_PTR;
-
/**
* Decode a flash region parameter
*
#include <asm/byteorder.h>
#include <linux/compiler.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Display values from last command.
* Memory modify remembered values are different from display memory.
*/
#include <dm.h>
#include <errno.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct cros_ec_dev *board_get_cros_ec_dev(void)
{
struct udevice *dev;
#include <lynxkdi.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#error "Lynx KDI support not implemented for configured CPU"
#include <console.h>
#include <version.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Board-specific Platform code can reimplement show_boot_progress () if needed
*/
#include <mmc.h>
#include <image.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static int mmc_load_legacy(struct spl_image_info *spl_image, struct mmc *mmc,
ulong sector, struct image_header *header)
{
#include <net.h>
#include <linux/libfdt.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#if defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)
static ulong spl_net_load_read(struct spl_load_info *load, ulong sector,
ulong count, void *buf)
#include <fat.h>
#include <image.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static int spl_sata_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
#include <g_dnl.h>
#include <sdp.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static int spl_sdp_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
#include <usb.h>
#include <fat.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_USB_STORAGE
static int usb_stor_curr_dev = -1; /* current device */
#endif
#endif
#include <asm/unaligned.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#include <usb.h>
#define USB_BUFSIZ 512
/* Check all partition types */
#define PART_TYPE_ALL -1
-DECLARE_GLOBAL_DATA_PTR;
-
static struct part_driver *part_driver_lookup_type(struct blk_desc *dev_desc)
{
struct part_driver *drv =
#include <adc.h>
#include <power/regulator.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define ADC_UCLASS_PLATDATA_SIZE sizeof(struct adc_uclass_platdata)
#define CHECK_NUMBER true
#define CHECK_MASK (!CHECK_NUMBER)
#include <asm/io.h>
#include <generic-phy.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct dwc_ahci_priv {
void *base;
void *wrapper_base;
#include <mach/at91_pmc.h>
#include "pmc.h"
-DECLARE_GLOBAL_DATA_PTR;
-
static int at91_plladiv_clk_enable(struct clk *clk)
{
return 0;
#include <mach/sama5_sfr.h>
#include "pmc.h"
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* The purpose of this clock is to generate a 480 MHz signal. A different
* rate can't be configured.
#include <common.h>
#include <dm.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct udevice_id at91_sckc_match[] = {
{ .compatible = "atmel,at91sam9x5-sckc" },
{}
* |---------------------------->
*/
-DECLARE_GLOBAL_DATA_PTR;
-
#define CGU_ARC_IDIV 0x080
#define CGU_TUN_IDIV_TUN 0x380
#define CGU_TUN_IDIV_ROM 0x390
#include <dt-bindings/clock/stm32h7-clks.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* RCC CR specific definitions */
#define RCC_CR_HSION BIT(0)
#define RCC_CR_HSIRDY BIT(2)
#include <asm/arch/sys_proto.h>
#include <dm.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const resource_size_t zynqmp_crf_apb_clkc_base = 0xfd1a0020;
static const resource_size_t zynqmp_crl_apb_clkc_base = 0xff5e0020;
#include <dt-bindings/clock/exynos7420-clk.h>
#include "clk-pll.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#define DIVIDER(reg, shift, mask) \
(((readl(reg) >> shift) & mask) + 1)
#include <dt-bindings/clock/rk3036-cru.h>
#include <linux/log2.h>
-DECLARE_GLOBAL_DATA_PTR;
-
enum {
VCO_MAX_HZ = 2400U * 1000000,
VCO_MIN_HZ = 600 * 1000000,
#include <dt-bindings/clock/rk3128-cru.h>
#include <linux/log2.h>
-DECLARE_GLOBAL_DATA_PTR;
-
enum {
VCO_MAX_HZ = 2400U * 1000000,
VCO_MIN_HZ = 600 * 1000000,
#include <dm/uclass-internal.h>
#include <linux/log2.h>
-DECLARE_GLOBAL_DATA_PTR;
-
enum rk3188_clk_type {
RK3188_CRU,
RK3188A_CRU,
#include <dt-bindings/clock/rk3228-cru.h>
#include <linux/log2.h>
-DECLARE_GLOBAL_DATA_PTR;
-
enum {
VCO_MAX_HZ = 3200U * 1000000,
VCO_MIN_HZ = 800 * 1000000,
#include <dm/lists.h>
#include <dt-bindings/clock/rk3328-cru.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct pll_div {
u32 refdiv;
u32 fbdiv;
#include <dm/lists.h>
#include <dt-bindings/clock/rk3368-cru.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3368_clk_plat {
struct dtd_rockchip_rk3368_cru dtd;
#include <dm/lists.h>
#include <dt-bindings/clock/rk3399-cru.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3399_clk_plat {
struct dtd_rockchip_rk3399_cru dtd;
#include <dm/lists.h>
#include <dt-bindings/clock/rv1108-cru.h>
-DECLARE_GLOBAL_DATA_PTR;
-
enum {
VCO_MAX_HZ = 2400U * 1000000,
VCO_MIN_HZ = 600 * 1000000,
#include <dm/lists.h>
#include <dm/root.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int cpu_get_desc(struct udevice *dev, char *buf, int size)
{
struct cpu_ops *ops = cpu_get_ops(dev);
#include <asm/arch/system_manager.h>
#include <asm/io.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct sdram_prot_rule {
u32 sdram_start; /* SDRAM start address */
u32 sdram_end; /* SDRAM end address */
#include <fsl_ddr_sdram.h>
#include <fsl_ddr.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
* of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
#include <dm/device-internal.h>
#include <errno.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int dma_get_device(u32 transfer_type, struct udevice **devp)
{
struct udevice *dev;
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Timeout count */
#define FPGA_TIMEOUT_CNT 0x1000000
#define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
#define FPGA_TIMEOUT_CNT 0x1000000
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct socfpga_fpga_manager *fpga_manager_base =
(void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define FPGA_TIMEOUT_CNT 0x1000000
static struct socfpga_fpga_manager *fpgamgr_regs =
#include <errno.h>
#include <linux/printk.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define HSDK_CREG_MAX_GPIO 8
#define GPIO_ACTIVATE 0x2
#include <asm/io.h>
#include <malloc.h>
-DECLARE_GLOBAL_DATA_PTR;
-
enum imx_rgpio2p_direction {
IMX_RGPIO2P_DIRECTION_IN,
IMX_RGPIO2P_DIRECTION_OUT,
#include <asm/io.h>
#include <errno.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define MVEBU_GPIOS_PER_BANK 32
struct mvebu_gpio_regs {
#ifdef CONFIG_DM_GPIO
#include <fdtdec.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static int mxc_gpio_is_output(struct gpio_regs *regs, int offset)
{
u32 val;
#include <asm/gpio.h>
#include <linux/bitops.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Register offset for each gpio */
#define REG_OFFSET(x) ((x) * 0x100)
#include <dm/of.h>
#include <dt-bindings/gpio/gpio.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Flags for each GPIO */
#define GPIOF_OUTPUT (1 << 0) /* Currently set as an output */
#define GPIOF_HIGH (1 << 1) /* Currently set high */
#include <dm/device-internal.h>
#include <dt-bindings/gpio/gpio.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define SUNXI_GPIOS_PER_BANK SUNXI_GPIO_A_NR
struct sunxi_gpio_platdata {
#include <dt-bindings/gpio/gpio.h>
#include "tegra186_gpio_priv.h"
-DECLARE_GLOBAL_DATA_PTR;
-
struct tegra186_gpio_port_data {
const char *name;
uint32_t offset;
#include <dm/device-internal.h>
#include <dt-bindings/gpio/gpio.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const int CONFIG_SFIO = 0;
static const int CONFIG_GPIO = 1;
static const int DIRECTION_INPUT = 0;
#define HIGHSPEED_TTIMEOUT 3
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Device private data
*/
#include <mapmem.h>
#include <wait_bit.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* i2c register set */
struct cdns_i2c_regs {
u32 control;
#include <fdtdec.h>
#include <i2c.h>
-DECLARE_GLOBAL_DATA_PTR;
#define LPI2C_FIFO_SIZE 4
#define LPI2C_TIMEOUT_MS 100
#include "omap24xx_i2c.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#define I2C_TIMEOUT 1000
/* Absolutely safe for status update at 100 kHz I2C: */
#include <dm/pinctrl.h>
#include <linux/sizes.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* i2c timerout */
#define I2C_TIMEOUT_MS 100
#define I2C_RETRY_COUNT 3
#include <dm/lists.h>
#include <dm/device-internal.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct sandbox_i2c_priv {
bool test_mode;
};
.analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE,
};
-DECLARE_GLOBAL_DATA_PTR;
-
static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv)
{
struct stm32_i2c_regs *regs = i2c_priv->regs;
#include <asm/arch/gpio.h>
#include <asm/arch-tegra/tegra_i2c.h>
-DECLARE_GLOBAL_DATA_PTR;
-
enum i2c_type {
TYPE_114,
TYPE_STD,
#include <key_matrix.h>
#include <stdio_dev.h>
-DECLARE_GLOBAL_DATA_PTR;
-
enum {
KBC_MAX_KEYS = 8, /* Maximum keys held down at once */
KBC_REPEAT_RATE_MS = 30,
#include <asm/arch-tegra/timer.h>
#include <linux/input.h>
-DECLARE_GLOBAL_DATA_PTR;
-
enum {
KBC_MAX_GPIO = 24,
KBC_MAX_KPENT = 8, /* size of keypress entry queue */
#include <asm/gpio.h>
#include <dm/lists.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct led_gpio_priv {
struct gpio_desc gpio;
};
#include <mailbox.h>
#include <mailbox-uclass.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static inline struct mbox_ops *mbox_dev_ops(struct udevice *dev)
{
return (struct mbox_ops *)dev->driver->ops;
uint32_t db_base;
};
-DECLARE_GLOBAL_DATA_PTR;
-
static uint32_t *tegra_hsp_reg(struct tegra_hsp *thsp, uint32_t db_id,
uint32_t reg)
{
CROS_EC_CMD_HASH_TIMEOUT_MS = 2000,
};
-DECLARE_GLOBAL_DATA_PTR;
-
void cros_ec_dump_data(const char *name, int cmd, const uint8_t *data, int len)
{
#ifdef DEBUG
* the EC image in with U-Boot (Vic has demonstrated a prototype for this).
*/
-DECLARE_GLOBAL_DATA_PTR;
-
#define KEYBOARD_ROWS 8
#define KEYBOARD_COLS 13
#include <errno.h>
#include <spi.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int cros_ec_spi_packet(struct udevice *udev, int out_bytes, int in_bytes)
{
struct cros_ec_dev *dev = dev_get_uclass_priv(udev);
#define debug_buffer(x, ...)
#endif
-DECLARE_GLOBAL_DATA_PTR;
-
struct sandbox_i2c_flash_plat_data {
enum sandbox_i2c_eeprom_test_mode test_mode;
const char *filename;
#include <dm.h>
#include <dt-structs.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static int sandbox_spl_probe(struct udevice *dev)
{
struct dtd_sandbox_spl_test *plat = dev_get_platdata(dev);
#include <asm/test.h>
#include <dm/lists.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct udevice_id sandbox_syscon_ids[] = {
{ .compatible = "sandbox,syscon0", .data = SYSCON0 },
{ .compatible = "sandbox,syscon1", .data = SYSCON1 },
#ifdef CONFIG_DM_MMC
#include <dm.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define MMC_CLOCK_MAX 48000000
#define MMC_CLOCK_MIN 400000
#include <mach/gpio.h>
#include <power/regulator.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define msleep(a) udelay(a * 1000)
#define SDCMD 0x00 /* Command to SD card - 16 R/W */
#include <asm/arch/hardware.h>
#include "atmel_mci.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#ifndef CONFIG_SYS_MMC_CLK_OD
# define CONFIG_SYS_MMC_CLK_OD 150000
#endif
#include <dm/lists.h>
#include "mmc_private.h"
-DECLARE_GLOBAL_DATA_PTR;
-
int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
struct mmc_data *data)
{
#include <asm/arch/periph.h>
#include <linux/err.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct rockchip_mmc_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_rockchip_rk3288_dw_mshc dtplat;
#include <sdhci.h>
#include <clk.h>
-DECLARE_GLOBAL_DATA_PTR;
/* 400KHz is max freq for card ID etc. Use that as min */
#define EMMC_MIN_FREQ 400000
#include <mmc.h>
#include <asm/test.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct sandbox_mmc_plat {
struct mmc_config cfg;
struct mmc mmc;
#define SDMMC_CMD_TIMEOUT 0xFFFFFFFF
-DECLARE_GLOBAL_DATA_PTR;
-
static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv,
struct mmc_data *data,
struct stm32_sdmmc2_ctx *ctx)
#include <asm/io.h>
#include <asm/arch-tegra/tegra_mmc.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct tegra_mmc_plat {
struct mmc_config cfg;
struct mmc mmc;
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#endif
-DECLARE_GLOBAL_DATA_PTR;
-
int nand_curr_device = -1;
static struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
#include <dm/lists.h>
#include <dm/uclass-internal.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* The different states that our SPI flash transitions between.
* We need to keep track of this across multiple xfer calls since
#include "sf_internal.h"
-DECLARE_GLOBAL_DATA_PTR;
-
static void spi_flash_addr(u32 addr, u8 *cmd)
{
/* cmd[0] is actual command */
#include <power/regulator.h>
#include "designware.h"
-DECLARE_GLOBAL_DATA_PTR;
-
static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
#ifdef CONFIG_DM_ETH
#include "MCD_dma.h"
-DECLARE_GLOBAL_DATA_PTR;
-
struct fec_info_dma fec_info[] = {
#ifdef CONFIG_SYS_FEC0_IOBASE
{
#include <dt-bindings/clock/rk3288-cru.h>
#include "designware.h"
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Platform data for the gmac
*
#define MII_MAX_PHY (MADR_PHY_MASK >> MADR_PHY_OFFSET)
-DECLARE_GLOBAL_DATA_PTR;
-
#if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
/*
* mii_reg_read - miiphy_read callback function.
#define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
#define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST)
-DECLARE_GLOBAL_DATA_PTR;
-
struct fec_info_s fec_info[] = {
#ifdef CONFIG_SYS_FEC0_IOBASE
{
#include <stdio_dev.h>
#include <net.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifndef CONFIG_NETCONSOLE_BUFFER_SIZE
#define CONFIG_NETCONSOLE_BUFFER_SIZE 512
#endif
#include <micrel.h>
#include <phy.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static struct phy_driver KSZ804_driver = {
.name = "Micrel KSZ804",
.uid = 0x221510,
#include <micrel.h>
#include <phy.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* KSZ9021 - KSZ9031 common
*/
#include <dm.h>
#include <pch.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int pch_get_spi_base(struct udevice *dev, ulong *sbasep)
{
struct pch_ops *ops = pch_get_ops(dev);
#define CFG_RD_UR_VAL 0xFFFFFFFF
#define CFG_RD_CRS_VAL 0xFFFF0001
-DECLARE_GLOBAL_DATA_PTR;
-
/**
* struct pcie_advk - Advk PCIe controller state
*
#include <pci.h>
#include <dm/lists.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct sandbox_pci_priv {
int dev_count;
};
#include <inttypes.h>
#include <pci.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static int sandbox_pci_write_config(struct udevice *bus, pci_dev_t devfn,
uint offset, ulong value,
enum pci_size_t size)
* use the new standard APIs, with no ifdefs.
*/
-DECLARE_GLOBAL_DATA_PTR;
-
#define AFI_AXI_BAR0_SZ 0x00
#define AFI_AXI_BAR1_SZ 0x04
#define AFI_AXI_BAR2_SZ 0x08
#include <linux/bitops.h>
#include <linux/compat.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* bits [31:27] are read-only */
#define U2P_R0 0x0
#define U2P_R0_BYPASS_SEL BIT(0)
#include <linux/compat.h>
#include <linux/bitfield.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define USB_R0 0x00
#define USB_R0_P30_FSEL_MASK GENMASK(5, 0)
#define USB_R0_P30_PHY_RESET BIT(6)
#include <dm.h>
#include <generic-phy.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static inline struct phy_ops *phy_dev_ops(struct udevice *dev)
{
return (struct phy_ops *)dev->driver->ops;
#include <dm.h>
#include <generic-phy.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct sandbox_phy_priv {
bool initialized;
bool on;
#include <asm/arch/scu_ast2500.h>
#include <dm/pinctrl.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* This driver works with very simple configuration that has the same name
* for group and function. This way it is compatible with the Linux Kernel
#include <asm/arch/pinmux.h>
#include "pinctrl-exynos.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#define GPD1_OFFSET 0xc0
static struct exynos_pinctrl_config_data serial2_conf[] = {
#include "sh_pfc.h"
-DECLARE_GLOBAL_DATA_PTR;
-
enum sh_pfc_model {
SH_PFC_R8A7790 = 0,
SH_PFC_R8A7791,
#include <asm/arch/periph.h>
#include <dm/pinctrl.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* GRF_GPIO0A_IOMUX */
enum {
GPIO0A3_SHIFT = 6,
#include <asm/io.h>
#include <dm/pinctrl.h>
-DECLARE_GLOBAL_DATA_PTR;
-
enum {
/* GPIO0A_IOMUX */
GPIO0A5_SEL_SHIFT = 10,
#include <asm/arch/periph.h>
#include <dm/pinctrl.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* PMUGRF_GPIO0B_IOMUX */
enum {
GPIO0B5_SHIFT = 10,
#include <asm/arch/clock.h>
#include <dm/pinctrl.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct rk3399_pinctrl_priv {
struct rk3399_grf_regs *grf;
struct rk3399_pmugrf_regs *pmugrf;
#include <asm/arch/periph.h>
#include <dm/pinctrl.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct rv1108_pinctrl_priv {
struct rv1108_grf *grf;
};
#include <power-domain.h>
#include <power-domain-uclass.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static inline struct power_domain_ops *power_domain_dev_ops(struct udevice *dev)
{
return (struct power_domain_ops *)dev->driver->ops;
#include <power/act8846_pmic.h>
#include <power/pmic.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct pmic_child_info pmic_children_info[] = {
{ .prefix = "REG", .driver = "act8846_reg"},
{ },
#include <power/pmic.h>
#include <power/sandbox_pmic.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/**
* struct sandbox_i2c_pmic_plat_data - platform data for the PMIC
*
#include <power/lp873x.h>
#include <dm/device.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct pmic_child_info pmic_children_info[] = {
{ .prefix = "ldo", .driver = LP873X_LDO_DRIVER },
{ .prefix = "buck", .driver = LP873X_BUCK_DRIVER },
#include <power/lp87565.h>
#include <dm/device.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct pmic_child_info pmic_children_info[] = {
{ .prefix = "buck", .driver = LP87565_BUCK_DRIVER },
{ },
#include <power/regulator.h>
#include <power/max77686_pmic.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct pmic_child_info pmic_children_info[] = {
{ .prefix = "LDO", .driver = MAX77686_LDO_DRIVER },
{ .prefix = "BUCK", .driver = MAX77686_BUCK_DRIVER },
#include <power/max8997_pmic.h>
#include <errno.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static int max8997_reg_count(struct udevice *dev)
{
return PMIC_NUM_OF_REGS;
#include <power/pmic.h>
#include <power/max8998_pmic.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static int max8998_reg_count(struct udevice *dev)
{
return PMIC_NUM_OF_REGS;
#include <power/palmas.h>
#include <dm/device.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct pmic_child_info pmic_children_info[] = {
{ .prefix = "ldo", .driver = PALMAS_LDO_DRIVER },
{ .prefix = "smps", .driver = PALMAS_SMPS_DRIVER },
#include <power/regulator.h>
#include <power/pfuze100_pmic.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct pmic_child_info pmic_children_info[] = {
/* sw[x], swbst */
{ .prefix = "s", .driver = PFUZE100_REGULATOR_DRIVER },
#include <power/pmic.h>
#include <spmi/spmi.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define PID_SHIFT 8
#define PID_MASK (0xFF << PID_SHIFT)
#define REG_MASK 0xFF
#include <power/pmic.h>
#include <linux/ctype.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#if CONFIG_IS_ENABLED(PMIC_CHILDREN)
int pmic_bind_children(struct udevice *pmic, ofnode parent,
const struct pmic_child_info *child_info)
#include <power/regulator.h>
#include <power/tps65910_pmic.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct pmic_child_info pmic_children_info[] = {
{ .prefix = "ldo_", .driver = TPS65910_LDO_DRIVER },
{ .prefix = "buck_", .driver = TPS65910_BUCK_DRIVER },
#include <power/rk8xx_pmic.h>
#include <power/pmic.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct pmic_child_info pmic_children_info[] = {
{ .prefix = "DCDC_REG", .driver = "rk8xx_buck"},
{ .prefix = "LDO_REG", .driver = "rk8xx_ldo"},
#include <power/pmic.h>
#include <power/s2mps11.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct pmic_child_info pmic_children_info[] = {
{ .prefix = S2MPS11_OF_LDO_PREFIX, .driver = S2MPS11_LDO_DRIVER },
{ .prefix = S2MPS11_OF_BUCK_PREFIX, .driver = S2MPS11_BUCK_DRIVER },
#include <power/regulator.h>
#include <power/s5m8767.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct pmic_child_info pmic_children_info[] = {
{ .prefix = "LDO", .driver = S5M8767_LDO_DRIVER },
{ .prefix = "BUCK", .driver = S5M8767_BUCK_DRIVER },
#include <power/regulator.h>
#include <power/sandbox_pmic.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct pmic_child_info pmic_children_info[] = {
{ .prefix = SANDBOX_OF_LDO_PREFIX, .driver = SANDBOX_LDO_DRIVER },
{ .prefix = SANDBOX_OF_BUCK_PREFIX, .driver = SANDBOX_BUCK_DRIVER },
#include <power/pmic.h>
#include <power/tps65090.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct pmic_child_info pmic_children_info[] = {
{ .prefix = "fet", .driver = TPS65090_FET_DRIVER },
{ },
#include <power/pmic.h>
#include <power/regulator.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct fixed_regulator_platdata {
struct gpio_desc gpio; /* GPIO for regulator enable control */
unsigned int startup_delay_us;
#include <power/regulator.h>
#include <power/lp873x.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const char lp873x_buck_ctrl[LP873X_BUCK_NUM] = {0x2, 0x4};
static const char lp873x_buck_volt[LP873X_BUCK_NUM] = {0x6, 0x7};
static const char lp873x_ldo_ctrl[LP873X_LDO_NUM] = {0x8, 0x9};
#include <power/regulator.h>
#include <power/lp87565.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const char lp87565_buck_ctrl1[LP87565_BUCK_NUM] = {0x2, 0x4, 0x6, 0x8, 0x2, 0x6};
static const char lp87565_buck_vout[LP87565_BUCK_NUM] = {0xA, 0xC, 0xE, 0x10, 0xA, 0xE };
#include <power/regulator.h>
#include <power/max77686_pmic.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define MODE(_id, _val, _name) { \
.id = _id, \
.register_value = _val, \
#include <power/regulator.h>
#include <power/palmas.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define REGULATOR_ON 0x1
#define REGULATOR_OFF 0x0
#include <linux/ioport.h>
#include <dm/read.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct pbias_reg_info {
u32 enable;
u32 enable_mask;
#include <power/pmic.h>
#include <power/regulator.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int regulator_mode(struct udevice *dev, struct dm_regulator_mode **modep)
{
struct dm_regulator_uclass_platdata *uc_pdata;
#include <power/regulator.h>
#include <power/s2mps11.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define MODE(_id, _val, _name) { \
.id = _id, \
.register_value = _val, \
#include <power/regulator.h>
#include <power/s5m8767.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct sec_voltage_desc buck_v1 = {
.max = 2225000,
.min = 650000,
#include <power/regulator.h>
#include <power/sandbox_pmic.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define MODE(_id, _val, _name) [_id] = { \
.id = _id, \
.register_value = _val, \
#include <asm/arch/clock.h>
#include <asm/arch/pwm.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct exynos_pwm_priv {
struct s5p_timer *regs;
};
#include <asm/arch/pwm.h>
#include <power/regulator.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct rk_pwm_priv {
struct rk3288_pwm *regs;
ulong freq;
#include <pwm.h>
#include <asm/test.h>
-DECLARE_GLOBAL_DATA_PTR;
-
enum {
NUM_CHANNELS = 3,
};
#include <asm/arch/clock.h>
#include <asm/arch/pwm.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct tegra_pwm_priv {
struct pwm_ctlr *regs;
};
#include <asm/arch/sdram.h>
#include <asm/arch/sdram_common.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct dram_info {
struct ram_info info;
struct clk ddr_clk;
#include <asm/arch/grf_rk3128.h>
#include <asm/arch/sdram_common.h>
-DECLARE_GLOBAL_DATA_PTR;
struct dram_info {
struct ram_info info;
struct rk3128_grf *grf;
#include <asm/arch/sdram_common.h>
#include <linux/err.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct chan_info {
struct rk3288_ddr_pctl *pctl;
struct rk3288_ddr_publ *publ;
#include <power/regulator.h>
#include <power/rk8xx_pmic.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct chan_info {
struct rk3288_ddr_pctl *pctl;
struct rk3288_ddr_publ *publ;
#include <asm/arch/grf_rk3328.h>
#include <asm/arch/sdram_common.h>
-DECLARE_GLOBAL_DATA_PTR;
struct dram_info {
struct ram_info info;
struct rk3328_grf_regs *grf;
#include <linux/err.h>
#include <time.h>
-DECLARE_GLOBAL_DATA_PTR;
struct chan_info {
struct rk3399_ddr_pctl_regs *pctl;
struct rk3399_ddr_pi_regs *pi;
#define MEM_MODE_MASK GENMASK(2, 0)
#define NOT_FOUND 0xff
-DECLARE_GLOBAL_DATA_PTR;
-
struct stm32_fmc_regs {
/* 0x0 */
u32 bcr1; /* NOR/PSRAM Chip select control register 1 */
#include <asm/io.h>
#include "stm32mp1_ddr.h"
-DECLARE_GLOBAL_DATA_PTR;
-
static const char *const clkname[] = {
"ddrc1",
"ddrc2",
#include <asm/arch/scu_ast2500.h>
#include <asm/arch/wdt.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct ast2500_reset_priv {
/* WDT used to perform resets. */
struct udevice *wdt;
#include <reset.h>
#include <reset-uclass.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static inline struct reset_ops *reset_dev_ops(struct udevice *dev)
{
return (struct reset_ops *)dev->driver->ops;
#define debug_buffer(x, ...)
#endif
-DECLARE_GLOBAL_DATA_PTR;
-
/**
* struct sandbox_i2c_rtc_plat_data - platform data for the RTC
*
#include <serial.h>
#include <asm/io.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* data register */
#define ALTERA_JTAG_RVALID BIT(15) /* Read valid */
#include <asm/arch/uart.h>
#include <linux/compiler.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct lpc32xx_hsuart_priv {
struct hsuart_regs *hsuart;
};
#include <linux/compiler.h>
#include <serial.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct meson_uart {
u32 wfifo;
u32 rfifo;
#include <asm/arch/stm32.h>
#include "serial_stm32.h"
-DECLARE_GLOBAL_DATA_PTR;
-
static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
{
struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
#include <linux/compiler.h>
#include <serial.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define SR_TX_FIFO_FULL BIT(3) /* transmit FIFO full */
#define SR_TX_FIFO_EMPTY BIT(2) /* transmit FIFO empty */
#define SR_RX_FIFO_VALID_DATA BIT(0) /* data in receive FIFO */
#include <serial.h>
#include <asm/arch/hardware.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define ZYNQ_UART_SR_TXEMPTY (1 << 3) /* TX FIFO empty */
#define ZYNQ_UART_SR_TXACTIVE (1 << 11) /* TX active */
#define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
#include <spi.h>
#include <asm/io.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define ALTERA_SPI_STATUS_RRDY_MSK BIT(7)
#define ALTERA_SPI_CONTROL_SSO_MSK BIT(10)
#include "atmel_spi.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#ifndef CONFIG_DM_SPI
static int spi_has_wdrbt(struct atmel_spi_slave *slave)
#include <dm/pinctrl.h>
#include "rk_spi.h"
-DECLARE_GLOBAL_DATA_PTR;
-
/* Change to 1 to output registers at the start of each transaction */
#define DEBUG_RK_SPI 0
#include <asm/state.h>
#include <dm/device-internal.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifndef CONFIG_SPI_IDLE_VAL
# define CONFIG_SPI_IDLE_VAL 0xFF
#endif
#include <spi.h>
#include "tegra_spi.h"
-DECLARE_GLOBAL_DATA_PTR;
-
/* COMMAND1 */
#define SPI_CMD1_GO BIT(31)
#define SPI_CMD1_M_S BIT(30)
#include <asm/gpio.h>
#include <asm/io.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define EMUL_GPIO_PID_START 0xC0
#define EMUL_GPIO_PID_END 0xC3
#include <spmi/spmi.h>
#include <linux/ctype.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int spmi_reg_read(struct udevice *dev, int usid, int pid, int reg)
{
const struct dm_spmi_ops *ops = dev_get_driver_ops(dev);
#include <asm/state.h>
#include <asm/test.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static int sandbox_warm_sysreset_request(struct udevice *dev,
enum sysreset_t type)
{
#include <timer.h>
#include <linux/io.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Timer Control Register
*/
#include <timer.h>
#include <asm/io.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* control register */
#define ALTERA_TIMER_CONT BIT(1) /* Continuous mode */
#define ALTERA_TIMER_START BIT(2) /* Start timer */
#include <asm/io.h>
#include <asm/arch/timer.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define AST_TICK_TIMER 1
#define AST_TMC_RELOAD_VAL 0xffffffff
#include <timer.h>
#include <linux/io.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define REG32_TMR(x) (*(u32 *) ((plat->regs) + (x>>2)))
/*
#include <asm/io.h>
#include <asm/arch/clock.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Timer register bits */
#define TCLR_START BIT(0) /* Start=1 */
#define TCLR_AUTO_RELOAD BIT(1) /* Auto reload */
#include "tpm_tis.h"
#include "tpm_internal.h"
-DECLARE_GLOBAL_DATA_PTR;
-
enum i2c_chip_type {
SLB9635,
SLB9645,
#include <scsi.h>
#include <usb.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* This driver emulates a flash stick using the UFI command specification and
* the BBB (bulk/bulk/bulk) protocol. It supports only a single logical unit
#include <usb.h>
#include <dm/device-internal.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* We only support up to 8 */
#define SANDBOX_NUM_PORTS 4
#include <scsi.h>
#include <usb.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* This driver emulates a USB keyboard using the USB HID specification (boot
* protocol)
#include <usb.h>
#include <dm/device-internal.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static int copy_to_unicode(char *buff, int length, const char *str)
{
int ptr;
#include "dwc2.h"
-DECLARE_GLOBAL_DATA_PTR;
-
/* Use only HC channel 0. */
#define DWC2_HC_CHANNEL 0
#include <reset.h>
#include <clk.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct dwc3_of_simple {
struct clk_bulk clks;
struct reset_ctl_bulk resets;
#include "ehci.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#ifndef CONFIG_DM_USB
int ehci_hcd_init(int index, enum usb_init_type init,
#include "ehci.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#define USB1_ADDR_MASK 0xFFFF0000
#define HOSTPC1_DEVLC 0x84
#include <usb.h>
#include <dm/root.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct sandbox_usb_ctrl {
int rootdev;
};
#include <dm/lists.h>
#include <dm/uclass-internal.h>
-DECLARE_GLOBAL_DATA_PTR;
-
extern bool usb_started; /* flag for the started/stopped USB status */
static bool asynch_allowed;
#include <linux/usb/dwc3.h>
#include <linux/usb/otg.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct xhci_dwc3_platdata {
struct phy *usb_phys;
int num_phys;
#include <dm.h>
/* Declare global data pointer */
-DECLARE_GLOBAL_DATA_PTR;
-
#ifndef CONFIG_DM_USB
static struct fsl_xhci fsl_xhci;
unsigned long ctr_addr[] = FSL_USB_XHCI_ADDR;
#include "xhci.h"
-DECLARE_GLOBAL_DATA_PTR;
-
struct mvebu_xhci_platdata {
fdt_addr_t hcd_base;
};
#include "xhci.h"
/* Declare global data pointer */
-DECLARE_GLOBAL_DATA_PTR;
-
static struct omap_xhci omap;
static int omap_xhci_core_init(struct omap_xhci *omap)
#include "xhci.h"
-DECLARE_GLOBAL_DATA_PTR;
-
struct rockchip_xhci_platdata {
fdt_addr_t hcd_base;
fdt_addr_t phy_base;
#include "xhci.h"
/* Declare global data pointer */
-DECLARE_GLOBAL_DATA_PTR;
-
/* Default to the ZYNQMP XHCI defines */
#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000
#define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC
#include <backlight.h>
#include <asm/gpio.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct gpio_backlight_priv {
struct gpio_desc gpio;
bool def_value;
#define DP_MAX_LANE_COUNT 0x002
#define DP_MAX_LANE_COUNT_MASK 0x1f
-DECLARE_GLOBAL_DATA_PTR;
-
struct anx6345_priv {
u8 edid[EDID_SIZE];
};
#include "exynos_dp_lowlevel.h"
/* Declare global data pointer */
-DECLARE_GLOBAL_DATA_PTR;
-
static void exynos_dp_enable_video_input(struct exynos_dp *dp_regs,
unsigned int enable)
{
struct chan_param_mem_interleaved ip;
};
-DECLARE_GLOBAL_DATA_PTR;
-
/* graphics setup */
static GraphicDevice panel;
static struct ctfb_res_modes *mode;
#include <asm/gpio.h>
#include <power/regulator.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct pwm_backlight_priv {
struct udevice *reg;
struct gpio_desc enable;
#include <asm/arch/grf_rk3288.h>
#include <asm/arch/rockchip_mipi_dsi.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define MHz 1000000
/* Select mipi dsi source, big or little vop */
#include <asm/arch/grf_rk3399.h>
#include <asm/arch/rockchip_mipi_dsi.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Select mipi dsi source, big or little vop */
static int rk_mipi_dsi_source_select(struct udevice *dev)
{
#include <asm/arch/grf_rk3288.h>
#include <dt-bindings/clock/rk3288-cru.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define MAX_CR_LOOP 5
#define MAX_EQ_LOOP 5
#define DP_LINK_STATUS_SIZE 6
#include <asm/gpio.h>
#include <power/regulator.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct simple_panel_priv {
struct udevice *reg;
struct udevice *backlight;
#include <dm/uclass-internal.h>
#include "displayport.h"
-DECLARE_GLOBAL_DATA_PTR;
-
/* return in 1000ths of a Hertz */
static int tegra_dc_calc_refresh(const struct display_timing *timing)
{
#include "sor.h"
#include "displayport.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#define DO_FAST_LINK_TRAINING 1
struct tegra_dp_plat {
#include "displayport.h"
#include "sor.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#define DEBUG_SOR 0
#define APBDEV_PMC_DPD_SAMPLE 0x20
#define WDT_AST2500 2500
#define WDT_AST2400 2400
-DECLARE_GLOBAL_DATA_PTR;
-
struct ast_wdt_priv {
struct ast_wdt *regs;
};
#include <asm/cpm_8xx.h>
#include <asm/io.h>
-DECLARE_GLOBAL_DATA_PTR;
-
void hw_watchdog_reset(void)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
#include <wdt.h>
#include <asm/state.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static int sandbox_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
{
struct sandbox_state *state = state_get_current();
#define WDG_32KHZ_CLK (0x2)
#define WDG_EXT_CLK (0x3)
-DECLARE_GLOBAL_DATA_PTR;
-
void hw_watchdog_set_timeout(u16 val)
{
/* setting timeout value */
#include <dm/device-internal.h>
#include <dm/lists.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
{
const struct wdt_ops *ops = device_get_ops(dev);
#include <ext4fs.h>
#include <mmc.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_CMD_SAVEENV
static int env_ext4_save(void)
{
# endif
#endif
-DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CMD_SAVEENV
static int env_fat_save(void)
{
#error CONFIG_ENV_OFFSET or CONFIG_ENV_SIZE not defined
#endif
-DECLARE_GLOBAL_DATA_PTR;
-
__weak int sata_get_env_dev(void)
{
return CONFIG_SYS_SATA_ENV_DEV;
#include <efi.h>
#include <efi_api.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Unfortunately we cannot access any code outside what is built especially
* for the stub. lib/string.c is already being built for the U-Boot payload
#include <linux/err.h>
#include <linux/types.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#ifndef CONFIG_X86
/*
* Problem areas:
#include <pe.h>
#include <asm/global_data.h>
-DECLARE_GLOBAL_DATA_PTR;
-
const efi_guid_t efi_global_variable_guid = EFI_GLOBAL_VARIABLE_GUID;
const efi_guid_t efi_guid_device_path = DEVICE_PATH_GUID;
const efi_guid_t efi_guid_loaded_image = LOADED_IMAGE_GUID;
#include <lcd.h>
#include <malloc.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static const efi_guid_t efi_net_guid = EFI_SIMPLE_NETWORK_GUID;
static const efi_guid_t efi_pxe_guid = EFI_PXE_GUID;
static struct efi_pxe_packet *dhcp_ack;
#include <dm/of_access.h>
#include <linux/err.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static void *unflatten_dt_alloc(void **mem, unsigned long size,
unsigned long align)
{
#include <dm/uclass-internal.h>
#endif
-DECLARE_GLOBAL_DATA_PTR;
-
/**
* smbios_add_string() - add a string to the string area
*
#include "sntp.h"
#endif
-DECLARE_GLOBAL_DATA_PTR;
-
/** BOOTP EXTENTIONS **/
/* Our subnet mask (0=unknown) */
extern int cpu_post_test_string (void);
extern int cpu_post_test_complex (void);
-DECLARE_GLOBAL_DATA_PTR;
-
ulong cpu_post_makecr (long v)
{
ulong cr = 0;
#include <sandbox-adc.h>
#include <test/ut.h>
-DECLARE_GLOBAL_DATA_PTR;
-
static int dm_test_adc_bind(struct unit_test_state *uts)
{
struct udevice *dev;
#include <asm/eth.h>
#include <test/ut.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define DM_TEST_ETH_NUM 4
static int dm_test_eth(struct unit_test_state *uts)
#include <asm/gpio.h>
#include <test/ut.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Test that sandbox GPIOs work correctly */
static int dm_test_gpio(struct unit_test_state *uts)
{
#include <dm/test.h>
#include <test/ut.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Base test of the led uclass */
static int dm_test_led_base(struct unit_test_state *uts)
{
#include <dm/test.h>
#include <test/ut.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Basic test of the mmc uclass. We could expand this by implementing an MMC
* stack for sandbox, or at least implementing the basic operation.
#include <dm/test.h>
#include <test/ut.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Base test of the phy uclass */
static int dm_test_phy_base(struct unit_test_state *uts)
{
#include <power/sandbox_pmic.h>
#include <test/ut.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Test PMIC get method */
static int dm_test_power_pmic_get(struct unit_test_state *uts)
{
#include <dm/test.h>
#include <test/ut.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Basic test of the pwm uclass */
static int dm_test_pwm_base(struct unit_test_state *uts)
{
#include <dm/test.h>
#include <test/ut.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Base test of register maps */
static int dm_test_regmap_base(struct unit_test_state *uts)
{
#include <power/sandbox_pmic.h>
#include <test/ut.h>
-DECLARE_GLOBAL_DATA_PTR;
-
enum {
BUCK1,
BUCK2,
#include <asm/gpio.h>
#include <test/ut.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Test if bus childs got probed propperly*/
static int dm_test_spmi_probe(struct unit_test_state *uts)
{
#include <dm/test.h>
#include <test/ut.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Base test of system controllers */
static int dm_test_syscon_base(struct unit_test_state *uts)
{
#include <dm/test.h>
#include <test/ut.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Basic test of the timer uclass.
*/
#include <dm/uclass-internal.h>
#include <test/ut.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Test that sandbox USB works correctly */
static int dm_test_usb_base(struct unit_test_state *uts)
{
* in sandbox_sdl_sync() would also need to change to handle the different
* surface depth.
*/
-DECLARE_GLOBAL_DATA_PTR;
-
/* Basic test of the video uclass */
static int dm_test_video_base(struct unit_test_state *uts)
{
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