#define portNO_SECURE_CONTEXT 0\r
/*-----------------------------------------------------------*/\r
\r
-/**\r
- * @brief Setup the timer to generate the tick interrupts.\r
- */\r
-static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
-\r
/**\r
* @brief Used to catch tasks that attempt to return from their implementing\r
* function.\r
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
#endif /* configENABLE_FPU */\r
\r
+/**\r
+ * @brief Setup the timer to generate the tick interrupts.\r
+ *\r
+ * The implementation in this file is weak to allow application writers to\r
+ * change the timer used to generate the tick interrupt.\r
+ */\r
+void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Checks whether the current execution context is interrupt.\r
+ *\r
+ * @return pdTRUE if the current execution context is interrupt, pdFALSE\r
+ * otherwise.\r
+ */\r
+BaseType_t xPortIsInsideInterrupt( void );\r
+\r
/**\r
* @brief Yield the processor.\r
*/\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
-static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
{\r
/* Stop and reset the SysTick. */\r
*( portNVIC_SYSTICK_CTRL ) = 0UL;\r
\r
/* Start the timer that generates the tick ISR. Interrupts are disabled\r
* here already. */\r
- prvSetupTimerInterrupt();\r
+ vPortSetupTimerInterrupt();\r
\r
/* Initialize the critical nesting count ready for the first task. */\r
ulCriticalNesting = 0;\r
}\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortIsInsideInterrupt( void )\r
+{\r
+uint32_t ulCurrentInterrupt;\r
+BaseType_t xReturn;\r
+\r
+ /* Obtain the number of the currently executing interrupt. Interrupt Program\r
+ * Status Register (IPSR) holds the exception number of the currently-executing\r
+ * exception or zero for Thread mode.*/\r
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
+\r
+ if( ulCurrentInterrupt == 0 )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdTRUE;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/
\ No newline at end of file
}\r
/*-----------------------------------------------------------*/\r
\r
-uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
{\r
__asm volatile\r
(\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
{\r
__asm volatile\r
(\r
/**\r
* @brief Extern declarations.\r
*/\r
+extern BaseType_t xPortIsInsideInterrupt( void );\r
+\r
extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
\r
extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
\r
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
/**\r
* @brief Critical section management.\r
*/\r
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMask( x )\r
#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
#define portENTER_CRITICAL() vPortEnterCritical()\r
}\r
/*-----------------------------------------------------------*/\r
\r
-uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
{\r
__asm volatile\r
(\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
{\r
__asm volatile\r
(\r
/**\r
* @brief Extern declarations.\r
*/\r
+extern BaseType_t xPortIsInsideInterrupt( void );\r
+\r
extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
\r
extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
\r
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
/**\r
* @brief Critical section management.\r
*/\r
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMask( x )\r
#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
#define portENTER_CRITICAL() vPortEnterCritical()\r
}\r
/*-----------------------------------------------------------*/\r
\r
-uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
{\r
__asm volatile\r
(\r
- " mrs r0, PRIMASK \n"\r
- " cpsid i \n"\r
- " bx lr \n"\r
- ::: "memory"\r
+ " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */\r
+ " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
+ " msr basepri, r1 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
+ " dsb \n"\r
+ " isb \n"\r
+ " bx lr \n" /* Return. */\r
+ :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"\r
);\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
{\r
__asm volatile\r
(\r
- " msr PRIMASK, r0 \n"\r
- " bx lr \n"\r
+ " msr basepri, r0 \n" /* basepri = ulMask. */\r
+ " dsb \n"\r
+ " isb \n"\r
+ " bx lr \n" /* Return. */\r
::: "memory"\r
);\r
}\r
#endif /* configENABLE_MPU */\r
" \n"\r
" select_next_task: \n"\r
- " cpsid i \n"\r
+ " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */\r
+ " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
+ " dsb \n"\r
+ " isb \n"\r
" bl vTaskSwitchContext \n"\r
- " cpsie i \n"\r
+ " mov r0, #0 \n" /* r0 = 0. */\r
+ " msr basepri, r0 \n" /* Enable interrupts. */\r
" \n"\r
" ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
" ldr r3, [r2] \n" /* Read pxCurrentTCB. */\r
"xRNRConst: .word 0xe000ed98 \n"\r
"xRBARConst: .word 0xe000ed9c \n"\r
#endif /* configENABLE_MPU */\r
+ :: "i"( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
);\r
}\r
/*-----------------------------------------------------------*/\r
/**\r
* @brief Extern declarations.\r
*/\r
+extern BaseType_t xPortIsInsideInterrupt( void );\r
+\r
extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
\r
extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
\r
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
/**\r
* @brief Critical section management.\r
*/\r
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
-#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
-#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )\r
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()\r
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )\r
#define portENTER_CRITICAL() vPortEnterCritical()\r
#define portEXIT_CRITICAL() vPortExitCritical()\r
/*-----------------------------------------------------------*/\r
}\r
/*-----------------------------------------------------------*/\r
\r
-uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
{\r
__asm volatile\r
(\r
- " mrs r0, PRIMASK \n"\r
- " cpsid i \n"\r
- " bx lr \n"\r
- ::: "memory"\r
+ " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */\r
+ " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
+ " msr basepri, r1 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
+ " dsb \n"\r
+ " isb \n"\r
+ " bx lr \n" /* Return. */\r
+ :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"\r
);\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
{\r
__asm volatile\r
(\r
- " msr PRIMASK, r0 \n"\r
- " bx lr \n"\r
+ " msr basepri, r0 \n" /* basepri = ulMask. */\r
+ " dsb \n"\r
+ " isb \n"\r
+ " bx lr \n" /* Return. */\r
::: "memory"\r
);\r
}\r
" ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
" str r0, [r1] \n" /* Save the new top of stack in TCB. */\r
" \n"\r
- " cpsid i \n"\r
+ " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */\r
+ " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
+ " dsb \n"\r
+ " isb \n"\r
" bl vTaskSwitchContext \n"\r
- " cpsie i \n"\r
+ " mov r0, #0 \n" /* r0 = 0. */\r
+ " msr basepri, r0 \n" /* Enable interrupts. */\r
" \n"\r
" ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
" ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
"xRNRConst: .word 0xe000ed98 \n"\r
"xRBARConst: .word 0xe000ed9c \n"\r
#endif /* configENABLE_MPU */\r
+ :: "i"( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
);\r
}\r
/*-----------------------------------------------------------*/\r
/**\r
* @brief Extern declarations.\r
*/\r
+extern BaseType_t xPortIsInsideInterrupt( void );\r
+\r
extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
\r
extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
\r
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
/**\r
* @brief Critical section management.\r
*/\r
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
-#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
-#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMask( x )\r
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()\r
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )\r
#define portENTER_CRITICAL() vPortEnterCritical()\r
#define portEXIT_CRITICAL() vPortExitCritical()\r
/*-----------------------------------------------------------*/\r
PUBLIC vRestoreContextOfFirstTask\r
PUBLIC vRaisePrivilege\r
PUBLIC vStartFirstTask\r
- PUBLIC ulSetInterruptMaskFromISR\r
- PUBLIC vClearInterruptMaskFromISR\r
+ PUBLIC ulSetInterruptMask\r
+ PUBLIC vClearInterruptMask\r
PUBLIC PendSV_Handler\r
PUBLIC SVC_Handler\r
PUBLIC vPortFreeSecureContext\r
svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
/*-----------------------------------------------------------*/\r
\r
-ulSetInterruptMaskFromISR:\r
+ulSetInterruptMask:\r
mrs r0, PRIMASK\r
cpsid i\r
bx lr\r
/*-----------------------------------------------------------*/\r
\r
-vClearInterruptMaskFromISR:\r
+vClearInterruptMask:\r
msr PRIMASK, r0\r
bx lr\r
/*-----------------------------------------------------------*/\r
/**\r
* @brief Extern declarations.\r
*/\r
+extern BaseType_t xPortIsInsideInterrupt( void );\r
+\r
extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
\r
extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
\r
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
/**\r
* @brief Critical section management.\r
*/\r
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMask( x )\r
#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
#define portENTER_CRITICAL() vPortEnterCritical()\r
PUBLIC vRestoreContextOfFirstTask\r
PUBLIC vRaisePrivilege\r
PUBLIC vStartFirstTask\r
- PUBLIC ulSetInterruptMaskFromISR\r
- PUBLIC vClearInterruptMaskFromISR\r
+ PUBLIC ulSetInterruptMask\r
+ PUBLIC vClearInterruptMask\r
PUBLIC PendSV_Handler\r
PUBLIC SVC_Handler\r
\r
nop\r
/*-----------------------------------------------------------*/\r
\r
-ulSetInterruptMaskFromISR:\r
+ulSetInterruptMask:\r
mrs r0, PRIMASK\r
cpsid i\r
bx lr\r
/*-----------------------------------------------------------*/\r
\r
-vClearInterruptMaskFromISR:\r
+vClearInterruptMask:\r
msr PRIMASK, r0\r
bx lr\r
/*-----------------------------------------------------------*/\r
/**\r
* @brief Extern declarations.\r
*/\r
+extern BaseType_t xPortIsInsideInterrupt( void );\r
+\r
extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
\r
extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
\r
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
/**\r
* @brief Critical section management.\r
*/\r
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMask( x )\r
#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
#define portENTER_CRITICAL() vPortEnterCritical()\r
*\r
* 1 tab == 4 spaces!\r
*/\r
+/* Including FreeRTOSConfig.h here will cause build errors if the header file\r
+contains code not understood by the assembler - for example the 'extern' keyword.\r
+To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so\r
+the code is included in C files but excluded by the preprocessor in assembly\r
+files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */\r
+#include "FreeRTOSConfig.h"\r
\r
EXTERN pxCurrentTCB\r
EXTERN xSecureContext\r
PUBLIC vRestoreContextOfFirstTask\r
PUBLIC vRaisePrivilege\r
PUBLIC vStartFirstTask\r
- PUBLIC ulSetInterruptMaskFromISR\r
- PUBLIC vClearInterruptMaskFromISR\r
+ PUBLIC ulSetInterruptMask\r
+ PUBLIC vClearInterruptMask\r
PUBLIC PendSV_Handler\r
PUBLIC SVC_Handler\r
PUBLIC vPortFreeSecureContext\r
svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
/*-----------------------------------------------------------*/\r
\r
-ulSetInterruptMaskFromISR:\r
- mrs r0, PRIMASK\r
- cpsid i\r
- bx lr\r
+ulSetInterruptMask:\r
+ mrs r0, basepri /* r0 = basepri. Return original basepri value. */\r
+ mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
+ msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
+ dsb\r
+ isb\r
+ bx lr /* Return. */\r
/*-----------------------------------------------------------*/\r
\r
-vClearInterruptMaskFromISR:\r
- msr PRIMASK, r0\r
- bx lr\r
+vClearInterruptMask:\r
+ msr basepri, r0 /* basepri = ulMask. */\r
+ dsb\r
+ isb\r
+ bx lr /* Return. */\r
/*-----------------------------------------------------------*/\r
\r
PendSV_Handler:\r
#endif /* configENABLE_MPU */\r
\r
select_next_task:\r
- cpsid i\r
+ mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
+ msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
+ dsb\r
+ isb\r
bl vTaskSwitchContext\r
- cpsie i\r
+ mov r0, #0 /* r0 = 0. */\r
+ msr basepri, r0 /* Enable interrupts. */\r
\r
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
ldr r3, [r2] /* Read pxCurrentTCB. */\r
/**\r
* @brief Extern declarations.\r
*/\r
+extern BaseType_t xPortIsInsideInterrupt( void );\r
+\r
extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
\r
extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
\r
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
/**\r
* @brief Critical section management.\r
*/\r
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
-#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
-#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMask( x )\r
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()\r
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )\r
#define portENTER_CRITICAL() vPortEnterCritical()\r
#define portEXIT_CRITICAL() vPortExitCritical()\r
/*-----------------------------------------------------------*/\r
*\r
* 1 tab == 4 spaces!\r
*/\r
+/* Including FreeRTOSConfig.h here will cause build errors if the header file\r
+contains code not understood by the assembler - for example the 'extern' keyword.\r
+To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so\r
+the code is included in C files but excluded by the preprocessor in assembly\r
+files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */\r
+#include "FreeRTOSConfig.h"\r
\r
EXTERN pxCurrentTCB\r
EXTERN vTaskSwitchContext\r
PUBLIC vRestoreContextOfFirstTask\r
PUBLIC vRaisePrivilege\r
PUBLIC vStartFirstTask\r
- PUBLIC ulSetInterruptMaskFromISR\r
- PUBLIC vClearInterruptMaskFromISR\r
+ PUBLIC ulSetInterruptMask\r
+ PUBLIC vClearInterruptMask\r
PUBLIC PendSV_Handler\r
PUBLIC SVC_Handler\r
/*-----------------------------------------------------------*/\r
svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
/*-----------------------------------------------------------*/\r
\r
-ulSetInterruptMaskFromISR:\r
- mrs r0, PRIMASK\r
- cpsid i\r
- bx lr\r
+ulSetInterruptMask:\r
+ mrs r0, basepri /* r0 = basepri. Return original basepri value. */\r
+ mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
+ msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
+ dsb\r
+ isb\r
+ bx lr /* Return. */\r
/*-----------------------------------------------------------*/\r
\r
-vClearInterruptMaskFromISR:\r
- msr PRIMASK, r0\r
- bx lr\r
+vClearInterruptMask:\r
+ msr basepri, r0 /* basepri = ulMask. */\r
+ dsb\r
+ isb\r
+ bx lr /* Return. */\r
/*-----------------------------------------------------------*/\r
\r
PendSV_Handler:\r
ldr r1, [r2] /* Read pxCurrentTCB. */\r
str r0, [r1] /* Save the new top of stack in TCB. */\r
\r
- cpsid i\r
+ mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
+ msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
+ dsb\r
+ isb\r
bl vTaskSwitchContext\r
- cpsie i\r
+ mov r0, #0 /* r0 = 0. */\r
+ msr basepri, r0 /* Enable interrupts. */\r
\r
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
ldr r1, [r2] /* Read pxCurrentTCB. */\r
/**\r
* @brief Extern declarations.\r
*/\r
+extern BaseType_t xPortIsInsideInterrupt( void );\r
+\r
extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
\r
extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
\r
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
/**\r
* @brief Critical section management.\r
*/\r
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
-#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
-#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMask( x )\r
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()\r
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )\r
#define portENTER_CRITICAL() vPortEnterCritical()\r
#define portEXIT_CRITICAL() vPortExitCritical()\r
/*-----------------------------------------------------------*/\r
/**\r
* @brief Disables interrupts.\r
*/\r
-uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+uint32_t ulSetInterruptMask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
\r
/**\r
* @brief Enables interrupts.\r
*/\r
-void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+void vClearInterruptMask( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
\r
/**\r
* @brief PendSV Exception handler.\r
#define portNO_SECURE_CONTEXT 0\r
/*-----------------------------------------------------------*/\r
\r
-/**\r
- * @brief Setup the timer to generate the tick interrupts.\r
- */\r
-static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
-\r
/**\r
* @brief Used to catch tasks that attempt to return from their implementing\r
* function.\r
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
#endif /* configENABLE_FPU */\r
\r
+/**\r
+ * @brief Setup the timer to generate the tick interrupts.\r
+ *\r
+ * The implementation in this file is weak to allow application writers to\r
+ * change the timer used to generate the tick interrupt.\r
+ */\r
+void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Checks whether the current execution context is interrupt.\r
+ *\r
+ * @return pdTRUE if the current execution context is interrupt, pdFALSE\r
+ * otherwise.\r
+ */\r
+BaseType_t xPortIsInsideInterrupt( void );\r
+\r
/**\r
* @brief Yield the processor.\r
*/\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
-static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
{\r
/* Stop and reset the SysTick. */\r
*( portNVIC_SYSTICK_CTRL ) = 0UL;\r
\r
/* Start the timer that generates the tick ISR. Interrupts are disabled\r
* here already. */\r
- prvSetupTimerInterrupt();\r
+ vPortSetupTimerInterrupt();\r
\r
/* Initialize the critical nesting count ready for the first task. */\r
ulCriticalNesting = 0;\r
}\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortIsInsideInterrupt( void )\r
+{\r
+uint32_t ulCurrentInterrupt;\r
+BaseType_t xReturn;\r
+\r
+ /* Obtain the number of the currently executing interrupt. Interrupt Program\r
+ * Status Register (IPSR) holds the exception number of the currently-executing\r
+ * exception or zero for Thread mode.*/\r
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
+\r
+ if( ulCurrentInterrupt == 0 )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdTRUE;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/
\ No newline at end of file
}\r
/*-----------------------------------------------------------*/\r
\r
-uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
{\r
__asm volatile\r
(\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
{\r
__asm volatile\r
(\r
/**\r
* @brief Disables interrupts.\r
*/\r
-uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+uint32_t ulSetInterruptMask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
\r
/**\r
* @brief Enables interrupts.\r
*/\r
-void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+void vClearInterruptMask( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
\r
/**\r
* @brief PendSV Exception handler.\r
/**\r
* @brief Extern declarations.\r
*/\r
+extern BaseType_t xPortIsInsideInterrupt( void );\r
+\r
extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
\r
extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
\r
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
/**\r
* @brief Critical section management.\r
*/\r
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMask( x )\r
#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
#define portENTER_CRITICAL() vPortEnterCritical()\r
#define portNO_SECURE_CONTEXT 0\r
/*-----------------------------------------------------------*/\r
\r
-/**\r
- * @brief Setup the timer to generate the tick interrupts.\r
- */\r
-static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
-\r
/**\r
* @brief Used to catch tasks that attempt to return from their implementing\r
* function.\r
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
#endif /* configENABLE_FPU */\r
\r
+/**\r
+ * @brief Setup the timer to generate the tick interrupts.\r
+ *\r
+ * The implementation in this file is weak to allow application writers to\r
+ * change the timer used to generate the tick interrupt.\r
+ */\r
+void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Checks whether the current execution context is interrupt.\r
+ *\r
+ * @return pdTRUE if the current execution context is interrupt, pdFALSE\r
+ * otherwise.\r
+ */\r
+BaseType_t xPortIsInsideInterrupt( void );\r
+\r
/**\r
* @brief Yield the processor.\r
*/\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
-static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
{\r
/* Stop and reset the SysTick. */\r
*( portNVIC_SYSTICK_CTRL ) = 0UL;\r
\r
/* Start the timer that generates the tick ISR. Interrupts are disabled\r
* here already. */\r
- prvSetupTimerInterrupt();\r
+ vPortSetupTimerInterrupt();\r
\r
/* Initialize the critical nesting count ready for the first task. */\r
ulCriticalNesting = 0;\r
}\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortIsInsideInterrupt( void )\r
+{\r
+uint32_t ulCurrentInterrupt;\r
+BaseType_t xReturn;\r
+\r
+ /* Obtain the number of the currently executing interrupt. Interrupt Program\r
+ * Status Register (IPSR) holds the exception number of the currently-executing\r
+ * exception or zero for Thread mode.*/\r
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
+\r
+ if( ulCurrentInterrupt == 0 )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdTRUE;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/
\ No newline at end of file
}\r
/*-----------------------------------------------------------*/\r
\r
-uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
{\r
__asm volatile\r
(\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
{\r
__asm volatile\r
(\r
/**\r
* @brief Disables interrupts.\r
*/\r
-uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+uint32_t ulSetInterruptMask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
\r
/**\r
* @brief Enables interrupts.\r
*/\r
-void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+void vClearInterruptMask( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
\r
/**\r
* @brief PendSV Exception handler.\r
/**\r
* @brief Extern declarations.\r
*/\r
+extern BaseType_t xPortIsInsideInterrupt( void );\r
+\r
extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
\r
extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
\r
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
/**\r
* @brief Critical section management.\r
*/\r
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMask( x )\r
#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
#define portENTER_CRITICAL() vPortEnterCritical()\r
#define portNO_SECURE_CONTEXT 0\r
/*-----------------------------------------------------------*/\r
\r
-/**\r
- * @brief Setup the timer to generate the tick interrupts.\r
- */\r
-static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
-\r
/**\r
* @brief Used to catch tasks that attempt to return from their implementing\r
* function.\r
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
#endif /* configENABLE_FPU */\r
\r
+/**\r
+ * @brief Setup the timer to generate the tick interrupts.\r
+ *\r
+ * The implementation in this file is weak to allow application writers to\r
+ * change the timer used to generate the tick interrupt.\r
+ */\r
+void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Checks whether the current execution context is interrupt.\r
+ *\r
+ * @return pdTRUE if the current execution context is interrupt, pdFALSE\r
+ * otherwise.\r
+ */\r
+BaseType_t xPortIsInsideInterrupt( void );\r
+\r
/**\r
* @brief Yield the processor.\r
*/\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
-static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
{\r
/* Stop and reset the SysTick. */\r
*( portNVIC_SYSTICK_CTRL ) = 0UL;\r
\r
/* Start the timer that generates the tick ISR. Interrupts are disabled\r
* here already. */\r
- prvSetupTimerInterrupt();\r
+ vPortSetupTimerInterrupt();\r
\r
/* Initialize the critical nesting count ready for the first task. */\r
ulCriticalNesting = 0;\r
}\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortIsInsideInterrupt( void )\r
+{\r
+uint32_t ulCurrentInterrupt;\r
+BaseType_t xReturn;\r
+\r
+ /* Obtain the number of the currently executing interrupt. Interrupt Program\r
+ * Status Register (IPSR) holds the exception number of the currently-executing\r
+ * exception or zero for Thread mode.*/\r
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
+\r
+ if( ulCurrentInterrupt == 0 )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdTRUE;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/
\ No newline at end of file
}\r
/*-----------------------------------------------------------*/\r
\r
-uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
{\r
__asm volatile\r
(\r
- " mrs r0, PRIMASK \n"\r
- " cpsid i \n"\r
- " bx lr \n"\r
- ::: "memory"\r
+ " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */\r
+ " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
+ " msr basepri, r1 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
+ " dsb \n"\r
+ " isb \n"\r
+ " bx lr \n" /* Return. */\r
+ :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"\r
);\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
{\r
__asm volatile\r
(\r
- " msr PRIMASK, r0 \n"\r
- " bx lr \n"\r
+ " msr basepri, r0 \n" /* basepri = ulMask. */\r
+ " dsb \n"\r
+ " isb \n"\r
+ " bx lr \n" /* Return. */\r
::: "memory"\r
);\r
}\r
#endif /* configENABLE_MPU */\r
" \n"\r
" select_next_task: \n"\r
- " cpsid i \n"\r
+ " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */\r
+ " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
+ " dsb \n"\r
+ " isb \n"\r
" bl vTaskSwitchContext \n"\r
- " cpsie i \n"\r
+ " mov r0, #0 \n" /* r0 = 0. */\r
+ " msr basepri, r0 \n" /* Enable interrupts. */\r
" \n"\r
" ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
" ldr r3, [r2] \n" /* Read pxCurrentTCB. */\r
"xRNRConst: .word 0xe000ed98 \n"\r
"xRBARConst: .word 0xe000ed9c \n"\r
#endif /* configENABLE_MPU */\r
+ :: "i"( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
);\r
}\r
/*-----------------------------------------------------------*/\r
/**\r
* @brief Disables interrupts.\r
*/\r
-uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+uint32_t ulSetInterruptMask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
\r
/**\r
* @brief Enables interrupts.\r
*/\r
-void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+void vClearInterruptMask( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
\r
/**\r
* @brief PendSV Exception handler.\r
/**\r
* @brief Extern declarations.\r
*/\r
+extern BaseType_t xPortIsInsideInterrupt( void );\r
+\r
extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
\r
extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
\r
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
/**\r
* @brief Critical section management.\r
*/\r
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
-#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
-#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )\r
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()\r
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )\r
#define portENTER_CRITICAL() vPortEnterCritical()\r
#define portEXIT_CRITICAL() vPortExitCritical()\r
/*-----------------------------------------------------------*/\r
#define portNO_SECURE_CONTEXT 0\r
/*-----------------------------------------------------------*/\r
\r
-/**\r
- * @brief Setup the timer to generate the tick interrupts.\r
- */\r
-static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
-\r
/**\r
* @brief Used to catch tasks that attempt to return from their implementing\r
* function.\r
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
#endif /* configENABLE_FPU */\r
\r
+/**\r
+ * @brief Setup the timer to generate the tick interrupts.\r
+ *\r
+ * The implementation in this file is weak to allow application writers to\r
+ * change the timer used to generate the tick interrupt.\r
+ */\r
+void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Checks whether the current execution context is interrupt.\r
+ *\r
+ * @return pdTRUE if the current execution context is interrupt, pdFALSE\r
+ * otherwise.\r
+ */\r
+BaseType_t xPortIsInsideInterrupt( void );\r
+\r
/**\r
* @brief Yield the processor.\r
*/\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
-static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
{\r
/* Stop and reset the SysTick. */\r
*( portNVIC_SYSTICK_CTRL ) = 0UL;\r
\r
/* Start the timer that generates the tick ISR. Interrupts are disabled\r
* here already. */\r
- prvSetupTimerInterrupt();\r
+ vPortSetupTimerInterrupt();\r
\r
/* Initialize the critical nesting count ready for the first task. */\r
ulCriticalNesting = 0;\r
}\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortIsInsideInterrupt( void )\r
+{\r
+uint32_t ulCurrentInterrupt;\r
+BaseType_t xReturn;\r
+\r
+ /* Obtain the number of the currently executing interrupt. Interrupt Program\r
+ * Status Register (IPSR) holds the exception number of the currently-executing\r
+ * exception or zero for Thread mode.*/\r
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
+\r
+ if( ulCurrentInterrupt == 0 )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdTRUE;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/
\ No newline at end of file
}\r
/*-----------------------------------------------------------*/\r
\r
-uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
{\r
__asm volatile\r
(\r
- " mrs r0, PRIMASK \n"\r
- " cpsid i \n"\r
- " bx lr \n"\r
- ::: "memory"\r
+ " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */\r
+ " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
+ " msr basepri, r1 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
+ " dsb \n"\r
+ " isb \n"\r
+ " bx lr \n" /* Return. */\r
+ :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"\r
);\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
{\r
__asm volatile\r
(\r
- " msr PRIMASK, r0 \n"\r
- " bx lr \n"\r
+ " msr basepri, r0 \n" /* basepri = ulMask. */\r
+ " dsb \n"\r
+ " isb \n"\r
+ " bx lr \n" /* Return. */\r
::: "memory"\r
);\r
}\r
" ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
" str r0, [r1] \n" /* Save the new top of stack in TCB. */\r
" \n"\r
- " cpsid i \n"\r
+ " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */\r
+ " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
+ " dsb \n"\r
+ " isb \n"\r
" bl vTaskSwitchContext \n"\r
- " cpsie i \n"\r
+ " mov r0, #0 \n" /* r0 = 0. */\r
+ " msr basepri, r0 \n" /* Enable interrupts. */\r
" \n"\r
" ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
" ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
"xRNRConst: .word 0xe000ed98 \n"\r
"xRBARConst: .word 0xe000ed9c \n"\r
#endif /* configENABLE_MPU */\r
+ :: "i"( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
);\r
}\r
/*-----------------------------------------------------------*/\r
/**\r
* @brief Disables interrupts.\r
*/\r
-uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+uint32_t ulSetInterruptMask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
\r
/**\r
* @brief Enables interrupts.\r
*/\r
-void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+void vClearInterruptMask( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
\r
/**\r
* @brief PendSV Exception handler.\r
/**\r
* @brief Extern declarations.\r
*/\r
+extern BaseType_t xPortIsInsideInterrupt( void );\r
+\r
extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
\r
extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
\r
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
/**\r
* @brief Critical section management.\r
*/\r
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
-#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
-#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMask( x )\r
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()\r
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )\r
#define portENTER_CRITICAL() vPortEnterCritical()\r
#define portEXIT_CRITICAL() vPortExitCritical()\r
/*-----------------------------------------------------------*/\r
#define portNO_SECURE_CONTEXT 0\r
/*-----------------------------------------------------------*/\r
\r
-/**\r
- * @brief Setup the timer to generate the tick interrupts.\r
- */\r
-static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
-\r
/**\r
* @brief Used to catch tasks that attempt to return from their implementing\r
* function.\r
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
#endif /* configENABLE_FPU */\r
\r
+/**\r
+ * @brief Setup the timer to generate the tick interrupts.\r
+ *\r
+ * The implementation in this file is weak to allow application writers to\r
+ * change the timer used to generate the tick interrupt.\r
+ */\r
+void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Checks whether the current execution context is interrupt.\r
+ *\r
+ * @return pdTRUE if the current execution context is interrupt, pdFALSE\r
+ * otherwise.\r
+ */\r
+BaseType_t xPortIsInsideInterrupt( void );\r
+\r
/**\r
* @brief Yield the processor.\r
*/\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
-static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
{\r
/* Stop and reset the SysTick. */\r
*( portNVIC_SYSTICK_CTRL ) = 0UL;\r
\r
/* Start the timer that generates the tick ISR. Interrupts are disabled\r
* here already. */\r
- prvSetupTimerInterrupt();\r
+ vPortSetupTimerInterrupt();\r
\r
/* Initialize the critical nesting count ready for the first task. */\r
ulCriticalNesting = 0;\r
}\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortIsInsideInterrupt( void )\r
+{\r
+uint32_t ulCurrentInterrupt;\r
+BaseType_t xReturn;\r
+\r
+ /* Obtain the number of the currently executing interrupt. Interrupt Program\r
+ * Status Register (IPSR) holds the exception number of the currently-executing\r
+ * exception or zero for Thread mode.*/\r
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
+\r
+ if( ulCurrentInterrupt == 0 )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdTRUE;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/
\ No newline at end of file
/**\r
* @brief Disables interrupts.\r
*/\r
-uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+uint32_t ulSetInterruptMask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
\r
/**\r
* @brief Enables interrupts.\r
*/\r
-void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+void vClearInterruptMask( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
\r
/**\r
* @brief PendSV Exception handler.\r
PUBLIC vRestoreContextOfFirstTask\r
PUBLIC vRaisePrivilege\r
PUBLIC vStartFirstTask\r
- PUBLIC ulSetInterruptMaskFromISR\r
- PUBLIC vClearInterruptMaskFromISR\r
+ PUBLIC ulSetInterruptMask\r
+ PUBLIC vClearInterruptMask\r
PUBLIC PendSV_Handler\r
PUBLIC SVC_Handler\r
PUBLIC vPortFreeSecureContext\r
svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
/*-----------------------------------------------------------*/\r
\r
-ulSetInterruptMaskFromISR:\r
+ulSetInterruptMask:\r
mrs r0, PRIMASK\r
cpsid i\r
bx lr\r
/*-----------------------------------------------------------*/\r
\r
-vClearInterruptMaskFromISR:\r
+vClearInterruptMask:\r
msr PRIMASK, r0\r
bx lr\r
/*-----------------------------------------------------------*/\r
/**\r
* @brief Extern declarations.\r
*/\r
+extern BaseType_t xPortIsInsideInterrupt( void );\r
+\r
extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
\r
extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
\r
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
/**\r
* @brief Critical section management.\r
*/\r
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMask( x )\r
#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
#define portENTER_CRITICAL() vPortEnterCritical()\r
#define portNO_SECURE_CONTEXT 0\r
/*-----------------------------------------------------------*/\r
\r
-/**\r
- * @brief Setup the timer to generate the tick interrupts.\r
- */\r
-static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
-\r
/**\r
* @brief Used to catch tasks that attempt to return from their implementing\r
* function.\r
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
#endif /* configENABLE_FPU */\r
\r
+/**\r
+ * @brief Setup the timer to generate the tick interrupts.\r
+ *\r
+ * The implementation in this file is weak to allow application writers to\r
+ * change the timer used to generate the tick interrupt.\r
+ */\r
+void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Checks whether the current execution context is interrupt.\r
+ *\r
+ * @return pdTRUE if the current execution context is interrupt, pdFALSE\r
+ * otherwise.\r
+ */\r
+BaseType_t xPortIsInsideInterrupt( void );\r
+\r
/**\r
* @brief Yield the processor.\r
*/\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
-static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
{\r
/* Stop and reset the SysTick. */\r
*( portNVIC_SYSTICK_CTRL ) = 0UL;\r
\r
/* Start the timer that generates the tick ISR. Interrupts are disabled\r
* here already. */\r
- prvSetupTimerInterrupt();\r
+ vPortSetupTimerInterrupt();\r
\r
/* Initialize the critical nesting count ready for the first task. */\r
ulCriticalNesting = 0;\r
}\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortIsInsideInterrupt( void )\r
+{\r
+uint32_t ulCurrentInterrupt;\r
+BaseType_t xReturn;\r
+\r
+ /* Obtain the number of the currently executing interrupt. Interrupt Program\r
+ * Status Register (IPSR) holds the exception number of the currently-executing\r
+ * exception or zero for Thread mode.*/\r
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
+\r
+ if( ulCurrentInterrupt == 0 )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdTRUE;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/
\ No newline at end of file
/**\r
* @brief Disables interrupts.\r
*/\r
-uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+uint32_t ulSetInterruptMask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
\r
/**\r
* @brief Enables interrupts.\r
*/\r
-void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+void vClearInterruptMask( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
\r
/**\r
* @brief PendSV Exception handler.\r
PUBLIC vRestoreContextOfFirstTask\r
PUBLIC vRaisePrivilege\r
PUBLIC vStartFirstTask\r
- PUBLIC ulSetInterruptMaskFromISR\r
- PUBLIC vClearInterruptMaskFromISR\r
+ PUBLIC ulSetInterruptMask\r
+ PUBLIC vClearInterruptMask\r
PUBLIC PendSV_Handler\r
PUBLIC SVC_Handler\r
\r
nop\r
/*-----------------------------------------------------------*/\r
\r
-ulSetInterruptMaskFromISR:\r
+ulSetInterruptMask:\r
mrs r0, PRIMASK\r
cpsid i\r
bx lr\r
/*-----------------------------------------------------------*/\r
\r
-vClearInterruptMaskFromISR:\r
+vClearInterruptMask:\r
msr PRIMASK, r0\r
bx lr\r
/*-----------------------------------------------------------*/\r
/**\r
* @brief Extern declarations.\r
*/\r
+extern BaseType_t xPortIsInsideInterrupt( void );\r
+\r
extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
\r
extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
\r
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
/**\r
* @brief Critical section management.\r
*/\r
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMask( x )\r
#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
#define portENTER_CRITICAL() vPortEnterCritical()\r
#define portNO_SECURE_CONTEXT 0\r
/*-----------------------------------------------------------*/\r
\r
-/**\r
- * @brief Setup the timer to generate the tick interrupts.\r
- */\r
-static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
-\r
/**\r
* @brief Used to catch tasks that attempt to return from their implementing\r
* function.\r
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
#endif /* configENABLE_FPU */\r
\r
+/**\r
+ * @brief Setup the timer to generate the tick interrupts.\r
+ *\r
+ * The implementation in this file is weak to allow application writers to\r
+ * change the timer used to generate the tick interrupt.\r
+ */\r
+void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Checks whether the current execution context is interrupt.\r
+ *\r
+ * @return pdTRUE if the current execution context is interrupt, pdFALSE\r
+ * otherwise.\r
+ */\r
+BaseType_t xPortIsInsideInterrupt( void );\r
+\r
/**\r
* @brief Yield the processor.\r
*/\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
-static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
{\r
/* Stop and reset the SysTick. */\r
*( portNVIC_SYSTICK_CTRL ) = 0UL;\r
\r
/* Start the timer that generates the tick ISR. Interrupts are disabled\r
* here already. */\r
- prvSetupTimerInterrupt();\r
+ vPortSetupTimerInterrupt();\r
\r
/* Initialize the critical nesting count ready for the first task. */\r
ulCriticalNesting = 0;\r
}\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortIsInsideInterrupt( void )\r
+{\r
+uint32_t ulCurrentInterrupt;\r
+BaseType_t xReturn;\r
+\r
+ /* Obtain the number of the currently executing interrupt. Interrupt Program\r
+ * Status Register (IPSR) holds the exception number of the currently-executing\r
+ * exception or zero for Thread mode.*/\r
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
+\r
+ if( ulCurrentInterrupt == 0 )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdTRUE;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/
\ No newline at end of file
/**\r
* @brief Disables interrupts.\r
*/\r
-uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+uint32_t ulSetInterruptMask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
\r
/**\r
* @brief Enables interrupts.\r
*/\r
-void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+void vClearInterruptMask( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
\r
/**\r
* @brief PendSV Exception handler.\r
* 1 tab == 4 spaces!\r
*/\r
\r
+/* Including FreeRTOSConfig.h here will cause build errors if the header file\r
+contains code not understood by the assembler - for example the 'extern' keyword.\r
+To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so\r
+the code is included in C files but excluded by the preprocessor in assembly\r
+files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */\r
+#include "FreeRTOSConfig.h"\r
+\r
EXTERN pxCurrentTCB\r
EXTERN xSecureContext\r
EXTERN vTaskSwitchContext\r
PUBLIC vRestoreContextOfFirstTask\r
PUBLIC vRaisePrivilege\r
PUBLIC vStartFirstTask\r
- PUBLIC ulSetInterruptMaskFromISR\r
- PUBLIC vClearInterruptMaskFromISR\r
+ PUBLIC ulSetInterruptMask\r
+ PUBLIC vClearInterruptMask\r
PUBLIC PendSV_Handler\r
PUBLIC SVC_Handler\r
PUBLIC vPortFreeSecureContext\r
svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
/*-----------------------------------------------------------*/\r
\r
-ulSetInterruptMaskFromISR:\r
- mrs r0, PRIMASK\r
- cpsid i\r
- bx lr\r
+ulSetInterruptMask:\r
+ mrs r0, basepri /* r0 = basepri. Return original basepri value. */\r
+ mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
+ msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
+ dsb\r
+ isb\r
+ bx lr /* Return. */\r
/*-----------------------------------------------------------*/\r
\r
-vClearInterruptMaskFromISR:\r
- msr PRIMASK, r0\r
- bx lr\r
+vClearInterruptMask:\r
+ msr basepri, r0 /* basepri = ulMask. */\r
+ dsb\r
+ isb\r
+ bx lr /* Return. */\r
/*-----------------------------------------------------------*/\r
\r
PendSV_Handler:\r
#endif /* configENABLE_MPU */\r
\r
select_next_task:\r
- cpsid i\r
+ mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
+ msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
+ dsb\r
+ isb\r
bl vTaskSwitchContext\r
- cpsie i\r
+ mov r0, #0 /* r0 = 0. */\r
+ msr basepri, r0 /* Enable interrupts. */\r
\r
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
ldr r3, [r2] /* Read pxCurrentTCB. */\r
/**\r
* @brief Extern declarations.\r
*/\r
+extern BaseType_t xPortIsInsideInterrupt( void );\r
+\r
extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
\r
extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
\r
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
/**\r
* @brief Critical section management.\r
*/\r
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
-#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
-#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMask( x )\r
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()\r
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )\r
#define portENTER_CRITICAL() vPortEnterCritical()\r
#define portEXIT_CRITICAL() vPortExitCritical()\r
/*-----------------------------------------------------------*/\r
#define portNO_SECURE_CONTEXT 0\r
/*-----------------------------------------------------------*/\r
\r
-/**\r
- * @brief Setup the timer to generate the tick interrupts.\r
- */\r
-static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
-\r
/**\r
* @brief Used to catch tasks that attempt to return from their implementing\r
* function.\r
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
#endif /* configENABLE_FPU */\r
\r
+/**\r
+ * @brief Setup the timer to generate the tick interrupts.\r
+ *\r
+ * The implementation in this file is weak to allow application writers to\r
+ * change the timer used to generate the tick interrupt.\r
+ */\r
+void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Checks whether the current execution context is interrupt.\r
+ *\r
+ * @return pdTRUE if the current execution context is interrupt, pdFALSE\r
+ * otherwise.\r
+ */\r
+BaseType_t xPortIsInsideInterrupt( void );\r
+\r
/**\r
* @brief Yield the processor.\r
*/\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
-static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
{\r
/* Stop and reset the SysTick. */\r
*( portNVIC_SYSTICK_CTRL ) = 0UL;\r
\r
/* Start the timer that generates the tick ISR. Interrupts are disabled\r
* here already. */\r
- prvSetupTimerInterrupt();\r
+ vPortSetupTimerInterrupt();\r
\r
/* Initialize the critical nesting count ready for the first task. */\r
ulCriticalNesting = 0;\r
}\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortIsInsideInterrupt( void )\r
+{\r
+uint32_t ulCurrentInterrupt;\r
+BaseType_t xReturn;\r
+\r
+ /* Obtain the number of the currently executing interrupt. Interrupt Program\r
+ * Status Register (IPSR) holds the exception number of the currently-executing\r
+ * exception or zero for Thread mode.*/\r
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
+\r
+ if( ulCurrentInterrupt == 0 )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdTRUE;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/
\ No newline at end of file
/**\r
* @brief Disables interrupts.\r
*/\r
-uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+uint32_t ulSetInterruptMask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
\r
/**\r
* @brief Enables interrupts.\r
*/\r
-void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+void vClearInterruptMask( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
\r
/**\r
* @brief PendSV Exception handler.\r
* 1 tab == 4 spaces!\r
*/\r
\r
+/* Including FreeRTOSConfig.h here will cause build errors if the header file\r
+contains code not understood by the assembler - for example the 'extern' keyword.\r
+To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so\r
+the code is included in C files but excluded by the preprocessor in assembly\r
+files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */\r
+#include "FreeRTOSConfig.h"\r
+\r
EXTERN pxCurrentTCB\r
EXTERN vTaskSwitchContext\r
EXTERN vPortSVCHandler_C\r
PUBLIC vRestoreContextOfFirstTask\r
PUBLIC vRaisePrivilege\r
PUBLIC vStartFirstTask\r
- PUBLIC ulSetInterruptMaskFromISR\r
- PUBLIC vClearInterruptMaskFromISR\r
+ PUBLIC ulSetInterruptMask\r
+ PUBLIC vClearInterruptMask\r
PUBLIC PendSV_Handler\r
PUBLIC SVC_Handler\r
/*-----------------------------------------------------------*/\r
svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
/*-----------------------------------------------------------*/\r
\r
-ulSetInterruptMaskFromISR:\r
- mrs r0, PRIMASK\r
- cpsid i\r
- bx lr\r
+ulSetInterruptMask:\r
+ mrs r0, basepri /* r0 = basepri. Return original basepri value. */\r
+ mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
+ msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
+ dsb\r
+ isb\r
+ bx lr /* Return. */\r
/*-----------------------------------------------------------*/\r
\r
-vClearInterruptMaskFromISR:\r
- msr PRIMASK, r0\r
- bx lr\r
+vClearInterruptMask:\r
+ msr basepri, r0 /* basepri = ulMask. */\r
+ dsb\r
+ isb\r
+ bx lr /* Return. */\r
/*-----------------------------------------------------------*/\r
\r
PendSV_Handler:\r
ldr r1, [r2] /* Read pxCurrentTCB. */\r
str r0, [r1] /* Save the new top of stack in TCB. */\r
\r
- cpsid i\r
+ mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
+ msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
+ dsb\r
+ isb\r
bl vTaskSwitchContext\r
- cpsie i\r
+ mov r0, #0 /* r0 = 0. */\r
+ msr basepri, r0 /* Enable interrupts. */\r
\r
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
ldr r1, [r2] /* Read pxCurrentTCB. */\r
/**\r
* @brief Extern declarations.\r
*/\r
+extern BaseType_t xPortIsInsideInterrupt( void );\r
+\r
extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
\r
extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
\r
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
/**\r
* @brief Critical section management.\r
*/\r
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
-#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
-#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMask( x )\r
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()\r
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )\r
#define portENTER_CRITICAL() vPortEnterCritical()\r
#define portEXIT_CRITICAL() vPortExitCritical()\r
/*-----------------------------------------------------------*/\r
*\r
* 1 tab == 4 spaces!\r
*/\r
-\r
+/* Including FreeRTOSConfig.h here will cause build errors if the header file\r
+contains code not understood by the assembler - for example the 'extern' keyword.\r
+To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so\r
+the code is included in C files but excluded by the preprocessor in assembly\r
+files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */\r
#include <FreeRTOSConfig.h>\r
\r
RSEG CODE:CODE(2)\r
--- /dev/null
+[{000214A0-0000-0000-C000-000000000046}]\r
+Prop3=19,11\r
+[InternetShortcut]\r
+IDList=\r
+URL=https://www.freertos.org/FreeRTOS-V10.3.x.html\r