-Disassembly Listing for PIC32MEC14xx_RTOSDemo
-Generated From:
-C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/dist/default/debug/PIC32MEC14xx_RTOSDemo.X.debug.elf
-15-Jul-2015 17:16:07
-
---- c:/e/dev/freertos/workingcopy/freertos/source/timers.c --------------------------------------------
+Disassembly Listing for PIC32MEC14xx_RTOSDemo\r
+Generated From:\r
+C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/dist/default/debug/PIC32MEC14xx_RTOSDemo.X.debug.elf\r
+15-Jul-2015 17:16:07\r
+\r
+--- c:/e/dev/freertos/workingcopy/freertos/source/timers.c --------------------------------------------\r
1: /*\r
2: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
3: All rights reserved\r
8: \r
9: FreeRTOS is free software; you can redistribute it and/or modify it under\r
10: the terms of the GNU General Public License (version 2) as published by the\r
-11: Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+11: Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
12: \r
13: ***************************************************************************\r
14: >>! NOTE: The modification to the GPL is included to allow you to !<<\r
239: \r
240: BaseType_t xTimerCreateTimerTask( void )\r
241: {\r
-BFD07A6C 4FE9 ADDIU SP, SP, -48
-BFD07A6E CBEB SW RA, 44(SP)
-BFD07A70 CBCA SW S8, 40(SP)
-BFD07A72 0FDD MOVE S8, SP
+BFD07A6C 4FE9 ADDIU SP, SP, -48\r
+BFD07A6E CBEB SW RA, 44(SP)\r
+BFD07A70 CBCA SW S8, 40(SP)\r
+BFD07A72 0FDD MOVE S8, SP\r
242: BaseType_t xReturn = pdFAIL;\r
-BFD07A74 0020F81E SW ZERO, 32(S8)
+BFD07A74 0020F81E SW ZERO, 32(S8)\r
243: \r
244: /* This function is called when the scheduler is started if\r
245: configUSE_TIMERS is set to 1. Check that the infrastructure used by the\r
246: timer service task has been created/initialised. If timers have already\r
247: been created then the initialisation will already have been performed. */\r
248: prvCheckForValidListAndQueue();\r
-BFD07A78 35F477E8 JALS prvCheckForValidListAndQueue
-BFD07A7A 0C0035F4 LHU T7, 3072(S4)
-BFD07A7C 0C00 NOP
+BFD07A78 35F477E8 JALS prvCheckForValidListAndQueue\r
+BFD07A7A 0C0035F4 LHU T7, 3072(S4)\r
+BFD07A7C 0C00 NOP\r
249: \r
250: if( xTimerQueue != NULL )\r
-BFD07A7E 8068FC5C LW V0, -32664(GP)
-BFD07A82 001540E2 BEQZC V0, 0xBFD07AB0
+BFD07A7E 8068FC5C LW V0, -32664(GP)\r
+BFD07A82 001540E2 BEQZC V0, 0xBFD07AB0\r
251: {\r
252: #if ( INCLUDE_xTimerGetTimerDaemonTaskHandle == 1 )\r
253: {\r
259: {\r
260: /* Create the timer task without storing its handle. */\r
261: xReturn = xTaskCreate( prvTimerTask, "Tmr Svc", ( uint16_t ) configTIMER_TASK_STACK_DEPTH, NULL, ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, NULL);\r
-BFD07A86 ED02 LI V0, 2
-BFD07A88 C844 SW V0, 16(SP)
-BFD07A8A C805 SW ZERO, 20(SP)
-BFD07A8C C806 SW ZERO, 24(SP)
-BFD07A8E C807 SW ZERO, 28(SP)
-BFD07A90 BFD141A2 LUI V0, 0xBFD1
-BFD07A92 3082BFD1 LDC1 F30, 12418(S1)
-BFD07A94 97393082 ADDIU A0, V0, -26823
-BFD07A96 41A29739 BEQ T9, T9, 0xBFD0FDDE
-BFD07A98 BFD141A2 LUI V0, 0xBFD1
-BFD07A9A 30A2BFD1 LDC1 F30, 12450(S1)
-BFD07A9C 9AE030A2 ADDIU A1, V0, -25888
-BFD07A9E 30C09AE0 SWC1 F23, 12480(ZERO)
-BFD07AA0 017C30C0 ADDIU A2, ZERO, 380
-BFD07AA4 0CE0 MOVE A3, ZERO
-BFD07AA6 0A9A77E8 JALS xTaskGenericCreate
-BFD07AA8 0A9A LBU A1, 10(S1)
-BFD07AAA 0C00 NOP
-BFD07AAC 0020F85E SW V0, 32(S8)
+BFD07A86 ED02 LI V0, 2\r
+BFD07A88 C844 SW V0, 16(SP)\r
+BFD07A8A C805 SW ZERO, 20(SP)\r
+BFD07A8C C806 SW ZERO, 24(SP)\r
+BFD07A8E C807 SW ZERO, 28(SP)\r
+BFD07A90 BFD141A2 LUI V0, 0xBFD1\r
+BFD07A92 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD07A94 97393082 ADDIU A0, V0, -26823\r
+BFD07A96 41A29739 BEQ T9, T9, 0xBFD0FDDE\r
+BFD07A98 BFD141A2 LUI V0, 0xBFD1\r
+BFD07A9A 30A2BFD1 LDC1 F30, 12450(S1)\r
+BFD07A9C 9AE030A2 ADDIU A1, V0, -25888\r
+BFD07A9E 30C09AE0 SWC1 F23, 12480(ZERO)\r
+BFD07AA0 017C30C0 ADDIU A2, ZERO, 380\r
+BFD07AA4 0CE0 MOVE A3, ZERO\r
+BFD07AA6 0A9A77E8 JALS xTaskGenericCreate\r
+BFD07AA8 0A9A LBU A1, 10(S1)\r
+BFD07AAA 0C00 NOP\r
+BFD07AAC 0020F85E SW V0, 32(S8)\r
262: }\r
263: #endif\r
264: }\r
268: }\r
269: \r
270: configASSERT( xReturn );\r
-BFD07AB0 0020FC5E LW V0, 32(S8)
-BFD07AB4 000940A2 BNEZC V0, 0xBFD07ACA
-BFD07AB8 BFD141A2 LUI V0, 0xBFD1
-BFD07ABA 3082BFD1 LDC1 F30, 12418(S1)
-BFD07ABC 9AE83082 ADDIU A0, V0, -25880
-BFD07ABE 30A09AE8 SWC1 F23, 12448(T0)
-BFD07AC0 010E30A0 ADDIU A1, ZERO, 270
-BFD07AC4 4B7E77E8 JALS vAssertCalled
-BFD07AC6 4B7E LW K1, 120(SP)
-BFD07AC8 0C00 NOP
+BFD07AB0 0020FC5E LW V0, 32(S8)\r
+BFD07AB4 000940A2 BNEZC V0, 0xBFD07ACA\r
+BFD07AB8 BFD141A2 LUI V0, 0xBFD1\r
+BFD07ABA 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD07ABC 9AE83082 ADDIU A0, V0, -25880\r
+BFD07ABE 30A09AE8 SWC1 F23, 12448(T0)\r
+BFD07AC0 010E30A0 ADDIU A1, ZERO, 270\r
+BFD07AC4 4B7E77E8 JALS vAssertCalled\r
+BFD07AC6 4B7E LW K1, 120(SP)\r
+BFD07AC8 0C00 NOP\r
271: return xReturn;\r
-BFD07ACA 0020FC5E LW V0, 32(S8)
+BFD07ACA 0020FC5E LW V0, 32(S8)\r
272: }\r
-BFD07ACE 0FBE MOVE SP, S8
-BFD07AD0 4BEB LW RA, 44(SP)
-BFD07AD2 4BCA LW S8, 40(SP)
-BFD07AD4 4C19 ADDIU SP, SP, 48
-BFD07AD6 459F JR16 RA
-BFD07AD8 0C00 NOP
+BFD07ACE 0FBE MOVE SP, S8\r
+BFD07AD0 4BEB LW RA, 44(SP)\r
+BFD07AD2 4BCA LW S8, 40(SP)\r
+BFD07AD4 4C19 ADDIU SP, SP, 48\r
+BFD07AD6 459F JR16 RA\r
+BFD07AD8 0C00 NOP\r
273: /*-----------------------------------------------------------*/\r
274: \r
275: TimerHandle_t xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r
276: {\r
-BFD061D8 4FF1 ADDIU SP, SP, -32
-BFD061DA CBE7 SW RA, 28(SP)
-BFD061DC CBC6 SW S8, 24(SP)
-BFD061DE 0FDD MOVE S8, SP
-BFD061E0 0020F89E SW A0, 32(S8)
-BFD061E4 0024F8BE SW A1, 36(S8)
-BFD061E8 0028F8DE SW A2, 40(S8)
-BFD061EC 002CF8FE SW A3, 44(S8)
+BFD061D8 4FF1 ADDIU SP, SP, -32\r
+BFD061DA CBE7 SW RA, 28(SP)\r
+BFD061DC CBC6 SW S8, 24(SP)\r
+BFD061DE 0FDD MOVE S8, SP\r
+BFD061E0 0020F89E SW A0, 32(S8)\r
+BFD061E4 0024F8BE SW A1, 36(S8)\r
+BFD061E8 0028F8DE SW A2, 40(S8)\r
+BFD061EC 002CF8FE SW A3, 44(S8)\r
277: Timer_t *pxNewTimer;\r
278: \r
279: /* Allocate the timer structure. */\r
280: if( xTimerPeriodInTicks == ( TickType_t ) 0U )\r
-BFD061F0 0024FC5E LW V0, 36(S8)
-BFD061F4 000440A2 BNEZC V0, 0xBFD06200
+BFD061F0 0024FC5E LW V0, 36(S8)\r
+BFD061F4 000440A2 BNEZC V0, 0xBFD06200\r
281: {\r
282: pxNewTimer = NULL;\r
-BFD061F8 0010F81E SW ZERO, 16(S8)
-BFD061FC CC2E B 0xBFD0625A
-BFD061FE 0C00 NOP
+BFD061F8 0010F81E SW ZERO, 16(S8)\r
+BFD061FC CC2E B 0xBFD0625A\r
+BFD061FE 0C00 NOP\r
283: }\r
284: else\r
285: {\r
286: pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) );\r
-BFD06200 EE28 LI A0, 40
-BFD06202 111677E8 JALS pvPortMalloc
-BFD06204 0C001116 ADDI T0, S6, 3072
-BFD06206 0C00 NOP
-BFD06208 0010F85E SW V0, 16(S8)
+BFD06200 EE28 LI A0, 40\r
+BFD06202 111677E8 JALS pvPortMalloc\r
+BFD06204 0C001116 ADDI T0, S6, 3072\r
+BFD06206 0C00 NOP\r
+BFD06208 0010F85E SW V0, 16(S8)\r
287: if( pxNewTimer != NULL )\r
-BFD0620C 0010FC5E LW V0, 16(S8)
-BFD06210 002340E2 BEQZC V0, 0xBFD0625A
+BFD0620C 0010FC5E LW V0, 16(S8)\r
+BFD06210 002340E2 BEQZC V0, 0xBFD0625A\r
288: {\r
289: /* Ensure the infrastructure used by the timer service task has been\r
290: created/initialised. */\r
291: prvCheckForValidListAndQueue();\r
-BFD06214 35F477E8 JALS prvCheckForValidListAndQueue
-BFD06216 0C0035F4 LHU T7, 3072(S4)
-BFD06218 0C00 NOP
+BFD06214 35F477E8 JALS prvCheckForValidListAndQueue\r
+BFD06216 0C0035F4 LHU T7, 3072(S4)\r
+BFD06218 0C00 NOP\r
292: \r
293: /* Initialise the timer structure members using the function parameters. */\r
294: pxNewTimer->pcTimerName = pcTimerName;\r
-BFD0621A 0010FC5E LW V0, 16(S8)
-BFD0621E 0020FC7E LW V1, 32(S8)
-BFD06222 E9A0 SW V1, 0(V0)
+BFD0621A 0010FC5E LW V0, 16(S8)\r
+BFD0621E 0020FC7E LW V1, 32(S8)\r
+BFD06222 E9A0 SW V1, 0(V0)\r
295: pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;\r
-BFD06224 0010FC5E LW V0, 16(S8)
-BFD06228 0024FC7E LW V1, 36(S8)
-BFD0622C E9A6 SW V1, 24(V0)
+BFD06224 0010FC5E LW V0, 16(S8)\r
+BFD06228 0024FC7E LW V1, 36(S8)\r
+BFD0622C E9A6 SW V1, 24(V0)\r
296: pxNewTimer->uxAutoReload = uxAutoReload;\r
-BFD0622E 0010FC5E LW V0, 16(S8)
-BFD06232 0028FC7E LW V1, 40(S8)
-BFD06236 E9A7 SW V1, 28(V0)
+BFD0622E 0010FC5E LW V0, 16(S8)\r
+BFD06232 0028FC7E LW V1, 40(S8)\r
+BFD06236 E9A7 SW V1, 28(V0)\r
297: pxNewTimer->pvTimerID = pvTimerID;\r
-BFD06238 0010FC5E LW V0, 16(S8)
-BFD0623C 002CFC7E LW V1, 44(S8)
-BFD06240 E9A8 SW V1, 32(V0)
+BFD06238 0010FC5E LW V0, 16(S8)\r
+BFD0623C 002CFC7E LW V1, 44(S8)\r
+BFD06240 E9A8 SW V1, 32(V0)\r
298: pxNewTimer->pxCallbackFunction = pxCallbackFunction;\r
-BFD06242 0010FC5E LW V0, 16(S8)
-BFD06246 0030FC7E LW V1, 48(S8)
-BFD0624A E9A9 SW V1, 36(V0)
+BFD06242 0010FC5E LW V0, 16(S8)\r
+BFD06246 0030FC7E LW V1, 48(S8)\r
+BFD0624A E9A9 SW V1, 36(V0)\r
299: vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );\r
-BFD0624C 0010FC5E LW V0, 16(S8)
-BFD06250 6D22 ADDIU V0, V0, 4
-BFD06252 0C82 MOVE A0, V0
-BFD06254 4EE677E8 JALS vListInitialiseItem
-BFD06256 4EE6 ADDIU S7, S7, 3
-BFD06258 0C00 NOP
+BFD0624C 0010FC5E LW V0, 16(S8)\r
+BFD06250 6D22 ADDIU V0, V0, 4\r
+BFD06252 0C82 MOVE A0, V0\r
+BFD06254 4EE677E8 JALS vListInitialiseItem\r
+BFD06256 4EE6 ADDIU S7, S7, 3\r
+BFD06258 0C00 NOP\r
300: \r
301: traceTIMER_CREATE( pxNewTimer );\r
302: }\r
308: \r
309: /* 0 is not a valid value for xTimerPeriodInTicks. */\r
310: configASSERT( ( xTimerPeriodInTicks > 0 ) );\r
-BFD0625A 0024FC5E LW V0, 36(S8)
-BFD0625E 000940A2 BNEZC V0, 0xBFD06274
-BFD06262 BFD141A2 LUI V0, 0xBFD1
-BFD06264 3082BFD1 LDC1 F30, 12418(S1)
-BFD06266 9AE83082 ADDIU A0, V0, -25880
-BFD06268 30A09AE8 SWC1 F23, 12448(T0)
-BFD0626A 013630A0 ADDIU A1, ZERO, 310
-BFD0626E 4B7E77E8 JALS vAssertCalled
-BFD06270 4B7E LW K1, 120(SP)
-BFD06272 0C00 NOP
+BFD0625A 0024FC5E LW V0, 36(S8)\r
+BFD0625E 000940A2 BNEZC V0, 0xBFD06274\r
+BFD06262 BFD141A2 LUI V0, 0xBFD1\r
+BFD06264 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD06266 9AE83082 ADDIU A0, V0, -25880\r
+BFD06268 30A09AE8 SWC1 F23, 12448(T0)\r
+BFD0626A 013630A0 ADDIU A1, ZERO, 310\r
+BFD0626E 4B7E77E8 JALS vAssertCalled\r
+BFD06270 4B7E LW K1, 120(SP)\r
+BFD06272 0C00 NOP\r
311: \r
312: return ( TimerHandle_t ) pxNewTimer;\r
-BFD06274 0010FC5E LW V0, 16(S8)
+BFD06274 0010FC5E LW V0, 16(S8)\r
313: }\r
-BFD06278 0FBE MOVE SP, S8
-BFD0627A 4BE7 LW RA, 28(SP)
-BFD0627C 4BC6 LW S8, 24(SP)
-BFD0627E 4C11 ADDIU SP, SP, 32
-BFD06280 459F JR16 RA
-BFD06282 0C00 NOP
+BFD06278 0FBE MOVE SP, S8\r
+BFD0627A 4BE7 LW RA, 28(SP)\r
+BFD0627C 4BC6 LW S8, 24(SP)\r
+BFD0627E 4C11 ADDIU SP, SP, 32\r
+BFD06280 459F JR16 RA\r
+BFD06282 0C00 NOP\r
314: /*-----------------------------------------------------------*/\r
315: \r
316: BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )\r
317: {\r
-BFD05A1C 4FE9 ADDIU SP, SP, -48
-BFD05A1E CBEB SW RA, 44(SP)
-BFD05A20 CBCA SW S8, 40(SP)
-BFD05A22 0FDD MOVE S8, SP
-BFD05A24 0030F89E SW A0, 48(S8)
-BFD05A28 0034F8BE SW A1, 52(S8)
-BFD05A2C 0038F8DE SW A2, 56(S8)
-BFD05A30 003CF8FE SW A3, 60(S8)
+BFD05A1C 4FE9 ADDIU SP, SP, -48\r
+BFD05A1E CBEB SW RA, 44(SP)\r
+BFD05A20 CBCA SW S8, 40(SP)\r
+BFD05A22 0FDD MOVE S8, SP\r
+BFD05A24 0030F89E SW A0, 48(S8)\r
+BFD05A28 0034F8BE SW A1, 52(S8)\r
+BFD05A2C 0038F8DE SW A2, 56(S8)\r
+BFD05A30 003CF8FE SW A3, 60(S8)\r
318: BaseType_t xReturn = pdFAIL;\r
-BFD05A34 0010F81E SW ZERO, 16(S8)
+BFD05A34 0010F81E SW ZERO, 16(S8)\r
319: DaemonTaskMessage_t xMessage;\r
320: \r
321: /* Send a message to the timer service task to perform a particular action\r
322: on a particular timer definition. */\r
323: if( xTimerQueue != NULL )\r
-BFD05A38 8068FC5C LW V0, -32664(GP)
-BFD05A3C 004740E2 BEQZC V0, 0xBFD05ACE
+BFD05A38 8068FC5C LW V0, -32664(GP)\r
+BFD05A3C 004740E2 BEQZC V0, 0xBFD05ACE\r
324: {\r
325: /* Send a command to the timer service task to start the xTimer timer. */\r
326: xMessage.xMessageID = xCommandID;\r
-BFD05A40 0034FC5E LW V0, 52(S8)
-BFD05A44 0014F85E SW V0, 20(S8)
+BFD05A40 0034FC5E LW V0, 52(S8)\r
+BFD05A44 0014F85E SW V0, 20(S8)\r
327: xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;\r
-BFD05A48 0038FC5E LW V0, 56(S8)
-BFD05A4C 0018F85E SW V0, 24(S8)
+BFD05A48 0038FC5E LW V0, 56(S8)\r
+BFD05A4C 0018F85E SW V0, 24(S8)\r
328: xMessage.u.xTimerParameters.pxTimer = ( Timer_t * ) xTimer;\r
-BFD05A50 0030FC5E LW V0, 48(S8)
-BFD05A54 001CF85E SW V0, 28(S8)
+BFD05A50 0030FC5E LW V0, 48(S8)\r
+BFD05A54 001CF85E SW V0, 28(S8)\r
329: \r
330: if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )\r
-BFD05A58 0034FC5E LW V0, 52(S8)
-BFD05A5C 00069042 SLTI V0, V0, 6
-BFD05A60 002740E2 BEQZC V0, 0xBFD05AB2
+BFD05A58 0034FC5E LW V0, 52(S8)\r
+BFD05A5C 00069042 SLTI V0, V0, 6\r
+BFD05A60 002740E2 BEQZC V0, 0xBFD05AB2\r
331: {\r
332: if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )\r
-BFD05A64 4A8E77E8 JALS xTaskGetSchedulerState
-BFD05A66 4A8E LW S4, 56(SP)
-BFD05A68 0C00 NOP
-BFD05A6A 0C62 MOVE V1, V0
-BFD05A6C ED02 LI V0, 2
-BFD05A6E 0011B443 BNE V1, V0, 0xBFD05A94
-BFD05A70 0C000011 SLL ZERO, S1, 1
-BFD05A72 0C00 NOP
+BFD05A64 4A8E77E8 JALS xTaskGetSchedulerState\r
+BFD05A66 4A8E LW S4, 56(SP)\r
+BFD05A68 0C00 NOP\r
+BFD05A6A 0C62 MOVE V1, V0\r
+BFD05A6C ED02 LI V0, 2\r
+BFD05A6E 0011B443 BNE V1, V0, 0xBFD05A94\r
+BFD05A70 0C000011 SLL ZERO, S1, 1\r
+BFD05A72 0C00 NOP\r
333: {\r
334: xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );\r
-BFD05A74 8068FC7C LW V1, -32664(GP)
-BFD05A78 0014305E ADDIU V0, S8, 20
-BFD05A7C 0C83 MOVE A0, V1
-BFD05A7E 0CA2 MOVE A1, V0
-BFD05A80 0040FCDE LW A2, 64(S8)
-BFD05A84 0CE0 MOVE A3, ZERO
-BFD05A86 06A277E8 JALS xQueueGenericSend
-BFD05A88 06A2 ADDU A1, S1, V0
-BFD05A8A 0C00 NOP
-BFD05A8C 0010F85E SW V0, 16(S8)
-BFD05A90 CC1E B 0xBFD05ACE
-BFD05A92 0C00 NOP
+BFD05A74 8068FC7C LW V1, -32664(GP)\r
+BFD05A78 0014305E ADDIU V0, S8, 20\r
+BFD05A7C 0C83 MOVE A0, V1\r
+BFD05A7E 0CA2 MOVE A1, V0\r
+BFD05A80 0040FCDE LW A2, 64(S8)\r
+BFD05A84 0CE0 MOVE A3, ZERO\r
+BFD05A86 06A277E8 JALS xQueueGenericSend\r
+BFD05A88 06A2 ADDU A1, S1, V0\r
+BFD05A8A 0C00 NOP\r
+BFD05A8C 0010F85E SW V0, 16(S8)\r
+BFD05A90 CC1E B 0xBFD05ACE\r
+BFD05A92 0C00 NOP\r
335: }\r
336: else\r
337: {\r
338: xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );\r
-BFD05A94 8068FC7C LW V1, -32664(GP)
-BFD05A98 0014305E ADDIU V0, S8, 20
-BFD05A9C 0C83 MOVE A0, V1
-BFD05A9E 0CA2 MOVE A1, V0
-BFD05AA0 0CC0 MOVE A2, ZERO
-BFD05AA2 0CE0 MOVE A3, ZERO
-BFD05AA4 06A277E8 JALS xQueueGenericSend
-BFD05AA6 06A2 ADDU A1, S1, V0
-BFD05AA8 0C00 NOP
-BFD05AAA 0010F85E SW V0, 16(S8)
-BFD05AAE CC0F B 0xBFD05ACE
-BFD05AB0 0C00 NOP
+BFD05A94 8068FC7C LW V1, -32664(GP)\r
+BFD05A98 0014305E ADDIU V0, S8, 20\r
+BFD05A9C 0C83 MOVE A0, V1\r
+BFD05A9E 0CA2 MOVE A1, V0\r
+BFD05AA0 0CC0 MOVE A2, ZERO\r
+BFD05AA2 0CE0 MOVE A3, ZERO\r
+BFD05AA4 06A277E8 JALS xQueueGenericSend\r
+BFD05AA6 06A2 ADDU A1, S1, V0\r
+BFD05AA8 0C00 NOP\r
+BFD05AAA 0010F85E SW V0, 16(S8)\r
+BFD05AAE CC0F B 0xBFD05ACE\r
+BFD05AB0 0C00 NOP\r
339: }\r
340: }\r
341: else\r
342: {\r
343: xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );\r
-BFD05AB2 8068FC7C LW V1, -32664(GP)
-BFD05AB6 0014305E ADDIU V0, S8, 20
-BFD05ABA 0C83 MOVE A0, V1
-BFD05ABC 0CA2 MOVE A1, V0
-BFD05ABE 003CFCDE LW A2, 60(S8)
-BFD05AC2 0CE0 MOVE A3, ZERO
-BFD05AC4 11EA77E8 JALS xQueueGenericSendFromISR
-BFD05AC6 0C0011EA ADDI T7, T2, 3072
-BFD05AC8 0C00 NOP
-BFD05ACA 0010F85E SW V0, 16(S8)
+BFD05AB2 8068FC7C LW V1, -32664(GP)\r
+BFD05AB6 0014305E ADDIU V0, S8, 20\r
+BFD05ABA 0C83 MOVE A0, V1\r
+BFD05ABC 0CA2 MOVE A1, V0\r
+BFD05ABE 003CFCDE LW A2, 60(S8)\r
+BFD05AC2 0CE0 MOVE A3, ZERO\r
+BFD05AC4 11EA77E8 JALS xQueueGenericSendFromISR\r
+BFD05AC6 0C0011EA ADDI T7, T2, 3072\r
+BFD05AC8 0C00 NOP\r
+BFD05ACA 0010F85E SW V0, 16(S8)\r
344: }\r
345: \r
346: traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );\r
351: }\r
352: \r
353: return xReturn;\r
-BFD05ACE 0010FC5E LW V0, 16(S8)
+BFD05ACE 0010FC5E LW V0, 16(S8)\r
354: }\r
-BFD05AD2 0FBE MOVE SP, S8
-BFD05AD4 4BEB LW RA, 44(SP)
-BFD05AD6 4BCA LW S8, 40(SP)
-BFD05AD8 4C19 ADDIU SP, SP, 48
-BFD05ADA 459F JR16 RA
-BFD05ADC 0C00 NOP
+BFD05AD2 0FBE MOVE SP, S8\r
+BFD05AD4 4BEB LW RA, 44(SP)\r
+BFD05AD6 4BCA LW S8, 40(SP)\r
+BFD05AD8 4C19 ADDIU SP, SP, 48\r
+BFD05ADA 459F JR16 RA\r
+BFD05ADC 0C00 NOP\r
355: /*-----------------------------------------------------------*/\r
356: \r
357: #if ( INCLUDE_xTimerGetTimerDaemonTaskHandle == 1 )\r
369: \r
370: const char * pcTimerGetTimerName( TimerHandle_t xTimer )\r
371: {\r
-BFD09B04 4FF9 ADDIU SP, SP, -16
-BFD09B06 CBC3 SW S8, 12(SP)
-BFD09B08 0FDD MOVE S8, SP
-BFD09B0A 0010F89E SW A0, 16(S8)
+BFD09B04 4FF9 ADDIU SP, SP, -16\r
+BFD09B06 CBC3 SW S8, 12(SP)\r
+BFD09B08 0FDD MOVE S8, SP\r
+BFD09B0A 0010F89E SW A0, 16(S8)\r
372: Timer_t *pxTimer = ( Timer_t * ) xTimer;\r
-BFD09B0E 0010FC5E LW V0, 16(S8)
-BFD09B12 0000F85E SW V0, 0(S8)
+BFD09B0E 0010FC5E LW V0, 16(S8)\r
+BFD09B12 0000F85E SW V0, 0(S8)\r
373: \r
374: return pxTimer->pcTimerName;\r
-BFD09B16 0000FC5E LW V0, 0(S8)
-BFD09B1A 6920 LW V0, 0(V0)
+BFD09B16 0000FC5E LW V0, 0(S8)\r
+BFD09B1A 6920 LW V0, 0(V0)\r
375: }\r
-BFD09B1C 0FBE MOVE SP, S8
-BFD09B1E 4BC3 LW S8, 12(SP)
-BFD09B20 4C09 ADDIU SP, SP, 16
-BFD09B22 459F JR16 RA
-BFD09B24 0C00 NOP
+BFD09B1C 0FBE MOVE SP, S8\r
+BFD09B1E 4BC3 LW S8, 12(SP)\r
+BFD09B20 4C09 ADDIU SP, SP, 16\r
+BFD09B22 459F JR16 RA\r
+BFD09B24 0C00 NOP\r
376: /*-----------------------------------------------------------*/\r
377: \r
378: static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )\r
379: {\r
-BFD05F24 4FED ADDIU SP, SP, -40
-BFD05F26 CBE9 SW RA, 36(SP)
-BFD05F28 CBC8 SW S8, 32(SP)
-BFD05F2A 0FDD MOVE S8, SP
-BFD05F2C 0028F89E SW A0, 40(S8)
-BFD05F30 002CF8BE SW A1, 44(S8)
+BFD05F24 4FED ADDIU SP, SP, -40\r
+BFD05F26 CBE9 SW RA, 36(SP)\r
+BFD05F28 CBC8 SW S8, 32(SP)\r
+BFD05F2A 0FDD MOVE S8, SP\r
+BFD05F2C 0028F89E SW A0, 40(S8)\r
+BFD05F30 002CF8BE SW A1, 44(S8)\r
380: BaseType_t xResult;\r
381: Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );\r
-BFD05F34 8060FC5C LW V0, -32672(GP)
-BFD05F38 6923 LW V0, 12(V0)
-BFD05F3A 6923 LW V0, 12(V0)
-BFD05F3C 0018F85E SW V0, 24(S8)
+BFD05F34 8060FC5C LW V0, -32672(GP)\r
+BFD05F38 6923 LW V0, 12(V0)\r
+BFD05F3A 6923 LW V0, 12(V0)\r
+BFD05F3C 0018F85E SW V0, 24(S8)\r
382: \r
383: /* Remove the timer from the list of active timers. A check has already\r
384: been performed to ensure the list is not empty. */\r
385: ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );\r
-BFD05F40 0018FC5E LW V0, 24(S8)
-BFD05F44 6D22 ADDIU V0, V0, 4
-BFD05F46 0C82 MOVE A0, V0
-BFD05F48 00C877E8 JALS uxListRemove
-BFD05F4A 0C0000C8 SLL A2, T0, 1
-BFD05F4C 0C00 NOP
+BFD05F40 0018FC5E LW V0, 24(S8)\r
+BFD05F44 6D22 ADDIU V0, V0, 4\r
+BFD05F46 0C82 MOVE A0, V0\r
+BFD05F48 00C877E8 JALS uxListRemove\r
+BFD05F4A 0C0000C8 SLL A2, T0, 1\r
+BFD05F4C 0C00 NOP\r
386: traceTIMER_EXPIRED( pxTimer );\r
387: \r
388: /* If the timer is an auto reload timer then calculate the next\r
389: expiry time and re-insert the timer in the list of active timers. */\r
390: if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )\r
-BFD05F4E 0018FC5E LW V0, 24(S8)
-BFD05F52 69A7 LW V1, 28(V0)
-BFD05F54 ED01 LI V0, 1
-BFD05F56 002FB443 BNE V1, V0, 0xBFD05FB8
-BFD05F58 0C00002F SLL AT, T7, 1
-BFD05F5A 0C00 NOP
+BFD05F4E 0018FC5E LW V0, 24(S8)\r
+BFD05F52 69A7 LW V1, 28(V0)\r
+BFD05F54 ED01 LI V0, 1\r
+BFD05F56 002FB443 BNE V1, V0, 0xBFD05FB8\r
+BFD05F58 0C00002F SLL AT, T7, 1\r
+BFD05F5A 0C00 NOP\r
391: {\r
392: /* The timer is inserted into a list using a time relative to anything\r
393: other than the current time. It will therefore be inserted into the\r
394: correct list relative to the time this task thinks it is now. */\r
395: if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) == pdTRUE )\r
-BFD05F5C 0018FC5E LW V0, 24(S8)
-BFD05F60 69A6 LW V1, 24(V0)
-BFD05F62 0028FC5E LW V0, 40(S8)
-BFD05F66 0526 ADDU V0, V1, V0
-BFD05F68 0018FC9E LW A0, 24(S8)
-BFD05F6C 0CA2 MOVE A1, V0
-BFD05F6E 002CFCDE LW A2, 44(S8)
-BFD05F72 0028FCFE LW A3, 40(S8)
-BFD05F76 2BE477E8 JALS prvInsertTimerInActiveList
-BFD05F78 2BE4 LHU A3, 8(A2)
-BFD05F7A 0C00 NOP
-BFD05F7C 0C62 MOVE V1, V0
-BFD05F7E ED01 LI V0, 1
-BFD05F80 001AB443 BNE V1, V0, 0xBFD05FB8
-BFD05F82 0C00001A SLL ZERO, K0, 1
-BFD05F84 0C00 NOP
+BFD05F5C 0018FC5E LW V0, 24(S8)\r
+BFD05F60 69A6 LW V1, 24(V0)\r
+BFD05F62 0028FC5E LW V0, 40(S8)\r
+BFD05F66 0526 ADDU V0, V1, V0\r
+BFD05F68 0018FC9E LW A0, 24(S8)\r
+BFD05F6C 0CA2 MOVE A1, V0\r
+BFD05F6E 002CFCDE LW A2, 44(S8)\r
+BFD05F72 0028FCFE LW A3, 40(S8)\r
+BFD05F76 2BE477E8 JALS prvInsertTimerInActiveList\r
+BFD05F78 2BE4 LHU A3, 8(A2)\r
+BFD05F7A 0C00 NOP\r
+BFD05F7C 0C62 MOVE V1, V0\r
+BFD05F7E ED01 LI V0, 1\r
+BFD05F80 001AB443 BNE V1, V0, 0xBFD05FB8\r
+BFD05F82 0C00001A SLL ZERO, K0, 1\r
+BFD05F84 0C00 NOP\r
396: {\r
397: /* The timer expired before it was added to the active timer\r
398: list. Reload it now. */\r
399: xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );\r
-BFD05F86 C804 SW ZERO, 16(SP)
-BFD05F88 0018FC9E LW A0, 24(S8)
-BFD05F8C 0CA0 MOVE A1, ZERO
-BFD05F8E 0028FCDE LW A2, 40(S8)
-BFD05F92 0CE0 MOVE A3, ZERO
-BFD05F94 2D0E77E8 JALS xTimerGenericCommand
-BFD05F96 2D0E ANDI V0, S0, 0x8000
-BFD05F98 0C00 NOP
-BFD05F9A 001CF85E SW V0, 28(S8)
+BFD05F86 C804 SW ZERO, 16(SP)\r
+BFD05F88 0018FC9E LW A0, 24(S8)\r
+BFD05F8C 0CA0 MOVE A1, ZERO\r
+BFD05F8E 0028FCDE LW A2, 40(S8)\r
+BFD05F92 0CE0 MOVE A3, ZERO\r
+BFD05F94 2D0E77E8 JALS xTimerGenericCommand\r
+BFD05F96 2D0E ANDI V0, S0, 0x8000\r
+BFD05F98 0C00 NOP\r
+BFD05F9A 001CF85E SW V0, 28(S8)\r
400: configASSERT( xResult );\r
-BFD05F9E 001CFC5E LW V0, 28(S8)
-BFD05FA2 000940A2 BNEZC V0, 0xBFD05FB8
-BFD05FA6 BFD141A2 LUI V0, 0xBFD1
-BFD05FA8 3082BFD1 LDC1 F30, 12418(S1)
-BFD05FAA 9AE83082 ADDIU A0, V0, -25880
-BFD05FAC 30A09AE8 SWC1 F23, 12448(T0)
-BFD05FAE 019030A0 ADDIU A1, ZERO, 400
-BFD05FB2 4B7E77E8 JALS vAssertCalled
-BFD05FB4 4B7E LW K1, 120(SP)
-BFD05FB6 0C00 NOP
+BFD05F9E 001CFC5E LW V0, 28(S8)\r
+BFD05FA2 000940A2 BNEZC V0, 0xBFD05FB8\r
+BFD05FA6 BFD141A2 LUI V0, 0xBFD1\r
+BFD05FA8 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD05FAA 9AE83082 ADDIU A0, V0, -25880\r
+BFD05FAC 30A09AE8 SWC1 F23, 12448(T0)\r
+BFD05FAE 019030A0 ADDIU A1, ZERO, 400\r
+BFD05FB2 4B7E77E8 JALS vAssertCalled\r
+BFD05FB4 4B7E LW K1, 120(SP)\r
+BFD05FB6 0C00 NOP\r
401: ( void ) xResult;\r
402: }\r
403: else\r
412: \r
413: /* Call the timer callback. */\r
414: pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );\r
-BFD05FB8 0018FC5E LW V0, 24(S8)
-BFD05FBC 6929 LW V0, 36(V0)
-BFD05FBE 0018FC9E LW A0, 24(S8)
-BFD05FC2 45E2 JALRS16 V0
-BFD05FC4 0C00 NOP
+BFD05FB8 0018FC5E LW V0, 24(S8)\r
+BFD05FBC 6929 LW V0, 36(V0)\r
+BFD05FBE 0018FC9E LW A0, 24(S8)\r
+BFD05FC2 45E2 JALRS16 V0\r
+BFD05FC4 0C00 NOP\r
415: }\r
-BFD05FC6 0FBE MOVE SP, S8
-BFD05FC8 4BE9 LW RA, 36(SP)
-BFD05FCA 4BC8 LW S8, 32(SP)
-BFD05FCC 4C15 ADDIU SP, SP, 40
-BFD05FCE 459F JR16 RA
-BFD05FD0 0C00 NOP
+BFD05FC6 0FBE MOVE SP, S8\r
+BFD05FC8 4BE9 LW RA, 36(SP)\r
+BFD05FCA 4BC8 LW S8, 32(SP)\r
+BFD05FCC 4C15 ADDIU SP, SP, 40\r
+BFD05FCE 459F JR16 RA\r
+BFD05FD0 0C00 NOP\r
416: /*-----------------------------------------------------------*/\r
417: \r
418: static void prvTimerTask( void *pvParameters )\r
419: {\r
-BFD09738 4FF1 ADDIU SP, SP, -32
-BFD0973A CBE7 SW RA, 28(SP)
-BFD0973C CBC6 SW S8, 24(SP)
-BFD0973E 0FDD MOVE S8, SP
-BFD09740 0020F89E SW A0, 32(S8)
+BFD09738 4FF1 ADDIU SP, SP, -32\r
+BFD0973A CBE7 SW RA, 28(SP)\r
+BFD0973C CBC6 SW S8, 24(SP)\r
+BFD0973E 0FDD MOVE S8, SP\r
+BFD09740 0020F89E SW A0, 32(S8)\r
420: TickType_t xNextExpireTime;\r
421: BaseType_t xListWasEmpty;\r
422: \r
428: /* Query the timers list to see if it contains any timers, and if so,\r
429: obtain the time at which the next timer will expire. */\r
430: xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );\r
-BFD09744 0014305E ADDIU V0, S8, 20
-BFD09748 0C82 MOVE A0, V0
-BFD0974A 47EE77E8 JALS prvGetNextExpireTime
-BFD0974E 0C00 NOP
-BFD09750 0010F85E SW V0, 16(S8)
+BFD09744 0014305E ADDIU V0, S8, 20\r
+BFD09748 0C82 MOVE A0, V0\r
+BFD0974A 47EE77E8 JALS prvGetNextExpireTime\r
+BFD0974E 0C00 NOP\r
+BFD09750 0010F85E SW V0, 16(S8)\r
431: \r
432: /* If a timer has expired, process it. Otherwise, block this task\r
433: until either a timer does expire, or a command is received. */\r
434: prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );\r
-BFD09754 0014FC5E LW V0, 20(S8)
-BFD09758 0010FC9E LW A0, 16(S8)
-BFD0975C 0CA2 MOVE A1, V0
-BFD0975E 2D7077E8 JALS prvProcessTimerOrBlockTask
-BFD09760 2D70 ANDI V0, A3, 0x80
-BFD09762 0C00 NOP
+BFD09754 0014FC5E LW V0, 20(S8)\r
+BFD09758 0010FC9E LW A0, 16(S8)\r
+BFD0975C 0CA2 MOVE A1, V0\r
+BFD0975E 2D7077E8 JALS prvProcessTimerOrBlockTask\r
+BFD09760 2D70 ANDI V0, A3, 0x80\r
+BFD09762 0C00 NOP\r
435: \r
436: /* Empty the command queue. */\r
437: prvProcessReceivedCommands();\r
-BFD09764 0B9A77E8 JALS prvProcessReceivedCommands
-BFD09766 0B9A LBU A3, 10(S1)
-BFD09768 0C00 NOP
+BFD09764 0B9A77E8 JALS prvProcessReceivedCommands\r
+BFD09766 0B9A LBU A3, 10(S1)\r
+BFD09768 0C00 NOP\r
438: }\r
-BFD0976A CFEC B 0xBFD09744
-BFD0976C 0C00 NOP
+BFD0976A CFEC B 0xBFD09744\r
+BFD0976C 0C00 NOP\r
439: }\r
440: /*-----------------------------------------------------------*/\r
441: \r
442: static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, const BaseType_t xListWasEmpty )\r
443: {\r
-BFD05AE0 4FED ADDIU SP, SP, -40
-BFD05AE2 CBE9 SW RA, 36(SP)
-BFD05AE4 CBC8 SW S8, 32(SP)
-BFD05AE6 0FDD MOVE S8, SP
-BFD05AE8 0028F89E SW A0, 40(S8)
-BFD05AEC 002CF8BE SW A1, 44(S8)
+BFD05AE0 4FED ADDIU SP, SP, -40\r
+BFD05AE2 CBE9 SW RA, 36(SP)\r
+BFD05AE4 CBC8 SW S8, 32(SP)\r
+BFD05AE6 0FDD MOVE S8, SP\r
+BFD05AE8 0028F89E SW A0, 40(S8)\r
+BFD05AEC 002CF8BE SW A1, 44(S8)\r
444: TickType_t xTimeNow;\r
445: BaseType_t xTimerListsWereSwitched;\r
446: \r
447: vTaskSuspendAll();\r
-BFD05AF0 4EF477E8 JALS vTaskSuspendAll
-BFD05AF2 4EF4 ADDIU S7, S7, -6
-BFD05AF4 0C00 NOP
+BFD05AF0 4EF477E8 JALS vTaskSuspendAll\r
+BFD05AF2 4EF4 ADDIU S7, S7, -6\r
+BFD05AF4 0C00 NOP\r
448: {\r
449: /* Obtain the time now to make an assessment as to whether the timer\r
450: has expired or not. If obtaining the time causes the lists to switch\r
452: when the lists were switched will have been processed within the\r
453: prvSampleTimeNow() function. */\r
454: xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );\r
-BFD05AF6 0018305E ADDIU V0, S8, 24
-BFD05AFA 0C82 MOVE A0, V0
-BFD05AFC 42A877E8 JALS prvSampleTimeNow
-BFD05AFE 0C0042A8 BC2T 2, 0xBFD07302
-BFD05B00 0C00 NOP
-BFD05B02 0010F85E SW V0, 16(S8)
+BFD05AF6 0018305E ADDIU V0, S8, 24\r
+BFD05AFA 0C82 MOVE A0, V0\r
+BFD05AFC 42A877E8 JALS prvSampleTimeNow\r
+BFD05AFE 0C0042A8 BC2T 2, 0xBFD07302\r
+BFD05B00 0C00 NOP\r
+BFD05B02 0010F85E SW V0, 16(S8)\r
455: if( xTimerListsWereSwitched == pdFALSE )\r
-BFD05B06 0018FC5E LW V0, 24(S8)
-BFD05B0A 003D40A2 BNEZC V0, 0xBFD05B88
+BFD05B06 0018FC5E LW V0, 24(S8)\r
+BFD05B0A 003D40A2 BNEZC V0, 0xBFD05B88\r
456: {\r
457: /* The tick count has not overflowed, has the timer expired? */\r
458: if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )\r
-BFD05B0E 002CFC5E LW V0, 44(S8)
-BFD05B12 001440A2 BNEZC V0, 0xBFD05B3E
-BFD05B16 0028FC7E LW V1, 40(S8)
-BFD05B1A 0010FC5E LW V0, 16(S8)
-BFD05B1E 13900062 SLTU V0, V0, V1
-BFD05B20 40A21390 ADDI GP, S0, 16546
-BFD05B22 000C40A2 BNEZC V0, 0xBFD05B3E
+BFD05B0E 002CFC5E LW V0, 44(S8)\r
+BFD05B12 001440A2 BNEZC V0, 0xBFD05B3E\r
+BFD05B16 0028FC7E LW V1, 40(S8)\r
+BFD05B1A 0010FC5E LW V0, 16(S8)\r
+BFD05B1E 13900062 SLTU V0, V0, V1\r
+BFD05B20 40A21390 ADDI GP, S0, 16546\r
+BFD05B22 000C40A2 BNEZC V0, 0xBFD05B3E\r
459: {\r
460: ( void ) xTaskResumeAll();\r
-BFD05B26 158E77E8 JALS xTaskResumeAll
-BFD05B28 0C00158E LBU T4, 3072(T6)
-BFD05B2A 0C00 NOP
+BFD05B26 158E77E8 JALS xTaskResumeAll\r
+BFD05B28 0C00158E LBU T4, 3072(T6)\r
+BFD05B2A 0C00 NOP\r
461: prvProcessExpiredTimer( xNextExpireTime, xTimeNow );\r
-BFD05B2C 0028FC9E LW A0, 40(S8)
-BFD05B30 0010FCBE LW A1, 16(S8)
-BFD05B34 2F9277E8 JALS prvProcessExpiredTimer
-BFD05B36 2F92 ANDI A3, S1, 0x2
-BFD05B38 0C00 NOP
-BFD05B3A CC2C B 0xBFD05B94
-BFD05B3C 0C00 NOP
+BFD05B2C 0028FC9E LW A0, 40(S8)\r
+BFD05B30 0010FCBE LW A1, 16(S8)\r
+BFD05B34 2F9277E8 JALS prvProcessExpiredTimer\r
+BFD05B36 2F92 ANDI A3, S1, 0x2\r
+BFD05B38 0C00 NOP\r
+BFD05B3A CC2C B 0xBFD05B94\r
+BFD05B3C 0C00 NOP\r
462: }\r
463: else\r
464: {\r
469: be reached unless xNextExpireTime > xTimeNow, except in the\r
470: case when the current timer list is empty. */\r
471: vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );\r
-BFD05B3E 8068FC7C LW V1, -32664(GP)
-BFD05B42 0028FC9E LW A0, 40(S8)
-BFD05B46 0010FC5E LW V0, 16(S8)
-BFD05B4A 0529 SUBU V0, A0, V0
-BFD05B4C 0C83 MOVE A0, V1
-BFD05B4E 0CA2 MOVE A1, V0
-BFD05B50 002CFCDE LW A2, 44(S8)
-BFD05B54 349477E8 JALS vQueueWaitForMessageRestricted
-BFD05B56 0C003494 LHU A0, 3072(S4)
-BFD05B58 0C00 NOP
+BFD05B3E 8068FC7C LW V1, -32664(GP)\r
+BFD05B42 0028FC9E LW A0, 40(S8)\r
+BFD05B46 0010FC5E LW V0, 16(S8)\r
+BFD05B4A 0529 SUBU V0, A0, V0\r
+BFD05B4C 0C83 MOVE A0, V1\r
+BFD05B4E 0CA2 MOVE A1, V0\r
+BFD05B50 002CFCDE LW A2, 44(S8)\r
+BFD05B54 349477E8 JALS vQueueWaitForMessageRestricted\r
+BFD05B56 0C003494 LHU A0, 3072(S4)\r
+BFD05B58 0C00 NOP\r
472: \r
473: if( xTaskResumeAll() == pdFALSE )\r
-BFD05B5A 158E77E8 JALS xTaskResumeAll
-BFD05B5C 0C00158E LBU T4, 3072(T6)
-BFD05B5E 0C00 NOP
-BFD05B60 001740A2 BNEZC V0, 0xBFD05B92
+BFD05B5A 158E77E8 JALS xTaskResumeAll\r
+BFD05B5C 0C00158E LBU T4, 3072(T6)\r
+BFD05B5E 0C00 NOP\r
+BFD05B60 001740A2 BNEZC V0, 0xBFD05B92\r
474: {\r
475: /* Yield to wait for either a command to arrive, or the\r
476: block time to expire. If a command arrived between the\r
477: critical section being exited and this yield then the yield\r
478: will not cause the task to block. */\r
479: portYIELD_WITHIN_API();\r
-BFD05B64 4E7677E8 JALS ulPortGetCP0Cause
-BFD05B66 4E76 ADDIU S3, S3, -5
-BFD05B68 0C00 NOP
-BFD05B6A 0014F85E SW V0, 20(S8)
-BFD05B6E 0014FC5E LW V0, 20(S8)
-BFD05B72 01005042 ORI V0, V0, 256
-BFD05B76 0014F85E SW V0, 20(S8)
-BFD05B7A 0014FC9E LW A0, 20(S8)
-BFD05B7E 4E8677E8 JALS vPortSetCP0Cause
-BFD05B80 4E86 ADDIU S4, S4, 3
-BFD05B82 0C00 NOP
-BFD05B84 CC07 B 0xBFD05B94
-BFD05B86 0C00 NOP
-BFD05B92 0C00 NOP
+BFD05B64 4E7677E8 JALS ulPortGetCP0Cause\r
+BFD05B66 4E76 ADDIU S3, S3, -5\r
+BFD05B68 0C00 NOP\r
+BFD05B6A 0014F85E SW V0, 20(S8)\r
+BFD05B6E 0014FC5E LW V0, 20(S8)\r
+BFD05B72 01005042 ORI V0, V0, 256\r
+BFD05B76 0014F85E SW V0, 20(S8)\r
+BFD05B7A 0014FC9E LW A0, 20(S8)\r
+BFD05B7E 4E8677E8 JALS vPortSetCP0Cause\r
+BFD05B80 4E86 ADDIU S4, S4, 3\r
+BFD05B82 0C00 NOP\r
+BFD05B84 CC07 B 0xBFD05B94\r
+BFD05B86 0C00 NOP\r
+BFD05B92 0C00 NOP\r
480: }\r
481: else\r
482: {\r
487: else\r
488: {\r
489: ( void ) xTaskResumeAll();\r
-BFD05B88 158E77E8 JALS xTaskResumeAll
-BFD05B8A 0C00158E LBU T4, 3072(T6)
-BFD05B8C 0C00 NOP
-BFD05B8E CC02 B 0xBFD05B94
-BFD05B90 0C00 NOP
+BFD05B88 158E77E8 JALS xTaskResumeAll\r
+BFD05B8A 0C00158E LBU T4, 3072(T6)\r
+BFD05B8C 0C00 NOP\r
+BFD05B8E CC02 B 0xBFD05B94\r
+BFD05B90 0C00 NOP\r
490: }\r
491: }\r
492: }\r
-BFD05B94 0FBE MOVE SP, S8
-BFD05B96 4BE9 LW RA, 36(SP)
-BFD05B98 4BC8 LW S8, 32(SP)
-BFD05B9A 4C15 ADDIU SP, SP, 40
-BFD05B9C 459F JR16 RA
-BFD05B9E 0C00 NOP
+BFD05B94 0FBE MOVE SP, S8\r
+BFD05B96 4BE9 LW RA, 36(SP)\r
+BFD05B98 4BC8 LW S8, 32(SP)\r
+BFD05B9A 4C15 ADDIU SP, SP, 40\r
+BFD05B9C 459F JR16 RA\r
+BFD05B9E 0C00 NOP\r
493: /*-----------------------------------------------------------*/\r
494: \r
495: static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )\r
496: {\r
-BFD08FDC 4FF9 ADDIU SP, SP, -16
-BFD08FDE CBC3 SW S8, 12(SP)
-BFD08FE0 0FDD MOVE S8, SP
-BFD08FE2 0010F89E SW A0, 16(S8)
+BFD08FDC 4FF9 ADDIU SP, SP, -16\r
+BFD08FDE CBC3 SW S8, 12(SP)\r
+BFD08FE0 0FDD MOVE S8, SP\r
+BFD08FE2 0010F89E SW A0, 16(S8)\r
497: TickType_t xNextExpireTime;\r
498: \r
499: /* Timers are listed in expiry time order, with the head of the list\r
504: timer lists will be switched and the next expiry time can be\r
505: re-assessed. */\r
506: *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );\r
-BFD08FE6 8060FC5C LW V0, -32672(GP)
-BFD08FEA 6920 LW V0, 0(V0)
-BFD08FEC 0001B062 SLTIU V1, V0, 1
-BFD08FF0 0010FC5E LW V0, 16(S8)
-BFD08FF4 E9A0 SW V1, 0(V0)
+BFD08FE6 8060FC5C LW V0, -32672(GP)\r
+BFD08FEA 6920 LW V0, 0(V0)\r
+BFD08FEC 0001B062 SLTIU V1, V0, 1\r
+BFD08FF0 0010FC5E LW V0, 16(S8)\r
+BFD08FF4 E9A0 SW V1, 0(V0)\r
507: if( *pxListWasEmpty == pdFALSE )\r
-BFD08FF6 0010FC5E LW V0, 16(S8)
-BFD08FFA 6920 LW V0, 0(V0)
-BFD08FFC 000840A2 BNEZC V0, 0xBFD09010
+BFD08FF6 0010FC5E LW V0, 16(S8)\r
+BFD08FFA 6920 LW V0, 0(V0)\r
+BFD08FFC 000840A2 BNEZC V0, 0xBFD09010\r
508: {\r
509: xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );\r
-BFD09000 8060FC5C LW V0, -32672(GP)
-BFD09004 6923 LW V0, 12(V0)
-BFD09006 6920 LW V0, 0(V0)
-BFD09008 0000F85E SW V0, 0(S8)
-BFD0900C CC03 B 0xBFD09014
-BFD0900E 0C00 NOP
+BFD09000 8060FC5C LW V0, -32672(GP)\r
+BFD09004 6923 LW V0, 12(V0)\r
+BFD09006 6920 LW V0, 0(V0)\r
+BFD09008 0000F85E SW V0, 0(S8)\r
+BFD0900C CC03 B 0xBFD09014\r
+BFD0900E 0C00 NOP\r
510: }\r
511: else\r
512: {\r
513: /* Ensure the task unblocks when the tick count rolls over. */\r
514: xNextExpireTime = ( TickType_t ) 0U;\r
-BFD09010 0000F81E SW ZERO, 0(S8)
+BFD09010 0000F81E SW ZERO, 0(S8)\r
515: }\r
516: \r
517: return xNextExpireTime;\r
-BFD09014 0000FC5E LW V0, 0(S8)
+BFD09014 0000FC5E LW V0, 0(S8)\r
518: }\r
-BFD09018 0FBE MOVE SP, S8
-BFD0901A 4BC3 LW S8, 12(SP)
-BFD0901C 4C09 ADDIU SP, SP, 16
-BFD0901E 459F JR16 RA
-BFD09020 0C00 NOP
+BFD09018 0FBE MOVE SP, S8\r
+BFD0901A 4BC3 LW S8, 12(SP)\r
+BFD0901C 4C09 ADDIU SP, SP, 16\r
+BFD0901E 459F JR16 RA\r
+BFD09020 0C00 NOP\r
519: /*-----------------------------------------------------------*/\r
520: \r
521: static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )\r
522: {\r
-BFD08550 4FF1 ADDIU SP, SP, -32
-BFD08552 CBE7 SW RA, 28(SP)
-BFD08554 CBC6 SW S8, 24(SP)
-BFD08556 0FDD MOVE S8, SP
-BFD08558 0020F89E SW A0, 32(S8)
+BFD08550 4FF1 ADDIU SP, SP, -32\r
+BFD08552 CBE7 SW RA, 28(SP)\r
+BFD08554 CBC6 SW S8, 24(SP)\r
+BFD08556 0FDD MOVE S8, SP\r
+BFD08558 0020F89E SW A0, 32(S8)\r
523: TickType_t xTimeNow;\r
524: PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */\r
525: \r
526: xTimeNow = xTaskGetTickCount();\r
-BFD0855C 4CCA77E8 JALS xTaskGetTickCount
-BFD0855E 4CCA ADDIU A2, A2, 5
-BFD08560 0C00 NOP
-BFD08562 0010F85E SW V0, 16(S8)
+BFD0855C 4CCA77E8 JALS xTaskGetTickCount\r
+BFD0855E 4CCA ADDIU A2, A2, 5\r
+BFD08560 0C00 NOP\r
+BFD08562 0010F85E SW V0, 16(S8)\r
527: \r
528: if( xTimeNow < xLastTime )\r
-BFD08566 806CFC5C LW V0, -32660(GP)
-BFD0856A 0010FC7E LW V1, 16(S8)
-BFD0856E 13900043 SLTU V0, V1, V0
-BFD08570 40E21390 ADDI GP, S0, 16610
-BFD08572 000940E2 BEQZC V0, 0xBFD08588
+BFD08566 806CFC5C LW V0, -32660(GP)\r
+BFD0856A 0010FC7E LW V1, 16(S8)\r
+BFD0856E 13900043 SLTU V0, V1, V0\r
+BFD08570 40E21390 ADDI GP, S0, 16610\r
+BFD08572 000940E2 BEQZC V0, 0xBFD08588\r
529: {\r
530: prvSwitchTimerLists();\r
-BFD08576 1F7877E8 JALS prvSwitchTimerLists
-BFD08578 0C001F78 LB K1, 3072(T8)
-BFD0857A 0C00 NOP
+BFD08576 1F7877E8 JALS prvSwitchTimerLists\r
+BFD08578 0C001F78 LB K1, 3072(T8)\r
+BFD0857A 0C00 NOP\r
531: *pxTimerListsWereSwitched = pdTRUE;\r
-BFD0857C 0020FC5E LW V0, 32(S8)
-BFD08580 ED81 LI V1, 1
-BFD08582 E9A0 SW V1, 0(V0)
-BFD08584 CC04 B 0xBFD0858E
-BFD08586 0C00 NOP
+BFD0857C 0020FC5E LW V0, 32(S8)\r
+BFD08580 ED81 LI V1, 1\r
+BFD08582 E9A0 SW V1, 0(V0)\r
+BFD08584 CC04 B 0xBFD0858E\r
+BFD08586 0C00 NOP\r
532: }\r
533: else\r
534: {\r
535: *pxTimerListsWereSwitched = pdFALSE;\r
-BFD08588 0020FC5E LW V0, 32(S8)
-BFD0858C E820 SW S0, 0(V0)
+BFD08588 0020FC5E LW V0, 32(S8)\r
+BFD0858C E820 SW S0, 0(V0)\r
536: }\r
537: \r
538: xLastTime = xTimeNow;\r
-BFD0858E 0010FC5E LW V0, 16(S8)
-BFD08592 806CF85C SW V0, -32660(GP)
+BFD0858E 0010FC5E LW V0, 16(S8)\r
+BFD08592 806CF85C SW V0, -32660(GP)\r
539: \r
540: return xTimeNow;\r
-BFD08596 0010FC5E LW V0, 16(S8)
+BFD08596 0010FC5E LW V0, 16(S8)\r
541: }\r
-BFD0859A 0FBE MOVE SP, S8
-BFD0859C 4BE7 LW RA, 28(SP)
-BFD0859E 4BC6 LW S8, 24(SP)
-BFD085A0 4C11 ADDIU SP, SP, 32
-BFD085A2 459F JR16 RA
-BFD085A4 0C00 NOP
+BFD0859A 0FBE MOVE SP, S8\r
+BFD0859C 4BE7 LW RA, 28(SP)\r
+BFD0859E 4BC6 LW S8, 24(SP)\r
+BFD085A0 4C11 ADDIU SP, SP, 32\r
+BFD085A2 459F JR16 RA\r
+BFD085A4 0C00 NOP\r
542: /*-----------------------------------------------------------*/\r
543: \r
544: static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )\r
545: {\r
-BFD057C8 4FF1 ADDIU SP, SP, -32
-BFD057CA CBE7 SW RA, 28(SP)
-BFD057CC CBC6 SW S8, 24(SP)
-BFD057CE 0FDD MOVE S8, SP
-BFD057D0 0020F89E SW A0, 32(S8)
-BFD057D4 0024F8BE SW A1, 36(S8)
-BFD057D8 0028F8DE SW A2, 40(S8)
-BFD057DC 002CF8FE SW A3, 44(S8)
+BFD057C8 4FF1 ADDIU SP, SP, -32\r
+BFD057CA CBE7 SW RA, 28(SP)\r
+BFD057CC CBC6 SW S8, 24(SP)\r
+BFD057CE 0FDD MOVE S8, SP\r
+BFD057D0 0020F89E SW A0, 32(S8)\r
+BFD057D4 0024F8BE SW A1, 36(S8)\r
+BFD057D8 0028F8DE SW A2, 40(S8)\r
+BFD057DC 002CF8FE SW A3, 44(S8)\r
546: BaseType_t xProcessTimerNow = pdFALSE;\r
-BFD057E0 0010F81E SW ZERO, 16(S8)
+BFD057E0 0010F81E SW ZERO, 16(S8)\r
547: \r
548: listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );\r
-BFD057E4 0020FC5E LW V0, 32(S8)
-BFD057E8 0024FC7E LW V1, 36(S8)
-BFD057EC E9A1 SW V1, 4(V0)
+BFD057E4 0020FC5E LW V0, 32(S8)\r
+BFD057E8 0024FC7E LW V1, 36(S8)\r
+BFD057EC E9A1 SW V1, 4(V0)\r
549: listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );\r
-BFD057EE 0020FC5E LW V0, 32(S8)
-BFD057F2 0020FC7E LW V1, 32(S8)
-BFD057F6 E9A4 SW V1, 16(V0)
+BFD057EE 0020FC5E LW V0, 32(S8)\r
+BFD057F2 0020FC7E LW V1, 32(S8)\r
+BFD057F6 E9A4 SW V1, 16(V0)\r
550: \r
551: if( xNextExpiryTime <= xTimeNow )\r
-BFD057F8 0024FC7E LW V1, 36(S8)
-BFD057FC 0028FC5E LW V0, 40(S8)
-BFD05800 13900062 SLTU V0, V0, V1
-BFD05802 40A21390 ADDI GP, S0, 16546
-BFD05804 001D40A2 BNEZC V0, 0xBFD05842
+BFD057F8 0024FC7E LW V1, 36(S8)\r
+BFD057FC 0028FC5E LW V0, 40(S8)\r
+BFD05800 13900062 SLTU V0, V0, V1\r
+BFD05802 40A21390 ADDI GP, S0, 16546\r
+BFD05804 001D40A2 BNEZC V0, 0xBFD05842\r
552: {\r
553: /* Has the expiry time elapsed between the command to start/reset a\r
554: timer was issued, and the time the command was processed? */\r
555: if( ( xTimeNow - xCommandTime ) >= pxTimer->xTimerPeriodInTicks )\r
-BFD05808 0028FC7E LW V1, 40(S8)
-BFD0580C 002CFC5E LW V0, 44(S8)
-BFD05810 05A7 SUBU V1, V1, V0
-BFD05812 0020FC5E LW V0, 32(S8)
-BFD05816 6926 LW V0, 24(V0)
-BFD05818 13900043 SLTU V0, V1, V0
-BFD0581A 40A21390 ADDI GP, S0, 16546
-BFD0581C 000540A2 BNEZC V0, 0xBFD0582A
+BFD05808 0028FC7E LW V1, 40(S8)\r
+BFD0580C 002CFC5E LW V0, 44(S8)\r
+BFD05810 05A7 SUBU V1, V1, V0\r
+BFD05812 0020FC5E LW V0, 32(S8)\r
+BFD05816 6926 LW V0, 24(V0)\r
+BFD05818 13900043 SLTU V0, V1, V0\r
+BFD0581A 40A21390 ADDI GP, S0, 16546\r
+BFD0581C 000540A2 BNEZC V0, 0xBFD0582A\r
556: {\r
557: /* The time between a command being issued and the command being\r
558: processed actually exceeds the timers period. */\r
559: xProcessTimerNow = pdTRUE;\r
-BFD05820 ED01 LI V0, 1
-BFD05822 0010F85E SW V0, 16(S8)
-BFD05824 CC2C0010 EXT ZERO, S0, 16, 26
-BFD05826 CC2C B 0xBFD05880
-BFD05828 0C00 NOP
+BFD05820 ED01 LI V0, 1\r
+BFD05822 0010F85E SW V0, 16(S8)\r
+BFD05824 CC2C0010 EXT ZERO, S0, 16, 26\r
+BFD05826 CC2C B 0xBFD05880\r
+BFD05828 0C00 NOP\r
560: }\r
561: else\r
562: {\r
563: vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );\r
-BFD0582A 8064FC7C LW V1, -32668(GP)
-BFD0582E 0020FC5E LW V0, 32(S8)
-BFD05832 6D22 ADDIU V0, V0, 4
-BFD05834 0C83 MOVE A0, V1
-BFD05836 0CA2 MOVE A1, V0
-BFD05838 304077E8 JALS vListInsert
-BFD0583A 0C003040 ADDIU V0, ZERO, 3072
-BFD0583C 0C00 NOP
-BFD0583E CC20 B 0xBFD05880
-BFD05840 0C00 NOP
+BFD0582A 8064FC7C LW V1, -32668(GP)\r
+BFD0582E 0020FC5E LW V0, 32(S8)\r
+BFD05832 6D22 ADDIU V0, V0, 4\r
+BFD05834 0C83 MOVE A0, V1\r
+BFD05836 0CA2 MOVE A1, V0\r
+BFD05838 304077E8 JALS vListInsert\r
+BFD0583A 0C003040 ADDIU V0, ZERO, 3072\r
+BFD0583C 0C00 NOP\r
+BFD0583E CC20 B 0xBFD05880\r
+BFD05840 0C00 NOP\r
564: }\r
565: }\r
566: else\r
567: {\r
568: if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )\r
-BFD05842 0028FC7E LW V1, 40(S8)
-BFD05846 002CFC5E LW V0, 44(S8)
-BFD0584A 13900043 SLTU V0, V1, V0
-BFD0584C 40E21390 ADDI GP, S0, 16610
-BFD0584E 000D40E2 BEQZC V0, 0xBFD0586C
-BFD05852 0024FC7E LW V1, 36(S8)
-BFD05856 002CFC5E LW V0, 44(S8)
-BFD0585A 13900043 SLTU V0, V1, V0
-BFD0585C 40A21390 ADDI GP, S0, 16546
-BFD0585E 000540A2 BNEZC V0, 0xBFD0586C
+BFD05842 0028FC7E LW V1, 40(S8)\r
+BFD05846 002CFC5E LW V0, 44(S8)\r
+BFD0584A 13900043 SLTU V0, V1, V0\r
+BFD0584C 40E21390 ADDI GP, S0, 16610\r
+BFD0584E 000D40E2 BEQZC V0, 0xBFD0586C\r
+BFD05852 0024FC7E LW V1, 36(S8)\r
+BFD05856 002CFC5E LW V0, 44(S8)\r
+BFD0585A 13900043 SLTU V0, V1, V0\r
+BFD0585C 40A21390 ADDI GP, S0, 16546\r
+BFD0585E 000540A2 BNEZC V0, 0xBFD0586C\r
569: {\r
570: /* If, since the command was issued, the tick count has overflowed\r
571: but the expiry time has not, then the timer must have already passed\r
572: its expiry time and should be processed immediately. */\r
573: xProcessTimerNow = pdTRUE;\r
-BFD05862 ED01 LI V0, 1
-BFD05864 0010F85E SW V0, 16(S8)
-BFD05868 CC0B B 0xBFD05880
-BFD0586A 0C00 NOP
+BFD05862 ED01 LI V0, 1\r
+BFD05864 0010F85E SW V0, 16(S8)\r
+BFD05868 CC0B B 0xBFD05880\r
+BFD0586A 0C00 NOP\r
574: }\r
575: else\r
576: {\r
577: vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );\r
-BFD0586C 8060FC7C LW V1, -32672(GP)
-BFD05870 0020FC5E LW V0, 32(S8)
-BFD05874 6D22 ADDIU V0, V0, 4
-BFD05876 0C83 MOVE A0, V1
-BFD05878 0CA2 MOVE A1, V0
-BFD0587A 304077E8 JALS vListInsert
-BFD0587C 0C003040 ADDIU V0, ZERO, 3072
-BFD0587E 0C00 NOP
+BFD0586C 8060FC7C LW V1, -32672(GP)\r
+BFD05870 0020FC5E LW V0, 32(S8)\r
+BFD05874 6D22 ADDIU V0, V0, 4\r
+BFD05876 0C83 MOVE A0, V1\r
+BFD05878 0CA2 MOVE A1, V0\r
+BFD0587A 304077E8 JALS vListInsert\r
+BFD0587C 0C003040 ADDIU V0, ZERO, 3072\r
+BFD0587E 0C00 NOP\r
578: }\r
579: }\r
580: \r
581: return xProcessTimerNow;\r
-BFD05880 0010FC5E LW V0, 16(S8)
+BFD05880 0010FC5E LW V0, 16(S8)\r
582: }\r
-BFD05884 0FBE MOVE SP, S8
-BFD05886 4BE7 LW RA, 28(SP)
-BFD05888 4BC6 LW S8, 24(SP)
-BFD0588A 4C11 ADDIU SP, SP, 32
-BFD0588C 459F JR16 RA
-BFD0588E 0C00 NOP
+BFD05884 0FBE MOVE SP, S8\r
+BFD05886 4BE7 LW RA, 28(SP)\r
+BFD05888 4BC6 LW S8, 24(SP)\r
+BFD0588A 4C11 ADDIU SP, SP, 32\r
+BFD0588C 459F JR16 RA\r
+BFD0588E 0C00 NOP\r
583: /*-----------------------------------------------------------*/\r
584: \r
585: static void prvProcessReceivedCommands( void )\r
586: {\r
-BFD01734 4FDD ADDIU SP, SP, -72
-BFD01736 CBF1 SW RA, 68(SP)
-BFD01738 CBD0 SW S8, 64(SP)
-BFD0173A 0FDD MOVE S8, SP
+BFD01734 4FDD ADDIU SP, SP, -72\r
+BFD01736 CBF1 SW RA, 68(SP)\r
+BFD01738 CBD0 SW S8, 64(SP)\r
+BFD0173A 0FDD MOVE S8, SP\r
587: DaemonTaskMessage_t xMessage;\r
588: Timer_t *pxTimer;\r
589: BaseType_t xTimerListsWereSwitched, xResult;\r
590: TickType_t xTimeNow;\r
591: \r
592: while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */\r
-BFD0173C CCE0 B 0xBFD018FE
-BFD0173E 0C00 NOP
-BFD018FE 8068FC7C LW V1, -32664(GP)
-BFD01902 0028305E ADDIU V0, S8, 40
-BFD01906 0C83 MOVE A0, V1
-BFD01908 0CA2 MOVE A1, V0
-BFD0190A 0CC0 MOVE A2, ZERO
-BFD0190C 0CE0 MOVE A3, ZERO
-BFD0190E 081E77E8 JALS xQueueGenericReceive
-BFD01910 081E LBU S0, 14(S1)
-BFD01912 0C00 NOP
-BFD01914 FF1440A2 BNEZC V0, 0xBFD01740
-BFD01916 0FBEFF14 LW T8, 4030(S4)
+BFD0173C CCE0 B 0xBFD018FE\r
+BFD0173E 0C00 NOP\r
+BFD018FE 8068FC7C LW V1, -32664(GP)\r
+BFD01902 0028305E ADDIU V0, S8, 40\r
+BFD01906 0C83 MOVE A0, V1\r
+BFD01908 0CA2 MOVE A1, V0\r
+BFD0190A 0CC0 MOVE A2, ZERO\r
+BFD0190C 0CE0 MOVE A3, ZERO\r
+BFD0190E 081E77E8 JALS xQueueGenericReceive\r
+BFD01910 081E LBU S0, 14(S1)\r
+BFD01912 0C00 NOP\r
+BFD01914 FF1440A2 BNEZC V0, 0xBFD01740\r
+BFD01916 0FBEFF14 LW T8, 4030(S4)\r
593: {\r
594: #if ( INCLUDE_xTimerPendFunctionCall == 1 )\r
595: {\r
596: /* Negative commands are pended function calls rather than timer\r
597: commands. */\r
598: if( xMessage.xMessageID < ( BaseType_t ) 0 )\r
-BFD01740 0028FC5E LW V0, 40(S8)
-BFD01744 001F4042 BGEZ V0, 0xBFD01786
-BFD01746 0C00001F SLL ZERO, RA, 1
-BFD01748 0C00 NOP
+BFD01740 0028FC5E LW V0, 40(S8)\r
+BFD01744 001F4042 BGEZ V0, 0xBFD01786\r
+BFD01746 0C00001F SLL ZERO, RA, 1\r
+BFD01748 0C00 NOP\r
599: {\r
600: const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );\r
-BFD0174A 0028305E ADDIU V0, S8, 40
-BFD0174E 6D22 ADDIU V0, V0, 4
-BFD01750 0018F85E SW V0, 24(S8)
+BFD0174A 0028305E ADDIU V0, S8, 40\r
+BFD0174E 6D22 ADDIU V0, V0, 4\r
+BFD01750 0018F85E SW V0, 24(S8)\r
601: \r
602: /* The timer uses the xCallbackParameters member to request a\r
603: callback be executed. Check the callback is not NULL. */\r
604: configASSERT( pxCallback );\r
-BFD01754 0018FC5E LW V0, 24(S8)
-BFD01758 000940A2 BNEZC V0, 0xBFD0176E
-BFD0175C BFD141A2 LUI V0, 0xBFD1
-BFD0175E 3082BFD1 LDC1 F30, 12418(S1)
-BFD01760 9AE83082 ADDIU A0, V0, -25880
-BFD01762 30A09AE8 SWC1 F23, 12448(T0)
-BFD01764 025C30A0 ADDIU A1, ZERO, 604
-BFD01768 4B7E77E8 JALS vAssertCalled
-BFD0176A 4B7E LW K1, 120(SP)
-BFD0176C 0C00 NOP
+BFD01754 0018FC5E LW V0, 24(S8)\r
+BFD01758 000940A2 BNEZC V0, 0xBFD0176E\r
+BFD0175C BFD141A2 LUI V0, 0xBFD1\r
+BFD0175E 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD01760 9AE83082 ADDIU A0, V0, -25880\r
+BFD01762 30A09AE8 SWC1 F23, 12448(T0)\r
+BFD01764 025C30A0 ADDIU A1, ZERO, 604\r
+BFD01768 4B7E77E8 JALS vAssertCalled\r
+BFD0176A 4B7E LW K1, 120(SP)\r
+BFD0176C 0C00 NOP\r
605: \r
606: /* Call the function. */\r
607: pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );\r
-BFD0176E 0018FC5E LW V0, 24(S8)
-BFD01772 6920 LW V0, 0(V0)
-BFD01774 0018FC7E LW V1, 24(S8)
-BFD01778 6A31 LW A0, 4(V1)
-BFD0177A 0018FC7E LW V1, 24(S8)
-BFD0177E 69B2 LW V1, 8(V1)
-BFD01780 0CA3 MOVE A1, V1
-BFD01782 45E2 JALRS16 V0
-BFD01784 0C00 NOP
+BFD0176E 0018FC5E LW V0, 24(S8)\r
+BFD01772 6920 LW V0, 0(V0)\r
+BFD01774 0018FC7E LW V1, 24(S8)\r
+BFD01778 6A31 LW A0, 4(V1)\r
+BFD0177A 0018FC7E LW V1, 24(S8)\r
+BFD0177E 69B2 LW V1, 8(V1)\r
+BFD01780 0CA3 MOVE A1, V1\r
+BFD01782 45E2 JALRS16 V0\r
+BFD01784 0C00 NOP\r
608: }\r
609: else\r
610: {\r
616: /* Commands that are positive are timer commands rather than pended\r
617: function calls. */\r
618: if( xMessage.xMessageID >= ( BaseType_t ) 0 )\r
-BFD01786 0028FC5E LW V0, 40(S8)
-BFD0178A 00B84002 BLTZ V0, 0xBFD018FE
-BFD0178C 0C0000B8 SLL A1, T8, 1
-BFD0178E 0C00 NOP
+BFD01786 0028FC5E LW V0, 40(S8)\r
+BFD0178A 00B84002 BLTZ V0, 0xBFD018FE\r
+BFD0178C 0C0000B8 SLL A1, T8, 1\r
+BFD0178E 0C00 NOP\r
619: {\r
620: /* The messages uses the xTimerParameters member to work on a\r
621: software timer. */\r
622: pxTimer = xMessage.u.xTimerParameters.pxTimer;\r
-BFD01790 0030FC5E LW V0, 48(S8)
-BFD01794 001CF85E SW V0, 28(S8)
+BFD01790 0030FC5E LW V0, 48(S8)\r
+BFD01794 001CF85E SW V0, 28(S8)\r
623: \r
624: if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE )\r
-BFD01798 001CFC5E LW V0, 28(S8)
-BFD0179C 6925 LW V0, 20(V0)
-BFD0179E 000740E2 BEQZC V0, 0xBFD017B0
+BFD01798 001CFC5E LW V0, 28(S8)\r
+BFD0179C 6925 LW V0, 20(V0)\r
+BFD0179E 000740E2 BEQZC V0, 0xBFD017B0\r
625: {\r
626: /* The timer is in a list, remove it. */\r
627: ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );\r
-BFD017A2 001CFC5E LW V0, 28(S8)
-BFD017A6 6D22 ADDIU V0, V0, 4
-BFD017A8 0C82 MOVE A0, V0
-BFD017AA 00C877E8 JALS uxListRemove
-BFD017AC 0C0000C8 SLL A2, T0, 1
-BFD017AE 0C00 NOP
+BFD017A2 001CFC5E LW V0, 28(S8)\r
+BFD017A6 6D22 ADDIU V0, V0, 4\r
+BFD017A8 0C82 MOVE A0, V0\r
+BFD017AA 00C877E8 JALS uxListRemove\r
+BFD017AC 0C0000C8 SLL A2, T0, 1\r
+BFD017AE 0C00 NOP\r
628: }\r
629: else\r
630: {\r
640: queue with a time that is ahead of the timer daemon task (because it\r
641: pre-empted the timer daemon task after the xTimeNow value was set). */\r
642: xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );\r
-BFD017B0 0038305E ADDIU V0, S8, 56
-BFD017B4 0C82 MOVE A0, V0
-BFD017B6 42A877E8 JALS prvSampleTimeNow
-BFD017B8 0C0042A8 BC2T 2, 0xBFD02FBC
-BFD017BA 0C00 NOP
-BFD017BC 0020F85E SW V0, 32(S8)
+BFD017B0 0038305E ADDIU V0, S8, 56\r
+BFD017B4 0C82 MOVE A0, V0\r
+BFD017B6 42A877E8 JALS prvSampleTimeNow\r
+BFD017B8 0C0042A8 BC2T 2, 0xBFD02FBC\r
+BFD017BA 0C00 NOP\r
+BFD017BC 0020F85E SW V0, 32(S8)\r
643: \r
644: switch( xMessage.xMessageID )\r
-BFD017C0 0028FC5E LW V0, 40(S8)
-BFD017C4 000AB062 SLTIU V1, V0, 10
-BFD017C8 008C40E3 BEQZC V1, 0xBFD018E4
-BFD017CC 25A4 SLL V1, V0, 2
-BFD017CE BFD041A2 LUI V0, 0xBFD0
-BFD017D0 3042BFD0 LDC1 F30, 12354(S0)
-BFD017D2 17DC3042 ADDIU V0, V0, 6108
-BFD017D4 052617DC LBU S8, 1318(GP)
-BFD017D6 0526 ADDU V0, V1, V0
-BFD017D8 6920 LW V0, 0(V0)
-BFD017DA 45A2 JRC V0
-BFD017DC BFD01805 SB ZERO, -16432(A1)
-BFD017DE 1805BFD0 LDC1 F30, 6149(S0)
-BFD017E0 BFD01805 SB ZERO, -16432(A1)
-BFD017E2 1805BFD0 LDC1 F30, 6149(S0)
-BFD017E4 BFD01805 SB ZERO, -16432(A1)
-BFD017E6 18EBBFD0 LDC1 F30, 6379(S0)
-BFD017E8 BFD018EB SB A3, -16432(T3)
-BFD017EA 188DBFD0 LDC1 F30, 6285(S0)
-BFD017EC BFD0188D SB A0, -16432(T5)
-BFD017EE 18D7BFD0 LDC1 F30, 6359(S0)
-BFD017F0 BFD018D7 SB A2, -16432(S7)
-BFD017F2 1805BFD0 LDC1 F30, 6149(S0)
-BFD017F4 BFD01805 SB ZERO, -16432(A1)
-BFD017F6 1805BFD0 LDC1 F30, 6149(S0)
-BFD017F8 BFD01805 SB ZERO, -16432(A1)
-BFD017FA 18EBBFD0 LDC1 F30, 6379(S0)
-BFD017FC BFD018EB SB A3, -16432(T3)
-BFD017FE 188DBFD0 LDC1 F30, 6285(S0)
-BFD01800 BFD0188D SB A0, -16432(T5)
-BFD01802 FC7EBFD0 LDC1 F30, -898(S0)
+BFD017C0 0028FC5E LW V0, 40(S8)\r
+BFD017C4 000AB062 SLTIU V1, V0, 10\r
+BFD017C8 008C40E3 BEQZC V1, 0xBFD018E4\r
+BFD017CC 25A4 SLL V1, V0, 2\r
+BFD017CE BFD041A2 LUI V0, 0xBFD0\r
+BFD017D0 3042BFD0 LDC1 F30, 12354(S0)\r
+BFD017D2 17DC3042 ADDIU V0, V0, 6108\r
+BFD017D4 052617DC LBU S8, 1318(GP)\r
+BFD017D6 0526 ADDU V0, V1, V0\r
+BFD017D8 6920 LW V0, 0(V0)\r
+BFD017DA 45A2 JRC V0\r
+BFD017DC BFD01805 SB ZERO, -16432(A1)\r
+BFD017DE 1805BFD0 LDC1 F30, 6149(S0)\r
+BFD017E0 BFD01805 SB ZERO, -16432(A1)\r
+BFD017E2 1805BFD0 LDC1 F30, 6149(S0)\r
+BFD017E4 BFD01805 SB ZERO, -16432(A1)\r
+BFD017E6 18EBBFD0 LDC1 F30, 6379(S0)\r
+BFD017E8 BFD018EB SB A3, -16432(T3)\r
+BFD017EA 188DBFD0 LDC1 F30, 6285(S0)\r
+BFD017EC BFD0188D SB A0, -16432(T5)\r
+BFD017EE 18D7BFD0 LDC1 F30, 6359(S0)\r
+BFD017F0 BFD018D7 SB A2, -16432(S7)\r
+BFD017F2 1805BFD0 LDC1 F30, 6149(S0)\r
+BFD017F4 BFD01805 SB ZERO, -16432(A1)\r
+BFD017F6 1805BFD0 LDC1 F30, 6149(S0)\r
+BFD017F8 BFD01805 SB ZERO, -16432(A1)\r
+BFD017FA 18EBBFD0 LDC1 F30, 6379(S0)\r
+BFD017FC BFD018EB SB A3, -16432(T3)\r
+BFD017FE 188DBFD0 LDC1 F30, 6285(S0)\r
+BFD01800 BFD0188D SB A0, -16432(T5)\r
+BFD01802 FC7EBFD0 LDC1 F30, -898(S0)\r
645: {\r
646: case tmrCOMMAND_START :\r
647: case tmrCOMMAND_START_FROM_ISR :\r
650: case tmrCOMMAND_START_DONT_TRACE :\r
651: /* Start or restart a timer. */\r
652: if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) == pdTRUE )\r
-BFD01804 002CFC7E LW V1, 44(S8)
-BFD01808 001CFC5E LW V0, 28(S8)
-BFD0180C 6926 LW V0, 24(V0)
-BFD0180E 05A6 ADDU V1, V1, V0
-BFD01810 002CFC5E LW V0, 44(S8)
-BFD01814 001CFC9E LW A0, 28(S8)
-BFD01818 0CA3 MOVE A1, V1
-BFD0181A 0020FCDE LW A2, 32(S8)
-BFD0181E 0CE2 MOVE A3, V0
-BFD01820 2BE477E8 JALS prvInsertTimerInActiveList
-BFD01822 2BE4 LHU A3, 8(A2)
-BFD01824 0C00 NOP
-BFD01826 0C62 MOVE V1, V0
-BFD01828 ED01 LI V0, 1
-BFD0182A 0061B443 BNE V1, V0, 0xBFD018F0
-BFD0182C 0C000061 SLL V1, AT, 1
-BFD0182E 0C00 NOP
+BFD01804 002CFC7E LW V1, 44(S8)\r
+BFD01808 001CFC5E LW V0, 28(S8)\r
+BFD0180C 6926 LW V0, 24(V0)\r
+BFD0180E 05A6 ADDU V1, V1, V0\r
+BFD01810 002CFC5E LW V0, 44(S8)\r
+BFD01814 001CFC9E LW A0, 28(S8)\r
+BFD01818 0CA3 MOVE A1, V1\r
+BFD0181A 0020FCDE LW A2, 32(S8)\r
+BFD0181E 0CE2 MOVE A3, V0\r
+BFD01820 2BE477E8 JALS prvInsertTimerInActiveList\r
+BFD01822 2BE4 LHU A3, 8(A2)\r
+BFD01824 0C00 NOP\r
+BFD01826 0C62 MOVE V1, V0\r
+BFD01828 ED01 LI V0, 1\r
+BFD0182A 0061B443 BNE V1, V0, 0xBFD018F0\r
+BFD0182C 0C000061 SLL V1, AT, 1\r
+BFD0182E 0C00 NOP\r
653: {\r
654: /* The timer expired before it was added to the active\r
655: timer list. Process it now. */\r
656: pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );\r
-BFD01830 001CFC5E LW V0, 28(S8)
-BFD01834 6929 LW V0, 36(V0)
-BFD01836 001CFC9E LW A0, 28(S8)
-BFD0183A 45E2 JALRS16 V0
-BFD0183C 0C00 NOP
+BFD01830 001CFC5E LW V0, 28(S8)\r
+BFD01834 6929 LW V0, 36(V0)\r
+BFD01836 001CFC9E LW A0, 28(S8)\r
+BFD0183A 45E2 JALRS16 V0\r
+BFD0183C 0C00 NOP\r
657: traceTIMER_EXPIRED( pxTimer );\r
658: \r
659: if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )\r
-BFD0183E 001CFC5E LW V0, 28(S8)
-BFD01842 69A7 LW V1, 28(V0)
-BFD01844 ED01 LI V0, 1
-BFD01846 0056B443 BNE V1, V0, 0xBFD018F6
-BFD01848 0C000056 SLL V0, S6, 1
-BFD0184A 0C00 NOP
+BFD0183E 001CFC5E LW V0, 28(S8)\r
+BFD01842 69A7 LW V1, 28(V0)\r
+BFD01844 ED01 LI V0, 1\r
+BFD01846 0056B443 BNE V1, V0, 0xBFD018F6\r
+BFD01848 0C000056 SLL V0, S6, 1\r
+BFD0184A 0C00 NOP\r
660: {\r
661: xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );\r
-BFD0184C 002CFC7E LW V1, 44(S8)
-BFD01850 001CFC5E LW V0, 28(S8)
-BFD01854 6926 LW V0, 24(V0)
-BFD01856 0526 ADDU V0, V1, V0
-BFD01858 C804 SW ZERO, 16(SP)
-BFD0185A 001CFC9E LW A0, 28(S8)
-BFD0185E 0CA0 MOVE A1, ZERO
-BFD01860 0CC2 MOVE A2, V0
-BFD01862 0CE0 MOVE A3, ZERO
-BFD01864 2D0E77E8 JALS xTimerGenericCommand
-BFD01866 2D0E ANDI V0, S0, 0x8000
-BFD01868 0C00 NOP
-BFD0186A 0024F85E SW V0, 36(S8)
+BFD0184C 002CFC7E LW V1, 44(S8)\r
+BFD01850 001CFC5E LW V0, 28(S8)\r
+BFD01854 6926 LW V0, 24(V0)\r
+BFD01856 0526 ADDU V0, V1, V0\r
+BFD01858 C804 SW ZERO, 16(SP)\r
+BFD0185A 001CFC9E LW A0, 28(S8)\r
+BFD0185E 0CA0 MOVE A1, ZERO\r
+BFD01860 0CC2 MOVE A2, V0\r
+BFD01862 0CE0 MOVE A3, ZERO\r
+BFD01864 2D0E77E8 JALS xTimerGenericCommand\r
+BFD01866 2D0E ANDI V0, S0, 0x8000\r
+BFD01868 0C00 NOP\r
+BFD0186A 0024F85E SW V0, 36(S8)\r
662: configASSERT( xResult );\r
-BFD0186E 0024FC5E LW V0, 36(S8)
-BFD01872 004340A2 BNEZC V0, 0xBFD018FC
-BFD01876 BFD141A2 LUI V0, 0xBFD1
-BFD01878 3082BFD1 LDC1 F30, 12418(S1)
-BFD0187A 9AE83082 ADDIU A0, V0, -25880
-BFD0187C 30A09AE8 SWC1 F23, 12448(T0)
-BFD0187E 029630A0 ADDIU A1, ZERO, 662
-BFD01882 4B7E77E8 JALS vAssertCalled
-BFD01884 4B7E LW K1, 120(SP)
-BFD01886 0C00 NOP
+BFD0186E 0024FC5E LW V0, 36(S8)\r
+BFD01872 004340A2 BNEZC V0, 0xBFD018FC\r
+BFD01876 BFD141A2 LUI V0, 0xBFD1\r
+BFD01878 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD0187A 9AE83082 ADDIU A0, V0, -25880\r
+BFD0187C 30A09AE8 SWC1 F23, 12448(T0)\r
+BFD0187E 029630A0 ADDIU A1, ZERO, 662\r
+BFD01882 4B7E77E8 JALS vAssertCalled\r
+BFD01884 4B7E LW K1, 120(SP)\r
+BFD01886 0C00 NOP\r
663: ( void ) xResult;\r
664: }\r
665: else\r
672: mtCOVERAGE_TEST_MARKER();\r
673: }\r
674: break;\r
-BFD01888 CC3A B 0xBFD018FE
-BFD0188A 0C00 NOP
-BFD018F0 0C00 NOP
-BFD018F2 CC05 B 0xBFD018FE
-BFD018F4 0C00 NOP
-BFD018F6 0C00 NOP
-BFD018F8 CC02 B 0xBFD018FE
-BFD018FA 0C00 NOP
-BFD018FC 0C00 NOP
+BFD01888 CC3A B 0xBFD018FE\r
+BFD0188A 0C00 NOP\r
+BFD018F0 0C00 NOP\r
+BFD018F2 CC05 B 0xBFD018FE\r
+BFD018F4 0C00 NOP\r
+BFD018F6 0C00 NOP\r
+BFD018F8 CC02 B 0xBFD018FE\r
+BFD018FA 0C00 NOP\r
+BFD018FC 0C00 NOP\r
675: \r
676: case tmrCOMMAND_STOP :\r
677: case tmrCOMMAND_STOP_FROM_ISR :\r
678: /* The timer has already been removed from the active list.\r
679: There is nothing to do here. */\r
680: break;\r
-BFD018EA 0C00 NOP
-BFD018EC CC08 B 0xBFD018FE
-BFD018EE 0C00 NOP
+BFD018EA 0C00 NOP\r
+BFD018EC CC08 B 0xBFD018FE\r
+BFD018EE 0C00 NOP\r
681: \r
682: case tmrCOMMAND_CHANGE_PERIOD :\r
683: case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :\r
684: pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;\r
-BFD0188C 002CFC7E LW V1, 44(S8)
-BFD01890 001CFC5E LW V0, 28(S8)
-BFD01894 E9A6 SW V1, 24(V0)
+BFD0188C 002CFC7E LW V1, 44(S8)\r
+BFD01890 001CFC5E LW V0, 28(S8)\r
+BFD01894 E9A6 SW V1, 24(V0)\r
685: configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );\r
-BFD01896 001CFC5E LW V0, 28(S8)
-BFD0189A 6926 LW V0, 24(V0)
-BFD0189C 000940A2 BNEZC V0, 0xBFD018B2
-BFD018A0 BFD141A2 LUI V0, 0xBFD1
-BFD018A2 3082BFD1 LDC1 F30, 12418(S1)
-BFD018A4 9AE83082 ADDIU A0, V0, -25880
-BFD018A6 30A09AE8 SWC1 F23, 12448(T0)
-BFD018A8 02AD30A0 ADDIU A1, ZERO, 685
-BFD018AC 4B7E77E8 JALS vAssertCalled
-BFD018AE 4B7E LW K1, 120(SP)
-BFD018B0 0C00 NOP
+BFD01896 001CFC5E LW V0, 28(S8)\r
+BFD0189A 6926 LW V0, 24(V0)\r
+BFD0189C 000940A2 BNEZC V0, 0xBFD018B2\r
+BFD018A0 BFD141A2 LUI V0, 0xBFD1\r
+BFD018A2 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD018A4 9AE83082 ADDIU A0, V0, -25880\r
+BFD018A6 30A09AE8 SWC1 F23, 12448(T0)\r
+BFD018A8 02AD30A0 ADDIU A1, ZERO, 685\r
+BFD018AC 4B7E77E8 JALS vAssertCalled\r
+BFD018AE 4B7E LW K1, 120(SP)\r
+BFD018B0 0C00 NOP\r
686: \r
687: /* The new period does not really have a reference, and can be\r
688: longer or shorter than the old one. The command time is\r
691: (unlike for the xTimerStart() case above) there is no fail case\r
692: that needs to be handled here. */\r
693: ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );\r
-BFD018B2 001CFC5E LW V0, 28(S8)
-BFD018B6 69A6 LW V1, 24(V0)
-BFD018B8 0020FC5E LW V0, 32(S8)
-BFD018BC 0526 ADDU V0, V1, V0
-BFD018BE 001CFC9E LW A0, 28(S8)
-BFD018C2 0CA2 MOVE A1, V0
-BFD018C4 0020FCDE LW A2, 32(S8)
-BFD018C8 0020FCFE LW A3, 32(S8)
-BFD018CC 2BE477E8 JALS prvInsertTimerInActiveList
-BFD018CE 2BE4 LHU A3, 8(A2)
-BFD018D0 0C00 NOP
+BFD018B2 001CFC5E LW V0, 28(S8)\r
+BFD018B6 69A6 LW V1, 24(V0)\r
+BFD018B8 0020FC5E LW V0, 32(S8)\r
+BFD018BC 0526 ADDU V0, V1, V0\r
+BFD018BE 001CFC9E LW A0, 28(S8)\r
+BFD018C2 0CA2 MOVE A1, V0\r
+BFD018C4 0020FCDE LW A2, 32(S8)\r
+BFD018C8 0020FCFE LW A3, 32(S8)\r
+BFD018CC 2BE477E8 JALS prvInsertTimerInActiveList\r
+BFD018CE 2BE4 LHU A3, 8(A2)\r
+BFD018D0 0C00 NOP\r
694: break;\r
-BFD018D2 CC15 B 0xBFD018FE
-BFD018D4 0C00 NOP
+BFD018D2 CC15 B 0xBFD018FE\r
+BFD018D4 0C00 NOP\r
695: \r
696: case tmrCOMMAND_DELETE :\r
697: /* The timer has already been removed from the active list,\r
698: just free up the memory. */\r
699: vPortFree( pxTimer );\r
-BFD018D6 001CFC9E LW A0, 28(S8)
-BFD018DA 2FEA77E8 JALS vPortFree
-BFD018DC 2FEA ANDI A3, A2, 0x20
-BFD018DE 0C00 NOP
+BFD018D6 001CFC9E LW A0, 28(S8)\r
+BFD018DA 2FEA77E8 JALS vPortFree\r
+BFD018DC 2FEA ANDI A3, A2, 0x20\r
+BFD018DE 0C00 NOP\r
700: break;\r
-BFD018E0 CC0E B 0xBFD018FE
-BFD018E2 0C00 NOP
+BFD018E0 CC0E B 0xBFD018FE\r
+BFD018E2 0C00 NOP\r
701: \r
702: default :\r
703: /* Don't expect to get here. */\r
704: break;\r
-BFD018E4 0C00 NOP
-BFD018E6 CC0B B 0xBFD018FE
-BFD018E8 0C00 NOP
+BFD018E4 0C00 NOP\r
+BFD018E6 CC0B B 0xBFD018FE\r
+BFD018E8 0C00 NOP\r
705: }\r
706: }\r
707: }\r
708: }\r
-BFD01918 0FBE MOVE SP, S8
-BFD0191A 4BF1 LW RA, 68(SP)
-BFD0191C 4BD0 LW S8, 64(SP)
-BFD0191E 4C25 ADDIU SP, SP, 72
-BFD01920 459F JR16 RA
-BFD01922 0C00 NOP
+BFD01918 0FBE MOVE SP, S8\r
+BFD0191A 4BF1 LW RA, 68(SP)\r
+BFD0191C 4BD0 LW S8, 64(SP)\r
+BFD0191E 4C25 ADDIU SP, SP, 72\r
+BFD01920 459F JR16 RA\r
+BFD01922 0C00 NOP\r
709: /*-----------------------------------------------------------*/\r
710: \r
711: static void prvSwitchTimerLists( void )\r
712: {\r
-BFD03EF0 4FE5 ADDIU SP, SP, -56
-BFD03EF2 CBED SW RA, 52(SP)
-BFD03EF4 CBCC SW S8, 48(SP)
-BFD03EF6 0FDD MOVE S8, SP
+BFD03EF0 4FE5 ADDIU SP, SP, -56\r
+BFD03EF2 CBED SW RA, 52(SP)\r
+BFD03EF4 CBCC SW S8, 48(SP)\r
+BFD03EF6 0FDD MOVE S8, SP\r
713: TickType_t xNextExpireTime, xReloadTime;\r
714: List_t *pxTemp;\r
715: Timer_t *pxTimer;\r
720: then they must have expired and should be processed before the lists\r
721: are switched. */\r
722: while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )\r
-BFD03EF8 CC61 B 0xBFD03FBC
-BFD03EFA 0C00 NOP
-BFD03FBC 8060FC5C LW V0, -32672(GP)
-BFD03FC0 6920 LW V0, 0(V0)
-BFD03FC2 FF9B40A2 BNEZC V0, 0xBFD03EFC
-BFD03FC4 FC5CFF9B LW GP, -932(K1)
+BFD03EF8 CC61 B 0xBFD03FBC\r
+BFD03EFA 0C00 NOP\r
+BFD03FBC 8060FC5C LW V0, -32672(GP)\r
+BFD03FC0 6920 LW V0, 0(V0)\r
+BFD03FC2 FF9B40A2 BNEZC V0, 0xBFD03EFC\r
+BFD03FC4 FC5CFF9B LW GP, -932(K1)\r
723: {\r
724: xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );\r
-BFD03EFC 8060FC5C LW V0, -32672(GP)
-BFD03F00 6923 LW V0, 12(V0)
-BFD03F02 6920 LW V0, 0(V0)
-BFD03F04 0018F85E SW V0, 24(S8)
+BFD03EFC 8060FC5C LW V0, -32672(GP)\r
+BFD03F00 6923 LW V0, 12(V0)\r
+BFD03F02 6920 LW V0, 0(V0)\r
+BFD03F04 0018F85E SW V0, 24(S8)\r
725: \r
726: /* Remove the timer from the list. */\r
727: pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );\r
-BFD03F08 8060FC5C LW V0, -32672(GP)
-BFD03F0C 6923 LW V0, 12(V0)
-BFD03F0E 6923 LW V0, 12(V0)
-BFD03F10 001CF85E SW V0, 28(S8)
+BFD03F08 8060FC5C LW V0, -32672(GP)\r
+BFD03F0C 6923 LW V0, 12(V0)\r
+BFD03F0E 6923 LW V0, 12(V0)\r
+BFD03F10 001CF85E SW V0, 28(S8)\r
728: ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );\r
-BFD03F14 001CFC5E LW V0, 28(S8)
-BFD03F18 6D22 ADDIU V0, V0, 4
-BFD03F1A 0C82 MOVE A0, V0
-BFD03F1C 00C877E8 JALS uxListRemove
-BFD03F1E 0C0000C8 SLL A2, T0, 1
-BFD03F20 0C00 NOP
+BFD03F14 001CFC5E LW V0, 28(S8)\r
+BFD03F18 6D22 ADDIU V0, V0, 4\r
+BFD03F1A 0C82 MOVE A0, V0\r
+BFD03F1C 00C877E8 JALS uxListRemove\r
+BFD03F1E 0C0000C8 SLL A2, T0, 1\r
+BFD03F20 0C00 NOP\r
729: traceTIMER_EXPIRED( pxTimer );\r
730: \r
731: /* Execute its callback, then send a command to restart the timer if\r
732: it is an auto-reload timer. It cannot be restarted here as the lists\r
733: have not yet been switched. */\r
734: pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );\r
-BFD03F22 001CFC5E LW V0, 28(S8)
-BFD03F26 6929 LW V0, 36(V0)
-BFD03F28 001CFC9E LW A0, 28(S8)
-BFD03F2C 45E2 JALRS16 V0
-BFD03F2E 0C00 NOP
+BFD03F22 001CFC5E LW V0, 28(S8)\r
+BFD03F26 6929 LW V0, 36(V0)\r
+BFD03F28 001CFC9E LW A0, 28(S8)\r
+BFD03F2C 45E2 JALRS16 V0\r
+BFD03F2E 0C00 NOP\r
735: \r
736: if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )\r
-BFD03F30 001CFC5E LW V0, 28(S8)
-BFD03F34 69A7 LW V1, 28(V0)
-BFD03F36 ED01 LI V0, 1
-BFD03F38 0040B443 BNE V1, V0, 0xBFD03FBC
-BFD03F3A 0C000040 SLL V0, ZERO, 1
-BFD03F3C 0C00 NOP
+BFD03F30 001CFC5E LW V0, 28(S8)\r
+BFD03F34 69A7 LW V1, 28(V0)\r
+BFD03F36 ED01 LI V0, 1\r
+BFD03F38 0040B443 BNE V1, V0, 0xBFD03FBC\r
+BFD03F3A 0C000040 SLL V0, ZERO, 1\r
+BFD03F3C 0C00 NOP\r
737: {\r
738: /* Calculate the reload value, and if the reload value results in\r
739: the timer going into the same timer list then it has already expired\r
742: to restart the timer to ensure it is only inserted into a list after\r
743: the lists have been swapped. */\r
744: xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );\r
-BFD03F3E 001CFC5E LW V0, 28(S8)
-BFD03F42 69A6 LW V1, 24(V0)
-BFD03F44 0018FC5E LW V0, 24(S8)
-BFD03F48 0526 ADDU V0, V1, V0
-BFD03F4A 0020F85E SW V0, 32(S8)
+BFD03F3E 001CFC5E LW V0, 28(S8)\r
+BFD03F42 69A6 LW V1, 24(V0)\r
+BFD03F44 0018FC5E LW V0, 24(S8)\r
+BFD03F48 0526 ADDU V0, V1, V0\r
+BFD03F4A 0020F85E SW V0, 32(S8)\r
745: if( xReloadTime > xNextExpireTime )\r
-BFD03F4E 0020FC7E LW V1, 32(S8)
-BFD03F52 0018FC5E LW V0, 24(S8)
-BFD03F56 13900062 SLTU V0, V0, V1
-BFD03F58 40E21390 ADDI GP, S0, 16610
-BFD03F5A 001640E2 BEQZC V0, 0xBFD03F8A
+BFD03F4E 0020FC7E LW V1, 32(S8)\r
+BFD03F52 0018FC5E LW V0, 24(S8)\r
+BFD03F56 13900062 SLTU V0, V0, V1\r
+BFD03F58 40E21390 ADDI GP, S0, 16610\r
+BFD03F5A 001640E2 BEQZC V0, 0xBFD03F8A\r
746: {\r
747: listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );\r
-BFD03F5E 001CFC5E LW V0, 28(S8)
-BFD03F62 0020FC7E LW V1, 32(S8)
-BFD03F66 E9A1 SW V1, 4(V0)
+BFD03F5E 001CFC5E LW V0, 28(S8)\r
+BFD03F62 0020FC7E LW V1, 32(S8)\r
+BFD03F66 E9A1 SW V1, 4(V0)\r
748: listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );\r
-BFD03F68 001CFC5E LW V0, 28(S8)
-BFD03F6C 001CFC7E LW V1, 28(S8)
-BFD03F70 E9A4 SW V1, 16(V0)
+BFD03F68 001CFC5E LW V0, 28(S8)\r
+BFD03F6C 001CFC7E LW V1, 28(S8)\r
+BFD03F70 E9A4 SW V1, 16(V0)\r
749: vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );\r
-BFD03F72 8060FC7C LW V1, -32672(GP)
-BFD03F76 001CFC5E LW V0, 28(S8)
-BFD03F7A 6D22 ADDIU V0, V0, 4
-BFD03F7C 0C83 MOVE A0, V1
-BFD03F7E 0CA2 MOVE A1, V0
-BFD03F80 304077E8 JALS vListInsert
-BFD03F82 0C003040 ADDIU V0, ZERO, 3072
-BFD03F84 0C00 NOP
-BFD03F86 CC1A B 0xBFD03FBC
-BFD03F88 0C00 NOP
+BFD03F72 8060FC7C LW V1, -32672(GP)\r
+BFD03F76 001CFC5E LW V0, 28(S8)\r
+BFD03F7A 6D22 ADDIU V0, V0, 4\r
+BFD03F7C 0C83 MOVE A0, V1\r
+BFD03F7E 0CA2 MOVE A1, V0\r
+BFD03F80 304077E8 JALS vListInsert\r
+BFD03F82 0C003040 ADDIU V0, ZERO, 3072\r
+BFD03F84 0C00 NOP\r
+BFD03F86 CC1A B 0xBFD03FBC\r
+BFD03F88 0C00 NOP\r
750: }\r
751: else\r
752: {\r
753: xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );\r
-BFD03F8A C804 SW ZERO, 16(SP)
-BFD03F8C 001CFC9E LW A0, 28(S8)
-BFD03F90 0CA0 MOVE A1, ZERO
-BFD03F92 0018FCDE LW A2, 24(S8)
-BFD03F96 0CE0 MOVE A3, ZERO
-BFD03F98 2D0E77E8 JALS xTimerGenericCommand
-BFD03F9A 2D0E ANDI V0, S0, 0x8000
-BFD03F9C 0C00 NOP
-BFD03F9E 0024F85E SW V0, 36(S8)
+BFD03F8A C804 SW ZERO, 16(SP)\r
+BFD03F8C 001CFC9E LW A0, 28(S8)\r
+BFD03F90 0CA0 MOVE A1, ZERO\r
+BFD03F92 0018FCDE LW A2, 24(S8)\r
+BFD03F96 0CE0 MOVE A3, ZERO\r
+BFD03F98 2D0E77E8 JALS xTimerGenericCommand\r
+BFD03F9A 2D0E ANDI V0, S0, 0x8000\r
+BFD03F9C 0C00 NOP\r
+BFD03F9E 0024F85E SW V0, 36(S8)\r
754: configASSERT( xResult );\r
-BFD03FA2 0024FC5E LW V0, 36(S8)
-BFD03FA6 000940A2 BNEZC V0, 0xBFD03FBC
-BFD03FAA BFD141A2 LUI V0, 0xBFD1
-BFD03FAC 3082BFD1 LDC1 F30, 12418(S1)
-BFD03FAE 9AE83082 ADDIU A0, V0, -25880
-BFD03FB0 30A09AE8 SWC1 F23, 12448(T0)
-BFD03FB2 02F230A0 ADDIU A1, ZERO, 754
-BFD03FB6 4B7E77E8 JALS vAssertCalled
-BFD03FB8 4B7E LW K1, 120(SP)
-BFD03FBA 0C00 NOP
+BFD03FA2 0024FC5E LW V0, 36(S8)\r
+BFD03FA6 000940A2 BNEZC V0, 0xBFD03FBC\r
+BFD03FAA BFD141A2 LUI V0, 0xBFD1\r
+BFD03FAC 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD03FAE 9AE83082 ADDIU A0, V0, -25880\r
+BFD03FB0 30A09AE8 SWC1 F23, 12448(T0)\r
+BFD03FB2 02F230A0 ADDIU A1, ZERO, 754\r
+BFD03FB6 4B7E77E8 JALS vAssertCalled\r
+BFD03FB8 4B7E LW K1, 120(SP)\r
+BFD03FBA 0C00 NOP\r
755: ( void ) xResult;\r
756: }\r
757: }\r
762: }\r
763: \r
764: pxTemp = pxCurrentTimerList;\r
-BFD03FC6 8060FC5C LW V0, -32672(GP)
-BFD03FCA 0028F85E SW V0, 40(S8)
+BFD03FC6 8060FC5C LW V0, -32672(GP)\r
+BFD03FCA 0028F85E SW V0, 40(S8)\r
765: pxCurrentTimerList = pxOverflowTimerList;\r
-BFD03FCE 8064FC5C LW V0, -32668(GP)
-BFD03FD2 8060F85C SW V0, -32672(GP)
+BFD03FCE 8064FC5C LW V0, -32668(GP)\r
+BFD03FD2 8060F85C SW V0, -32672(GP)\r
766: pxOverflowTimerList = pxTemp;\r
-BFD03FD6 0028FC5E LW V0, 40(S8)
-BFD03FDA 8064F85C SW V0, -32668(GP)
+BFD03FD6 0028FC5E LW V0, 40(S8)\r
+BFD03FDA 8064F85C SW V0, -32668(GP)\r
767: }\r
-BFD03FDE 0FBE MOVE SP, S8
-BFD03FE0 4BED LW RA, 52(SP)
-BFD03FE2 4BCC LW S8, 48(SP)
-BFD03FE4 4C1D ADDIU SP, SP, 56
-BFD03FE6 459F JR16 RA
-BFD03FE8 0C00 NOP
+BFD03FDE 0FBE MOVE SP, S8\r
+BFD03FE0 4BED LW RA, 52(SP)\r
+BFD03FE2 4BCC LW S8, 48(SP)\r
+BFD03FE4 4C1D ADDIU SP, SP, 56\r
+BFD03FE6 459F JR16 RA\r
+BFD03FE8 0C00 NOP\r
768: /*-----------------------------------------------------------*/\r
769: \r
770: static void prvCheckForValidListAndQueue( void )\r
771: {\r
-BFD06BE8 4FF5 ADDIU SP, SP, -24
-BFD06BEA CBE5 SW RA, 20(SP)
-BFD06BEC CBC4 SW S8, 16(SP)
-BFD06BEE 0FDD MOVE S8, SP
+BFD06BE8 4FF5 ADDIU SP, SP, -24\r
+BFD06BEA CBE5 SW RA, 20(SP)\r
+BFD06BEC CBC4 SW S8, 16(SP)\r
+BFD06BEE 0FDD MOVE S8, SP\r
772: /* Check that the list from which active timers are referenced, and the\r
773: queue used to communicate with the timer service, have been\r
774: initialised. */\r
775: taskENTER_CRITICAL();\r
-BFD06BF0 33B877E8 JALS vTaskEnterCritical
-BFD06BF2 0C0033B8 ADDIU SP, T8, 3072
-BFD06BF4 0C00 NOP
+BFD06BF0 33B877E8 JALS vTaskEnterCritical\r
+BFD06BF2 0C0033B8 ADDIU SP, T8, 3072\r
+BFD06BF4 0C00 NOP\r
776: {\r
777: if( xTimerQueue == NULL )\r
-BFD06BF6 8068FC5C LW V0, -32664(GP)
-BFD06BFA 002F40A2 BNEZC V0, 0xBFD06C5C
+BFD06BF6 8068FC5C LW V0, -32664(GP)\r
+BFD06BFA 002F40A2 BNEZC V0, 0xBFD06C5C\r
778: {\r
779: vListInitialise( &xActiveTimerList1 );\r
-BFD06BFE BFD241A2 LUI V0, 0xBFD2
-BFD06C00 3082BFD2 LDC1 F30, 12418(S2)
-BFD06C02 B9483082 ADDIU A0, V0, -18104
-BFD06C04 77E8B948 SDC1 F10, 30696(T0)
-BFD06C06 457077E8 JALS vListInitialise
-BFD06C08 4570 SWM16 0x3, 0(SP)
-BFD06C0A 0C00 NOP
+BFD06BFE BFD241A2 LUI V0, 0xBFD2\r
+BFD06C00 3082BFD2 LDC1 F30, 12418(S2)\r
+BFD06C02 B9483082 ADDIU A0, V0, -18104\r
+BFD06C04 77E8B948 SDC1 F10, 30696(T0)\r
+BFD06C06 457077E8 JALS vListInitialise\r
+BFD06C08 4570 SWM16 0x3, 0(SP)\r
+BFD06C0A 0C00 NOP\r
780: vListInitialise( &xActiveTimerList2 );\r
-BFD06C0C BFD241A2 LUI V0, 0xBFD2
-BFD06C0E 3082BFD2 LDC1 F30, 12418(S2)
-BFD06C10 B95C3082 ADDIU A0, V0, -18084
-BFD06C12 77E8B95C SDC1 F10, 30696(GP)
-BFD06C14 457077E8 JALS vListInitialise
-BFD06C16 4570 SWM16 0x3, 0(SP)
-BFD06C18 0C00 NOP
+BFD06C0C BFD241A2 LUI V0, 0xBFD2\r
+BFD06C0E 3082BFD2 LDC1 F30, 12418(S2)\r
+BFD06C10 B95C3082 ADDIU A0, V0, -18084\r
+BFD06C12 77E8B95C SDC1 F10, 30696(GP)\r
+BFD06C14 457077E8 JALS vListInitialise\r
+BFD06C16 4570 SWM16 0x3, 0(SP)\r
+BFD06C18 0C00 NOP\r
781: pxCurrentTimerList = &xActiveTimerList1;\r
-BFD06C1A BFD241A2 LUI V0, 0xBFD2
-BFD06C1C 3042BFD2 LDC1 F30, 12354(S2)
-BFD06C1E B9483042 ADDIU V0, V0, -18104
-BFD06C20 F85CB948 SDC1 F10, -1956(T0)
-BFD06C22 8060F85C SW V0, -32672(GP)
+BFD06C1A BFD241A2 LUI V0, 0xBFD2\r
+BFD06C1C 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD06C1E B9483042 ADDIU V0, V0, -18104\r
+BFD06C20 F85CB948 SDC1 F10, -1956(T0)\r
+BFD06C22 8060F85C SW V0, -32672(GP)\r
782: pxOverflowTimerList = &xActiveTimerList2;\r
-BFD06C26 BFD241A2 LUI V0, 0xBFD2
-BFD06C28 3042BFD2 LDC1 F30, 12354(S2)
-BFD06C2A B95C3042 ADDIU V0, V0, -18084
-BFD06C2C F85CB95C SDC1 F10, -1956(GP)
-BFD06C2E 8064F85C SW V0, -32668(GP)
+BFD06C26 BFD241A2 LUI V0, 0xBFD2\r
+BFD06C28 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD06C2A B95C3042 ADDIU V0, V0, -18084\r
+BFD06C2C F85CB95C SDC1 F10, -1956(GP)\r
+BFD06C2E 8064F85C SW V0, -32668(GP)\r
783: xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );\r
-BFD06C32 EE05 LI A0, 5
-BFD06C34 EE90 LI A1, 16
-BFD06C36 0CC0 MOVE A2, ZERO
-BFD06C38 1EFA77E8 JALS xQueueGenericCreate
-BFD06C3A 0C001EFA LB S7, 3072(K0)
-BFD06C3C 0C00 NOP
-BFD06C3E 8068F85C SW V0, -32664(GP)
+BFD06C32 EE05 LI A0, 5\r
+BFD06C34 EE90 LI A1, 16\r
+BFD06C36 0CC0 MOVE A2, ZERO\r
+BFD06C38 1EFA77E8 JALS xQueueGenericCreate\r
+BFD06C3A 0C001EFA LB S7, 3072(K0)\r
+BFD06C3C 0C00 NOP\r
+BFD06C3E 8068F85C SW V0, -32664(GP)\r
784: configASSERT( xTimerQueue );\r
-BFD06C42 8068FC5C LW V0, -32664(GP)
-BFD06C46 000940A2 BNEZC V0, 0xBFD06C5C
-BFD06C4A BFD141A2 LUI V0, 0xBFD1
-BFD06C4C 3082BFD1 LDC1 F30, 12418(S1)
-BFD06C4E 9AE83082 ADDIU A0, V0, -25880
-BFD06C50 30A09AE8 SWC1 F23, 12448(T0)
-BFD06C52 031030A0 ADDIU A1, ZERO, 784
-BFD06C56 4B7E77E8 JALS vAssertCalled
-BFD06C58 4B7E LW K1, 120(SP)
-BFD06C5A 0C00 NOP
+BFD06C42 8068FC5C LW V0, -32664(GP)\r
+BFD06C46 000940A2 BNEZC V0, 0xBFD06C5C\r
+BFD06C4A BFD141A2 LUI V0, 0xBFD1\r
+BFD06C4C 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD06C4E 9AE83082 ADDIU A0, V0, -25880\r
+BFD06C50 30A09AE8 SWC1 F23, 12448(T0)\r
+BFD06C52 031030A0 ADDIU A1, ZERO, 784\r
+BFD06C56 4B7E77E8 JALS vAssertCalled\r
+BFD06C58 4B7E LW K1, 120(SP)\r
+BFD06C5A 0C00 NOP\r
785: \r
786: #if ( configQUEUE_REGISTRY_SIZE > 0 )\r
787: {\r
802: }\r
803: }\r
804: taskEXIT_CRITICAL();\r
-BFD06C5C 40AA77E8 JALS vTaskExitCritical
-BFD06C5E 0C0040AA BNEZC T2, 0xBFD08462
-BFD06C60 0C00 NOP
+BFD06C5C 40AA77E8 JALS vTaskExitCritical\r
+BFD06C5E 0C0040AA BNEZC T2, 0xBFD08462\r
+BFD06C60 0C00 NOP\r
805: }\r
-BFD06C62 0FBE MOVE SP, S8
-BFD06C64 4BE5 LW RA, 20(SP)
-BFD06C66 4BC4 LW S8, 16(SP)
-BFD06C68 4C0D ADDIU SP, SP, 24
-BFD06C6A 459F JR16 RA
-BFD06C6C 0C00 NOP
+BFD06C62 0FBE MOVE SP, S8\r
+BFD06C64 4BE5 LW RA, 20(SP)\r
+BFD06C66 4BC4 LW S8, 16(SP)\r
+BFD06C68 4C0D ADDIU SP, SP, 24\r
+BFD06C6A 459F JR16 RA\r
+BFD06C6C 0C00 NOP\r
806: /*-----------------------------------------------------------*/\r
807: \r
808: BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )\r
809: {\r
-BFD093E0 4FF1 ADDIU SP, SP, -32
-BFD093E2 CBE7 SW RA, 28(SP)
-BFD093E4 CBC6 SW S8, 24(SP)
-BFD093E6 0FDD MOVE S8, SP
-BFD093E8 0020F89E SW A0, 32(S8)
+BFD093E0 4FF1 ADDIU SP, SP, -32\r
+BFD093E2 CBE7 SW RA, 28(SP)\r
+BFD093E4 CBC6 SW S8, 24(SP)\r
+BFD093E6 0FDD MOVE S8, SP\r
+BFD093E8 0020F89E SW A0, 32(S8)\r
810: BaseType_t xTimerIsInActiveList;\r
811: Timer_t *pxTimer = ( Timer_t * ) xTimer;\r
-BFD093EC 0020FC5E LW V0, 32(S8)
-BFD093F0 0010F85E SW V0, 16(S8)
+BFD093EC 0020FC5E LW V0, 32(S8)\r
+BFD093F0 0010F85E SW V0, 16(S8)\r
812: \r
813: /* Is the timer in the list of active timers? */\r
814: taskENTER_CRITICAL();\r
-BFD093F4 33B877E8 JALS vTaskEnterCritical
-BFD093F6 0C0033B8 ADDIU SP, T8, 3072
-BFD093F8 0C00 NOP
+BFD093F4 33B877E8 JALS vTaskEnterCritical\r
+BFD093F6 0C0033B8 ADDIU SP, T8, 3072\r
+BFD093F8 0C00 NOP\r
815: {\r
816: /* Checking to see if it is in the NULL list in effect checks to see if\r
817: it is referenced from either the current or the overflow timer lists in\r
818: one go, but the logic has to be reversed, hence the '!'. */\r
819: xTimerIsInActiveList = ( BaseType_t ) !( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) );\r
-BFD093FA 0010FC5E LW V0, 16(S8)
-BFD093FE 6925 LW V0, 20(V0)
-BFD09400 13900040 SLTU V0, ZERO, V0
-BFD09402 F85E1390 ADDI GP, S0, -1954
-BFD09404 0014F85E SW V0, 20(S8)
+BFD093FA 0010FC5E LW V0, 16(S8)\r
+BFD093FE 6925 LW V0, 20(V0)\r
+BFD09400 13900040 SLTU V0, ZERO, V0\r
+BFD09402 F85E1390 ADDI GP, S0, -1954\r
+BFD09404 0014F85E SW V0, 20(S8)\r
820: }\r
821: taskEXIT_CRITICAL();\r
-BFD09408 40AA77E8 JALS vTaskExitCritical
-BFD0940A 0C0040AA BNEZC T2, 0xBFD0AC0E
-BFD0940C 0C00 NOP
+BFD09408 40AA77E8 JALS vTaskExitCritical\r
+BFD0940A 0C0040AA BNEZC T2, 0xBFD0AC0E\r
+BFD0940C 0C00 NOP\r
822: \r
823: return xTimerIsInActiveList;\r
-BFD0940E 0014FC5E LW V0, 20(S8)
+BFD0940E 0014FC5E LW V0, 20(S8)\r
824: } /*lint !e818 Can't be pointer to const due to the typedef. */\r
-BFD09412 0FBE MOVE SP, S8
-BFD09414 4BE7 LW RA, 28(SP)
-BFD09416 4BC6 LW S8, 24(SP)
-BFD09418 4C11 ADDIU SP, SP, 32
-BFD0941A 459F JR16 RA
-BFD0941C 0C00 NOP
+BFD09412 0FBE MOVE SP, S8\r
+BFD09414 4BE7 LW RA, 28(SP)\r
+BFD09416 4BC6 LW S8, 24(SP)\r
+BFD09418 4C11 ADDIU SP, SP, 32\r
+BFD0941A 459F JR16 RA\r
+BFD0941C 0C00 NOP\r
825: /*-----------------------------------------------------------*/\r
826: \r
827: void *pvTimerGetTimerID( const TimerHandle_t xTimer )\r
828: {\r
-BFD0875C 4FF1 ADDIU SP, SP, -32
-BFD0875E CBE7 SW RA, 28(SP)
-BFD08760 CBC6 SW S8, 24(SP)
-BFD08762 0FDD MOVE S8, SP
-BFD08764 0020F89E SW A0, 32(S8)
+BFD0875C 4FF1 ADDIU SP, SP, -32\r
+BFD0875E CBE7 SW RA, 28(SP)\r
+BFD08760 CBC6 SW S8, 24(SP)\r
+BFD08762 0FDD MOVE S8, SP\r
+BFD08764 0020F89E SW A0, 32(S8)\r
829: Timer_t * const pxTimer = ( Timer_t * ) xTimer;\r
-BFD08768 0020FC5E LW V0, 32(S8)
-BFD0876C 0010F85E SW V0, 16(S8)
+BFD08768 0020FC5E LW V0, 32(S8)\r
+BFD0876C 0010F85E SW V0, 16(S8)\r
830: void *pvReturn;\r
831: \r
832: configASSERT( xTimer );\r
-BFD08770 0020FC5E LW V0, 32(S8)
-BFD08774 000940A2 BNEZC V0, 0xBFD0878A
-BFD08778 BFD141A2 LUI V0, 0xBFD1
-BFD0877A 3082BFD1 LDC1 F30, 12418(S1)
-BFD0877C 9AE83082 ADDIU A0, V0, -25880
-BFD0877E 30A09AE8 SWC1 F23, 12448(T0)
-BFD08780 034030A0 ADDIU A1, ZERO, 832
-BFD08784 4B7E77E8 JALS vAssertCalled
-BFD08786 4B7E LW K1, 120(SP)
-BFD08788 0C00 NOP
+BFD08770 0020FC5E LW V0, 32(S8)\r
+BFD08774 000940A2 BNEZC V0, 0xBFD0878A\r
+BFD08778 BFD141A2 LUI V0, 0xBFD1\r
+BFD0877A 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD0877C 9AE83082 ADDIU A0, V0, -25880\r
+BFD0877E 30A09AE8 SWC1 F23, 12448(T0)\r
+BFD08780 034030A0 ADDIU A1, ZERO, 832\r
+BFD08784 4B7E77E8 JALS vAssertCalled\r
+BFD08786 4B7E LW K1, 120(SP)\r
+BFD08788 0C00 NOP\r
833: \r
834: taskENTER_CRITICAL();\r
-BFD0878A 33B877E8 JALS vTaskEnterCritical
-BFD0878C 0C0033B8 ADDIU SP, T8, 3072
-BFD0878E 0C00 NOP
+BFD0878A 33B877E8 JALS vTaskEnterCritical\r
+BFD0878C 0C0033B8 ADDIU SP, T8, 3072\r
+BFD0878E 0C00 NOP\r
835: {\r
836: pvReturn = pxTimer->pvTimerID;\r
-BFD08790 0010FC5E LW V0, 16(S8)
-BFD08794 6928 LW V0, 32(V0)
-BFD08796 0014F85E SW V0, 20(S8)
+BFD08790 0010FC5E LW V0, 16(S8)\r
+BFD08794 6928 LW V0, 32(V0)\r
+BFD08796 0014F85E SW V0, 20(S8)\r
837: }\r
838: taskEXIT_CRITICAL();\r
-BFD0879A 40AA77E8 JALS vTaskExitCritical
-BFD0879C 0C0040AA BNEZC T2, 0xBFD09FA0
-BFD0879E 0C00 NOP
+BFD0879A 40AA77E8 JALS vTaskExitCritical\r
+BFD0879C 0C0040AA BNEZC T2, 0xBFD09FA0\r
+BFD0879E 0C00 NOP\r
839: \r
840: return pvReturn;\r
-BFD087A0 0014FC5E LW V0, 20(S8)
+BFD087A0 0014FC5E LW V0, 20(S8)\r
841: }\r
-BFD087A4 0FBE MOVE SP, S8
-BFD087A6 4BE7 LW RA, 28(SP)
-BFD087A8 4BC6 LW S8, 24(SP)
-BFD087AA 4C11 ADDIU SP, SP, 32
-BFD087AC 459F JR16 RA
-BFD087AE 0C00 NOP
+BFD087A4 0FBE MOVE SP, S8\r
+BFD087A6 4BE7 LW RA, 28(SP)\r
+BFD087A8 4BC6 LW S8, 24(SP)\r
+BFD087AA 4C11 ADDIU SP, SP, 32\r
+BFD087AC 459F JR16 RA\r
+BFD087AE 0C00 NOP\r
842: /*-----------------------------------------------------------*/\r
843: \r
844: void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID )\r
845: {\r
-BFD087B0 4FF1 ADDIU SP, SP, -32
-BFD087B2 CBE7 SW RA, 28(SP)
-BFD087B4 CBC6 SW S8, 24(SP)
-BFD087B6 0FDD MOVE S8, SP
-BFD087B8 0020F89E SW A0, 32(S8)
-BFD087BC 0024F8BE SW A1, 36(S8)
+BFD087B0 4FF1 ADDIU SP, SP, -32\r
+BFD087B2 CBE7 SW RA, 28(SP)\r
+BFD087B4 CBC6 SW S8, 24(SP)\r
+BFD087B6 0FDD MOVE S8, SP\r
+BFD087B8 0020F89E SW A0, 32(S8)\r
+BFD087BC 0024F8BE SW A1, 36(S8)\r
846: Timer_t * const pxTimer = ( Timer_t * ) xTimer;\r
-BFD087C0 0020FC5E LW V0, 32(S8)
-BFD087C4 0010F85E SW V0, 16(S8)
+BFD087C0 0020FC5E LW V0, 32(S8)\r
+BFD087C4 0010F85E SW V0, 16(S8)\r
847: \r
848: configASSERT( xTimer );\r
-BFD087C8 0020FC5E LW V0, 32(S8)
-BFD087CC 000940A2 BNEZC V0, 0xBFD087E2
-BFD087D0 BFD141A2 LUI V0, 0xBFD1
-BFD087D2 3082BFD1 LDC1 F30, 12418(S1)
-BFD087D4 9AE83082 ADDIU A0, V0, -25880
-BFD087D6 30A09AE8 SWC1 F23, 12448(T0)
-BFD087D8 035030A0 ADDIU A1, ZERO, 848
-BFD087DC 4B7E77E8 JALS vAssertCalled
-BFD087DE 4B7E LW K1, 120(SP)
-BFD087E0 0C00 NOP
+BFD087C8 0020FC5E LW V0, 32(S8)\r
+BFD087CC 000940A2 BNEZC V0, 0xBFD087E2\r
+BFD087D0 BFD141A2 LUI V0, 0xBFD1\r
+BFD087D2 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD087D4 9AE83082 ADDIU A0, V0, -25880\r
+BFD087D6 30A09AE8 SWC1 F23, 12448(T0)\r
+BFD087D8 035030A0 ADDIU A1, ZERO, 848\r
+BFD087DC 4B7E77E8 JALS vAssertCalled\r
+BFD087DE 4B7E LW K1, 120(SP)\r
+BFD087E0 0C00 NOP\r
849: \r
850: taskENTER_CRITICAL();\r
-BFD087E2 33B877E8 JALS vTaskEnterCritical
-BFD087E4 0C0033B8 ADDIU SP, T8, 3072
-BFD087E6 0C00 NOP
+BFD087E2 33B877E8 JALS vTaskEnterCritical\r
+BFD087E4 0C0033B8 ADDIU SP, T8, 3072\r
+BFD087E6 0C00 NOP\r
851: {\r
852: pxTimer->pvTimerID = pvNewID;\r
-BFD087E8 0010FC5E LW V0, 16(S8)
-BFD087EC 0024FC7E LW V1, 36(S8)
-BFD087F0 E9A8 SW V1, 32(V0)
+BFD087E8 0010FC5E LW V0, 16(S8)\r
+BFD087EC 0024FC7E LW V1, 36(S8)\r
+BFD087F0 E9A8 SW V1, 32(V0)\r
853: }\r
854: taskEXIT_CRITICAL();\r
-BFD087F2 40AA77E8 JALS vTaskExitCritical
-BFD087F4 0C0040AA BNEZC T2, 0xBFD09FF8
-BFD087F6 0C00 NOP
+BFD087F2 40AA77E8 JALS vTaskExitCritical\r
+BFD087F4 0C0040AA BNEZC T2, 0xBFD09FF8\r
+BFD087F6 0C00 NOP\r
855: }\r
-BFD087F8 0FBE MOVE SP, S8
-BFD087FA 4BE7 LW RA, 28(SP)
-BFD087FC 4BC6 LW S8, 24(SP)
-BFD087FE 4C11 ADDIU SP, SP, 32
-BFD08800 459F JR16 RA
-BFD08802 0C00 NOP
+BFD087F8 0FBE MOVE SP, S8\r
+BFD087FA 4BE7 LW RA, 28(SP)\r
+BFD087FC 4BC6 LW S8, 24(SP)\r
+BFD087FE 4C11 ADDIU SP, SP, 32\r
+BFD08800 459F JR16 RA\r
+BFD08802 0C00 NOP\r
856: /*-----------------------------------------------------------*/\r
857: \r
858: #if( INCLUDE_xTimerPendFunctionCall == 1 )\r
859: \r
860: BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken )\r
861: {\r
-BFD07F64 4FE9 ADDIU SP, SP, -48
-BFD07F66 CBEB SW RA, 44(SP)
-BFD07F68 CBCA SW S8, 40(SP)
-BFD07F6A 0FDD MOVE S8, SP
-BFD07F6C 0030F89E SW A0, 48(S8)
-BFD07F70 0034F8BE SW A1, 52(S8)
-BFD07F74 0038F8DE SW A2, 56(S8)
-BFD07F78 003CF8FE SW A3, 60(S8)
-BFD07F7A 3040003C SRL AT, GP, 6
+BFD07F64 4FE9 ADDIU SP, SP, -48\r
+BFD07F66 CBEB SW RA, 44(SP)\r
+BFD07F68 CBCA SW S8, 40(SP)\r
+BFD07F6A 0FDD MOVE S8, SP\r
+BFD07F6C 0030F89E SW A0, 48(S8)\r
+BFD07F70 0034F8BE SW A1, 52(S8)\r
+BFD07F74 0038F8DE SW A2, 56(S8)\r
+BFD07F78 003CF8FE SW A3, 60(S8)\r
+BFD07F7A 3040003C SRL AT, GP, 6\r
862: DaemonTaskMessage_t xMessage;\r
863: BaseType_t xReturn;\r
864: \r
865: /* Complete the message with the function parameters and post it to the\r
866: daemon task. */\r
867: xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;\r
-BFD07F7C FFFE3040 ADDIU V0, ZERO, -2
-BFD07F7E F85EFFFE LW RA, -1954(S8)
-BFD07F80 0014F85E SW V0, 20(S8)
+BFD07F7C FFFE3040 ADDIU V0, ZERO, -2\r
+BFD07F7E F85EFFFE LW RA, -1954(S8)\r
+BFD07F80 0014F85E SW V0, 20(S8)\r
868: xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;\r
-BFD07F84 0030FC5E LW V0, 48(S8)
-BFD07F88 0018F85E SW V0, 24(S8)
+BFD07F84 0030FC5E LW V0, 48(S8)\r
+BFD07F88 0018F85E SW V0, 24(S8)\r
869: xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;\r
-BFD07F8C 0034FC5E LW V0, 52(S8)
-BFD07F90 001CF85E SW V0, 28(S8)
+BFD07F8C 0034FC5E LW V0, 52(S8)\r
+BFD07F90 001CF85E SW V0, 28(S8)\r
870: xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;\r
-BFD07F94 0038FC5E LW V0, 56(S8)
-BFD07F98 0020F85E SW V0, 32(S8)
+BFD07F94 0038FC5E LW V0, 56(S8)\r
+BFD07F98 0020F85E SW V0, 32(S8)\r
871: \r
872: xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );\r
-BFD07F9C 8068FC7C LW V1, -32664(GP)
-BFD07FA0 0014305E ADDIU V0, S8, 20
-BFD07FA4 0C83 MOVE A0, V1
-BFD07FA6 0CA2 MOVE A1, V0
-BFD07FA8 003CFCDE LW A2, 60(S8)
-BFD07FAC 0CE0 MOVE A3, ZERO
-BFD07FAE 11EA77E8 JALS xQueueGenericSendFromISR
-BFD07FB0 0C0011EA ADDI T7, T2, 3072
-BFD07FB2 0C00 NOP
-BFD07FB4 0010F85E SW V0, 16(S8)
+BFD07F9C 8068FC7C LW V1, -32664(GP)\r
+BFD07FA0 0014305E ADDIU V0, S8, 20\r
+BFD07FA4 0C83 MOVE A0, V1\r
+BFD07FA6 0CA2 MOVE A1, V0\r
+BFD07FA8 003CFCDE LW A2, 60(S8)\r
+BFD07FAC 0CE0 MOVE A3, ZERO\r
+BFD07FAE 11EA77E8 JALS xQueueGenericSendFromISR\r
+BFD07FB0 0C0011EA ADDI T7, T2, 3072\r
+BFD07FB2 0C00 NOP\r
+BFD07FB4 0010F85E SW V0, 16(S8)\r
873: \r
874: tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );\r
875: \r
876: return xReturn;\r
-BFD07FB8 0010FC5E LW V0, 16(S8)
+BFD07FB8 0010FC5E LW V0, 16(S8)\r
877: }\r
-BFD07FBC 0FBE MOVE SP, S8
-BFD07FBE 4BEB LW RA, 44(SP)
-BFD07FC0 4BCA LW S8, 40(SP)
-BFD07FC2 4C19 ADDIU SP, SP, 48
-BFD07FC4 459F JR16 RA
-BFD07FC6 0C00 NOP
+BFD07FBC 0FBE MOVE SP, S8\r
+BFD07FBE 4BEB LW RA, 44(SP)\r
+BFD07FC0 4BCA LW S8, 40(SP)\r
+BFD07FC2 4C19 ADDIU SP, SP, 48\r
+BFD07FC4 459F JR16 RA\r
+BFD07FC6 0C00 NOP\r
878: \r
879: #endif /* INCLUDE_xTimerPendFunctionCall */\r
880: /*-----------------------------------------------------------*/\r
883: \r
884: BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait )\r
885: {\r
-BFD06D70 4FE9 ADDIU SP, SP, -48
-BFD06D72 CBEB SW RA, 44(SP)
-BFD06D74 CBCA SW S8, 40(SP)
-BFD06D76 0FDD MOVE S8, SP
-BFD06D78 0030F89E SW A0, 48(S8)
-BFD06D7C 0034F8BE SW A1, 52(S8)
-BFD06D80 0038F8DE SW A2, 56(S8)
-BFD06D84 003CF8FE SW A3, 60(S8)
+BFD06D70 4FE9 ADDIU SP, SP, -48\r
+BFD06D72 CBEB SW RA, 44(SP)\r
+BFD06D74 CBCA SW S8, 40(SP)\r
+BFD06D76 0FDD MOVE S8, SP\r
+BFD06D78 0030F89E SW A0, 48(S8)\r
+BFD06D7C 0034F8BE SW A1, 52(S8)\r
+BFD06D80 0038F8DE SW A2, 56(S8)\r
+BFD06D84 003CF8FE SW A3, 60(S8)\r
886: DaemonTaskMessage_t xMessage;\r
887: BaseType_t xReturn;\r
888: \r
890: after the scheduler has been started because, until then, the timer\r
891: queue does not exist. */\r
892: configASSERT( xTimerQueue );\r
-BFD06D88 8068FC5C LW V0, -32664(GP)
-BFD06D8C 000940A2 BNEZC V0, 0xBFD06DA2
-BFD06D90 BFD141A2 LUI V0, 0xBFD1
-BFD06D92 3082BFD1 LDC1 F30, 12418(S1)
-BFD06D94 9AE83082 ADDIU A0, V0, -25880
-BFD06D96 30A09AE8 SWC1 F23, 12448(T0)
-BFD06D98 037C30A0 ADDIU A1, ZERO, 892
-BFD06D9C 4B7E77E8 JALS vAssertCalled
-BFD06D9E 4B7E LW K1, 120(SP)
-BFD06DA0 0C00 NOP
+BFD06D88 8068FC5C LW V0, -32664(GP)\r
+BFD06D8C 000940A2 BNEZC V0, 0xBFD06DA2\r
+BFD06D90 BFD141A2 LUI V0, 0xBFD1\r
+BFD06D92 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD06D94 9AE83082 ADDIU A0, V0, -25880\r
+BFD06D96 30A09AE8 SWC1 F23, 12448(T0)\r
+BFD06D98 037C30A0 ADDIU A1, ZERO, 892\r
+BFD06D9C 4B7E77E8 JALS vAssertCalled\r
+BFD06D9E 4B7E LW K1, 120(SP)\r
+BFD06DA0 0C00 NOP\r
893: \r
894: /* Complete the message with the function parameters and post it to the\r
895: daemon task. */\r
896: xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK;\r
-BFD06DA2 ED7F LI V0, -1
-BFD06DA4 0014F85E SW V0, 20(S8)
+BFD06DA2 ED7F LI V0, -1\r
+BFD06DA4 0014F85E SW V0, 20(S8)\r
897: xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;\r
-BFD06DA8 0030FC5E LW V0, 48(S8)
-BFD06DAC 0018F85E SW V0, 24(S8)
+BFD06DA8 0030FC5E LW V0, 48(S8)\r
+BFD06DAC 0018F85E SW V0, 24(S8)\r
898: xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;\r
-BFD06DB0 0034FC5E LW V0, 52(S8)
-BFD06DB4 001CF85E SW V0, 28(S8)
+BFD06DB0 0034FC5E LW V0, 52(S8)\r
+BFD06DB4 001CF85E SW V0, 28(S8)\r
899: xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;\r
-BFD06DB8 0038FC5E LW V0, 56(S8)
-BFD06DBC 0020F85E SW V0, 32(S8)
+BFD06DB8 0038FC5E LW V0, 56(S8)\r
+BFD06DBC 0020F85E SW V0, 32(S8)\r
900: \r
901: xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );\r
-BFD06DC0 8068FC7C LW V1, -32664(GP)
-BFD06DC4 0014305E ADDIU V0, S8, 20
-BFD06DC8 0C83 MOVE A0, V1
-BFD06DCA 0CA2 MOVE A1, V0
-BFD06DCC 003CFCDE LW A2, 60(S8)
-BFD06DD0 0CE0 MOVE A3, ZERO
-BFD06DD2 06A277E8 JALS xQueueGenericSend
-BFD06DD4 06A2 ADDU A1, S1, V0
-BFD06DD6 0C00 NOP
-BFD06DD8 0010F85E SW V0, 16(S8)
+BFD06DC0 8068FC7C LW V1, -32664(GP)\r
+BFD06DC4 0014305E ADDIU V0, S8, 20\r
+BFD06DC8 0C83 MOVE A0, V1\r
+BFD06DCA 0CA2 MOVE A1, V0\r
+BFD06DCC 003CFCDE LW A2, 60(S8)\r
+BFD06DD0 0CE0 MOVE A3, ZERO\r
+BFD06DD2 06A277E8 JALS xQueueGenericSend\r
+BFD06DD4 06A2 ADDU A1, S1, V0\r
+BFD06DD6 0C00 NOP\r
+BFD06DD8 0010F85E SW V0, 16(S8)\r
902: \r
903: tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );\r
904: \r
905: return xReturn;\r
-BFD06DDC 0010FC5E LW V0, 16(S8)
+BFD06DDC 0010FC5E LW V0, 16(S8)\r
906: }\r
-BFD06DE0 0FBE MOVE SP, S8
-BFD06DE2 4BEB LW RA, 44(SP)
-BFD06DE4 4BCA LW S8, 40(SP)
-BFD06DE6 4C19 ADDIU SP, SP, 48
-BFD06DE8 459F JR16 RA
-BFD06DEA 0C00 NOP
+BFD06DE0 0FBE MOVE SP, S8\r
+BFD06DE2 4BEB LW RA, 44(SP)\r
+BFD06DE4 4BCA LW S8, 40(SP)\r
+BFD06DE6 4C19 ADDIU SP, SP, 48\r
+BFD06DE8 459F JR16 RA\r
+BFD06DEA 0C00 NOP\r
907: \r
908: #endif /* INCLUDE_xTimerPendFunctionCall */\r
909: /*-----------------------------------------------------------*/\r
915: \r
916: \r
917: \r
---- c:/e/dev/freertos/workingcopy/freertos/source/tasks.c ---------------------------------------------
+--- c:/e/dev/freertos/workingcopy/freertos/source/tasks.c ---------------------------------------------\r
1: /*\r
2: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
3: All rights reserved\r
8: \r
9: FreeRTOS is free software; you can redistribute it and/or modify it under\r
10: the terms of the GNU General Public License (version 2) as published by the\r
-11: Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+11: Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
12: \r
13: ***************************************************************************\r
14: >>! NOTE: The modification to the GPL is included to allow you to !<<\r
550: \r
551: BaseType_t xTaskGenericCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask, StackType_t * const puxStackBuffer, const MemoryRegion_t * const xRegions ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r
552: {\r
-BFD01534 4FE9 ADDIU SP, SP, -48
-BFD01536 CBEB SW RA, 44(SP)
-BFD01538 CBCA SW S8, 40(SP)
-BFD0153A 0FDD MOVE S8, SP
-BFD0153C 0030F89E SW A0, 48(S8)
-BFD01540 0034F8BE SW A1, 52(S8)
-BFD01544 0C46 MOVE V0, A2
-BFD01546 003CF8FE SW A3, 60(S8)
-BFD0154A 0038385E SH V0, 56(S8)
+BFD01534 4FE9 ADDIU SP, SP, -48\r
+BFD01536 CBEB SW RA, 44(SP)\r
+BFD01538 CBCA SW S8, 40(SP)\r
+BFD0153A 0FDD MOVE S8, SP\r
+BFD0153C 0030F89E SW A0, 48(S8)\r
+BFD01540 0034F8BE SW A1, 52(S8)\r
+BFD01544 0C46 MOVE V0, A2\r
+BFD01546 003CF8FE SW A3, 60(S8)\r
+BFD0154A 0038385E SH V0, 56(S8)\r
553: BaseType_t xReturn;\r
554: TCB_t * pxNewTCB;\r
555: StackType_t *pxTopOfStack;\r
556: \r
557: configASSERT( pxTaskCode );\r
-BFD0154E 0030FC5E LW V0, 48(S8)
-BFD01552 000940A2 BNEZC V0, 0xBFD01568
-BFD01556 BFD141A2 LUI V0, 0xBFD1
-BFD01558 3082BFD1 LDC1 F30, 12418(S1)
-BFD0155A 98103082 ADDIU A0, V0, -26608
-BFD0155C 30A09810 SWC1 F0, 12448(S0)
-BFD0155E 022D30A0 ADDIU A1, ZERO, 557
-BFD01562 4B7E77E8 JALS vAssertCalled
-BFD01564 4B7E LW K1, 120(SP)
-BFD01566 0C00 NOP
+BFD0154E 0030FC5E LW V0, 48(S8)\r
+BFD01552 000940A2 BNEZC V0, 0xBFD01568\r
+BFD01556 BFD141A2 LUI V0, 0xBFD1\r
+BFD01558 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD0155A 98103082 ADDIU A0, V0, -26608\r
+BFD0155C 30A09810 SWC1 F0, 12448(S0)\r
+BFD0155E 022D30A0 ADDIU A1, ZERO, 557\r
+BFD01562 4B7E77E8 JALS vAssertCalled\r
+BFD01564 4B7E LW K1, 120(SP)\r
+BFD01566 0C00 NOP\r
558: configASSERT( ( ( uxPriority & ( UBaseType_t ) ( ~portPRIVILEGE_BIT ) ) < ( UBaseType_t ) configMAX_PRIORITIES ) );\r
-BFD01568 0040FC5E LW V0, 64(S8)
-BFD0156C 0005B042 SLTIU V0, V0, 5
-BFD01570 000940A2 BNEZC V0, 0xBFD01586
-BFD01574 BFD141A2 LUI V0, 0xBFD1
-BFD01576 3082BFD1 LDC1 F30, 12418(S1)
-BFD01578 98103082 ADDIU A0, V0, -26608
-BFD0157A 30A09810 SWC1 F0, 12448(S0)
-BFD0157C 022E30A0 ADDIU A1, ZERO, 558
-BFD01580 4B7E77E8 JALS vAssertCalled
-BFD01582 4B7E LW K1, 120(SP)
-BFD01584 0C00 NOP
+BFD01568 0040FC5E LW V0, 64(S8)\r
+BFD0156C 0005B042 SLTIU V0, V0, 5\r
+BFD01570 000940A2 BNEZC V0, 0xBFD01586\r
+BFD01574 BFD141A2 LUI V0, 0xBFD1\r
+BFD01576 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD01578 98103082 ADDIU A0, V0, -26608\r
+BFD0157A 30A09810 SWC1 F0, 12448(S0)\r
+BFD0157C 022E30A0 ADDIU A1, ZERO, 558\r
+BFD01580 4B7E77E8 JALS vAssertCalled\r
+BFD01582 4B7E LW K1, 120(SP)\r
+BFD01584 0C00 NOP\r
559: \r
560: /* Allocate the memory required by the TCB and stack for the new task,\r
561: checking that the allocation was successful. */\r
562: pxNewTCB = prvAllocateTCBAndStack( usStackDepth, puxStackBuffer );\r
-BFD01586 0038345E LHU V0, 56(S8)
-BFD0158A 0C82 MOVE A0, V0
-BFD0158C 0048FCBE LW A1, 72(S8)
-BFD01590 319477E8 JALS prvAllocateTCBAndStack
-BFD01592 0C003194 ADDIU T4, S4, 3072
-BFD01594 0C00 NOP
-BFD01596 001CF85E SW V0, 28(S8)
+BFD01586 0038345E LHU V0, 56(S8)\r
+BFD0158A 0C82 MOVE A0, V0\r
+BFD0158C 0048FCBE LW A1, 72(S8)\r
+BFD01590 319477E8 JALS prvAllocateTCBAndStack\r
+BFD01592 0C003194 ADDIU T4, S4, 3072\r
+BFD01594 0C00 NOP\r
+BFD01596 001CF85E SW V0, 28(S8)\r
563: \r
564: if( pxNewTCB != NULL )\r
-BFD0159A 001CFC5E LW V0, 28(S8)
-BFD0159E 009A40E2 BEQZC V0, 0xBFD016D6
+BFD0159A 001CFC5E LW V0, 28(S8)\r
+BFD0159E 009A40E2 BEQZC V0, 0xBFD016D6\r
565: {\r
566: #if( portUSING_MPU_WRAPPERS == 1 )\r
567: /* Should the task be created in privileged mode? */\r
598: #if( portSTACK_GROWTH < 0 )\r
599: {\r
600: pxTopOfStack = pxNewTCB->pxStack + ( usStackDepth - ( uint16_t ) 1 );\r
-BFD015A2 001CFC5E LW V0, 28(S8)
-BFD015A4 69AC001C EXT ZERO, GP, 6, 14
-BFD015A6 69AC LW V1, 48(V0)
-BFD015A8 0038345E LHU V0, 56(S8)
-BFD015AC 6D2E ADDIU V0, V0, -1
-BFD015AE 2524 SLL V0, V0, 2
-BFD015B0 0526 ADDU V0, V1, V0
-BFD015B2 0020F85E SW V0, 32(S8)
+BFD015A2 001CFC5E LW V0, 28(S8)\r
+BFD015A4 69AC001C EXT ZERO, GP, 6, 14\r
+BFD015A6 69AC LW V1, 48(V0)\r
+BFD015A8 0038345E LHU V0, 56(S8)\r
+BFD015AC 6D2E ADDIU V0, V0, -1\r
+BFD015AE 2524 SLL V0, V0, 2\r
+BFD015B0 0526 ADDU V0, V1, V0\r
+BFD015B2 0020F85E SW V0, 32(S8)\r
601: pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. */\r
-BFD015B6 0020FC7E LW V1, 32(S8)
-BFD015B8 30400020 SRL AT, ZERO, 6
-BFD015BA FFF83040 ADDIU V0, ZERO, -8
-BFD015BC 4493FFF8 LW RA, 17555(T8)
-BFD015BE 4493 AND16 V0, V1
-BFD015C0 0020F85E SW V0, 32(S8)
+BFD015B6 0020FC7E LW V1, 32(S8)\r
+BFD015B8 30400020 SRL AT, ZERO, 6\r
+BFD015BA FFF83040 ADDIU V0, ZERO, -8\r
+BFD015BC 4493FFF8 LW RA, 17555(T8)\r
+BFD015BE 4493 AND16 V0, V1\r
+BFD015C0 0020F85E SW V0, 32(S8)\r
602: \r
603: /* Check the alignment of the calculated top of stack is correct. */\r
604: configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );\r
-BFD015C4 0020FC5E LW V0, 32(S8)
-BFD015C8 2D25 ANDI V0, V0, 0x7
-BFD015CA 000940E2 BEQZC V0, 0xBFD015E0
-BFD015CE BFD141A2 LUI V0, 0xBFD1
-BFD015D0 3082BFD1 LDC1 F30, 12418(S1)
-BFD015D2 98103082 ADDIU A0, V0, -26608
-BFD015D4 30A09810 SWC1 F0, 12448(S0)
-BFD015D6 025C30A0 ADDIU A1, ZERO, 604
-BFD015DA 4B7E77E8 JALS vAssertCalled
-BFD015DC 4B7E LW K1, 120(SP)
-BFD015DE 0C00 NOP
+BFD015C4 0020FC5E LW V0, 32(S8)\r
+BFD015C8 2D25 ANDI V0, V0, 0x7\r
+BFD015CA 000940E2 BEQZC V0, 0xBFD015E0\r
+BFD015CE BFD141A2 LUI V0, 0xBFD1\r
+BFD015D0 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD015D2 98103082 ADDIU A0, V0, -26608\r
+BFD015D4 30A09810 SWC1 F0, 12448(S0)\r
+BFD015D6 025C30A0 ADDIU A1, ZERO, 604\r
+BFD015DA 4B7E77E8 JALS vAssertCalled\r
+BFD015DC 4B7E LW K1, 120(SP)\r
+BFD015DE 0C00 NOP\r
605: }\r
606: #else /* portSTACK_GROWTH */\r
607: {\r
619: \r
620: /* Setup the newly allocated TCB with the initial state of the task. */\r
621: prvInitialiseTCBVariables( pxNewTCB, pcName, uxPriority, xRegions, usStackDepth );\r
-BFD015E0 0038345E LHU V0, 56(S8)
-BFD015E4 C844 SW V0, 16(SP)
-BFD015E6 001CFC9E LW A0, 28(S8)
-BFD015EA 0034FCBE LW A1, 52(S8)
-BFD015EE 0040FCDE LW A2, 64(S8)
-BFD015F2 004CFCFE LW A3, 76(S8)
-BFD015F6 1E7477E8 JALS prvInitialiseTCBVariables
-BFD015F8 0C001E74 LB S3, 3072(S4)
-BFD015FA 0C00 NOP
+BFD015E0 0038345E LHU V0, 56(S8)\r
+BFD015E4 C844 SW V0, 16(SP)\r
+BFD015E6 001CFC9E LW A0, 28(S8)\r
+BFD015EA 0034FCBE LW A1, 52(S8)\r
+BFD015EE 0040FCDE LW A2, 64(S8)\r
+BFD015F2 004CFCFE LW A3, 76(S8)\r
+BFD015F6 1E7477E8 JALS prvInitialiseTCBVariables\r
+BFD015F8 0C001E74 LB S3, 3072(S4)\r
+BFD015FA 0C00 NOP\r
622: \r
623: /* Initialize the TCB stack to look as if the task was already running,\r
624: but had been interrupted by the scheduler. The return address is set\r
631: #else /* portUSING_MPU_WRAPPERS */\r
632: {\r
633: pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );\r
-BFD015FC 0020FC9E LW A0, 32(S8)
-BFD01600 0030FCBE LW A1, 48(S8)
-BFD01604 003CFCDE LW A2, 60(S8)
-BFD01608 2B1877E8 JALS pxPortInitialiseStack
-BFD0160A 2B18 LHU A2, 16(S1)
-BFD0160C 0C00 NOP
-BFD0160E 0C62 MOVE V1, V0
-BFD01610 001CFC5E LW V0, 28(S8)
-BFD01614 E9A0 SW V1, 0(V0)
+BFD015FC 0020FC9E LW A0, 32(S8)\r
+BFD01600 0030FCBE LW A1, 48(S8)\r
+BFD01604 003CFCDE LW A2, 60(S8)\r
+BFD01608 2B1877E8 JALS pxPortInitialiseStack\r
+BFD0160A 2B18 LHU A2, 16(S1)\r
+BFD0160C 0C00 NOP\r
+BFD0160E 0C62 MOVE V1, V0\r
+BFD01610 001CFC5E LW V0, 28(S8)\r
+BFD01614 E9A0 SW V1, 0(V0)\r
634: }\r
635: #endif /* portUSING_MPU_WRAPPERS */\r
636: \r
637: if( ( void * ) pxCreatedTask != NULL )\r
-BFD01616 0044FC5E LW V0, 68(S8)
-BFD0161A 000540E2 BEQZC V0, 0xBFD01628
+BFD01616 0044FC5E LW V0, 68(S8)\r
+BFD0161A 000540E2 BEQZC V0, 0xBFD01628\r
638: {\r
639: /* Pass the TCB out - in an anonymous way. The calling function/\r
640: task can use this as a handle to delete the task later if\r
641: required.*/\r
642: *pxCreatedTask = ( TaskHandle_t ) pxNewTCB;\r
-BFD0161E 0044FC5E LW V0, 68(S8)
-BFD01622 001CFC7E LW V1, 28(S8)
-BFD01626 E9A0 SW V1, 0(V0)
+BFD0161E 0044FC5E LW V0, 68(S8)\r
+BFD01622 001CFC7E LW V1, 28(S8)\r
+BFD01626 E9A0 SW V1, 0(V0)\r
643: }\r
644: else\r
645: {\r
649: /* Ensure interrupts don't access the task lists while they are being\r
650: updated. */\r
651: taskENTER_CRITICAL();\r
-BFD01628 33B877E8 JALS vTaskEnterCritical
-BFD0162A 0C0033B8 ADDIU SP, T8, 3072
-BFD0162C 0C00 NOP
+BFD01628 33B877E8 JALS vTaskEnterCritical\r
+BFD0162A 0C0033B8 ADDIU SP, T8, 3072\r
+BFD0162C 0C00 NOP\r
652: {\r
653: uxCurrentNumberOfTasks++;\r
-BFD0162E 8038FC5C LW V0, -32712(GP)
-BFD01632 6D20 ADDIU V0, V0, 1
-BFD01634 8038F85C SW V0, -32712(GP)
+BFD0162E 8038FC5C LW V0, -32712(GP)\r
+BFD01632 6D20 ADDIU V0, V0, 1\r
+BFD01634 8038F85C SW V0, -32712(GP)\r
654: if( pxCurrentTCB == NULL )\r
-BFD01638 8030FC5C LW V0, -32720(GP)
-BFD0163C 000F40A2 BNEZC V0, 0xBFD0165E
+BFD01638 8030FC5C LW V0, -32720(GP)\r
+BFD0163C 000F40A2 BNEZC V0, 0xBFD0165E\r
655: {\r
656: /* There are no other tasks, or all the other tasks are in\r
657: the suspended state - make this the current task. */\r
658: pxCurrentTCB = pxNewTCB;\r
-BFD01640 001CFC5E LW V0, 28(S8)
-BFD01644 8030F85C SW V0, -32720(GP)
+BFD01640 001CFC5E LW V0, 28(S8)\r
+BFD01644 8030F85C SW V0, -32720(GP)\r
659: \r
660: if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )\r
-BFD01648 8038FC7C LW V1, -32712(GP)
-BFD0164C ED01 LI V0, 1
-BFD0164E 0017B443 BNE V1, V0, 0xBFD01680
-BFD01650 0C000017 SLL ZERO, S7, 1
-BFD01652 0C00 NOP
+BFD01648 8038FC7C LW V1, -32712(GP)\r
+BFD0164C ED01 LI V0, 1\r
+BFD0164E 0017B443 BNE V1, V0, 0xBFD01680\r
+BFD01650 0C000017 SLL ZERO, S7, 1\r
+BFD01652 0C00 NOP\r
661: {\r
662: /* This is the first task to be created so do the preliminary\r
663: initialisation required. We will not recover if this call\r
664: fails, but we will report the failure. */\r
665: prvInitialiseTaskLists();\r
-BFD01654 309677E8 JALS prvInitialiseTaskLists
-BFD01656 0C003096 ADDIU A0, S6, 3072
-BFD01658 0C00 NOP
-BFD0165A CC12 B 0xBFD01680
-BFD0165C 0C00 NOP
+BFD01654 309677E8 JALS prvInitialiseTaskLists\r
+BFD01656 0C003096 ADDIU A0, S6, 3072\r
+BFD01658 0C00 NOP\r
+BFD0165A CC12 B 0xBFD01680\r
+BFD0165C 0C00 NOP\r
666: }\r
667: else\r
668: {\r
675: current task if it is the highest priority task to be created\r
676: so far. */\r
677: if( xSchedulerRunning == pdFALSE )\r
-BFD0165E 8044FC5C LW V0, -32700(GP)
-BFD01662 000D40A2 BNEZC V0, 0xBFD01680
+BFD0165E 8044FC5C LW V0, -32700(GP)\r
+BFD01662 000D40A2 BNEZC V0, 0xBFD01680\r
678: {\r
679: if( pxCurrentTCB->uxPriority <= uxPriority )\r
-BFD01666 8030FC5C LW V0, -32720(GP)
-BFD0166A 69AB LW V1, 44(V0)
-BFD0166C 0040FC5E LW V0, 64(S8)
-BFD01670 13900062 SLTU V0, V0, V1
-BFD01672 40A21390 ADDI GP, S0, 16546
-BFD01674 000440A2 BNEZC V0, 0xBFD01680
+BFD01666 8030FC5C LW V0, -32720(GP)\r
+BFD0166A 69AB LW V1, 44(V0)\r
+BFD0166C 0040FC5E LW V0, 64(S8)\r
+BFD01670 13900062 SLTU V0, V0, V1\r
+BFD01672 40A21390 ADDI GP, S0, 16546\r
+BFD01674 000440A2 BNEZC V0, 0xBFD01680\r
680: {\r
681: pxCurrentTCB = pxNewTCB;\r
-BFD01678 001CFC5E LW V0, 28(S8)
-BFD0167C 8030F85C SW V0, -32720(GP)
+BFD01678 001CFC5E LW V0, 28(S8)\r
+BFD0167C 8030F85C SW V0, -32720(GP)\r
682: }\r
683: else\r
684: {\r
692: }\r
693: \r
694: uxTaskNumber++;\r
-BFD01680 8054FC5C LW V0, -32684(GP)
-BFD01684 6D20 ADDIU V0, V0, 1
-BFD01686 8054F85C SW V0, -32684(GP)
+BFD01680 8054FC5C LW V0, -32684(GP)\r
+BFD01684 6D20 ADDIU V0, V0, 1\r
+BFD01686 8054F85C SW V0, -32684(GP)\r
695: \r
696: #if ( configUSE_TRACE_FACILITY == 1 )\r
697: {\r
702: traceTASK_CREATE( pxNewTCB );\r
703: \r
704: prvAddTaskToReadyList( pxNewTCB );\r
-BFD0168A 001CFC5E LW V0, 28(S8)
-BFD0168E 692B LW V0, 44(V0)
-BFD01690 ED81 LI V1, 1
-BFD01692 18100062 SLLV V1, V0, V1
-BFD01694 FC5C1810 SB ZERO, -932(S0)
-BFD01696 8040FC5C LW V0, -32704(GP)
-BFD0169A 44D3 OR16 V0, V1
-BFD0169C 8040F85C SW V0, -32704(GP)
-BFD016A0 001CFC5E LW V0, 28(S8)
-BFD016A4 692B LW V0, 44(V0)
-BFD016A6 2524 SLL V0, V0, 2
-BFD016A8 25A4 SLL V1, V0, 2
-BFD016AA 05B4 ADDU V1, V0, V1
-BFD016AC BFD241A2 LUI V0, 0xBFD2
-BFD016AE 3042BFD2 LDC1 F30, 12354(S2)
-BFD016B0 806C3042 ADDIU V0, V0, -32660
-BFD016B4 05A6 ADDU V1, V1, V0
-BFD016B6 001CFC5E LW V0, 28(S8)
-BFD016BA 6D22 ADDIU V0, V0, 4
-BFD016BC 0C83 MOVE A0, V1
-BFD016BE 0CA2 MOVE A1, V0
-BFD016C0 3E4A77E8 JALS vListInsertEnd
-BFD016C2 0C003E4A LH S2, 3072(T2)
-BFD016C4 0C00 NOP
+BFD0168A 001CFC5E LW V0, 28(S8)\r
+BFD0168E 692B LW V0, 44(V0)\r
+BFD01690 ED81 LI V1, 1\r
+BFD01692 18100062 SLLV V1, V0, V1\r
+BFD01694 FC5C1810 SB ZERO, -932(S0)\r
+BFD01696 8040FC5C LW V0, -32704(GP)\r
+BFD0169A 44D3 OR16 V0, V1\r
+BFD0169C 8040F85C SW V0, -32704(GP)\r
+BFD016A0 001CFC5E LW V0, 28(S8)\r
+BFD016A4 692B LW V0, 44(V0)\r
+BFD016A6 2524 SLL V0, V0, 2\r
+BFD016A8 25A4 SLL V1, V0, 2\r
+BFD016AA 05B4 ADDU V1, V0, V1\r
+BFD016AC BFD241A2 LUI V0, 0xBFD2\r
+BFD016AE 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD016B0 806C3042 ADDIU V0, V0, -32660\r
+BFD016B4 05A6 ADDU V1, V1, V0\r
+BFD016B6 001CFC5E LW V0, 28(S8)\r
+BFD016BA 6D22 ADDIU V0, V0, 4\r
+BFD016BC 0C83 MOVE A0, V1\r
+BFD016BE 0CA2 MOVE A1, V0\r
+BFD016C0 3E4A77E8 JALS vListInsertEnd\r
+BFD016C2 0C003E4A LH S2, 3072(T2)\r
+BFD016C4 0C00 NOP\r
705: \r
706: xReturn = pdPASS;\r
-BFD016C6 ED01 LI V0, 1
-BFD016C8 0018F85E SW V0, 24(S8)
+BFD016C6 ED01 LI V0, 1\r
+BFD016C8 0018F85E SW V0, 24(S8)\r
707: portSETUP_TCB( pxNewTCB );\r
708: }\r
709: taskEXIT_CRITICAL();\r
-BFD016CC 40AA77E8 JALS vTaskExitCritical
-BFD016CE 0C0040AA BNEZC T2, 0xBFD02ED2
-BFD016D0 0C00 NOP
-BFD016D2 CC04 B 0xBFD016DC
-BFD016D4 0C00 NOP
+BFD016CC 40AA77E8 JALS vTaskExitCritical\r
+BFD016CE 0C0040AA BNEZC T2, 0xBFD02ED2\r
+BFD016D0 0C00 NOP\r
+BFD016D2 CC04 B 0xBFD016DC\r
+BFD016D4 0C00 NOP\r
710: }\r
711: else\r
712: {\r
713: xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;\r
-BFD016D6 ED7F LI V0, -1
-BFD016D8 0018F85E SW V0, 24(S8)
+BFD016D6 ED7F LI V0, -1\r
+BFD016D8 0018F85E SW V0, 24(S8)\r
714: traceTASK_CREATE_FAILED();\r
715: }\r
716: \r
717: if( xReturn == pdPASS )\r
-BFD016DC 0018FC7E LW V1, 24(S8)
-BFD016E0 ED01 LI V0, 1
-BFD016E2 001EB443 BNE V1, V0, 0xBFD01722
-BFD016E4 0C00001E SLL ZERO, S8, 1
-BFD016E6 0C00 NOP
+BFD016DC 0018FC7E LW V1, 24(S8)\r
+BFD016E0 ED01 LI V0, 1\r
+BFD016E2 001EB443 BNE V1, V0, 0xBFD01722\r
+BFD016E4 0C00001E SLL ZERO, S8, 1\r
+BFD016E6 0C00 NOP\r
718: {\r
719: if( xSchedulerRunning != pdFALSE )\r
-BFD016E8 8044FC5C LW V0, -32700(GP)
-BFD016EC 001940E2 BEQZC V0, 0xBFD01722
+BFD016E8 8044FC5C LW V0, -32700(GP)\r
+BFD016EC 001940E2 BEQZC V0, 0xBFD01722\r
720: {\r
721: /* If the created task is of a higher priority than the current task\r
722: then it should run now. */\r
723: if( pxCurrentTCB->uxPriority < uxPriority )\r
-BFD016F0 8030FC5C LW V0, -32720(GP)
-BFD016F4 69AB LW V1, 44(V0)
-BFD016F6 0040FC5E LW V0, 64(S8)
-BFD016FA 13900043 SLTU V0, V1, V0
-BFD016FC 40E21390 ADDI GP, S0, 16610
-BFD016FE 001040E2 BEQZC V0, 0xBFD01722
+BFD016F0 8030FC5C LW V0, -32720(GP)\r
+BFD016F4 69AB LW V1, 44(V0)\r
+BFD016F6 0040FC5E LW V0, 64(S8)\r
+BFD016FA 13900043 SLTU V0, V1, V0\r
+BFD016FC 40E21390 ADDI GP, S0, 16610\r
+BFD016FE 001040E2 BEQZC V0, 0xBFD01722\r
724: {\r
725: taskYIELD_IF_USING_PREEMPTION();\r
-BFD01702 4E5677E8 JALS ulPortGetCP0Cause
-BFD01704 4E56 ADDIU S2, S2, -5
-BFD01706 0C00 NOP
-BFD01708 0024F85E SW V0, 36(S8)
-BFD0170C 0024FC5E LW V0, 36(S8)
-BFD01710 01005042 ORI V0, V0, 256
-BFD01714 0024F85E SW V0, 36(S8)
-BFD01718 0024FC9E LW A0, 36(S8)
-BFD0171C 4E6677E8 JALS vPortSetCP0Cause
-BFD0171E 4E66 ADDIU S3, S3, 3
-BFD01720 0C00 NOP
+BFD01702 4E5677E8 JALS ulPortGetCP0Cause\r
+BFD01704 4E56 ADDIU S2, S2, -5\r
+BFD01706 0C00 NOP\r
+BFD01708 0024F85E SW V0, 36(S8)\r
+BFD0170C 0024FC5E LW V0, 36(S8)\r
+BFD01710 01005042 ORI V0, V0, 256\r
+BFD01714 0024F85E SW V0, 36(S8)\r
+BFD01718 0024FC9E LW A0, 36(S8)\r
+BFD0171C 4E6677E8 JALS vPortSetCP0Cause\r
+BFD0171E 4E66 ADDIU S3, S3, 3\r
+BFD01720 0C00 NOP\r
726: }\r
727: else\r
728: {\r
736: }\r
737: \r
738: return xReturn;\r
-BFD01722 0018FC5E LW V0, 24(S8)
+BFD01722 0018FC5E LW V0, 24(S8)\r
739: }\r
-BFD01726 0FBE MOVE SP, S8
-BFD01728 4BEB LW RA, 44(SP)
-BFD0172A 4BCA LW S8, 40(SP)
-BFD0172C 4C19 ADDIU SP, SP, 48
-BFD0172E 459F JR16 RA
-BFD01730 0C00 NOP
+BFD01726 0FBE MOVE SP, S8\r
+BFD01728 4BEB LW RA, 44(SP)\r
+BFD0172A 4BCA LW S8, 40(SP)\r
+BFD0172C 4C19 ADDIU SP, SP, 48\r
+BFD0172E 459F JR16 RA\r
+BFD01730 0C00 NOP\r
740: /*-----------------------------------------------------------*/\r
741: \r
742: #if ( INCLUDE_vTaskDelete == 1 )\r
743: \r
744: void vTaskDelete( TaskHandle_t xTaskToDelete )\r
745: {\r
-BFD033F4 4FF1 ADDIU SP, SP, -32
-BFD033F6 CBE7 SW RA, 28(SP)
-BFD033F8 CBC6 SW S8, 24(SP)
-BFD033FA 0FDD MOVE S8, SP
-BFD033FC 0020F89E SW A0, 32(S8)
+BFD033F4 4FF1 ADDIU SP, SP, -32\r
+BFD033F6 CBE7 SW RA, 28(SP)\r
+BFD033F8 CBC6 SW S8, 24(SP)\r
+BFD033FA 0FDD MOVE S8, SP\r
+BFD033FC 0020F89E SW A0, 32(S8)\r
746: TCB_t *pxTCB;\r
747: \r
748: taskENTER_CRITICAL();\r
-BFD03400 33B877E8 JALS vTaskEnterCritical
-BFD03402 0C0033B8 ADDIU SP, T8, 3072
-BFD03404 0C00 NOP
+BFD03400 33B877E8 JALS vTaskEnterCritical\r
+BFD03402 0C0033B8 ADDIU SP, T8, 3072\r
+BFD03404 0C00 NOP\r
749: {\r
750: /* If null is passed in here then it is the calling task that is\r
751: being deleted. */\r
752: pxTCB = prvGetTCBFromHandle( xTaskToDelete );\r
-BFD03406 0020FC5E LW V0, 32(S8)
-BFD0340A 000440A2 BNEZC V0, 0xBFD03416
-BFD0340E 8030FC5C LW V0, -32720(GP)
-BFD03412 CC03 B 0xBFD0341A
-BFD03414 0C00 NOP
-BFD03416 0020FC5E LW V0, 32(S8)
-BFD0341A 0010F85E SW V0, 16(S8)
+BFD03406 0020FC5E LW V0, 32(S8)\r
+BFD0340A 000440A2 BNEZC V0, 0xBFD03416\r
+BFD0340E 8030FC5C LW V0, -32720(GP)\r
+BFD03412 CC03 B 0xBFD0341A\r
+BFD03414 0C00 NOP\r
+BFD03416 0020FC5E LW V0, 32(S8)\r
+BFD0341A 0010F85E SW V0, 16(S8)\r
753: \r
754: /* Remove task from the ready list and place in the termination list.\r
755: This will stop the task from be scheduled. The idle task will check\r
756: the termination list and free up any memory allocated by the\r
757: scheduler for the TCB and stack. */\r
758: if( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r
-BFD0341E 0010FC5E LW V0, 16(S8)
-BFD03422 6D22 ADDIU V0, V0, 4
-BFD03424 0C82 MOVE A0, V0
-BFD03426 00C877E8 JALS uxListRemove
-BFD03428 0C0000C8 SLL A2, T0, 1
-BFD0342A 0C00 NOP
-BFD0342C 001A40A2 BNEZC V0, 0xBFD03464
+BFD0341E 0010FC5E LW V0, 16(S8)\r
+BFD03422 6D22 ADDIU V0, V0, 4\r
+BFD03424 0C82 MOVE A0, V0\r
+BFD03426 00C877E8 JALS uxListRemove\r
+BFD03428 0C0000C8 SLL A2, T0, 1\r
+BFD0342A 0C00 NOP\r
+BFD0342C 001A40A2 BNEZC V0, 0xBFD03464\r
759: {\r
760: taskRESET_READY_PRIORITY( pxTCB->uxPriority );\r
-BFD03430 0010FC5E LW V0, 16(S8)
-BFD03434 692B LW V0, 44(V0)
-BFD03436 2524 SLL V0, V0, 2
-BFD03438 25A4 SLL V1, V0, 2
-BFD0343A 05B4 ADDU V1, V0, V1
-BFD0343C BFD241A2 LUI V0, 0xBFD2
-BFD0343E 3042BFD2 LDC1 F30, 12354(S2)
-BFD03440 806C3042 ADDIU V0, V0, -32660
-BFD03444 0526 ADDU V0, V1, V0
-BFD03446 6920 LW V0, 0(V0)
-BFD03448 000C40A2 BNEZC V0, 0xBFD03464
-BFD0344C 0010FC5E LW V0, 16(S8)
-BFD03450 692B LW V0, 44(V0)
-BFD03452 ED81 LI V1, 1
-BFD03454 10100062 SLLV V0, V0, V1
-BFD03456 441A1010 ADDI ZERO, S0, 17434
-BFD03458 441A NOT16 V1, V0
-BFD0345A 8040FC5C LW V0, -32704(GP)
-BFD0345E 4493 AND16 V0, V1
-BFD03460 8040F85C SW V0, -32704(GP)
+BFD03430 0010FC5E LW V0, 16(S8)\r
+BFD03434 692B LW V0, 44(V0)\r
+BFD03436 2524 SLL V0, V0, 2\r
+BFD03438 25A4 SLL V1, V0, 2\r
+BFD0343A 05B4 ADDU V1, V0, V1\r
+BFD0343C BFD241A2 LUI V0, 0xBFD2\r
+BFD0343E 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD03440 806C3042 ADDIU V0, V0, -32660\r
+BFD03444 0526 ADDU V0, V1, V0\r
+BFD03446 6920 LW V0, 0(V0)\r
+BFD03448 000C40A2 BNEZC V0, 0xBFD03464\r
+BFD0344C 0010FC5E LW V0, 16(S8)\r
+BFD03450 692B LW V0, 44(V0)\r
+BFD03452 ED81 LI V1, 1\r
+BFD03454 10100062 SLLV V0, V0, V1\r
+BFD03456 441A1010 ADDI ZERO, S0, 17434\r
+BFD03458 441A NOT16 V1, V0\r
+BFD0345A 8040FC5C LW V0, -32704(GP)\r
+BFD0345E 4493 AND16 V0, V1\r
+BFD03460 8040F85C SW V0, -32704(GP)\r
761: }\r
762: else\r
763: {\r
766: \r
767: /* Is the task waiting on an event also? */\r
768: if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )\r
-BFD03464 0010FC5E LW V0, 16(S8)
-BFD03468 692A LW V0, 40(V0)
-BFD0346A 000740E2 BEQZC V0, 0xBFD0347C
+BFD03464 0010FC5E LW V0, 16(S8)\r
+BFD03468 692A LW V0, 40(V0)\r
+BFD0346A 000740E2 BEQZC V0, 0xBFD0347C\r
769: {\r
770: ( void ) uxListRemove( &( pxTCB->xEventListItem ) );\r
-BFD0346E 0010FC5E LW V0, 16(S8)
-BFD03470 6D2C0010 EXT ZERO, S0, 20, 14
-BFD03472 6D2C ADDIU V0, V0, 24
-BFD03474 0C82 MOVE A0, V0
-BFD03476 00C877E8 JALS uxListRemove
-BFD03478 0C0000C8 SLL A2, T0, 1
-BFD0347A 0C00 NOP
+BFD0346E 0010FC5E LW V0, 16(S8)\r
+BFD03470 6D2C0010 EXT ZERO, S0, 20, 14\r
+BFD03472 6D2C ADDIU V0, V0, 24\r
+BFD03474 0C82 MOVE A0, V0\r
+BFD03476 00C877E8 JALS uxListRemove\r
+BFD03478 0C0000C8 SLL A2, T0, 1\r
+BFD0347A 0C00 NOP\r
771: }\r
772: else\r
773: {\r
775: }\r
776: \r
777: vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xGenericListItem ) );\r
-BFD0347C 0010FC5E LW V0, 16(S8)
-BFD03480 6D22 ADDIU V0, V0, 4
-BFD03482 BFD241A3 LUI V1, 0xBFD2
-BFD03484 3083BFD2 LDC1 F30, 12419(S2)
-BFD03486 810C3083 ADDIU A0, V1, -32500
-BFD0348A 0CA2 MOVE A1, V0
-BFD0348C 3E4A77E8 JALS vListInsertEnd
-BFD0348E 0C003E4A LH S2, 3072(T2)
-BFD03490 0C00 NOP
+BFD0347C 0010FC5E LW V0, 16(S8)\r
+BFD03480 6D22 ADDIU V0, V0, 4\r
+BFD03482 BFD241A3 LUI V1, 0xBFD2\r
+BFD03484 3083BFD2 LDC1 F30, 12419(S2)\r
+BFD03486 810C3083 ADDIU A0, V1, -32500\r
+BFD0348A 0CA2 MOVE A1, V0\r
+BFD0348C 3E4A77E8 JALS vListInsertEnd\r
+BFD0348E 0C003E4A LH S2, 3072(T2)\r
+BFD03490 0C00 NOP\r
778: \r
779: /* Increment the ucTasksDeleted variable so the idle task knows\r
780: there is a task that has been deleted and that it should therefore\r
781: check the xTasksWaitingTermination list. */\r
782: ++uxTasksDeleted;\r
-BFD03492 8034FC5C LW V0, -32716(GP)
-BFD03496 6D20 ADDIU V0, V0, 1
-BFD03498 8034F85C SW V0, -32716(GP)
+BFD03492 8034FC5C LW V0, -32716(GP)\r
+BFD03496 6D20 ADDIU V0, V0, 1\r
+BFD03498 8034F85C SW V0, -32716(GP)\r
783: \r
784: /* Increment the uxTaskNumberVariable also so kernel aware debuggers\r
785: can detect that the task lists need re-generating. */\r
786: uxTaskNumber++;\r
-BFD0349C 8054FC5C LW V0, -32684(GP)
-BFD034A0 6D20 ADDIU V0, V0, 1
-BFD034A2 8054F85C SW V0, -32684(GP)
+BFD0349C 8054FC5C LW V0, -32684(GP)\r
+BFD034A0 6D20 ADDIU V0, V0, 1\r
+BFD034A2 8054F85C SW V0, -32684(GP)\r
787: \r
788: traceTASK_DELETE( pxTCB );\r
789: }\r
790: taskEXIT_CRITICAL();\r
-BFD034A6 40AA77E8 JALS vTaskExitCritical
-BFD034A8 0C0040AA BNEZC T2, 0xBFD04CAC
-BFD034AA 0C00 NOP
+BFD034A6 40AA77E8 JALS vTaskExitCritical\r
+BFD034A8 0C0040AA BNEZC T2, 0xBFD04CAC\r
+BFD034AA 0C00 NOP\r
791: \r
792: /* Force a reschedule if it is the currently running task that has just\r
793: been deleted. */\r
794: if( xSchedulerRunning != pdFALSE )\r
-BFD034AC 8044FC5C LW V0, -32700(GP)
-BFD034B0 002F40E2 BEQZC V0, 0xBFD03512
+BFD034AC 8044FC5C LW V0, -32700(GP)\r
+BFD034B0 002F40E2 BEQZC V0, 0xBFD03512\r
795: {\r
796: if( pxTCB == pxCurrentTCB )\r
-BFD034B4 8030FC5C LW V0, -32720(GP)
-BFD034B8 0010FC7E LW V1, 16(S8)
-BFD034BC 0020B443 BNE V1, V0, 0xBFD03500
-BFD034BE 0C000020 SLL AT, ZERO, 1
-BFD034C0 0C00 NOP
+BFD034B4 8030FC5C LW V0, -32720(GP)\r
+BFD034B8 0010FC7E LW V1, 16(S8)\r
+BFD034BC 0020B443 BNE V1, V0, 0xBFD03500\r
+BFD034BE 0C000020 SLL AT, ZERO, 1\r
+BFD034C0 0C00 NOP\r
797: {\r
798: configASSERT( uxSchedulerSuspended == 0 );\r
-BFD034C2 805CFC5C LW V0, -32676(GP)
-BFD034C6 000940E2 BEQZC V0, 0xBFD034DC
-BFD034CA BFD141A2 LUI V0, 0xBFD1
-BFD034CC 3082BFD1 LDC1 F30, 12418(S1)
-BFD034CE 98103082 ADDIU A0, V0, -26608
-BFD034D0 30A09810 SWC1 F0, 12448(S0)
-BFD034D2 031E30A0 ADDIU A1, ZERO, 798
-BFD034D6 4B7E77E8 JALS vAssertCalled
-BFD034D8 4B7E LW K1, 120(SP)
-BFD034DA 0C00 NOP
+BFD034C2 805CFC5C LW V0, -32676(GP)\r
+BFD034C6 000940E2 BEQZC V0, 0xBFD034DC\r
+BFD034CA BFD141A2 LUI V0, 0xBFD1\r
+BFD034CC 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD034CE 98103082 ADDIU A0, V0, -26608\r
+BFD034D0 30A09810 SWC1 F0, 12448(S0)\r
+BFD034D2 031E30A0 ADDIU A1, ZERO, 798\r
+BFD034D6 4B7E77E8 JALS vAssertCalled\r
+BFD034D8 4B7E LW K1, 120(SP)\r
+BFD034DA 0C00 NOP\r
799: \r
800: /* The pre-delete hook is primarily for the Windows simulator,\r
801: in which Windows specific clean up operations are performed,\r
804: required. */\r
805: portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );\r
806: portYIELD_WITHIN_API();\r
-BFD034DC 4E5677E8 JALS ulPortGetCP0Cause
-BFD034DE 4E56 ADDIU S2, S2, -5
-BFD034E0 0C00 NOP
-BFD034E2 0014F85E SW V0, 20(S8)
-BFD034E6 0014FC5E LW V0, 20(S8)
-BFD034EA 01005042 ORI V0, V0, 256
-BFD034EE 0014F85E SW V0, 20(S8)
-BFD034F2 0014FC9E LW A0, 20(S8)
-BFD034F6 4E6677E8 JALS vPortSetCP0Cause
-BFD034F8 4E66 ADDIU S3, S3, 3
-BFD034FA 0C00 NOP
-BFD034FC CC0A B 0xBFD03512
-BFD034FE 0C00 NOP
+BFD034DC 4E5677E8 JALS ulPortGetCP0Cause\r
+BFD034DE 4E56 ADDIU S2, S2, -5\r
+BFD034E0 0C00 NOP\r
+BFD034E2 0014F85E SW V0, 20(S8)\r
+BFD034E6 0014FC5E LW V0, 20(S8)\r
+BFD034EA 01005042 ORI V0, V0, 256\r
+BFD034EE 0014F85E SW V0, 20(S8)\r
+BFD034F2 0014FC9E LW A0, 20(S8)\r
+BFD034F6 4E6677E8 JALS vPortSetCP0Cause\r
+BFD034F8 4E66 ADDIU S3, S3, 3\r
+BFD034FA 0C00 NOP\r
+BFD034FC CC0A B 0xBFD03512\r
+BFD034FE 0C00 NOP\r
807: }\r
808: else\r
809: {\r
810: /* Reset the next expected unblock time in case it referred to\r
811: the task that has just been deleted. */\r
812: taskENTER_CRITICAL();\r
-BFD03500 33B877E8 JALS vTaskEnterCritical
-BFD03502 0C0033B8 ADDIU SP, T8, 3072
-BFD03504 0C00 NOP
+BFD03500 33B877E8 JALS vTaskEnterCritical\r
+BFD03502 0C0033B8 ADDIU SP, T8, 3072\r
+BFD03504 0C00 NOP\r
813: {\r
814: prvResetNextTaskUnblockTime();\r
-BFD03506 47CA77E8 JALS prvResetNextTaskUnblockTime
-BFD0350A 0C00 NOP
+BFD03506 47CA77E8 JALS prvResetNextTaskUnblockTime\r
+BFD0350A 0C00 NOP\r
815: }\r
816: taskEXIT_CRITICAL();\r
-BFD0350C 40AA77E8 JALS vTaskExitCritical
-BFD0350E 0C0040AA BNEZC T2, 0xBFD04D12
-BFD03510 0C00 NOP
+BFD0350C 40AA77E8 JALS vTaskExitCritical\r
+BFD0350E 0C0040AA BNEZC T2, 0xBFD04D12\r
+BFD03510 0C00 NOP\r
817: }\r
818: }\r
819: }\r
-BFD03512 0FBE MOVE SP, S8
-BFD03514 4BE7 LW RA, 28(SP)
-BFD03516 4BC6 LW S8, 24(SP)
-BFD03518 4C11 ADDIU SP, SP, 32
-BFD0351A 459F JR16 RA
-BFD0351C 0C00 NOP
+BFD03512 0FBE MOVE SP, S8\r
+BFD03514 4BE7 LW RA, 28(SP)\r
+BFD03516 4BC6 LW S8, 24(SP)\r
+BFD03518 4C11 ADDIU SP, SP, 32\r
+BFD0351A 459F JR16 RA\r
+BFD0351C 0C00 NOP\r
820: \r
821: #endif /* INCLUDE_vTaskDelete */\r
822: /*-----------------------------------------------------------*/\r
825: \r
826: void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement )\r
827: {\r
-BFD00008 4FE9 ADDIU SP, SP, -48
-BFD0000A CBEB SW RA, 44(SP)
-BFD0000C CBCA SW S8, 40(SP)
-BFD0000E 0FDD MOVE S8, SP
-BFD00010 0030F89E SW A0, 48(S8)
-BFD00014 0034F8BE SW A1, 52(S8)
+BFD00008 4FE9 ADDIU SP, SP, -48\r
+BFD0000A CBEB SW RA, 44(SP)\r
+BFD0000C CBCA SW S8, 40(SP)\r
+BFD0000E 0FDD MOVE S8, SP\r
+BFD00010 0030F89E SW A0, 48(S8)\r
+BFD00014 0034F8BE SW A1, 52(S8)\r
828: TickType_t xTimeToWake;\r
829: BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;\r
-BFD00018 0010F81E SW ZERO, 16(S8)
+BFD00018 0010F81E SW ZERO, 16(S8)\r
830: \r
831: configASSERT( pxPreviousWakeTime );\r
-BFD0001C 0030FC5E LW V0, 48(S8)
-BFD00020 000940A2 BNEZC V0, 0xBFD00036
-BFD00024 BFD141A2 LUI V0, 0xBFD1
-BFD00026 3082BFD1 LDC1 F30, 12418(S1)
-BFD00028 98103082 ADDIU A0, V0, -26608
-BFD0002A 30A09810 SWC1 F0, 12448(S0)
-BFD0002C 033F30A0 ADDIU A1, ZERO, 831
-BFD00030 4B7E77E8 JALS vAssertCalled
-BFD00032 4B7E LW K1, 120(SP)
-BFD00034 0C00 NOP
+BFD0001C 0030FC5E LW V0, 48(S8)\r
+BFD00020 000940A2 BNEZC V0, 0xBFD00036\r
+BFD00024 BFD141A2 LUI V0, 0xBFD1\r
+BFD00026 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD00028 98103082 ADDIU A0, V0, -26608\r
+BFD0002A 30A09810 SWC1 F0, 12448(S0)\r
+BFD0002C 033F30A0 ADDIU A1, ZERO, 831\r
+BFD00030 4B7E77E8 JALS vAssertCalled\r
+BFD00032 4B7E LW K1, 120(SP)\r
+BFD00034 0C00 NOP\r
832: configASSERT( ( xTimeIncrement > 0U ) );\r
-BFD00036 0034FC5E LW V0, 52(S8)
-BFD0003A 000940A2 BNEZC V0, 0xBFD00050
-BFD0003E BFD141A2 LUI V0, 0xBFD1
-BFD00040 3082BFD1 LDC1 F30, 12418(S1)
-BFD00042 98103082 ADDIU A0, V0, -26608
-BFD00044 30A09810 SWC1 F0, 12448(S0)
-BFD00046 034030A0 ADDIU A1, ZERO, 832
-BFD0004A 4B7E77E8 JALS vAssertCalled
-BFD0004C 4B7E LW K1, 120(SP)
-BFD0004E 0C00 NOP
+BFD00036 0034FC5E LW V0, 52(S8)\r
+BFD0003A 000940A2 BNEZC V0, 0xBFD00050\r
+BFD0003E BFD141A2 LUI V0, 0xBFD1\r
+BFD00040 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD00042 98103082 ADDIU A0, V0, -26608\r
+BFD00044 30A09810 SWC1 F0, 12448(S0)\r
+BFD00046 034030A0 ADDIU A1, ZERO, 832\r
+BFD0004A 4B7E77E8 JALS vAssertCalled\r
+BFD0004C 4B7E LW K1, 120(SP)\r
+BFD0004E 0C00 NOP\r
833: configASSERT( uxSchedulerSuspended == 0 );\r
-BFD00050 805CFC5C LW V0, -32676(GP)
-BFD00054 000940E2 BEQZC V0, 0xBFD0006A
-BFD00058 BFD141A2 LUI V0, 0xBFD1
-BFD0005A 3082BFD1 LDC1 F30, 12418(S1)
-BFD0005C 98103082 ADDIU A0, V0, -26608
-BFD0005E 30A09810 SWC1 F0, 12448(S0)
-BFD00060 034130A0 ADDIU A1, ZERO, 833
-BFD00064 4B7E77E8 JALS vAssertCalled
-BFD00066 4B7E LW K1, 120(SP)
-BFD00068 0C00 NOP
+BFD00050 805CFC5C LW V0, -32676(GP)\r
+BFD00054 000940E2 BEQZC V0, 0xBFD0006A\r
+BFD00058 BFD141A2 LUI V0, 0xBFD1\r
+BFD0005A 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD0005C 98103082 ADDIU A0, V0, -26608\r
+BFD0005E 30A09810 SWC1 F0, 12448(S0)\r
+BFD00060 034130A0 ADDIU A1, ZERO, 833\r
+BFD00064 4B7E77E8 JALS vAssertCalled\r
+BFD00066 4B7E LW K1, 120(SP)\r
+BFD00068 0C00 NOP\r
834: \r
835: vTaskSuspendAll();\r
-BFD0006A 4EF477E8 JALS vTaskSuspendAll
-BFD0006C 4EF4 ADDIU S7, S7, -6
-BFD0006E 0C00 NOP
+BFD0006A 4EF477E8 JALS vTaskSuspendAll\r
+BFD0006C 4EF4 ADDIU S7, S7, -6\r
+BFD0006E 0C00 NOP\r
836: {\r
837: /* Minor optimisation. The tick count cannot change in this\r
838: block. */\r
839: const TickType_t xConstTickCount = xTickCount;\r
-BFD00070 803CFC5C LW V0, -32708(GP)
-BFD00074 0014F85E SW V0, 20(S8)
+BFD00070 803CFC5C LW V0, -32708(GP)\r
+BFD00074 0014F85E SW V0, 20(S8)\r
840: \r
841: /* Generate the tick time at which the task wants to wake. */\r
842: xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;\r
-BFD00078 0030FC5E LW V0, 48(S8)
-BFD0007C 69A0 LW V1, 0(V0)
-BFD0007E 0034FC5E LW V0, 52(S8)
-BFD00082 0526 ADDU V0, V1, V0
-BFD00084 0018F85E SW V0, 24(S8)
+BFD00078 0030FC5E LW V0, 48(S8)\r
+BFD0007C 69A0 LW V1, 0(V0)\r
+BFD0007E 0034FC5E LW V0, 52(S8)\r
+BFD00082 0526 ADDU V0, V1, V0\r
+BFD00084 0018F85E SW V0, 24(S8)\r
843: \r
844: if( xConstTickCount < *pxPreviousWakeTime )\r
-BFD00088 0030FC5E LW V0, 48(S8)
-BFD0008C 69A0 LW V1, 0(V0)
-BFD0008E 0014FC5E LW V0, 20(S8)
-BFD00092 13900062 SLTU V0, V0, V1
-BFD00094 40E21390 ADDI GP, S0, 16610
-BFD00096 001640E2 BEQZC V0, 0xBFD000C6
+BFD00088 0030FC5E LW V0, 48(S8)\r
+BFD0008C 69A0 LW V1, 0(V0)\r
+BFD0008E 0014FC5E LW V0, 20(S8)\r
+BFD00092 13900062 SLTU V0, V0, V1\r
+BFD00094 40E21390 ADDI GP, S0, 16610\r
+BFD00096 001640E2 BEQZC V0, 0xBFD000C6\r
845: {\r
846: /* The tick count has overflowed since this function was\r
847: lasted called. In this case the only time we should ever\r
849: and the wake time is greater than the tick time. When this\r
850: is the case it is as if neither time had overflowed. */\r
851: if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )\r
-BFD0009A 0030FC5E LW V0, 48(S8)
-BFD0009E 69A0 LW V1, 0(V0)
-BFD000A0 0018FC5E LW V0, 24(S8)
-BFD000A4 13900062 SLTU V0, V0, V1
-BFD000A6 40E21390 ADDI GP, S0, 16610
-BFD000A8 002140E2 BEQZC V0, 0xBFD000EE
-BFD000AC 0018FC7E LW V1, 24(S8)
-BFD000B0 0014FC5E LW V0, 20(S8)
-BFD000B4 13900062 SLTU V0, V0, V1
-BFD000B6 40E21390 ADDI GP, S0, 16610
-BFD000B8 001940E2 BEQZC V0, 0xBFD000EE
+BFD0009A 0030FC5E LW V0, 48(S8)\r
+BFD0009E 69A0 LW V1, 0(V0)\r
+BFD000A0 0018FC5E LW V0, 24(S8)\r
+BFD000A4 13900062 SLTU V0, V0, V1\r
+BFD000A6 40E21390 ADDI GP, S0, 16610\r
+BFD000A8 002140E2 BEQZC V0, 0xBFD000EE\r
+BFD000AC 0018FC7E LW V1, 24(S8)\r
+BFD000B0 0014FC5E LW V0, 20(S8)\r
+BFD000B4 13900062 SLTU V0, V0, V1\r
+BFD000B6 40E21390 ADDI GP, S0, 16610\r
+BFD000B8 001940E2 BEQZC V0, 0xBFD000EE\r
852: {\r
853: xShouldDelay = pdTRUE;\r
-BFD000BC ED01 LI V0, 1
-BFD000BE 0010F85E SW V0, 16(S8)
-BFD000C2 CC15 B 0xBFD000EE
-BFD000C4 0C00 NOP
+BFD000BC ED01 LI V0, 1\r
+BFD000BE 0010F85E SW V0, 16(S8)\r
+BFD000C2 CC15 B 0xBFD000EE\r
+BFD000C4 0C00 NOP\r
854: }\r
855: else\r
856: {\r
863: delay if either the wake time has overflowed, and/or the\r
864: tick time is less than the wake time. */\r
865: if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )\r
-BFD000C6 0030FC5E LW V0, 48(S8)
-BFD000CA 69A0 LW V1, 0(V0)
-BFD000CC 0018FC5E LW V0, 24(S8)
-BFD000D0 13900062 SLTU V0, V0, V1
-BFD000D2 40A21390 ADDI GP, S0, 16546
-BFD000D4 000840A2 BNEZC V0, 0xBFD000E8
-BFD000D8 0018FC7E LW V1, 24(S8)
-BFD000DC 0014FC5E LW V0, 20(S8)
-BFD000E0 13900062 SLTU V0, V0, V1
-BFD000E2 40E21390 ADDI GP, S0, 16610
-BFD000E4 000340E2 BEQZC V0, 0xBFD000EE
+BFD000C6 0030FC5E LW V0, 48(S8)\r
+BFD000CA 69A0 LW V1, 0(V0)\r
+BFD000CC 0018FC5E LW V0, 24(S8)\r
+BFD000D0 13900062 SLTU V0, V0, V1\r
+BFD000D2 40A21390 ADDI GP, S0, 16546\r
+BFD000D4 000840A2 BNEZC V0, 0xBFD000E8\r
+BFD000D8 0018FC7E LW V1, 24(S8)\r
+BFD000DC 0014FC5E LW V0, 20(S8)\r
+BFD000E0 13900062 SLTU V0, V0, V1\r
+BFD000E2 40E21390 ADDI GP, S0, 16610\r
+BFD000E4 000340E2 BEQZC V0, 0xBFD000EE\r
866: {\r
867: xShouldDelay = pdTRUE;\r
-BFD000E8 ED01 LI V0, 1
-BFD000EA 0010F85E SW V0, 16(S8)
+BFD000E8 ED01 LI V0, 1\r
+BFD000EA 0010F85E SW V0, 16(S8)\r
868: }\r
869: else\r
870: {\r
874: \r
875: /* Update the wake time ready for the next call. */\r
876: *pxPreviousWakeTime = xTimeToWake;\r
-BFD000EE 0030FC5E LW V0, 48(S8)
-BFD000F2 0018FC7E LW V1, 24(S8)
-BFD000F6 E9A0 SW V1, 0(V0)
+BFD000EE 0030FC5E LW V0, 48(S8)\r
+BFD000F2 0018FC7E LW V1, 24(S8)\r
+BFD000F6 E9A0 SW V1, 0(V0)\r
877: \r
878: if( xShouldDelay != pdFALSE )\r
-BFD000F8 0010FC5E LW V0, 16(S8)
-BFD000FC 001A40E2 BEQZC V0, 0xBFD00134
+BFD000F8 0010FC5E LW V0, 16(S8)\r
+BFD000FC 001A40E2 BEQZC V0, 0xBFD00134\r
879: {\r
880: traceTASK_DELAY_UNTIL();\r
881: \r
882: /* Remove the task from the ready list before adding it to the\r
883: blocked list as the same list item is used for both lists. */\r
884: if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r
-BFD00100 8030FC5C LW V0, -32720(GP)
-BFD00104 6D22 ADDIU V0, V0, 4
-BFD00106 0C82 MOVE A0, V0
-BFD00108 00C877E8 JALS uxListRemove
-BFD0010A 0C0000C8 SLL A2, T0, 1
-BFD0010C 0C00 NOP
-BFD0010E 000C40A2 BNEZC V0, 0xBFD0012A
+BFD00100 8030FC5C LW V0, -32720(GP)\r
+BFD00104 6D22 ADDIU V0, V0, 4\r
+BFD00106 0C82 MOVE A0, V0\r
+BFD00108 00C877E8 JALS uxListRemove\r
+BFD0010A 0C0000C8 SLL A2, T0, 1\r
+BFD0010C 0C00 NOP\r
+BFD0010E 000C40A2 BNEZC V0, 0xBFD0012A\r
885: {\r
886: /* The current task must be in a ready list, so there is\r
887: no need to check, and the port reset macro can be called\r
888: directly. */\r
889: portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );\r
-BFD00112 8030FC5C LW V0, -32720(GP)
-BFD00116 692B LW V0, 44(V0)
-BFD00118 ED81 LI V1, 1
-BFD0011A 10100062 SLLV V0, V0, V1
-BFD0011C 441A1010 ADDI ZERO, S0, 17434
-BFD0011E 441A NOT16 V1, V0
-BFD00120 8040FC5C LW V0, -32704(GP)
-BFD00124 4493 AND16 V0, V1
-BFD00126 8040F85C SW V0, -32704(GP)
+BFD00112 8030FC5C LW V0, -32720(GP)\r
+BFD00116 692B LW V0, 44(V0)\r
+BFD00118 ED81 LI V1, 1\r
+BFD0011A 10100062 SLLV V0, V0, V1\r
+BFD0011C 441A1010 ADDI ZERO, S0, 17434\r
+BFD0011E 441A NOT16 V1, V0\r
+BFD00120 8040FC5C LW V0, -32704(GP)\r
+BFD00124 4493 AND16 V0, V1\r
+BFD00126 8040F85C SW V0, -32704(GP)\r
890: }\r
891: else\r
892: {\r
894: }\r
895: \r
896: prvAddCurrentTaskToDelayedList( xTimeToWake );\r
-BFD0012A 0018FC9E LW A0, 24(S8)
-BFD0012E 373477E8 JALS prvAddCurrentTaskToDelayedList
-BFD00130 0C003734 LHU T9, 3072(S4)
-BFD00132 0C00 NOP
+BFD0012A 0018FC9E LW A0, 24(S8)\r
+BFD0012E 373477E8 JALS prvAddCurrentTaskToDelayedList\r
+BFD00130 0C003734 LHU T9, 3072(S4)\r
+BFD00132 0C00 NOP\r
897: }\r
898: else\r
899: {\r
901: }\r
902: }\r
903: xAlreadyYielded = xTaskResumeAll();\r
-BFD00134 158E77E8 JALS xTaskResumeAll
-BFD00136 0C00158E LBU T4, 3072(T6)
-BFD00138 0C00 NOP
-BFD0013A 001CF85E SW V0, 28(S8)
+BFD00134 158E77E8 JALS xTaskResumeAll\r
+BFD00136 0C00158E LBU T4, 3072(T6)\r
+BFD00138 0C00 NOP\r
+BFD0013A 001CF85E SW V0, 28(S8)\r
904: \r
905: /* Force a reschedule if xTaskResumeAll has not already done so, we may\r
906: have put ourselves to sleep. */\r
907: if( xAlreadyYielded == pdFALSE )\r
-BFD0013E 001CFC5E LW V0, 28(S8)
-BFD00142 001040A2 BNEZC V0, 0xBFD00166
+BFD0013E 001CFC5E LW V0, 28(S8)\r
+BFD00142 001040A2 BNEZC V0, 0xBFD00166\r
908: {\r
909: portYIELD_WITHIN_API();\r
-BFD00146 4E5677E8 JALS ulPortGetCP0Cause
-BFD00148 4E56 ADDIU S2, S2, -5
-BFD0014A 0C00 NOP
-BFD0014C 0020F85E SW V0, 32(S8)
-BFD00150 0020FC5E LW V0, 32(S8)
-BFD00154 01005042 ORI V0, V0, 256
-BFD00158 0020F85E SW V0, 32(S8)
-BFD0015C 0020FC9E LW A0, 32(S8)
-BFD00160 4E6677E8 JALS vPortSetCP0Cause
-BFD00162 4E66 ADDIU S3, S3, 3
-BFD00164 0C00 NOP
+BFD00146 4E5677E8 JALS ulPortGetCP0Cause\r
+BFD00148 4E56 ADDIU S2, S2, -5\r
+BFD0014A 0C00 NOP\r
+BFD0014C 0020F85E SW V0, 32(S8)\r
+BFD00150 0020FC5E LW V0, 32(S8)\r
+BFD00154 01005042 ORI V0, V0, 256\r
+BFD00158 0020F85E SW V0, 32(S8)\r
+BFD0015C 0020FC9E LW A0, 32(S8)\r
+BFD00160 4E6677E8 JALS vPortSetCP0Cause\r
+BFD00162 4E66 ADDIU S3, S3, 3\r
+BFD00164 0C00 NOP\r
910: }\r
911: else\r
912: {\r
913: mtCOVERAGE_TEST_MARKER();\r
914: }\r
915: }\r
-BFD00166 0FBE MOVE SP, S8
-BFD00168 4BEB LW RA, 44(SP)
-BFD0016A 4BCA LW S8, 40(SP)
-BFD0016C 4C19 ADDIU SP, SP, 48
-BFD0016E 459F JR16 RA
-BFD00170 0C00 NOP
+BFD00166 0FBE MOVE SP, S8\r
+BFD00168 4BEB LW RA, 44(SP)\r
+BFD0016A 4BCA LW S8, 40(SP)\r
+BFD0016C 4C19 ADDIU SP, SP, 48\r
+BFD0016E 459F JR16 RA\r
+BFD00170 0C00 NOP\r
916: \r
917: #endif /* INCLUDE_vTaskDelayUntil */\r
918: /*-----------------------------------------------------------*/\r
921: \r
922: void vTaskDelay( const TickType_t xTicksToDelay )\r
923: {\r
-BFD05BA0 4FED ADDIU SP, SP, -40
-BFD05BA2 CBE9 SW RA, 36(SP)
-BFD05BA4 CBC8 SW S8, 32(SP)
-BFD05BA6 0FDD MOVE S8, SP
-BFD05BA8 0028F89E SW A0, 40(S8)
+BFD05BA0 4FED ADDIU SP, SP, -40\r
+BFD05BA2 CBE9 SW RA, 36(SP)\r
+BFD05BA4 CBC8 SW S8, 32(SP)\r
+BFD05BA6 0FDD MOVE S8, SP\r
+BFD05BA8 0028F89E SW A0, 40(S8)\r
924: TickType_t xTimeToWake;\r
925: BaseType_t xAlreadyYielded = pdFALSE;\r
-BFD05BAC 0010F81E SW ZERO, 16(S8)
+BFD05BAC 0010F81E SW ZERO, 16(S8)\r
926: \r
927: \r
928: /* A delay time of zero just forces a reschedule. */\r
929: if( xTicksToDelay > ( TickType_t ) 0U )\r
-BFD05BB0 0028FC5E LW V0, 40(S8)
-BFD05BB4 003640E2 BEQZC V0, 0xBFD05C24
+BFD05BB0 0028FC5E LW V0, 40(S8)\r
+BFD05BB4 003640E2 BEQZC V0, 0xBFD05C24\r
930: {\r
931: configASSERT( uxSchedulerSuspended == 0 );\r
-BFD05BB8 805CFC5C LW V0, -32676(GP)
-BFD05BBC 000940E2 BEQZC V0, 0xBFD05BD2
-BFD05BC0 BFD141A2 LUI V0, 0xBFD1
-BFD05BC2 3082BFD1 LDC1 F30, 12418(S1)
-BFD05BC4 98103082 ADDIU A0, V0, -26608
-BFD05BC6 30A09810 SWC1 F0, 12448(S0)
-BFD05BC8 03A330A0 ADDIU A1, ZERO, 931
-BFD05BCC 4B7E77E8 JALS vAssertCalled
-BFD05BCE 4B7E LW K1, 120(SP)
-BFD05BD0 0C00 NOP
+BFD05BB8 805CFC5C LW V0, -32676(GP)\r
+BFD05BBC 000940E2 BEQZC V0, 0xBFD05BD2\r
+BFD05BC0 BFD141A2 LUI V0, 0xBFD1\r
+BFD05BC2 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD05BC4 98103082 ADDIU A0, V0, -26608\r
+BFD05BC6 30A09810 SWC1 F0, 12448(S0)\r
+BFD05BC8 03A330A0 ADDIU A1, ZERO, 931\r
+BFD05BCC 4B7E77E8 JALS vAssertCalled\r
+BFD05BCE 4B7E LW K1, 120(SP)\r
+BFD05BD0 0C00 NOP\r
932: vTaskSuspendAll();\r
-BFD05BD2 4EF477E8 JALS vTaskSuspendAll
-BFD05BD4 4EF4 ADDIU S7, S7, -6
-BFD05BD6 0C00 NOP
+BFD05BD2 4EF477E8 JALS vTaskSuspendAll\r
+BFD05BD4 4EF4 ADDIU S7, S7, -6\r
+BFD05BD6 0C00 NOP\r
933: {\r
934: traceTASK_DELAY();\r
935: \r
944: /* Calculate the time to wake - this may overflow but this is\r
945: not a problem. */\r
946: xTimeToWake = xTickCount + xTicksToDelay;\r
-BFD05BD8 803CFC7C LW V1, -32708(GP)
-BFD05BDC 0028FC5E LW V0, 40(S8)
-BFD05BE0 0526 ADDU V0, V1, V0
-BFD05BE2 0014F85E SW V0, 20(S8)
+BFD05BD8 803CFC7C LW V1, -32708(GP)\r
+BFD05BDC 0028FC5E LW V0, 40(S8)\r
+BFD05BE0 0526 ADDU V0, V1, V0\r
+BFD05BE2 0014F85E SW V0, 20(S8)\r
947: \r
948: /* We must remove ourselves from the ready list before adding\r
949: ourselves to the blocked list as the same list item is used for\r
950: both lists. */\r
951: if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r
-BFD05BE6 8030FC5C LW V0, -32720(GP)
-BFD05BEA 6D22 ADDIU V0, V0, 4
-BFD05BEC 0C82 MOVE A0, V0
-BFD05BEE 00C877E8 JALS uxListRemove
-BFD05BF0 0C0000C8 SLL A2, T0, 1
-BFD05BF2 0C00 NOP
-BFD05BF4 000C40A2 BNEZC V0, 0xBFD05C10
+BFD05BE6 8030FC5C LW V0, -32720(GP)\r
+BFD05BEA 6D22 ADDIU V0, V0, 4\r
+BFD05BEC 0C82 MOVE A0, V0\r
+BFD05BEE 00C877E8 JALS uxListRemove\r
+BFD05BF0 0C0000C8 SLL A2, T0, 1\r
+BFD05BF2 0C00 NOP\r
+BFD05BF4 000C40A2 BNEZC V0, 0xBFD05C10\r
952: {\r
953: /* The current task must be in a ready list, so there is\r
954: no need to check, and the port reset macro can be called\r
955: directly. */\r
956: portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );\r
-BFD05BF8 8030FC5C LW V0, -32720(GP)
-BFD05BFC 692B LW V0, 44(V0)
-BFD05BFE ED81 LI V1, 1
-BFD05C00 10100062 SLLV V0, V0, V1
-BFD05C02 441A1010 ADDI ZERO, S0, 17434
-BFD05C04 441A NOT16 V1, V0
-BFD05C06 8040FC5C LW V0, -32704(GP)
-BFD05C0A 4493 AND16 V0, V1
-BFD05C0C 8040F85C SW V0, -32704(GP)
+BFD05BF8 8030FC5C LW V0, -32720(GP)\r
+BFD05BFC 692B LW V0, 44(V0)\r
+BFD05BFE ED81 LI V1, 1\r
+BFD05C00 10100062 SLLV V0, V0, V1\r
+BFD05C02 441A1010 ADDI ZERO, S0, 17434\r
+BFD05C04 441A NOT16 V1, V0\r
+BFD05C06 8040FC5C LW V0, -32704(GP)\r
+BFD05C0A 4493 AND16 V0, V1\r
+BFD05C0C 8040F85C SW V0, -32704(GP)\r
957: }\r
958: else\r
959: {\r
960: mtCOVERAGE_TEST_MARKER();\r
961: }\r
962: prvAddCurrentTaskToDelayedList( xTimeToWake );\r
-BFD05C10 0014FC9E LW A0, 20(S8)
-BFD05C14 373477E8 JALS prvAddCurrentTaskToDelayedList
-BFD05C16 0C003734 LHU T9, 3072(S4)
-BFD05C18 0C00 NOP
+BFD05C10 0014FC9E LW A0, 20(S8)\r
+BFD05C14 373477E8 JALS prvAddCurrentTaskToDelayedList\r
+BFD05C16 0C003734 LHU T9, 3072(S4)\r
+BFD05C18 0C00 NOP\r
963: }\r
964: xAlreadyYielded = xTaskResumeAll();\r
-BFD05C1A 158E77E8 JALS xTaskResumeAll
-BFD05C1C 0C00158E LBU T4, 3072(T6)
-BFD05C1E 0C00 NOP
-BFD05C20 0010F85E SW V0, 16(S8)
+BFD05C1A 158E77E8 JALS xTaskResumeAll\r
+BFD05C1C 0C00158E LBU T4, 3072(T6)\r
+BFD05C1E 0C00 NOP\r
+BFD05C20 0010F85E SW V0, 16(S8)\r
965: }\r
966: else\r
967: {\r
971: /* Force a reschedule if xTaskResumeAll has not already done so, we may\r
972: have put ourselves to sleep. */\r
973: if( xAlreadyYielded == pdFALSE )\r
-BFD05C24 0010FC5E LW V0, 16(S8)
-BFD05C28 001040A2 BNEZC V0, 0xBFD05C4C
+BFD05C24 0010FC5E LW V0, 16(S8)\r
+BFD05C28 001040A2 BNEZC V0, 0xBFD05C4C\r
974: {\r
975: portYIELD_WITHIN_API();\r
-BFD05C2C 4E5677E8 JALS ulPortGetCP0Cause
-BFD05C2E 4E56 ADDIU S2, S2, -5
-BFD05C30 0C00 NOP
-BFD05C32 0018F85E SW V0, 24(S8)
-BFD05C36 0018FC5E LW V0, 24(S8)
-BFD05C3A 01005042 ORI V0, V0, 256
-BFD05C3E 0018F85E SW V0, 24(S8)
-BFD05C42 0018FC9E LW A0, 24(S8)
-BFD05C46 4E6677E8 JALS vPortSetCP0Cause
-BFD05C48 4E66 ADDIU S3, S3, 3
-BFD05C4A 0C00 NOP
+BFD05C2C 4E5677E8 JALS ulPortGetCP0Cause\r
+BFD05C2E 4E56 ADDIU S2, S2, -5\r
+BFD05C30 0C00 NOP\r
+BFD05C32 0018F85E SW V0, 24(S8)\r
+BFD05C36 0018FC5E LW V0, 24(S8)\r
+BFD05C3A 01005042 ORI V0, V0, 256\r
+BFD05C3E 0018F85E SW V0, 24(S8)\r
+BFD05C42 0018FC9E LW A0, 24(S8)\r
+BFD05C46 4E6677E8 JALS vPortSetCP0Cause\r
+BFD05C48 4E66 ADDIU S3, S3, 3\r
+BFD05C4A 0C00 NOP\r
976: }\r
977: else\r
978: {\r
979: mtCOVERAGE_TEST_MARKER();\r
980: }\r
981: }\r
-BFD05C4C 0FBE MOVE SP, S8
-BFD05C4E 4BE9 LW RA, 36(SP)
-BFD05C50 4BC8 LW S8, 32(SP)
-BFD05C52 4C15 ADDIU SP, SP, 40
-BFD05C54 459F JR16 RA
-BFD05C56 0C00 NOP
+BFD05C4C 0FBE MOVE SP, S8\r
+BFD05C4E 4BE9 LW RA, 36(SP)\r
+BFD05C50 4BC8 LW S8, 32(SP)\r
+BFD05C52 4C15 ADDIU SP, SP, 40\r
+BFD05C54 459F JR16 RA\r
+BFD05C56 0C00 NOP\r
982: \r
983: #endif /* INCLUDE_vTaskDelay */\r
984: /*-----------------------------------------------------------*/\r
987: \r
988: eTaskState eTaskGetState( TaskHandle_t xTask )\r
989: {\r
-BFD04494 4FED ADDIU SP, SP, -40
-BFD04496 CBE9 SW RA, 36(SP)
-BFD04498 CBC8 SW S8, 32(SP)
-BFD0449A 0FDD MOVE S8, SP
-BFD0449C 0028F89E SW A0, 40(S8)
+BFD04494 4FED ADDIU SP, SP, -40\r
+BFD04496 CBE9 SW RA, 36(SP)\r
+BFD04498 CBC8 SW S8, 32(SP)\r
+BFD0449A 0FDD MOVE S8, SP\r
+BFD0449C 0028F89E SW A0, 40(S8)\r
990: eTaskState eReturn;\r
991: List_t *pxStateList;\r
992: const TCB_t * const pxTCB = ( TCB_t * ) xTask;\r
-BFD044A0 0028FC5E LW V0, 40(S8)
-BFD044A4 0014F85E SW V0, 20(S8)
+BFD044A0 0028FC5E LW V0, 40(S8)\r
+BFD044A4 0014F85E SW V0, 20(S8)\r
993: \r
994: configASSERT( pxTCB );\r
-BFD044A8 0014FC5E LW V0, 20(S8)
-BFD044AC 000940A2 BNEZC V0, 0xBFD044C2
-BFD044B0 BFD141A2 LUI V0, 0xBFD1
-BFD044B2 3082BFD1 LDC1 F30, 12418(S1)
-BFD044B4 98103082 ADDIU A0, V0, -26608
-BFD044B6 30A09810 SWC1 F0, 12448(S0)
-BFD044B8 03E230A0 ADDIU A1, ZERO, 994
-BFD044BC 4B7E77E8 JALS vAssertCalled
-BFD044BE 4B7E LW K1, 120(SP)
-BFD044C0 0C00 NOP
+BFD044A8 0014FC5E LW V0, 20(S8)\r
+BFD044AC 000940A2 BNEZC V0, 0xBFD044C2\r
+BFD044B0 BFD141A2 LUI V0, 0xBFD1\r
+BFD044B2 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD044B4 98103082 ADDIU A0, V0, -26608\r
+BFD044B6 30A09810 SWC1 F0, 12448(S0)\r
+BFD044B8 03E230A0 ADDIU A1, ZERO, 994\r
+BFD044BC 4B7E77E8 JALS vAssertCalled\r
+BFD044BE 4B7E LW K1, 120(SP)\r
+BFD044C0 0C00 NOP\r
995: \r
996: if( pxTCB == pxCurrentTCB )\r
-BFD044C2 8030FC5C LW V0, -32720(GP)
-BFD044C6 0014FC7E LW V1, 20(S8)
-BFD044CA 0005B443 BNE V1, V0, 0xBFD044D8
-BFD044CC 0C000005 SLL ZERO, A1, 1
-BFD044CE 0C00 NOP
+BFD044C2 8030FC5C LW V0, -32720(GP)\r
+BFD044C6 0014FC7E LW V1, 20(S8)\r
+BFD044CA 0005B443 BNE V1, V0, 0xBFD044D8\r
+BFD044CC 0C000005 SLL ZERO, A1, 1\r
+BFD044CE 0C00 NOP\r
997: {\r
998: /* The task calling this function is querying its own state. */\r
999: eReturn = eRunning;\r
-BFD044D0 0010F81E SW ZERO, 16(S8)
-BFD044D4 CC48 B 0xBFD04566
-BFD044D6 0C00 NOP
+BFD044D0 0010F81E SW ZERO, 16(S8)\r
+BFD044D4 CC48 B 0xBFD04566\r
+BFD044D6 0C00 NOP\r
1000: }\r
1001: else\r
1002: {\r
1003: taskENTER_CRITICAL();\r
-BFD044D8 33B877E8 JALS vTaskEnterCritical
-BFD044DA 0C0033B8 ADDIU SP, T8, 3072
-BFD044DC 0C00 NOP
+BFD044D8 33B877E8 JALS vTaskEnterCritical\r
+BFD044DA 0C0033B8 ADDIU SP, T8, 3072\r
+BFD044DC 0C00 NOP\r
1004: {\r
1005: pxStateList = ( List_t * ) listLIST_ITEM_CONTAINER( &( pxTCB->xGenericListItem ) );\r
-BFD044DE 0014FC5E LW V0, 20(S8)
-BFD044E2 6925 LW V0, 20(V0)
-BFD044E4 0018F85E SW V0, 24(S8)
+BFD044DE 0014FC5E LW V0, 20(S8)\r
+BFD044E2 6925 LW V0, 20(V0)\r
+BFD044E4 0018F85E SW V0, 24(S8)\r
1006: }\r
1007: taskEXIT_CRITICAL();\r
-BFD044E8 40AA77E8 JALS vTaskExitCritical
-BFD044EA 0C0040AA BNEZC T2, 0xBFD05CEE
-BFD044EC 0C00 NOP
+BFD044E8 40AA77E8 JALS vTaskExitCritical\r
+BFD044EA 0C0040AA BNEZC T2, 0xBFD05CEE\r
+BFD044EC 0C00 NOP\r
1008: \r
1009: if( ( pxStateList == pxDelayedTaskList ) || ( pxStateList == pxOverflowDelayedTaskList ) )\r
-BFD044EE 8074FC5C LW V0, -32652(GP)
-BFD044F2 0018FC7E LW V1, 24(S8)
-BFD044F6 00089443 BEQ V1, V0, 0xBFD0450A
-BFD044F8 0C000008 SLL ZERO, T0, 1
-BFD044FA 0C00 NOP
-BFD044FC 8078FC5C LW V0, -32648(GP)
-BFD04500 0018FC7E LW V1, 24(S8)
-BFD04504 0006B443 BNE V1, V0, 0xBFD04514
-BFD04506 0C000006 SLL ZERO, A2, 1
-BFD04508 0C00 NOP
+BFD044EE 8074FC5C LW V0, -32652(GP)\r
+BFD044F2 0018FC7E LW V1, 24(S8)\r
+BFD044F6 00089443 BEQ V1, V0, 0xBFD0450A\r
+BFD044F8 0C000008 SLL ZERO, T0, 1\r
+BFD044FA 0C00 NOP\r
+BFD044FC 8078FC5C LW V0, -32648(GP)\r
+BFD04500 0018FC7E LW V1, 24(S8)\r
+BFD04504 0006B443 BNE V1, V0, 0xBFD04514\r
+BFD04506 0C000006 SLL ZERO, A2, 1\r
+BFD04508 0C00 NOP\r
1010: {\r
1011: /* The task being queried is referenced from one of the Blocked\r
1012: lists. */\r
1013: eReturn = eBlocked;\r
-BFD0450A ED02 LI V0, 2
-BFD0450C 0010F85E SW V0, 16(S8)
-BFD04510 CC2A B 0xBFD04566
-BFD04512 0C00 NOP
+BFD0450A ED02 LI V0, 2\r
+BFD0450C 0010F85E SW V0, 16(S8)\r
+BFD04510 CC2A B 0xBFD04566\r
+BFD04512 0C00 NOP\r
1014: }\r
1015: \r
1016: #if ( INCLUDE_vTaskSuspend == 1 )\r
1017: else if( pxStateList == &xSuspendedTaskList )\r
-BFD04514 0018FC7E LW V1, 24(S8)
-BFD04518 BFD241A2 LUI V0, 0xBFD2
-BFD0451A 3042BFD2 LDC1 F30, 12354(S2)
-BFD0451C 80E43042 ADDIU V0, V0, -32540
-BFD04520 0010B443 BNE V1, V0, 0xBFD04544
-BFD04522 0C000010 SLL ZERO, S0, 1
-BFD04524 0C00 NOP
+BFD04514 0018FC7E LW V1, 24(S8)\r
+BFD04518 BFD241A2 LUI V0, 0xBFD2\r
+BFD0451A 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD0451C 80E43042 ADDIU V0, V0, -32540\r
+BFD04520 0010B443 BNE V1, V0, 0xBFD04544\r
+BFD04522 0C000010 SLL ZERO, S0, 1\r
+BFD04524 0C00 NOP\r
1018: {\r
1019: /* The task being queried is referenced from the suspended\r
1020: list. Is it genuinely suspended or is it block\r
1021: indefinitely? */\r
1022: if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )\r
-BFD04526 0014FC5E LW V0, 20(S8)
-BFD0452A 692A LW V0, 40(V0)
-BFD0452C 000540A2 BNEZC V0, 0xBFD0453A
+BFD04526 0014FC5E LW V0, 20(S8)\r
+BFD0452A 692A LW V0, 40(V0)\r
+BFD0452C 000540A2 BNEZC V0, 0xBFD0453A\r
1023: {\r
1024: eReturn = eSuspended;\r
-BFD04530 ED03 LI V0, 3
-BFD04532 0010F85E SW V0, 16(S8)
-BFD04536 CC17 B 0xBFD04566
-BFD04538 0C00 NOP
+BFD04530 ED03 LI V0, 3\r
+BFD04532 0010F85E SW V0, 16(S8)\r
+BFD04536 CC17 B 0xBFD04566\r
+BFD04538 0C00 NOP\r
1025: }\r
1026: else\r
1027: {\r
1028: eReturn = eBlocked;\r
-BFD0453A ED02 LI V0, 2
-BFD0453C 0010F85E SW V0, 16(S8)
-BFD04540 CC12 B 0xBFD04566
-BFD04542 0C00 NOP
+BFD0453A ED02 LI V0, 2\r
+BFD0453C 0010F85E SW V0, 16(S8)\r
+BFD04540 CC12 B 0xBFD04566\r
+BFD04542 0C00 NOP\r
1029: }\r
1030: }\r
1031: #endif\r
1032: \r
1033: #if ( INCLUDE_vTaskDelete == 1 )\r
1034: else if( pxStateList == &xTasksWaitingTermination )\r
-BFD04544 0018FC7E LW V1, 24(S8)
-BFD04548 BFD241A2 LUI V0, 0xBFD2
-BFD0454A 3042BFD2 LDC1 F30, 12354(S2)
-BFD0454C 810C3042 ADDIU V0, V0, -32500
-BFD04550 0006B443 BNE V1, V0, 0xBFD04560
-BFD04552 0C000006 SLL ZERO, A2, 1
-BFD04554 0C00 NOP
+BFD04544 0018FC7E LW V1, 24(S8)\r
+BFD04548 BFD241A2 LUI V0, 0xBFD2\r
+BFD0454A 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD0454C 810C3042 ADDIU V0, V0, -32500\r
+BFD04550 0006B443 BNE V1, V0, 0xBFD04560\r
+BFD04552 0C000006 SLL ZERO, A2, 1\r
+BFD04554 0C00 NOP\r
1035: {\r
1036: /* The task being queried is referenced from the deleted\r
1037: tasks list. */\r
1038: eReturn = eDeleted;\r
-BFD04556 ED04 LI V0, 4
-BFD04558 0010F85E SW V0, 16(S8)
-BFD0455C CC04 B 0xBFD04566
-BFD0455E 0C00 NOP
+BFD04556 ED04 LI V0, 4\r
+BFD04558 0010F85E SW V0, 16(S8)\r
+BFD0455C CC04 B 0xBFD04566\r
+BFD0455E 0C00 NOP\r
1039: }\r
1040: #endif\r
1041: \r
1044: /* If the task is not in any other state, it must be in the\r
1045: Ready (including pending ready) state. */\r
1046: eReturn = eReady;\r
-BFD04560 ED01 LI V0, 1
-BFD04562 0010F85E SW V0, 16(S8)
+BFD04560 ED01 LI V0, 1\r
+BFD04562 0010F85E SW V0, 16(S8)\r
1047: }\r
1048: }\r
1049: \r
1050: return eReturn;\r
-BFD04566 0010FC5E LW V0, 16(S8)
+BFD04566 0010FC5E LW V0, 16(S8)\r
1051: } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */\r
-BFD0456A 0FBE MOVE SP, S8
-BFD0456C 4BE9 LW RA, 36(SP)
-BFD0456E 4BC8 LW S8, 32(SP)
-BFD04570 4C15 ADDIU SP, SP, 40
-BFD04572 459F JR16 RA
-BFD04574 0C00 NOP
+BFD0456A 0FBE MOVE SP, S8\r
+BFD0456C 4BE9 LW RA, 36(SP)\r
+BFD0456E 4BC8 LW S8, 32(SP)\r
+BFD04570 4C15 ADDIU SP, SP, 40\r
+BFD04572 459F JR16 RA\r
+BFD04574 0C00 NOP\r
1052: \r
1053: #endif /* INCLUDE_eTaskGetState */\r
1054: /*-----------------------------------------------------------*/\r
1057: \r
1058: UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask )\r
1059: {\r
-BFD08B78 4FF1 ADDIU SP, SP, -32
-BFD08B7A CBE7 SW RA, 28(SP)
-BFD08B7C CBC6 SW S8, 24(SP)
-BFD08B7E 0FDD MOVE S8, SP
-BFD08B80 0020F89E SW A0, 32(S8)
+BFD08B78 4FF1 ADDIU SP, SP, -32\r
+BFD08B7A CBE7 SW RA, 28(SP)\r
+BFD08B7C CBC6 SW S8, 24(SP)\r
+BFD08B7E 0FDD MOVE S8, SP\r
+BFD08B80 0020F89E SW A0, 32(S8)\r
1060: TCB_t *pxTCB;\r
1061: UBaseType_t uxReturn;\r
1062: \r
1063: taskENTER_CRITICAL();\r
-BFD08B84 33B877E8 JALS vTaskEnterCritical
-BFD08B86 0C0033B8 ADDIU SP, T8, 3072
-BFD08B88 0C00 NOP
+BFD08B84 33B877E8 JALS vTaskEnterCritical\r
+BFD08B86 0C0033B8 ADDIU SP, T8, 3072\r
+BFD08B88 0C00 NOP\r
1064: {\r
1065: /* If null is passed in here then we are changing the\r
1066: priority of the calling function. */\r
1067: pxTCB = prvGetTCBFromHandle( xTask );\r
-BFD08B8A 0020FC5E LW V0, 32(S8)
-BFD08B8E 000440A2 BNEZC V0, 0xBFD08B9A
-BFD08B92 8030FC5C LW V0, -32720(GP)
-BFD08B96 CC03 B 0xBFD08B9E
-BFD08B98 0C00 NOP
-BFD08B9A 0020FC5E LW V0, 32(S8)
-BFD08B9E 0010F85E SW V0, 16(S8)
+BFD08B8A 0020FC5E LW V0, 32(S8)\r
+BFD08B8E 000440A2 BNEZC V0, 0xBFD08B9A\r
+BFD08B92 8030FC5C LW V0, -32720(GP)\r
+BFD08B96 CC03 B 0xBFD08B9E\r
+BFD08B98 0C00 NOP\r
+BFD08B9A 0020FC5E LW V0, 32(S8)\r
+BFD08B9E 0010F85E SW V0, 16(S8)\r
1068: uxReturn = pxTCB->uxPriority;\r
-BFD08BA2 0010FC5E LW V0, 16(S8)
-BFD08BA6 692B LW V0, 44(V0)
-BFD08BA8 0014F85E SW V0, 20(S8)
+BFD08BA2 0010FC5E LW V0, 16(S8)\r
+BFD08BA6 692B LW V0, 44(V0)\r
+BFD08BA8 0014F85E SW V0, 20(S8)\r
1069: }\r
1070: taskEXIT_CRITICAL();\r
-BFD08BAC 40AA77E8 JALS vTaskExitCritical
-BFD08BAE 0C0040AA BNEZC T2, 0xBFD0A3B2
-BFD08BB0 0C00 NOP
+BFD08BAC 40AA77E8 JALS vTaskExitCritical\r
+BFD08BAE 0C0040AA BNEZC T2, 0xBFD0A3B2\r
+BFD08BB0 0C00 NOP\r
1071: \r
1072: return uxReturn;\r
-BFD08BB2 0014FC5E LW V0, 20(S8)
+BFD08BB2 0014FC5E LW V0, 20(S8)\r
1073: }\r
-BFD08BB6 0FBE MOVE SP, S8
-BFD08BB8 4BE7 LW RA, 28(SP)
-BFD08BBA 4BC6 LW S8, 24(SP)
-BFD08BBC 4C11 ADDIU SP, SP, 32
-BFD08BBE 459F JR16 RA
-BFD08BC0 0C00 NOP
+BFD08BB6 0FBE MOVE SP, S8\r
+BFD08BB8 4BE7 LW RA, 28(SP)\r
+BFD08BBA 4BC6 LW S8, 24(SP)\r
+BFD08BBC 4C11 ADDIU SP, SP, 32\r
+BFD08BBE 459F JR16 RA\r
+BFD08BC0 0C00 NOP\r
1074: \r
1075: #endif /* INCLUDE_uxTaskPriorityGet */\r
1076: /*-----------------------------------------------------------*/\r
1079: \r
1080: UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask )\r
1081: {\r
-BFD08708 4FED ADDIU SP, SP, -40
-BFD0870A CBE9 SW RA, 36(SP)
-BFD0870C CBC8 SW S8, 32(SP)
-BFD0870E 0FDD MOVE S8, SP
-BFD08710 0028F89E SW A0, 40(S8)
+BFD08708 4FED ADDIU SP, SP, -40\r
+BFD0870A CBE9 SW RA, 36(SP)\r
+BFD0870C CBC8 SW S8, 32(SP)\r
+BFD0870E 0FDD MOVE S8, SP\r
+BFD08710 0028F89E SW A0, 40(S8)\r
1082: TCB_t *pxTCB;\r
1083: UBaseType_t uxReturn, uxSavedInterruptState;\r
1084: \r
1101: portASSERT_IF_INTERRUPT_PRIORITY_INVALID();\r
1102: \r
1103: uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR();\r
-BFD08714 475E77E8 JALS uxPortSetInterruptMaskFromISR
-BFD08718 0C00 NOP
-BFD0871A 0010F85E SW V0, 16(S8)
+BFD08714 475E77E8 JALS uxPortSetInterruptMaskFromISR\r
+BFD08718 0C00 NOP\r
+BFD0871A 0010F85E SW V0, 16(S8)\r
1104: {\r
1105: /* If null is passed in here then it is the priority of the calling\r
1106: task that is being queried. */\r
1107: pxTCB = prvGetTCBFromHandle( xTask );\r
-BFD0871E 0028FC5E LW V0, 40(S8)
-BFD08722 000440A2 BNEZC V0, 0xBFD0872E
-BFD08726 8030FC5C LW V0, -32720(GP)
-BFD0872A CC03 B 0xBFD08732
-BFD0872C 0C00 NOP
-BFD0872E 0028FC5E LW V0, 40(S8)
-BFD08732 0014F85E SW V0, 20(S8)
+BFD0871E 0028FC5E LW V0, 40(S8)\r
+BFD08722 000440A2 BNEZC V0, 0xBFD0872E\r
+BFD08726 8030FC5C LW V0, -32720(GP)\r
+BFD0872A CC03 B 0xBFD08732\r
+BFD0872C 0C00 NOP\r
+BFD0872E 0028FC5E LW V0, 40(S8)\r
+BFD08732 0014F85E SW V0, 20(S8)\r
1108: uxReturn = pxTCB->uxPriority;\r
-BFD08736 0014FC5E LW V0, 20(S8)
-BFD0873A 692B LW V0, 44(V0)
-BFD0873C 0018F85E SW V0, 24(S8)
+BFD08736 0014FC5E LW V0, 20(S8)\r
+BFD0873A 692B LW V0, 44(V0)\r
+BFD0873C 0018F85E SW V0, 24(S8)\r
1109: }\r
1110: portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState );\r
-BFD08740 0010FC9E LW A0, 16(S8)
-BFD08744 4D5E77E8 JALS vPortClearInterruptMaskFromISR
-BFD08746 4D5E ADDIU T2, T2, -1
-BFD08748 0C00 NOP
+BFD08740 0010FC9E LW A0, 16(S8)\r
+BFD08744 4D5E77E8 JALS vPortClearInterruptMaskFromISR\r
+BFD08746 4D5E ADDIU T2, T2, -1\r
+BFD08748 0C00 NOP\r
1111: \r
1112: return uxReturn;\r
-BFD0874A 0018FC5E LW V0, 24(S8)
+BFD0874A 0018FC5E LW V0, 24(S8)\r
1113: }\r
-BFD0874E 0FBE MOVE SP, S8
-BFD08750 4BE9 LW RA, 36(SP)
-BFD08752 4BC8 LW S8, 32(SP)
-BFD08754 4C15 ADDIU SP, SP, 40
-BFD08756 459F JR16 RA
-BFD08758 0C00 NOP
+BFD0874E 0FBE MOVE SP, S8\r
+BFD08750 4BE9 LW RA, 36(SP)\r
+BFD08752 4BC8 LW S8, 32(SP)\r
+BFD08754 4C15 ADDIU SP, SP, 40\r
+BFD08756 459F JR16 RA\r
+BFD08758 0C00 NOP\r
1114: \r
1115: #endif /* INCLUDE_uxTaskPriorityGet */\r
1116: /*-----------------------------------------------------------*/\r
1119: \r
1120: void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority )\r
1121: {\r
-BFD01924 4FE9 ADDIU SP, SP, -48
-BFD01926 CBEB SW RA, 44(SP)
-BFD01928 CBCA SW S8, 40(SP)
-BFD0192A 0FDD MOVE S8, SP
-BFD0192C 0030F89E SW A0, 48(S8)
-BFD01930 0034F8BE SW A1, 52(S8)
+BFD01924 4FE9 ADDIU SP, SP, -48\r
+BFD01926 CBEB SW RA, 44(SP)\r
+BFD01928 CBCA SW S8, 40(SP)\r
+BFD0192A 0FDD MOVE S8, SP\r
+BFD0192C 0030F89E SW A0, 48(S8)\r
+BFD01930 0034F8BE SW A1, 52(S8)\r
1122: TCB_t *pxTCB;\r
1123: UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;\r
1124: BaseType_t xYieldRequired = pdFALSE;\r
-BFD01934 0010F81E SW ZERO, 16(S8)
+BFD01934 0010F81E SW ZERO, 16(S8)\r
1125: \r
1126: configASSERT( ( uxNewPriority < configMAX_PRIORITIES ) );\r
-BFD01938 0034FC5E LW V0, 52(S8)
-BFD0193C 0005B042 SLTIU V0, V0, 5
-BFD01940 000940A2 BNEZC V0, 0xBFD01956
-BFD01944 BFD141A2 LUI V0, 0xBFD1
-BFD01946 3082BFD1 LDC1 F30, 12418(S1)
-BFD01948 98103082 ADDIU A0, V0, -26608
-BFD0194A 30A09810 SWC1 F0, 12448(S0)
-BFD0194C 046630A0 ADDIU A1, ZERO, 1126
-BFD0194E 0466 ADDU S0, V1, A2
-BFD01950 4B7E77E8 JALS vAssertCalled
-BFD01952 4B7E LW K1, 120(SP)
-BFD01954 0C00 NOP
+BFD01938 0034FC5E LW V0, 52(S8)\r
+BFD0193C 0005B042 SLTIU V0, V0, 5\r
+BFD01940 000940A2 BNEZC V0, 0xBFD01956\r
+BFD01944 BFD141A2 LUI V0, 0xBFD1\r
+BFD01946 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD01948 98103082 ADDIU A0, V0, -26608\r
+BFD0194A 30A09810 SWC1 F0, 12448(S0)\r
+BFD0194C 046630A0 ADDIU A1, ZERO, 1126\r
+BFD0194E 0466 ADDU S0, V1, A2\r
+BFD01950 4B7E77E8 JALS vAssertCalled\r
+BFD01952 4B7E LW K1, 120(SP)\r
+BFD01954 0C00 NOP\r
1127: \r
1128: /* Ensure the new priority is valid. */\r
1129: if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES )\r
-BFD01956 0034FC5E LW V0, 52(S8)
-BFD0195A 0005B042 SLTIU V0, V0, 5
-BFD0195E 000340A2 BNEZC V0, 0xBFD01968
+BFD01956 0034FC5E LW V0, 52(S8)\r
+BFD0195A 0005B042 SLTIU V0, V0, 5\r
+BFD0195E 000340A2 BNEZC V0, 0xBFD01968\r
1130: {\r
1131: uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;\r
-BFD01962 ED04 LI V0, 4
-BFD01964 0034F85E SW V0, 52(S8)
+BFD01962 ED04 LI V0, 4\r
+BFD01964 0034F85E SW V0, 52(S8)\r
1132: }\r
1133: else\r
1134: {\r
1136: }\r
1137: \r
1138: taskENTER_CRITICAL();\r
-BFD01968 33B877E8 JALS vTaskEnterCritical
-BFD0196A 0C0033B8 ADDIU SP, T8, 3072
-BFD0196C 0C00 NOP
+BFD01968 33B877E8 JALS vTaskEnterCritical\r
+BFD0196A 0C0033B8 ADDIU SP, T8, 3072\r
+BFD0196C 0C00 NOP\r
1139: {\r
1140: /* If null is passed in here then it is the priority of the calling\r
1141: task that is being changed. */\r
1142: pxTCB = prvGetTCBFromHandle( xTask );\r
-BFD0196E 0030FC5E LW V0, 48(S8)
-BFD01972 000440A2 BNEZC V0, 0xBFD0197E
-BFD01976 8030FC5C LW V0, -32720(GP)
-BFD0197A CC03 B 0xBFD01982
-BFD0197C 0C00 NOP
-BFD0197E 0030FC5E LW V0, 48(S8)
-BFD01982 0014F85E SW V0, 20(S8)
+BFD0196E 0030FC5E LW V0, 48(S8)\r
+BFD01972 000440A2 BNEZC V0, 0xBFD0197E\r
+BFD01976 8030FC5C LW V0, -32720(GP)\r
+BFD0197A CC03 B 0xBFD01982\r
+BFD0197C 0C00 NOP\r
+BFD0197E 0030FC5E LW V0, 48(S8)\r
+BFD01982 0014F85E SW V0, 20(S8)\r
1143: \r
1144: traceTASK_PRIORITY_SET( pxTCB, uxNewPriority );\r
1145: \r
1146: #if ( configUSE_MUTEXES == 1 )\r
1147: {\r
1148: uxCurrentBasePriority = pxTCB->uxBasePriority;\r
-BFD01986 0014FC5E LW V0, 20(S8)
-BFD0198A 0040FC42 LW V0, 64(V0)
-BFD0198E 0018F85E SW V0, 24(S8)
+BFD01986 0014FC5E LW V0, 20(S8)\r
+BFD0198A 0040FC42 LW V0, 64(V0)\r
+BFD0198E 0018F85E SW V0, 24(S8)\r
1149: }\r
1150: #else\r
1151: {\r
1154: #endif\r
1155: \r
1156: if( uxCurrentBasePriority != uxNewPriority )\r
-BFD01992 0018FC7E LW V1, 24(S8)
-BFD01996 0034FC5E LW V0, 52(S8)
-BFD0199A 00AD9443 BEQ V1, V0, 0xBFD01AF8
-BFD0199C 0C0000AD SLL A1, T5, 1
-BFD0199E 0C00 NOP
+BFD01992 0018FC7E LW V1, 24(S8)\r
+BFD01996 0034FC5E LW V0, 52(S8)\r
+BFD0199A 00AD9443 BEQ V1, V0, 0xBFD01AF8\r
+BFD0199C 0C0000AD SLL A1, T5, 1\r
+BFD0199E 0C00 NOP\r
1157: {\r
1158: /* The priority change may have readied a task of higher\r
1159: priority than the calling task. */\r
1160: if( uxNewPriority > uxCurrentBasePriority )\r
-BFD019A0 0034FC7E LW V1, 52(S8)
-BFD019A4 0018FC5E LW V0, 24(S8)
-BFD019A8 13900062 SLTU V0, V0, V1
-BFD019AA 40E21390 ADDI GP, S0, 16610
-BFD019AC 001540E2 BEQZC V0, 0xBFD019DA
+BFD019A0 0034FC7E LW V1, 52(S8)\r
+BFD019A4 0018FC5E LW V0, 24(S8)\r
+BFD019A8 13900062 SLTU V0, V0, V1\r
+BFD019AA 40E21390 ADDI GP, S0, 16610\r
+BFD019AC 001540E2 BEQZC V0, 0xBFD019DA\r
1161: {\r
1162: if( pxTCB != pxCurrentTCB )\r
-BFD019B0 8030FC5C LW V0, -32720(GP)
-BFD019B4 0014FC7E LW V1, 20(S8)
-BFD019B8 00199443 BEQ V1, V0, 0xBFD019EE
-BFD019BA 0C000019 SLL ZERO, T9, 1
-BFD019BC 0C00 NOP
+BFD019B0 8030FC5C LW V0, -32720(GP)\r
+BFD019B4 0014FC7E LW V1, 20(S8)\r
+BFD019B8 00199443 BEQ V1, V0, 0xBFD019EE\r
+BFD019BA 0C000019 SLL ZERO, T9, 1\r
+BFD019BC 0C00 NOP\r
1163: {\r
1164: /* The priority of a task other than the currently\r
1165: running task is being raised. Is the priority being\r
1166: raised above that of the running task? */\r
1167: if( uxNewPriority >= pxCurrentTCB->uxPriority )\r
-BFD019BE 8030FC5C LW V0, -32720(GP)
-BFD019C2 69AB LW V1, 44(V0)
-BFD019C4 0034FC5E LW V0, 52(S8)
-BFD019C8 13900062 SLTU V0, V0, V1
-BFD019CA 40A21390 ADDI GP, S0, 16546
-BFD019CC 000F40A2 BNEZC V0, 0xBFD019EE
+BFD019BE 8030FC5C LW V0, -32720(GP)\r
+BFD019C2 69AB LW V1, 44(V0)\r
+BFD019C4 0034FC5E LW V0, 52(S8)\r
+BFD019C8 13900062 SLTU V0, V0, V1\r
+BFD019CA 40A21390 ADDI GP, S0, 16546\r
+BFD019CC 000F40A2 BNEZC V0, 0xBFD019EE\r
1168: {\r
1169: xYieldRequired = pdTRUE;\r
-BFD019D0 ED01 LI V0, 1
-BFD019D2 0010F85E SW V0, 16(S8)
-BFD019D6 CC0B B 0xBFD019EE
-BFD019D8 0C00 NOP
+BFD019D0 ED01 LI V0, 1\r
+BFD019D2 0010F85E SW V0, 16(S8)\r
+BFD019D6 CC0B B 0xBFD019EE\r
+BFD019D8 0C00 NOP\r
1170: }\r
1171: else\r
1172: {\r
1181: }\r
1182: }\r
1183: else if( pxTCB == pxCurrentTCB )\r
-BFD019DA 8030FC5C LW V0, -32720(GP)
-BFD019DE 0014FC7E LW V1, 20(S8)
-BFD019E2 0004B443 BNE V1, V0, 0xBFD019EE
-BFD019E4 0C000004 SLL ZERO, A0, 1
-BFD019E6 0C00 NOP
+BFD019DA 8030FC5C LW V0, -32720(GP)\r
+BFD019DE 0014FC7E LW V1, 20(S8)\r
+BFD019E2 0004B443 BNE V1, V0, 0xBFD019EE\r
+BFD019E4 0C000004 SLL ZERO, A0, 1\r
+BFD019E6 0C00 NOP\r
1184: {\r
1185: /* Setting the priority of the running task down means\r
1186: there may now be another task of higher priority that\r
1187: is ready to execute. */\r
1188: xYieldRequired = pdTRUE;\r
-BFD019E8 ED01 LI V0, 1
-BFD019EA 0010F85E SW V0, 16(S8)
+BFD019E8 ED01 LI V0, 1\r
+BFD019EA 0010F85E SW V0, 16(S8)\r
1189: }\r
1190: else\r
1191: {\r
1198: before its uxPriority member is changed so the\r
1199: taskRESET_READY_PRIORITY() macro can function correctly. */\r
1200: uxPriorityUsedOnEntry = pxTCB->uxPriority;\r
-BFD019EE 0014FC5E LW V0, 20(S8)
-BFD019F2 692B LW V0, 44(V0)
-BFD019F4 001CF85E SW V0, 28(S8)
+BFD019EE 0014FC5E LW V0, 20(S8)\r
+BFD019F2 692B LW V0, 44(V0)\r
+BFD019F4 001CF85E SW V0, 28(S8)\r
1201: \r
1202: #if ( configUSE_MUTEXES == 1 )\r
1203: {\r
1204: /* Only change the priority being used if the task is not\r
1205: currently using an inherited priority. */\r
1206: if( pxTCB->uxBasePriority == pxTCB->uxPriority )\r
-BFD019F8 0014FC5E LW V0, 20(S8)
-BFD019FC 0040FC62 LW V1, 64(V0)
-BFD01A00 0014FC5E LW V0, 20(S8)
-BFD01A04 692B LW V0, 44(V0)
-BFD01A06 0006B443 BNE V1, V0, 0xBFD01A16
-BFD01A08 0C000006 SLL ZERO, A2, 1
-BFD01A0A 0C00 NOP
+BFD019F8 0014FC5E LW V0, 20(S8)\r
+BFD019FC 0040FC62 LW V1, 64(V0)\r
+BFD01A00 0014FC5E LW V0, 20(S8)\r
+BFD01A04 692B LW V0, 44(V0)\r
+BFD01A06 0006B443 BNE V1, V0, 0xBFD01A16\r
+BFD01A08 0C000006 SLL ZERO, A2, 1\r
+BFD01A0A 0C00 NOP\r
1207: {\r
1208: pxTCB->uxPriority = uxNewPriority;\r
-BFD01A0C 0014FC5E LW V0, 20(S8)
-BFD01A10 0034FC7E LW V1, 52(S8)
-BFD01A14 E9AB SW V1, 44(V0)
+BFD01A0C 0014FC5E LW V0, 20(S8)\r
+BFD01A10 0034FC7E LW V1, 52(S8)\r
+BFD01A14 E9AB SW V1, 44(V0)\r
1209: }\r
1210: else\r
1211: {\r
1214: \r
1215: /* The base priority gets set whatever. */\r
1216: pxTCB->uxBasePriority = uxNewPriority;\r
-BFD01A16 0014FC5E LW V0, 20(S8)
-BFD01A1A 0034FC7E LW V1, 52(S8)
-BFD01A1E 0040F862 SW V1, 64(V0)
+BFD01A16 0014FC5E LW V0, 20(S8)\r
+BFD01A1A 0034FC7E LW V1, 52(S8)\r
+BFD01A1E 0040F862 SW V1, 64(V0)\r
1217: }\r
1218: #else\r
1219: {\r
1224: /* Only reset the event list item value if the value is not\r
1225: being used for anything else. */\r
1226: if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )\r
-BFD01A22 0014FC5E LW V0, 20(S8)
-BFD01A26 6926 LW V0, 24(V0)
-BFD01A28 00084002 BLTZ V0, 0xBFD01A3C
-BFD01A2A 0C000008 SLL ZERO, T0, 1
-BFD01A2C 0C00 NOP
+BFD01A22 0014FC5E LW V0, 20(S8)\r
+BFD01A26 6926 LW V0, 24(V0)\r
+BFD01A28 00084002 BLTZ V0, 0xBFD01A3C\r
+BFD01A2A 0C000008 SLL ZERO, T0, 1\r
+BFD01A2C 0C00 NOP\r
1227: {\r
1228: listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\r
-BFD01A2E ED85 LI V1, 5
-BFD01A30 0034FC5E LW V0, 52(S8)
-BFD01A34 05A7 SUBU V1, V1, V0
-BFD01A36 0014FC5E LW V0, 20(S8)
-BFD01A3A E9A6 SW V1, 24(V0)
+BFD01A2E ED85 LI V1, 5\r
+BFD01A30 0034FC5E LW V0, 52(S8)\r
+BFD01A34 05A7 SUBU V1, V1, V0\r
+BFD01A36 0014FC5E LW V0, 20(S8)\r
+BFD01A3A E9A6 SW V1, 24(V0)\r
1229: }\r
1230: else\r
1231: {\r
1237: the task is in a ready list it needs to be removed and placed\r
1238: in the list appropriate to its new priority. */\r
1239: if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xGenericListItem ) ) != pdFALSE )\r
-BFD01A3C 0014FC5E LW V0, 20(S8)
-BFD01A3E 69A50014 LWX T5, 0(S4)
-BFD01A40 69A5 LW V1, 20(V0)
-BFD01A42 001CFC5E LW V0, 28(S8)
-BFD01A46 2524 SLL V0, V0, 2
-BFD01A48 2624 SLL A0, V0, 2
-BFD01A4A 0644 ADDU A0, V0, A0
-BFD01A4C BFD241A2 LUI V0, 0xBFD2
-BFD01A4E 3042BFD2 LDC1 F30, 12354(S2)
-BFD01A50 806C3042 ADDIU V0, V0, -32660
-BFD01A54 0528 ADDU V0, A0, V0
-BFD01A56 0004B443 BNE V1, V0, 0xBFD01A62
-BFD01A58 0C000004 SLL ZERO, A0, 1
-BFD01A5A 0C00 NOP
-BFD01A5C ED01 LI V0, 1
-BFD01A5E CC02 B 0xBFD01A64
-BFD01A60 0C00 NOP
-BFD01A62 0C40 MOVE V0, ZERO
-BFD01A64 003240E2 BEQZC V0, 0xBFD01ACC
+BFD01A3C 0014FC5E LW V0, 20(S8)\r
+BFD01A3E 69A50014 LWX T5, 0(S4)\r
+BFD01A40 69A5 LW V1, 20(V0)\r
+BFD01A42 001CFC5E LW V0, 28(S8)\r
+BFD01A46 2524 SLL V0, V0, 2\r
+BFD01A48 2624 SLL A0, V0, 2\r
+BFD01A4A 0644 ADDU A0, V0, A0\r
+BFD01A4C BFD241A2 LUI V0, 0xBFD2\r
+BFD01A4E 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD01A50 806C3042 ADDIU V0, V0, -32660\r
+BFD01A54 0528 ADDU V0, A0, V0\r
+BFD01A56 0004B443 BNE V1, V0, 0xBFD01A62\r
+BFD01A58 0C000004 SLL ZERO, A0, 1\r
+BFD01A5A 0C00 NOP\r
+BFD01A5C ED01 LI V0, 1\r
+BFD01A5E CC02 B 0xBFD01A64\r
+BFD01A60 0C00 NOP\r
+BFD01A62 0C40 MOVE V0, ZERO\r
+BFD01A64 003240E2 BEQZC V0, 0xBFD01ACC\r
1240: {\r
1241: /* The task is currently in its ready list - remove before adding\r
1242: it to it's new ready list. As we are in a critical section we\r
1243: can do this even if the scheduler is suspended. */\r
1244: if( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r
-BFD01A68 0014FC5E LW V0, 20(S8)
-BFD01A6C 6D22 ADDIU V0, V0, 4
-BFD01A6E 0C82 MOVE A0, V0
-BFD01A70 00C877E8 JALS uxListRemove
-BFD01A72 0C0000C8 SLL A2, T0, 1
-BFD01A74 0C00 NOP
-BFD01A76 000B40A2 BNEZC V0, 0xBFD01A90
+BFD01A68 0014FC5E LW V0, 20(S8)\r
+BFD01A6C 6D22 ADDIU V0, V0, 4\r
+BFD01A6E 0C82 MOVE A0, V0\r
+BFD01A70 00C877E8 JALS uxListRemove\r
+BFD01A72 0C0000C8 SLL A2, T0, 1\r
+BFD01A74 0C00 NOP\r
+BFD01A76 000B40A2 BNEZC V0, 0xBFD01A90\r
1245: {\r
1246: /* It is known that the task is in its ready list so\r
1247: there is no need to check again and the port level\r
1248: reset macro can be called directly. */\r
1249: portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority );\r
-BFD01A7A 001CFC5E LW V0, 28(S8)
-BFD01A7E ED81 LI V1, 1
-BFD01A80 10100062 SLLV V0, V0, V1
-BFD01A82 441A1010 ADDI ZERO, S0, 17434
-BFD01A84 441A NOT16 V1, V0
-BFD01A86 8040FC5C LW V0, -32704(GP)
-BFD01A8A 4493 AND16 V0, V1
-BFD01A8C 8040F85C SW V0, -32704(GP)
+BFD01A7A 001CFC5E LW V0, 28(S8)\r
+BFD01A7E ED81 LI V1, 1\r
+BFD01A80 10100062 SLLV V0, V0, V1\r
+BFD01A82 441A1010 ADDI ZERO, S0, 17434\r
+BFD01A84 441A NOT16 V1, V0\r
+BFD01A86 8040FC5C LW V0, -32704(GP)\r
+BFD01A8A 4493 AND16 V0, V1\r
+BFD01A8C 8040F85C SW V0, -32704(GP)\r
1250: }\r
1251: else\r
1252: {\r
1253: mtCOVERAGE_TEST_MARKER();\r
1254: }\r
1255: prvAddTaskToReadyList( pxTCB );\r
-BFD01A90 0014FC5E LW V0, 20(S8)
-BFD01A94 692B LW V0, 44(V0)
-BFD01A96 ED81 LI V1, 1
-BFD01A98 18100062 SLLV V1, V0, V1
-BFD01A9A FC5C1810 SB ZERO, -932(S0)
-BFD01A9C 8040FC5C LW V0, -32704(GP)
-BFD01AA0 44D3 OR16 V0, V1
-BFD01AA2 8040F85C SW V0, -32704(GP)
-BFD01AA6 0014FC5E LW V0, 20(S8)
-BFD01AAA 692B LW V0, 44(V0)
-BFD01AAC 2524 SLL V0, V0, 2
-BFD01AAE 25A4 SLL V1, V0, 2
-BFD01AB0 05B4 ADDU V1, V0, V1
-BFD01AB2 BFD241A2 LUI V0, 0xBFD2
-BFD01AB4 3042BFD2 LDC1 F30, 12354(S2)
-BFD01AB6 806C3042 ADDIU V0, V0, -32660
-BFD01ABA 05A6 ADDU V1, V1, V0
-BFD01ABC 0014FC5E LW V0, 20(S8)
-BFD01AC0 6D22 ADDIU V0, V0, 4
-BFD01AC2 0C83 MOVE A0, V1
-BFD01AC4 0CA2 MOVE A1, V0
-BFD01AC6 3E4A77E8 JALS vListInsertEnd
-BFD01AC8 0C003E4A LH S2, 3072(T2)
-BFD01ACA 0C00 NOP
+BFD01A90 0014FC5E LW V0, 20(S8)\r
+BFD01A94 692B LW V0, 44(V0)\r
+BFD01A96 ED81 LI V1, 1\r
+BFD01A98 18100062 SLLV V1, V0, V1\r
+BFD01A9A FC5C1810 SB ZERO, -932(S0)\r
+BFD01A9C 8040FC5C LW V0, -32704(GP)\r
+BFD01AA0 44D3 OR16 V0, V1\r
+BFD01AA2 8040F85C SW V0, -32704(GP)\r
+BFD01AA6 0014FC5E LW V0, 20(S8)\r
+BFD01AAA 692B LW V0, 44(V0)\r
+BFD01AAC 2524 SLL V0, V0, 2\r
+BFD01AAE 25A4 SLL V1, V0, 2\r
+BFD01AB0 05B4 ADDU V1, V0, V1\r
+BFD01AB2 BFD241A2 LUI V0, 0xBFD2\r
+BFD01AB4 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD01AB6 806C3042 ADDIU V0, V0, -32660\r
+BFD01ABA 05A6 ADDU V1, V1, V0\r
+BFD01ABC 0014FC5E LW V0, 20(S8)\r
+BFD01AC0 6D22 ADDIU V0, V0, 4\r
+BFD01AC2 0C83 MOVE A0, V1\r
+BFD01AC4 0CA2 MOVE A1, V0\r
+BFD01AC6 3E4A77E8 JALS vListInsertEnd\r
+BFD01AC8 0C003E4A LH S2, 3072(T2)\r
+BFD01ACA 0C00 NOP\r
1256: }\r
1257: else\r
1258: {\r
1260: }\r
1261: \r
1262: if( xYieldRequired == pdTRUE )\r
-BFD01ACC 0010FC7E LW V1, 16(S8)
-BFD01AD0 ED01 LI V0, 1
-BFD01AD2 0011B443 BNE V1, V0, 0xBFD01AF8
-BFD01AD4 0C000011 SLL ZERO, S1, 1
-BFD01AD6 0C00 NOP
+BFD01ACC 0010FC7E LW V1, 16(S8)\r
+BFD01AD0 ED01 LI V0, 1\r
+BFD01AD2 0011B443 BNE V1, V0, 0xBFD01AF8\r
+BFD01AD4 0C000011 SLL ZERO, S1, 1\r
+BFD01AD6 0C00 NOP\r
1263: {\r
1264: taskYIELD_IF_USING_PREEMPTION();\r
-BFD01AD8 4E5677E8 JALS ulPortGetCP0Cause
-BFD01ADA 4E56 ADDIU S2, S2, -5
-BFD01ADC 0C00 NOP
-BFD01ADE 0020F85E SW V0, 32(S8)
-BFD01AE2 0020FC5E LW V0, 32(S8)
-BFD01AE6 01005042 ORI V0, V0, 256
-BFD01AEA 0020F85E SW V0, 32(S8)
-BFD01AEE 0020FC9E LW A0, 32(S8)
-BFD01AF2 4E6677E8 JALS vPortSetCP0Cause
-BFD01AF4 4E66 ADDIU S3, S3, 3
-BFD01AF6 0C00 NOP
+BFD01AD8 4E5677E8 JALS ulPortGetCP0Cause\r
+BFD01ADA 4E56 ADDIU S2, S2, -5\r
+BFD01ADC 0C00 NOP\r
+BFD01ADE 0020F85E SW V0, 32(S8)\r
+BFD01AE2 0020FC5E LW V0, 32(S8)\r
+BFD01AE6 01005042 ORI V0, V0, 256\r
+BFD01AEA 0020F85E SW V0, 32(S8)\r
+BFD01AEE 0020FC9E LW A0, 32(S8)\r
+BFD01AF2 4E6677E8 JALS vPortSetCP0Cause\r
+BFD01AF4 4E66 ADDIU S3, S3, 3\r
+BFD01AF6 0C00 NOP\r
1265: }\r
1266: else\r
1267: {\r
1274: }\r
1275: }\r
1276: taskEXIT_CRITICAL();\r
-BFD01AF8 40AA77E8 JALS vTaskExitCritical
-BFD01AFA 0C0040AA BNEZC T2, 0xBFD032FE
-BFD01AFC 0C00 NOP
+BFD01AF8 40AA77E8 JALS vTaskExitCritical\r
+BFD01AFA 0C0040AA BNEZC T2, 0xBFD032FE\r
+BFD01AFC 0C00 NOP\r
1277: }\r
-BFD01AFE 0FBE MOVE SP, S8
-BFD01B00 4BEB LW RA, 44(SP)
-BFD01B02 4BCA LW S8, 40(SP)
-BFD01B04 4C19 ADDIU SP, SP, 48
-BFD01B06 459F JR16 RA
-BFD01B08 0C00 NOP
+BFD01AFE 0FBE MOVE SP, S8\r
+BFD01B00 4BEB LW RA, 44(SP)\r
+BFD01B02 4BCA LW S8, 40(SP)\r
+BFD01B04 4C19 ADDIU SP, SP, 48\r
+BFD01B06 459F JR16 RA\r
+BFD01B08 0C00 NOP\r
1278: \r
1279: #endif /* INCLUDE_vTaskPrioritySet */\r
1280: /*-----------------------------------------------------------*/\r
1283: \r
1284: void vTaskSuspend( TaskHandle_t xTaskToSuspend )\r
1285: {\r
-BFD0304C 4FF1 ADDIU SP, SP, -32
-BFD0304E CBE7 SW RA, 28(SP)
-BFD03050 CBC6 SW S8, 24(SP)
-BFD03052 0FDD MOVE S8, SP
-BFD03054 0020F89E SW A0, 32(S8)
+BFD0304C 4FF1 ADDIU SP, SP, -32\r
+BFD0304E CBE7 SW RA, 28(SP)\r
+BFD03050 CBC6 SW S8, 24(SP)\r
+BFD03052 0FDD MOVE S8, SP\r
+BFD03054 0020F89E SW A0, 32(S8)\r
1286: TCB_t *pxTCB;\r
1287: \r
1288: taskENTER_CRITICAL();\r
-BFD03058 33B877E8 JALS vTaskEnterCritical
-BFD0305A 0C0033B8 ADDIU SP, T8, 3072
-BFD0305C 0C00 NOP
+BFD03058 33B877E8 JALS vTaskEnterCritical\r
+BFD0305A 0C0033B8 ADDIU SP, T8, 3072\r
+BFD0305C 0C00 NOP\r
1289: {\r
1290: /* If null is passed in here then it is the running task that is\r
1291: being suspended. */\r
1292: pxTCB = prvGetTCBFromHandle( xTaskToSuspend );\r
-BFD0305E 0020FC5E LW V0, 32(S8)
-BFD03062 000440A2 BNEZC V0, 0xBFD0306E
-BFD03066 8030FC5C LW V0, -32720(GP)
-BFD0306A CC03 B 0xBFD03072
-BFD0306C 0C00 NOP
-BFD0306E 0020FC5E LW V0, 32(S8)
-BFD03072 0010F85E SW V0, 16(S8)
+BFD0305E 0020FC5E LW V0, 32(S8)\r
+BFD03062 000440A2 BNEZC V0, 0xBFD0306E\r
+BFD03066 8030FC5C LW V0, -32720(GP)\r
+BFD0306A CC03 B 0xBFD03072\r
+BFD0306C 0C00 NOP\r
+BFD0306E 0020FC5E LW V0, 32(S8)\r
+BFD03072 0010F85E SW V0, 16(S8)\r
1293: \r
1294: traceTASK_SUSPEND( pxTCB );\r
1295: \r
1296: /* Remove task from the ready/delayed list and place in the\r
1297: suspended list. */\r
1298: if( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r
-BFD03076 0010FC5E LW V0, 16(S8)
-BFD0307A 6D22 ADDIU V0, V0, 4
-BFD0307C 0C82 MOVE A0, V0
-BFD0307E 00C877E8 JALS uxListRemove
-BFD03080 0C0000C8 SLL A2, T0, 1
-BFD03082 0C00 NOP
-BFD03084 001A40A2 BNEZC V0, 0xBFD030BC
+BFD03076 0010FC5E LW V0, 16(S8)\r
+BFD0307A 6D22 ADDIU V0, V0, 4\r
+BFD0307C 0C82 MOVE A0, V0\r
+BFD0307E 00C877E8 JALS uxListRemove\r
+BFD03080 0C0000C8 SLL A2, T0, 1\r
+BFD03082 0C00 NOP\r
+BFD03084 001A40A2 BNEZC V0, 0xBFD030BC\r
1299: {\r
1300: taskRESET_READY_PRIORITY( pxTCB->uxPriority );\r
-BFD03088 0010FC5E LW V0, 16(S8)
-BFD0308C 692B LW V0, 44(V0)
-BFD0308E 2524 SLL V0, V0, 2
-BFD03090 25A4 SLL V1, V0, 2
-BFD03092 05B4 ADDU V1, V0, V1
-BFD03094 BFD241A2 LUI V0, 0xBFD2
-BFD03096 3042BFD2 LDC1 F30, 12354(S2)
-BFD03098 806C3042 ADDIU V0, V0, -32660
-BFD0309C 0526 ADDU V0, V1, V0
-BFD0309E 6920 LW V0, 0(V0)
-BFD030A0 000C40A2 BNEZC V0, 0xBFD030BC
-BFD030A4 0010FC5E LW V0, 16(S8)
-BFD030A8 692B LW V0, 44(V0)
-BFD030AA ED81 LI V1, 1
-BFD030AC 10100062 SLLV V0, V0, V1
-BFD030AE 441A1010 ADDI ZERO, S0, 17434
-BFD030B0 441A NOT16 V1, V0
-BFD030B2 8040FC5C LW V0, -32704(GP)
-BFD030B6 4493 AND16 V0, V1
-BFD030B8 8040F85C SW V0, -32704(GP)
+BFD03088 0010FC5E LW V0, 16(S8)\r
+BFD0308C 692B LW V0, 44(V0)\r
+BFD0308E 2524 SLL V0, V0, 2\r
+BFD03090 25A4 SLL V1, V0, 2\r
+BFD03092 05B4 ADDU V1, V0, V1\r
+BFD03094 BFD241A2 LUI V0, 0xBFD2\r
+BFD03096 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD03098 806C3042 ADDIU V0, V0, -32660\r
+BFD0309C 0526 ADDU V0, V1, V0\r
+BFD0309E 6920 LW V0, 0(V0)\r
+BFD030A0 000C40A2 BNEZC V0, 0xBFD030BC\r
+BFD030A4 0010FC5E LW V0, 16(S8)\r
+BFD030A8 692B LW V0, 44(V0)\r
+BFD030AA ED81 LI V1, 1\r
+BFD030AC 10100062 SLLV V0, V0, V1\r
+BFD030AE 441A1010 ADDI ZERO, S0, 17434\r
+BFD030B0 441A NOT16 V1, V0\r
+BFD030B2 8040FC5C LW V0, -32704(GP)\r
+BFD030B6 4493 AND16 V0, V1\r
+BFD030B8 8040F85C SW V0, -32704(GP)\r
1301: }\r
1302: else\r
1303: {\r
1306: \r
1307: /* Is the task waiting on an event also? */\r
1308: if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )\r
-BFD030BC 0010FC5E LW V0, 16(S8)
-BFD030C0 692A LW V0, 40(V0)
-BFD030C2 000740E2 BEQZC V0, 0xBFD030D4
+BFD030BC 0010FC5E LW V0, 16(S8)\r
+BFD030C0 692A LW V0, 40(V0)\r
+BFD030C2 000740E2 BEQZC V0, 0xBFD030D4\r
1309: {\r
1310: ( void ) uxListRemove( &( pxTCB->xEventListItem ) );\r
-BFD030C6 0010FC5E LW V0, 16(S8)
-BFD030C8 6D2C0010 EXT ZERO, S0, 20, 14
-BFD030CA 6D2C ADDIU V0, V0, 24
-BFD030CC 0C82 MOVE A0, V0
-BFD030CE 00C877E8 JALS uxListRemove
-BFD030D0 0C0000C8 SLL A2, T0, 1
-BFD030D2 0C00 NOP
+BFD030C6 0010FC5E LW V0, 16(S8)\r
+BFD030C8 6D2C0010 EXT ZERO, S0, 20, 14\r
+BFD030CA 6D2C ADDIU V0, V0, 24\r
+BFD030CC 0C82 MOVE A0, V0\r
+BFD030CE 00C877E8 JALS uxListRemove\r
+BFD030D0 0C0000C8 SLL A2, T0, 1\r
+BFD030D2 0C00 NOP\r
1311: }\r
1312: else\r
1313: {\r
1315: }\r
1316: \r
1317: vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) );\r
-BFD030D4 0010FC5E LW V0, 16(S8)
-BFD030D8 6D22 ADDIU V0, V0, 4
-BFD030DA BFD241A3 LUI V1, 0xBFD2
-BFD030DC 3083BFD2 LDC1 F30, 12419(S2)
-BFD030DE 80E43083 ADDIU A0, V1, -32540
-BFD030E2 0CA2 MOVE A1, V0
-BFD030E4 3E4A77E8 JALS vListInsertEnd
-BFD030E6 0C003E4A LH S2, 3072(T2)
-BFD030E8 0C00 NOP
+BFD030D4 0010FC5E LW V0, 16(S8)\r
+BFD030D8 6D22 ADDIU V0, V0, 4\r
+BFD030DA BFD241A3 LUI V1, 0xBFD2\r
+BFD030DC 3083BFD2 LDC1 F30, 12419(S2)\r
+BFD030DE 80E43083 ADDIU A0, V1, -32540\r
+BFD030E2 0CA2 MOVE A1, V0\r
+BFD030E4 3E4A77E8 JALS vListInsertEnd\r
+BFD030E6 0C003E4A LH S2, 3072(T2)\r
+BFD030E8 0C00 NOP\r
1318: }\r
1319: taskEXIT_CRITICAL();\r
-BFD030EA 40AA77E8 JALS vTaskExitCritical
-BFD030EC 0C0040AA BNEZC T2, 0xBFD048F0
-BFD030EE 0C00 NOP
+BFD030EA 40AA77E8 JALS vTaskExitCritical\r
+BFD030EC 0C0040AA BNEZC T2, 0xBFD048F0\r
+BFD030EE 0C00 NOP\r
1320: \r
1321: if( pxTCB == pxCurrentTCB )\r
-BFD030F0 8030FC5C LW V0, -32720(GP)
-BFD030F4 0010FC7E LW V1, 16(S8)
-BFD030F8 0036B443 BNE V1, V0, 0xBFD03168
-BFD030FA 0C000036 SLL AT, S6, 1
-BFD030FC 0C00 NOP
+BFD030F0 8030FC5C LW V0, -32720(GP)\r
+BFD030F4 0010FC7E LW V1, 16(S8)\r
+BFD030F8 0036B443 BNE V1, V0, 0xBFD03168\r
+BFD030FA 0C000036 SLL AT, S6, 1\r
+BFD030FC 0C00 NOP\r
1322: {\r
1323: if( xSchedulerRunning != pdFALSE )\r
-BFD030FE 8044FC5C LW V0, -32700(GP)
-BFD03102 001F40E2 BEQZC V0, 0xBFD03144
+BFD030FE 8044FC5C LW V0, -32700(GP)\r
+BFD03102 001F40E2 BEQZC V0, 0xBFD03144\r
1324: {\r
1325: /* The current task has just been suspended. */\r
1326: configASSERT( uxSchedulerSuspended == 0 );\r
-BFD03106 805CFC5C LW V0, -32676(GP)
-BFD0310A 000940E2 BEQZC V0, 0xBFD03120
-BFD0310E BFD141A2 LUI V0, 0xBFD1
-BFD03110 3082BFD1 LDC1 F30, 12418(S1)
-BFD03112 98103082 ADDIU A0, V0, -26608
-BFD03114 30A09810 SWC1 F0, 12448(S0)
-BFD03116 052E30A0 ADDIU A1, ZERO, 1326
-BFD03118 052E ADDU V0, A3, V0
-BFD0311A 4B7E77E8 JALS vAssertCalled
-BFD0311C 4B7E LW K1, 120(SP)
-BFD0311E 0C00 NOP
+BFD03106 805CFC5C LW V0, -32676(GP)\r
+BFD0310A 000940E2 BEQZC V0, 0xBFD03120\r
+BFD0310E BFD141A2 LUI V0, 0xBFD1\r
+BFD03110 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD03112 98103082 ADDIU A0, V0, -26608\r
+BFD03114 30A09810 SWC1 F0, 12448(S0)\r
+BFD03116 052E30A0 ADDIU A1, ZERO, 1326\r
+BFD03118 052E ADDU V0, A3, V0\r
+BFD0311A 4B7E77E8 JALS vAssertCalled\r
+BFD0311C 4B7E LW K1, 120(SP)\r
+BFD0311E 0C00 NOP\r
1327: portYIELD_WITHIN_API();\r
-BFD03120 4E5677E8 JALS ulPortGetCP0Cause
-BFD03122 4E56 ADDIU S2, S2, -5
-BFD03124 0C00 NOP
-BFD03126 0014F85E SW V0, 20(S8)
-BFD0312A 0014FC5E LW V0, 20(S8)
-BFD0312E 01005042 ORI V0, V0, 256
-BFD03132 0014F85E SW V0, 20(S8)
-BFD03136 0014FC9E LW A0, 20(S8)
-BFD0313A 4E6677E8 JALS vPortSetCP0Cause
-BFD0313C 4E66 ADDIU S3, S3, 3
-BFD0313E 0C00 NOP
-BFD03140 CC20 B 0xBFD03182
-BFD03142 0C00 NOP
+BFD03120 4E5677E8 JALS ulPortGetCP0Cause\r
+BFD03122 4E56 ADDIU S2, S2, -5\r
+BFD03124 0C00 NOP\r
+BFD03126 0014F85E SW V0, 20(S8)\r
+BFD0312A 0014FC5E LW V0, 20(S8)\r
+BFD0312E 01005042 ORI V0, V0, 256\r
+BFD03132 0014F85E SW V0, 20(S8)\r
+BFD03136 0014FC9E LW A0, 20(S8)\r
+BFD0313A 4E6677E8 JALS vPortSetCP0Cause\r
+BFD0313C 4E66 ADDIU S3, S3, 3\r
+BFD0313E 0C00 NOP\r
+BFD03140 CC20 B 0xBFD03182\r
+BFD03142 0C00 NOP\r
1328: }\r
1329: else\r
1330: {\r
1332: to by pxCurrentTCB has just been suspended and pxCurrentTCB\r
1333: must be adjusted to point to a different task. */\r
1334: if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks )\r
-BFD03144 BFD241A2 LUI V0, 0xBFD2
-BFD03146 FC62BFD2 LDC1 F30, -926(S2)
-BFD03148 80E4FC62 LW V1, -32540(V0)
-BFD0314C 8038FC5C LW V0, -32712(GP)
-BFD03150 0005B443 BNE V1, V0, 0xBFD0315E
-BFD03152 0C000005 SLL ZERO, A1, 1
-BFD03154 0C00 NOP
+BFD03144 BFD241A2 LUI V0, 0xBFD2\r
+BFD03146 FC62BFD2 LDC1 F30, -926(S2)\r
+BFD03148 80E4FC62 LW V1, -32540(V0)\r
+BFD0314C 8038FC5C LW V0, -32712(GP)\r
+BFD03150 0005B443 BNE V1, V0, 0xBFD0315E\r
+BFD03152 0C000005 SLL ZERO, A1, 1\r
+BFD03154 0C00 NOP\r
1335: {\r
1336: /* No other tasks are ready, so set pxCurrentTCB back to\r
1337: NULL so when the next task is created pxCurrentTCB will\r
1338: be set to point to it no matter what its relative priority\r
1339: is. */\r
1340: pxCurrentTCB = NULL;\r
-BFD03156 8030F81C SW ZERO, -32720(GP)
-BFD0315A CC13 B 0xBFD03182
-BFD0315C 0C00 NOP
+BFD03156 8030F81C SW ZERO, -32720(GP)\r
+BFD0315A CC13 B 0xBFD03182\r
+BFD0315C 0C00 NOP\r
1341: }\r
1342: else\r
1343: {\r
1344: vTaskSwitchContext();\r
-BFD0315E 16DE77E8 JALS vTaskSwitchContext
-BFD03160 0C0016DE LBU S6, 3072(S8)
-BFD03162 0C00 NOP
-BFD03164 CC0E B 0xBFD03182
-BFD03166 0C00 NOP
+BFD0315E 16DE77E8 JALS vTaskSwitchContext\r
+BFD03160 0C0016DE LBU S6, 3072(S8)\r
+BFD03162 0C00 NOP\r
+BFD03164 CC0E B 0xBFD03182\r
+BFD03166 0C00 NOP\r
1345: }\r
1346: }\r
1347: }\r
1348: else\r
1349: {\r
1350: if( xSchedulerRunning != pdFALSE )\r
-BFD03168 8044FC5C LW V0, -32700(GP)
-BFD0316C 000940E2 BEQZC V0, 0xBFD03182
+BFD03168 8044FC5C LW V0, -32700(GP)\r
+BFD0316C 000940E2 BEQZC V0, 0xBFD03182\r
1351: {\r
1352: /* A task other than the currently running task was suspended,\r
1353: reset the next expected unblock time in case it referred to the\r
1354: task that is now in the Suspended state. */\r
1355: taskENTER_CRITICAL();\r
-BFD03170 33B877E8 JALS vTaskEnterCritical
-BFD03172 0C0033B8 ADDIU SP, T8, 3072
-BFD03174 0C00 NOP
+BFD03170 33B877E8 JALS vTaskEnterCritical\r
+BFD03172 0C0033B8 ADDIU SP, T8, 3072\r
+BFD03174 0C00 NOP\r
1356: {\r
1357: prvResetNextTaskUnblockTime();\r
-BFD03176 47CA77E8 JALS prvResetNextTaskUnblockTime
-BFD0317A 0C00 NOP
+BFD03176 47CA77E8 JALS prvResetNextTaskUnblockTime\r
+BFD0317A 0C00 NOP\r
1358: }\r
1359: taskEXIT_CRITICAL();\r
-BFD0317C 40AA77E8 JALS vTaskExitCritical
-BFD0317E 0C0040AA BNEZC T2, 0xBFD04982
-BFD03180 0C00 NOP
+BFD0317C 40AA77E8 JALS vTaskExitCritical\r
+BFD0317E 0C0040AA BNEZC T2, 0xBFD04982\r
+BFD03180 0C00 NOP\r
1360: }\r
1361: else\r
1362: {\r
1364: }\r
1365: }\r
1366: }\r
-BFD03182 0FBE MOVE SP, S8
-BFD03184 4BE7 LW RA, 28(SP)
-BFD03186 4BC6 LW S8, 24(SP)
-BFD03188 4C11 ADDIU SP, SP, 32
-BFD0318A 459F JR16 RA
-BFD0318C 0C00 NOP
+BFD03182 0FBE MOVE SP, S8\r
+BFD03184 4BE7 LW RA, 28(SP)\r
+BFD03186 4BC6 LW S8, 24(SP)\r
+BFD03188 4C11 ADDIU SP, SP, 32\r
+BFD0318A 459F JR16 RA\r
+BFD0318C 0C00 NOP\r
1367: \r
1368: #endif /* INCLUDE_vTaskSuspend */\r
1369: /*-----------------------------------------------------------*/\r
1372: \r
1373: static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )\r
1374: {\r
-BFD066DC 4FF1 ADDIU SP, SP, -32
-BFD066DE CBE7 SW RA, 28(SP)
-BFD066E0 CBC6 SW S8, 24(SP)
-BFD066E2 0FDD MOVE S8, SP
-BFD066E4 0020F89E SW A0, 32(S8)
+BFD066DC 4FF1 ADDIU SP, SP, -32\r
+BFD066DE CBE7 SW RA, 28(SP)\r
+BFD066E0 CBC6 SW S8, 24(SP)\r
+BFD066E2 0FDD MOVE S8, SP\r
+BFD066E4 0020F89E SW A0, 32(S8)\r
1375: BaseType_t xReturn = pdFALSE;\r
-BFD066E8 0010F81E SW ZERO, 16(S8)
+BFD066E8 0010F81E SW ZERO, 16(S8)\r
1376: const TCB_t * const pxTCB = ( TCB_t * ) xTask;\r
-BFD066EC 0020FC5E LW V0, 32(S8)
-BFD066F0 0014F85E SW V0, 20(S8)
+BFD066EC 0020FC5E LW V0, 32(S8)\r
+BFD066F0 0014F85E SW V0, 20(S8)\r
1377: \r
1378: /* Accesses xPendingReadyList so must be called from a critical\r
1379: section. */\r
1380: \r
1381: /* It does not make sense to check if the calling task is suspended. */\r
1382: configASSERT( xTask );\r
-BFD066F4 0020FC5E LW V0, 32(S8)
-BFD066F8 000940A2 BNEZC V0, 0xBFD0670E
-BFD066FC BFD141A2 LUI V0, 0xBFD1
-BFD066FE 3082BFD1 LDC1 F30, 12418(S1)
-BFD06700 98103082 ADDIU A0, V0, -26608
-BFD06702 30A09810 SWC1 F0, 12448(S0)
-BFD06704 056630A0 ADDIU A1, ZERO, 1382
-BFD06706 0566 ADDU V0, V1, A2
-BFD06708 4B7E77E8 JALS vAssertCalled
-BFD0670A 4B7E LW K1, 120(SP)
-BFD0670C 0C00 NOP
+BFD066F4 0020FC5E LW V0, 32(S8)\r
+BFD066F8 000940A2 BNEZC V0, 0xBFD0670E\r
+BFD066FC BFD141A2 LUI V0, 0xBFD1\r
+BFD066FE 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD06700 98103082 ADDIU A0, V0, -26608\r
+BFD06702 30A09810 SWC1 F0, 12448(S0)\r
+BFD06704 056630A0 ADDIU A1, ZERO, 1382\r
+BFD06706 0566 ADDU V0, V1, A2\r
+BFD06708 4B7E77E8 JALS vAssertCalled\r
+BFD0670A 4B7E LW K1, 120(SP)\r
+BFD0670C 0C00 NOP\r
1383: \r
1384: /* Is the task being resumed actually in the suspended list? */\r
1385: if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ) != pdFALSE )\r
-BFD0670E 0014FC5E LW V0, 20(S8)
-BFD06710 69A50014 LWX T5, 0(S4)
-BFD06712 69A5 LW V1, 20(V0)
-BFD06714 BFD241A2 LUI V0, 0xBFD2
-BFD06716 3042BFD2 LDC1 F30, 12354(S2)
-BFD06718 80E43042 ADDIU V0, V0, -32540
-BFD0671C 0004B443 BNE V1, V0, 0xBFD06728
-BFD0671E 0C000004 SLL ZERO, A0, 1
-BFD06720 0C00 NOP
-BFD06722 ED01 LI V0, 1
-BFD06724 CC02 B 0xBFD0672A
-BFD06726 0C00 NOP
-BFD06728 0C40 MOVE V0, ZERO
-BFD0672A 001840E2 BEQZC V0, 0xBFD0675E
+BFD0670E 0014FC5E LW V0, 20(S8)\r
+BFD06710 69A50014 LWX T5, 0(S4)\r
+BFD06712 69A5 LW V1, 20(V0)\r
+BFD06714 BFD241A2 LUI V0, 0xBFD2\r
+BFD06716 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD06718 80E43042 ADDIU V0, V0, -32540\r
+BFD0671C 0004B443 BNE V1, V0, 0xBFD06728\r
+BFD0671E 0C000004 SLL ZERO, A0, 1\r
+BFD06720 0C00 NOP\r
+BFD06722 ED01 LI V0, 1\r
+BFD06724 CC02 B 0xBFD0672A\r
+BFD06726 0C00 NOP\r
+BFD06728 0C40 MOVE V0, ZERO\r
+BFD0672A 001840E2 BEQZC V0, 0xBFD0675E\r
1386: {\r
1387: /* Has the task already been resumed from within an ISR? */\r
1388: if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )\r
-BFD0672E 0014FC5E LW V0, 20(S8)
-BFD06732 69AA LW V1, 40(V0)
-BFD06734 BFD241A2 LUI V0, 0xBFD2
-BFD06736 3042BFD2 LDC1 F30, 12354(S2)
-BFD06738 80D03042 ADDIU V0, V0, -32560
-BFD0673C 000F9443 BEQ V1, V0, 0xBFD0675E
-BFD0673E 0C00000F SLL ZERO, T7, 1
-BFD06740 0C00 NOP
+BFD0672E 0014FC5E LW V0, 20(S8)\r
+BFD06732 69AA LW V1, 40(V0)\r
+BFD06734 BFD241A2 LUI V0, 0xBFD2\r
+BFD06736 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD06738 80D03042 ADDIU V0, V0, -32560\r
+BFD0673C 000F9443 BEQ V1, V0, 0xBFD0675E\r
+BFD0673E 0C00000F SLL ZERO, T7, 1\r
+BFD06740 0C00 NOP\r
1389: {\r
1390: /* Is it in the suspended list because it is in the Suspended\r
1391: state, or because is is blocked with no timeout? */\r
1392: if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE )\r
-BFD06742 0014FC5E LW V0, 20(S8)
-BFD06746 692A LW V0, 40(V0)
-BFD06748 000340A2 BNEZC V0, 0xBFD06752
-BFD0674C ED01 LI V0, 1
-BFD0674E CC02 B 0xBFD06754
-BFD06750 0C00 NOP
-BFD06752 0C40 MOVE V0, ZERO
-BFD06754 000340E2 BEQZC V0, 0xBFD0675E
+BFD06742 0014FC5E LW V0, 20(S8)\r
+BFD06746 692A LW V0, 40(V0)\r
+BFD06748 000340A2 BNEZC V0, 0xBFD06752\r
+BFD0674C ED01 LI V0, 1\r
+BFD0674E CC02 B 0xBFD06754\r
+BFD06750 0C00 NOP\r
+BFD06752 0C40 MOVE V0, ZERO\r
+BFD06754 000340E2 BEQZC V0, 0xBFD0675E\r
1393: {\r
1394: xReturn = pdTRUE;\r
-BFD06758 ED01 LI V0, 1
-BFD0675A 0010F85E SW V0, 16(S8)
+BFD06758 ED01 LI V0, 1\r
+BFD0675A 0010F85E SW V0, 16(S8)\r
1395: }\r
1396: else\r
1397: {\r
1409: }\r
1410: \r
1411: return xReturn;\r
-BFD0675E 0010FC5E LW V0, 16(S8)
+BFD0675E 0010FC5E LW V0, 16(S8)\r
1412: } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */\r
-BFD06762 0FBE MOVE SP, S8
-BFD06764 4BE7 LW RA, 28(SP)
-BFD06766 4BC6 LW S8, 24(SP)
-BFD06768 4C11 ADDIU SP, SP, 32
-BFD0676A 459F JR16 RA
-BFD0676C 0C00 NOP
+BFD06762 0FBE MOVE SP, S8\r
+BFD06764 4BE7 LW RA, 28(SP)\r
+BFD06766 4BC6 LW S8, 24(SP)\r
+BFD06768 4C11 ADDIU SP, SP, 32\r
+BFD0676A 459F JR16 RA\r
+BFD0676C 0C00 NOP\r
1413: \r
1414: #endif /* INCLUDE_vTaskSuspend */\r
1415: /*-----------------------------------------------------------*/\r
1418: \r
1419: void vTaskResume( TaskHandle_t xTaskToResume )\r
1420: {\r
-BFD040E4 4FF1 ADDIU SP, SP, -32
-BFD040E6 CBE7 SW RA, 28(SP)
-BFD040E8 CBC6 SW S8, 24(SP)
-BFD040EA 0FDD MOVE S8, SP
-BFD040EC 0020F89E SW A0, 32(S8)
+BFD040E4 4FF1 ADDIU SP, SP, -32\r
+BFD040E6 CBE7 SW RA, 28(SP)\r
+BFD040E8 CBC6 SW S8, 24(SP)\r
+BFD040EA 0FDD MOVE S8, SP\r
+BFD040EC 0020F89E SW A0, 32(S8)\r
1421: TCB_t * const pxTCB = ( TCB_t * ) xTaskToResume;\r
-BFD040F0 0020FC5E LW V0, 32(S8)
-BFD040F4 0010F85E SW V0, 16(S8)
+BFD040F0 0020FC5E LW V0, 32(S8)\r
+BFD040F4 0010F85E SW V0, 16(S8)\r
1422: \r
1423: /* It does not make sense to resume the calling task. */\r
1424: configASSERT( xTaskToResume );\r
-BFD040F8 0020FC5E LW V0, 32(S8)
-BFD040FC 000940A2 BNEZC V0, 0xBFD04112
-BFD04100 BFD141A2 LUI V0, 0xBFD1
-BFD04102 3082BFD1 LDC1 F30, 12418(S1)
-BFD04104 98103082 ADDIU A0, V0, -26608
-BFD04106 30A09810 SWC1 F0, 12448(S0)
-BFD04108 059030A0 ADDIU A1, ZERO, 1424
-BFD0410A 0590 ADDU V1, S0, S1
-BFD0410C 4B7E77E8 JALS vAssertCalled
-BFD0410E 4B7E LW K1, 120(SP)
-BFD04110 0C00 NOP
+BFD040F8 0020FC5E LW V0, 32(S8)\r
+BFD040FC 000940A2 BNEZC V0, 0xBFD04112\r
+BFD04100 BFD141A2 LUI V0, 0xBFD1\r
+BFD04102 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD04104 98103082 ADDIU A0, V0, -26608\r
+BFD04106 30A09810 SWC1 F0, 12448(S0)\r
+BFD04108 059030A0 ADDIU A1, ZERO, 1424\r
+BFD0410A 0590 ADDU V1, S0, S1\r
+BFD0410C 4B7E77E8 JALS vAssertCalled\r
+BFD0410E 4B7E LW K1, 120(SP)\r
+BFD04110 0C00 NOP\r
1425: \r
1426: /* The parameter cannot be NULL as it is impossible to resume the\r
1427: currently executing task. */\r
1428: if( ( pxTCB != NULL ) && ( pxTCB != pxCurrentTCB ) )\r
-BFD04112 0010FC5E LW V0, 16(S8)
-BFD04116 005640E2 BEQZC V0, 0xBFD041C6
-BFD0411A 8030FC5C LW V0, -32720(GP)
-BFD0411E 0010FC7E LW V1, 16(S8)
-BFD04122 00509443 BEQ V1, V0, 0xBFD041C6
-BFD04124 0C000050 SLL V0, S0, 1
-BFD04126 0C00 NOP
+BFD04112 0010FC5E LW V0, 16(S8)\r
+BFD04116 005640E2 BEQZC V0, 0xBFD041C6\r
+BFD0411A 8030FC5C LW V0, -32720(GP)\r
+BFD0411E 0010FC7E LW V1, 16(S8)\r
+BFD04122 00509443 BEQ V1, V0, 0xBFD041C6\r
+BFD04124 0C000050 SLL V0, S0, 1\r
+BFD04126 0C00 NOP\r
1429: {\r
1430: taskENTER_CRITICAL();\r
-BFD04128 33B877E8 JALS vTaskEnterCritical
-BFD0412A 0C0033B8 ADDIU SP, T8, 3072
-BFD0412C 0C00 NOP
+BFD04128 33B877E8 JALS vTaskEnterCritical\r
+BFD0412A 0C0033B8 ADDIU SP, T8, 3072\r
+BFD0412C 0C00 NOP\r
1431: {\r
1432: if( prvTaskIsTaskSuspended( pxTCB ) == pdTRUE )\r
-BFD0412E 0010FC9E LW A0, 16(S8)
-BFD04132 336E77E8 JALS prvTaskIsTaskSuspended
-BFD04134 0C00336E ADDIU K1, T6, 3072
-BFD04136 0C00 NOP
-BFD04138 0C62 MOVE V1, V0
-BFD0413A ED01 LI V0, 1
-BFD0413C 0040B443 BNE V1, V0, 0xBFD041C0
-BFD0413E 0C000040 SLL V0, ZERO, 1
-BFD04140 0C00 NOP
+BFD0412E 0010FC9E LW A0, 16(S8)\r
+BFD04132 336E77E8 JALS prvTaskIsTaskSuspended\r
+BFD04134 0C00336E ADDIU K1, T6, 3072\r
+BFD04136 0C00 NOP\r
+BFD04138 0C62 MOVE V1, V0\r
+BFD0413A ED01 LI V0, 1\r
+BFD0413C 0040B443 BNE V1, V0, 0xBFD041C0\r
+BFD0413E 0C000040 SLL V0, ZERO, 1\r
+BFD04140 0C00 NOP\r
1433: {\r
1434: traceTASK_RESUME( pxTCB );\r
1435: \r
1436: /* As we are in a critical section we can access the ready\r
1437: lists even if the scheduler is suspended. */\r
1438: ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );\r
-BFD04142 0010FC5E LW V0, 16(S8)
-BFD04146 6D22 ADDIU V0, V0, 4
-BFD04148 0C82 MOVE A0, V0
-BFD0414A 00C877E8 JALS uxListRemove
-BFD0414C 0C0000C8 SLL A2, T0, 1
-BFD0414E 0C00 NOP
+BFD04142 0010FC5E LW V0, 16(S8)\r
+BFD04146 6D22 ADDIU V0, V0, 4\r
+BFD04148 0C82 MOVE A0, V0\r
+BFD0414A 00C877E8 JALS uxListRemove\r
+BFD0414C 0C0000C8 SLL A2, T0, 1\r
+BFD0414E 0C00 NOP\r
1439: prvAddTaskToReadyList( pxTCB );\r
-BFD04150 0010FC5E LW V0, 16(S8)
-BFD04154 692B LW V0, 44(V0)
-BFD04156 ED81 LI V1, 1
-BFD04158 18100062 SLLV V1, V0, V1
-BFD0415A FC5C1810 SB ZERO, -932(S0)
-BFD0415C 8040FC5C LW V0, -32704(GP)
-BFD04160 44D3 OR16 V0, V1
-BFD04162 8040F85C SW V0, -32704(GP)
-BFD04166 0010FC5E LW V0, 16(S8)
-BFD0416A 692B LW V0, 44(V0)
-BFD0416C 2524 SLL V0, V0, 2
-BFD0416E 25A4 SLL V1, V0, 2
-BFD04170 05B4 ADDU V1, V0, V1
-BFD04172 BFD241A2 LUI V0, 0xBFD2
-BFD04174 3042BFD2 LDC1 F30, 12354(S2)
-BFD04176 806C3042 ADDIU V0, V0, -32660
-BFD0417A 05A6 ADDU V1, V1, V0
-BFD0417C 0010FC5E LW V0, 16(S8)
-BFD04180 6D22 ADDIU V0, V0, 4
-BFD04182 0C83 MOVE A0, V1
-BFD04184 0CA2 MOVE A1, V0
-BFD04186 3E4A77E8 JALS vListInsertEnd
-BFD04188 0C003E4A LH S2, 3072(T2)
-BFD0418A 0C00 NOP
+BFD04150 0010FC5E LW V0, 16(S8)\r
+BFD04154 692B LW V0, 44(V0)\r
+BFD04156 ED81 LI V1, 1\r
+BFD04158 18100062 SLLV V1, V0, V1\r
+BFD0415A FC5C1810 SB ZERO, -932(S0)\r
+BFD0415C 8040FC5C LW V0, -32704(GP)\r
+BFD04160 44D3 OR16 V0, V1\r
+BFD04162 8040F85C SW V0, -32704(GP)\r
+BFD04166 0010FC5E LW V0, 16(S8)\r
+BFD0416A 692B LW V0, 44(V0)\r
+BFD0416C 2524 SLL V0, V0, 2\r
+BFD0416E 25A4 SLL V1, V0, 2\r
+BFD04170 05B4 ADDU V1, V0, V1\r
+BFD04172 BFD241A2 LUI V0, 0xBFD2\r
+BFD04174 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD04176 806C3042 ADDIU V0, V0, -32660\r
+BFD0417A 05A6 ADDU V1, V1, V0\r
+BFD0417C 0010FC5E LW V0, 16(S8)\r
+BFD04180 6D22 ADDIU V0, V0, 4\r
+BFD04182 0C83 MOVE A0, V1\r
+BFD04184 0CA2 MOVE A1, V0\r
+BFD04186 3E4A77E8 JALS vListInsertEnd\r
+BFD04188 0C003E4A LH S2, 3072(T2)\r
+BFD0418A 0C00 NOP\r
1440: \r
1441: /* We may have just resumed a higher priority task. */\r
1442: if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )\r
-BFD0418C 0010FC5E LW V0, 16(S8)
-BFD04190 69AB LW V1, 44(V0)
-BFD04192 8030FC5C LW V0, -32720(GP)
-BFD04196 692B LW V0, 44(V0)
-BFD04198 13900043 SLTU V0, V1, V0
-BFD0419A 40A21390 ADDI GP, S0, 16546
-BFD0419C 001040A2 BNEZC V0, 0xBFD041C0
+BFD0418C 0010FC5E LW V0, 16(S8)\r
+BFD04190 69AB LW V1, 44(V0)\r
+BFD04192 8030FC5C LW V0, -32720(GP)\r
+BFD04196 692B LW V0, 44(V0)\r
+BFD04198 13900043 SLTU V0, V1, V0\r
+BFD0419A 40A21390 ADDI GP, S0, 16546\r
+BFD0419C 001040A2 BNEZC V0, 0xBFD041C0\r
1443: {\r
1444: /* This yield may not cause the task just resumed to run,\r
1445: but will leave the lists in the correct state for the\r
1446: next yield. */\r
1447: taskYIELD_IF_USING_PREEMPTION();\r
-BFD041A0 4E5677E8 JALS ulPortGetCP0Cause
-BFD041A2 4E56 ADDIU S2, S2, -5
-BFD041A4 0C00 NOP
-BFD041A6 0014F85E SW V0, 20(S8)
-BFD041AA 0014FC5E LW V0, 20(S8)
-BFD041AE 01005042 ORI V0, V0, 256
-BFD041B2 0014F85E SW V0, 20(S8)
-BFD041B6 0014FC9E LW A0, 20(S8)
-BFD041BA 4E6677E8 JALS vPortSetCP0Cause
-BFD041BC 4E66 ADDIU S3, S3, 3
-BFD041BE 0C00 NOP
+BFD041A0 4E5677E8 JALS ulPortGetCP0Cause\r
+BFD041A2 4E56 ADDIU S2, S2, -5\r
+BFD041A4 0C00 NOP\r
+BFD041A6 0014F85E SW V0, 20(S8)\r
+BFD041AA 0014FC5E LW V0, 20(S8)\r
+BFD041AE 01005042 ORI V0, V0, 256\r
+BFD041B2 0014F85E SW V0, 20(S8)\r
+BFD041B6 0014FC9E LW A0, 20(S8)\r
+BFD041BA 4E6677E8 JALS vPortSetCP0Cause\r
+BFD041BC 4E66 ADDIU S3, S3, 3\r
+BFD041BE 0C00 NOP\r
1448: }\r
1449: else\r
1450: {\r
1457: }\r
1458: }\r
1459: taskEXIT_CRITICAL();\r
-BFD041C0 40AA77E8 JALS vTaskExitCritical
-BFD041C2 0C0040AA BNEZC T2, 0xBFD059C6
-BFD041C4 0C00 NOP
+BFD041C0 40AA77E8 JALS vTaskExitCritical\r
+BFD041C2 0C0040AA BNEZC T2, 0xBFD059C6\r
+BFD041C4 0C00 NOP\r
1460: }\r
1461: else\r
1462: {\r
1463: mtCOVERAGE_TEST_MARKER();\r
1464: }\r
1465: }\r
-BFD041C6 0FBE MOVE SP, S8
-BFD041C8 4BE7 LW RA, 28(SP)
-BFD041CA 4BC6 LW S8, 24(SP)
-BFD041CC 4C11 ADDIU SP, SP, 32
-BFD041CE 459F JR16 RA
-BFD041D0 0C00 NOP
+BFD041C6 0FBE MOVE SP, S8\r
+BFD041C8 4BE7 LW RA, 28(SP)\r
+BFD041CA 4BC6 LW S8, 24(SP)\r
+BFD041CC 4C11 ADDIU SP, SP, 32\r
+BFD041CE 459F JR16 RA\r
+BFD041D0 0C00 NOP\r
1466: \r
1467: #endif /* INCLUDE_vTaskSuspend */\r
1468: \r
1472: \r
1473: BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )\r
1474: {\r
-BFD041D4 4FED ADDIU SP, SP, -40
-BFD041D6 CBE9 SW RA, 36(SP)
-BFD041D8 CBC8 SW S8, 32(SP)
-BFD041DA 0FDD MOVE S8, SP
-BFD041DC 0028F89E SW A0, 40(S8)
+BFD041D4 4FED ADDIU SP, SP, -40\r
+BFD041D6 CBE9 SW RA, 36(SP)\r
+BFD041D8 CBC8 SW S8, 32(SP)\r
+BFD041DA 0FDD MOVE S8, SP\r
+BFD041DC 0028F89E SW A0, 40(S8)\r
1475: BaseType_t xYieldRequired = pdFALSE;\r
-BFD041E0 0010F81E SW ZERO, 16(S8)
+BFD041E0 0010F81E SW ZERO, 16(S8)\r
1476: TCB_t * const pxTCB = ( TCB_t * ) xTaskToResume;\r
-BFD041E4 0028FC5E LW V0, 40(S8)
-BFD041E8 0014F85E SW V0, 20(S8)
+BFD041E4 0028FC5E LW V0, 40(S8)\r
+BFD041E8 0014F85E SW V0, 20(S8)\r
1477: UBaseType_t uxSavedInterruptStatus;\r
1478: \r
1479: configASSERT( xTaskToResume );\r
-BFD041EC 0028FC5E LW V0, 40(S8)
-BFD041F0 000940A2 BNEZC V0, 0xBFD04206
-BFD041F4 BFD141A2 LUI V0, 0xBFD1
-BFD041F6 3082BFD1 LDC1 F30, 12418(S1)
-BFD041F8 98103082 ADDIU A0, V0, -26608
-BFD041FA 30A09810 SWC1 F0, 12448(S0)
-BFD041FC 05C730A0 ADDIU A1, ZERO, 1479
-BFD041FE 05C7 SUBU V1, V1, A0
-BFD04200 4B7E77E8 JALS vAssertCalled
-BFD04202 4B7E LW K1, 120(SP)
-BFD04204 0C00 NOP
+BFD041EC 0028FC5E LW V0, 40(S8)\r
+BFD041F0 000940A2 BNEZC V0, 0xBFD04206\r
+BFD041F4 BFD141A2 LUI V0, 0xBFD1\r
+BFD041F6 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD041F8 98103082 ADDIU A0, V0, -26608\r
+BFD041FA 30A09810 SWC1 F0, 12448(S0)\r
+BFD041FC 05C730A0 ADDIU A1, ZERO, 1479\r
+BFD041FE 05C7 SUBU V1, V1, A0\r
+BFD04200 4B7E77E8 JALS vAssertCalled\r
+BFD04202 4B7E LW K1, 120(SP)\r
+BFD04204 0C00 NOP\r
1480: \r
1481: /* RTOS ports that support interrupt nesting have the concept of a\r
1482: maximum system call (or maximum API call) interrupt priority.\r
1497: portASSERT_IF_INTERRUPT_PRIORITY_INVALID();\r
1498: \r
1499: uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r
-BFD04206 475E77E8 JALS uxPortSetInterruptMaskFromISR
-BFD0420A 0C00 NOP
-BFD0420C 0018F85E SW V0, 24(S8)
+BFD04206 475E77E8 JALS uxPortSetInterruptMaskFromISR\r
+BFD0420A 0C00 NOP\r
+BFD0420C 0018F85E SW V0, 24(S8)\r
1500: {\r
1501: if( prvTaskIsTaskSuspended( pxTCB ) == pdTRUE )\r
-BFD04210 0014FC9E LW A0, 20(S8)
-BFD04214 336E77E8 JALS prvTaskIsTaskSuspended
-BFD04216 0C00336E ADDIU K1, T6, 3072
-BFD04218 0C00 NOP
-BFD0421A 0C62 MOVE V1, V0
-BFD0421C ED01 LI V0, 1
-BFD0421E 0044B443 BNE V1, V0, 0xBFD042AA
-BFD04220 0C000044 SLL V0, A0, 1
-BFD04222 0C00 NOP
+BFD04210 0014FC9E LW A0, 20(S8)\r
+BFD04214 336E77E8 JALS prvTaskIsTaskSuspended\r
+BFD04216 0C00336E ADDIU K1, T6, 3072\r
+BFD04218 0C00 NOP\r
+BFD0421A 0C62 MOVE V1, V0\r
+BFD0421C ED01 LI V0, 1\r
+BFD0421E 0044B443 BNE V1, V0, 0xBFD042AA\r
+BFD04220 0C000044 SLL V0, A0, 1\r
+BFD04222 0C00 NOP\r
1502: {\r
1503: traceTASK_RESUME_FROM_ISR( pxTCB );\r
1504: \r
1505: /* Check the ready lists can be accessed. */\r
1506: if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\r
-BFD04224 805CFC5C LW V0, -32676(GP)
-BFD04228 003440A2 BNEZC V0, 0xBFD04294
+BFD04224 805CFC5C LW V0, -32676(GP)\r
+BFD04228 003440A2 BNEZC V0, 0xBFD04294\r
1507: {\r
1508: /* Ready lists can be accessed so move the task from the\r
1509: suspended list to the ready list directly. */\r
1510: if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )\r
-BFD0422C 0014FC5E LW V0, 20(S8)
-BFD04230 69AB LW V1, 44(V0)
-BFD04232 8030FC5C LW V0, -32720(GP)
-BFD04236 692B LW V0, 44(V0)
-BFD04238 13900043 SLTU V0, V1, V0
-BFD0423A 40A21390 ADDI GP, S0, 16546
-BFD0423C 000340A2 BNEZC V0, 0xBFD04246
+BFD0422C 0014FC5E LW V0, 20(S8)\r
+BFD04230 69AB LW V1, 44(V0)\r
+BFD04232 8030FC5C LW V0, -32720(GP)\r
+BFD04236 692B LW V0, 44(V0)\r
+BFD04238 13900043 SLTU V0, V1, V0\r
+BFD0423A 40A21390 ADDI GP, S0, 16546\r
+BFD0423C 000340A2 BNEZC V0, 0xBFD04246\r
1511: {\r
1512: xYieldRequired = pdTRUE;\r
-BFD04240 ED01 LI V0, 1
-BFD04242 0010F85E SW V0, 16(S8)
+BFD04240 ED01 LI V0, 1\r
+BFD04242 0010F85E SW V0, 16(S8)\r
1513: }\r
1514: else\r
1515: {\r
1517: }\r
1518: \r
1519: ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );\r
-BFD04246 0014FC5E LW V0, 20(S8)
-BFD0424A 6D22 ADDIU V0, V0, 4
-BFD0424C 0C82 MOVE A0, V0
-BFD0424E 00C877E8 JALS uxListRemove
-BFD04250 0C0000C8 SLL A2, T0, 1
-BFD04252 0C00 NOP
+BFD04246 0014FC5E LW V0, 20(S8)\r
+BFD0424A 6D22 ADDIU V0, V0, 4\r
+BFD0424C 0C82 MOVE A0, V0\r
+BFD0424E 00C877E8 JALS uxListRemove\r
+BFD04250 0C0000C8 SLL A2, T0, 1\r
+BFD04252 0C00 NOP\r
1520: prvAddTaskToReadyList( pxTCB );\r
-BFD04254 0014FC5E LW V0, 20(S8)
-BFD04258 692B LW V0, 44(V0)
-BFD0425A ED81 LI V1, 1
-BFD0425C 18100062 SLLV V1, V0, V1
-BFD0425E FC5C1810 SB ZERO, -932(S0)
-BFD04260 8040FC5C LW V0, -32704(GP)
-BFD04264 44D3 OR16 V0, V1
-BFD04266 8040F85C SW V0, -32704(GP)
-BFD0426A 0014FC5E LW V0, 20(S8)
-BFD0426E 692B LW V0, 44(V0)
-BFD04270 2524 SLL V0, V0, 2
-BFD04272 25A4 SLL V1, V0, 2
-BFD04274 05B4 ADDU V1, V0, V1
-BFD04276 BFD241A2 LUI V0, 0xBFD2
-BFD04278 3042BFD2 LDC1 F30, 12354(S2)
-BFD0427A 806C3042 ADDIU V0, V0, -32660
-BFD0427E 05A6 ADDU V1, V1, V0
-BFD04280 0014FC5E LW V0, 20(S8)
-BFD04284 6D22 ADDIU V0, V0, 4
-BFD04286 0C83 MOVE A0, V1
-BFD04288 0CA2 MOVE A1, V0
-BFD0428A 3E4A77E8 JALS vListInsertEnd
-BFD0428C 0C003E4A LH S2, 3072(T2)
-BFD0428E 0C00 NOP
-BFD04290 CC0C B 0xBFD042AA
-BFD04292 0C00 NOP
+BFD04254 0014FC5E LW V0, 20(S8)\r
+BFD04258 692B LW V0, 44(V0)\r
+BFD0425A ED81 LI V1, 1\r
+BFD0425C 18100062 SLLV V1, V0, V1\r
+BFD0425E FC5C1810 SB ZERO, -932(S0)\r
+BFD04260 8040FC5C LW V0, -32704(GP)\r
+BFD04264 44D3 OR16 V0, V1\r
+BFD04266 8040F85C SW V0, -32704(GP)\r
+BFD0426A 0014FC5E LW V0, 20(S8)\r
+BFD0426E 692B LW V0, 44(V0)\r
+BFD04270 2524 SLL V0, V0, 2\r
+BFD04272 25A4 SLL V1, V0, 2\r
+BFD04274 05B4 ADDU V1, V0, V1\r
+BFD04276 BFD241A2 LUI V0, 0xBFD2\r
+BFD04278 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD0427A 806C3042 ADDIU V0, V0, -32660\r
+BFD0427E 05A6 ADDU V1, V1, V0\r
+BFD04280 0014FC5E LW V0, 20(S8)\r
+BFD04284 6D22 ADDIU V0, V0, 4\r
+BFD04286 0C83 MOVE A0, V1\r
+BFD04288 0CA2 MOVE A1, V0\r
+BFD0428A 3E4A77E8 JALS vListInsertEnd\r
+BFD0428C 0C003E4A LH S2, 3072(T2)\r
+BFD0428E 0C00 NOP\r
+BFD04290 CC0C B 0xBFD042AA\r
+BFD04292 0C00 NOP\r
1521: }\r
1522: else\r
1523: {\r
1525: is held in the pending ready list until the scheduler is\r
1526: unsuspended. */\r
1527: vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );\r
-BFD04294 0014FC5E LW V0, 20(S8)
-BFD04296 6D2C0014 EXT ZERO, S4, 20, 14
-BFD04298 6D2C ADDIU V0, V0, 24
-BFD0429A BFD241A3 LUI V1, 0xBFD2
-BFD0429C 3083BFD2 LDC1 F30, 12419(S2)
-BFD0429E 80D03083 ADDIU A0, V1, -32560
-BFD042A2 0CA2 MOVE A1, V0
-BFD042A4 3E4A77E8 JALS vListInsertEnd
-BFD042A6 0C003E4A LH S2, 3072(T2)
-BFD042A8 0C00 NOP
+BFD04294 0014FC5E LW V0, 20(S8)\r
+BFD04296 6D2C0014 EXT ZERO, S4, 20, 14\r
+BFD04298 6D2C ADDIU V0, V0, 24\r
+BFD0429A BFD241A3 LUI V1, 0xBFD2\r
+BFD0429C 3083BFD2 LDC1 F30, 12419(S2)\r
+BFD0429E 80D03083 ADDIU A0, V1, -32560\r
+BFD042A2 0CA2 MOVE A1, V0\r
+BFD042A4 3E4A77E8 JALS vListInsertEnd\r
+BFD042A6 0C003E4A LH S2, 3072(T2)\r
+BFD042A8 0C00 NOP\r
1528: }\r
1529: }\r
1530: else\r
1533: }\r
1534: }\r
1535: portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r
-BFD042AA 0018FC9E LW A0, 24(S8)
-BFD042AE 4D5E77E8 JALS vPortClearInterruptMaskFromISR
-BFD042B0 4D5E ADDIU T2, T2, -1
-BFD042B2 0C00 NOP
+BFD042AA 0018FC9E LW A0, 24(S8)\r
+BFD042AE 4D5E77E8 JALS vPortClearInterruptMaskFromISR\r
+BFD042B0 4D5E ADDIU T2, T2, -1\r
+BFD042B2 0C00 NOP\r
1536: \r
1537: return xYieldRequired;\r
-BFD042B4 0010FC5E LW V0, 16(S8)
+BFD042B4 0010FC5E LW V0, 16(S8)\r
1538: }\r
-BFD042B8 0FBE MOVE SP, S8
-BFD042BA 4BE9 LW RA, 36(SP)
-BFD042BC 4BC8 LW S8, 32(SP)
-BFD042BE 4C15 ADDIU SP, SP, 40
-BFD042C0 459F JR16 RA
-BFD042C2 0C00 NOP
+BFD042B8 0FBE MOVE SP, S8\r
+BFD042BA 4BE9 LW RA, 36(SP)\r
+BFD042BC 4BC8 LW S8, 32(SP)\r
+BFD042BE 4C15 ADDIU SP, SP, 40\r
+BFD042C0 459F JR16 RA\r
+BFD042C2 0C00 NOP\r
1539: \r
1540: #endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */\r
1541: /*-----------------------------------------------------------*/\r
1542: \r
1543: void vTaskStartScheduler( void )\r
1544: {\r
-BFD04AC0 4FE9 ADDIU SP, SP, -48
-BFD04AC2 CBEB SW RA, 44(SP)
-BFD04AC4 CBCA SW S8, 40(SP)
-BFD04AC6 0FDD MOVE S8, SP
+BFD04AC0 4FE9 ADDIU SP, SP, -48\r
+BFD04AC2 CBEB SW RA, 44(SP)\r
+BFD04AC4 CBCA SW S8, 40(SP)\r
+BFD04AC6 0FDD MOVE S8, SP\r
1545: BaseType_t xReturn;\r
1546: \r
1547: /* Add the idle task at the lowest priority. */\r
1555: {\r
1556: /* Create the idle task without storing its handle. */\r
1557: xReturn = xTaskCreate( prvIdleTask, "IDLE", tskIDLE_STACK_SIZE, ( void * ) NULL, ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), NULL ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */\r
-BFD04AC8 C804 SW ZERO, 16(SP)
-BFD04ACA C805 SW ZERO, 20(SP)
-BFD04ACC C806 SW ZERO, 24(SP)
-BFD04ACE C807 SW ZERO, 28(SP)
-BFD04AD0 BFD141A2 LUI V0, 0xBFD1
-BFD04AD2 3082BFD1 LDC1 F30, 12418(S1)
-BFD04AD4 8BC53082 ADDIU A0, V0, -29755
-BFD04AD6 8BC5 SB A3, 5(A0)
-BFD04AD8 BFD141A2 LUI V0, 0xBFD1
-BFD04ADA 30A2BFD1 LDC1 F30, 12450(S1)
-BFD04ADC 982830A2 ADDIU A1, V0, -26584
-BFD04ADE 30C09828 SWC1 F1, 12480(T0)
-BFD04AE0 00BE30C0 ADDIU A2, ZERO, 190
-BFD04AE4 0CE0 MOVE A3, ZERO
-BFD04AE6 0A9A77E8 JALS xTaskGenericCreate
-BFD04AE8 0A9A LBU A1, 10(S1)
-BFD04AEA 0C00 NOP
-BFD04AEC 0020F85E SW V0, 32(S8)
+BFD04AC8 C804 SW ZERO, 16(SP)\r
+BFD04ACA C805 SW ZERO, 20(SP)\r
+BFD04ACC C806 SW ZERO, 24(SP)\r
+BFD04ACE C807 SW ZERO, 28(SP)\r
+BFD04AD0 BFD141A2 LUI V0, 0xBFD1\r
+BFD04AD2 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD04AD4 8BC53082 ADDIU A0, V0, -29755\r
+BFD04AD6 8BC5 SB A3, 5(A0)\r
+BFD04AD8 BFD141A2 LUI V0, 0xBFD1\r
+BFD04ADA 30A2BFD1 LDC1 F30, 12450(S1)\r
+BFD04ADC 982830A2 ADDIU A1, V0, -26584\r
+BFD04ADE 30C09828 SWC1 F1, 12480(T0)\r
+BFD04AE0 00BE30C0 ADDIU A2, ZERO, 190\r
+BFD04AE4 0CE0 MOVE A3, ZERO\r
+BFD04AE6 0A9A77E8 JALS xTaskGenericCreate\r
+BFD04AE8 0A9A LBU A1, 10(S1)\r
+BFD04AEA 0C00 NOP\r
+BFD04AEC 0020F85E SW V0, 32(S8)\r
1558: }\r
1559: #endif /* INCLUDE_xTaskGetIdleTaskHandle */\r
1560: \r
1561: #if ( configUSE_TIMERS == 1 )\r
1562: {\r
1563: if( xReturn == pdPASS )\r
-BFD04AF0 0020FC7E LW V1, 32(S8)
-BFD04AF4 ED01 LI V0, 1
-BFD04AF6 0006B443 BNE V1, V0, 0xBFD04B06
-BFD04AF8 0C000006 SLL ZERO, A2, 1
-BFD04AFA 0C00 NOP
+BFD04AF0 0020FC7E LW V1, 32(S8)\r
+BFD04AF4 ED01 LI V0, 1\r
+BFD04AF6 0006B443 BNE V1, V0, 0xBFD04B06\r
+BFD04AF8 0C000006 SLL ZERO, A2, 1\r
+BFD04AFA 0C00 NOP\r
1564: {\r
1565: xReturn = xTimerCreateTimerTask();\r
-BFD04AFC 3D3677E8 JALS xTimerCreateTimerTask
-BFD04AFE 0C003D36 LH T1, 3072(S6)
-BFD04B00 0C00 NOP
-BFD04B02 0020F85E SW V0, 32(S8)
+BFD04AFC 3D3677E8 JALS xTimerCreateTimerTask\r
+BFD04AFE 0C003D36 LH T1, 3072(S6)\r
+BFD04B00 0C00 NOP\r
+BFD04B02 0020F85E SW V0, 32(S8)\r
1566: }\r
1567: else\r
1568: {\r
1572: #endif /* configUSE_TIMERS */\r
1573: \r
1574: if( xReturn == pdPASS )\r
-BFD04B06 0020FC7E LW V1, 32(S8)
-BFD04B0A ED01 LI V0, 1
-BFD04B0C 0031B443 BNE V1, V0, 0xBFD04B72
-BFD04B0E 0C000031 SLL AT, S1, 1
-BFD04B10 0C00 NOP
+BFD04B06 0020FC7E LW V1, 32(S8)\r
+BFD04B0A ED01 LI V0, 1\r
+BFD04B0C 0031B443 BNE V1, V0, 0xBFD04B72\r
+BFD04B0E 0C000031 SLL AT, S1, 1\r
+BFD04B10 0C00 NOP\r
1575: {\r
1576: /* Interrupts are turned off here, to ensure a tick does not occur\r
1577: before or during the call to xPortStartScheduler(). The stacks of\r
1579: so interrupts will automatically get re-enabled when the first task\r
1580: starts to run. */\r
1581: portDISABLE_INTERRUPTS();\r
-BFD04B12 4E3677E8 JALS ulPortGetCP0Status
-BFD04B14 4E36 ADDIU S1, S1, -5
-BFD04B16 0C00 NOP
-BFD04B18 0024F85E SW V0, 36(S8)
-BFD04B1C 0024FC7E LW V1, 36(S8)
-BFD04B20 000141A2 LUI V0, 0x1
-BFD04B24 FC005042 ORI V0, V0, -1024
-BFD04B26 4493FC00 LW ZERO, 17555(ZERO)
-BFD04B28 4493 AND16 V0, V1
-BFD04B2A 50400042 SRL V0, V0, 10
-BFD04B2C B0425040 ORI V0, ZERO, -20414
-BFD04B2E 0003B042 SLTIU V0, V0, 3
-BFD04B32 001140E2 BEQZC V0, 0xBFD04B58
-BFD04B36 0024FC7E LW V1, 36(S8)
-BFD04B3A FFFE41A2 LUI V0, 0xFFFE
-BFD04B3C 5042FFFE LW RA, 20546(S8)
-BFD04B3E 03FF5042 ORI V0, V0, 1023
-BFD04B42 4493 AND16 V0, V1
-BFD04B44 0024F85E SW V0, 36(S8)
-BFD04B48 0024FC5E LW V0, 36(S8)
-BFD04B4C 0C005042 ORI V0, V0, 3072
-BFD04B4E 0C00 NOP
-BFD04B50 0C82 MOVE A0, V0
-BFD04B52 4E4677E8 JALS vPortSetCP0Status
-BFD04B54 4E46 ADDIU S2, S2, 3
-BFD04B56 0C00 NOP
+BFD04B12 4E3677E8 JALS ulPortGetCP0Status\r
+BFD04B14 4E36 ADDIU S1, S1, -5\r
+BFD04B16 0C00 NOP\r
+BFD04B18 0024F85E SW V0, 36(S8)\r
+BFD04B1C 0024FC7E LW V1, 36(S8)\r
+BFD04B20 000141A2 LUI V0, 0x1\r
+BFD04B24 FC005042 ORI V0, V0, -1024\r
+BFD04B26 4493FC00 LW ZERO, 17555(ZERO)\r
+BFD04B28 4493 AND16 V0, V1\r
+BFD04B2A 50400042 SRL V0, V0, 10\r
+BFD04B2C B0425040 ORI V0, ZERO, -20414\r
+BFD04B2E 0003B042 SLTIU V0, V0, 3\r
+BFD04B32 001140E2 BEQZC V0, 0xBFD04B58\r
+BFD04B36 0024FC7E LW V1, 36(S8)\r
+BFD04B3A FFFE41A2 LUI V0, 0xFFFE\r
+BFD04B3C 5042FFFE LW RA, 20546(S8)\r
+BFD04B3E 03FF5042 ORI V0, V0, 1023\r
+BFD04B42 4493 AND16 V0, V1\r
+BFD04B44 0024F85E SW V0, 36(S8)\r
+BFD04B48 0024FC5E LW V0, 36(S8)\r
+BFD04B4C 0C005042 ORI V0, V0, 3072\r
+BFD04B4E 0C00 NOP\r
+BFD04B50 0C82 MOVE A0, V0\r
+BFD04B52 4E4677E8 JALS vPortSetCP0Status\r
+BFD04B54 4E46 ADDIU S2, S2, 3\r
+BFD04B56 0C00 NOP\r
1582: \r
1583: #if ( configUSE_NEWLIB_REENTRANT == 1 )\r
1584: {\r
1589: #endif /* configUSE_NEWLIB_REENTRANT */\r
1590: \r
1591: xNextTaskUnblockTime = portMAX_DELAY;\r
-BFD04B58 ED7F LI V0, -1
-BFD04B5A 8058F85C SW V0, -32680(GP)
+BFD04B58 ED7F LI V0, -1\r
+BFD04B5A 8058F85C SW V0, -32680(GP)\r
1592: xSchedulerRunning = pdTRUE;\r
-BFD04B5E ED01 LI V0, 1
-BFD04B60 8044F85C SW V0, -32700(GP)
+BFD04B5E ED01 LI V0, 1\r
+BFD04B60 8044F85C SW V0, -32700(GP)\r
1593: xTickCount = ( TickType_t ) 0U;\r
-BFD04B64 803CF81C SW ZERO, -32708(GP)
+BFD04B64 803CF81C SW ZERO, -32708(GP)\r
1594: \r
1595: /* If configGENERATE_RUN_TIME_STATS is defined then the following\r
1596: macro must be defined to configure the timer/counter used to generate\r
1600: /* Setting up the timer tick is hardware specific and thus in the\r
1601: portable interface. */\r
1602: if( xPortStartScheduler() != pdFALSE )\r
-BFD04B68 344C77E8 JALS xPortStartScheduler
-BFD04B6A 0C00344C LHU V0, 3072(T4)
-BFD04B6C 0C00 NOP
-BFD04B6E CC0E B 0xBFD04B8C
-BFD04B70 0C00 NOP
+BFD04B68 344C77E8 JALS xPortStartScheduler\r
+BFD04B6A 0C00344C LHU V0, 3072(T4)\r
+BFD04B6C 0C00 NOP\r
+BFD04B6E CC0E B 0xBFD04B8C\r
+BFD04B70 0C00 NOP\r
1603: {\r
1604: /* Should not reach here as if the scheduler is running the\r
1605: function will not return. */\r
1615: because there was not enough FreeRTOS heap to create the idle task\r
1616: or the timer task. */\r
1617: configASSERT( xReturn );\r
-BFD04B72 0020FC5E LW V0, 32(S8)
-BFD04B76 000940A2 BNEZC V0, 0xBFD04B8C
-BFD04B7A BFD141A2 LUI V0, 0xBFD1
-BFD04B7C 3082BFD1 LDC1 F30, 12418(S1)
-BFD04B7E 98103082 ADDIU A0, V0, -26608
-BFD04B80 30A09810 SWC1 F0, 12448(S0)
-BFD04B82 065130A0 ADDIU A1, ZERO, 1617
-BFD04B84 0651 SUBU A0, S0, A1
-BFD04B86 4B7E77E8 JALS vAssertCalled
-BFD04B88 4B7E LW K1, 120(SP)
-BFD04B8A 0C00 NOP
+BFD04B72 0020FC5E LW V0, 32(S8)\r
+BFD04B76 000940A2 BNEZC V0, 0xBFD04B8C\r
+BFD04B7A BFD141A2 LUI V0, 0xBFD1\r
+BFD04B7C 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD04B7E 98103082 ADDIU A0, V0, -26608\r
+BFD04B80 30A09810 SWC1 F0, 12448(S0)\r
+BFD04B82 065130A0 ADDIU A1, ZERO, 1617\r
+BFD04B84 0651 SUBU A0, S0, A1\r
+BFD04B86 4B7E77E8 JALS vAssertCalled\r
+BFD04B88 4B7E LW K1, 120(SP)\r
+BFD04B8A 0C00 NOP\r
1618: }\r
1619: }\r
-BFD04B8C 0FBE MOVE SP, S8
-BFD04B8E 4BEB LW RA, 44(SP)
-BFD04B90 4BCA LW S8, 40(SP)
-BFD04B92 4C19 ADDIU SP, SP, 48
-BFD04B94 459F JR16 RA
-BFD04B96 0C00 NOP
+BFD04B8C 0FBE MOVE SP, S8\r
+BFD04B8E 4BEB LW RA, 44(SP)\r
+BFD04B90 4BCA LW S8, 40(SP)\r
+BFD04B92 4C19 ADDIU SP, SP, 48\r
+BFD04B94 459F JR16 RA\r
+BFD04B96 0C00 NOP\r
1620: /*-----------------------------------------------------------*/\r
1621: \r
1622: void vTaskEndScheduler( void )\r
1623: {\r
-BFD07F00 4FF1 ADDIU SP, SP, -32
-BFD07F02 CBE7 SW RA, 28(SP)
-BFD07F04 CBC6 SW S8, 24(SP)
-BFD07F06 0FDD MOVE S8, SP
+BFD07F00 4FF1 ADDIU SP, SP, -32\r
+BFD07F02 CBE7 SW RA, 28(SP)\r
+BFD07F04 CBC6 SW S8, 24(SP)\r
+BFD07F06 0FDD MOVE S8, SP\r
1624: /* Stop the scheduler interrupts and call the portable scheduler end\r
1625: routine so the original ISRs can be restored if necessary. The port\r
1626: layer must ensure interrupts enable bit is left in the correct state. */\r
1627: portDISABLE_INTERRUPTS();\r
-BFD07F08 4E3677E8 JALS ulPortGetCP0Status
-BFD07F0A 4E36 ADDIU S1, S1, -5
-BFD07F0C 0C00 NOP
-BFD07F0E 0010F85E SW V0, 16(S8)
-BFD07F12 0010FC7E LW V1, 16(S8)
-BFD07F16 000141A2 LUI V0, 0x1
-BFD07F1A FC005042 ORI V0, V0, -1024
-BFD07F1C 4493FC00 LW ZERO, 17555(ZERO)
-BFD07F1E 4493 AND16 V0, V1
-BFD07F20 50400042 SRL V0, V0, 10
-BFD07F22 B0425040 ORI V0, ZERO, -20414
-BFD07F24 0003B042 SLTIU V0, V0, 3
-BFD07F28 001140E2 BEQZC V0, 0xBFD07F4E
-BFD07F2C 0010FC7E LW V1, 16(S8)
-BFD07F30 FFFE41A2 LUI V0, 0xFFFE
-BFD07F32 5042FFFE LW RA, 20546(S8)
-BFD07F34 03FF5042 ORI V0, V0, 1023
-BFD07F38 4493 AND16 V0, V1
-BFD07F3A 0010F85E SW V0, 16(S8)
-BFD07F3E 0010FC5E LW V0, 16(S8)
-BFD07F42 0C005042 ORI V0, V0, 3072
-BFD07F44 0C00 NOP
-BFD07F46 0C82 MOVE A0, V0
-BFD07F48 4E4677E8 JALS vPortSetCP0Status
-BFD07F4A 4E46 ADDIU S2, S2, 3
-BFD07F4C 0C00 NOP
+BFD07F08 4E3677E8 JALS ulPortGetCP0Status\r
+BFD07F0A 4E36 ADDIU S1, S1, -5\r
+BFD07F0C 0C00 NOP\r
+BFD07F0E 0010F85E SW V0, 16(S8)\r
+BFD07F12 0010FC7E LW V1, 16(S8)\r
+BFD07F16 000141A2 LUI V0, 0x1\r
+BFD07F1A FC005042 ORI V0, V0, -1024\r
+BFD07F1C 4493FC00 LW ZERO, 17555(ZERO)\r
+BFD07F1E 4493 AND16 V0, V1\r
+BFD07F20 50400042 SRL V0, V0, 10\r
+BFD07F22 B0425040 ORI V0, ZERO, -20414\r
+BFD07F24 0003B042 SLTIU V0, V0, 3\r
+BFD07F28 001140E2 BEQZC V0, 0xBFD07F4E\r
+BFD07F2C 0010FC7E LW V1, 16(S8)\r
+BFD07F30 FFFE41A2 LUI V0, 0xFFFE\r
+BFD07F32 5042FFFE LW RA, 20546(S8)\r
+BFD07F34 03FF5042 ORI V0, V0, 1023\r
+BFD07F38 4493 AND16 V0, V1\r
+BFD07F3A 0010F85E SW V0, 16(S8)\r
+BFD07F3E 0010FC5E LW V0, 16(S8)\r
+BFD07F42 0C005042 ORI V0, V0, 3072\r
+BFD07F44 0C00 NOP\r
+BFD07F46 0C82 MOVE A0, V0\r
+BFD07F48 4E4677E8 JALS vPortSetCP0Status\r
+BFD07F4A 4E46 ADDIU S2, S2, 3\r
+BFD07F4C 0C00 NOP\r
1628: xSchedulerRunning = pdFALSE;\r
-BFD07F4E 8044F81C SW ZERO, -32700(GP)
+BFD07F4E 8044F81C SW ZERO, -32700(GP)\r
1629: vPortEndScheduler();\r
-BFD07F52 4BD477E8 JALS vPortEndScheduler
-BFD07F54 4BD4 LW S8, 80(SP)
-BFD07F56 0C00 NOP
+BFD07F52 4BD477E8 JALS vPortEndScheduler\r
+BFD07F54 4BD4 LW S8, 80(SP)\r
+BFD07F56 0C00 NOP\r
1630: }\r
-BFD07F58 0FBE MOVE SP, S8
-BFD07F5A 4BE7 LW RA, 28(SP)
-BFD07F5C 4BC6 LW S8, 24(SP)
-BFD07F5E 4C11 ADDIU SP, SP, 32
-BFD07F60 459F JR16 RA
-BFD07F62 0C00 NOP
+BFD07F58 0FBE MOVE SP, S8\r
+BFD07F5A 4BE7 LW RA, 28(SP)\r
+BFD07F5C 4BC6 LW S8, 24(SP)\r
+BFD07F5E 4C11 ADDIU SP, SP, 32\r
+BFD07F60 459F JR16 RA\r
+BFD07F62 0C00 NOP\r
1631: /*----------------------------------------------------------*/\r
1632: \r
1633: void vTaskSuspendAll( void )\r
1634: {\r
-BFD09DE8 4FB0 ADDIU SP, SP, -8
-BFD09DEA CBC1 SW S8, 4(SP)
-BFD09DEC 0FDD MOVE S8, SP
+BFD09DE8 4FB0 ADDIU SP, SP, -8\r
+BFD09DEA CBC1 SW S8, 4(SP)\r
+BFD09DEC 0FDD MOVE S8, SP\r
1635: /* A critical section is not required as the variable is of type\r
1636: BaseType_t. Please read Richard Barry's reply in the following link to a\r
1637: post in the FreeRTOS support forum before reporting this as a bug! -\r
1638: http://goo.gl/wu4acr */\r
1639: ++uxSchedulerSuspended;\r
-BFD09DEE 805CFC5C LW V0, -32676(GP)
-BFD09DF2 6D20 ADDIU V0, V0, 1
-BFD09DF4 805CF85C SW V0, -32676(GP)
+BFD09DEE 805CFC5C LW V0, -32676(GP)\r
+BFD09DF2 6D20 ADDIU V0, V0, 1\r
+BFD09DF4 805CF85C SW V0, -32676(GP)\r
1640: }\r
-BFD09DF8 0FBE MOVE SP, S8
-BFD09DFA 4BC1 LW S8, 4(SP)
-BFD09DFC 4C05 ADDIU SP, SP, 8
-BFD09DFE 459F JR16 RA
-BFD09E00 0C00 NOP
+BFD09DF8 0FBE MOVE SP, S8\r
+BFD09DFA 4BC1 LW S8, 4(SP)\r
+BFD09DFC 4C05 ADDIU SP, SP, 8\r
+BFD09DFE 459F JR16 RA\r
+BFD09E00 0C00 NOP\r
1641: /*----------------------------------------------------------*/\r
1642: \r
1643: #if ( configUSE_TICKLESS_IDLE != 0 )\r
1670: \r
1671: BaseType_t xTaskResumeAll( void )\r
1672: {\r
-BFD02B1C 4FED ADDIU SP, SP, -40
-BFD02B1E CBE9 SW RA, 36(SP)
-BFD02B20 CBC8 SW S8, 32(SP)
-BFD02B22 0FDD MOVE S8, SP
+BFD02B1C 4FED ADDIU SP, SP, -40\r
+BFD02B1E CBE9 SW RA, 36(SP)\r
+BFD02B20 CBC8 SW S8, 32(SP)\r
+BFD02B22 0FDD MOVE S8, SP\r
1673: TCB_t *pxTCB;\r
1674: BaseType_t xAlreadyYielded = pdFALSE;\r
-BFD02B24 0010F81E SW ZERO, 16(S8)
+BFD02B24 0010F81E SW ZERO, 16(S8)\r
1675: \r
1676: /* If uxSchedulerSuspended is zero then this function does not match a\r
1677: previous call to vTaskSuspendAll(). */\r
1678: configASSERT( uxSchedulerSuspended );\r
-BFD02B28 805CFC5C LW V0, -32676(GP)
-BFD02B2C 000940A2 BNEZC V0, 0xBFD02B42
-BFD02B30 BFD141A2 LUI V0, 0xBFD1
-BFD02B32 3082BFD1 LDC1 F30, 12418(S1)
-BFD02B34 98103082 ADDIU A0, V0, -26608
-BFD02B36 30A09810 SWC1 F0, 12448(S0)
-BFD02B38 068E30A0 ADDIU A1, ZERO, 1678
-BFD02B3A 068E ADDU A1, A3, S0
-BFD02B3C 4B7E77E8 JALS vAssertCalled
-BFD02B3E 4B7E LW K1, 120(SP)
-BFD02B40 0C00 NOP
+BFD02B28 805CFC5C LW V0, -32676(GP)\r
+BFD02B2C 000940A2 BNEZC V0, 0xBFD02B42\r
+BFD02B30 BFD141A2 LUI V0, 0xBFD1\r
+BFD02B32 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD02B34 98103082 ADDIU A0, V0, -26608\r
+BFD02B36 30A09810 SWC1 F0, 12448(S0)\r
+BFD02B38 068E30A0 ADDIU A1, ZERO, 1678\r
+BFD02B3A 068E ADDU A1, A3, S0\r
+BFD02B3C 4B7E77E8 JALS vAssertCalled\r
+BFD02B3E 4B7E LW K1, 120(SP)\r
+BFD02B40 0C00 NOP\r
1679: \r
1680: /* It is possible that an ISR caused a task to be removed from an event\r
1681: list while the scheduler was suspended. If this was the case then the\r
1683: scheduler has been resumed it is safe to move all the pending ready\r
1684: tasks from this list into their appropriate ready list. */\r
1685: taskENTER_CRITICAL();\r
-BFD02B42 33B877E8 JALS vTaskEnterCritical
-BFD02B44 0C0033B8 ADDIU SP, T8, 3072
-BFD02B46 0C00 NOP
+BFD02B42 33B877E8 JALS vTaskEnterCritical\r
+BFD02B44 0C0033B8 ADDIU SP, T8, 3072\r
+BFD02B46 0C00 NOP\r
1686: {\r
1687: --uxSchedulerSuspended;\r
-BFD02B48 805CFC5C LW V0, -32676(GP)
-BFD02B4C 6D2E ADDIU V0, V0, -1
-BFD02B4E 805CF85C SW V0, -32676(GP)
+BFD02B48 805CFC5C LW V0, -32676(GP)\r
+BFD02B4C 6D2E ADDIU V0, V0, -1\r
+BFD02B4E 805CF85C SW V0, -32676(GP)\r
1688: \r
1689: if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\r
-BFD02B52 805CFC5C LW V0, -32676(GP)
-BFD02B56 007D40A2 BNEZC V0, 0xBFD02C54
+BFD02B52 805CFC5C LW V0, -32676(GP)\r
+BFD02B56 007D40A2 BNEZC V0, 0xBFD02C54\r
1690: {\r
1691: if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )\r
-BFD02B5A 8038FC5C LW V0, -32712(GP)
-BFD02B5E 007940E2 BEQZC V0, 0xBFD02C54
+BFD02B5A 8038FC5C LW V0, -32712(GP)\r
+BFD02B5E 007940E2 BEQZC V0, 0xBFD02C54\r
1692: {\r
1693: /* Move any readied tasks from the pending list into the\r
1694: appropriate ready list. */\r
1695: while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )\r
-BFD02B62 CC42 B 0xBFD02BE8
-BFD02B64 0C00 NOP
-BFD02BE8 BFD241A2 LUI V0, 0xBFD2
-BFD02BEA FC42BFD2 LDC1 F30, -958(S2)
-BFD02BEC 80D0FC42 LW V0, -32560(V0)
-BFD02BF0 FFB940A2 BNEZC V0, 0xBFD02B66
-BFD02BF2 FC5CFFB9 LW SP, -932(T9)
+BFD02B62 CC42 B 0xBFD02BE8\r
+BFD02B64 0C00 NOP\r
+BFD02BE8 BFD241A2 LUI V0, 0xBFD2\r
+BFD02BEA FC42BFD2 LDC1 F30, -958(S2)\r
+BFD02BEC 80D0FC42 LW V0, -32560(V0)\r
+BFD02BF0 FFB940A2 BNEZC V0, 0xBFD02B66\r
+BFD02BF2 FC5CFFB9 LW SP, -932(T9)\r
1696: {\r
1697: pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) );\r
-BFD02B66 BFD241A2 LUI V0, 0xBFD2
-BFD02B68 3042BFD2 LDC1 F30, 12354(S2)
-BFD02B6A 80D03042 ADDIU V0, V0, -32560
-BFD02B6E 6923 LW V0, 12(V0)
-BFD02B70 6923 LW V0, 12(V0)
-BFD02B72 0014F85E SW V0, 20(S8)
+BFD02B66 BFD241A2 LUI V0, 0xBFD2\r
+BFD02B68 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD02B6A 80D03042 ADDIU V0, V0, -32560\r
+BFD02B6E 6923 LW V0, 12(V0)\r
+BFD02B70 6923 LW V0, 12(V0)\r
+BFD02B72 0014F85E SW V0, 20(S8)\r
1698: ( void ) uxListRemove( &( pxTCB->xEventListItem ) );\r
-BFD02B76 0014FC5E LW V0, 20(S8)
-BFD02B78 6D2C0014 EXT ZERO, S4, 20, 14
-BFD02B7A 6D2C ADDIU V0, V0, 24
-BFD02B7C 0C82 MOVE A0, V0
-BFD02B7E 00C877E8 JALS uxListRemove
-BFD02B80 0C0000C8 SLL A2, T0, 1
-BFD02B82 0C00 NOP
+BFD02B76 0014FC5E LW V0, 20(S8)\r
+BFD02B78 6D2C0014 EXT ZERO, S4, 20, 14\r
+BFD02B7A 6D2C ADDIU V0, V0, 24\r
+BFD02B7C 0C82 MOVE A0, V0\r
+BFD02B7E 00C877E8 JALS uxListRemove\r
+BFD02B80 0C0000C8 SLL A2, T0, 1\r
+BFD02B82 0C00 NOP\r
1699: ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );\r
-BFD02B84 0014FC5E LW V0, 20(S8)
-BFD02B88 6D22 ADDIU V0, V0, 4
-BFD02B8A 0C82 MOVE A0, V0
-BFD02B8C 00C877E8 JALS uxListRemove
-BFD02B8E 0C0000C8 SLL A2, T0, 1
-BFD02B90 0C00 NOP
+BFD02B84 0014FC5E LW V0, 20(S8)\r
+BFD02B88 6D22 ADDIU V0, V0, 4\r
+BFD02B8A 0C82 MOVE A0, V0\r
+BFD02B8C 00C877E8 JALS uxListRemove\r
+BFD02B8E 0C0000C8 SLL A2, T0, 1\r
+BFD02B90 0C00 NOP\r
1700: prvAddTaskToReadyList( pxTCB );\r
-BFD02B92 0014FC5E LW V0, 20(S8)
-BFD02B96 692B LW V0, 44(V0)
-BFD02B98 ED81 LI V1, 1
-BFD02B9A 18100062 SLLV V1, V0, V1
-BFD02B9C FC5C1810 SB ZERO, -932(S0)
-BFD02B9E 8040FC5C LW V0, -32704(GP)
-BFD02BA2 44D3 OR16 V0, V1
-BFD02BA4 8040F85C SW V0, -32704(GP)
-BFD02BA8 0014FC5E LW V0, 20(S8)
-BFD02BAC 692B LW V0, 44(V0)
-BFD02BAE 2524 SLL V0, V0, 2
-BFD02BB0 25A4 SLL V1, V0, 2
-BFD02BB2 05B4 ADDU V1, V0, V1
-BFD02BB4 BFD241A2 LUI V0, 0xBFD2
-BFD02BB6 3042BFD2 LDC1 F30, 12354(S2)
-BFD02BB8 806C3042 ADDIU V0, V0, -32660
-BFD02BBC 05A6 ADDU V1, V1, V0
-BFD02BBE 0014FC5E LW V0, 20(S8)
-BFD02BC2 6D22 ADDIU V0, V0, 4
-BFD02BC4 0C83 MOVE A0, V1
-BFD02BC6 0CA2 MOVE A1, V0
-BFD02BC8 3E4A77E8 JALS vListInsertEnd
-BFD02BCA 0C003E4A LH S2, 3072(T2)
-BFD02BCC 0C00 NOP
+BFD02B92 0014FC5E LW V0, 20(S8)\r
+BFD02B96 692B LW V0, 44(V0)\r
+BFD02B98 ED81 LI V1, 1\r
+BFD02B9A 18100062 SLLV V1, V0, V1\r
+BFD02B9C FC5C1810 SB ZERO, -932(S0)\r
+BFD02B9E 8040FC5C LW V0, -32704(GP)\r
+BFD02BA2 44D3 OR16 V0, V1\r
+BFD02BA4 8040F85C SW V0, -32704(GP)\r
+BFD02BA8 0014FC5E LW V0, 20(S8)\r
+BFD02BAC 692B LW V0, 44(V0)\r
+BFD02BAE 2524 SLL V0, V0, 2\r
+BFD02BB0 25A4 SLL V1, V0, 2\r
+BFD02BB2 05B4 ADDU V1, V0, V1\r
+BFD02BB4 BFD241A2 LUI V0, 0xBFD2\r
+BFD02BB6 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD02BB8 806C3042 ADDIU V0, V0, -32660\r
+BFD02BBC 05A6 ADDU V1, V1, V0\r
+BFD02BBE 0014FC5E LW V0, 20(S8)\r
+BFD02BC2 6D22 ADDIU V0, V0, 4\r
+BFD02BC4 0C83 MOVE A0, V1\r
+BFD02BC6 0CA2 MOVE A1, V0\r
+BFD02BC8 3E4A77E8 JALS vListInsertEnd\r
+BFD02BCA 0C003E4A LH S2, 3072(T2)\r
+BFD02BCC 0C00 NOP\r
1701: \r
1702: /* If the moved task has a priority higher than the current\r
1703: task then a yield must be performed. */\r
1704: if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )\r
-BFD02BCE 0014FC5E LW V0, 20(S8)
-BFD02BD2 69AB LW V1, 44(V0)
-BFD02BD4 8030FC5C LW V0, -32720(GP)
-BFD02BD8 692B LW V0, 44(V0)
-BFD02BDA 13900043 SLTU V0, V1, V0
-BFD02BDC 40A21390 ADDI GP, S0, 16546
-BFD02BDE 000340A2 BNEZC V0, 0xBFD02BE8
+BFD02BCE 0014FC5E LW V0, 20(S8)\r
+BFD02BD2 69AB LW V1, 44(V0)\r
+BFD02BD4 8030FC5C LW V0, -32720(GP)\r
+BFD02BD8 692B LW V0, 44(V0)\r
+BFD02BDA 13900043 SLTU V0, V1, V0\r
+BFD02BDC 40A21390 ADDI GP, S0, 16546\r
+BFD02BDE 000340A2 BNEZC V0, 0xBFD02BE8\r
1705: {\r
1706: xYieldPending = pdTRUE;\r
-BFD02BE2 ED01 LI V0, 1
-BFD02BE4 804CF85C SW V0, -32692(GP)
+BFD02BE2 ED01 LI V0, 1\r
+BFD02BE4 804CF85C SW V0, -32692(GP)\r
1707: }\r
1708: else\r
1709: {\r
1716: not slip, and that any delayed tasks are resumed at the correct\r
1717: time. */\r
1718: if( uxPendedTicks > ( UBaseType_t ) 0U )\r
-BFD02BF4 8048FC5C LW V0, -32696(GP)
-BFD02BF8 001340E2 BEQZC V0, 0xBFD02C22
+BFD02BF4 8048FC5C LW V0, -32696(GP)\r
+BFD02BF8 001340E2 BEQZC V0, 0xBFD02C22\r
1719: {\r
1720: while( uxPendedTicks > ( UBaseType_t ) 0U )\r
-BFD02BFC CC0E B 0xBFD02C1A
-BFD02BFE 0C00 NOP
-BFD02C1A 8048FC5C LW V0, -32696(GP)
-BFD02C1E FFEF40A2 BNEZC V0, 0xBFD02C00
-BFD02C20 FC7CFFEF LW RA, -900(T7)
+BFD02BFC CC0E B 0xBFD02C1A\r
+BFD02BFE 0C00 NOP\r
+BFD02C1A 8048FC5C LW V0, -32696(GP)\r
+BFD02C1E FFEF40A2 BNEZC V0, 0xBFD02C00\r
+BFD02C20 FC7CFFEF LW RA, -900(T7)\r
1721: {\r
1722: if( xTaskIncrementTick() != pdFALSE )\r
-BFD02C00 104077E8 JALS xTaskIncrementTick
-BFD02C02 0C001040 ADDI V0, ZERO, 3072
-BFD02C04 0C00 NOP
-BFD02C06 000340E2 BEQZC V0, 0xBFD02C10
+BFD02C00 104077E8 JALS xTaskIncrementTick\r
+BFD02C02 0C001040 ADDI V0, ZERO, 3072\r
+BFD02C04 0C00 NOP\r
+BFD02C06 000340E2 BEQZC V0, 0xBFD02C10\r
1723: {\r
1724: xYieldPending = pdTRUE;\r
-BFD02C0A ED01 LI V0, 1
-BFD02C0C 804CF85C SW V0, -32692(GP)
+BFD02C0A ED01 LI V0, 1\r
+BFD02C0C 804CF85C SW V0, -32692(GP)\r
1725: }\r
1726: else\r
1727: {\r
1728: mtCOVERAGE_TEST_MARKER();\r
1729: }\r
1730: --uxPendedTicks;\r
-BFD02C10 8048FC5C LW V0, -32696(GP)
-BFD02C14 6D2E ADDIU V0, V0, -1
-BFD02C16 8048F85C SW V0, -32696(GP)
+BFD02C10 8048FC5C LW V0, -32696(GP)\r
+BFD02C14 6D2E ADDIU V0, V0, -1\r
+BFD02C16 8048F85C SW V0, -32696(GP)\r
1731: }\r
1732: }\r
1733: else\r
1736: }\r
1737: \r
1738: if( xYieldPending == pdTRUE )\r
-BFD02C22 804CFC7C LW V1, -32692(GP)
-BFD02C26 ED01 LI V0, 1
-BFD02C28 0014B443 BNE V1, V0, 0xBFD02C54
-BFD02C2A 0C000014 SLL ZERO, S4, 1
-BFD02C2C 0C00 NOP
+BFD02C22 804CFC7C LW V1, -32692(GP)\r
+BFD02C26 ED01 LI V0, 1\r
+BFD02C28 0014B443 BNE V1, V0, 0xBFD02C54\r
+BFD02C2A 0C000014 SLL ZERO, S4, 1\r
+BFD02C2C 0C00 NOP\r
1739: {\r
1740: #if( configUSE_PREEMPTION != 0 )\r
1741: {\r
1742: xAlreadyYielded = pdTRUE;\r
-BFD02C2E ED01 LI V0, 1
-BFD02C30 0010F85E SW V0, 16(S8)
+BFD02C2E ED01 LI V0, 1\r
+BFD02C30 0010F85E SW V0, 16(S8)\r
1743: }\r
1744: #endif\r
1745: taskYIELD_IF_USING_PREEMPTION();\r
-BFD02C34 4E5677E8 JALS ulPortGetCP0Cause
-BFD02C36 4E56 ADDIU S2, S2, -5
-BFD02C38 0C00 NOP
-BFD02C3A 0018F85E SW V0, 24(S8)
-BFD02C3E 0018FC5E LW V0, 24(S8)
-BFD02C42 01005042 ORI V0, V0, 256
-BFD02C46 0018F85E SW V0, 24(S8)
-BFD02C4A 0018FC9E LW A0, 24(S8)
-BFD02C4E 4E6677E8 JALS vPortSetCP0Cause
-BFD02C50 4E66 ADDIU S3, S3, 3
-BFD02C52 0C00 NOP
+BFD02C34 4E5677E8 JALS ulPortGetCP0Cause\r
+BFD02C36 4E56 ADDIU S2, S2, -5\r
+BFD02C38 0C00 NOP\r
+BFD02C3A 0018F85E SW V0, 24(S8)\r
+BFD02C3E 0018FC5E LW V0, 24(S8)\r
+BFD02C42 01005042 ORI V0, V0, 256\r
+BFD02C46 0018F85E SW V0, 24(S8)\r
+BFD02C4A 0018FC9E LW A0, 24(S8)\r
+BFD02C4E 4E6677E8 JALS vPortSetCP0Cause\r
+BFD02C50 4E66 ADDIU S3, S3, 3\r
+BFD02C52 0C00 NOP\r
1746: }\r
1747: else\r
1748: {\r
1756: }\r
1757: }\r
1758: taskEXIT_CRITICAL();\r
-BFD02C54 40AA77E8 JALS vTaskExitCritical
-BFD02C56 0C0040AA BNEZC T2, 0xBFD0445A
-BFD02C58 0C00 NOP
+BFD02C54 40AA77E8 JALS vTaskExitCritical\r
+BFD02C56 0C0040AA BNEZC T2, 0xBFD0445A\r
+BFD02C58 0C00 NOP\r
1759: \r
1760: return xAlreadyYielded;\r
-BFD02C5A 0010FC5E LW V0, 16(S8)
+BFD02C5A 0010FC5E LW V0, 16(S8)\r
1761: }\r
-BFD02C5E 0FBE MOVE SP, S8
-BFD02C60 4BE9 LW RA, 36(SP)
-BFD02C62 4BC8 LW S8, 32(SP)
-BFD02C64 4C15 ADDIU SP, SP, 40
-BFD02C66 459F JR16 RA
-BFD02C68 0C00 NOP
+BFD02C5E 0FBE MOVE SP, S8\r
+BFD02C60 4BE9 LW RA, 36(SP)\r
+BFD02C62 4BC8 LW S8, 32(SP)\r
+BFD02C64 4C15 ADDIU SP, SP, 40\r
+BFD02C66 459F JR16 RA\r
+BFD02C68 0C00 NOP\r
1762: /*-----------------------------------------------------------*/\r
1763: \r
1764: TickType_t xTaskGetTickCount( void )\r
1765: {\r
-BFD09994 4FF1 ADDIU SP, SP, -32
-BFD09996 CBE7 SW RA, 28(SP)
-BFD09998 CBC6 SW S8, 24(SP)
-BFD0999A 0FDD MOVE S8, SP
+BFD09994 4FF1 ADDIU SP, SP, -32\r
+BFD09996 CBE7 SW RA, 28(SP)\r
+BFD09998 CBC6 SW S8, 24(SP)\r
+BFD0999A 0FDD MOVE S8, SP\r
1766: TickType_t xTicks;\r
1767: \r
1768: /* Critical section required if running on a 16 bit processor. */\r
1769: portTICK_TYPE_ENTER_CRITICAL();\r
-BFD0999C 33B877E8 JALS vTaskEnterCritical
-BFD0999E 0C0033B8 ADDIU SP, T8, 3072
-BFD099A0 0C00 NOP
+BFD0999C 33B877E8 JALS vTaskEnterCritical\r
+BFD0999E 0C0033B8 ADDIU SP, T8, 3072\r
+BFD099A0 0C00 NOP\r
1770: {\r
1771: xTicks = xTickCount;\r
-BFD099A2 803CFC5C LW V0, -32708(GP)
-BFD099A6 0010F85E SW V0, 16(S8)
+BFD099A2 803CFC5C LW V0, -32708(GP)\r
+BFD099A6 0010F85E SW V0, 16(S8)\r
1772: }\r
1773: portTICK_TYPE_EXIT_CRITICAL();\r
-BFD099AA 40AA77E8 JALS vTaskExitCritical
-BFD099AC 0C0040AA BNEZC T2, 0xBFD0B1B0
-BFD099AE 0C00 NOP
+BFD099AA 40AA77E8 JALS vTaskExitCritical\r
+BFD099AC 0C0040AA BNEZC T2, 0xBFD0B1B0\r
+BFD099AE 0C00 NOP\r
1774: \r
1775: return xTicks;\r
-BFD099B0 0010FC5E LW V0, 16(S8)
+BFD099B0 0010FC5E LW V0, 16(S8)\r
1776: }\r
-BFD099B4 0FBE MOVE SP, S8
-BFD099B6 4BE7 LW RA, 28(SP)
-BFD099B8 4BC6 LW S8, 24(SP)
-BFD099BA 4C11 ADDIU SP, SP, 32
-BFD099BC 459F JR16 RA
-BFD099BE 0C00 NOP
+BFD099B4 0FBE MOVE SP, S8\r
+BFD099B6 4BE7 LW RA, 28(SP)\r
+BFD099B8 4BC6 LW S8, 24(SP)\r
+BFD099BA 4C11 ADDIU SP, SP, 32\r
+BFD099BC 459F JR16 RA\r
+BFD099BE 0C00 NOP\r
1777: /*-----------------------------------------------------------*/\r
1778: \r
1779: TickType_t xTaskGetTickCountFromISR( void )\r
1780: {\r
-BFD09844 4FF1 ADDIU SP, SP, -32
-BFD09846 CBE7 SW RA, 28(SP)
-BFD09848 CBC6 SW S8, 24(SP)
-BFD0984A 0FDD MOVE S8, SP
+BFD09844 4FF1 ADDIU SP, SP, -32\r
+BFD09846 CBE7 SW RA, 28(SP)\r
+BFD09848 CBC6 SW S8, 24(SP)\r
+BFD0984A 0FDD MOVE S8, SP\r
1781: TickType_t xReturn;\r
1782: UBaseType_t uxSavedInterruptStatus;\r
1783: \r
1798: portASSERT_IF_INTERRUPT_PRIORITY_INVALID();\r
1799: \r
1800: uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();\r
-BFD0984C 475E77E8 JALS uxPortSetInterruptMaskFromISR
-BFD09850 0C00 NOP
-BFD09852 0010F85E SW V0, 16(S8)
+BFD0984C 475E77E8 JALS uxPortSetInterruptMaskFromISR\r
+BFD09850 0C00 NOP\r
+BFD09852 0010F85E SW V0, 16(S8)\r
1801: {\r
1802: xReturn = xTickCount;\r
-BFD09856 803CFC5C LW V0, -32708(GP)
-BFD0985A 0014F85E SW V0, 20(S8)
+BFD09856 803CFC5C LW V0, -32708(GP)\r
+BFD0985A 0014F85E SW V0, 20(S8)\r
1803: }\r
1804: portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r
-BFD0985E 0010FC9E LW A0, 16(S8)
-BFD09862 4D5E77E8 JALS vPortClearInterruptMaskFromISR
-BFD09864 4D5E ADDIU T2, T2, -1
-BFD09866 0C00 NOP
+BFD0985E 0010FC9E LW A0, 16(S8)\r
+BFD09862 4D5E77E8 JALS vPortClearInterruptMaskFromISR\r
+BFD09864 4D5E ADDIU T2, T2, -1\r
+BFD09866 0C00 NOP\r
1805: \r
1806: return xReturn;\r
-BFD09868 0014FC5E LW V0, 20(S8)
+BFD09868 0014FC5E LW V0, 20(S8)\r
1807: }\r
-BFD0986C 0FBE MOVE SP, S8
-BFD0986E 4BE7 LW RA, 28(SP)
-BFD09870 4BC6 LW S8, 24(SP)
-BFD09872 4C11 ADDIU SP, SP, 32
-BFD09874 459F JR16 RA
-BFD09876 0C00 NOP
+BFD0986C 0FBE MOVE SP, S8\r
+BFD0986E 4BE7 LW RA, 28(SP)\r
+BFD09870 4BC6 LW S8, 24(SP)\r
+BFD09872 4C11 ADDIU SP, SP, 32\r
+BFD09874 459F JR16 RA\r
+BFD09876 0C00 NOP\r
1808: /*-----------------------------------------------------------*/\r
1809: \r
1810: UBaseType_t uxTaskGetNumberOfTasks( void )\r
1811: {\r
-BFD09E98 4FB0 ADDIU SP, SP, -8
-BFD09E9A CBC1 SW S8, 4(SP)
-BFD09E9C 0FDD MOVE S8, SP
+BFD09E98 4FB0 ADDIU SP, SP, -8\r
+BFD09E9A CBC1 SW S8, 4(SP)\r
+BFD09E9C 0FDD MOVE S8, SP\r
1812: /* A critical section is not required because the variables are of type\r
1813: BaseType_t. */\r
1814: return uxCurrentNumberOfTasks;\r
-BFD09E9E 8038FC5C LW V0, -32712(GP)
+BFD09E9E 8038FC5C LW V0, -32712(GP)\r
1815: }\r
-BFD09EA2 0FBE MOVE SP, S8
-BFD09EA4 4BC1 LW S8, 4(SP)
-BFD09EA6 4C05 ADDIU SP, SP, 8
-BFD09EA8 459F JR16 RA
-BFD09EAA 0C00 NOP
+BFD09EA2 0FBE MOVE SP, S8\r
+BFD09EA4 4BC1 LW S8, 4(SP)\r
+BFD09EA6 4C05 ADDIU SP, SP, 8\r
+BFD09EA8 459F JR16 RA\r
+BFD09EAA 0C00 NOP\r
1816: /*-----------------------------------------------------------*/\r
1817: \r
1818: #if ( INCLUDE_pcTaskGetTaskName == 1 )\r
1938: \r
1939: BaseType_t xTaskIncrementTick( void )\r
1940: {\r
-BFD02080 4FE9 ADDIU SP, SP, -48
-BFD02082 CBEB SW RA, 44(SP)
-BFD02084 CBCA SW S8, 40(SP)
-BFD02086 0FDD MOVE S8, SP
+BFD02080 4FE9 ADDIU SP, SP, -48\r
+BFD02082 CBEB SW RA, 44(SP)\r
+BFD02084 CBCA SW S8, 40(SP)\r
+BFD02086 0FDD MOVE S8, SP\r
1941: TCB_t * pxTCB;\r
1942: TickType_t xItemValue;\r
1943: BaseType_t xSwitchRequired = pdFALSE;\r
-BFD02088 0010F81E SW ZERO, 16(S8)
+BFD02088 0010F81E SW ZERO, 16(S8)\r
1944: \r
1945: /* Called by the portable layer each time a tick interrupt occurs.\r
1946: Increments the tick then checks to see if the new tick value will cause any\r
1947: tasks to be unblocked. */\r
1948: traceTASK_INCREMENT_TICK( xTickCount );\r
1949: if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\r
-BFD0208C 805CFC5C LW V0, -32676(GP)
-BFD02090 00B840A2 BNEZC V0, 0xBFD02204
+BFD0208C 805CFC5C LW V0, -32676(GP)\r
+BFD02090 00B840A2 BNEZC V0, 0xBFD02204\r
1950: {\r
1951: /* Increment the RTOS tick, switching the delayed and overflowed\r
1952: delayed lists if it wraps to 0. */\r
1953: ++xTickCount;\r
-BFD02094 803CFC5C LW V0, -32708(GP)
-BFD02098 6D20 ADDIU V0, V0, 1
-BFD0209A 803CF85C SW V0, -32708(GP)
+BFD02094 803CFC5C LW V0, -32708(GP)\r
+BFD02098 6D20 ADDIU V0, V0, 1\r
+BFD0209A 803CF85C SW V0, -32708(GP)\r
1954: \r
1955: {\r
1956: /* Minor optimisation. The tick count cannot change in this\r
1957: block. */\r
1958: const TickType_t xConstTickCount = xTickCount;\r
-BFD0209E 803CFC5C LW V0, -32708(GP)
-BFD020A2 0014F85E SW V0, 20(S8)
+BFD0209E 803CFC5C LW V0, -32708(GP)\r
+BFD020A2 0014F85E SW V0, 20(S8)\r
1959: \r
1960: if( xConstTickCount == ( TickType_t ) 0U )\r
-BFD020A6 0014FC5E LW V0, 20(S8)
-BFD020AA 002240A2 BNEZC V0, 0xBFD020F2
+BFD020A6 0014FC5E LW V0, 20(S8)\r
+BFD020AA 002240A2 BNEZC V0, 0xBFD020F2\r
1961: {\r
1962: taskSWITCH_DELAYED_LISTS();\r
-BFD020AE 8074FC5C LW V0, -32652(GP)
-BFD020B2 6920 LW V0, 0(V0)
-BFD020B4 000940E2 BEQZC V0, 0xBFD020CA
-BFD020B8 BFD141A2 LUI V0, 0xBFD1
-BFD020BA 3082BFD1 LDC1 F30, 12418(S1)
-BFD020BC 98103082 ADDIU A0, V0, -26608
-BFD020BE 30A09810 SWC1 F0, 12448(S0)
-BFD020C0 07AA30A0 ADDIU A1, ZERO, 1962
-BFD020C2 07AA ADDU A3, A1, V0
-BFD020C4 4B7E77E8 JALS vAssertCalled
-BFD020C6 4B7E LW K1, 120(SP)
-BFD020C8 0C00 NOP
-BFD020CA 8074FC5C LW V0, -32652(GP)
-BFD020CE 0018F85E SW V0, 24(S8)
-BFD020D2 8078FC5C LW V0, -32648(GP)
-BFD020D6 8074F85C SW V0, -32652(GP)
-BFD020DA 0018FC5E LW V0, 24(S8)
-BFD020DE 8078F85C SW V0, -32648(GP)
-BFD020E2 8050FC5C LW V0, -32688(GP)
-BFD020E6 6D20 ADDIU V0, V0, 1
-BFD020E8 8050F85C SW V0, -32688(GP)
-BFD020EC 47CA77E8 JALS prvResetNextTaskUnblockTime
-BFD020F0 0C00 NOP
+BFD020AE 8074FC5C LW V0, -32652(GP)\r
+BFD020B2 6920 LW V0, 0(V0)\r
+BFD020B4 000940E2 BEQZC V0, 0xBFD020CA\r
+BFD020B8 BFD141A2 LUI V0, 0xBFD1\r
+BFD020BA 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD020BC 98103082 ADDIU A0, V0, -26608\r
+BFD020BE 30A09810 SWC1 F0, 12448(S0)\r
+BFD020C0 07AA30A0 ADDIU A1, ZERO, 1962\r
+BFD020C2 07AA ADDU A3, A1, V0\r
+BFD020C4 4B7E77E8 JALS vAssertCalled\r
+BFD020C6 4B7E LW K1, 120(SP)\r
+BFD020C8 0C00 NOP\r
+BFD020CA 8074FC5C LW V0, -32652(GP)\r
+BFD020CE 0018F85E SW V0, 24(S8)\r
+BFD020D2 8078FC5C LW V0, -32648(GP)\r
+BFD020D6 8074F85C SW V0, -32652(GP)\r
+BFD020DA 0018FC5E LW V0, 24(S8)\r
+BFD020DE 8078F85C SW V0, -32648(GP)\r
+BFD020E2 8050FC5C LW V0, -32688(GP)\r
+BFD020E6 6D20 ADDIU V0, V0, 1\r
+BFD020E8 8050F85C SW V0, -32688(GP)\r
+BFD020EC 47CA77E8 JALS prvResetNextTaskUnblockTime\r
+BFD020F0 0C00 NOP\r
1963: }\r
1964: else\r
1965: {\r
1971: has been found whose block time has not expired there is no need to\r
1972: look any further down the list. */\r
1973: if( xConstTickCount >= xNextTaskUnblockTime )\r
-BFD020F2 8058FC5C LW V0, -32680(GP)
-BFD020F6 0014FC7E LW V1, 20(S8)
-BFD020FA 13900043 SLTU V0, V1, V0
-BFD020FC 40A21390 ADDI GP, S0, 16546
-BFD020FE 006C40A2 BNEZC V0, 0xBFD021DA
-BFD02102 CC02 B 0xBFD02108
-BFD02104 0C00 NOP
+BFD020F2 8058FC5C LW V0, -32680(GP)\r
+BFD020F6 0014FC7E LW V1, 20(S8)\r
+BFD020FA 13900043 SLTU V0, V1, V0\r
+BFD020FC 40A21390 ADDI GP, S0, 16546\r
+BFD020FE 006C40A2 BNEZC V0, 0xBFD021DA\r
+BFD02102 CC02 B 0xBFD02108\r
+BFD02104 0C00 NOP\r
1974: {\r
1975: for( ;; )\r
1976: {\r
1977: if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )\r
-BFD02108 8074FC5C LW V0, -32652(GP)
-BFD0210C 6920 LW V0, 0(V0)
-BFD0210E 000340A2 BNEZC V0, 0xBFD02118
-BFD02112 ED01 LI V0, 1
-BFD02114 CC02 B 0xBFD0211A
-BFD02116 0C00 NOP
-BFD02118 0C40 MOVE V0, ZERO
-BFD0211A 000540E2 BEQZC V0, 0xBFD02128
+BFD02108 8074FC5C LW V0, -32652(GP)\r
+BFD0210C 6920 LW V0, 0(V0)\r
+BFD0210E 000340A2 BNEZC V0, 0xBFD02118\r
+BFD02112 ED01 LI V0, 1\r
+BFD02114 CC02 B 0xBFD0211A\r
+BFD02116 0C00 NOP\r
+BFD02118 0C40 MOVE V0, ZERO\r
+BFD0211A 000540E2 BEQZC V0, 0xBFD02128\r
1978: {\r
1979: /* The delayed list is empty. Set xNextTaskUnblockTime\r
1980: to the maximum possible value so it is extremely\r
1982: if( xTickCount >= xNextTaskUnblockTime ) test will pass\r
1983: next time through. */\r
1984: xNextTaskUnblockTime = portMAX_DELAY;\r
-BFD0211E ED7F LI V0, -1
-BFD02120 8058F85C SW V0, -32680(GP)
+BFD0211E ED7F LI V0, -1\r
+BFD02120 8058F85C SW V0, -32680(GP)\r
1985: break;\r
-BFD02124 CC5A B 0xBFD021DA
-BFD02126 0C00 NOP
+BFD02124 CC5A B 0xBFD021DA\r
+BFD02126 0C00 NOP\r
1986: }\r
1987: else\r
1988: {\r
1991: at which the task at the head of the delayed list must\r
1992: be removed from the Blocked state. */\r
1993: pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );\r
-BFD02128 8074FC5C LW V0, -32652(GP)
-BFD0212C 6923 LW V0, 12(V0)
-BFD0212E 6923 LW V0, 12(V0)
-BFD02130 001CF85E SW V0, 28(S8)
+BFD02128 8074FC5C LW V0, -32652(GP)\r
+BFD0212C 6923 LW V0, 12(V0)\r
+BFD0212E 6923 LW V0, 12(V0)\r
+BFD02130 001CF85E SW V0, 28(S8)\r
1994: xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xGenericListItem ) );\r
-BFD02134 001CFC5E LW V0, 28(S8)
-BFD02138 6921 LW V0, 4(V0)
-BFD0213A 0020F85E SW V0, 32(S8)
+BFD02134 001CFC5E LW V0, 28(S8)\r
+BFD02138 6921 LW V0, 4(V0)\r
+BFD0213A 0020F85E SW V0, 32(S8)\r
1995: \r
1996: if( xConstTickCount < xItemValue )\r
-BFD0213E 0014FC7E LW V1, 20(S8)
-BFD02142 0020FC5E LW V0, 32(S8)
-BFD02146 13900043 SLTU V0, V1, V0
-BFD02148 40E21390 ADDI GP, S0, 16610
-BFD0214A 000640E2 BEQZC V0, 0xBFD0215A
+BFD0213E 0014FC7E LW V1, 20(S8)\r
+BFD02142 0020FC5E LW V0, 32(S8)\r
+BFD02146 13900043 SLTU V0, V1, V0\r
+BFD02148 40E21390 ADDI GP, S0, 16610\r
+BFD0214A 000640E2 BEQZC V0, 0xBFD0215A\r
1997: {\r
1998: /* It is not time to unblock this item yet, but the\r
1999: item value is the time at which the task at the head\r
2001: state - so record the item value in\r
2002: xNextTaskUnblockTime. */\r
2003: xNextTaskUnblockTime = xItemValue;\r
-BFD0214E 0020FC5E LW V0, 32(S8)
-BFD02152 8058F85C SW V0, -32680(GP)
+BFD0214E 0020FC5E LW V0, 32(S8)\r
+BFD02152 8058F85C SW V0, -32680(GP)\r
2004: break;\r
-BFD02156 CC41 B 0xBFD021DA
-BFD02158 0C00 NOP
+BFD02156 CC41 B 0xBFD021DA\r
+BFD02158 0C00 NOP\r
2005: }\r
2006: else\r
2007: {\r
2010: \r
2011: /* It is time to remove the item from the Blocked state. */\r
2012: ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );\r
-BFD0215A 001CFC5E LW V0, 28(S8)
-BFD0215E 6D22 ADDIU V0, V0, 4
-BFD02160 0C82 MOVE A0, V0
-BFD02162 00C877E8 JALS uxListRemove
-BFD02164 0C0000C8 SLL A2, T0, 1
-BFD02166 0C00 NOP
+BFD0215A 001CFC5E LW V0, 28(S8)\r
+BFD0215E 6D22 ADDIU V0, V0, 4\r
+BFD02160 0C82 MOVE A0, V0\r
+BFD02162 00C877E8 JALS uxListRemove\r
+BFD02164 0C0000C8 SLL A2, T0, 1\r
+BFD02166 0C00 NOP\r
2013: \r
2014: /* Is the task waiting on an event also? If so remove\r
2015: it from the event list. */\r
2016: if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )\r
-BFD02168 001CFC5E LW V0, 28(S8)
-BFD0216C 692A LW V0, 40(V0)
-BFD0216E 000740E2 BEQZC V0, 0xBFD02180
+BFD02168 001CFC5E LW V0, 28(S8)\r
+BFD0216C 692A LW V0, 40(V0)\r
+BFD0216E 000740E2 BEQZC V0, 0xBFD02180\r
2017: {\r
2018: ( void ) uxListRemove( &( pxTCB->xEventListItem ) );\r
-BFD02172 001CFC5E LW V0, 28(S8)
-BFD02174 6D2C001C EXT ZERO, GP, 20, 14
-BFD02176 6D2C ADDIU V0, V0, 24
-BFD02178 0C82 MOVE A0, V0
-BFD0217A 00C877E8 JALS uxListRemove
-BFD0217C 0C0000C8 SLL A2, T0, 1
-BFD0217E 0C00 NOP
+BFD02172 001CFC5E LW V0, 28(S8)\r
+BFD02174 6D2C001C EXT ZERO, GP, 20, 14\r
+BFD02176 6D2C ADDIU V0, V0, 24\r
+BFD02178 0C82 MOVE A0, V0\r
+BFD0217A 00C877E8 JALS uxListRemove\r
+BFD0217C 0C0000C8 SLL A2, T0, 1\r
+BFD0217E 0C00 NOP\r
2019: }\r
2020: else\r
2021: {\r
2025: /* Place the unblocked task into the appropriate ready\r
2026: list. */\r
2027: prvAddTaskToReadyList( pxTCB );\r
-BFD02180 001CFC5E LW V0, 28(S8)
-BFD02184 692B LW V0, 44(V0)
-BFD02186 ED81 LI V1, 1
-BFD02188 18100062 SLLV V1, V0, V1
-BFD0218A FC5C1810 SB ZERO, -932(S0)
-BFD0218C 8040FC5C LW V0, -32704(GP)
-BFD02190 44D3 OR16 V0, V1
-BFD02192 8040F85C SW V0, -32704(GP)
-BFD02196 001CFC5E LW V0, 28(S8)
-BFD0219A 692B LW V0, 44(V0)
-BFD0219C 2524 SLL V0, V0, 2
-BFD0219E 25A4 SLL V1, V0, 2
-BFD021A0 05B4 ADDU V1, V0, V1
-BFD021A2 BFD241A2 LUI V0, 0xBFD2
-BFD021A4 3042BFD2 LDC1 F30, 12354(S2)
-BFD021A6 806C3042 ADDIU V0, V0, -32660
-BFD021AA 05A6 ADDU V1, V1, V0
-BFD021AC 001CFC5E LW V0, 28(S8)
-BFD021B0 6D22 ADDIU V0, V0, 4
-BFD021B2 0C83 MOVE A0, V1
-BFD021B4 0CA2 MOVE A1, V0
-BFD021B6 3E4A77E8 JALS vListInsertEnd
-BFD021B8 0C003E4A LH S2, 3072(T2)
-BFD021BA 0C00 NOP
+BFD02180 001CFC5E LW V0, 28(S8)\r
+BFD02184 692B LW V0, 44(V0)\r
+BFD02186 ED81 LI V1, 1\r
+BFD02188 18100062 SLLV V1, V0, V1\r
+BFD0218A FC5C1810 SB ZERO, -932(S0)\r
+BFD0218C 8040FC5C LW V0, -32704(GP)\r
+BFD02190 44D3 OR16 V0, V1\r
+BFD02192 8040F85C SW V0, -32704(GP)\r
+BFD02196 001CFC5E LW V0, 28(S8)\r
+BFD0219A 692B LW V0, 44(V0)\r
+BFD0219C 2524 SLL V0, V0, 2\r
+BFD0219E 25A4 SLL V1, V0, 2\r
+BFD021A0 05B4 ADDU V1, V0, V1\r
+BFD021A2 BFD241A2 LUI V0, 0xBFD2\r
+BFD021A4 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD021A6 806C3042 ADDIU V0, V0, -32660\r
+BFD021AA 05A6 ADDU V1, V1, V0\r
+BFD021AC 001CFC5E LW V0, 28(S8)\r
+BFD021B0 6D22 ADDIU V0, V0, 4\r
+BFD021B2 0C83 MOVE A0, V1\r
+BFD021B4 0CA2 MOVE A1, V0\r
+BFD021B6 3E4A77E8 JALS vListInsertEnd\r
+BFD021B8 0C003E4A LH S2, 3072(T2)\r
+BFD021BA 0C00 NOP\r
2028: \r
2029: /* A task being unblocked cannot cause an immediate\r
2030: context switch if preemption is turned off. */\r
2035: priority that is equal to or higher than the\r
2036: currently executing task. */\r
2037: if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )\r
-BFD021BC 001CFC5E LW V0, 28(S8)
-BFD021C0 69AB LW V1, 44(V0)
-BFD021C2 8030FC5C LW V0, -32720(GP)
-BFD021C6 692B LW V0, 44(V0)
-BFD021C8 13900043 SLTU V0, V1, V0
-BFD021CA 40A21390 ADDI GP, S0, 16546
-BFD021CC FF9B40A2 BNEZC V0, 0xBFD02106
-BFD021CE ED01FF9B LW GP, -4863(K1)
+BFD021BC 001CFC5E LW V0, 28(S8)\r
+BFD021C0 69AB LW V1, 44(V0)\r
+BFD021C2 8030FC5C LW V0, -32720(GP)\r
+BFD021C6 692B LW V0, 44(V0)\r
+BFD021C8 13900043 SLTU V0, V1, V0\r
+BFD021CA 40A21390 ADDI GP, S0, 16546\r
+BFD021CC FF9B40A2 BNEZC V0, 0xBFD02106\r
+BFD021CE ED01FF9B LW GP, -4863(K1)\r
2038: {\r
2039: xSwitchRequired = pdTRUE;\r
-BFD021D0 ED01 LI V0, 1
-BFD021D2 0010F85E SW V0, 16(S8)
+BFD021D0 ED01 LI V0, 1\r
+BFD021D2 0010F85E SW V0, 16(S8)\r
2040: }\r
2041: else\r
2042: {\r
2046: #endif /* configUSE_PREEMPTION */\r
2047: }\r
2048: }\r
-BFD02106 0C00 NOP
-BFD021D6 CF98 B 0xBFD02108
-BFD021D8 0C00 NOP
+BFD02106 0C00 NOP\r
+BFD021D6 CF98 B 0xBFD02108\r
+BFD021D8 0C00 NOP\r
2049: }\r
2050: }\r
2051: \r
2055: #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )\r
2056: {\r
2057: if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )\r
-BFD021DA 8030FC5C LW V0, -32720(GP)
-BFD021DE 692B LW V0, 44(V0)
-BFD021E0 2524 SLL V0, V0, 2
-BFD021E2 25A4 SLL V1, V0, 2
-BFD021E4 05B4 ADDU V1, V0, V1
-BFD021E6 BFD241A2 LUI V0, 0xBFD2
-BFD021E8 3042BFD2 LDC1 F30, 12354(S2)
-BFD021EA 806C3042 ADDIU V0, V0, -32660
-BFD021EE 0526 ADDU V0, V1, V0
-BFD021F0 6920 LW V0, 0(V0)
-BFD021F2 0002B042 SLTIU V0, V0, 2
-BFD021F6 000A40A2 BNEZC V0, 0xBFD0220E
+BFD021DA 8030FC5C LW V0, -32720(GP)\r
+BFD021DE 692B LW V0, 44(V0)\r
+BFD021E0 2524 SLL V0, V0, 2\r
+BFD021E2 25A4 SLL V1, V0, 2\r
+BFD021E4 05B4 ADDU V1, V0, V1\r
+BFD021E6 BFD241A2 LUI V0, 0xBFD2\r
+BFD021E8 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD021EA 806C3042 ADDIU V0, V0, -32660\r
+BFD021EE 0526 ADDU V0, V1, V0\r
+BFD021F0 6920 LW V0, 0(V0)\r
+BFD021F2 0002B042 SLTIU V0, V0, 2\r
+BFD021F6 000A40A2 BNEZC V0, 0xBFD0220E\r
2058: {\r
2059: xSwitchRequired = pdTRUE;\r
-BFD021FA ED01 LI V0, 1
-BFD021FC 0010F85E SW V0, 16(S8)
-BFD02200 CC06 B 0xBFD0220E
-BFD02202 0C00 NOP
+BFD021FA ED01 LI V0, 1\r
+BFD021FC 0010F85E SW V0, 16(S8)\r
+BFD02200 CC06 B 0xBFD0220E\r
+BFD02202 0C00 NOP\r
2060: }\r
2061: else\r
2062: {\r
2083: else\r
2084: {\r
2085: ++uxPendedTicks;\r
-BFD02204 8048FC5C LW V0, -32696(GP)
-BFD02208 6D20 ADDIU V0, V0, 1
-BFD0220A 8048F85C SW V0, -32696(GP)
+BFD02204 8048FC5C LW V0, -32696(GP)\r
+BFD02208 6D20 ADDIU V0, V0, 1\r
+BFD0220A 8048F85C SW V0, -32696(GP)\r
2086: \r
2087: /* The tick hook gets called at regular intervals, even if the\r
2088: scheduler is locked. */\r
2096: #if ( configUSE_PREEMPTION == 1 )\r
2097: {\r
2098: if( xYieldPending != pdFALSE )\r
-BFD0220E 804CFC5C LW V0, -32692(GP)
-BFD02212 000340E2 BEQZC V0, 0xBFD0221C
+BFD0220E 804CFC5C LW V0, -32692(GP)\r
+BFD02212 000340E2 BEQZC V0, 0xBFD0221C\r
2099: {\r
2100: xSwitchRequired = pdTRUE;\r
-BFD02216 ED01 LI V0, 1
-BFD02218 0010F85E SW V0, 16(S8)
+BFD02216 ED01 LI V0, 1\r
+BFD02218 0010F85E SW V0, 16(S8)\r
2101: }\r
2102: else\r
2103: {\r
2107: #endif /* configUSE_PREEMPTION */\r
2108: \r
2109: return xSwitchRequired;\r
-BFD0221C 0010FC5E LW V0, 16(S8)
+BFD0221C 0010FC5E LW V0, 16(S8)\r
2110: }\r
-BFD02220 0FBE MOVE SP, S8
-BFD02222 4BEB LW RA, 44(SP)
-BFD02224 4BCA LW S8, 40(SP)
-BFD02226 4C19 ADDIU SP, SP, 48
-BFD02228 459F JR16 RA
-BFD0222A 0C00 NOP
+BFD02220 0FBE MOVE SP, S8\r
+BFD02222 4BEB LW RA, 44(SP)\r
+BFD02224 4BCA LW S8, 40(SP)\r
+BFD02226 4C19 ADDIU SP, SP, 48\r
+BFD02228 459F JR16 RA\r
+BFD0222A 0C00 NOP\r
2111: /*-----------------------------------------------------------*/\r
2112: \r
2113: #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
2202: \r
2203: void vTaskSwitchContext( void )\r
2204: {\r
-BFD02DBC 4FE5 ADDIU SP, SP, -56
-BFD02DBE CBED SW RA, 52(SP)
-BFD02DC0 CBCC SW S8, 48(SP)
-BFD02DC2 0FDD MOVE S8, SP
+BFD02DBC 4FE5 ADDIU SP, SP, -56\r
+BFD02DBE CBED SW RA, 52(SP)\r
+BFD02DC0 CBCC SW S8, 48(SP)\r
+BFD02DC2 0FDD MOVE S8, SP\r
2205: if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )\r
-BFD02DC4 805CFC5C LW V0, -32676(GP)
-BFD02DC8 000540E2 BEQZC V0, 0xBFD02DD6
+BFD02DC4 805CFC5C LW V0, -32676(GP)\r
+BFD02DC8 000540E2 BEQZC V0, 0xBFD02DD6\r
2206: {\r
2207: /* The scheduler is currently suspended - do not allow a context\r
2208: switch. */\r
2209: xYieldPending = pdTRUE;\r
-BFD02DCC ED01 LI V0, 1
-BFD02DCE 804CF85C SW V0, -32692(GP)
-BFD02DD2 CC91 B 0xBFD02EF6
-BFD02DD4 0C00 NOP
+BFD02DCC ED01 LI V0, 1\r
+BFD02DCE 804CF85C SW V0, -32692(GP)\r
+BFD02DD2 CC91 B 0xBFD02EF6\r
+BFD02DD4 0C00 NOP\r
2210: }\r
2211: else\r
2212: {\r
2213: xYieldPending = pdFALSE;\r
-BFD02DD6 804CF81C SW ZERO, -32692(GP)
+BFD02DD6 804CF81C SW ZERO, -32692(GP)\r
2214: traceTASK_SWITCHED_OUT();\r
2215: \r
2216: #if ( configGENERATE_RUN_TIME_STATS == 1 )\r
2242: \r
2243: /* Check for stack overflow, if configured. */\r
2244: taskFIRST_CHECK_FOR_STACK_OVERFLOW();\r
-BFD02DDA 8030FC5C LW V0, -32720(GP)
-BFD02DDE 69A0 LW V1, 0(V0)
-BFD02DE0 8030FC5C LW V0, -32720(GP)
-BFD02DE4 692C LW V0, 48(V0)
-BFD02DE6 13900062 SLTU V0, V0, V1
-BFD02DE8 40A21390 ADDI GP, S0, 16546
-BFD02DEA 000B40A2 BNEZC V0, 0xBFD02E04
-BFD02DEE 8030FC7C LW V1, -32720(GP)
-BFD02DF2 8030FC5C LW V0, -32720(GP)
-BFD02DF6 00343042 ADDIU V0, V0, 52
-BFD02DFA 0C83 MOVE A0, V1
-BFD02DFC 0CA2 MOVE A1, V0
-BFD02DFE 422277E8 JALS vApplicationStackOverflowHook
-BFD02E00 0C004222 BLTZALS V0, 0xBFD04604
-BFD02E02 0C00 NOP
+BFD02DDA 8030FC5C LW V0, -32720(GP)\r
+BFD02DDE 69A0 LW V1, 0(V0)\r
+BFD02DE0 8030FC5C LW V0, -32720(GP)\r
+BFD02DE4 692C LW V0, 48(V0)\r
+BFD02DE6 13900062 SLTU V0, V0, V1\r
+BFD02DE8 40A21390 ADDI GP, S0, 16546\r
+BFD02DEA 000B40A2 BNEZC V0, 0xBFD02E04\r
+BFD02DEE 8030FC7C LW V1, -32720(GP)\r
+BFD02DF2 8030FC5C LW V0, -32720(GP)\r
+BFD02DF6 00343042 ADDIU V0, V0, 52\r
+BFD02DFA 0C83 MOVE A0, V1\r
+BFD02DFC 0CA2 MOVE A1, V0\r
+BFD02DFE 422277E8 JALS vApplicationStackOverflowHook\r
+BFD02E00 0C004222 BLTZALS V0, 0xBFD04604\r
+BFD02E02 0C00 NOP\r
2245: taskSECOND_CHECK_FOR_STACK_OVERFLOW();\r
-BFD02E04 BFD141A2 LUI V0, 0xBFD1
-BFD02E06 FCC2BFD1 LDC1 F30, -830(S1)
-BFD02E08 9830FCC2 LW A2, -26576(V0)
-BFD02E0A 30629830 SWC1 F1, 12386(S0)
-BFD02E0C 98303062 ADDIU V1, V0, -26576
-BFD02E0E 6AB19830 SWC1 F1, 27313(S0)
-BFD02E10 6AB1 LW A1, 4(V1)
-BFD02E12 98303062 ADDIU V1, V0, -26576
-BFD02E14 6A329830 SWC1 F1, 27186(S0)
-BFD02E16 6A32 LW A0, 8(V1)
-BFD02E18 98303062 ADDIU V1, V0, -26576
-BFD02E1A 69B39830 SWC1 F1, 27059(S0)
-BFD02E1C 69B3 LW V1, 12(V1)
-BFD02E1E 98303042 ADDIU V0, V0, -26576
-BFD02E20 69249830 SWC1 F1, 26916(S0)
-BFD02E22 6924 LW V0, 16(V0)
-BFD02E24 0018F8DE SW A2, 24(S8)
-BFD02E28 001CF8BE SW A1, 28(S8)
-BFD02E2C 0020F89E SW A0, 32(S8)
-BFD02E30 0024F87E SW V1, 36(S8)
-BFD02E34 0028F85E SW V0, 40(S8)
-BFD02E38 8030FC5C LW V0, -32720(GP)
-BFD02E3C 69AC LW V1, 48(V0)
-BFD02E3E 0018305E ADDIU V0, S8, 24
-BFD02E42 0C83 MOVE A0, V1
-BFD02E44 0CA2 MOVE A1, V0
-BFD02E46 EF14 LI A2, 20
-BFD02E48 3DA677E8 JALS 0xBFD07B4C
-BFD02E4A 0C003DA6 LH T5, 3072(A2)
-BFD02E4C 0C00 NOP
-BFD02E4E 000B40E2 BEQZC V0, 0xBFD02E68
-BFD02E52 8030FC7C LW V1, -32720(GP)
-BFD02E56 8030FC5C LW V0, -32720(GP)
-BFD02E5A 00343042 ADDIU V0, V0, 52
-BFD02E5E 0C83 MOVE A0, V1
-BFD02E60 0CA2 MOVE A1, V0
-BFD02E62 422277E8 JALS vApplicationStackOverflowHook
-BFD02E64 0C004222 BLTZALS V0, 0xBFD04668
-BFD02E66 0C00 NOP
+BFD02E04 BFD141A2 LUI V0, 0xBFD1\r
+BFD02E06 FCC2BFD1 LDC1 F30, -830(S1)\r
+BFD02E08 9830FCC2 LW A2, -26576(V0)\r
+BFD02E0A 30629830 SWC1 F1, 12386(S0)\r
+BFD02E0C 98303062 ADDIU V1, V0, -26576\r
+BFD02E0E 6AB19830 SWC1 F1, 27313(S0)\r
+BFD02E10 6AB1 LW A1, 4(V1)\r
+BFD02E12 98303062 ADDIU V1, V0, -26576\r
+BFD02E14 6A329830 SWC1 F1, 27186(S0)\r
+BFD02E16 6A32 LW A0, 8(V1)\r
+BFD02E18 98303062 ADDIU V1, V0, -26576\r
+BFD02E1A 69B39830 SWC1 F1, 27059(S0)\r
+BFD02E1C 69B3 LW V1, 12(V1)\r
+BFD02E1E 98303042 ADDIU V0, V0, -26576\r
+BFD02E20 69249830 SWC1 F1, 26916(S0)\r
+BFD02E22 6924 LW V0, 16(V0)\r
+BFD02E24 0018F8DE SW A2, 24(S8)\r
+BFD02E28 001CF8BE SW A1, 28(S8)\r
+BFD02E2C 0020F89E SW A0, 32(S8)\r
+BFD02E30 0024F87E SW V1, 36(S8)\r
+BFD02E34 0028F85E SW V0, 40(S8)\r
+BFD02E38 8030FC5C LW V0, -32720(GP)\r
+BFD02E3C 69AC LW V1, 48(V0)\r
+BFD02E3E 0018305E ADDIU V0, S8, 24\r
+BFD02E42 0C83 MOVE A0, V1\r
+BFD02E44 0CA2 MOVE A1, V0\r
+BFD02E46 EF14 LI A2, 20\r
+BFD02E48 3DA677E8 JALS 0xBFD07B4C\r
+BFD02E4A 0C003DA6 LH T5, 3072(A2)\r
+BFD02E4C 0C00 NOP\r
+BFD02E4E 000B40E2 BEQZC V0, 0xBFD02E68\r
+BFD02E52 8030FC7C LW V1, -32720(GP)\r
+BFD02E56 8030FC5C LW V0, -32720(GP)\r
+BFD02E5A 00343042 ADDIU V0, V0, 52\r
+BFD02E5E 0C83 MOVE A0, V1\r
+BFD02E60 0CA2 MOVE A1, V0\r
+BFD02E62 422277E8 JALS vApplicationStackOverflowHook\r
+BFD02E64 0C004222 BLTZALS V0, 0xBFD04668\r
+BFD02E66 0C00 NOP\r
2246: \r
2247: /* Select a new task to run using either the generic C or port\r
2248: optimised asm code. */\r
2249: taskSELECT_HIGHEST_PRIORITY_TASK();\r
-BFD02E68 8040FC5C LW V0, -32704(GP)
-BFD02E6C 5B3C0042 CLZ V0, V0
-BFD02E70 ED9F LI V1, 31
-BFD02E72 0527 SUBU V0, V1, V0
-BFD02E74 0010F85E SW V0, 16(S8)
-BFD02E78 0010FC5E LW V0, 16(S8)
-BFD02E7C 2524 SLL V0, V0, 2
-BFD02E7E 25A4 SLL V1, V0, 2
-BFD02E80 05B4 ADDU V1, V0, V1
-BFD02E82 BFD241A2 LUI V0, 0xBFD2
-BFD02E84 3042BFD2 LDC1 F30, 12354(S2)
-BFD02E86 806C3042 ADDIU V0, V0, -32660
-BFD02E8A 0526 ADDU V0, V1, V0
-BFD02E8C 6920 LW V0, 0(V0)
-BFD02E8E 000940A2 BNEZC V0, 0xBFD02EA4
-BFD02E92 BFD141A2 LUI V0, 0xBFD1
-BFD02E94 3082BFD1 LDC1 F30, 12418(S1)
-BFD02E96 98103082 ADDIU A0, V0, -26608
-BFD02E98 30A09810 SWC1 F0, 12448(S0)
-BFD02E9A 08C930A0 ADDIU A1, ZERO, 2249
-BFD02E9C 08C9 LBU S1, 9(A0)
-BFD02E9E 4B7E77E8 JALS vAssertCalled
-BFD02EA0 4B7E LW K1, 120(SP)
-BFD02EA2 0C00 NOP
-BFD02EA4 0010FC5E LW V0, 16(S8)
-BFD02EA8 2524 SLL V0, V0, 2
-BFD02EAA 25A4 SLL V1, V0, 2
-BFD02EAC 05B4 ADDU V1, V0, V1
-BFD02EAE BFD241A2 LUI V0, 0xBFD2
-BFD02EB0 3042BFD2 LDC1 F30, 12354(S2)
-BFD02EB2 806C3042 ADDIU V0, V0, -32660
-BFD02EB6 0526 ADDU V0, V1, V0
-BFD02EB8 0014F85E SW V0, 20(S8)
-BFD02EBC 0014FC5E LW V0, 20(S8)
-BFD02EC0 6921 LW V0, 4(V0)
-BFD02EC2 69A1 LW V1, 4(V0)
-BFD02EC4 0014FC5E LW V0, 20(S8)
-BFD02EC8 E9A1 SW V1, 4(V0)
-BFD02ECA 0014FC5E LW V0, 20(S8)
-BFD02ECE 69A1 LW V1, 4(V0)
-BFD02ED0 0014FC5E LW V0, 20(S8)
-BFD02ED4 6D24 ADDIU V0, V0, 8
-BFD02ED6 0008B443 BNE V1, V0, 0xBFD02EEA
-BFD02ED8 0C000008 SLL ZERO, T0, 1
-BFD02EDA 0C00 NOP
-BFD02EDC 0014FC5E LW V0, 20(S8)
-BFD02EE0 6921 LW V0, 4(V0)
-BFD02EE2 69A1 LW V1, 4(V0)
-BFD02EE4 0014FC5E LW V0, 20(S8)
-BFD02EE8 E9A1 SW V1, 4(V0)
-BFD02EEA 0014FC5E LW V0, 20(S8)
-BFD02EEE 6921 LW V0, 4(V0)
-BFD02EF0 6923 LW V0, 12(V0)
-BFD02EF2 8030F85C SW V0, -32720(GP)
+BFD02E68 8040FC5C LW V0, -32704(GP)\r
+BFD02E6C 5B3C0042 CLZ V0, V0\r
+BFD02E70 ED9F LI V1, 31\r
+BFD02E72 0527 SUBU V0, V1, V0\r
+BFD02E74 0010F85E SW V0, 16(S8)\r
+BFD02E78 0010FC5E LW V0, 16(S8)\r
+BFD02E7C 2524 SLL V0, V0, 2\r
+BFD02E7E 25A4 SLL V1, V0, 2\r
+BFD02E80 05B4 ADDU V1, V0, V1\r
+BFD02E82 BFD241A2 LUI V0, 0xBFD2\r
+BFD02E84 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD02E86 806C3042 ADDIU V0, V0, -32660\r
+BFD02E8A 0526 ADDU V0, V1, V0\r
+BFD02E8C 6920 LW V0, 0(V0)\r
+BFD02E8E 000940A2 BNEZC V0, 0xBFD02EA4\r
+BFD02E92 BFD141A2 LUI V0, 0xBFD1\r
+BFD02E94 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD02E96 98103082 ADDIU A0, V0, -26608\r
+BFD02E98 30A09810 SWC1 F0, 12448(S0)\r
+BFD02E9A 08C930A0 ADDIU A1, ZERO, 2249\r
+BFD02E9C 08C9 LBU S1, 9(A0)\r
+BFD02E9E 4B7E77E8 JALS vAssertCalled\r
+BFD02EA0 4B7E LW K1, 120(SP)\r
+BFD02EA2 0C00 NOP\r
+BFD02EA4 0010FC5E LW V0, 16(S8)\r
+BFD02EA8 2524 SLL V0, V0, 2\r
+BFD02EAA 25A4 SLL V1, V0, 2\r
+BFD02EAC 05B4 ADDU V1, V0, V1\r
+BFD02EAE BFD241A2 LUI V0, 0xBFD2\r
+BFD02EB0 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD02EB2 806C3042 ADDIU V0, V0, -32660\r
+BFD02EB6 0526 ADDU V0, V1, V0\r
+BFD02EB8 0014F85E SW V0, 20(S8)\r
+BFD02EBC 0014FC5E LW V0, 20(S8)\r
+BFD02EC0 6921 LW V0, 4(V0)\r
+BFD02EC2 69A1 LW V1, 4(V0)\r
+BFD02EC4 0014FC5E LW V0, 20(S8)\r
+BFD02EC8 E9A1 SW V1, 4(V0)\r
+BFD02ECA 0014FC5E LW V0, 20(S8)\r
+BFD02ECE 69A1 LW V1, 4(V0)\r
+BFD02ED0 0014FC5E LW V0, 20(S8)\r
+BFD02ED4 6D24 ADDIU V0, V0, 8\r
+BFD02ED6 0008B443 BNE V1, V0, 0xBFD02EEA\r
+BFD02ED8 0C000008 SLL ZERO, T0, 1\r
+BFD02EDA 0C00 NOP\r
+BFD02EDC 0014FC5E LW V0, 20(S8)\r
+BFD02EE0 6921 LW V0, 4(V0)\r
+BFD02EE2 69A1 LW V1, 4(V0)\r
+BFD02EE4 0014FC5E LW V0, 20(S8)\r
+BFD02EE8 E9A1 SW V1, 4(V0)\r
+BFD02EEA 0014FC5E LW V0, 20(S8)\r
+BFD02EEE 6921 LW V0, 4(V0)\r
+BFD02EF0 6923 LW V0, 12(V0)\r
+BFD02EF2 8030F85C SW V0, -32720(GP)\r
2250: traceTASK_SWITCHED_IN();\r
2251: \r
2252: #if ( configUSE_NEWLIB_REENTRANT == 1 )\r
2258: #endif /* configUSE_NEWLIB_REENTRANT */\r
2259: }\r
2260: }\r
-BFD02EF6 0FBE MOVE SP, S8
-BFD02EF8 4BED LW RA, 52(SP)
-BFD02EFA 4BCC LW S8, 48(SP)
-BFD02EFC 4C1D ADDIU SP, SP, 56
-BFD02EFE 459F JR16 RA
-BFD02F00 0C00 NOP
+BFD02EF6 0FBE MOVE SP, S8\r
+BFD02EF8 4BED LW RA, 52(SP)\r
+BFD02EFA 4BCC LW S8, 48(SP)\r
+BFD02EFC 4C1D ADDIU SP, SP, 56\r
+BFD02EFE 459F JR16 RA\r
+BFD02F00 0C00 NOP\r
2261: /*-----------------------------------------------------------*/\r
2262: \r
2263: void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )\r
2264: {\r
-BFD05E74 4FF1 ADDIU SP, SP, -32
-BFD05E76 CBE7 SW RA, 28(SP)
-BFD05E78 CBC6 SW S8, 24(SP)
-BFD05E7A 0FDD MOVE S8, SP
-BFD05E7C 0020F89E SW A0, 32(S8)
-BFD05E80 0024F8BE SW A1, 36(S8)
+BFD05E74 4FF1 ADDIU SP, SP, -32\r
+BFD05E76 CBE7 SW RA, 28(SP)\r
+BFD05E78 CBC6 SW S8, 24(SP)\r
+BFD05E7A 0FDD MOVE S8, SP\r
+BFD05E7C 0020F89E SW A0, 32(S8)\r
+BFD05E80 0024F8BE SW A1, 36(S8)\r
2265: TickType_t xTimeToWake;\r
2266: \r
2267: configASSERT( pxEventList );\r
-BFD05E84 0020FC5E LW V0, 32(S8)
-BFD05E88 000940A2 BNEZC V0, 0xBFD05E9E
-BFD05E8C BFD141A2 LUI V0, 0xBFD1
-BFD05E8E 3082BFD1 LDC1 F30, 12418(S1)
-BFD05E90 98103082 ADDIU A0, V0, -26608
-BFD05E92 30A09810 SWC1 F0, 12448(S0)
-BFD05E94 08DB30A0 ADDIU A1, ZERO, 2267
-BFD05E96 08DB LBU S1, 11(A1)
-BFD05E98 4B7E77E8 JALS vAssertCalled
-BFD05E9A 4B7E LW K1, 120(SP)
-BFD05E9C 0C00 NOP
+BFD05E84 0020FC5E LW V0, 32(S8)\r
+BFD05E88 000940A2 BNEZC V0, 0xBFD05E9E\r
+BFD05E8C BFD141A2 LUI V0, 0xBFD1\r
+BFD05E8E 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD05E90 98103082 ADDIU A0, V0, -26608\r
+BFD05E92 30A09810 SWC1 F0, 12448(S0)\r
+BFD05E94 08DB30A0 ADDIU A1, ZERO, 2267\r
+BFD05E96 08DB LBU S1, 11(A1)\r
+BFD05E98 4B7E77E8 JALS vAssertCalled\r
+BFD05E9A 4B7E LW K1, 120(SP)\r
+BFD05E9C 0C00 NOP\r
2268: \r
2269: /* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE\r
2270: SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */\r
2274: is the first to be woken by the event. The queue that contains the event\r
2275: list is locked, preventing simultaneous access from interrupts. */\r
2276: vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );\r
-BFD05E9E 8030FC5C LW V0, -32720(GP)
-BFD05EA2 6D2C ADDIU V0, V0, 24
-BFD05EA4 0020FC9E LW A0, 32(S8)
-BFD05EA8 0CA2 MOVE A1, V0
-BFD05EAA 304077E8 JALS vListInsert
-BFD05EAC 0C003040 ADDIU V0, ZERO, 3072
-BFD05EAE 0C00 NOP
+BFD05E9E 8030FC5C LW V0, -32720(GP)\r
+BFD05EA2 6D2C ADDIU V0, V0, 24\r
+BFD05EA4 0020FC9E LW A0, 32(S8)\r
+BFD05EA8 0CA2 MOVE A1, V0\r
+BFD05EAA 304077E8 JALS vListInsert\r
+BFD05EAC 0C003040 ADDIU V0, ZERO, 3072\r
+BFD05EAE 0C00 NOP\r
2277: \r
2278: /* The task must be removed from from the ready list before it is added to\r
2279: the blocked list as the same list item is used for both lists. Exclusive\r
2280: access to the ready lists guaranteed because the scheduler is locked. */\r
2281: if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r
-BFD05EB0 8030FC5C LW V0, -32720(GP)
-BFD05EB4 6D22 ADDIU V0, V0, 4
-BFD05EB6 0C82 MOVE A0, V0
-BFD05EB8 00C877E8 JALS uxListRemove
-BFD05EBA 0C0000C8 SLL A2, T0, 1
-BFD05EBC 0C00 NOP
-BFD05EBE 000C40A2 BNEZC V0, 0xBFD05EDA
+BFD05EB0 8030FC5C LW V0, -32720(GP)\r
+BFD05EB4 6D22 ADDIU V0, V0, 4\r
+BFD05EB6 0C82 MOVE A0, V0\r
+BFD05EB8 00C877E8 JALS uxListRemove\r
+BFD05EBA 0C0000C8 SLL A2, T0, 1\r
+BFD05EBC 0C00 NOP\r
+BFD05EBE 000C40A2 BNEZC V0, 0xBFD05EDA\r
2282: {\r
2283: /* The current task must be in a ready list, so there is no need to\r
2284: check, and the port reset macro can be called directly. */\r
2285: portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );\r
-BFD05EC2 8030FC5C LW V0, -32720(GP)
-BFD05EC6 692B LW V0, 44(V0)
-BFD05EC8 ED81 LI V1, 1
-BFD05ECA 10100062 SLLV V0, V0, V1
-BFD05ECC 441A1010 ADDI ZERO, S0, 17434
-BFD05ECE 441A NOT16 V1, V0
-BFD05ED0 8040FC5C LW V0, -32704(GP)
-BFD05ED4 4493 AND16 V0, V1
-BFD05ED6 8040F85C SW V0, -32704(GP)
+BFD05EC2 8030FC5C LW V0, -32720(GP)\r
+BFD05EC6 692B LW V0, 44(V0)\r
+BFD05EC8 ED81 LI V1, 1\r
+BFD05ECA 10100062 SLLV V0, V0, V1\r
+BFD05ECC 441A1010 ADDI ZERO, S0, 17434\r
+BFD05ECE 441A NOT16 V1, V0\r
+BFD05ED0 8040FC5C LW V0, -32704(GP)\r
+BFD05ED4 4493 AND16 V0, V1\r
+BFD05ED6 8040F85C SW V0, -32704(GP)\r
2286: }\r
2287: else\r
2288: {\r
2292: #if ( INCLUDE_vTaskSuspend == 1 )\r
2293: {\r
2294: if( xTicksToWait == portMAX_DELAY )\r
-BFD05EDA 0024FC7E LW V1, 36(S8)
-BFD05EDE ED7F LI V0, -1
-BFD05EE0 000EB443 BNE V1, V0, 0xBFD05F00
-BFD05EE2 0C00000E SLL ZERO, T6, 1
-BFD05EE4 0C00 NOP
+BFD05EDA 0024FC7E LW V1, 36(S8)\r
+BFD05EDE ED7F LI V0, -1\r
+BFD05EE0 000EB443 BNE V1, V0, 0xBFD05F00\r
+BFD05EE2 0C00000E SLL ZERO, T6, 1\r
+BFD05EE4 0C00 NOP\r
2295: {\r
2296: /* Add the task to the suspended task list instead of a delayed task\r
2297: list to ensure the task is not woken by a timing event. It will\r
2298: block indefinitely. */\r
2299: vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xGenericListItem ) );\r
-BFD05EE6 8030FC5C LW V0, -32720(GP)
-BFD05EEA 6D22 ADDIU V0, V0, 4
-BFD05EEC BFD241A3 LUI V1, 0xBFD2
-BFD05EEE 3083BFD2 LDC1 F30, 12419(S2)
-BFD05EF0 80E43083 ADDIU A0, V1, -32540
-BFD05EF4 0CA2 MOVE A1, V0
-BFD05EF6 3E4A77E8 JALS vListInsertEnd
-BFD05EF8 0C003E4A LH S2, 3072(T2)
-BFD05EFA 0C00 NOP
-BFD05EFC CC0D B 0xBFD05F18
-BFD05EFE 0C00 NOP
+BFD05EE6 8030FC5C LW V0, -32720(GP)\r
+BFD05EEA 6D22 ADDIU V0, V0, 4\r
+BFD05EEC BFD241A3 LUI V1, 0xBFD2\r
+BFD05EEE 3083BFD2 LDC1 F30, 12419(S2)\r
+BFD05EF0 80E43083 ADDIU A0, V1, -32540\r
+BFD05EF4 0CA2 MOVE A1, V0\r
+BFD05EF6 3E4A77E8 JALS vListInsertEnd\r
+BFD05EF8 0C003E4A LH S2, 3072(T2)\r
+BFD05EFA 0C00 NOP\r
+BFD05EFC CC0D B 0xBFD05F18\r
+BFD05EFE 0C00 NOP\r
2300: }\r
2301: else\r
2302: {\r
2304: does not occur. This may overflow but this doesn't matter, the\r
2305: scheduler will handle it. */\r
2306: xTimeToWake = xTickCount + xTicksToWait;\r
-BFD05F00 803CFC7C LW V1, -32708(GP)
-BFD05F04 0024FC5E LW V0, 36(S8)
-BFD05F08 0526 ADDU V0, V1, V0
-BFD05F0A 0010F85E SW V0, 16(S8)
+BFD05F00 803CFC7C LW V1, -32708(GP)\r
+BFD05F04 0024FC5E LW V0, 36(S8)\r
+BFD05F08 0526 ADDU V0, V1, V0\r
+BFD05F0A 0010F85E SW V0, 16(S8)\r
2307: prvAddCurrentTaskToDelayedList( xTimeToWake );\r
-BFD05F0E 0010FC9E LW A0, 16(S8)
-BFD05F12 373477E8 JALS prvAddCurrentTaskToDelayedList
-BFD05F14 0C003734 LHU T9, 3072(S4)
-BFD05F16 0C00 NOP
+BFD05F0E 0010FC9E LW A0, 16(S8)\r
+BFD05F12 373477E8 JALS prvAddCurrentTaskToDelayedList\r
+BFD05F14 0C003734 LHU T9, 3072(S4)\r
+BFD05F16 0C00 NOP\r
2308: }\r
2309: }\r
2310: #else /* INCLUDE_vTaskSuspend */\r
2317: }\r
2318: #endif /* INCLUDE_vTaskSuspend */\r
2319: }\r
-BFD05F18 0FBE MOVE SP, S8
-BFD05F1A 4BE7 LW RA, 28(SP)
-BFD05F1C 4BC6 LW S8, 24(SP)
-BFD05F1E 4C11 ADDIU SP, SP, 32
-BFD05F20 459F JR16 RA
-BFD05F22 0C00 NOP
+BFD05F18 0FBE MOVE SP, S8\r
+BFD05F1A 4BE7 LW RA, 28(SP)\r
+BFD05F1C 4BC6 LW S8, 24(SP)\r
+BFD05F1E 4C11 ADDIU SP, SP, 32\r
+BFD05F20 459F JR16 RA\r
+BFD05F22 0C00 NOP\r
2320: /*-----------------------------------------------------------*/\r
2321: \r
2322: void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait )\r
2323: {\r
-BFD04904 4FF1 ADDIU SP, SP, -32
-BFD04906 CBE7 SW RA, 28(SP)
-BFD04908 CBC6 SW S8, 24(SP)
-BFD0490A 0FDD MOVE S8, SP
-BFD0490C 0020F89E SW A0, 32(S8)
-BFD04910 0024F8BE SW A1, 36(S8)
-BFD04914 0028F8DE SW A2, 40(S8)
+BFD04904 4FF1 ADDIU SP, SP, -32\r
+BFD04906 CBE7 SW RA, 28(SP)\r
+BFD04908 CBC6 SW S8, 24(SP)\r
+BFD0490A 0FDD MOVE S8, SP\r
+BFD0490C 0020F89E SW A0, 32(S8)\r
+BFD04910 0024F8BE SW A1, 36(S8)\r
+BFD04914 0028F8DE SW A2, 40(S8)\r
2324: TickType_t xTimeToWake;\r
2325: \r
2326: configASSERT( pxEventList );\r
-BFD04918 0020FC5E LW V0, 32(S8)
-BFD0491C 000940A2 BNEZC V0, 0xBFD04932
-BFD04920 BFD141A2 LUI V0, 0xBFD1
-BFD04922 3082BFD1 LDC1 F30, 12418(S1)
-BFD04924 98103082 ADDIU A0, V0, -26608
-BFD04926 30A09810 SWC1 F0, 12448(S0)
-BFD04928 091630A0 ADDIU A1, ZERO, 2326
-BFD0492A 0916 LBU V0, 6(S1)
-BFD0492C 4B7E77E8 JALS vAssertCalled
-BFD0492E 4B7E LW K1, 120(SP)
-BFD04930 0C00 NOP
+BFD04918 0020FC5E LW V0, 32(S8)\r
+BFD0491C 000940A2 BNEZC V0, 0xBFD04932\r
+BFD04920 BFD141A2 LUI V0, 0xBFD1\r
+BFD04922 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD04924 98103082 ADDIU A0, V0, -26608\r
+BFD04926 30A09810 SWC1 F0, 12448(S0)\r
+BFD04928 091630A0 ADDIU A1, ZERO, 2326\r
+BFD0492A 0916 LBU V0, 6(S1)\r
+BFD0492C 4B7E77E8 JALS vAssertCalled\r
+BFD0492E 4B7E LW K1, 120(SP)\r
+BFD04930 0C00 NOP\r
2327: \r
2328: /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. It is used by\r
2329: the event groups implementation. */\r
2330: configASSERT( uxSchedulerSuspended != 0 );\r
-BFD04932 805CFC5C LW V0, -32676(GP)
-BFD04936 000940A2 BNEZC V0, 0xBFD0494C
-BFD0493A BFD141A2 LUI V0, 0xBFD1
-BFD0493C 3082BFD1 LDC1 F30, 12418(S1)
-BFD0493E 98103082 ADDIU A0, V0, -26608
-BFD04940 30A09810 SWC1 F0, 12448(S0)
-BFD04942 091A30A0 ADDIU A1, ZERO, 2330
-BFD04944 091A LBU V0, 10(S1)
-BFD04946 4B7E77E8 JALS vAssertCalled
-BFD04948 4B7E LW K1, 120(SP)
-BFD0494A 0C00 NOP
+BFD04932 805CFC5C LW V0, -32676(GP)\r
+BFD04936 000940A2 BNEZC V0, 0xBFD0494C\r
+BFD0493A BFD141A2 LUI V0, 0xBFD1\r
+BFD0493C 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD0493E 98103082 ADDIU A0, V0, -26608\r
+BFD04940 30A09810 SWC1 F0, 12448(S0)\r
+BFD04942 091A30A0 ADDIU A1, ZERO, 2330\r
+BFD04944 091A LBU V0, 10(S1)\r
+BFD04946 4B7E77E8 JALS vAssertCalled\r
+BFD04948 4B7E LW K1, 120(SP)\r
+BFD0494A 0C00 NOP\r
2331: \r
2332: /* Store the item value in the event list item. It is safe to access the\r
2333: event list item here as interrupts won't access the event list item of a\r
2334: task that is not in the Blocked state. */\r
2335: listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );\r
-BFD0494C 8030FC5C LW V0, -32720(GP)
-BFD04950 0024FC9E LW A0, 36(S8)
-BFD04954 800041A3 LUI V1, 0x8000
-BFD04958 44DC OR16 V1, A0
-BFD0495A E9A6 SW V1, 24(V0)
+BFD0494C 8030FC5C LW V0, -32720(GP)\r
+BFD04950 0024FC9E LW A0, 36(S8)\r
+BFD04954 800041A3 LUI V1, 0x8000\r
+BFD04958 44DC OR16 V1, A0\r
+BFD0495A E9A6 SW V1, 24(V0)\r
2336: \r
2337: /* Place the event list item of the TCB at the end of the appropriate event\r
2338: list. It is safe to access the event list here because it is part of an\r
2340: directly (instead they access them indirectly by pending function calls to\r
2341: the task level). */\r
2342: vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );\r
-BFD0495C 8030FC5C LW V0, -32720(GP)
-BFD04960 6D2C ADDIU V0, V0, 24
-BFD04962 0020FC9E LW A0, 32(S8)
-BFD04966 0CA2 MOVE A1, V0
-BFD04968 3E4A77E8 JALS vListInsertEnd
-BFD0496A 0C003E4A LH S2, 3072(T2)
-BFD0496C 0C00 NOP
+BFD0495C 8030FC5C LW V0, -32720(GP)\r
+BFD04960 6D2C ADDIU V0, V0, 24\r
+BFD04962 0020FC9E LW A0, 32(S8)\r
+BFD04966 0CA2 MOVE A1, V0\r
+BFD04968 3E4A77E8 JALS vListInsertEnd\r
+BFD0496A 0C003E4A LH S2, 3072(T2)\r
+BFD0496C 0C00 NOP\r
2343: \r
2344: /* The task must be removed from the ready list before it is added to the\r
2345: blocked list. Exclusive access can be assured to the ready list as the\r
2346: scheduler is locked. */\r
2347: if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r
-BFD0496E 8030FC5C LW V0, -32720(GP)
-BFD04972 6D22 ADDIU V0, V0, 4
-BFD04974 0C82 MOVE A0, V0
-BFD04976 00C877E8 JALS uxListRemove
-BFD04978 0C0000C8 SLL A2, T0, 1
-BFD0497A 0C00 NOP
-BFD0497C 000C40A2 BNEZC V0, 0xBFD04998
+BFD0496E 8030FC5C LW V0, -32720(GP)\r
+BFD04972 6D22 ADDIU V0, V0, 4\r
+BFD04974 0C82 MOVE A0, V0\r
+BFD04976 00C877E8 JALS uxListRemove\r
+BFD04978 0C0000C8 SLL A2, T0, 1\r
+BFD0497A 0C00 NOP\r
+BFD0497C 000C40A2 BNEZC V0, 0xBFD04998\r
2348: {\r
2349: /* The current task must be in a ready list, so there is no need to\r
2350: check, and the port reset macro can be called directly. */\r
2351: portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );\r
-BFD04980 8030FC5C LW V0, -32720(GP)
-BFD04984 692B LW V0, 44(V0)
-BFD04986 ED81 LI V1, 1
-BFD04988 10100062 SLLV V0, V0, V1
-BFD0498A 441A1010 ADDI ZERO, S0, 17434
-BFD0498C 441A NOT16 V1, V0
-BFD0498E 8040FC5C LW V0, -32704(GP)
-BFD04992 4493 AND16 V0, V1
-BFD04994 8040F85C SW V0, -32704(GP)
+BFD04980 8030FC5C LW V0, -32720(GP)\r
+BFD04984 692B LW V0, 44(V0)\r
+BFD04986 ED81 LI V1, 1\r
+BFD04988 10100062 SLLV V0, V0, V1\r
+BFD0498A 441A1010 ADDI ZERO, S0, 17434\r
+BFD0498C 441A NOT16 V1, V0\r
+BFD0498E 8040FC5C LW V0, -32704(GP)\r
+BFD04992 4493 AND16 V0, V1\r
+BFD04994 8040F85C SW V0, -32704(GP)\r
2352: }\r
2353: else\r
2354: {\r
2358: #if ( INCLUDE_vTaskSuspend == 1 )\r
2359: {\r
2360: if( xTicksToWait == portMAX_DELAY )\r
-BFD04998 0028FC7E LW V1, 40(S8)
-BFD0499C ED7F LI V0, -1
-BFD0499E 000EB443 BNE V1, V0, 0xBFD049BE
-BFD049A0 0C00000E SLL ZERO, T6, 1
-BFD049A2 0C00 NOP
+BFD04998 0028FC7E LW V1, 40(S8)\r
+BFD0499C ED7F LI V0, -1\r
+BFD0499E 000EB443 BNE V1, V0, 0xBFD049BE\r
+BFD049A0 0C00000E SLL ZERO, T6, 1\r
+BFD049A2 0C00 NOP\r
2361: {\r
2362: /* Add the task to the suspended task list instead of a delayed task\r
2363: list to ensure it is not woken by a timing event. It will block\r
2364: indefinitely. */\r
2365: vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xGenericListItem ) );\r
-BFD049A4 8030FC5C LW V0, -32720(GP)
-BFD049A8 6D22 ADDIU V0, V0, 4
-BFD049AA BFD241A3 LUI V1, 0xBFD2
-BFD049AC 3083BFD2 LDC1 F30, 12419(S2)
-BFD049AE 80E43083 ADDIU A0, V1, -32540
-BFD049B2 0CA2 MOVE A1, V0
-BFD049B4 3E4A77E8 JALS vListInsertEnd
-BFD049B6 0C003E4A LH S2, 3072(T2)
-BFD049B8 0C00 NOP
-BFD049BA CC0D B 0xBFD049D6
-BFD049BC 0C00 NOP
+BFD049A4 8030FC5C LW V0, -32720(GP)\r
+BFD049A8 6D22 ADDIU V0, V0, 4\r
+BFD049AA BFD241A3 LUI V1, 0xBFD2\r
+BFD049AC 3083BFD2 LDC1 F30, 12419(S2)\r
+BFD049AE 80E43083 ADDIU A0, V1, -32540\r
+BFD049B2 0CA2 MOVE A1, V0\r
+BFD049B4 3E4A77E8 JALS vListInsertEnd\r
+BFD049B6 0C003E4A LH S2, 3072(T2)\r
+BFD049B8 0C00 NOP\r
+BFD049BA CC0D B 0xBFD049D6\r
+BFD049BC 0C00 NOP\r
2366: }\r
2367: else\r
2368: {\r
2370: does not occur. This may overflow but this doesn't matter, the\r
2371: kernel will manage it correctly. */\r
2372: xTimeToWake = xTickCount + xTicksToWait;\r
-BFD049BE 803CFC7C LW V1, -32708(GP)
-BFD049C2 0028FC5E LW V0, 40(S8)
-BFD049C6 0526 ADDU V0, V1, V0
-BFD049C8 0010F85E SW V0, 16(S8)
+BFD049BE 803CFC7C LW V1, -32708(GP)\r
+BFD049C2 0028FC5E LW V0, 40(S8)\r
+BFD049C6 0526 ADDU V0, V1, V0\r
+BFD049C8 0010F85E SW V0, 16(S8)\r
2373: prvAddCurrentTaskToDelayedList( xTimeToWake );\r
-BFD049CC 0010FC9E LW A0, 16(S8)
-BFD049D0 373477E8 JALS prvAddCurrentTaskToDelayedList
-BFD049D2 0C003734 LHU T9, 3072(S4)
-BFD049D4 0C00 NOP
+BFD049CC 0010FC9E LW A0, 16(S8)\r
+BFD049D0 373477E8 JALS prvAddCurrentTaskToDelayedList\r
+BFD049D2 0C003734 LHU T9, 3072(S4)\r
+BFD049D4 0C00 NOP\r
2374: }\r
2375: }\r
2376: #else /* INCLUDE_vTaskSuspend */\r
2383: }\r
2384: #endif /* INCLUDE_vTaskSuspend */\r
2385: }\r
-BFD049D6 0FBE MOVE SP, S8
-BFD049D8 4BE7 LW RA, 28(SP)
-BFD049DA 4BC6 LW S8, 24(SP)
-BFD049DC 4C11 ADDIU SP, SP, 32
-BFD049DE 459F JR16 RA
-BFD049E0 0C00 NOP
+BFD049D6 0FBE MOVE SP, S8\r
+BFD049D8 4BE7 LW RA, 28(SP)\r
+BFD049DA 4BC6 LW S8, 24(SP)\r
+BFD049DC 4C11 ADDIU SP, SP, 32\r
+BFD049DE 459F JR16 RA\r
+BFD049E0 0C00 NOP\r
2386: /*-----------------------------------------------------------*/\r
2387: \r
2388: #if configUSE_TIMERS == 1\r
2389: \r
2390: void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, const TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )\r
2391: {\r
-BFD05C58 4FF1 ADDIU SP, SP, -32
-BFD05C5A CBE7 SW RA, 28(SP)
-BFD05C5C CBC6 SW S8, 24(SP)
-BFD05C5E 0FDD MOVE S8, SP
-BFD05C60 0020F89E SW A0, 32(S8)
-BFD05C64 0024F8BE SW A1, 36(S8)
-BFD05C68 0028F8DE SW A2, 40(S8)
+BFD05C58 4FF1 ADDIU SP, SP, -32\r
+BFD05C5A CBE7 SW RA, 28(SP)\r
+BFD05C5C CBC6 SW S8, 24(SP)\r
+BFD05C5E 0FDD MOVE S8, SP\r
+BFD05C60 0020F89E SW A0, 32(S8)\r
+BFD05C64 0024F8BE SW A1, 36(S8)\r
+BFD05C68 0028F8DE SW A2, 40(S8)\r
2392: TickType_t xTimeToWake;\r
2393: \r
2394: configASSERT( pxEventList );\r
-BFD05C6C 0020FC5E LW V0, 32(S8)
-BFD05C70 000940A2 BNEZC V0, 0xBFD05C86
-BFD05C74 BFD141A2 LUI V0, 0xBFD1
-BFD05C76 3082BFD1 LDC1 F30, 12418(S1)
-BFD05C78 98103082 ADDIU A0, V0, -26608
-BFD05C7A 30A09810 SWC1 F0, 12448(S0)
-BFD05C7C 095A30A0 ADDIU A1, ZERO, 2394
-BFD05C7E 095A LBU V0, 10(A1)
-BFD05C80 4B7E77E8 JALS vAssertCalled
-BFD05C82 4B7E LW K1, 120(SP)
-BFD05C84 0C00 NOP
+BFD05C6C 0020FC5E LW V0, 32(S8)\r
+BFD05C70 000940A2 BNEZC V0, 0xBFD05C86\r
+BFD05C74 BFD141A2 LUI V0, 0xBFD1\r
+BFD05C76 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD05C78 98103082 ADDIU A0, V0, -26608\r
+BFD05C7A 30A09810 SWC1 F0, 12448(S0)\r
+BFD05C7C 095A30A0 ADDIU A1, ZERO, 2394\r
+BFD05C7E 095A LBU V0, 10(A1)\r
+BFD05C80 4B7E77E8 JALS vAssertCalled\r
+BFD05C82 4B7E LW K1, 120(SP)\r
+BFD05C84 0C00 NOP\r
2395: \r
2396: /* This function should not be called by application code hence the\r
2397: 'Restricted' in its name. It is not part of the public API. It is\r
2404: be waiting on this event list, so the faster vListInsertEnd() function\r
2405: can be used in place of vListInsert. */\r
2406: vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );\r
-BFD05C86 8030FC5C LW V0, -32720(GP)
-BFD05C8A 6D2C ADDIU V0, V0, 24
-BFD05C8C 0020FC9E LW A0, 32(S8)
-BFD05C90 0CA2 MOVE A1, V0
-BFD05C92 3E4A77E8 JALS vListInsertEnd
-BFD05C94 0C003E4A LH S2, 3072(T2)
-BFD05C96 0C00 NOP
+BFD05C86 8030FC5C LW V0, -32720(GP)\r
+BFD05C8A 6D2C ADDIU V0, V0, 24\r
+BFD05C8C 0020FC9E LW A0, 32(S8)\r
+BFD05C90 0CA2 MOVE A1, V0\r
+BFD05C92 3E4A77E8 JALS vListInsertEnd\r
+BFD05C94 0C003E4A LH S2, 3072(T2)\r
+BFD05C96 0C00 NOP\r
2407: \r
2408: /* We must remove this task from the ready list before adding it to the\r
2409: blocked list as the same list item is used for both lists. This\r
2410: function is called with the scheduler locked so interrupts will not\r
2411: access the lists at the same time. */\r
2412: if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r
-BFD05C98 8030FC5C LW V0, -32720(GP)
-BFD05C9C 6D22 ADDIU V0, V0, 4
-BFD05C9E 0C82 MOVE A0, V0
-BFD05CA0 00C877E8 JALS uxListRemove
-BFD05CA2 0C0000C8 SLL A2, T0, 1
-BFD05CA4 0C00 NOP
-BFD05CA6 000C40A2 BNEZC V0, 0xBFD05CC2
+BFD05C98 8030FC5C LW V0, -32720(GP)\r
+BFD05C9C 6D22 ADDIU V0, V0, 4\r
+BFD05C9E 0C82 MOVE A0, V0\r
+BFD05CA0 00C877E8 JALS uxListRemove\r
+BFD05CA2 0C0000C8 SLL A2, T0, 1\r
+BFD05CA4 0C00 NOP\r
+BFD05CA6 000C40A2 BNEZC V0, 0xBFD05CC2\r
2413: {\r
2414: /* The current task must be in a ready list, so there is no need to\r
2415: check, and the port reset macro can be called directly. */\r
2416: portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );\r
-BFD05CAA 8030FC5C LW V0, -32720(GP)
-BFD05CAE 692B LW V0, 44(V0)
-BFD05CB0 ED81 LI V1, 1
-BFD05CB2 10100062 SLLV V0, V0, V1
-BFD05CB4 441A1010 ADDI ZERO, S0, 17434
-BFD05CB6 441A NOT16 V1, V0
-BFD05CB8 8040FC5C LW V0, -32704(GP)
-BFD05CBC 4493 AND16 V0, V1
-BFD05CBE 8040F85C SW V0, -32704(GP)
+BFD05CAA 8030FC5C LW V0, -32720(GP)\r
+BFD05CAE 692B LW V0, 44(V0)\r
+BFD05CB0 ED81 LI V1, 1\r
+BFD05CB2 10100062 SLLV V0, V0, V1\r
+BFD05CB4 441A1010 ADDI ZERO, S0, 17434\r
+BFD05CB6 441A NOT16 V1, V0\r
+BFD05CB8 8040FC5C LW V0, -32704(GP)\r
+BFD05CBC 4493 AND16 V0, V1\r
+BFD05CBE 8040F85C SW V0, -32704(GP)\r
2417: }\r
2418: else\r
2419: {\r
2429: #if( INCLUDE_vTaskSuspend == 1 )\r
2430: {\r
2431: if( xWaitIndefinitely == pdTRUE )\r
-BFD05CC2 0028FC7E LW V1, 40(S8)
-BFD05CC6 ED01 LI V0, 1
-BFD05CC8 000EB443 BNE V1, V0, 0xBFD05CE8
-BFD05CCA 0C00000E SLL ZERO, T6, 1
-BFD05CCC 0C00 NOP
+BFD05CC2 0028FC7E LW V1, 40(S8)\r
+BFD05CC6 ED01 LI V0, 1\r
+BFD05CC8 000EB443 BNE V1, V0, 0xBFD05CE8\r
+BFD05CCA 0C00000E SLL ZERO, T6, 1\r
+BFD05CCC 0C00 NOP\r
2432: {\r
2433: /* Add the task to the suspended task list instead of a delayed\r
2434: task list to ensure the task is not woken by a timing event. It\r
2435: will block indefinitely. */\r
2436: vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xGenericListItem ) );\r
-BFD05CCE 8030FC5C LW V0, -32720(GP)
-BFD05CD2 6D22 ADDIU V0, V0, 4
-BFD05CD4 BFD241A3 LUI V1, 0xBFD2
-BFD05CD6 3083BFD2 LDC1 F30, 12419(S2)
-BFD05CD8 80E43083 ADDIU A0, V1, -32540
-BFD05CDC 0CA2 MOVE A1, V0
-BFD05CDE 3E4A77E8 JALS vListInsertEnd
-BFD05CE0 0C003E4A LH S2, 3072(T2)
-BFD05CE2 0C00 NOP
-BFD05CE4 CC0D B 0xBFD05D00
-BFD05CE6 0C00 NOP
+BFD05CCE 8030FC5C LW V0, -32720(GP)\r
+BFD05CD2 6D22 ADDIU V0, V0, 4\r
+BFD05CD4 BFD241A3 LUI V1, 0xBFD2\r
+BFD05CD6 3083BFD2 LDC1 F30, 12419(S2)\r
+BFD05CD8 80E43083 ADDIU A0, V1, -32540\r
+BFD05CDC 0CA2 MOVE A1, V0\r
+BFD05CDE 3E4A77E8 JALS vListInsertEnd\r
+BFD05CE0 0C003E4A LH S2, 3072(T2)\r
+BFD05CE2 0C00 NOP\r
+BFD05CE4 CC0D B 0xBFD05D00\r
+BFD05CE6 0C00 NOP\r
2437: }\r
2438: else\r
2439: {\r
2441: event does not occur. This may overflow but this doesn't\r
2442: matter. */\r
2443: xTimeToWake = xTickCount + xTicksToWait;\r
-BFD05CE8 803CFC7C LW V1, -32708(GP)
-BFD05CEC 0024FC5E LW V0, 36(S8)
-BFD05CF0 0526 ADDU V0, V1, V0
-BFD05CF2 0010F85E SW V0, 16(S8)
+BFD05CE8 803CFC7C LW V1, -32708(GP)\r
+BFD05CEC 0024FC5E LW V0, 36(S8)\r
+BFD05CF0 0526 ADDU V0, V1, V0\r
+BFD05CF2 0010F85E SW V0, 16(S8)\r
2444: traceTASK_DELAY_UNTIL();\r
2445: prvAddCurrentTaskToDelayedList( xTimeToWake );\r
-BFD05CF6 0010FC9E LW A0, 16(S8)
-BFD05CFA 373477E8 JALS prvAddCurrentTaskToDelayedList
-BFD05CFC 0C003734 LHU T9, 3072(S4)
-BFD05CFE 0C00 NOP
+BFD05CF6 0010FC9E LW A0, 16(S8)\r
+BFD05CFA 373477E8 JALS prvAddCurrentTaskToDelayedList\r
+BFD05CFC 0C003734 LHU T9, 3072(S4)\r
+BFD05CFE 0C00 NOP\r
2446: }\r
2447: }\r
2448: #else\r
2459: }\r
2460: #endif\r
2461: }\r
-BFD05D00 0FBE MOVE SP, S8
-BFD05D02 4BE7 LW RA, 28(SP)
-BFD05D04 4BC6 LW S8, 24(SP)
-BFD05D06 4C11 ADDIU SP, SP, 32
-BFD05D08 459F JR16 RA
-BFD05D0A 0C00 NOP
+BFD05D00 0FBE MOVE SP, S8\r
+BFD05D02 4BE7 LW RA, 28(SP)\r
+BFD05D04 4BC6 LW S8, 24(SP)\r
+BFD05D06 4C11 ADDIU SP, SP, 32\r
+BFD05D08 459F JR16 RA\r
+BFD05D0A 0C00 NOP\r
2462: \r
2463: #endif /* configUSE_TIMERS */\r
2464: /*-----------------------------------------------------------*/\r
2465: \r
2466: BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )\r
2467: {\r
-BFD04578 4FF1 ADDIU SP, SP, -32
-BFD0457A CBE7 SW RA, 28(SP)
-BFD0457C CBC6 SW S8, 24(SP)
-BFD0457E 0FDD MOVE S8, SP
-BFD04580 0020F89E SW A0, 32(S8)
+BFD04578 4FF1 ADDIU SP, SP, -32\r
+BFD0457A CBE7 SW RA, 28(SP)\r
+BFD0457C CBC6 SW S8, 24(SP)\r
+BFD0457E 0FDD MOVE S8, SP\r
+BFD04580 0020F89E SW A0, 32(S8)\r
2468: TCB_t *pxUnblockedTCB;\r
2469: BaseType_t xReturn;\r
2470: \r
2482: This function assumes that a check has already been made to ensure that\r
2483: pxEventList is not empty. */\r
2484: pxUnblockedTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );\r
-BFD04584 0020FC5E LW V0, 32(S8)
-BFD04588 6923 LW V0, 12(V0)
-BFD0458A 6923 LW V0, 12(V0)
-BFD0458C 0014F85E SW V0, 20(S8)
+BFD04584 0020FC5E LW V0, 32(S8)\r
+BFD04588 6923 LW V0, 12(V0)\r
+BFD0458A 6923 LW V0, 12(V0)\r
+BFD0458C 0014F85E SW V0, 20(S8)\r
2485: configASSERT( pxUnblockedTCB );\r
-BFD04590 0014FC5E LW V0, 20(S8)
-BFD04594 000940A2 BNEZC V0, 0xBFD045AA
-BFD04598 BFD141A2 LUI V0, 0xBFD1
-BFD0459A 3082BFD1 LDC1 F30, 12418(S1)
-BFD0459C 98103082 ADDIU A0, V0, -26608
-BFD0459E 30A09810 SWC1 F0, 12448(S0)
-BFD045A0 09B530A0 ADDIU A1, ZERO, 2485
-BFD045A2 09B5 LBU V1, 5(V1)
-BFD045A4 4B7E77E8 JALS vAssertCalled
-BFD045A6 4B7E LW K1, 120(SP)
-BFD045A8 0C00 NOP
+BFD04590 0014FC5E LW V0, 20(S8)\r
+BFD04594 000940A2 BNEZC V0, 0xBFD045AA\r
+BFD04598 BFD141A2 LUI V0, 0xBFD1\r
+BFD0459A 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD0459C 98103082 ADDIU A0, V0, -26608\r
+BFD0459E 30A09810 SWC1 F0, 12448(S0)\r
+BFD045A0 09B530A0 ADDIU A1, ZERO, 2485\r
+BFD045A2 09B5 LBU V1, 5(V1)\r
+BFD045A4 4B7E77E8 JALS vAssertCalled\r
+BFD045A6 4B7E LW K1, 120(SP)\r
+BFD045A8 0C00 NOP\r
2486: ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );\r
-BFD045AA 0014FC5E LW V0, 20(S8)
-BFD045AC 6D2C0014 EXT ZERO, S4, 20, 14
-BFD045AE 6D2C ADDIU V0, V0, 24
-BFD045B0 0C82 MOVE A0, V0
-BFD045B2 00C877E8 JALS uxListRemove
-BFD045B4 0C0000C8 SLL A2, T0, 1
-BFD045B6 0C00 NOP
+BFD045AA 0014FC5E LW V0, 20(S8)\r
+BFD045AC 6D2C0014 EXT ZERO, S4, 20, 14\r
+BFD045AE 6D2C ADDIU V0, V0, 24\r
+BFD045B0 0C82 MOVE A0, V0\r
+BFD045B2 00C877E8 JALS uxListRemove\r
+BFD045B4 0C0000C8 SLL A2, T0, 1\r
+BFD045B6 0C00 NOP\r
2487: \r
2488: if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\r
-BFD045B8 805CFC5C LW V0, -32676(GP)
-BFD045BC 002740A2 BNEZC V0, 0xBFD0460E
+BFD045B8 805CFC5C LW V0, -32676(GP)\r
+BFD045BC 002740A2 BNEZC V0, 0xBFD0460E\r
2489: {\r
2490: ( void ) uxListRemove( &( pxUnblockedTCB->xGenericListItem ) );\r
-BFD045C0 0014FC5E LW V0, 20(S8)
-BFD045C4 6D22 ADDIU V0, V0, 4
-BFD045C6 0C82 MOVE A0, V0
-BFD045C8 00C877E8 JALS uxListRemove
-BFD045CA 0C0000C8 SLL A2, T0, 1
-BFD045CC 0C00 NOP
+BFD045C0 0014FC5E LW V0, 20(S8)\r
+BFD045C4 6D22 ADDIU V0, V0, 4\r
+BFD045C6 0C82 MOVE A0, V0\r
+BFD045C8 00C877E8 JALS uxListRemove\r
+BFD045CA 0C0000C8 SLL A2, T0, 1\r
+BFD045CC 0C00 NOP\r
2491: prvAddTaskToReadyList( pxUnblockedTCB );\r
-BFD045CE 0014FC5E LW V0, 20(S8)
-BFD045D2 692B LW V0, 44(V0)
-BFD045D4 ED81 LI V1, 1
-BFD045D6 18100062 SLLV V1, V0, V1
-BFD045D8 FC5C1810 SB ZERO, -932(S0)
-BFD045DA 8040FC5C LW V0, -32704(GP)
-BFD045DE 44D3 OR16 V0, V1
-BFD045E0 8040F85C SW V0, -32704(GP)
-BFD045E4 0014FC5E LW V0, 20(S8)
-BFD045E8 692B LW V0, 44(V0)
-BFD045EA 2524 SLL V0, V0, 2
-BFD045EC 25A4 SLL V1, V0, 2
-BFD045EE 05B4 ADDU V1, V0, V1
-BFD045F0 BFD241A2 LUI V0, 0xBFD2
-BFD045F2 3042BFD2 LDC1 F30, 12354(S2)
-BFD045F4 806C3042 ADDIU V0, V0, -32660
-BFD045F8 05A6 ADDU V1, V1, V0
-BFD045FA 0014FC5E LW V0, 20(S8)
-BFD045FE 6D22 ADDIU V0, V0, 4
-BFD04600 0C83 MOVE A0, V1
-BFD04602 0CA2 MOVE A1, V0
-BFD04604 3E4A77E8 JALS vListInsertEnd
-BFD04606 0C003E4A LH S2, 3072(T2)
-BFD04608 0C00 NOP
-BFD0460A CC0C B 0xBFD04624
-BFD0460C 0C00 NOP
+BFD045CE 0014FC5E LW V0, 20(S8)\r
+BFD045D2 692B LW V0, 44(V0)\r
+BFD045D4 ED81 LI V1, 1\r
+BFD045D6 18100062 SLLV V1, V0, V1\r
+BFD045D8 FC5C1810 SB ZERO, -932(S0)\r
+BFD045DA 8040FC5C LW V0, -32704(GP)\r
+BFD045DE 44D3 OR16 V0, V1\r
+BFD045E0 8040F85C SW V0, -32704(GP)\r
+BFD045E4 0014FC5E LW V0, 20(S8)\r
+BFD045E8 692B LW V0, 44(V0)\r
+BFD045EA 2524 SLL V0, V0, 2\r
+BFD045EC 25A4 SLL V1, V0, 2\r
+BFD045EE 05B4 ADDU V1, V0, V1\r
+BFD045F0 BFD241A2 LUI V0, 0xBFD2\r
+BFD045F2 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD045F4 806C3042 ADDIU V0, V0, -32660\r
+BFD045F8 05A6 ADDU V1, V1, V0\r
+BFD045FA 0014FC5E LW V0, 20(S8)\r
+BFD045FE 6D22 ADDIU V0, V0, 4\r
+BFD04600 0C83 MOVE A0, V1\r
+BFD04602 0CA2 MOVE A1, V0\r
+BFD04604 3E4A77E8 JALS vListInsertEnd\r
+BFD04606 0C003E4A LH S2, 3072(T2)\r
+BFD04608 0C00 NOP\r
+BFD0460A CC0C B 0xBFD04624\r
+BFD0460C 0C00 NOP\r
2492: }\r
2493: else\r
2494: {\r
2495: /* The delayed and ready lists cannot be accessed, so hold this task\r
2496: pending until the scheduler is resumed. */\r
2497: vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );\r
-BFD0460E 0014FC5E LW V0, 20(S8)
-BFD04610 6D2C0014 EXT ZERO, S4, 20, 14
-BFD04612 6D2C ADDIU V0, V0, 24
-BFD04614 BFD241A3 LUI V1, 0xBFD2
-BFD04616 3083BFD2 LDC1 F30, 12419(S2)
-BFD04618 80D03083 ADDIU A0, V1, -32560
-BFD0461C 0CA2 MOVE A1, V0
-BFD0461E 3E4A77E8 JALS vListInsertEnd
-BFD04620 0C003E4A LH S2, 3072(T2)
-BFD04622 0C00 NOP
+BFD0460E 0014FC5E LW V0, 20(S8)\r
+BFD04610 6D2C0014 EXT ZERO, S4, 20, 14\r
+BFD04612 6D2C ADDIU V0, V0, 24\r
+BFD04614 BFD241A3 LUI V1, 0xBFD2\r
+BFD04616 3083BFD2 LDC1 F30, 12419(S2)\r
+BFD04618 80D03083 ADDIU A0, V1, -32560\r
+BFD0461C 0CA2 MOVE A1, V0\r
+BFD0461E 3E4A77E8 JALS vListInsertEnd\r
+BFD04620 0C003E4A LH S2, 3072(T2)\r
+BFD04622 0C00 NOP\r
2498: }\r
2499: \r
2500: if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )\r
-BFD04624 0014FC5E LW V0, 20(S8)
-BFD04628 69AB LW V1, 44(V0)
-BFD0462A 8030FC5C LW V0, -32720(GP)
-BFD0462E 692B LW V0, 44(V0)
-BFD04630 13900062 SLTU V0, V0, V1
-BFD04632 40E21390 ADDI GP, S0, 16610
-BFD04634 000840E2 BEQZC V0, 0xBFD04648
+BFD04624 0014FC5E LW V0, 20(S8)\r
+BFD04628 69AB LW V1, 44(V0)\r
+BFD0462A 8030FC5C LW V0, -32720(GP)\r
+BFD0462E 692B LW V0, 44(V0)\r
+BFD04630 13900062 SLTU V0, V0, V1\r
+BFD04632 40E21390 ADDI GP, S0, 16610\r
+BFD04634 000840E2 BEQZC V0, 0xBFD04648\r
2501: {\r
2502: /* Return true if the task removed from the event list has a higher\r
2503: priority than the calling task. This allows the calling task to know if\r
2504: it should force a context switch now. */\r
2505: xReturn = pdTRUE;\r
-BFD04638 ED01 LI V0, 1
-BFD0463A 0010F85E SW V0, 16(S8)
+BFD04638 ED01 LI V0, 1\r
+BFD0463A 0010F85E SW V0, 16(S8)\r
2506: \r
2507: /* Mark that a yield is pending in case the user is not using the\r
2508: "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */\r
2509: xYieldPending = pdTRUE;\r
-BFD0463E ED01 LI V0, 1
-BFD04640 804CF85C SW V0, -32692(GP)
-BFD04644 CC03 B 0xBFD0464C
-BFD04646 0C00 NOP
+BFD0463E ED01 LI V0, 1\r
+BFD04640 804CF85C SW V0, -32692(GP)\r
+BFD04644 CC03 B 0xBFD0464C\r
+BFD04646 0C00 NOP\r
2510: }\r
2511: else\r
2512: {\r
2513: xReturn = pdFALSE;\r
-BFD04648 0010F81E SW ZERO, 16(S8)
+BFD04648 0010F81E SW ZERO, 16(S8)\r
2514: }\r
2515: \r
2516: #if( configUSE_TICKLESS_IDLE != 0 )\r
2528: #endif\r
2529: \r
2530: return xReturn;\r
-BFD0464C 0010FC5E LW V0, 16(S8)
+BFD0464C 0010FC5E LW V0, 16(S8)\r
2531: }\r
-BFD04650 0FBE MOVE SP, S8
-BFD04652 4BE7 LW RA, 28(SP)
-BFD04654 4BC6 LW S8, 24(SP)
-BFD04656 4C11 ADDIU SP, SP, 32
-BFD04658 459F JR16 RA
-BFD0465A 0C00 NOP
+BFD04650 0FBE MOVE SP, S8\r
+BFD04652 4BE7 LW RA, 28(SP)\r
+BFD04654 4BC6 LW S8, 24(SP)\r
+BFD04656 4C11 ADDIU SP, SP, 32\r
+BFD04658 459F JR16 RA\r
+BFD0465A 0C00 NOP\r
2532: /*-----------------------------------------------------------*/\r
2533: \r
2534: BaseType_t xTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue )\r
2535: {\r
-BFD042C4 4FF1 ADDIU SP, SP, -32
-BFD042C6 CBE7 SW RA, 28(SP)
-BFD042C8 CBC6 SW S8, 24(SP)
-BFD042CA 0FDD MOVE S8, SP
-BFD042CC 0020F89E SW A0, 32(S8)
-BFD042D0 0024F8BE SW A1, 36(S8)
+BFD042C4 4FF1 ADDIU SP, SP, -32\r
+BFD042C6 CBE7 SW RA, 28(SP)\r
+BFD042C8 CBC6 SW S8, 24(SP)\r
+BFD042CA 0FDD MOVE S8, SP\r
+BFD042CC 0020F89E SW A0, 32(S8)\r
+BFD042D0 0024F8BE SW A1, 36(S8)\r
2536: TCB_t *pxUnblockedTCB;\r
2537: BaseType_t xReturn;\r
2538: \r
2539: /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. It is used by\r
2540: the event flags implementation. */\r
2541: configASSERT( uxSchedulerSuspended != pdFALSE );\r
-BFD042D4 805CFC5C LW V0, -32676(GP)
-BFD042D8 000940A2 BNEZC V0, 0xBFD042EE
-BFD042DC BFD141A2 LUI V0, 0xBFD1
-BFD042DE 3082BFD1 LDC1 F30, 12418(S1)
-BFD042E0 98103082 ADDIU A0, V0, -26608
-BFD042E2 30A09810 SWC1 F0, 12448(S0)
-BFD042E4 09ED30A0 ADDIU A1, ZERO, 2541
-BFD042E6 09ED LBU V1, 13(A2)
-BFD042E8 4B7E77E8 JALS vAssertCalled
-BFD042EA 4B7E LW K1, 120(SP)
-BFD042EC 0C00 NOP
+BFD042D4 805CFC5C LW V0, -32676(GP)\r
+BFD042D8 000940A2 BNEZC V0, 0xBFD042EE\r
+BFD042DC BFD141A2 LUI V0, 0xBFD1\r
+BFD042DE 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD042E0 98103082 ADDIU A0, V0, -26608\r
+BFD042E2 30A09810 SWC1 F0, 12448(S0)\r
+BFD042E4 09ED30A0 ADDIU A1, ZERO, 2541\r
+BFD042E6 09ED LBU V1, 13(A2)\r
+BFD042E8 4B7E77E8 JALS vAssertCalled\r
+BFD042EA 4B7E LW K1, 120(SP)\r
+BFD042EC 0C00 NOP\r
2542: \r
2543: /* Store the new item value in the event list. */\r
2544: listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );\r
-BFD042EE 0024FC7E LW V1, 36(S8)
-BFD042F2 800041A2 LUI V0, 0x8000
-BFD042F6 44DA OR16 V1, V0
-BFD042F8 0020FC5E LW V0, 32(S8)
-BFD042FC E9A0 SW V1, 0(V0)
+BFD042EE 0024FC7E LW V1, 36(S8)\r
+BFD042F2 800041A2 LUI V0, 0x8000\r
+BFD042F6 44DA OR16 V1, V0\r
+BFD042F8 0020FC5E LW V0, 32(S8)\r
+BFD042FC E9A0 SW V1, 0(V0)\r
2545: \r
2546: /* Remove the event list form the event flag. Interrupts do not access\r
2547: event flags. */\r
2548: pxUnblockedTCB = ( TCB_t * ) listGET_LIST_ITEM_OWNER( pxEventListItem );\r
-BFD042FE 0020FC5E LW V0, 32(S8)
-BFD04302 6923 LW V0, 12(V0)
-BFD04304 0014F85E SW V0, 20(S8)
+BFD042FE 0020FC5E LW V0, 32(S8)\r
+BFD04302 6923 LW V0, 12(V0)\r
+BFD04304 0014F85E SW V0, 20(S8)\r
2549: configASSERT( pxUnblockedTCB );\r
-BFD04308 0014FC5E LW V0, 20(S8)
-BFD0430C 000940A2 BNEZC V0, 0xBFD04322
-BFD04310 BFD141A2 LUI V0, 0xBFD1
-BFD04312 3082BFD1 LDC1 F30, 12418(S1)
-BFD04314 98103082 ADDIU A0, V0, -26608
-BFD04316 30A09810 SWC1 F0, 12448(S0)
-BFD04318 09F530A0 ADDIU A1, ZERO, 2549
-BFD0431A 09F5 LBU V1, 5(A3)
-BFD0431C 4B7E77E8 JALS vAssertCalled
-BFD0431E 4B7E LW K1, 120(SP)
-BFD04320 0C00 NOP
+BFD04308 0014FC5E LW V0, 20(S8)\r
+BFD0430C 000940A2 BNEZC V0, 0xBFD04322\r
+BFD04310 BFD141A2 LUI V0, 0xBFD1\r
+BFD04312 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD04314 98103082 ADDIU A0, V0, -26608\r
+BFD04316 30A09810 SWC1 F0, 12448(S0)\r
+BFD04318 09F530A0 ADDIU A1, ZERO, 2549\r
+BFD0431A 09F5 LBU V1, 5(A3)\r
+BFD0431C 4B7E77E8 JALS vAssertCalled\r
+BFD0431E 4B7E LW K1, 120(SP)\r
+BFD04320 0C00 NOP\r
2550: ( void ) uxListRemove( pxEventListItem );\r
-BFD04322 0020FC9E LW A0, 32(S8)
-BFD04326 00C877E8 JALS uxListRemove
-BFD04328 0C0000C8 SLL A2, T0, 1
-BFD0432A 0C00 NOP
+BFD04322 0020FC9E LW A0, 32(S8)\r
+BFD04326 00C877E8 JALS uxListRemove\r
+BFD04328 0C0000C8 SLL A2, T0, 1\r
+BFD0432A 0C00 NOP\r
2551: \r
2552: /* Remove the task from the delayed list and add it to the ready list. The\r
2553: scheduler is suspended so interrupts will not be accessing the ready\r
2554: lists. */\r
2555: ( void ) uxListRemove( &( pxUnblockedTCB->xGenericListItem ) );\r
-BFD0432C 0014FC5E LW V0, 20(S8)
-BFD04330 6D22 ADDIU V0, V0, 4
-BFD04332 0C82 MOVE A0, V0
-BFD04334 00C877E8 JALS uxListRemove
-BFD04336 0C0000C8 SLL A2, T0, 1
-BFD04338 0C00 NOP
+BFD0432C 0014FC5E LW V0, 20(S8)\r
+BFD04330 6D22 ADDIU V0, V0, 4\r
+BFD04332 0C82 MOVE A0, V0\r
+BFD04334 00C877E8 JALS uxListRemove\r
+BFD04336 0C0000C8 SLL A2, T0, 1\r
+BFD04338 0C00 NOP\r
2556: prvAddTaskToReadyList( pxUnblockedTCB );\r
-BFD0433A 0014FC5E LW V0, 20(S8)
-BFD0433E 692B LW V0, 44(V0)
-BFD04340 ED81 LI V1, 1
-BFD04342 18100062 SLLV V1, V0, V1
-BFD04344 FC5C1810 SB ZERO, -932(S0)
-BFD04346 8040FC5C LW V0, -32704(GP)
-BFD0434A 44D3 OR16 V0, V1
-BFD0434C 8040F85C SW V0, -32704(GP)
-BFD04350 0014FC5E LW V0, 20(S8)
-BFD04354 692B LW V0, 44(V0)
-BFD04356 2524 SLL V0, V0, 2
-BFD04358 25A4 SLL V1, V0, 2
-BFD0435A 05B4 ADDU V1, V0, V1
-BFD0435C BFD241A2 LUI V0, 0xBFD2
-BFD0435E 3042BFD2 LDC1 F30, 12354(S2)
-BFD04360 806C3042 ADDIU V0, V0, -32660
-BFD04364 05A6 ADDU V1, V1, V0
-BFD04366 0014FC5E LW V0, 20(S8)
-BFD0436A 6D22 ADDIU V0, V0, 4
-BFD0436C 0C83 MOVE A0, V1
-BFD0436E 0CA2 MOVE A1, V0
-BFD04370 3E4A77E8 JALS vListInsertEnd
-BFD04372 0C003E4A LH S2, 3072(T2)
-BFD04374 0C00 NOP
+BFD0433A 0014FC5E LW V0, 20(S8)\r
+BFD0433E 692B LW V0, 44(V0)\r
+BFD04340 ED81 LI V1, 1\r
+BFD04342 18100062 SLLV V1, V0, V1\r
+BFD04344 FC5C1810 SB ZERO, -932(S0)\r
+BFD04346 8040FC5C LW V0, -32704(GP)\r
+BFD0434A 44D3 OR16 V0, V1\r
+BFD0434C 8040F85C SW V0, -32704(GP)\r
+BFD04350 0014FC5E LW V0, 20(S8)\r
+BFD04354 692B LW V0, 44(V0)\r
+BFD04356 2524 SLL V0, V0, 2\r
+BFD04358 25A4 SLL V1, V0, 2\r
+BFD0435A 05B4 ADDU V1, V0, V1\r
+BFD0435C BFD241A2 LUI V0, 0xBFD2\r
+BFD0435E 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD04360 806C3042 ADDIU V0, V0, -32660\r
+BFD04364 05A6 ADDU V1, V1, V0\r
+BFD04366 0014FC5E LW V0, 20(S8)\r
+BFD0436A 6D22 ADDIU V0, V0, 4\r
+BFD0436C 0C83 MOVE A0, V1\r
+BFD0436E 0CA2 MOVE A1, V0\r
+BFD04370 3E4A77E8 JALS vListInsertEnd\r
+BFD04372 0C003E4A LH S2, 3072(T2)\r
+BFD04374 0C00 NOP\r
2557: \r
2558: if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )\r
-BFD04376 0014FC5E LW V0, 20(S8)
-BFD0437A 69AB LW V1, 44(V0)
-BFD0437C 8030FC5C LW V0, -32720(GP)
-BFD04380 692B LW V0, 44(V0)
-BFD04382 13900062 SLTU V0, V0, V1
-BFD04384 40E21390 ADDI GP, S0, 16610
-BFD04386 000840E2 BEQZC V0, 0xBFD0439A
+BFD04376 0014FC5E LW V0, 20(S8)\r
+BFD0437A 69AB LW V1, 44(V0)\r
+BFD0437C 8030FC5C LW V0, -32720(GP)\r
+BFD04380 692B LW V0, 44(V0)\r
+BFD04382 13900062 SLTU V0, V0, V1\r
+BFD04384 40E21390 ADDI GP, S0, 16610\r
+BFD04386 000840E2 BEQZC V0, 0xBFD0439A\r
2559: {\r
2560: /* Return true if the task removed from the event list has\r
2561: a higher priority than the calling task. This allows\r
2562: the calling task to know if it should force a context\r
2563: switch now. */\r
2564: xReturn = pdTRUE;\r
-BFD0438A ED01 LI V0, 1
-BFD0438C 0010F85E SW V0, 16(S8)
+BFD0438A ED01 LI V0, 1\r
+BFD0438C 0010F85E SW V0, 16(S8)\r
2565: \r
2566: /* Mark that a yield is pending in case the user is not using the\r
2567: "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */\r
2568: xYieldPending = pdTRUE;\r
-BFD04390 ED01 LI V0, 1
-BFD04392 804CF85C SW V0, -32692(GP)
-BFD04396 CC03 B 0xBFD0439E
-BFD04398 0C00 NOP
+BFD04390 ED01 LI V0, 1\r
+BFD04392 804CF85C SW V0, -32692(GP)\r
+BFD04396 CC03 B 0xBFD0439E\r
+BFD04398 0C00 NOP\r
2569: }\r
2570: else\r
2571: {\r
2572: xReturn = pdFALSE;\r
-BFD0439A 0010F81E SW ZERO, 16(S8)
+BFD0439A 0010F81E SW ZERO, 16(S8)\r
2573: }\r
2574: \r
2575: return xReturn;\r
-BFD0439E 0010FC5E LW V0, 16(S8)
+BFD0439E 0010FC5E LW V0, 16(S8)\r
2576: }\r
-BFD043A2 0FBE MOVE SP, S8
-BFD043A4 4BE7 LW RA, 28(SP)
-BFD043A6 4BC6 LW S8, 24(SP)
-BFD043A8 4C11 ADDIU SP, SP, 32
-BFD043AA 459F JR16 RA
-BFD043AC 0C00 NOP
+BFD043A2 0FBE MOVE SP, S8\r
+BFD043A4 4BE7 LW RA, 28(SP)\r
+BFD043A6 4BC6 LW S8, 24(SP)\r
+BFD043A8 4C11 ADDIU SP, SP, 32\r
+BFD043AA 459F JR16 RA\r
+BFD043AC 0C00 NOP\r
2577: /*-----------------------------------------------------------*/\r
2578: \r
2579: void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )\r
2580: {\r
-BFD08F4C 4FF5 ADDIU SP, SP, -24
-BFD08F4E CBE5 SW RA, 20(SP)
-BFD08F50 CBC4 SW S8, 16(SP)
-BFD08F52 0FDD MOVE S8, SP
-BFD08F54 0018F89E SW A0, 24(S8)
+BFD08F4C 4FF5 ADDIU SP, SP, -24\r
+BFD08F4E CBE5 SW RA, 20(SP)\r
+BFD08F50 CBC4 SW S8, 16(SP)\r
+BFD08F52 0FDD MOVE S8, SP\r
+BFD08F54 0018F89E SW A0, 24(S8)\r
2581: configASSERT( pxTimeOut );\r
-BFD08F58 0018FC5E LW V0, 24(S8)
-BFD08F5C 000940A2 BNEZC V0, 0xBFD08F72
-BFD08F60 BFD141A2 LUI V0, 0xBFD1
-BFD08F62 3082BFD1 LDC1 F30, 12418(S1)
-BFD08F64 98103082 ADDIU A0, V0, -26608
-BFD08F66 30A09810 SWC1 F0, 12448(S0)
-BFD08F68 0A1530A0 ADDIU A1, ZERO, 2581
-BFD08F6A 0A15 LBU A0, 5(S1)
-BFD08F6C 4B7E77E8 JALS vAssertCalled
-BFD08F6E 4B7E LW K1, 120(SP)
-BFD08F70 0C00 NOP
+BFD08F58 0018FC5E LW V0, 24(S8)\r
+BFD08F5C 000940A2 BNEZC V0, 0xBFD08F72\r
+BFD08F60 BFD141A2 LUI V0, 0xBFD1\r
+BFD08F62 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD08F64 98103082 ADDIU A0, V0, -26608\r
+BFD08F66 30A09810 SWC1 F0, 12448(S0)\r
+BFD08F68 0A1530A0 ADDIU A1, ZERO, 2581\r
+BFD08F6A 0A15 LBU A0, 5(S1)\r
+BFD08F6C 4B7E77E8 JALS vAssertCalled\r
+BFD08F6E 4B7E LW K1, 120(SP)\r
+BFD08F70 0C00 NOP\r
2582: pxTimeOut->xOverflowCount = xNumOfOverflows;\r
-BFD08F72 8050FC7C LW V1, -32688(GP)
-BFD08F76 0018FC5E LW V0, 24(S8)
-BFD08F7A E9A0 SW V1, 0(V0)
+BFD08F72 8050FC7C LW V1, -32688(GP)\r
+BFD08F76 0018FC5E LW V0, 24(S8)\r
+BFD08F7A E9A0 SW V1, 0(V0)\r
2583: pxTimeOut->xTimeOnEntering = xTickCount;\r
-BFD08F7C 803CFC7C LW V1, -32708(GP)
-BFD08F80 0018FC5E LW V0, 24(S8)
-BFD08F84 E9A1 SW V1, 4(V0)
+BFD08F7C 803CFC7C LW V1, -32708(GP)\r
+BFD08F80 0018FC5E LW V0, 24(S8)\r
+BFD08F84 E9A1 SW V1, 4(V0)\r
2584: }\r
-BFD08F86 0FBE MOVE SP, S8
-BFD08F88 4BE5 LW RA, 20(SP)
-BFD08F8A 4BC4 LW S8, 16(SP)
-BFD08F8C 4C0D ADDIU SP, SP, 24
-BFD08F8E 459F JR16 RA
-BFD08F90 0C00 NOP
+BFD08F86 0FBE MOVE SP, S8\r
+BFD08F88 4BE5 LW RA, 20(SP)\r
+BFD08F8A 4BC4 LW S8, 16(SP)\r
+BFD08F8C 4C0D ADDIU SP, SP, 24\r
+BFD08F8E 459F JR16 RA\r
+BFD08F90 0C00 NOP\r
2585: /*-----------------------------------------------------------*/\r
2586: \r
2587: BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )\r
2588: {\r
-BFD03FEC 4FF1 ADDIU SP, SP, -32
-BFD03FEE CBE7 SW RA, 28(SP)
-BFD03FF0 CBC6 SW S8, 24(SP)
-BFD03FF2 0FDD MOVE S8, SP
-BFD03FF4 0020F89E SW A0, 32(S8)
-BFD03FF8 0024F8BE SW A1, 36(S8)
+BFD03FEC 4FF1 ADDIU SP, SP, -32\r
+BFD03FEE CBE7 SW RA, 28(SP)\r
+BFD03FF0 CBC6 SW S8, 24(SP)\r
+BFD03FF2 0FDD MOVE S8, SP\r
+BFD03FF4 0020F89E SW A0, 32(S8)\r
+BFD03FF8 0024F8BE SW A1, 36(S8)\r
2589: BaseType_t xReturn;\r
2590: \r
2591: configASSERT( pxTimeOut );\r
-BFD03FFC 0020FC5E LW V0, 32(S8)
-BFD04000 000940A2 BNEZC V0, 0xBFD04016
-BFD04004 BFD141A2 LUI V0, 0xBFD1
-BFD04006 3082BFD1 LDC1 F30, 12418(S1)
-BFD04008 98103082 ADDIU A0, V0, -26608
-BFD0400A 30A09810 SWC1 F0, 12448(S0)
-BFD0400C 0A1F30A0 ADDIU A1, ZERO, 2591
-BFD0400E 0A1F LBU A0, -1(S1)
-BFD04010 4B7E77E8 JALS vAssertCalled
-BFD04012 4B7E LW K1, 120(SP)
-BFD04014 0C00 NOP
+BFD03FFC 0020FC5E LW V0, 32(S8)\r
+BFD04000 000940A2 BNEZC V0, 0xBFD04016\r
+BFD04004 BFD141A2 LUI V0, 0xBFD1\r
+BFD04006 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD04008 98103082 ADDIU A0, V0, -26608\r
+BFD0400A 30A09810 SWC1 F0, 12448(S0)\r
+BFD0400C 0A1F30A0 ADDIU A1, ZERO, 2591\r
+BFD0400E 0A1F LBU A0, -1(S1)\r
+BFD04010 4B7E77E8 JALS vAssertCalled\r
+BFD04012 4B7E LW K1, 120(SP)\r
+BFD04014 0C00 NOP\r
2592: configASSERT( pxTicksToWait );\r
-BFD04016 0024FC5E LW V0, 36(S8)
-BFD0401A 000940A2 BNEZC V0, 0xBFD04030
-BFD0401E BFD141A2 LUI V0, 0xBFD1
-BFD04020 3082BFD1 LDC1 F30, 12418(S1)
-BFD04022 98103082 ADDIU A0, V0, -26608
-BFD04024 30A09810 SWC1 F0, 12448(S0)
-BFD04026 0A2030A0 ADDIU A1, ZERO, 2592
-BFD04028 0A20 LBU A0, 0(V0)
-BFD0402A 4B7E77E8 JALS vAssertCalled
-BFD0402C 4B7E LW K1, 120(SP)
-BFD0402E 0C00 NOP
+BFD04016 0024FC5E LW V0, 36(S8)\r
+BFD0401A 000940A2 BNEZC V0, 0xBFD04030\r
+BFD0401E BFD141A2 LUI V0, 0xBFD1\r
+BFD04020 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD04022 98103082 ADDIU A0, V0, -26608\r
+BFD04024 30A09810 SWC1 F0, 12448(S0)\r
+BFD04026 0A2030A0 ADDIU A1, ZERO, 2592\r
+BFD04028 0A20 LBU A0, 0(V0)\r
+BFD0402A 4B7E77E8 JALS vAssertCalled\r
+BFD0402C 4B7E LW K1, 120(SP)\r
+BFD0402E 0C00 NOP\r
2593: \r
2594: taskENTER_CRITICAL();\r
-BFD04030 33B877E8 JALS vTaskEnterCritical
-BFD04032 0C0033B8 ADDIU SP, T8, 3072
-BFD04034 0C00 NOP
+BFD04030 33B877E8 JALS vTaskEnterCritical\r
+BFD04032 0C0033B8 ADDIU SP, T8, 3072\r
+BFD04034 0C00 NOP\r
2595: {\r
2596: /* Minor optimisation. The tick count cannot change in this block. */\r
2597: const TickType_t xConstTickCount = xTickCount;\r
-BFD04036 803CFC5C LW V0, -32708(GP)
-BFD0403A 0014F85E SW V0, 20(S8)
+BFD04036 803CFC5C LW V0, -32708(GP)\r
+BFD0403A 0014F85E SW V0, 20(S8)\r
2598: \r
2599: #if ( INCLUDE_vTaskSuspend == 1 )\r
2600: /* If INCLUDE_vTaskSuspend is set to 1 and the block time specified is\r
2601: the maximum block time then the task should block indefinitely, and\r
2602: therefore never time out. */\r
2603: if( *pxTicksToWait == portMAX_DELAY )\r
-BFD0403E 0024FC5E LW V0, 36(S8)
-BFD04042 69A0 LW V1, 0(V0)
-BFD04044 ED7F LI V0, -1
-BFD04046 0005B443 BNE V1, V0, 0xBFD04054
-BFD04048 0C000005 SLL ZERO, A1, 1
-BFD0404A 0C00 NOP
+BFD0403E 0024FC5E LW V0, 36(S8)\r
+BFD04042 69A0 LW V1, 0(V0)\r
+BFD04044 ED7F LI V0, -1\r
+BFD04046 0005B443 BNE V1, V0, 0xBFD04054\r
+BFD04048 0C000005 SLL ZERO, A1, 1\r
+BFD0404A 0C00 NOP\r
2604: {\r
2605: xReturn = pdFALSE;\r
-BFD0404C 0010F81E SW ZERO, 16(S8)
-BFD0404E CC3D0010 REPL.PH T9, 0x10
-BFD04050 CC3D B 0xBFD040CC
-BFD04052 0C00 NOP
+BFD0404C 0010F81E SW ZERO, 16(S8)\r
+BFD0404E CC3D0010 REPL.PH T9, 0x10\r
+BFD04050 CC3D B 0xBFD040CC\r
+BFD04052 0C00 NOP\r
2606: }\r
2607: else /* We are not blocking indefinitely, perform the checks below. */\r
2608: #endif\r
2609: \r
2610: if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */\r
-BFD04054 0020FC5E LW V0, 32(S8)
-BFD04058 69A0 LW V1, 0(V0)
-BFD0405A 8050FC5C LW V0, -32688(GP)
-BFD0405E 000F9443 BEQ V1, V0, 0xBFD04080
-BFD04060 0C00000F SLL ZERO, T7, 1
-BFD04062 0C00 NOP
-BFD04064 0020FC5E LW V0, 32(S8)
-BFD04068 69A1 LW V1, 4(V0)
-BFD0406A 0014FC5E LW V0, 20(S8)
-BFD0406E 13900062 SLTU V0, V0, V1
-BFD04070 40A21390 ADDI GP, S0, 16546
-BFD04072 000540A2 BNEZC V0, 0xBFD04080
+BFD04054 0020FC5E LW V0, 32(S8)\r
+BFD04058 69A0 LW V1, 0(V0)\r
+BFD0405A 8050FC5C LW V0, -32688(GP)\r
+BFD0405E 000F9443 BEQ V1, V0, 0xBFD04080\r
+BFD04060 0C00000F SLL ZERO, T7, 1\r
+BFD04062 0C00 NOP\r
+BFD04064 0020FC5E LW V0, 32(S8)\r
+BFD04068 69A1 LW V1, 4(V0)\r
+BFD0406A 0014FC5E LW V0, 20(S8)\r
+BFD0406E 13900062 SLTU V0, V0, V1\r
+BFD04070 40A21390 ADDI GP, S0, 16546\r
+BFD04072 000540A2 BNEZC V0, 0xBFD04080\r
2611: {\r
2612: /* The tick count is greater than the time at which vTaskSetTimeout()\r
2613: was called, but has also overflowed since vTaskSetTimeOut() was called.\r
2614: It must have wrapped all the way around and gone past us again. This\r
2615: passed since vTaskSetTimeout() was called. */\r
2616: xReturn = pdTRUE;\r
-BFD04076 ED01 LI V0, 1
-BFD04078 0010F85E SW V0, 16(S8)
-BFD0407C CC27 B 0xBFD040CC
-BFD0407E 0C00 NOP
+BFD04076 ED01 LI V0, 1\r
+BFD04078 0010F85E SW V0, 16(S8)\r
+BFD0407C CC27 B 0xBFD040CC\r
+BFD0407E 0C00 NOP\r
2617: }\r
2618: else if( ( xConstTickCount - pxTimeOut->xTimeOnEntering ) < *pxTicksToWait )\r
-BFD04080 0020FC5E LW V0, 32(S8)
-BFD04084 6921 LW V0, 4(V0)
-BFD04086 0014FC7E LW V1, 20(S8)
-BFD0408A 05A7 SUBU V1, V1, V0
-BFD0408C 0024FC5E LW V0, 36(S8)
-BFD04090 6920 LW V0, 0(V0)
-BFD04092 13900043 SLTU V0, V1, V0
-BFD04094 40E21390 ADDI GP, S0, 16610
-BFD04096 001640E2 BEQZC V0, 0xBFD040C6
+BFD04080 0020FC5E LW V0, 32(S8)\r
+BFD04084 6921 LW V0, 4(V0)\r
+BFD04086 0014FC7E LW V1, 20(S8)\r
+BFD0408A 05A7 SUBU V1, V1, V0\r
+BFD0408C 0024FC5E LW V0, 36(S8)\r
+BFD04090 6920 LW V0, 0(V0)\r
+BFD04092 13900043 SLTU V0, V1, V0\r
+BFD04094 40E21390 ADDI GP, S0, 16610\r
+BFD04096 001640E2 BEQZC V0, 0xBFD040C6\r
2619: {\r
2620: /* Not a genuine timeout. Adjust parameters for time remaining. */\r
2621: *pxTicksToWait -= ( xConstTickCount - pxTimeOut->xTimeOnEntering );\r
-BFD0409A 0024FC5E LW V0, 36(S8)
-BFD0409E 69A0 LW V1, 0(V0)
-BFD040A0 0020FC5E LW V0, 32(S8)
-BFD040A4 6A21 LW A0, 4(V0)
-BFD040A6 0014FC5E LW V0, 20(S8)
-BFD040AA 0529 SUBU V0, A0, V0
-BFD040AC 05A6 ADDU V1, V1, V0
-BFD040AE 0024FC5E LW V0, 36(S8)
-BFD040B2 E9A0 SW V1, 0(V0)
+BFD0409A 0024FC5E LW V0, 36(S8)\r
+BFD0409E 69A0 LW V1, 0(V0)\r
+BFD040A0 0020FC5E LW V0, 32(S8)\r
+BFD040A4 6A21 LW A0, 4(V0)\r
+BFD040A6 0014FC5E LW V0, 20(S8)\r
+BFD040AA 0529 SUBU V0, A0, V0\r
+BFD040AC 05A6 ADDU V1, V1, V0\r
+BFD040AE 0024FC5E LW V0, 36(S8)\r
+BFD040B2 E9A0 SW V1, 0(V0)\r
2622: vTaskSetTimeOutState( pxTimeOut );\r
-BFD040B4 0020FC9E LW A0, 32(S8)
-BFD040B8 47A677E8 JALS vTaskSetTimeOutState
-BFD040BC 0C00 NOP
+BFD040B4 0020FC9E LW A0, 32(S8)\r
+BFD040B8 47A677E8 JALS vTaskSetTimeOutState\r
+BFD040BC 0C00 NOP\r
2623: xReturn = pdFALSE;\r
-BFD040BE 0010F81E SW ZERO, 16(S8)
-BFD040C2 CC04 B 0xBFD040CC
-BFD040C4 0C00 NOP
+BFD040BE 0010F81E SW ZERO, 16(S8)\r
+BFD040C2 CC04 B 0xBFD040CC\r
+BFD040C4 0C00 NOP\r
2624: }\r
2625: else\r
2626: {\r
2627: xReturn = pdTRUE;\r
-BFD040C6 ED01 LI V0, 1
-BFD040C8 0010F85E SW V0, 16(S8)
+BFD040C6 ED01 LI V0, 1\r
+BFD040C8 0010F85E SW V0, 16(S8)\r
2628: }\r
2629: }\r
2630: taskEXIT_CRITICAL();\r
-BFD040CC 40AA77E8 JALS vTaskExitCritical
-BFD040CE 0C0040AA BNEZC T2, 0xBFD058D2
-BFD040D0 0C00 NOP
+BFD040CC 40AA77E8 JALS vTaskExitCritical\r
+BFD040CE 0C0040AA BNEZC T2, 0xBFD058D2\r
+BFD040D0 0C00 NOP\r
2631: \r
2632: return xReturn;\r
-BFD040D2 0010FC5E LW V0, 16(S8)
+BFD040D2 0010FC5E LW V0, 16(S8)\r
2633: }\r
-BFD040D6 0FBE MOVE SP, S8
-BFD040D8 4BE7 LW RA, 28(SP)
-BFD040DA 4BC6 LW S8, 24(SP)
-BFD040DC 4C11 ADDIU SP, SP, 32
-BFD040DE 459F JR16 RA
-BFD040E0 0C00 NOP
+BFD040D6 0FBE MOVE SP, S8\r
+BFD040D8 4BE7 LW RA, 28(SP)\r
+BFD040DA 4BC6 LW S8, 24(SP)\r
+BFD040DC 4C11 ADDIU SP, SP, 32\r
+BFD040DE 459F JR16 RA\r
+BFD040E0 0C00 NOP\r
2634: /*-----------------------------------------------------------*/\r
2635: \r
2636: void vTaskMissedYield( void )\r
2637: {\r
-BFD09E54 4FB0 ADDIU SP, SP, -8
-BFD09E56 CBC1 SW S8, 4(SP)
-BFD09E58 0FDD MOVE S8, SP
+BFD09E54 4FB0 ADDIU SP, SP, -8\r
+BFD09E56 CBC1 SW S8, 4(SP)\r
+BFD09E58 0FDD MOVE S8, SP\r
2638: xYieldPending = pdTRUE;\r
-BFD09E5A ED01 LI V0, 1
-BFD09E5C 804CF85C SW V0, -32692(GP)
+BFD09E5A ED01 LI V0, 1\r
+BFD09E5C 804CF85C SW V0, -32692(GP)\r
2639: }\r
-BFD09E60 0FBE MOVE SP, S8
-BFD09E62 4BC1 LW S8, 4(SP)
-BFD09E64 4C05 ADDIU SP, SP, 8
-BFD09E66 459F JR16 RA
-BFD09E68 0C00 NOP
+BFD09E60 0FBE MOVE SP, S8\r
+BFD09E62 4BC1 LW S8, 4(SP)\r
+BFD09E64 4C05 ADDIU SP, SP, 8\r
+BFD09E66 459F JR16 RA\r
+BFD09E68 0C00 NOP\r
2640: /*-----------------------------------------------------------*/\r
2641: \r
2642: #if ( configUSE_TRACE_FACILITY == 1 )\r
2690: */\r
2691: static portTASK_FUNCTION( prvIdleTask, pvParameters )\r
2692: {\r
-BFD08BC4 4FF1 ADDIU SP, SP, -32
-BFD08BC6 CBE7 SW RA, 28(SP)
-BFD08BC8 CBC6 SW S8, 24(SP)
-BFD08BCA 0FDD MOVE S8, SP
-BFD08BCC 0020F89E SW A0, 32(S8)
-BFD08BD0 CC02 B 0xBFD08BD6
-BFD08BD2 0C00 NOP
+BFD08BC4 4FF1 ADDIU SP, SP, -32\r
+BFD08BC6 CBE7 SW RA, 28(SP)\r
+BFD08BC8 CBC6 SW S8, 24(SP)\r
+BFD08BCA 0FDD MOVE S8, SP\r
+BFD08BCC 0020F89E SW A0, 32(S8)\r
+BFD08BD0 CC02 B 0xBFD08BD6\r
+BFD08BD2 0C00 NOP\r
2693: /* Stop warnings. */\r
2694: ( void ) pvParameters;\r
2695: \r
2697: {\r
2698: /* See if any tasks have been deleted. */\r
2699: prvCheckTasksWaitingTermination();\r
-BFD08BD6 35AE77E8 JALS prvCheckTasksWaitingTermination
-BFD08BD8 0C0035AE LHU T5, 3072(T6)
-BFD08BDA 0C00 NOP
+BFD08BD6 35AE77E8 JALS prvCheckTasksWaitingTermination\r
+BFD08BD8 0C0035AE LHU T5, 3072(T6)\r
+BFD08BDA 0C00 NOP\r
2700: \r
2701: #if ( configUSE_PREEMPTION == 0 )\r
2702: {\r
2720: the ready list at the idle priority contains more than one task\r
2721: then a task other than the idle task is ready to execute. */\r
2722: if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )\r
-BFD08BDC BFD241A2 LUI V0, 0xBFD2
-BFD08BDE FC42BFD2 LDC1 F30, -958(S2)
-BFD08BE0 806CFC42 LW V0, -32660(V0)
-BFD08BE4 0002B042 SLTIU V0, V0, 2
-BFD08BE8 FFF440A2 BNEZC V0, 0xBFD08BD4
-BFD08BEA 77E8FFF4 LW RA, 30696(S4)
+BFD08BDC BFD241A2 LUI V0, 0xBFD2\r
+BFD08BDE FC42BFD2 LDC1 F30, -958(S2)\r
+BFD08BE0 806CFC42 LW V0, -32660(V0)\r
+BFD08BE4 0002B042 SLTIU V0, V0, 2\r
+BFD08BE8 FFF440A2 BNEZC V0, 0xBFD08BD4\r
+BFD08BEA 77E8FFF4 LW RA, 30696(S4)\r
2723: {\r
2724: taskYIELD();\r
-BFD08BEC 4E5677E8 JALS ulPortGetCP0Cause
-BFD08BEE 4E56 ADDIU S2, S2, -5
-BFD08BF0 0C00 NOP
-BFD08BF2 0010F85E SW V0, 16(S8)
-BFD08BF6 0010FC5E LW V0, 16(S8)
-BFD08BFA 01005042 ORI V0, V0, 256
-BFD08BFE 0010F85E SW V0, 16(S8)
-BFD08C02 0010FC9E LW A0, 16(S8)
-BFD08C06 4E6677E8 JALS vPortSetCP0Cause
-BFD08C08 4E66 ADDIU S3, S3, 3
-BFD08C0A 0C00 NOP
+BFD08BEC 4E5677E8 JALS ulPortGetCP0Cause\r
+BFD08BEE 4E56 ADDIU S2, S2, -5\r
+BFD08BF0 0C00 NOP\r
+BFD08BF2 0010F85E SW V0, 16(S8)\r
+BFD08BF6 0010FC5E LW V0, 16(S8)\r
+BFD08BFA 01005042 ORI V0, V0, 256\r
+BFD08BFE 0010F85E SW V0, 16(S8)\r
+BFD08C02 0010FC9E LW A0, 16(S8)\r
+BFD08C06 4E6677E8 JALS vPortSetCP0Cause\r
+BFD08C08 4E66 ADDIU S3, S3, 3\r
+BFD08C0A 0C00 NOP\r
2725: }\r
2726: else\r
2727: {\r
2788: }\r
2789: #endif /* configUSE_TICKLESS_IDLE */\r
2790: }\r
-BFD08BD4 0C00 NOP
-BFD08C0C CFE4 B 0xBFD08BD6
-BFD08C0E 0C00 NOP
+BFD08BD4 0C00 NOP\r
+BFD08C0C CFE4 B 0xBFD08BD6\r
+BFD08C0E 0C00 NOP\r
2791: }\r
2792: /*-----------------------------------------------------------*/\r
2793: \r
2833: \r
2834: static void prvInitialiseTCBVariables( TCB_t * const pxTCB, const char * const pcName, UBaseType_t uxPriority, const MemoryRegion_t * const xRegions, const uint16_t usStackDepth ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r
2835: {\r
-BFD03CE8 4FED ADDIU SP, SP, -40
-BFD03CEA CBE9 SW RA, 36(SP)
-BFD03CEC CBC8 SW S8, 32(SP)
-BFD03CEE 0FDD MOVE S8, SP
-BFD03CF0 0028F89E SW A0, 40(S8)
-BFD03CF4 002CF8BE SW A1, 44(S8)
-BFD03CF8 0030F8DE SW A2, 48(S8)
-BFD03CFC 0034F8FE SW A3, 52(S8)
-BFD03D00 0038FC5E LW V0, 56(S8)
-BFD03D04 0018385E SH V0, 24(S8)
+BFD03CE8 4FED ADDIU SP, SP, -40\r
+BFD03CEA CBE9 SW RA, 36(SP)\r
+BFD03CEC CBC8 SW S8, 32(SP)\r
+BFD03CEE 0FDD MOVE S8, SP\r
+BFD03CF0 0028F89E SW A0, 40(S8)\r
+BFD03CF4 002CF8BE SW A1, 44(S8)\r
+BFD03CF8 0030F8DE SW A2, 48(S8)\r
+BFD03CFC 0034F8FE SW A3, 52(S8)\r
+BFD03D00 0038FC5E LW V0, 56(S8)\r
+BFD03D04 0018385E SH V0, 24(S8)\r
2836: UBaseType_t x;\r
2837: \r
2838: /* Store the task name in the TCB. */\r
2839: for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )\r
-BFD03D08 0010F81E SW ZERO, 16(S8)
-BFD03D0A CC1D0010 SHILO null, 16
-BFD03D0C CC1D B 0xBFD03D48
-BFD03D0E 0C00 NOP
-BFD03D3E 0010FC5E LW V0, 16(S8)
-BFD03D42 6D20 ADDIU V0, V0, 1
-BFD03D44 0010F85E SW V0, 16(S8)
-BFD03D48 0010FC5E LW V0, 16(S8)
-BFD03D4C 0008B042 SLTIU V0, V0, 8
-BFD03D50 FFDE40A2 BNEZC V0, 0xBFD03D10
-BFD03D52 CC02FFDE LW S8, -13310(S8)
-BFD03D54 CC02 B 0xBFD03D5A
-BFD03D56 0C00 NOP
+BFD03D08 0010F81E SW ZERO, 16(S8)\r
+BFD03D0A CC1D0010 SHILO null, 16\r
+BFD03D0C CC1D B 0xBFD03D48\r
+BFD03D0E 0C00 NOP\r
+BFD03D3E 0010FC5E LW V0, 16(S8)\r
+BFD03D42 6D20 ADDIU V0, V0, 1\r
+BFD03D44 0010F85E SW V0, 16(S8)\r
+BFD03D48 0010FC5E LW V0, 16(S8)\r
+BFD03D4C 0008B042 SLTIU V0, V0, 8\r
+BFD03D50 FFDE40A2 BNEZC V0, 0xBFD03D10\r
+BFD03D52 CC02FFDE LW S8, -13310(S8)\r
+BFD03D54 CC02 B 0xBFD03D5A\r
+BFD03D56 0C00 NOP\r
2840: {\r
2841: pxTCB->pcTaskName[ x ] = pcName[ x ];\r
-BFD03D10 002CFC7E LW V1, 44(S8)
-BFD03D14 0010FC5E LW V0, 16(S8)
-BFD03D18 0526 ADDU V0, V1, V0
-BFD03D1A 00001C62 LB V1, 0(V0)
-BFD03D1E 0028FC9E LW A0, 40(S8)
-BFD03D22 0010FC5E LW V0, 16(S8)
-BFD03D26 0528 ADDU V0, A0, V0
-BFD03D28 00341862 SB V1, 52(V0)
+BFD03D10 002CFC7E LW V1, 44(S8)\r
+BFD03D14 0010FC5E LW V0, 16(S8)\r
+BFD03D18 0526 ADDU V0, V1, V0\r
+BFD03D1A 00001C62 LB V1, 0(V0)\r
+BFD03D1E 0028FC9E LW A0, 40(S8)\r
+BFD03D22 0010FC5E LW V0, 16(S8)\r
+BFD03D26 0528 ADDU V0, A0, V0\r
+BFD03D28 00341862 SB V1, 52(V0)\r
2842: \r
2843: /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than\r
2844: configMAX_TASK_NAME_LEN characters just in case the memory after the\r
2845: string is not accessible (extremely unlikely). */\r
2846: if( pcName[ x ] == 0x00 )\r
-BFD03D2C 002CFC7E LW V1, 44(S8)
-BFD03D30 0010FC5E LW V0, 16(S8)
-BFD03D34 0526 ADDU V0, V1, V0
-BFD03D36 00001C42 LB V0, 0(V0)
-BFD03D3A 000D40E2 BEQZC V0, 0xBFD03D58
+BFD03D2C 002CFC7E LW V1, 44(S8)\r
+BFD03D30 0010FC5E LW V0, 16(S8)\r
+BFD03D34 0526 ADDU V0, V1, V0\r
+BFD03D36 00001C42 LB V0, 0(V0)\r
+BFD03D3A 000D40E2 BEQZC V0, 0xBFD03D58\r
2847: {\r
2848: break;\r
-BFD03D58 0C00 NOP
+BFD03D58 0C00 NOP\r
2849: }\r
2850: else\r
2851: {\r
2856: /* Ensure the name string is terminated in the case that the string length\r
2857: was greater or equal to configMAX_TASK_NAME_LEN. */\r
2858: pxTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';\r
-BFD03D5A 0028FC5E LW V0, 40(S8)
-BFD03D5E 003B1802 SB ZERO, 59(V0)
+BFD03D5A 0028FC5E LW V0, 40(S8)\r
+BFD03D5E 003B1802 SB ZERO, 59(V0)\r
2859: \r
2860: /* This is used as an array index so must ensure it's not too large. First\r
2861: remove the privilege bit if one is present. */\r
2862: if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )\r
-BFD03D62 0030FC5E LW V0, 48(S8)
-BFD03D66 0005B042 SLTIU V0, V0, 5
-BFD03D6A 000340A2 BNEZC V0, 0xBFD03D74
+BFD03D62 0030FC5E LW V0, 48(S8)\r
+BFD03D66 0005B042 SLTIU V0, V0, 5\r
+BFD03D6A 000340A2 BNEZC V0, 0xBFD03D74\r
2863: {\r
2864: uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;\r
-BFD03D6E ED04 LI V0, 4
-BFD03D70 0030F85E SW V0, 48(S8)
+BFD03D6E ED04 LI V0, 4\r
+BFD03D70 0030F85E SW V0, 48(S8)\r
2865: }\r
2866: else\r
2867: {\r
2869: }\r
2870: \r
2871: pxTCB->uxPriority = uxPriority;\r
-BFD03D74 0028FC5E LW V0, 40(S8)
-BFD03D78 0030FC7E LW V1, 48(S8)
-BFD03D7C E9AB SW V1, 44(V0)
+BFD03D74 0028FC5E LW V0, 40(S8)\r
+BFD03D78 0030FC7E LW V1, 48(S8)\r
+BFD03D7C E9AB SW V1, 44(V0)\r
2872: #if ( configUSE_MUTEXES == 1 )\r
2873: {\r
2874: pxTCB->uxBasePriority = uxPriority;\r
-BFD03D7E 0028FC5E LW V0, 40(S8)
-BFD03D82 0030FC7E LW V1, 48(S8)
-BFD03D86 0040F862 SW V1, 64(V0)
+BFD03D7E 0028FC5E LW V0, 40(S8)\r
+BFD03D82 0030FC7E LW V1, 48(S8)\r
+BFD03D86 0040F862 SW V1, 64(V0)\r
2875: pxTCB->uxMutexesHeld = 0;\r
-BFD03D8A 0028FC5E LW V0, 40(S8)
-BFD03D8E 0044F802 SW ZERO, 68(V0)
+BFD03D8A 0028FC5E LW V0, 40(S8)\r
+BFD03D8E 0044F802 SW ZERO, 68(V0)\r
2876: }\r
2877: #endif /* configUSE_MUTEXES */\r
2878: \r
2879: vListInitialiseItem( &( pxTCB->xGenericListItem ) );\r
-BFD03D92 0028FC5E LW V0, 40(S8)
-BFD03D96 6D22 ADDIU V0, V0, 4
-BFD03D98 0C82 MOVE A0, V0
-BFD03D9A 4EE677E8 JALS vListInitialiseItem
-BFD03D9C 4EE6 ADDIU S7, S7, 3
-BFD03D9E 0C00 NOP
+BFD03D92 0028FC5E LW V0, 40(S8)\r
+BFD03D96 6D22 ADDIU V0, V0, 4\r
+BFD03D98 0C82 MOVE A0, V0\r
+BFD03D9A 4EE677E8 JALS vListInitialiseItem\r
+BFD03D9C 4EE6 ADDIU S7, S7, 3\r
+BFD03D9E 0C00 NOP\r
2880: vListInitialiseItem( &( pxTCB->xEventListItem ) );\r
-BFD03DA0 0028FC5E LW V0, 40(S8)
-BFD03DA2 6D2C0028 EXT AT, T0, 20, 14
-BFD03DA4 6D2C ADDIU V0, V0, 24
-BFD03DA6 0C82 MOVE A0, V0
-BFD03DA8 4EE677E8 JALS vListInitialiseItem
-BFD03DAA 4EE6 ADDIU S7, S7, 3
-BFD03DAC 0C00 NOP
+BFD03DA0 0028FC5E LW V0, 40(S8)\r
+BFD03DA2 6D2C0028 EXT AT, T0, 20, 14\r
+BFD03DA4 6D2C ADDIU V0, V0, 24\r
+BFD03DA6 0C82 MOVE A0, V0\r
+BFD03DA8 4EE677E8 JALS vListInitialiseItem\r
+BFD03DAA 4EE6 ADDIU S7, S7, 3\r
+BFD03DAC 0C00 NOP\r
2881: \r
2882: /* Set the pxTCB as a link back from the ListItem_t. This is so we can get\r
2883: back to the containing TCB from a generic item in a list. */\r
2884: listSET_LIST_ITEM_OWNER( &( pxTCB->xGenericListItem ), pxTCB );\r
-BFD03DAE 0028FC5E LW V0, 40(S8)
-BFD03DB2 0028FC7E LW V1, 40(S8)
-BFD03DB6 E9A4 SW V1, 16(V0)
+BFD03DAE 0028FC5E LW V0, 40(S8)\r
+BFD03DB2 0028FC7E LW V1, 40(S8)\r
+BFD03DB6 E9A4 SW V1, 16(V0)\r
2885: \r
2886: /* Event lists are always in priority order. */\r
2887: listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\r
-BFD03DB8 ED85 LI V1, 5
-BFD03DBA 0030FC5E LW V0, 48(S8)
-BFD03DBE 05A7 SUBU V1, V1, V0
-BFD03DC0 0028FC5E LW V0, 40(S8)
-BFD03DC4 E9A6 SW V1, 24(V0)
+BFD03DB8 ED85 LI V1, 5\r
+BFD03DBA 0030FC5E LW V0, 48(S8)\r
+BFD03DBE 05A7 SUBU V1, V1, V0\r
+BFD03DC0 0028FC5E LW V0, 40(S8)\r
+BFD03DC4 E9A6 SW V1, 24(V0)\r
2888: listSET_LIST_ITEM_OWNER( &( pxTCB->xEventListItem ), pxTCB );\r
-BFD03DC6 0028FC5E LW V0, 40(S8)
-BFD03DCA 0028FC7E LW V1, 40(S8)
-BFD03DCE E9A9 SW V1, 36(V0)
+BFD03DC6 0028FC5E LW V0, 40(S8)\r
+BFD03DCA 0028FC7E LW V1, 40(S8)\r
+BFD03DCE E9A9 SW V1, 36(V0)\r
2889: \r
2890: #if ( portCRITICAL_NESTING_IN_TCB == 1 )\r
2891: {\r
2892: pxTCB->uxCriticalNesting = ( UBaseType_t ) 0U;\r
-BFD03DD0 0028FC5E LW V0, 40(S8)
-BFD03DD4 E82F SW S0, 60(V0)
+BFD03DD0 0028FC5E LW V0, 40(S8)\r
+BFD03DD4 E82F SW S0, 60(V0)\r
2893: }\r
2894: #endif /* portCRITICAL_NESTING_IN_TCB */\r
2895: \r
2928: #if ( configUSE_TASK_NOTIFICATIONS == 1 )\r
2929: {\r
2930: pxTCB->ulNotifiedValue = 0;\r
-BFD03DD6 0028FC5E LW V0, 40(S8)
-BFD03DDA 0048F802 SW ZERO, 72(V0)
+BFD03DD6 0028FC5E LW V0, 40(S8)\r
+BFD03DDA 0048F802 SW ZERO, 72(V0)\r
2931: pxTCB->eNotifyState = eNotWaitingNotification;\r
-BFD03DDE 0028FC5E LW V0, 40(S8)
-BFD03DE2 004CF802 SW ZERO, 76(V0)
+BFD03DDE 0028FC5E LW V0, 40(S8)\r
+BFD03DE2 004CF802 SW ZERO, 76(V0)\r
2932: }\r
2933: #endif\r
2934: \r
2939: }\r
2940: #endif /* configUSE_NEWLIB_REENTRANT */\r
2941: }\r
-BFD03DE6 0FBE MOVE SP, S8
-BFD03DE8 4BE9 LW RA, 36(SP)
-BFD03DEA 4BC8 LW S8, 32(SP)
-BFD03DEC 4C15 ADDIU SP, SP, 40
-BFD03DEE 459F JR16 RA
-BFD03DF0 0C00 NOP
+BFD03DE6 0FBE MOVE SP, S8\r
+BFD03DE8 4BE9 LW RA, 36(SP)\r
+BFD03DEA 4BC8 LW S8, 32(SP)\r
+BFD03DEC 4C15 ADDIU SP, SP, 40\r
+BFD03DEE 459F JR16 RA\r
+BFD03DF0 0C00 NOP\r
2942: /*-----------------------------------------------------------*/\r
2943: \r
2944: #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )\r
2998: \r
2999: static void prvInitialiseTaskLists( void )\r
3000: {\r
-BFD0612C 4FF1 ADDIU SP, SP, -32
-BFD0612E CBE7 SW RA, 28(SP)
-BFD06130 CBC6 SW S8, 24(SP)
-BFD06132 0FDD MOVE S8, SP
+BFD0612C 4FF1 ADDIU SP, SP, -32\r
+BFD0612E CBE7 SW RA, 28(SP)\r
+BFD06130 CBC6 SW S8, 24(SP)\r
+BFD06132 0FDD MOVE S8, SP\r
3001: UBaseType_t uxPriority;\r
3002: \r
3003: for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )\r
-BFD06134 0010F81E SW ZERO, 16(S8)
-BFD06138 CC14 B 0xBFD06162
-BFD0613A 0C00 NOP
-BFD06158 0010FC5E LW V0, 16(S8)
-BFD0615C 6D20 ADDIU V0, V0, 1
-BFD0615E 0010F85E SW V0, 16(S8)
-BFD06162 0010FC5E LW V0, 16(S8)
-BFD06166 0005B042 SLTIU V0, V0, 5
-BFD0616A FFE740A2 BNEZC V0, 0xBFD0613C
-BFD0616C 41A2FFE7 LW RA, 16802(A3)
+BFD06134 0010F81E SW ZERO, 16(S8)\r
+BFD06138 CC14 B 0xBFD06162\r
+BFD0613A 0C00 NOP\r
+BFD06158 0010FC5E LW V0, 16(S8)\r
+BFD0615C 6D20 ADDIU V0, V0, 1\r
+BFD0615E 0010F85E SW V0, 16(S8)\r
+BFD06162 0010FC5E LW V0, 16(S8)\r
+BFD06166 0005B042 SLTIU V0, V0, 5\r
+BFD0616A FFE740A2 BNEZC V0, 0xBFD0613C\r
+BFD0616C 41A2FFE7 LW RA, 16802(A3)\r
3004: {\r
3005: vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );\r
-BFD0613C 0010FC5E LW V0, 16(S8)
-BFD06140 2524 SLL V0, V0, 2
-BFD06142 25A4 SLL V1, V0, 2
-BFD06144 05B4 ADDU V1, V0, V1
-BFD06146 BFD241A2 LUI V0, 0xBFD2
-BFD06148 3042BFD2 LDC1 F30, 12354(S2)
-BFD0614A 806C3042 ADDIU V0, V0, -32660
-BFD0614E 0526 ADDU V0, V1, V0
-BFD06150 0C82 MOVE A0, V0
-BFD06152 457077E8 JALS vListInitialise
-BFD06154 4570 SWM16 0x3, 0(SP)
-BFD06156 0C00 NOP
+BFD0613C 0010FC5E LW V0, 16(S8)\r
+BFD06140 2524 SLL V0, V0, 2\r
+BFD06142 25A4 SLL V1, V0, 2\r
+BFD06144 05B4 ADDU V1, V0, V1\r
+BFD06146 BFD241A2 LUI V0, 0xBFD2\r
+BFD06148 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD0614A 806C3042 ADDIU V0, V0, -32660\r
+BFD0614E 0526 ADDU V0, V1, V0\r
+BFD06150 0C82 MOVE A0, V0\r
+BFD06152 457077E8 JALS vListInitialise\r
+BFD06154 4570 SWM16 0x3, 0(SP)\r
+BFD06156 0C00 NOP\r
3006: }\r
3007: \r
3008: vListInitialise( &xDelayedTaskList1 );\r
-BFD0616E BFD241A2 LUI V0, 0xBFD2
-BFD06170 3082BFD2 LDC1 F30, 12418(S2)
-BFD06172 80F83082 ADDIU A0, V0, -32520
-BFD06176 457077E8 JALS vListInitialise
-BFD06178 4570 SWM16 0x3, 0(SP)
-BFD0617A 0C00 NOP
+BFD0616E BFD241A2 LUI V0, 0xBFD2\r
+BFD06170 3082BFD2 LDC1 F30, 12418(S2)\r
+BFD06172 80F83082 ADDIU A0, V0, -32520\r
+BFD06176 457077E8 JALS vListInitialise\r
+BFD06178 4570 SWM16 0x3, 0(SP)\r
+BFD0617A 0C00 NOP\r
3009: vListInitialise( &xDelayedTaskList2 );\r
-BFD0617C BFD241A2 LUI V0, 0xBFD2
-BFD0617E 3082BFD2 LDC1 F30, 12418(S2)
-BFD06180 81203082 ADDIU A0, V0, -32480
-BFD06184 457077E8 JALS vListInitialise
-BFD06186 4570 SWM16 0x3, 0(SP)
-BFD06188 0C00 NOP
+BFD0617C BFD241A2 LUI V0, 0xBFD2\r
+BFD0617E 3082BFD2 LDC1 F30, 12418(S2)\r
+BFD06180 81203082 ADDIU A0, V0, -32480\r
+BFD06184 457077E8 JALS vListInitialise\r
+BFD06186 4570 SWM16 0x3, 0(SP)\r
+BFD06188 0C00 NOP\r
3010: vListInitialise( &xPendingReadyList );\r
-BFD0618A BFD241A2 LUI V0, 0xBFD2
-BFD0618C 3082BFD2 LDC1 F30, 12418(S2)
-BFD0618E 80D03082 ADDIU A0, V0, -32560
-BFD06192 457077E8 JALS vListInitialise
-BFD06194 4570 SWM16 0x3, 0(SP)
-BFD06196 0C00 NOP
+BFD0618A BFD241A2 LUI V0, 0xBFD2\r
+BFD0618C 3082BFD2 LDC1 F30, 12418(S2)\r
+BFD0618E 80D03082 ADDIU A0, V0, -32560\r
+BFD06192 457077E8 JALS vListInitialise\r
+BFD06194 4570 SWM16 0x3, 0(SP)\r
+BFD06196 0C00 NOP\r
3011: \r
3012: #if ( INCLUDE_vTaskDelete == 1 )\r
3013: {\r
3014: vListInitialise( &xTasksWaitingTermination );\r
-BFD06198 BFD241A2 LUI V0, 0xBFD2
-BFD0619A 3082BFD2 LDC1 F30, 12418(S2)
-BFD0619C 810C3082 ADDIU A0, V0, -32500
-BFD061A0 457077E8 JALS vListInitialise
-BFD061A2 4570 SWM16 0x3, 0(SP)
-BFD061A4 0C00 NOP
+BFD06198 BFD241A2 LUI V0, 0xBFD2\r
+BFD0619A 3082BFD2 LDC1 F30, 12418(S2)\r
+BFD0619C 810C3082 ADDIU A0, V0, -32500\r
+BFD061A0 457077E8 JALS vListInitialise\r
+BFD061A2 4570 SWM16 0x3, 0(SP)\r
+BFD061A4 0C00 NOP\r
3015: }\r
3016: #endif /* INCLUDE_vTaskDelete */\r
3017: \r
3018: #if ( INCLUDE_vTaskSuspend == 1 )\r
3019: {\r
3020: vListInitialise( &xSuspendedTaskList );\r
-BFD061A6 BFD241A2 LUI V0, 0xBFD2
-BFD061A8 3082BFD2 LDC1 F30, 12418(S2)
-BFD061AA 80E43082 ADDIU A0, V0, -32540
-BFD061AE 457077E8 JALS vListInitialise
-BFD061B0 4570 SWM16 0x3, 0(SP)
-BFD061B2 0C00 NOP
+BFD061A6 BFD241A2 LUI V0, 0xBFD2\r
+BFD061A8 3082BFD2 LDC1 F30, 12418(S2)\r
+BFD061AA 80E43082 ADDIU A0, V0, -32540\r
+BFD061AE 457077E8 JALS vListInitialise\r
+BFD061B0 4570 SWM16 0x3, 0(SP)\r
+BFD061B2 0C00 NOP\r
3021: }\r
3022: #endif /* INCLUDE_vTaskSuspend */\r
3023: \r
3024: /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList\r
3025: using list2. */\r
3026: pxDelayedTaskList = &xDelayedTaskList1;\r
-BFD061B4 BFD241A2 LUI V0, 0xBFD2
-BFD061B6 3042BFD2 LDC1 F30, 12354(S2)
-BFD061B8 80F83042 ADDIU V0, V0, -32520
-BFD061BC 8074F85C SW V0, -32652(GP)
+BFD061B4 BFD241A2 LUI V0, 0xBFD2\r
+BFD061B6 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD061B8 80F83042 ADDIU V0, V0, -32520\r
+BFD061BC 8074F85C SW V0, -32652(GP)\r
3027: pxOverflowDelayedTaskList = &xDelayedTaskList2;\r
-BFD061C0 BFD241A2 LUI V0, 0xBFD2
-BFD061C2 3042BFD2 LDC1 F30, 12354(S2)
-BFD061C4 81203042 ADDIU V0, V0, -32480
-BFD061C8 8078F85C SW V0, -32648(GP)
+BFD061C0 BFD241A2 LUI V0, 0xBFD2\r
+BFD061C2 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD061C4 81203042 ADDIU V0, V0, -32480\r
+BFD061C8 8078F85C SW V0, -32648(GP)\r
3028: }\r
-BFD061CC 0FBE MOVE SP, S8
-BFD061CE 4BE7 LW RA, 28(SP)
-BFD061D0 4BC6 LW S8, 24(SP)
-BFD061D2 4C11 ADDIU SP, SP, 32
-BFD061D4 459F JR16 RA
-BFD061D6 0C00 NOP
+BFD061CC 0FBE MOVE SP, S8\r
+BFD061CE 4BE7 LW RA, 28(SP)\r
+BFD061D0 4BC6 LW S8, 24(SP)\r
+BFD061D2 4C11 ADDIU SP, SP, 32\r
+BFD061D4 459F JR16 RA\r
+BFD061D6 0C00 NOP\r
3029: /*-----------------------------------------------------------*/\r
3030: \r
3031: static void prvCheckTasksWaitingTermination( void )\r
3032: {\r
-BFD06B5C 4FF1 ADDIU SP, SP, -32
-BFD06B5E CBE7 SW RA, 28(SP)
-BFD06B60 CBC6 SW S8, 24(SP)
-BFD06B62 0FDD MOVE S8, SP
+BFD06B5C 4FF1 ADDIU SP, SP, -32\r
+BFD06B5E CBE7 SW RA, 28(SP)\r
+BFD06B60 CBC6 SW S8, 24(SP)\r
+BFD06B62 0FDD MOVE S8, SP\r
3033: #if ( INCLUDE_vTaskDelete == 1 )\r
3034: {\r
3035: BaseType_t xListIsEmpty;\r
3037: /* ucTasksDeleted is used to prevent vTaskSuspendAll() being called\r
3038: too often in the idle task. */\r
3039: while( uxTasksDeleted > ( UBaseType_t ) 0U )\r
-BFD06B64 CC37 B 0xBFD06BD4
-BFD06B66 0C00 NOP
-BFD06BD4 8034FC5C LW V0, -32716(GP)
-BFD06BD8 FFC640A2 BNEZC V0, 0xBFD06B68
-BFD06BDA 0FBEFFC6 LW S8, 4030(A2)
+BFD06B64 CC37 B 0xBFD06BD4\r
+BFD06B66 0C00 NOP\r
+BFD06BD4 8034FC5C LW V0, -32716(GP)\r
+BFD06BD8 FFC640A2 BNEZC V0, 0xBFD06B68\r
+BFD06BDA 0FBEFFC6 LW S8, 4030(A2)\r
3040: {\r
3041: vTaskSuspendAll();\r
-BFD06B68 4EF477E8 JALS vTaskSuspendAll
-BFD06B6A 4EF4 ADDIU S7, S7, -6
-BFD06B6C 0C00 NOP
+BFD06B68 4EF477E8 JALS vTaskSuspendAll\r
+BFD06B6A 4EF4 ADDIU S7, S7, -6\r
+BFD06B6C 0C00 NOP\r
3042: {\r
3043: xListIsEmpty = listLIST_IS_EMPTY( &xTasksWaitingTermination );\r
-BFD06B6E BFD241A2 LUI V0, 0xBFD2
-BFD06B70 FC42BFD2 LDC1 F30, -958(S2)
-BFD06B72 810CFC42 LW V0, -32500(V0)
-BFD06B76 0001B042 SLTIU V0, V0, 1
-BFD06B7A 0010F85E SW V0, 16(S8)
+BFD06B6E BFD241A2 LUI V0, 0xBFD2\r
+BFD06B70 FC42BFD2 LDC1 F30, -958(S2)\r
+BFD06B72 810CFC42 LW V0, -32500(V0)\r
+BFD06B76 0001B042 SLTIU V0, V0, 1\r
+BFD06B7A 0010F85E SW V0, 16(S8)\r
3044: }\r
3045: ( void ) xTaskResumeAll();\r
-BFD06B7E 158E77E8 JALS xTaskResumeAll
-BFD06B80 0C00158E LBU T4, 3072(T6)
-BFD06B82 0C00 NOP
+BFD06B7E 158E77E8 JALS xTaskResumeAll\r
+BFD06B80 0C00158E LBU T4, 3072(T6)\r
+BFD06B82 0C00 NOP\r
3046: \r
3047: if( xListIsEmpty == pdFALSE )\r
-BFD06B84 0010FC5E LW V0, 16(S8)
-BFD06B88 002440A2 BNEZC V0, 0xBFD06BD4
+BFD06B84 0010FC5E LW V0, 16(S8)\r
+BFD06B88 002440A2 BNEZC V0, 0xBFD06BD4\r
3048: {\r
3049: TCB_t *pxTCB;\r
3050: \r
3051: taskENTER_CRITICAL();\r
-BFD06B8C 33B877E8 JALS vTaskEnterCritical
-BFD06B8E 0C0033B8 ADDIU SP, T8, 3072
-BFD06B90 0C00 NOP
+BFD06B8C 33B877E8 JALS vTaskEnterCritical\r
+BFD06B8E 0C0033B8 ADDIU SP, T8, 3072\r
+BFD06B90 0C00 NOP\r
3052: {\r
3053: pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) );\r
-BFD06B92 BFD241A2 LUI V0, 0xBFD2
-BFD06B94 3042BFD2 LDC1 F30, 12354(S2)
-BFD06B96 810C3042 ADDIU V0, V0, -32500
-BFD06B9A 6923 LW V0, 12(V0)
-BFD06B9C 6923 LW V0, 12(V0)
-BFD06B9E 0014F85E SW V0, 20(S8)
+BFD06B92 BFD241A2 LUI V0, 0xBFD2\r
+BFD06B94 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD06B96 810C3042 ADDIU V0, V0, -32500\r
+BFD06B9A 6923 LW V0, 12(V0)\r
+BFD06B9C 6923 LW V0, 12(V0)\r
+BFD06B9E 0014F85E SW V0, 20(S8)\r
3054: ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );\r
-BFD06BA2 0014FC5E LW V0, 20(S8)
-BFD06BA6 6D22 ADDIU V0, V0, 4
-BFD06BA8 0C82 MOVE A0, V0
-BFD06BAA 00C877E8 JALS uxListRemove
-BFD06BAC 0C0000C8 SLL A2, T0, 1
-BFD06BAE 0C00 NOP
+BFD06BA2 0014FC5E LW V0, 20(S8)\r
+BFD06BA6 6D22 ADDIU V0, V0, 4\r
+BFD06BA8 0C82 MOVE A0, V0\r
+BFD06BAA 00C877E8 JALS uxListRemove\r
+BFD06BAC 0C0000C8 SLL A2, T0, 1\r
+BFD06BAE 0C00 NOP\r
3055: --uxCurrentNumberOfTasks;\r
-BFD06BB0 8038FC5C LW V0, -32712(GP)
-BFD06BB4 6D2E ADDIU V0, V0, -1
-BFD06BB6 8038F85C SW V0, -32712(GP)
+BFD06BB0 8038FC5C LW V0, -32712(GP)\r
+BFD06BB4 6D2E ADDIU V0, V0, -1\r
+BFD06BB6 8038F85C SW V0, -32712(GP)\r
3056: --uxTasksDeleted;\r
-BFD06BBA 8034FC5C LW V0, -32716(GP)
-BFD06BBE 6D2E ADDIU V0, V0, -1
-BFD06BC0 8034F85C SW V0, -32716(GP)
+BFD06BBA 8034FC5C LW V0, -32716(GP)\r
+BFD06BBE 6D2E ADDIU V0, V0, -1\r
+BFD06BC0 8034F85C SW V0, -32716(GP)\r
3057: }\r
3058: taskEXIT_CRITICAL();\r
-BFD06BC4 40AA77E8 JALS vTaskExitCritical
-BFD06BC6 0C0040AA BNEZC T2, 0xBFD083CA
-BFD06BC8 0C00 NOP
+BFD06BC4 40AA77E8 JALS vTaskExitCritical\r
+BFD06BC6 0C0040AA BNEZC T2, 0xBFD083CA\r
+BFD06BC8 0C00 NOP\r
3059: \r
3060: prvDeleteTCB( pxTCB );\r
-BFD06BCA 0014FC9E LW A0, 20(S8)
-BFD06BCE 4C6E77E8 JALS prvDeleteTCB
-BFD06BD0 4C6E ADDIU V1, V1, 7
-BFD06BD2 0C00 NOP
+BFD06BCA 0014FC9E LW A0, 20(S8)\r
+BFD06BCE 4C6E77E8 JALS prvDeleteTCB\r
+BFD06BD0 4C6E ADDIU V1, V1, 7\r
+BFD06BD2 0C00 NOP\r
3061: }\r
3062: else\r
3063: {\r
3067: }\r
3068: #endif /* vTaskDelete */\r
3069: }\r
-BFD06BDC 0FBE MOVE SP, S8
-BFD06BDE 4BE7 LW RA, 28(SP)
-BFD06BE0 4BC6 LW S8, 24(SP)
-BFD06BE2 4C11 ADDIU SP, SP, 32
-BFD06BE4 459F JR16 RA
-BFD06BE6 0C00 NOP
+BFD06BDC 0FBE MOVE SP, S8\r
+BFD06BDE 4BE7 LW RA, 28(SP)\r
+BFD06BE0 4BC6 LW S8, 24(SP)\r
+BFD06BE2 4C11 ADDIU SP, SP, 32\r
+BFD06BE4 459F JR16 RA\r
+BFD06BE6 0C00 NOP\r
3070: /*-----------------------------------------------------------*/\r
3071: \r
3072: static void prvAddCurrentTaskToDelayedList( const TickType_t xTimeToWake )\r
3073: {\r
-BFD06E68 4FF5 ADDIU SP, SP, -24
-BFD06E6A CBE5 SW RA, 20(SP)
-BFD06E6C CBC4 SW S8, 16(SP)
-BFD06E6E 0FDD MOVE S8, SP
-BFD06E70 0018F89E SW A0, 24(S8)
+BFD06E68 4FF5 ADDIU SP, SP, -24\r
+BFD06E6A CBE5 SW RA, 20(SP)\r
+BFD06E6C CBC4 SW S8, 16(SP)\r
+BFD06E6E 0FDD MOVE S8, SP\r
+BFD06E70 0018F89E SW A0, 24(S8)\r
3074: /* The list item will be inserted in wake time order. */\r
3075: listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake );\r
-BFD06E74 8030FC5C LW V0, -32720(GP)
-BFD06E78 0018FC7E LW V1, 24(S8)
-BFD06E7C E9A1 SW V1, 4(V0)
+BFD06E74 8030FC5C LW V0, -32720(GP)\r
+BFD06E78 0018FC7E LW V1, 24(S8)\r
+BFD06E7C E9A1 SW V1, 4(V0)\r
3076: \r
3077: if( xTimeToWake < xTickCount )\r
-BFD06E7E 803CFC5C LW V0, -32708(GP)
-BFD06E82 0018FC7E LW V1, 24(S8)
-BFD06E86 13900043 SLTU V0, V1, V0
-BFD06E88 40E21390 ADDI GP, S0, 16610
-BFD06E8A 000C40E2 BEQZC V0, 0xBFD06EA6
+BFD06E7E 803CFC5C LW V0, -32708(GP)\r
+BFD06E82 0018FC7E LW V1, 24(S8)\r
+BFD06E86 13900043 SLTU V0, V1, V0\r
+BFD06E88 40E21390 ADDI GP, S0, 16610\r
+BFD06E8A 000C40E2 BEQZC V0, 0xBFD06EA6\r
3078: {\r
3079: /* Wake time has overflowed. Place this item in the overflow list. */\r
3080: vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xGenericListItem ) );\r
-BFD06E8E 8078FC7C LW V1, -32648(GP)
-BFD06E92 8030FC5C LW V0, -32720(GP)
-BFD06E96 6D22 ADDIU V0, V0, 4
-BFD06E98 0C83 MOVE A0, V1
-BFD06E9A 0CA2 MOVE A1, V0
-BFD06E9C 304077E8 JALS vListInsert
-BFD06E9E 0C003040 ADDIU V0, ZERO, 3072
-BFD06EA0 0C00 NOP
-BFD06EA2 CC17 B 0xBFD06ED2
-BFD06EA4 0C00 NOP
+BFD06E8E 8078FC7C LW V1, -32648(GP)\r
+BFD06E92 8030FC5C LW V0, -32720(GP)\r
+BFD06E96 6D22 ADDIU V0, V0, 4\r
+BFD06E98 0C83 MOVE A0, V1\r
+BFD06E9A 0CA2 MOVE A1, V0\r
+BFD06E9C 304077E8 JALS vListInsert\r
+BFD06E9E 0C003040 ADDIU V0, ZERO, 3072\r
+BFD06EA0 0C00 NOP\r
+BFD06EA2 CC17 B 0xBFD06ED2\r
+BFD06EA4 0C00 NOP\r
3081: }\r
3082: else\r
3083: {\r
3084: /* The wake time has not overflowed, so the current block list is used. */\r
3085: vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xGenericListItem ) );\r
-BFD06EA6 8074FC7C LW V1, -32652(GP)
-BFD06EAA 8030FC5C LW V0, -32720(GP)
-BFD06EAE 6D22 ADDIU V0, V0, 4
-BFD06EB0 0C83 MOVE A0, V1
-BFD06EB2 0CA2 MOVE A1, V0
-BFD06EB4 304077E8 JALS vListInsert
-BFD06EB6 0C003040 ADDIU V0, ZERO, 3072
-BFD06EB8 0C00 NOP
+BFD06EA6 8074FC7C LW V1, -32652(GP)\r
+BFD06EAA 8030FC5C LW V0, -32720(GP)\r
+BFD06EAE 6D22 ADDIU V0, V0, 4\r
+BFD06EB0 0C83 MOVE A0, V1\r
+BFD06EB2 0CA2 MOVE A1, V0\r
+BFD06EB4 304077E8 JALS vListInsert\r
+BFD06EB6 0C003040 ADDIU V0, ZERO, 3072\r
+BFD06EB8 0C00 NOP\r
3086: \r
3087: /* If the task entering the blocked state was placed at the head of the\r
3088: list of blocked tasks then xNextTaskUnblockTime needs to be updated\r
3089: too. */\r
3090: if( xTimeToWake < xNextTaskUnblockTime )\r
-BFD06EBA 8058FC5C LW V0, -32680(GP)
-BFD06EBE 0018FC7E LW V1, 24(S8)
-BFD06EC2 13900043 SLTU V0, V1, V0
-BFD06EC4 40E21390 ADDI GP, S0, 16610
-BFD06EC6 000440E2 BEQZC V0, 0xBFD06ED2
+BFD06EBA 8058FC5C LW V0, -32680(GP)\r
+BFD06EBE 0018FC7E LW V1, 24(S8)\r
+BFD06EC2 13900043 SLTU V0, V1, V0\r
+BFD06EC4 40E21390 ADDI GP, S0, 16610\r
+BFD06EC6 000440E2 BEQZC V0, 0xBFD06ED2\r
3091: {\r
3092: xNextTaskUnblockTime = xTimeToWake;\r
-BFD06ECA 0018FC5E LW V0, 24(S8)
-BFD06ECE 8058F85C SW V0, -32680(GP)
+BFD06ECA 0018FC5E LW V0, 24(S8)\r
+BFD06ECE 8058F85C SW V0, -32680(GP)\r
3093: }\r
3094: else\r
3095: {\r
3097: }\r
3098: }\r
3099: }\r
-BFD06ED2 0FBE MOVE SP, S8
-BFD06ED4 4BE5 LW RA, 20(SP)
-BFD06ED6 4BC4 LW S8, 16(SP)
-BFD06ED8 4C0D ADDIU SP, SP, 24
-BFD06EDA 459F JR16 RA
-BFD06EDC 0C00 NOP
+BFD06ED2 0FBE MOVE SP, S8\r
+BFD06ED4 4BE5 LW RA, 20(SP)\r
+BFD06ED6 4BC4 LW S8, 16(SP)\r
+BFD06ED8 4C0D ADDIU SP, SP, 24\r
+BFD06EDA 459F JR16 RA\r
+BFD06EDC 0C00 NOP\r
3100: /*-----------------------------------------------------------*/\r
3101: \r
3102: static TCB_t *prvAllocateTCBAndStack( const uint16_t usStackDepth, StackType_t * const puxStackBuffer )\r
3103: {\r
-BFD06328 4FF1 ADDIU SP, SP, -32
-BFD0632A CBE7 SW RA, 28(SP)
-BFD0632C CBC6 SW S8, 24(SP)
-BFD0632E 0FDD MOVE S8, SP
-BFD06330 0C44 MOVE V0, A0
-BFD06332 0024F8BE SW A1, 36(S8)
-BFD06336 0020385E SH V0, 32(S8)
+BFD06328 4FF1 ADDIU SP, SP, -32\r
+BFD0632A CBE7 SW RA, 28(SP)\r
+BFD0632C CBC6 SW S8, 24(SP)\r
+BFD0632E 0FDD MOVE S8, SP\r
+BFD06330 0C44 MOVE V0, A0\r
+BFD06332 0024F8BE SW A1, 36(S8)\r
+BFD06336 0020385E SH V0, 32(S8)\r
3104: TCB_t *pxNewTCB;\r
3105: \r
3106: /* If the stack grows down then allocate the stack then the TCB so the stack\r
3133: \r
3134: /* Allocate space for the stack used by the task being created. */\r
3135: pxStack = ( StackType_t * ) pvPortMallocAligned( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ), puxStackBuffer ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\r
-BFD0633A 0024FC5E LW V0, 36(S8)
-BFD0633E 000940A2 BNEZC V0, 0xBFD06354
-BFD06342 0020345E LHU V0, 32(S8)
-BFD06346 2524 SLL V0, V0, 2
-BFD06348 0C82 MOVE A0, V0
-BFD0634A 111677E8 JALS pvPortMalloc
-BFD0634C 0C001116 ADDI T0, S6, 3072
-BFD0634E 0C00 NOP
-BFD06350 CC03 B 0xBFD06358
-BFD06352 0C00 NOP
-BFD06354 0024FC5E LW V0, 36(S8)
-BFD06358 0014F85E SW V0, 20(S8)
+BFD0633A 0024FC5E LW V0, 36(S8)\r
+BFD0633E 000940A2 BNEZC V0, 0xBFD06354\r
+BFD06342 0020345E LHU V0, 32(S8)\r
+BFD06346 2524 SLL V0, V0, 2\r
+BFD06348 0C82 MOVE A0, V0\r
+BFD0634A 111677E8 JALS pvPortMalloc\r
+BFD0634C 0C001116 ADDI T0, S6, 3072\r
+BFD0634E 0C00 NOP\r
+BFD06350 CC03 B 0xBFD06358\r
+BFD06352 0C00 NOP\r
+BFD06354 0024FC5E LW V0, 36(S8)\r
+BFD06358 0014F85E SW V0, 20(S8)\r
3136: \r
3137: if( pxStack != NULL )\r
-BFD0635C 0014FC5E LW V0, 20(S8)
-BFD06360 001840E2 BEQZC V0, 0xBFD06394
-BFD06362 EE500018 AND SP, T8, ZERO
+BFD0635C 0014FC5E LW V0, 20(S8)\r
+BFD06360 001840E2 BEQZC V0, 0xBFD06394\r
+BFD06362 EE500018 AND SP, T8, ZERO\r
3138: {\r
3139: /* Allocate space for the TCB. Where the memory comes from depends\r
3140: on the implementation of the port malloc function. */\r
3141: pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );\r
-BFD06364 EE50 LI A0, 80
-BFD06366 111677E8 JALS pvPortMalloc
-BFD06368 0C001116 ADDI T0, S6, 3072
-BFD0636A 0C00 NOP
-BFD0636C 0010F85E SW V0, 16(S8)
+BFD06364 EE50 LI A0, 80\r
+BFD06366 111677E8 JALS pvPortMalloc\r
+BFD06368 0C001116 ADDI T0, S6, 3072\r
+BFD0636A 0C00 NOP\r
+BFD0636C 0010F85E SW V0, 16(S8)\r
3142: \r
3143: if( pxNewTCB != NULL )\r
-BFD06370 0010FC5E LW V0, 16(S8)
-BFD06374 000740E2 BEQZC V0, 0xBFD06386
+BFD06370 0010FC5E LW V0, 16(S8)\r
+BFD06374 000740E2 BEQZC V0, 0xBFD06386\r
3144: {\r
3145: /* Store the stack location in the TCB. */\r
3146: pxNewTCB->pxStack = pxStack;\r
-BFD06378 0010FC5E LW V0, 16(S8)
-BFD0637C 0014FC7E LW V1, 20(S8)
-BFD0637E E9AC0014 EXT ZERO, S4, 6, 30
-BFD06380 E9AC SW V1, 48(V0)
-BFD06382 CC0A B 0xBFD06398
-BFD06384 0C00 NOP
+BFD06378 0010FC5E LW V0, 16(S8)\r
+BFD0637C 0014FC7E LW V1, 20(S8)\r
+BFD0637E E9AC0014 EXT ZERO, S4, 6, 30\r
+BFD06380 E9AC SW V1, 48(V0)\r
+BFD06382 CC0A B 0xBFD06398\r
+BFD06384 0C00 NOP\r
3147: }\r
3148: else\r
3149: {\r
3150: /* The stack cannot be used as the TCB was not created. Free it\r
3151: again. */\r
3152: vPortFree( pxStack );\r
-BFD06386 0014FC9E LW A0, 20(S8)
-BFD0638A 2FEA77E8 JALS vPortFree
-BFD0638C 2FEA ANDI A3, A2, 0x20
-BFD0638E 0C00 NOP
-BFD06390 CC03 B 0xBFD06398
-BFD06392 0C00 NOP
+BFD06386 0014FC9E LW A0, 20(S8)\r
+BFD0638A 2FEA77E8 JALS vPortFree\r
+BFD0638C 2FEA ANDI A3, A2, 0x20\r
+BFD0638E 0C00 NOP\r
+BFD06390 CC03 B 0xBFD06398\r
+BFD06392 0C00 NOP\r
3153: }\r
3154: }\r
3155: else\r
3156: {\r
3157: pxNewTCB = NULL;\r
-BFD06394 0010F81E SW ZERO, 16(S8)
+BFD06394 0010F81E SW ZERO, 16(S8)\r
3158: }\r
3159: }\r
3160: #endif /* portSTACK_GROWTH */\r
3161: \r
3162: if( pxNewTCB != NULL )\r
-BFD06398 0010FC5E LW V0, 16(S8)
-BFD0639C 000D40E2 BEQZC V0, 0xBFD063BA
+BFD06398 0010FC5E LW V0, 16(S8)\r
+BFD0639C 000D40E2 BEQZC V0, 0xBFD063BA\r
3163: {\r
3164: /* Avoid dependency on memset() if it is not required. */\r
3165: #if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )\r
3166: {\r
3167: /* Just to help debugging. */\r
3168: ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) usStackDepth * sizeof( StackType_t ) );\r
-BFD063A0 0010FC5E LW V0, 16(S8)
-BFD063A2 69AC0010 EXT ZERO, S0, 6, 14
-BFD063A4 69AC LW V1, 48(V0)
-BFD063A6 0020345E LHU V0, 32(S8)
-BFD063AA 2524 SLL V0, V0, 2
-BFD063AC 0C83 MOVE A0, V1
-BFD063AE 00A530A0 ADDIU A1, ZERO, 165
-BFD063B2 0CC2 MOVE A2, V0
-BFD063B4 36F677E8 JALS 0xBFD06DEC
-BFD063B6 0C0036F6 LHU S7, 3072(S6)
-BFD063B8 0C00 NOP
+BFD063A0 0010FC5E LW V0, 16(S8)\r
+BFD063A2 69AC0010 EXT ZERO, S0, 6, 14\r
+BFD063A4 69AC LW V1, 48(V0)\r
+BFD063A6 0020345E LHU V0, 32(S8)\r
+BFD063AA 2524 SLL V0, V0, 2\r
+BFD063AC 0C83 MOVE A0, V1\r
+BFD063AE 00A530A0 ADDIU A1, ZERO, 165\r
+BFD063B2 0CC2 MOVE A2, V0\r
+BFD063B4 36F677E8 JALS 0xBFD06DEC\r
+BFD063B6 0C0036F6 LHU S7, 3072(S6)\r
+BFD063B8 0C00 NOP\r
3169: }\r
3170: #endif /* ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) ) ) */\r
3171: }\r
3172: \r
3173: return pxNewTCB;\r
-BFD063BA 0010FC5E LW V0, 16(S8)
+BFD063BA 0010FC5E LW V0, 16(S8)\r
3174: }\r
-BFD063BE 0FBE MOVE SP, S8
-BFD063C0 4BE7 LW RA, 28(SP)
-BFD063C2 4BC6 LW S8, 24(SP)
-BFD063C4 4C11 ADDIU SP, SP, 32
-BFD063C6 459F JR16 RA
-BFD063C8 0C00 NOP
+BFD063BE 0FBE MOVE SP, S8\r
+BFD063C0 4BE7 LW RA, 28(SP)\r
+BFD063C2 4BC6 LW S8, 24(SP)\r
+BFD063C4 4C11 ADDIU SP, SP, 32\r
+BFD063C6 459F JR16 RA\r
+BFD063C8 0C00 NOP\r
3175: /*-----------------------------------------------------------*/\r
3176: \r
3177: #if ( configUSE_TRACE_FACILITY == 1 )\r
3263: \r
3264: static uint16_t prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )\r
3265: {\r
-BFD089A4 4FF9 ADDIU SP, SP, -16
-BFD089A6 CBC3 SW S8, 12(SP)
-BFD089A8 0FDD MOVE S8, SP
-BFD089AA 0010F89E SW A0, 16(S8)
+BFD089A4 4FF9 ADDIU SP, SP, -16\r
+BFD089A6 CBC3 SW S8, 12(SP)\r
+BFD089A8 0FDD MOVE S8, SP\r
+BFD089AA 0010F89E SW A0, 16(S8)\r
3266: uint32_t ulCount = 0U;\r
-BFD089AE 0000F81E SW ZERO, 0(S8)
+BFD089AE 0000F81E SW ZERO, 0(S8)\r
3267: \r
3268: while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )\r
-BFD089B2 CC0B B 0xBFD089CA
-BFD089B4 0C00 NOP
-BFD089CA 0010FC5E LW V0, 16(S8)
-BFD089CE 09A0 LBU V1, 0(V0)
-BFD089D0 00A53040 ADDIU V0, ZERO, 165
-BFD089D4 FFEF9443 BEQ V1, V0, 0xBFD089B6
-BFD089D6 0C00FFEF LW RA, 3072(T7)
-BFD089D8 0C00 NOP
+BFD089B2 CC0B B 0xBFD089CA\r
+BFD089B4 0C00 NOP\r
+BFD089CA 0010FC5E LW V0, 16(S8)\r
+BFD089CE 09A0 LBU V1, 0(V0)\r
+BFD089D0 00A53040 ADDIU V0, ZERO, 165\r
+BFD089D4 FFEF9443 BEQ V1, V0, 0xBFD089B6\r
+BFD089D6 0C00FFEF LW RA, 3072(T7)\r
+BFD089D8 0C00 NOP\r
3269: {\r
3270: pucStackByte -= portSTACK_GROWTH;\r
-BFD089B6 0010FC5E LW V0, 16(S8)
-BFD089BA 6D20 ADDIU V0, V0, 1
-BFD089BC 0010F85E SW V0, 16(S8)
+BFD089B6 0010FC5E LW V0, 16(S8)\r
+BFD089BA 6D20 ADDIU V0, V0, 1\r
+BFD089BC 0010F85E SW V0, 16(S8)\r
3271: ulCount++;\r
-BFD089C0 0000FC5E LW V0, 0(S8)
-BFD089C4 6D20 ADDIU V0, V0, 1
-BFD089C6 0000F85E SW V0, 0(S8)
+BFD089C0 0000FC5E LW V0, 0(S8)\r
+BFD089C4 6D20 ADDIU V0, V0, 1\r
+BFD089C6 0000F85E SW V0, 0(S8)\r
3272: }\r
3273: \r
3274: ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */\r
-BFD089DA 0000FC5E LW V0, 0(S8)
-BFD089DE 2525 SRL V0, V0, 2
-BFD089E0 0000F85E SW V0, 0(S8)
+BFD089DA 0000FC5E LW V0, 0(S8)\r
+BFD089DE 2525 SRL V0, V0, 2\r
+BFD089E0 0000F85E SW V0, 0(S8)\r
3275: \r
3276: return ( uint16_t ) ulCount;\r
-BFD089E4 0000FC5E LW V0, 0(S8)
-BFD089E8 2D2F ANDI V0, V0, 0xFFFF
+BFD089E4 0000FC5E LW V0, 0(S8)\r
+BFD089E8 2D2F ANDI V0, V0, 0xFFFF\r
3277: }\r
-BFD089EA 0FBE MOVE SP, S8
-BFD089EC 4BC3 LW S8, 12(SP)
-BFD089EE 4C09 ADDIU SP, SP, 16
-BFD089F0 459F JR16 RA
-BFD089F2 0C00 NOP
+BFD089EA 0FBE MOVE SP, S8\r
+BFD089EC 4BC3 LW S8, 12(SP)\r
+BFD089EE 4C09 ADDIU SP, SP, 16\r
+BFD089F0 459F JR16 RA\r
+BFD089F2 0C00 NOP\r
3278: \r
3279: #endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) ) */\r
3280: /*-----------------------------------------------------------*/\r
3283: \r
3284: UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask )\r
3285: {\r
-BFD08C10 4FED ADDIU SP, SP, -40
-BFD08C12 CBE9 SW RA, 36(SP)
-BFD08C14 CBC8 SW S8, 32(SP)
-BFD08C16 0FDD MOVE S8, SP
-BFD08C18 0028F89E SW A0, 40(S8)
+BFD08C10 4FED ADDIU SP, SP, -40\r
+BFD08C12 CBE9 SW RA, 36(SP)\r
+BFD08C14 CBC8 SW S8, 32(SP)\r
+BFD08C16 0FDD MOVE S8, SP\r
+BFD08C18 0028F89E SW A0, 40(S8)\r
3286: TCB_t *pxTCB;\r
3287: uint8_t *pucEndOfStack;\r
3288: UBaseType_t uxReturn;\r
3289: \r
3290: pxTCB = prvGetTCBFromHandle( xTask );\r
-BFD08C1C 0028FC5E LW V0, 40(S8)
-BFD08C20 000440A2 BNEZC V0, 0xBFD08C2C
-BFD08C24 8030FC5C LW V0, -32720(GP)
-BFD08C28 CC03 B 0xBFD08C30
-BFD08C2A 0C00 NOP
-BFD08C2C 0028FC5E LW V0, 40(S8)
-BFD08C30 0010F85E SW V0, 16(S8)
+BFD08C1C 0028FC5E LW V0, 40(S8)\r
+BFD08C20 000440A2 BNEZC V0, 0xBFD08C2C\r
+BFD08C24 8030FC5C LW V0, -32720(GP)\r
+BFD08C28 CC03 B 0xBFD08C30\r
+BFD08C2A 0C00 NOP\r
+BFD08C2C 0028FC5E LW V0, 40(S8)\r
+BFD08C30 0010F85E SW V0, 16(S8)\r
3291: \r
3292: #if portSTACK_GROWTH < 0\r
3293: {\r
3294: pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;\r
-BFD08C34 0010FC5E LW V0, 16(S8)
-BFD08C36 692C0010 EXT ZERO, S0, 4, 14
-BFD08C38 692C LW V0, 48(V0)
-BFD08C3A 0014F85E SW V0, 20(S8)
+BFD08C34 0010FC5E LW V0, 16(S8)\r
+BFD08C36 692C0010 EXT ZERO, S0, 4, 14\r
+BFD08C38 692C LW V0, 48(V0)\r
+BFD08C3A 0014F85E SW V0, 20(S8)\r
3295: }\r
3296: #else\r
3297: {\r
3300: #endif\r
3301: \r
3302: uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );\r
-BFD08C3E 0014FC9E LW A0, 20(S8)
-BFD08C42 44D277E8 JALS prvTaskCheckFreeStackSpace
-BFD08C44 44D2 OR16 V0, V0
-BFD08C46 0C00 NOP
-BFD08C48 0018F85E SW V0, 24(S8)
+BFD08C3E 0014FC9E LW A0, 20(S8)\r
+BFD08C42 44D277E8 JALS prvTaskCheckFreeStackSpace\r
+BFD08C44 44D2 OR16 V0, V0\r
+BFD08C46 0C00 NOP\r
+BFD08C48 0018F85E SW V0, 24(S8)\r
3303: \r
3304: return uxReturn;\r
-BFD08C4C 0018FC5E LW V0, 24(S8)
+BFD08C4C 0018FC5E LW V0, 24(S8)\r
3305: }\r
-BFD08C50 0FBE MOVE SP, S8
-BFD08C52 4BE9 LW RA, 36(SP)
-BFD08C54 4BC8 LW S8, 32(SP)
-BFD08C56 4C15 ADDIU SP, SP, 40
-BFD08C58 459F JR16 RA
-BFD08C5A 0C00 NOP
+BFD08C50 0FBE MOVE SP, S8\r
+BFD08C52 4BE9 LW RA, 36(SP)\r
+BFD08C54 4BC8 LW S8, 32(SP)\r
+BFD08C56 4C15 ADDIU SP, SP, 40\r
+BFD08C58 459F JR16 RA\r
+BFD08C5A 0C00 NOP\r
3306: \r
3307: #endif /* INCLUDE_uxTaskGetStackHighWaterMark */\r
3308: /*-----------------------------------------------------------*/\r
3311: \r
3312: static void prvDeleteTCB( TCB_t *pxTCB )\r
3313: {\r
-BFD098DC 4FF5 ADDIU SP, SP, -24
-BFD098DE CBE5 SW RA, 20(SP)
-BFD098E0 CBC4 SW S8, 16(SP)
-BFD098E2 0FDD MOVE S8, SP
-BFD098E4 0018F89E SW A0, 24(S8)
+BFD098DC 4FF5 ADDIU SP, SP, -24\r
+BFD098DE CBE5 SW RA, 20(SP)\r
+BFD098E0 CBC4 SW S8, 16(SP)\r
+BFD098E2 0FDD MOVE S8, SP\r
+BFD098E4 0018F89E SW A0, 24(S8)\r
3314: /* This call is required specifically for the TriCore port. It must be\r
3315: above the vPortFree() calls. The call is also used by ports/demos that\r
3316: want to allocate and clean RAM statically. */\r
3336: #else\r
3337: {\r
3338: vPortFreeAligned( pxTCB->pxStack );\r
-BFD098E8 0018FC5E LW V0, 24(S8)
-BFD098EA 692C0018 EXT ZERO, T8, 4, 14
-BFD098EC 692C LW V0, 48(V0)
-BFD098EE 0C82 MOVE A0, V0
-BFD098F0 2FEA77E8 JALS vPortFree
-BFD098F2 2FEA ANDI A3, A2, 0x20
-BFD098F4 0C00 NOP
+BFD098E8 0018FC5E LW V0, 24(S8)\r
+BFD098EA 692C0018 EXT ZERO, T8, 4, 14\r
+BFD098EC 692C LW V0, 48(V0)\r
+BFD098EE 0C82 MOVE A0, V0\r
+BFD098F0 2FEA77E8 JALS vPortFree\r
+BFD098F2 2FEA ANDI A3, A2, 0x20\r
+BFD098F4 0C00 NOP\r
3339: }\r
3340: #endif\r
3341: \r
3342: vPortFree( pxTCB );\r
-BFD098F6 0018FC9E LW A0, 24(S8)
-BFD098FA 2FEA77E8 JALS vPortFree
-BFD098FC 2FEA ANDI A3, A2, 0x20
-BFD098FE 0C00 NOP
+BFD098F6 0018FC9E LW A0, 24(S8)\r
+BFD098FA 2FEA77E8 JALS vPortFree\r
+BFD098FC 2FEA ANDI A3, A2, 0x20\r
+BFD098FE 0C00 NOP\r
3343: }\r
-BFD09900 0FBE MOVE SP, S8
-BFD09902 4BE5 LW RA, 20(SP)
-BFD09904 4BC4 LW S8, 16(SP)
-BFD09906 4C0D ADDIU SP, SP, 24
-BFD09908 459F JR16 RA
-BFD0990A 0C00 NOP
+BFD09900 0FBE MOVE SP, S8\r
+BFD09902 4BE5 LW RA, 20(SP)\r
+BFD09904 4BC4 LW S8, 16(SP)\r
+BFD09906 4C0D ADDIU SP, SP, 24\r
+BFD09908 459F JR16 RA\r
+BFD0990A 0C00 NOP\r
3344: \r
3345: #endif /* INCLUDE_vTaskDelete */\r
3346: /*-----------------------------------------------------------*/\r
3347: \r
3348: static void prvResetNextTaskUnblockTime( void )\r
3349: {\r
-BFD08F94 4FF9 ADDIU SP, SP, -16
-BFD08F96 CBC3 SW S8, 12(SP)
-BFD08F98 0FDD MOVE S8, SP
+BFD08F94 4FF9 ADDIU SP, SP, -16\r
+BFD08F96 CBC3 SW S8, 12(SP)\r
+BFD08F98 0FDD MOVE S8, SP\r
3350: TCB_t *pxTCB;\r
3351: \r
3352: if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )\r
-BFD08F9A 8074FC5C LW V0, -32652(GP)
-BFD08F9E 6920 LW V0, 0(V0)
-BFD08FA0 000340A2 BNEZC V0, 0xBFD08FAA
-BFD08FA4 ED01 LI V0, 1
-BFD08FA6 CC02 B 0xBFD08FAC
-BFD08FA8 0C00 NOP
-BFD08FAA 0C40 MOVE V0, ZERO
-BFD08FAC 000540E2 BEQZC V0, 0xBFD08FBA
+BFD08F9A 8074FC5C LW V0, -32652(GP)\r
+BFD08F9E 6920 LW V0, 0(V0)\r
+BFD08FA0 000340A2 BNEZC V0, 0xBFD08FAA\r
+BFD08FA4 ED01 LI V0, 1\r
+BFD08FA6 CC02 B 0xBFD08FAC\r
+BFD08FA8 0C00 NOP\r
+BFD08FAA 0C40 MOVE V0, ZERO\r
+BFD08FAC 000540E2 BEQZC V0, 0xBFD08FBA\r
3353: {\r
3354: /* The new current delayed list is empty. Set xNextTaskUnblockTime to\r
3355: the maximum possible value so it is extremely unlikely that the\r
3356: if( xTickCount >= xNextTaskUnblockTime ) test will pass until\r
3357: there is an item in the delayed list. */\r
3358: xNextTaskUnblockTime = portMAX_DELAY;\r
-BFD08FB0 ED7F LI V0, -1
-BFD08FB2 8058F85C SW V0, -32680(GP)
-BFD08FB6 CC0C B 0xBFD08FD0
-BFD08FB8 0C00 NOP
+BFD08FB0 ED7F LI V0, -1\r
+BFD08FB2 8058F85C SW V0, -32680(GP)\r
+BFD08FB6 CC0C B 0xBFD08FD0\r
+BFD08FB8 0C00 NOP\r
3359: }\r
3360: else\r
3361: {\r
3364: which the task at the head of the delayed list should be removed\r
3365: from the Blocked state. */\r
3366: ( pxTCB ) = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );\r
-BFD08FBA 8074FC5C LW V0, -32652(GP)
-BFD08FBE 6923 LW V0, 12(V0)
-BFD08FC0 6923 LW V0, 12(V0)
-BFD08FC2 0000F85E SW V0, 0(S8)
+BFD08FBA 8074FC5C LW V0, -32652(GP)\r
+BFD08FBE 6923 LW V0, 12(V0)\r
+BFD08FC0 6923 LW V0, 12(V0)\r
+BFD08FC2 0000F85E SW V0, 0(S8)\r
3367: xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xGenericListItem ) );\r
-BFD08FC6 0000FC5E LW V0, 0(S8)
-BFD08FCA 6921 LW V0, 4(V0)
-BFD08FCC 8058F85C SW V0, -32680(GP)
+BFD08FC6 0000FC5E LW V0, 0(S8)\r
+BFD08FCA 6921 LW V0, 4(V0)\r
+BFD08FCC 8058F85C SW V0, -32680(GP)\r
3368: }\r
3369: }\r
-BFD08FD0 0FBE MOVE SP, S8
-BFD08FD2 4BC3 LW S8, 12(SP)
-BFD08FD4 4C09 ADDIU SP, SP, 16
-BFD08FD6 459F JR16 RA
-BFD08FD8 0C00 NOP
+BFD08FD0 0FBE MOVE SP, S8\r
+BFD08FD2 4BC3 LW S8, 12(SP)\r
+BFD08FD4 4C09 ADDIU SP, SP, 16\r
+BFD08FD6 459F JR16 RA\r
+BFD08FD8 0C00 NOP\r
3370: /*-----------------------------------------------------------*/\r
3371: \r
3372: #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )\r
3373: \r
3374: TaskHandle_t xTaskGetCurrentTaskHandle( void )\r
3375: {\r
-BFD09E04 4FF9 ADDIU SP, SP, -16
-BFD09E06 CBC3 SW S8, 12(SP)
-BFD09E08 0FDD MOVE S8, SP
+BFD09E04 4FF9 ADDIU SP, SP, -16\r
+BFD09E06 CBC3 SW S8, 12(SP)\r
+BFD09E08 0FDD MOVE S8, SP\r
3376: TaskHandle_t xReturn;\r
3377: \r
3378: /* A critical section is not required as this is not called from\r
3379: an interrupt and the current TCB will always be the same for any\r
3380: individual execution thread. */\r
3381: xReturn = pxCurrentTCB;\r
-BFD09E0A 8030FC5C LW V0, -32720(GP)
-BFD09E0E 0000F85E SW V0, 0(S8)
+BFD09E0A 8030FC5C LW V0, -32720(GP)\r
+BFD09E0E 0000F85E SW V0, 0(S8)\r
3382: \r
3383: return xReturn;\r
-BFD09E12 0000FC5E LW V0, 0(S8)
+BFD09E12 0000FC5E LW V0, 0(S8)\r
3384: }\r
-BFD09E16 0FBE MOVE SP, S8
-BFD09E18 4BC3 LW S8, 12(SP)
-BFD09E1A 4C09 ADDIU SP, SP, 16
-BFD09E1C 459F JR16 RA
-BFD09E1E 0C00 NOP
+BFD09E16 0FBE MOVE SP, S8\r
+BFD09E18 4BC3 LW S8, 12(SP)\r
+BFD09E1A 4C09 ADDIU SP, SP, 16\r
+BFD09E1C 459F JR16 RA\r
+BFD09E1E 0C00 NOP\r
3385: \r
3386: #endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */\r
3387: /*-----------------------------------------------------------*/\r
3390: \r
3391: BaseType_t xTaskGetSchedulerState( void )\r
3392: {\r
-BFD0951C 4FF9 ADDIU SP, SP, -16
-BFD0951E CBC3 SW S8, 12(SP)
-BFD09520 0FDD MOVE S8, SP
+BFD0951C 4FF9 ADDIU SP, SP, -16\r
+BFD0951E CBC3 SW S8, 12(SP)\r
+BFD09520 0FDD MOVE S8, SP\r
3393: BaseType_t xReturn;\r
3394: \r
3395: if( xSchedulerRunning == pdFALSE )\r
-BFD09522 8044FC5C LW V0, -32700(GP)
-BFD09526 000540A2 BNEZC V0, 0xBFD09534
+BFD09522 8044FC5C LW V0, -32700(GP)\r
+BFD09526 000540A2 BNEZC V0, 0xBFD09534\r
3396: {\r
3397: xReturn = taskSCHEDULER_NOT_STARTED;\r
-BFD0952A ED01 LI V0, 1
-BFD0952C 0000F85E SW V0, 0(S8)
-BFD0952E CC0C0000 INS ZERO, ZERO, 16, 10
-BFD09530 CC0C B 0xBFD0954A
-BFD09532 0C00 NOP
+BFD0952A ED01 LI V0, 1\r
+BFD0952C 0000F85E SW V0, 0(S8)\r
+BFD0952E CC0C0000 INS ZERO, ZERO, 16, 10\r
+BFD09530 CC0C B 0xBFD0954A\r
+BFD09532 0C00 NOP\r
3398: }\r
3399: else\r
3400: {\r
3401: if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\r
-BFD09534 805CFC5C LW V0, -32676(GP)
-BFD09538 000540A2 BNEZC V0, 0xBFD09546
+BFD09534 805CFC5C LW V0, -32676(GP)\r
+BFD09538 000540A2 BNEZC V0, 0xBFD09546\r
3402: {\r
3403: xReturn = taskSCHEDULER_RUNNING;\r
-BFD0953C ED02 LI V0, 2
-BFD0953E 0000F85E SW V0, 0(S8)
-BFD09542 CC03 B 0xBFD0954A
-BFD09544 0C00 NOP
+BFD0953C ED02 LI V0, 2\r
+BFD0953E 0000F85E SW V0, 0(S8)\r
+BFD09542 CC03 B 0xBFD0954A\r
+BFD09544 0C00 NOP\r
3404: }\r
3405: else\r
3406: {\r
3407: xReturn = taskSCHEDULER_SUSPENDED;\r
-BFD09546 0000F81E SW ZERO, 0(S8)
+BFD09546 0000F81E SW ZERO, 0(S8)\r
3408: }\r
3409: }\r
3410: \r
3411: return xReturn;\r
-BFD0954A 0000FC5E LW V0, 0(S8)
+BFD0954A 0000FC5E LW V0, 0(S8)\r
3412: }\r
-BFD0954E 0FBE MOVE SP, S8
-BFD09550 4BC3 LW S8, 12(SP)
-BFD09552 4C09 ADDIU SP, SP, 16
-BFD09554 459F JR16 RA
-BFD09556 0C00 NOP
+BFD0954E 0FBE MOVE SP, S8\r
+BFD09550 4BC3 LW S8, 12(SP)\r
+BFD09552 4C09 ADDIU SP, SP, 16\r
+BFD09554 459F JR16 RA\r
+BFD09556 0C00 NOP\r
3413: \r
3414: #endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */\r
3415: /*-----------------------------------------------------------*/\r
3418: \r
3419: void vTaskPriorityInherit( TaskHandle_t const pxMutexHolder )\r
3420: {\r
-BFD03520 4FF1 ADDIU SP, SP, -32
-BFD03522 CBE7 SW RA, 28(SP)
-BFD03524 CBC6 SW S8, 24(SP)
-BFD03526 0FDD MOVE S8, SP
-BFD03528 0020F89E SW A0, 32(S8)
+BFD03520 4FF1 ADDIU SP, SP, -32\r
+BFD03522 CBE7 SW RA, 28(SP)\r
+BFD03524 CBC6 SW S8, 24(SP)\r
+BFD03526 0FDD MOVE S8, SP\r
+BFD03528 0020F89E SW A0, 32(S8)\r
3421: TCB_t * const pxTCB = ( TCB_t * ) pxMutexHolder;\r
-BFD0352C 0020FC5E LW V0, 32(S8)
-BFD03530 0010F85E SW V0, 16(S8)
+BFD0352C 0020FC5E LW V0, 32(S8)\r
+BFD03530 0010F85E SW V0, 16(S8)\r
3422: \r
3423: /* If the mutex was given back by an interrupt while the queue was\r
3424: locked then the mutex holder might now be NULL. */\r
3425: if( pxMutexHolder != NULL )\r
-BFD03534 0020FC5E LW V0, 32(S8)
-BFD03538 007E40E2 BEQZC V0, 0xBFD03638
+BFD03534 0020FC5E LW V0, 32(S8)\r
+BFD03538 007E40E2 BEQZC V0, 0xBFD03638\r
3426: {\r
3427: /* If the holder of the mutex has a priority below the priority of\r
3428: the task attempting to obtain the mutex then it will temporarily\r
3429: inherit the priority of the task attempting to obtain the mutex. */\r
3430: if( pxTCB->uxPriority < pxCurrentTCB->uxPriority )\r
-BFD0353C 0010FC5E LW V0, 16(S8)
-BFD03540 69AB LW V1, 44(V0)
-BFD03542 8030FC5C LW V0, -32720(GP)
-BFD03546 692B LW V0, 44(V0)
-BFD03548 13900043 SLTU V0, V1, V0
-BFD0354A 40E21390 ADDI GP, S0, 16610
-BFD0354C 007440E2 BEQZC V0, 0xBFD03638
+BFD0353C 0010FC5E LW V0, 16(S8)\r
+BFD03540 69AB LW V1, 44(V0)\r
+BFD03542 8030FC5C LW V0, -32720(GP)\r
+BFD03546 692B LW V0, 44(V0)\r
+BFD03548 13900043 SLTU V0, V1, V0\r
+BFD0354A 40E21390 ADDI GP, S0, 16610\r
+BFD0354C 007440E2 BEQZC V0, 0xBFD03638\r
3431: {\r
3432: /* Adjust the mutex holder state to account for its new\r
3433: priority. Only reset the event list item value if the value is\r
3434: not being used for anything else. */\r
3435: if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )\r
-BFD03550 0010FC5E LW V0, 16(S8)
-BFD03554 6926 LW V0, 24(V0)
-BFD03556 00094002 BLTZ V0, 0xBFD0356C
-BFD03558 0C000009 SLL ZERO, T1, 1
-BFD0355A 0C00 NOP
+BFD03550 0010FC5E LW V0, 16(S8)\r
+BFD03554 6926 LW V0, 24(V0)\r
+BFD03556 00094002 BLTZ V0, 0xBFD0356C\r
+BFD03558 0C000009 SLL ZERO, T1, 1\r
+BFD0355A 0C00 NOP\r
3436: {\r
3437: listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\r
-BFD0355C 8030FC5C LW V0, -32720(GP)
-BFD03560 692B LW V0, 44(V0)
-BFD03562 ED85 LI V1, 5
-BFD03564 05A7 SUBU V1, V1, V0
-BFD03566 0010FC5E LW V0, 16(S8)
-BFD0356A E9A6 SW V1, 24(V0)
+BFD0355C 8030FC5C LW V0, -32720(GP)\r
+BFD03560 692B LW V0, 44(V0)\r
+BFD03562 ED85 LI V1, 5\r
+BFD03564 05A7 SUBU V1, V1, V0\r
+BFD03566 0010FC5E LW V0, 16(S8)\r
+BFD0356A E9A6 SW V1, 24(V0)\r
3438: }\r
3439: else\r
3440: {\r
3444: /* If the task being modified is in the ready state it will need\r
3445: to be moved into a new list. */\r
3446: if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxTCB->uxPriority ] ), &( pxTCB->xGenericListItem ) ) != pdFALSE )\r
-BFD0356C 0010FC5E LW V0, 16(S8)
-BFD0356E 69A50010 LWX T5, 0(S0)
-BFD03570 69A5 LW V1, 20(V0)
-BFD03572 0010FC5E LW V0, 16(S8)
-BFD03576 692B LW V0, 44(V0)
-BFD03578 2524 SLL V0, V0, 2
-BFD0357A 2624 SLL A0, V0, 2
-BFD0357C 0644 ADDU A0, V0, A0
-BFD0357E BFD241A2 LUI V0, 0xBFD2
-BFD03580 3042BFD2 LDC1 F30, 12354(S2)
-BFD03582 806C3042 ADDIU V0, V0, -32660
-BFD03586 0528 ADDU V0, A0, V0
-BFD03588 0004B443 BNE V1, V0, 0xBFD03594
-BFD0358A 0C000004 SLL ZERO, A0, 1
-BFD0358C 0C00 NOP
-BFD0358E ED01 LI V0, 1
-BFD03590 CC02 B 0xBFD03596
-BFD03592 0C00 NOP
-BFD03594 0C40 MOVE V0, ZERO
-BFD03596 004940E2 BEQZC V0, 0xBFD0362C
+BFD0356C 0010FC5E LW V0, 16(S8)\r
+BFD0356E 69A50010 LWX T5, 0(S0)\r
+BFD03570 69A5 LW V1, 20(V0)\r
+BFD03572 0010FC5E LW V0, 16(S8)\r
+BFD03576 692B LW V0, 44(V0)\r
+BFD03578 2524 SLL V0, V0, 2\r
+BFD0357A 2624 SLL A0, V0, 2\r
+BFD0357C 0644 ADDU A0, V0, A0\r
+BFD0357E BFD241A2 LUI V0, 0xBFD2\r
+BFD03580 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD03582 806C3042 ADDIU V0, V0, -32660\r
+BFD03586 0528 ADDU V0, A0, V0\r
+BFD03588 0004B443 BNE V1, V0, 0xBFD03594\r
+BFD0358A 0C000004 SLL ZERO, A0, 1\r
+BFD0358C 0C00 NOP\r
+BFD0358E ED01 LI V0, 1\r
+BFD03590 CC02 B 0xBFD03596\r
+BFD03592 0C00 NOP\r
+BFD03594 0C40 MOVE V0, ZERO\r
+BFD03596 004940E2 BEQZC V0, 0xBFD0362C\r
3447: {\r
3448: if( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r
-BFD0359A 0010FC5E LW V0, 16(S8)
-BFD0359E 6D22 ADDIU V0, V0, 4
-BFD035A0 0C82 MOVE A0, V0
-BFD035A2 00C877E8 JALS uxListRemove
-BFD035A4 0C0000C8 SLL A2, T0, 1
-BFD035A6 0C00 NOP
-BFD035A8 001A40A2 BNEZC V0, 0xBFD035E0
+BFD0359A 0010FC5E LW V0, 16(S8)\r
+BFD0359E 6D22 ADDIU V0, V0, 4\r
+BFD035A0 0C82 MOVE A0, V0\r
+BFD035A2 00C877E8 JALS uxListRemove\r
+BFD035A4 0C0000C8 SLL A2, T0, 1\r
+BFD035A6 0C00 NOP\r
+BFD035A8 001A40A2 BNEZC V0, 0xBFD035E0\r
3449: {\r
3450: taskRESET_READY_PRIORITY( pxTCB->uxPriority );\r
-BFD035AC 0010FC5E LW V0, 16(S8)
-BFD035B0 692B LW V0, 44(V0)
-BFD035B2 2524 SLL V0, V0, 2
-BFD035B4 25A4 SLL V1, V0, 2
-BFD035B6 05B4 ADDU V1, V0, V1
-BFD035B8 BFD241A2 LUI V0, 0xBFD2
-BFD035BA 3042BFD2 LDC1 F30, 12354(S2)
-BFD035BC 806C3042 ADDIU V0, V0, -32660
-BFD035C0 0526 ADDU V0, V1, V0
-BFD035C2 6920 LW V0, 0(V0)
-BFD035C4 000C40A2 BNEZC V0, 0xBFD035E0
-BFD035C8 0010FC5E LW V0, 16(S8)
-BFD035CC 692B LW V0, 44(V0)
-BFD035CE ED81 LI V1, 1
-BFD035D0 10100062 SLLV V0, V0, V1
-BFD035D2 441A1010 ADDI ZERO, S0, 17434
-BFD035D4 441A NOT16 V1, V0
-BFD035D6 8040FC5C LW V0, -32704(GP)
-BFD035DA 4493 AND16 V0, V1
-BFD035DC 8040F85C SW V0, -32704(GP)
+BFD035AC 0010FC5E LW V0, 16(S8)\r
+BFD035B0 692B LW V0, 44(V0)\r
+BFD035B2 2524 SLL V0, V0, 2\r
+BFD035B4 25A4 SLL V1, V0, 2\r
+BFD035B6 05B4 ADDU V1, V0, V1\r
+BFD035B8 BFD241A2 LUI V0, 0xBFD2\r
+BFD035BA 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD035BC 806C3042 ADDIU V0, V0, -32660\r
+BFD035C0 0526 ADDU V0, V1, V0\r
+BFD035C2 6920 LW V0, 0(V0)\r
+BFD035C4 000C40A2 BNEZC V0, 0xBFD035E0\r
+BFD035C8 0010FC5E LW V0, 16(S8)\r
+BFD035CC 692B LW V0, 44(V0)\r
+BFD035CE ED81 LI V1, 1\r
+BFD035D0 10100062 SLLV V0, V0, V1\r
+BFD035D2 441A1010 ADDI ZERO, S0, 17434\r
+BFD035D4 441A NOT16 V1, V0\r
+BFD035D6 8040FC5C LW V0, -32704(GP)\r
+BFD035DA 4493 AND16 V0, V1\r
+BFD035DC 8040F85C SW V0, -32704(GP)\r
3451: }\r
3452: else\r
3453: {\r
3456: \r
3457: /* Inherit the priority before being moved into the new list. */\r
3458: pxTCB->uxPriority = pxCurrentTCB->uxPriority;\r
-BFD035E0 8030FC5C LW V0, -32720(GP)
-BFD035E4 69AB LW V1, 44(V0)
-BFD035E6 0010FC5E LW V0, 16(S8)
-BFD035EA E9AB SW V1, 44(V0)
+BFD035E0 8030FC5C LW V0, -32720(GP)\r
+BFD035E4 69AB LW V1, 44(V0)\r
+BFD035E6 0010FC5E LW V0, 16(S8)\r
+BFD035EA E9AB SW V1, 44(V0)\r
3459: prvAddTaskToReadyList( pxTCB );\r
-BFD035EC 0010FC5E LW V0, 16(S8)
-BFD035F0 692B LW V0, 44(V0)
-BFD035F2 ED81 LI V1, 1
-BFD035F4 18100062 SLLV V1, V0, V1
-BFD035F6 FC5C1810 SB ZERO, -932(S0)
-BFD035F8 8040FC5C LW V0, -32704(GP)
-BFD035FC 44D3 OR16 V0, V1
-BFD035FE 8040F85C SW V0, -32704(GP)
-BFD03602 0010FC5E LW V0, 16(S8)
-BFD03606 692B LW V0, 44(V0)
-BFD03608 2524 SLL V0, V0, 2
-BFD0360A 25A4 SLL V1, V0, 2
-BFD0360C 05B4 ADDU V1, V0, V1
-BFD0360E BFD241A2 LUI V0, 0xBFD2
-BFD03610 3042BFD2 LDC1 F30, 12354(S2)
-BFD03612 806C3042 ADDIU V0, V0, -32660
-BFD03616 05A6 ADDU V1, V1, V0
-BFD03618 0010FC5E LW V0, 16(S8)
-BFD0361C 6D22 ADDIU V0, V0, 4
-BFD0361E 0C83 MOVE A0, V1
-BFD03620 0CA2 MOVE A1, V0
-BFD03622 3E4A77E8 JALS vListInsertEnd
-BFD03624 0C003E4A LH S2, 3072(T2)
-BFD03626 0C00 NOP
-BFD03628 CC07 B 0xBFD03638
-BFD0362A 0C00 NOP
+BFD035EC 0010FC5E LW V0, 16(S8)\r
+BFD035F0 692B LW V0, 44(V0)\r
+BFD035F2 ED81 LI V1, 1\r
+BFD035F4 18100062 SLLV V1, V0, V1\r
+BFD035F6 FC5C1810 SB ZERO, -932(S0)\r
+BFD035F8 8040FC5C LW V0, -32704(GP)\r
+BFD035FC 44D3 OR16 V0, V1\r
+BFD035FE 8040F85C SW V0, -32704(GP)\r
+BFD03602 0010FC5E LW V0, 16(S8)\r
+BFD03606 692B LW V0, 44(V0)\r
+BFD03608 2524 SLL V0, V0, 2\r
+BFD0360A 25A4 SLL V1, V0, 2\r
+BFD0360C 05B4 ADDU V1, V0, V1\r
+BFD0360E BFD241A2 LUI V0, 0xBFD2\r
+BFD03610 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD03612 806C3042 ADDIU V0, V0, -32660\r
+BFD03616 05A6 ADDU V1, V1, V0\r
+BFD03618 0010FC5E LW V0, 16(S8)\r
+BFD0361C 6D22 ADDIU V0, V0, 4\r
+BFD0361E 0C83 MOVE A0, V1\r
+BFD03620 0CA2 MOVE A1, V0\r
+BFD03622 3E4A77E8 JALS vListInsertEnd\r
+BFD03624 0C003E4A LH S2, 3072(T2)\r
+BFD03626 0C00 NOP\r
+BFD03628 CC07 B 0xBFD03638\r
+BFD0362A 0C00 NOP\r
3460: }\r
3461: else\r
3462: {\r
3463: /* Just inherit the priority. */\r
3464: pxTCB->uxPriority = pxCurrentTCB->uxPriority;\r
-BFD0362C 8030FC5C LW V0, -32720(GP)
-BFD03630 69AB LW V1, 44(V0)
-BFD03632 0010FC5E LW V0, 16(S8)
-BFD03636 E9AB SW V1, 44(V0)
+BFD0362C 8030FC5C LW V0, -32720(GP)\r
+BFD03630 69AB LW V1, 44(V0)\r
+BFD03632 0010FC5E LW V0, 16(S8)\r
+BFD03636 E9AB SW V1, 44(V0)\r
3465: }\r
3466: \r
3467: traceTASK_PRIORITY_INHERIT( pxTCB, pxCurrentTCB->uxPriority );\r
3476: mtCOVERAGE_TEST_MARKER();\r
3477: }\r
3478: }\r
-BFD03638 0FBE MOVE SP, S8
-BFD0363A 4BE7 LW RA, 28(SP)
-BFD0363C 4BC6 LW S8, 24(SP)
-BFD0363E 4C11 ADDIU SP, SP, 32
-BFD03640 459F JR16 RA
-BFD03642 0C00 NOP
+BFD03638 0FBE MOVE SP, S8\r
+BFD0363A 4BE7 LW RA, 28(SP)\r
+BFD0363C 4BC6 LW S8, 24(SP)\r
+BFD0363E 4C11 ADDIU SP, SP, 32\r
+BFD03640 459F JR16 RA\r
+BFD03642 0C00 NOP\r
3479: \r
3480: #endif /* configUSE_MUTEXES */\r
3481: /*-----------------------------------------------------------*/\r
3484: \r
3485: BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )\r
3486: {\r
-BFD02F04 4FF1 ADDIU SP, SP, -32
-BFD02F06 CBE7 SW RA, 28(SP)
-BFD02F08 CBC6 SW S8, 24(SP)
-BFD02F0A 0FDD MOVE S8, SP
-BFD02F0C 0020F89E SW A0, 32(S8)
+BFD02F04 4FF1 ADDIU SP, SP, -32\r
+BFD02F06 CBE7 SW RA, 28(SP)\r
+BFD02F08 CBC6 SW S8, 24(SP)\r
+BFD02F0A 0FDD MOVE S8, SP\r
+BFD02F0C 0020F89E SW A0, 32(S8)\r
3487: TCB_t * const pxTCB = ( TCB_t * ) pxMutexHolder;\r
-BFD02F10 0020FC5E LW V0, 32(S8)
-BFD02F14 0014F85E SW V0, 20(S8)
+BFD02F10 0020FC5E LW V0, 32(S8)\r
+BFD02F14 0014F85E SW V0, 20(S8)\r
3488: BaseType_t xReturn = pdFALSE;\r
-BFD02F18 0010F81E SW ZERO, 16(S8)
+BFD02F18 0010F81E SW ZERO, 16(S8)\r
3489: \r
3490: if( pxMutexHolder != NULL )\r
-BFD02F1C 0020FC5E LW V0, 32(S8)
-BFD02F20 008B40E2 BEQZC V0, 0xBFD0303A
+BFD02F1C 0020FC5E LW V0, 32(S8)\r
+BFD02F20 008B40E2 BEQZC V0, 0xBFD0303A\r
3491: {\r
3492: /* A task can only have an inherited priority if it holds the mutex.\r
3493: If the mutex is held by a task then it cannot be given from an\r
3494: interrupt, and if a mutex is given by the holding task then it must\r
3495: be the running state task. */\r
3496: configASSERT( pxTCB == pxCurrentTCB );\r
-BFD02F24 8030FC5C LW V0, -32720(GP)
-BFD02F28 0014FC7E LW V1, 20(S8)
-BFD02F2C 000A9443 BEQ V1, V0, 0xBFD02F44
-BFD02F2E 0C00000A SLL ZERO, T2, 1
-BFD02F30 0C00 NOP
-BFD02F32 BFD141A2 LUI V0, 0xBFD1
-BFD02F34 3082BFD1 LDC1 F30, 12418(S1)
-BFD02F36 98103082 ADDIU A0, V0, -26608
-BFD02F38 30A09810 SWC1 F0, 12448(S0)
-BFD02F3A 0DA830A0 ADDIU A1, ZERO, 3496
-BFD02F3C 0DA8 MOVE T5, T0
-BFD02F3E 4B7E77E8 JALS vAssertCalled
-BFD02F40 4B7E LW K1, 120(SP)
-BFD02F42 0C00 NOP
+BFD02F24 8030FC5C LW V0, -32720(GP)\r
+BFD02F28 0014FC7E LW V1, 20(S8)\r
+BFD02F2C 000A9443 BEQ V1, V0, 0xBFD02F44\r
+BFD02F2E 0C00000A SLL ZERO, T2, 1\r
+BFD02F30 0C00 NOP\r
+BFD02F32 BFD141A2 LUI V0, 0xBFD1\r
+BFD02F34 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD02F36 98103082 ADDIU A0, V0, -26608\r
+BFD02F38 30A09810 SWC1 F0, 12448(S0)\r
+BFD02F3A 0DA830A0 ADDIU A1, ZERO, 3496\r
+BFD02F3C 0DA8 MOVE T5, T0\r
+BFD02F3E 4B7E77E8 JALS vAssertCalled\r
+BFD02F40 4B7E LW K1, 120(SP)\r
+BFD02F42 0C00 NOP\r
3497: \r
3498: configASSERT( pxTCB->uxMutexesHeld );\r
-BFD02F44 0014FC5E LW V0, 20(S8)
-BFD02F48 0044FC42 LW V0, 68(V0)
-BFD02F4C 000940A2 BNEZC V0, 0xBFD02F62
-BFD02F50 BFD141A2 LUI V0, 0xBFD1
-BFD02F52 3082BFD1 LDC1 F30, 12418(S1)
-BFD02F54 98103082 ADDIU A0, V0, -26608
-BFD02F56 30A09810 SWC1 F0, 12448(S0)
-BFD02F58 0DAA30A0 ADDIU A1, ZERO, 3498
-BFD02F5A 0DAA MOVE T5, T2
-BFD02F5C 4B7E77E8 JALS vAssertCalled
-BFD02F5E 4B7E LW K1, 120(SP)
-BFD02F60 0C00 NOP
+BFD02F44 0014FC5E LW V0, 20(S8)\r
+BFD02F48 0044FC42 LW V0, 68(V0)\r
+BFD02F4C 000940A2 BNEZC V0, 0xBFD02F62\r
+BFD02F50 BFD141A2 LUI V0, 0xBFD1\r
+BFD02F52 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD02F54 98103082 ADDIU A0, V0, -26608\r
+BFD02F56 30A09810 SWC1 F0, 12448(S0)\r
+BFD02F58 0DAA30A0 ADDIU A1, ZERO, 3498\r
+BFD02F5A 0DAA MOVE T5, T2\r
+BFD02F5C 4B7E77E8 JALS vAssertCalled\r
+BFD02F5E 4B7E LW K1, 120(SP)\r
+BFD02F60 0C00 NOP\r
3499: ( pxTCB->uxMutexesHeld )--;\r
-BFD02F62 0014FC5E LW V0, 20(S8)
-BFD02F66 0044FC42 LW V0, 68(V0)
-BFD02F6A 6DAE ADDIU V1, V0, -1
-BFD02F6C 0014FC5E LW V0, 20(S8)
-BFD02F70 0044F862 SW V1, 68(V0)
+BFD02F62 0014FC5E LW V0, 20(S8)\r
+BFD02F66 0044FC42 LW V0, 68(V0)\r
+BFD02F6A 6DAE ADDIU V1, V0, -1\r
+BFD02F6C 0014FC5E LW V0, 20(S8)\r
+BFD02F70 0044F862 SW V1, 68(V0)\r
3500: \r
3501: /* Has the holder of the mutex inherited the priority of another\r
3502: task? */\r
3503: if( pxTCB->uxPriority != pxTCB->uxBasePriority )\r
-BFD02F74 0014FC5E LW V0, 20(S8)
-BFD02F78 69AB LW V1, 44(V0)
-BFD02F7A 0014FC5E LW V0, 20(S8)
-BFD02F7E 0040FC42 LW V0, 64(V0)
-BFD02F82 005A9443 BEQ V1, V0, 0xBFD0303A
-BFD02F84 0C00005A SLL V0, K0, 1
-BFD02F86 0C00 NOP
+BFD02F74 0014FC5E LW V0, 20(S8)\r
+BFD02F78 69AB LW V1, 44(V0)\r
+BFD02F7A 0014FC5E LW V0, 20(S8)\r
+BFD02F7E 0040FC42 LW V0, 64(V0)\r
+BFD02F82 005A9443 BEQ V1, V0, 0xBFD0303A\r
+BFD02F84 0C00005A SLL V0, K0, 1\r
+BFD02F86 0C00 NOP\r
3504: {\r
3505: /* Only disinherit if no other mutexes are held. */\r
3506: if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )\r
-BFD02F88 0014FC5E LW V0, 20(S8)
-BFD02F8C 0044FC42 LW V0, 68(V0)
-BFD02F90 005340A2 BNEZC V0, 0xBFD0303A
+BFD02F88 0014FC5E LW V0, 20(S8)\r
+BFD02F8C 0044FC42 LW V0, 68(V0)\r
+BFD02F90 005340A2 BNEZC V0, 0xBFD0303A\r
3507: {\r
3508: /* A task can only have an inherited priority if it holds\r
3509: the mutex. If the mutex is held by a task then it cannot be\r
3511: holding task then it must be the running state task. Remove\r
3512: the holding task from the ready list. */\r
3513: if( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r
-BFD02F94 0014FC5E LW V0, 20(S8)
-BFD02F98 6D22 ADDIU V0, V0, 4
-BFD02F9A 0C82 MOVE A0, V0
-BFD02F9C 00C877E8 JALS uxListRemove
-BFD02F9E 0C0000C8 SLL A2, T0, 1
-BFD02FA0 0C00 NOP
-BFD02FA2 001A40A2 BNEZC V0, 0xBFD02FDA
+BFD02F94 0014FC5E LW V0, 20(S8)\r
+BFD02F98 6D22 ADDIU V0, V0, 4\r
+BFD02F9A 0C82 MOVE A0, V0\r
+BFD02F9C 00C877E8 JALS uxListRemove\r
+BFD02F9E 0C0000C8 SLL A2, T0, 1\r
+BFD02FA0 0C00 NOP\r
+BFD02FA2 001A40A2 BNEZC V0, 0xBFD02FDA\r
3514: {\r
3515: taskRESET_READY_PRIORITY( pxTCB->uxPriority );\r
-BFD02FA6 0014FC5E LW V0, 20(S8)
-BFD02FAA 692B LW V0, 44(V0)
-BFD02FAC 2524 SLL V0, V0, 2
-BFD02FAE 25A4 SLL V1, V0, 2
-BFD02FB0 05B4 ADDU V1, V0, V1
-BFD02FB2 BFD241A2 LUI V0, 0xBFD2
-BFD02FB4 3042BFD2 LDC1 F30, 12354(S2)
-BFD02FB6 806C3042 ADDIU V0, V0, -32660
-BFD02FBA 0526 ADDU V0, V1, V0
-BFD02FBC 6920 LW V0, 0(V0)
-BFD02FBE 000C40A2 BNEZC V0, 0xBFD02FDA
-BFD02FC2 0014FC5E LW V0, 20(S8)
-BFD02FC6 692B LW V0, 44(V0)
-BFD02FC8 ED81 LI V1, 1
-BFD02FCA 10100062 SLLV V0, V0, V1
-BFD02FCC 441A1010 ADDI ZERO, S0, 17434
-BFD02FCE 441A NOT16 V1, V0
-BFD02FD0 8040FC5C LW V0, -32704(GP)
-BFD02FD4 4493 AND16 V0, V1
-BFD02FD6 8040F85C SW V0, -32704(GP)
+BFD02FA6 0014FC5E LW V0, 20(S8)\r
+BFD02FAA 692B LW V0, 44(V0)\r
+BFD02FAC 2524 SLL V0, V0, 2\r
+BFD02FAE 25A4 SLL V1, V0, 2\r
+BFD02FB0 05B4 ADDU V1, V0, V1\r
+BFD02FB2 BFD241A2 LUI V0, 0xBFD2\r
+BFD02FB4 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD02FB6 806C3042 ADDIU V0, V0, -32660\r
+BFD02FBA 0526 ADDU V0, V1, V0\r
+BFD02FBC 6920 LW V0, 0(V0)\r
+BFD02FBE 000C40A2 BNEZC V0, 0xBFD02FDA\r
+BFD02FC2 0014FC5E LW V0, 20(S8)\r
+BFD02FC6 692B LW V0, 44(V0)\r
+BFD02FC8 ED81 LI V1, 1\r
+BFD02FCA 10100062 SLLV V0, V0, V1\r
+BFD02FCC 441A1010 ADDI ZERO, S0, 17434\r
+BFD02FCE 441A NOT16 V1, V0\r
+BFD02FD0 8040FC5C LW V0, -32704(GP)\r
+BFD02FD4 4493 AND16 V0, V1\r
+BFD02FD6 8040F85C SW V0, -32704(GP)\r
3516: }\r
3517: else\r
3518: {\r
3523: new ready list. */\r
3524: traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );\r
3525: pxTCB->uxPriority = pxTCB->uxBasePriority;\r
-BFD02FDA 0014FC5E LW V0, 20(S8)
-BFD02FDE 0040FC62 LW V1, 64(V0)
-BFD02FE2 0014FC5E LW V0, 20(S8)
-BFD02FE6 E9AB SW V1, 44(V0)
+BFD02FDA 0014FC5E LW V0, 20(S8)\r
+BFD02FDE 0040FC62 LW V1, 64(V0)\r
+BFD02FE2 0014FC5E LW V0, 20(S8)\r
+BFD02FE6 E9AB SW V1, 44(V0)\r
3526: \r
3527: /* Reset the event list item value. It cannot be in use for\r
3528: any other purpose if this task is running, and it must be\r
3529: running to give back the mutex. */\r
3530: listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\r
-BFD02FE8 0014FC5E LW V0, 20(S8)
-BFD02FEC 692B LW V0, 44(V0)
-BFD02FEE ED85 LI V1, 5
-BFD02FF0 05A7 SUBU V1, V1, V0
-BFD02FF2 0014FC5E LW V0, 20(S8)
-BFD02FF6 E9A6 SW V1, 24(V0)
+BFD02FE8 0014FC5E LW V0, 20(S8)\r
+BFD02FEC 692B LW V0, 44(V0)\r
+BFD02FEE ED85 LI V1, 5\r
+BFD02FF0 05A7 SUBU V1, V1, V0\r
+BFD02FF2 0014FC5E LW V0, 20(S8)\r
+BFD02FF6 E9A6 SW V1, 24(V0)\r
3531: prvAddTaskToReadyList( pxTCB );\r
-BFD02FF8 0014FC5E LW V0, 20(S8)
-BFD02FFC 692B LW V0, 44(V0)
-BFD02FFE ED81 LI V1, 1
-BFD03000 18100062 SLLV V1, V0, V1
-BFD03002 FC5C1810 SB ZERO, -932(S0)
-BFD03004 8040FC5C LW V0, -32704(GP)
-BFD03008 44D3 OR16 V0, V1
-BFD0300A 8040F85C SW V0, -32704(GP)
-BFD0300E 0014FC5E LW V0, 20(S8)
-BFD03012 692B LW V0, 44(V0)
-BFD03014 2524 SLL V0, V0, 2
-BFD03016 25A4 SLL V1, V0, 2
-BFD03018 05B4 ADDU V1, V0, V1
-BFD0301A BFD241A2 LUI V0, 0xBFD2
-BFD0301C 3042BFD2 LDC1 F30, 12354(S2)
-BFD0301E 806C3042 ADDIU V0, V0, -32660
-BFD03022 05A6 ADDU V1, V1, V0
-BFD03024 0014FC5E LW V0, 20(S8)
-BFD03028 6D22 ADDIU V0, V0, 4
-BFD0302A 0C83 MOVE A0, V1
-BFD0302C 0CA2 MOVE A1, V0
-BFD0302E 3E4A77E8 JALS vListInsertEnd
-BFD03030 0C003E4A LH S2, 3072(T2)
-BFD03032 0C00 NOP
+BFD02FF8 0014FC5E LW V0, 20(S8)\r
+BFD02FFC 692B LW V0, 44(V0)\r
+BFD02FFE ED81 LI V1, 1\r
+BFD03000 18100062 SLLV V1, V0, V1\r
+BFD03002 FC5C1810 SB ZERO, -932(S0)\r
+BFD03004 8040FC5C LW V0, -32704(GP)\r
+BFD03008 44D3 OR16 V0, V1\r
+BFD0300A 8040F85C SW V0, -32704(GP)\r
+BFD0300E 0014FC5E LW V0, 20(S8)\r
+BFD03012 692B LW V0, 44(V0)\r
+BFD03014 2524 SLL V0, V0, 2\r
+BFD03016 25A4 SLL V1, V0, 2\r
+BFD03018 05B4 ADDU V1, V0, V1\r
+BFD0301A BFD241A2 LUI V0, 0xBFD2\r
+BFD0301C 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD0301E 806C3042 ADDIU V0, V0, -32660\r
+BFD03022 05A6 ADDU V1, V1, V0\r
+BFD03024 0014FC5E LW V0, 20(S8)\r
+BFD03028 6D22 ADDIU V0, V0, 4\r
+BFD0302A 0C83 MOVE A0, V1\r
+BFD0302C 0CA2 MOVE A1, V0\r
+BFD0302E 3E4A77E8 JALS vListInsertEnd\r
+BFD03030 0C003E4A LH S2, 3072(T2)\r
+BFD03032 0C00 NOP\r
3532: \r
3533: /* Return true to indicate that a context switch is required.\r
3534: This is only actually required in the corner case whereby\r
3539: switch should occur when the last mutex is returned whether\r
3540: a task is waiting on it or not. */\r
3541: xReturn = pdTRUE;\r
-BFD03034 ED01 LI V0, 1
-BFD03036 0010F85E SW V0, 16(S8)
+BFD03034 ED01 LI V0, 1\r
+BFD03036 0010F85E SW V0, 16(S8)\r
3542: }\r
3543: else\r
3544: {\r
3556: }\r
3557: \r
3558: return xReturn;\r
-BFD0303A 0010FC5E LW V0, 16(S8)
+BFD0303A 0010FC5E LW V0, 16(S8)\r
3559: }\r
-BFD0303E 0FBE MOVE SP, S8
-BFD03040 4BE7 LW RA, 28(SP)
-BFD03042 4BC6 LW S8, 24(SP)
-BFD03044 4C11 ADDIU SP, SP, 32
-BFD03046 459F JR16 RA
-BFD03048 0C00 NOP
+BFD0303E 0FBE MOVE SP, S8\r
+BFD03040 4BE7 LW RA, 28(SP)\r
+BFD03042 4BC6 LW S8, 24(SP)\r
+BFD03044 4C11 ADDIU SP, SP, 32\r
+BFD03046 459F JR16 RA\r
+BFD03048 0C00 NOP\r
3560: \r
3561: #endif /* configUSE_MUTEXES */\r
3562: /*-----------------------------------------------------------*/\r
3565: \r
3566: void vTaskEnterCritical( void )\r
3567: {\r
-BFD06770 4FF1 ADDIU SP, SP, -32
-BFD06772 CBE7 SW RA, 28(SP)
-BFD06774 CBC6 SW S8, 24(SP)
-BFD06776 0FDD MOVE S8, SP
+BFD06770 4FF1 ADDIU SP, SP, -32\r
+BFD06772 CBE7 SW RA, 28(SP)\r
+BFD06774 CBC6 SW S8, 24(SP)\r
+BFD06776 0FDD MOVE S8, SP\r
3568: portDISABLE_INTERRUPTS();\r
-BFD06778 4E3677E8 JALS ulPortGetCP0Status
-BFD0677A 4E36 ADDIU S1, S1, -5
-BFD0677C 0C00 NOP
-BFD0677E 0010F85E SW V0, 16(S8)
-BFD06782 0010FC7E LW V1, 16(S8)
-BFD06786 000141A2 LUI V0, 0x1
-BFD0678A FC005042 ORI V0, V0, -1024
-BFD0678C 4493FC00 LW ZERO, 17555(ZERO)
-BFD0678E 4493 AND16 V0, V1
-BFD06790 50400042 SRL V0, V0, 10
-BFD06792 B0425040 ORI V0, ZERO, -20414
-BFD06794 0003B042 SLTIU V0, V0, 3
-BFD06798 001140E2 BEQZC V0, 0xBFD067BE
-BFD0679C 0010FC7E LW V1, 16(S8)
-BFD067A0 FFFE41A2 LUI V0, 0xFFFE
-BFD067A2 5042FFFE LW RA, 20546(S8)
-BFD067A4 03FF5042 ORI V0, V0, 1023
-BFD067A8 4493 AND16 V0, V1
-BFD067AA 0010F85E SW V0, 16(S8)
-BFD067AE 0010FC5E LW V0, 16(S8)
-BFD067B2 0C005042 ORI V0, V0, 3072
-BFD067B4 0C00 NOP
-BFD067B6 0C82 MOVE A0, V0
-BFD067B8 4E4677E8 JALS vPortSetCP0Status
-BFD067BA 4E46 ADDIU S2, S2, 3
-BFD067BC 0C00 NOP
+BFD06778 4E3677E8 JALS ulPortGetCP0Status\r
+BFD0677A 4E36 ADDIU S1, S1, -5\r
+BFD0677C 0C00 NOP\r
+BFD0677E 0010F85E SW V0, 16(S8)\r
+BFD06782 0010FC7E LW V1, 16(S8)\r
+BFD06786 000141A2 LUI V0, 0x1\r
+BFD0678A FC005042 ORI V0, V0, -1024\r
+BFD0678C 4493FC00 LW ZERO, 17555(ZERO)\r
+BFD0678E 4493 AND16 V0, V1\r
+BFD06790 50400042 SRL V0, V0, 10\r
+BFD06792 B0425040 ORI V0, ZERO, -20414\r
+BFD06794 0003B042 SLTIU V0, V0, 3\r
+BFD06798 001140E2 BEQZC V0, 0xBFD067BE\r
+BFD0679C 0010FC7E LW V1, 16(S8)\r
+BFD067A0 FFFE41A2 LUI V0, 0xFFFE\r
+BFD067A2 5042FFFE LW RA, 20546(S8)\r
+BFD067A4 03FF5042 ORI V0, V0, 1023\r
+BFD067A8 4493 AND16 V0, V1\r
+BFD067AA 0010F85E SW V0, 16(S8)\r
+BFD067AE 0010FC5E LW V0, 16(S8)\r
+BFD067B2 0C005042 ORI V0, V0, 3072\r
+BFD067B4 0C00 NOP\r
+BFD067B6 0C82 MOVE A0, V0\r
+BFD067B8 4E4677E8 JALS vPortSetCP0Status\r
+BFD067BA 4E46 ADDIU S2, S2, 3\r
+BFD067BC 0C00 NOP\r
3569: \r
3570: if( xSchedulerRunning != pdFALSE )\r
-BFD067BE 8044FC5C LW V0, -32700(GP)
-BFD067C2 001940E2 BEQZC V0, 0xBFD067F8
+BFD067BE 8044FC5C LW V0, -32700(GP)\r
+BFD067C2 001940E2 BEQZC V0, 0xBFD067F8\r
3571: {\r
3572: ( pxCurrentTCB->uxCriticalNesting )++;\r
-BFD067C6 8030FC5C LW V0, -32720(GP)
-BFD067CA 69AF LW V1, 60(V0)
-BFD067CC 6DB0 ADDIU V1, V1, 1
-BFD067CE E9AF SW V1, 60(V0)
+BFD067C6 8030FC5C LW V0, -32720(GP)\r
+BFD067CA 69AF LW V1, 60(V0)\r
+BFD067CC 6DB0 ADDIU V1, V1, 1\r
+BFD067CE E9AF SW V1, 60(V0)\r
3573: \r
3574: /* This is not the interrupt safe version of the enter critical\r
3575: function so assert() if it is being called from an interrupt\r
3578: protect against recursive calls if the assert function also uses a\r
3579: critical section. */\r
3580: if( pxCurrentTCB->uxCriticalNesting == 1 )\r
-BFD067D0 8030FC5C LW V0, -32720(GP)
-BFD067D4 69AF LW V1, 60(V0)
-BFD067D6 ED01 LI V0, 1
-BFD067D8 000EB443 BNE V1, V0, 0xBFD067F8
-BFD067DA 0C00000E SLL ZERO, T6, 1
-BFD067DC 0C00 NOP
+BFD067D0 8030FC5C LW V0, -32720(GP)\r
+BFD067D4 69AF LW V1, 60(V0)\r
+BFD067D6 ED01 LI V0, 1\r
+BFD067D8 000EB443 BNE V1, V0, 0xBFD067F8\r
+BFD067DA 0C00000E SLL ZERO, T6, 1\r
+BFD067DC 0C00 NOP\r
3581: {\r
3582: portASSERT_IF_IN_ISR();\r
-BFD067DE 8014FC5C LW V0, -32748(GP)
-BFD067E2 000940E2 BEQZC V0, 0xBFD067F8
-BFD067E6 BFD141A2 LUI V0, 0xBFD1
-BFD067E8 3082BFD1 LDC1 F30, 12418(S1)
-BFD067EA 98103082 ADDIU A0, V0, -26608
-BFD067EC 30A09810 SWC1 F0, 12448(S0)
-BFD067EE 0DFE30A0 ADDIU A1, ZERO, 3582
-BFD067F0 0DFE MOVE T7, S8
-BFD067F2 4B7E77E8 JALS vAssertCalled
-BFD067F4 4B7E LW K1, 120(SP)
-BFD067F6 0C00 NOP
+BFD067DE 8014FC5C LW V0, -32748(GP)\r
+BFD067E2 000940E2 BEQZC V0, 0xBFD067F8\r
+BFD067E6 BFD141A2 LUI V0, 0xBFD1\r
+BFD067E8 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD067EA 98103082 ADDIU A0, V0, -26608\r
+BFD067EC 30A09810 SWC1 F0, 12448(S0)\r
+BFD067EE 0DFE30A0 ADDIU A1, ZERO, 3582\r
+BFD067F0 0DFE MOVE T7, S8\r
+BFD067F2 4B7E77E8 JALS vAssertCalled\r
+BFD067F4 4B7E LW K1, 120(SP)\r
+BFD067F6 0C00 NOP\r
3583: }\r
3584: \r
3585: }\r
3588: mtCOVERAGE_TEST_MARKER();\r
3589: }\r
3590: }\r
-BFD067F8 0FBE MOVE SP, S8
-BFD067FA 4BE7 LW RA, 28(SP)
-BFD067FC 4BC6 LW S8, 24(SP)
-BFD067FE 4C11 ADDIU SP, SP, 32
-BFD06800 459F JR16 RA
-BFD06802 0C00 NOP
+BFD067F8 0FBE MOVE SP, S8\r
+BFD067FA 4BE7 LW RA, 28(SP)\r
+BFD067FC 4BC6 LW S8, 24(SP)\r
+BFD067FE 4C11 ADDIU SP, SP, 32\r
+BFD06800 459F JR16 RA\r
+BFD06802 0C00 NOP\r
3591: \r
3592: #endif /* portCRITICAL_NESTING_IN_TCB */\r
3593: /*-----------------------------------------------------------*/\r
3596: \r
3597: void vTaskExitCritical( void )\r
3598: {\r
-BFD08154 4FF1 ADDIU SP, SP, -32
-BFD08156 CBE7 SW RA, 28(SP)
-BFD08158 CBC6 SW S8, 24(SP)
-BFD0815A 0FDD MOVE S8, SP
+BFD08154 4FF1 ADDIU SP, SP, -32\r
+BFD08156 CBE7 SW RA, 28(SP)\r
+BFD08158 CBC6 SW S8, 24(SP)\r
+BFD0815A 0FDD MOVE S8, SP\r
3599: if( xSchedulerRunning != pdFALSE )\r
-BFD0815C 8044FC5C LW V0, -32700(GP)
-BFD08160 002240E2 BEQZC V0, 0xBFD081A8
+BFD0815C 8044FC5C LW V0, -32700(GP)\r
+BFD08160 002240E2 BEQZC V0, 0xBFD081A8\r
3600: {\r
3601: if( pxCurrentTCB->uxCriticalNesting > 0U )\r
-BFD08164 8030FC5C LW V0, -32720(GP)
-BFD08168 692F LW V0, 60(V0)
-BFD0816A 001D40E2 BEQZC V0, 0xBFD081A8
+BFD08164 8030FC5C LW V0, -32720(GP)\r
+BFD08168 692F LW V0, 60(V0)\r
+BFD0816A 001D40E2 BEQZC V0, 0xBFD081A8\r
3602: {\r
3603: ( pxCurrentTCB->uxCriticalNesting )--;\r
-BFD0816E 8030FC5C LW V0, -32720(GP)
-BFD08172 69AF LW V1, 60(V0)
-BFD08174 6DBE ADDIU V1, V1, -1
-BFD08176 E9AF SW V1, 60(V0)
+BFD0816E 8030FC5C LW V0, -32720(GP)\r
+BFD08172 69AF LW V1, 60(V0)\r
+BFD08174 6DBE ADDIU V1, V1, -1\r
+BFD08176 E9AF SW V1, 60(V0)\r
3604: \r
3605: if( pxCurrentTCB->uxCriticalNesting == 0U )\r
-BFD08178 8030FC5C LW V0, -32720(GP)
-BFD0817C 692F LW V0, 60(V0)
-BFD0817E 001340A2 BNEZC V0, 0xBFD081A8
+BFD08178 8030FC5C LW V0, -32720(GP)\r
+BFD0817C 692F LW V0, 60(V0)\r
+BFD0817E 001340A2 BNEZC V0, 0xBFD081A8\r
3606: {\r
3607: portENABLE_INTERRUPTS();\r
-BFD08182 4E3677E8 JALS ulPortGetCP0Status
-BFD08184 4E36 ADDIU S1, S1, -5
-BFD08186 0C00 NOP
-BFD08188 0010F85E SW V0, 16(S8)
-BFD0818C 0010FC7E LW V1, 16(S8)
-BFD08190 FFFE41A2 LUI V0, 0xFFFE
-BFD08192 5042FFFE LW RA, 20546(S8)
-BFD08194 03FF5042 ORI V0, V0, 1023
-BFD08198 4493 AND16 V0, V1
-BFD0819A 0010F85E SW V0, 16(S8)
-BFD0819E 0010FC9E LW A0, 16(S8)
-BFD081A2 4E4677E8 JALS vPortSetCP0Status
-BFD081A4 4E46 ADDIU S2, S2, 3
-BFD081A6 0C00 NOP
+BFD08182 4E3677E8 JALS ulPortGetCP0Status\r
+BFD08184 4E36 ADDIU S1, S1, -5\r
+BFD08186 0C00 NOP\r
+BFD08188 0010F85E SW V0, 16(S8)\r
+BFD0818C 0010FC7E LW V1, 16(S8)\r
+BFD08190 FFFE41A2 LUI V0, 0xFFFE\r
+BFD08192 5042FFFE LW RA, 20546(S8)\r
+BFD08194 03FF5042 ORI V0, V0, 1023\r
+BFD08198 4493 AND16 V0, V1\r
+BFD0819A 0010F85E SW V0, 16(S8)\r
+BFD0819E 0010FC9E LW A0, 16(S8)\r
+BFD081A2 4E4677E8 JALS vPortSetCP0Status\r
+BFD081A4 4E46 ADDIU S2, S2, 3\r
+BFD081A6 0C00 NOP\r
3608: }\r
3609: else\r
3610: {\r
3621: mtCOVERAGE_TEST_MARKER();\r
3622: }\r
3623: }\r
-BFD081A8 0FBE MOVE SP, S8
-BFD081AA 4BE7 LW RA, 28(SP)
-BFD081AC 4BC6 LW S8, 24(SP)
-BFD081AE 4C11 ADDIU SP, SP, 32
-BFD081B0 459F JR16 RA
-BFD081B2 0C00 NOP
+BFD081A8 0FBE MOVE SP, S8\r
+BFD081AA 4BE7 LW RA, 28(SP)\r
+BFD081AC 4BC6 LW S8, 24(SP)\r
+BFD081AE 4C11 ADDIU SP, SP, 32\r
+BFD081B0 459F JR16 RA\r
+BFD081B2 0C00 NOP\r
3624: \r
3625: #endif /* portCRITICAL_NESTING_IN_TCB */\r
3626: /*-----------------------------------------------------------*/\r
3869: \r
3870: TickType_t uxTaskResetEventItemValue( void )\r
3871: {\r
-BFD0990C 4FF9 ADDIU SP, SP, -16
-BFD0990E CBC3 SW S8, 12(SP)
-BFD09910 0FDD MOVE S8, SP
+BFD0990C 4FF9 ADDIU SP, SP, -16\r
+BFD0990E CBC3 SW S8, 12(SP)\r
+BFD09910 0FDD MOVE S8, SP\r
3872: TickType_t uxReturn;\r
3873: \r
3874: uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );\r
-BFD09912 8030FC5C LW V0, -32720(GP)
-BFD09916 6926 LW V0, 24(V0)
-BFD09918 0000F85E SW V0, 0(S8)
+BFD09912 8030FC5C LW V0, -32720(GP)\r
+BFD09916 6926 LW V0, 24(V0)\r
+BFD09918 0000F85E SW V0, 0(S8)\r
3875: \r
3876: /* Reset the event list item to its normal value - so it can be used with\r
3877: queues and semaphores. */\r
3878: listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\r
-BFD0991C 8030FC5C LW V0, -32720(GP)
-BFD09920 8030FC7C LW V1, -32720(GP)
-BFD09924 69BB LW V1, 44(V1)
-BFD09926 EE05 LI A0, 5
-BFD09928 05B9 SUBU V1, A0, V1
-BFD0992A E9A6 SW V1, 24(V0)
+BFD0991C 8030FC5C LW V0, -32720(GP)\r
+BFD09920 8030FC7C LW V1, -32720(GP)\r
+BFD09924 69BB LW V1, 44(V1)\r
+BFD09926 EE05 LI A0, 5\r
+BFD09928 05B9 SUBU V1, A0, V1\r
+BFD0992A E9A6 SW V1, 24(V0)\r
3879: \r
3880: return uxReturn;\r
-BFD0992C 0000FC5E LW V0, 0(S8)
+BFD0992C 0000FC5E LW V0, 0(S8)\r
3881: }\r
-BFD09930 0FBE MOVE SP, S8
-BFD09932 4BC3 LW S8, 12(SP)
-BFD09934 4C09 ADDIU SP, SP, 16
-BFD09936 459F JR16 RA
-BFD09938 0C00 NOP
+BFD09930 0FBE MOVE SP, S8\r
+BFD09932 4BC3 LW S8, 12(SP)\r
+BFD09934 4C09 ADDIU SP, SP, 16\r
+BFD09936 459F JR16 RA\r
+BFD09938 0C00 NOP\r
3882: /*-----------------------------------------------------------*/\r
3883: \r
3884: #if ( configUSE_MUTEXES == 1 )\r
3885: \r
3886: void *pvTaskIncrementMutexHeldCount( void )\r
3887: {\r
-BFD099C0 4FB0 ADDIU SP, SP, -8
-BFD099C2 CBC1 SW S8, 4(SP)
-BFD099C4 0FDD MOVE S8, SP
+BFD099C0 4FB0 ADDIU SP, SP, -8\r
+BFD099C2 CBC1 SW S8, 4(SP)\r
+BFD099C4 0FDD MOVE S8, SP\r
3888: /* If xSemaphoreCreateMutex() is called before any tasks have been created\r
3889: then pxCurrentTCB will be NULL. */\r
3890: if( pxCurrentTCB != NULL )\r
-BFD099C6 8030FC5C LW V0, -32720(GP)
-BFD099CA 000740E2 BEQZC V0, 0xBFD099DC
+BFD099C6 8030FC5C LW V0, -32720(GP)\r
+BFD099CA 000740E2 BEQZC V0, 0xBFD099DC\r
3891: {\r
3892: ( pxCurrentTCB->uxMutexesHeld )++;\r
-BFD099CE 8030FC5C LW V0, -32720(GP)
-BFD099D2 0044FC62 LW V1, 68(V0)
-BFD099D6 6DB0 ADDIU V1, V1, 1
-BFD099D8 0044F862 SW V1, 68(V0)
+BFD099CE 8030FC5C LW V0, -32720(GP)\r
+BFD099D2 0044FC62 LW V1, 68(V0)\r
+BFD099D6 6DB0 ADDIU V1, V1, 1\r
+BFD099D8 0044F862 SW V1, 68(V0)\r
3893: }\r
3894: \r
3895: return pxCurrentTCB;\r
-BFD099DC 8030FC5C LW V0, -32720(GP)
+BFD099DC 8030FC5C LW V0, -32720(GP)\r
3896: }\r
-BFD099E0 0FBE MOVE SP, S8
-BFD099E2 4BC1 LW S8, 4(SP)
-BFD099E4 4C05 ADDIU SP, SP, 8
-BFD099E6 459F JR16 RA
-BFD099E8 0C00 NOP
+BFD099E0 0FBE MOVE SP, S8\r
+BFD099E2 4BC1 LW S8, 4(SP)\r
+BFD099E4 4C05 ADDIU SP, SP, 8\r
+BFD099E6 459F JR16 RA\r
+BFD099E8 0C00 NOP\r
3897: \r
3898: #endif /* configUSE_MUTEXES */\r
3899: /*-----------------------------------------------------------*/\r
3902: \r
3903: uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait )\r
3904: {\r
-BFD039AC 4FED ADDIU SP, SP, -40
-BFD039AE CBE9 SW RA, 36(SP)
-BFD039B0 CBC8 SW S8, 32(SP)
-BFD039B2 0FDD MOVE S8, SP
-BFD039B4 0028F89E SW A0, 40(S8)
-BFD039B8 002CF8BE SW A1, 44(S8)
+BFD039AC 4FED ADDIU SP, SP, -40\r
+BFD039AE CBE9 SW RA, 36(SP)\r
+BFD039B0 CBC8 SW S8, 32(SP)\r
+BFD039B2 0FDD MOVE S8, SP\r
+BFD039B4 0028F89E SW A0, 40(S8)\r
+BFD039B8 002CF8BE SW A1, 44(S8)\r
3905: TickType_t xTimeToWake;\r
3906: uint32_t ulReturn;\r
3907: \r
3908: taskENTER_CRITICAL();\r
-BFD039BC 33B877E8 JALS vTaskEnterCritical
-BFD039BE 0C0033B8 ADDIU SP, T8, 3072
-BFD039C0 0C00 NOP
+BFD039BC 33B877E8 JALS vTaskEnterCritical\r
+BFD039BE 0C0033B8 ADDIU SP, T8, 3072\r
+BFD039C0 0C00 NOP\r
3909: {\r
3910: /* Only block if the notification count is not already non-zero. */\r
3911: if( pxCurrentTCB->ulNotifiedValue == 0UL )\r
-BFD039C2 8030FC5C LW V0, -32720(GP)
-BFD039C6 0048FC42 LW V0, 72(V0)
-BFD039CA 004D40A2 BNEZC V0, 0xBFD03A68
+BFD039C2 8030FC5C LW V0, -32720(GP)\r
+BFD039C6 0048FC42 LW V0, 72(V0)\r
+BFD039CA 004D40A2 BNEZC V0, 0xBFD03A68\r
3912: {\r
3913: /* Mark this task as waiting for a notification. */\r
3914: pxCurrentTCB->eNotifyState = eWaitingNotification;\r
-BFD039CE 8030FC5C LW V0, -32720(GP)
-BFD039D2 ED81 LI V1, 1
-BFD039D4 004CF862 SW V1, 76(V0)
+BFD039CE 8030FC5C LW V0, -32720(GP)\r
+BFD039D2 ED81 LI V1, 1\r
+BFD039D4 004CF862 SW V1, 76(V0)\r
3915: \r
3916: if( xTicksToWait > ( TickType_t ) 0 )\r
-BFD039D8 002CFC5E LW V0, 44(S8)
-BFD039DC 004440E2 BEQZC V0, 0xBFD03A68
+BFD039D8 002CFC5E LW V0, 44(S8)\r
+BFD039DC 004440E2 BEQZC V0, 0xBFD03A68\r
3917: {\r
3918: /* The task is going to block. First it must be removed\r
3919: from the ready list. */\r
3920: if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r
-BFD039E0 8030FC5C LW V0, -32720(GP)
-BFD039E4 6D22 ADDIU V0, V0, 4
-BFD039E6 0C82 MOVE A0, V0
-BFD039E8 00C877E8 JALS uxListRemove
-BFD039EA 0C0000C8 SLL A2, T0, 1
-BFD039EC 0C00 NOP
-BFD039EE 000C40A2 BNEZC V0, 0xBFD03A0A
+BFD039E0 8030FC5C LW V0, -32720(GP)\r
+BFD039E4 6D22 ADDIU V0, V0, 4\r
+BFD039E6 0C82 MOVE A0, V0\r
+BFD039E8 00C877E8 JALS uxListRemove\r
+BFD039EA 0C0000C8 SLL A2, T0, 1\r
+BFD039EC 0C00 NOP\r
+BFD039EE 000C40A2 BNEZC V0, 0xBFD03A0A\r
3921: {\r
3922: /* The current task must be in a ready list, so there is\r
3923: no need to check, and the port reset macro can be called\r
3924: directly. */\r
3925: portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );\r
-BFD039F2 8030FC5C LW V0, -32720(GP)
-BFD039F6 692B LW V0, 44(V0)
-BFD039F8 ED81 LI V1, 1
-BFD039FA 10100062 SLLV V0, V0, V1
-BFD039FC 441A1010 ADDI ZERO, S0, 17434
-BFD039FE 441A NOT16 V1, V0
-BFD03A00 8040FC5C LW V0, -32704(GP)
-BFD03A04 4493 AND16 V0, V1
-BFD03A06 8040F85C SW V0, -32704(GP)
+BFD039F2 8030FC5C LW V0, -32720(GP)\r
+BFD039F6 692B LW V0, 44(V0)\r
+BFD039F8 ED81 LI V1, 1\r
+BFD039FA 10100062 SLLV V0, V0, V1\r
+BFD039FC 441A1010 ADDI ZERO, S0, 17434\r
+BFD039FE 441A NOT16 V1, V0\r
+BFD03A00 8040FC5C LW V0, -32704(GP)\r
+BFD03A04 4493 AND16 V0, V1\r
+BFD03A06 8040F85C SW V0, -32704(GP)\r
3926: }\r
3927: else\r
3928: {\r
3932: #if ( INCLUDE_vTaskSuspend == 1 )\r
3933: {\r
3934: if( xTicksToWait == portMAX_DELAY )\r
-BFD03A0A 002CFC7E LW V1, 44(S8)
-BFD03A0E ED7F LI V0, -1
-BFD03A10 000EB443 BNE V1, V0, 0xBFD03A30
-BFD03A12 0C00000E SLL ZERO, T6, 1
-BFD03A14 0C00 NOP
+BFD03A0A 002CFC7E LW V1, 44(S8)\r
+BFD03A0E ED7F LI V0, -1\r
+BFD03A10 000EB443 BNE V1, V0, 0xBFD03A30\r
+BFD03A12 0C00000E SLL ZERO, T6, 1\r
+BFD03A14 0C00 NOP\r
3935: {\r
3936: /* Add the task to the suspended task list instead\r
3937: of a delayed task list to ensure the task is not\r
3938: woken by a timing event. It will block\r
3939: indefinitely. */\r
3940: vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xGenericListItem ) );\r
-BFD03A16 8030FC5C LW V0, -32720(GP)
-BFD03A1A 6D22 ADDIU V0, V0, 4
-BFD03A1C BFD241A3 LUI V1, 0xBFD2
-BFD03A1E 3083BFD2 LDC1 F30, 12419(S2)
-BFD03A20 80E43083 ADDIU A0, V1, -32540
-BFD03A24 0CA2 MOVE A1, V0
-BFD03A26 3E4A77E8 JALS vListInsertEnd
-BFD03A28 0C003E4A LH S2, 3072(T2)
-BFD03A2A 0C00 NOP
-BFD03A2C CC0D B 0xBFD03A48
-BFD03A2E 0C00 NOP
+BFD03A16 8030FC5C LW V0, -32720(GP)\r
+BFD03A1A 6D22 ADDIU V0, V0, 4\r
+BFD03A1C BFD241A3 LUI V1, 0xBFD2\r
+BFD03A1E 3083BFD2 LDC1 F30, 12419(S2)\r
+BFD03A20 80E43083 ADDIU A0, V1, -32540\r
+BFD03A24 0CA2 MOVE A1, V0\r
+BFD03A26 3E4A77E8 JALS vListInsertEnd\r
+BFD03A28 0C003E4A LH S2, 3072(T2)\r
+BFD03A2A 0C00 NOP\r
+BFD03A2C CC0D B 0xBFD03A48\r
+BFD03A2E 0C00 NOP\r
3941: }\r
3942: else\r
3943: {\r
3946: overflow but this doesn't matter, the scheduler will\r
3947: handle it. */\r
3948: xTimeToWake = xTickCount + xTicksToWait;\r
-BFD03A30 803CFC7C LW V1, -32708(GP)
-BFD03A34 002CFC5E LW V0, 44(S8)
-BFD03A38 0526 ADDU V0, V1, V0
-BFD03A3A 0010F85E SW V0, 16(S8)
+BFD03A30 803CFC7C LW V1, -32708(GP)\r
+BFD03A34 002CFC5E LW V0, 44(S8)\r
+BFD03A38 0526 ADDU V0, V1, V0\r
+BFD03A3A 0010F85E SW V0, 16(S8)\r
3949: prvAddCurrentTaskToDelayedList( xTimeToWake );\r
-BFD03A3E 0010FC9E LW A0, 16(S8)
-BFD03A42 373477E8 JALS prvAddCurrentTaskToDelayedList
-BFD03A44 0C003734 LHU T9, 3072(S4)
-BFD03A46 0C00 NOP
+BFD03A3E 0010FC9E LW A0, 16(S8)\r
+BFD03A42 373477E8 JALS prvAddCurrentTaskToDelayedList\r
+BFD03A44 0C003734 LHU T9, 3072(S4)\r
+BFD03A46 0C00 NOP\r
3950: }\r
3951: }\r
3952: #else /* INCLUDE_vTaskSuspend */\r
3965: critical section exits) - but it is not something that\r
3966: application code should ever do. */\r
3967: portYIELD_WITHIN_API();\r
-BFD03A48 4E5677E8 JALS ulPortGetCP0Cause
-BFD03A4A 4E56 ADDIU S2, S2, -5
-BFD03A4C 0C00 NOP
-BFD03A4E 0014F85E SW V0, 20(S8)
-BFD03A52 0014FC5E LW V0, 20(S8)
-BFD03A56 01005042 ORI V0, V0, 256
-BFD03A5A 0014F85E SW V0, 20(S8)
-BFD03A5E 0014FC9E LW A0, 20(S8)
-BFD03A62 4E6677E8 JALS vPortSetCP0Cause
-BFD03A64 4E66 ADDIU S3, S3, 3
-BFD03A66 0C00 NOP
+BFD03A48 4E5677E8 JALS ulPortGetCP0Cause\r
+BFD03A4A 4E56 ADDIU S2, S2, -5\r
+BFD03A4C 0C00 NOP\r
+BFD03A4E 0014F85E SW V0, 20(S8)\r
+BFD03A52 0014FC5E LW V0, 20(S8)\r
+BFD03A56 01005042 ORI V0, V0, 256\r
+BFD03A5A 0014F85E SW V0, 20(S8)\r
+BFD03A5E 0014FC9E LW A0, 20(S8)\r
+BFD03A62 4E6677E8 JALS vPortSetCP0Cause\r
+BFD03A64 4E66 ADDIU S3, S3, 3\r
+BFD03A66 0C00 NOP\r
3968: }\r
3969: else\r
3970: {\r
3977: }\r
3978: }\r
3979: taskEXIT_CRITICAL();\r
-BFD03A68 40AA77E8 JALS vTaskExitCritical
-BFD03A6A 0C0040AA BNEZC T2, 0xBFD0526E
-BFD03A6C 0C00 NOP
+BFD03A68 40AA77E8 JALS vTaskExitCritical\r
+BFD03A6A 0C0040AA BNEZC T2, 0xBFD0526E\r
+BFD03A6C 0C00 NOP\r
3980: \r
3981: taskENTER_CRITICAL();\r
-BFD03A6E 33B877E8 JALS vTaskEnterCritical
-BFD03A70 0C0033B8 ADDIU SP, T8, 3072
-BFD03A72 0C00 NOP
+BFD03A6E 33B877E8 JALS vTaskEnterCritical\r
+BFD03A70 0C0033B8 ADDIU SP, T8, 3072\r
+BFD03A72 0C00 NOP\r
3982: {\r
3983: ulReturn = pxCurrentTCB->ulNotifiedValue;\r
-BFD03A74 8030FC5C LW V0, -32720(GP)
-BFD03A78 0048FC42 LW V0, 72(V0)
-BFD03A7C 0018F85E SW V0, 24(S8)
+BFD03A74 8030FC5C LW V0, -32720(GP)\r
+BFD03A78 0048FC42 LW V0, 72(V0)\r
+BFD03A7C 0018F85E SW V0, 24(S8)\r
3984: \r
3985: if( ulReturn != 0UL )\r
-BFD03A80 0018FC5E LW V0, 24(S8)
-BFD03A84 001140E2 BEQZC V0, 0xBFD03AAA
+BFD03A80 0018FC5E LW V0, 24(S8)\r
+BFD03A84 001140E2 BEQZC V0, 0xBFD03AAA\r
3986: {\r
3987: if( xClearCountOnExit != pdFALSE )\r
-BFD03A88 0028FC5E LW V0, 40(S8)
-BFD03A8C 000640E2 BEQZC V0, 0xBFD03A9C
+BFD03A88 0028FC5E LW V0, 40(S8)\r
+BFD03A8C 000640E2 BEQZC V0, 0xBFD03A9C\r
3988: {\r
3989: pxCurrentTCB->ulNotifiedValue = 0UL;\r
-BFD03A90 8030FC5C LW V0, -32720(GP)
-BFD03A94 0048F802 SW ZERO, 72(V0)
-BFD03A98 CC08 B 0xBFD03AAA
-BFD03A9A 0C00 NOP
+BFD03A90 8030FC5C LW V0, -32720(GP)\r
+BFD03A94 0048F802 SW ZERO, 72(V0)\r
+BFD03A98 CC08 B 0xBFD03AAA\r
+BFD03A9A 0C00 NOP\r
3990: }\r
3991: else\r
3992: {\r
3993: ( pxCurrentTCB->ulNotifiedValue )--;\r
-BFD03A9C 8030FC5C LW V0, -32720(GP)
-BFD03AA0 0048FC62 LW V1, 72(V0)
-BFD03AA4 6DBE ADDIU V1, V1, -1
-BFD03AA6 0048F862 SW V1, 72(V0)
+BFD03A9C 8030FC5C LW V0, -32720(GP)\r
+BFD03AA0 0048FC62 LW V1, 72(V0)\r
+BFD03AA4 6DBE ADDIU V1, V1, -1\r
+BFD03AA6 0048F862 SW V1, 72(V0)\r
3994: }\r
3995: }\r
3996: else\r
3999: }\r
4000: \r
4001: pxCurrentTCB->eNotifyState = eNotWaitingNotification;\r
-BFD03AAA 8030FC5C LW V0, -32720(GP)
-BFD03AAE 004CF802 SW ZERO, 76(V0)
+BFD03AAA 8030FC5C LW V0, -32720(GP)\r
+BFD03AAE 004CF802 SW ZERO, 76(V0)\r
4002: }\r
4003: taskEXIT_CRITICAL();\r
-BFD03AB2 40AA77E8 JALS vTaskExitCritical
-BFD03AB4 0C0040AA BNEZC T2, 0xBFD052B8
-BFD03AB6 0C00 NOP
+BFD03AB2 40AA77E8 JALS vTaskExitCritical\r
+BFD03AB4 0C0040AA BNEZC T2, 0xBFD052B8\r
+BFD03AB6 0C00 NOP\r
4004: \r
4005: return ulReturn;\r
-BFD03AB8 0018FC5E LW V0, 24(S8)
+BFD03AB8 0018FC5E LW V0, 24(S8)\r
4006: }\r
-BFD03ABC 0FBE MOVE SP, S8
-BFD03ABE 4BE9 LW RA, 36(SP)
-BFD03AC0 4BC8 LW S8, 32(SP)
-BFD03AC2 4C15 ADDIU SP, SP, 40
-BFD03AC4 459F JR16 RA
-BFD03AC6 0C00 NOP
+BFD03ABC 0FBE MOVE SP, S8\r
+BFD03ABE 4BE9 LW RA, 36(SP)\r
+BFD03AC0 4BC8 LW S8, 32(SP)\r
+BFD03AC2 4C15 ADDIU SP, SP, 40\r
+BFD03AC4 459F JR16 RA\r
+BFD03AC6 0C00 NOP\r
4007: \r
4008: #endif /* configUSE_TASK_NOTIFICATIONS */\r
4009: /*-----------------------------------------------------------*/\r
4012: \r
4013: BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait )\r
4014: {\r
-BFD02C6C 4FED ADDIU SP, SP, -40
-BFD02C6E CBE9 SW RA, 36(SP)
-BFD02C70 CBC8 SW S8, 32(SP)
-BFD02C72 0FDD MOVE S8, SP
-BFD02C74 0028F89E SW A0, 40(S8)
-BFD02C78 002CF8BE SW A1, 44(S8)
-BFD02C7C 0030F8DE SW A2, 48(S8)
-BFD02C80 0034F8FE SW A3, 52(S8)
+BFD02C6C 4FED ADDIU SP, SP, -40\r
+BFD02C6E CBE9 SW RA, 36(SP)\r
+BFD02C70 CBC8 SW S8, 32(SP)\r
+BFD02C72 0FDD MOVE S8, SP\r
+BFD02C74 0028F89E SW A0, 40(S8)\r
+BFD02C78 002CF8BE SW A1, 44(S8)\r
+BFD02C7C 0030F8DE SW A2, 48(S8)\r
+BFD02C80 0034F8FE SW A3, 52(S8)\r
4015: TickType_t xTimeToWake;\r
4016: BaseType_t xReturn;\r
4017: \r
4018: taskENTER_CRITICAL();\r
-BFD02C84 33B877E8 JALS vTaskEnterCritical
-BFD02C86 0C0033B8 ADDIU SP, T8, 3072
-BFD02C88 0C00 NOP
+BFD02C84 33B877E8 JALS vTaskEnterCritical\r
+BFD02C86 0C0033B8 ADDIU SP, T8, 3072\r
+BFD02C88 0C00 NOP\r
4019: {\r
4020: /* Only block if a notification is not already pending. */\r
4021: if( pxCurrentTCB->eNotifyState != eNotified )\r
-BFD02C8A 8030FC5C LW V0, -32720(GP)
-BFD02C8E 004CFC62 LW V1, 76(V0)
-BFD02C92 ED02 LI V0, 2
-BFD02C94 00589443 BEQ V1, V0, 0xBFD02D48
-BFD02C96 0C000058 SLL V0, T8, 1
-BFD02C98 0C00 NOP
+BFD02C8A 8030FC5C LW V0, -32720(GP)\r
+BFD02C8E 004CFC62 LW V1, 76(V0)\r
+BFD02C92 ED02 LI V0, 2\r
+BFD02C94 00589443 BEQ V1, V0, 0xBFD02D48\r
+BFD02C96 0C000058 SLL V0, T8, 1\r
+BFD02C98 0C00 NOP\r
4022: {\r
4023: /* Clear bits in the task's notification value as bits may get\r
4024: set by the notifying task or interrupt. This can be used to\r
4025: clear the value to zero. */\r
4026: pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry;\r
-BFD02C9A 8030FC5C LW V0, -32720(GP)
-BFD02C9E 0048FC82 LW A0, 72(V0)
-BFD02CA2 0028FC7E LW V1, 40(S8)
-BFD02CA6 441B NOT16 V1, V1
-BFD02CA8 449C AND16 V1, A0
-BFD02CAA 0048F862 SW V1, 72(V0)
+BFD02C9A 8030FC5C LW V0, -32720(GP)\r
+BFD02C9E 0048FC82 LW A0, 72(V0)\r
+BFD02CA2 0028FC7E LW V1, 40(S8)\r
+BFD02CA6 441B NOT16 V1, V1\r
+BFD02CA8 449C AND16 V1, A0\r
+BFD02CAA 0048F862 SW V1, 72(V0)\r
4027: \r
4028: /* Mark this task as waiting for a notification. */\r
4029: pxCurrentTCB->eNotifyState = eWaitingNotification;\r
-BFD02CAE 8030FC5C LW V0, -32720(GP)
-BFD02CB2 ED81 LI V1, 1
-BFD02CB4 004CF862 SW V1, 76(V0)
+BFD02CAE 8030FC5C LW V0, -32720(GP)\r
+BFD02CB2 ED81 LI V1, 1\r
+BFD02CB4 004CF862 SW V1, 76(V0)\r
4030: \r
4031: if( xTicksToWait > ( TickType_t ) 0 )\r
-BFD02CB8 0034FC5E LW V0, 52(S8)
-BFD02CBC 004440E2 BEQZC V0, 0xBFD02D48
+BFD02CB8 0034FC5E LW V0, 52(S8)\r
+BFD02CBC 004440E2 BEQZC V0, 0xBFD02D48\r
4032: {\r
4033: /* The task is going to block. First it must be removed\r
4034: from the ready list. */\r
4035: if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r
-BFD02CC0 8030FC5C LW V0, -32720(GP)
-BFD02CC4 6D22 ADDIU V0, V0, 4
-BFD02CC6 0C82 MOVE A0, V0
-BFD02CC8 00C877E8 JALS uxListRemove
-BFD02CCA 0C0000C8 SLL A2, T0, 1
-BFD02CCC 0C00 NOP
-BFD02CCE 000C40A2 BNEZC V0, 0xBFD02CEA
+BFD02CC0 8030FC5C LW V0, -32720(GP)\r
+BFD02CC4 6D22 ADDIU V0, V0, 4\r
+BFD02CC6 0C82 MOVE A0, V0\r
+BFD02CC8 00C877E8 JALS uxListRemove\r
+BFD02CCA 0C0000C8 SLL A2, T0, 1\r
+BFD02CCC 0C00 NOP\r
+BFD02CCE 000C40A2 BNEZC V0, 0xBFD02CEA\r
4036: {\r
4037: /* The current task must be in a ready list, so there is\r
4038: no need to check, and the port reset macro can be called\r
4039: directly. */\r
4040: portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );\r
-BFD02CD2 8030FC5C LW V0, -32720(GP)
-BFD02CD6 692B LW V0, 44(V0)
-BFD02CD8 ED81 LI V1, 1
-BFD02CDA 10100062 SLLV V0, V0, V1
-BFD02CDC 441A1010 ADDI ZERO, S0, 17434
-BFD02CDE 441A NOT16 V1, V0
-BFD02CE0 8040FC5C LW V0, -32704(GP)
-BFD02CE4 4493 AND16 V0, V1
-BFD02CE6 8040F85C SW V0, -32704(GP)
+BFD02CD2 8030FC5C LW V0, -32720(GP)\r
+BFD02CD6 692B LW V0, 44(V0)\r
+BFD02CD8 ED81 LI V1, 1\r
+BFD02CDA 10100062 SLLV V0, V0, V1\r
+BFD02CDC 441A1010 ADDI ZERO, S0, 17434\r
+BFD02CDE 441A NOT16 V1, V0\r
+BFD02CE0 8040FC5C LW V0, -32704(GP)\r
+BFD02CE4 4493 AND16 V0, V1\r
+BFD02CE6 8040F85C SW V0, -32704(GP)\r
4041: }\r
4042: else\r
4043: {\r
4047: #if ( INCLUDE_vTaskSuspend == 1 )\r
4048: {\r
4049: if( xTicksToWait == portMAX_DELAY )\r
-BFD02CEA 0034FC7E LW V1, 52(S8)
-BFD02CEE ED7F LI V0, -1
-BFD02CF0 000EB443 BNE V1, V0, 0xBFD02D10
-BFD02CF2 0C00000E SLL ZERO, T6, 1
-BFD02CF4 0C00 NOP
+BFD02CEA 0034FC7E LW V1, 52(S8)\r
+BFD02CEE ED7F LI V0, -1\r
+BFD02CF0 000EB443 BNE V1, V0, 0xBFD02D10\r
+BFD02CF2 0C00000E SLL ZERO, T6, 1\r
+BFD02CF4 0C00 NOP\r
4050: {\r
4051: /* Add the task to the suspended task list instead\r
4052: of a delayed task list to ensure the task is not\r
4053: woken by a timing event. It will block\r
4054: indefinitely. */\r
4055: vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xGenericListItem ) );\r
-BFD02CF6 8030FC5C LW V0, -32720(GP)
-BFD02CFA 6D22 ADDIU V0, V0, 4
-BFD02CFC BFD241A3 LUI V1, 0xBFD2
-BFD02CFE 3083BFD2 LDC1 F30, 12419(S2)
-BFD02D00 80E43083 ADDIU A0, V1, -32540
-BFD02D04 0CA2 MOVE A1, V0
-BFD02D06 3E4A77E8 JALS vListInsertEnd
-BFD02D08 0C003E4A LH S2, 3072(T2)
-BFD02D0A 0C00 NOP
-BFD02D0C CC0D B 0xBFD02D28
-BFD02D0E 0C00 NOP
+BFD02CF6 8030FC5C LW V0, -32720(GP)\r
+BFD02CFA 6D22 ADDIU V0, V0, 4\r
+BFD02CFC BFD241A3 LUI V1, 0xBFD2\r
+BFD02CFE 3083BFD2 LDC1 F30, 12419(S2)\r
+BFD02D00 80E43083 ADDIU A0, V1, -32540\r
+BFD02D04 0CA2 MOVE A1, V0\r
+BFD02D06 3E4A77E8 JALS vListInsertEnd\r
+BFD02D08 0C003E4A LH S2, 3072(T2)\r
+BFD02D0A 0C00 NOP\r
+BFD02D0C CC0D B 0xBFD02D28\r
+BFD02D0E 0C00 NOP\r
4056: }\r
4057: else\r
4058: {\r
4061: overflow but this doesn't matter, the scheduler will\r
4062: handle it. */\r
4063: xTimeToWake = xTickCount + xTicksToWait;\r
-BFD02D10 803CFC7C LW V1, -32708(GP)
-BFD02D14 0034FC5E LW V0, 52(S8)
-BFD02D18 0526 ADDU V0, V1, V0
-BFD02D1A 0014F85E SW V0, 20(S8)
+BFD02D10 803CFC7C LW V1, -32708(GP)\r
+BFD02D14 0034FC5E LW V0, 52(S8)\r
+BFD02D18 0526 ADDU V0, V1, V0\r
+BFD02D1A 0014F85E SW V0, 20(S8)\r
4064: prvAddCurrentTaskToDelayedList( xTimeToWake );\r
-BFD02D1E 0014FC9E LW A0, 20(S8)
-BFD02D22 373477E8 JALS prvAddCurrentTaskToDelayedList
-BFD02D24 0C003734 LHU T9, 3072(S4)
-BFD02D26 0C00 NOP
+BFD02D1E 0014FC9E LW A0, 20(S8)\r
+BFD02D22 373477E8 JALS prvAddCurrentTaskToDelayedList\r
+BFD02D24 0C003734 LHU T9, 3072(S4)\r
+BFD02D26 0C00 NOP\r
4065: }\r
4066: }\r
4067: #else /* INCLUDE_vTaskSuspend */\r
4080: critical section exits) - but it is not something that\r
4081: application code should ever do. */\r
4082: portYIELD_WITHIN_API();\r
-BFD02D28 4E5677E8 JALS ulPortGetCP0Cause
-BFD02D2A 4E56 ADDIU S2, S2, -5
-BFD02D2C 0C00 NOP
-BFD02D2E 0018F85E SW V0, 24(S8)
-BFD02D32 0018FC5E LW V0, 24(S8)
-BFD02D36 01005042 ORI V0, V0, 256
-BFD02D3A 0018F85E SW V0, 24(S8)
-BFD02D3E 0018FC9E LW A0, 24(S8)
-BFD02D42 4E6677E8 JALS vPortSetCP0Cause
-BFD02D44 4E66 ADDIU S3, S3, 3
-BFD02D46 0C00 NOP
+BFD02D28 4E5677E8 JALS ulPortGetCP0Cause\r
+BFD02D2A 4E56 ADDIU S2, S2, -5\r
+BFD02D2C 0C00 NOP\r
+BFD02D2E 0018F85E SW V0, 24(S8)\r
+BFD02D32 0018FC5E LW V0, 24(S8)\r
+BFD02D36 01005042 ORI V0, V0, 256\r
+BFD02D3A 0018F85E SW V0, 24(S8)\r
+BFD02D3E 0018FC9E LW A0, 24(S8)\r
+BFD02D42 4E6677E8 JALS vPortSetCP0Cause\r
+BFD02D44 4E66 ADDIU S3, S3, 3\r
+BFD02D46 0C00 NOP\r
4083: }\r
4084: else\r
4085: {\r
4092: }\r
4093: }\r
4094: taskEXIT_CRITICAL();\r
-BFD02D48 40AA77E8 JALS vTaskExitCritical
-BFD02D4A 0C0040AA BNEZC T2, 0xBFD0454E
-BFD02D4C 0C00 NOP
+BFD02D48 40AA77E8 JALS vTaskExitCritical\r
+BFD02D4A 0C0040AA BNEZC T2, 0xBFD0454E\r
+BFD02D4C 0C00 NOP\r
4095: \r
4096: taskENTER_CRITICAL();\r
-BFD02D4E 33B877E8 JALS vTaskEnterCritical
-BFD02D50 0C0033B8 ADDIU SP, T8, 3072
-BFD02D52 0C00 NOP
+BFD02D4E 33B877E8 JALS vTaskEnterCritical\r
+BFD02D50 0C0033B8 ADDIU SP, T8, 3072\r
+BFD02D52 0C00 NOP\r
4097: {\r
4098: if( pulNotificationValue != NULL )\r
-BFD02D54 0030FC5E LW V0, 48(S8)
-BFD02D58 000740E2 BEQZC V0, 0xBFD02D6A
+BFD02D54 0030FC5E LW V0, 48(S8)\r
+BFD02D58 000740E2 BEQZC V0, 0xBFD02D6A\r
4099: {\r
4100: /* Output the current notification value, which may or may not\r
4101: have changed. */\r
4102: *pulNotificationValue = pxCurrentTCB->ulNotifiedValue;\r
-BFD02D5C 8030FC5C LW V0, -32720(GP)
-BFD02D60 0048FC62 LW V1, 72(V0)
-BFD02D64 0030FC5E LW V0, 48(S8)
-BFD02D68 E9A0 SW V1, 0(V0)
+BFD02D5C 8030FC5C LW V0, -32720(GP)\r
+BFD02D60 0048FC62 LW V1, 72(V0)\r
+BFD02D64 0030FC5E LW V0, 48(S8)\r
+BFD02D68 E9A0 SW V1, 0(V0)\r
4103: }\r
4104: \r
4105: /* If eNotifyValue is set then either the task never entered the\r
4107: task unblocked because of a notification. Otherwise the task\r
4108: unblocked because of a timeout. */\r
4109: if( pxCurrentTCB->eNotifyState == eWaitingNotification )\r
-BFD02D6A 8030FC5C LW V0, -32720(GP)
-BFD02D6E 004CFC62 LW V1, 76(V0)
-BFD02D72 ED01 LI V0, 1
-BFD02D74 0005B443 BNE V1, V0, 0xBFD02D82
-BFD02D76 0C000005 SLL ZERO, A1, 1
-BFD02D78 0C00 NOP
+BFD02D6A 8030FC5C LW V0, -32720(GP)\r
+BFD02D6E 004CFC62 LW V1, 76(V0)\r
+BFD02D72 ED01 LI V0, 1\r
+BFD02D74 0005B443 BNE V1, V0, 0xBFD02D82\r
+BFD02D76 0C000005 SLL ZERO, A1, 1\r
+BFD02D78 0C00 NOP\r
4110: {\r
4111: /* A notification was not received. */\r
4112: xReturn = pdFALSE;\r
-BFD02D7A 0010F81E SW ZERO, 16(S8)
-BFD02D7E CC0E B 0xBFD02D9C
-BFD02D80 0C00 NOP
+BFD02D7A 0010F81E SW ZERO, 16(S8)\r
+BFD02D7E CC0E B 0xBFD02D9C\r
+BFD02D80 0C00 NOP\r
4113: }\r
4114: else\r
4115: {\r
4116: /* A notification was already pending or a notification was\r
4117: received while the task was waiting. */\r
4118: pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit;\r
-BFD02D82 8030FC5C LW V0, -32720(GP)
-BFD02D86 0048FC82 LW A0, 72(V0)
-BFD02D8A 002CFC7E LW V1, 44(S8)
-BFD02D8E 441B NOT16 V1, V1
-BFD02D90 449C AND16 V1, A0
-BFD02D92 0048F862 SW V1, 72(V0)
+BFD02D82 8030FC5C LW V0, -32720(GP)\r
+BFD02D86 0048FC82 LW A0, 72(V0)\r
+BFD02D8A 002CFC7E LW V1, 44(S8)\r
+BFD02D8E 441B NOT16 V1, V1\r
+BFD02D90 449C AND16 V1, A0\r
+BFD02D92 0048F862 SW V1, 72(V0)\r
4119: xReturn = pdTRUE;\r
-BFD02D96 ED01 LI V0, 1
-BFD02D98 0010F85E SW V0, 16(S8)
+BFD02D96 ED01 LI V0, 1\r
+BFD02D98 0010F85E SW V0, 16(S8)\r
4120: }\r
4121: \r
4122: pxCurrentTCB->eNotifyState = eNotWaitingNotification;\r
-BFD02D9C 8030FC5C LW V0, -32720(GP)
-BFD02DA0 004CF802 SW ZERO, 76(V0)
+BFD02D9C 8030FC5C LW V0, -32720(GP)\r
+BFD02DA0 004CF802 SW ZERO, 76(V0)\r
4123: }\r
4124: taskEXIT_CRITICAL();\r
-BFD02DA4 40AA77E8 JALS vTaskExitCritical
-BFD02DA6 0C0040AA BNEZC T2, 0xBFD045AA
-BFD02DA8 0C00 NOP
+BFD02DA4 40AA77E8 JALS vTaskExitCritical\r
+BFD02DA6 0C0040AA BNEZC T2, 0xBFD045AA\r
+BFD02DA8 0C00 NOP\r
4125: \r
4126: return xReturn;\r
-BFD02DAA 0010FC5E LW V0, 16(S8)
+BFD02DAA 0010FC5E LW V0, 16(S8)\r
4127: }\r
-BFD02DAE 0FBE MOVE SP, S8
-BFD02DB0 4BE9 LW RA, 36(SP)
-BFD02DB2 4BC8 LW S8, 32(SP)
-BFD02DB4 4C15 ADDIU SP, SP, 40
-BFD02DB6 459F JR16 RA
-BFD02DB8 0C00 NOP
+BFD02DAE 0FBE MOVE SP, S8\r
+BFD02DB0 4BE9 LW RA, 36(SP)\r
+BFD02DB2 4BC8 LW S8, 32(SP)\r
+BFD02DB4 4C15 ADDIU SP, SP, 40\r
+BFD02DB6 459F JR16 RA\r
+BFD02DB8 0C00 NOP\r
4128: \r
4129: #endif /* configUSE_TASK_NOTIFICATIONS */\r
4130: /*-----------------------------------------------------------*/\r
4133: \r
4134: BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue )\r
4135: {\r
-BFD01CE8 4FED ADDIU SP, SP, -40
-BFD01CEA CBE9 SW RA, 36(SP)
-BFD01CEC CBC8 SW S8, 32(SP)
-BFD01CEE 0FDD MOVE S8, SP
-BFD01CF0 0028F89E SW A0, 40(S8)
-BFD01CF4 002CF8BE SW A1, 44(S8)
-BFD01CF8 0030F8DE SW A2, 48(S8)
-BFD01CFC 0034F8FE SW A3, 52(S8)
+BFD01CE8 4FED ADDIU SP, SP, -40\r
+BFD01CEA CBE9 SW RA, 36(SP)\r
+BFD01CEC CBC8 SW S8, 32(SP)\r
+BFD01CEE 0FDD MOVE S8, SP\r
+BFD01CF0 0028F89E SW A0, 40(S8)\r
+BFD01CF4 002CF8BE SW A1, 44(S8)\r
+BFD01CF8 0030F8DE SW A2, 48(S8)\r
+BFD01CFC 0034F8FE SW A3, 52(S8)\r
4136: TCB_t * pxTCB;\r
4137: eNotifyValue eOriginalNotifyState;\r
4138: BaseType_t xReturn = pdPASS;\r
-BFD01D00 ED01 LI V0, 1
-BFD01D02 0010F85E SW V0, 16(S8)
+BFD01D00 ED01 LI V0, 1\r
+BFD01D02 0010F85E SW V0, 16(S8)\r
4139: \r
4140: configASSERT( xTaskToNotify );\r
-BFD01D06 0028FC5E LW V0, 40(S8)
-BFD01D0A 000940A2 BNEZC V0, 0xBFD01D20
-BFD01D0E BFD141A2 LUI V0, 0xBFD1
-BFD01D10 3082BFD1 LDC1 F30, 12418(S1)
-BFD01D12 98103082 ADDIU A0, V0, -26608
-BFD01D14 30A09810 SWC1 F0, 12448(S0)
-BFD01D16 102C30A0 ADDIU A1, ZERO, 4140
-BFD01D18 77E8102C ADDI AT, T4, 30696
-BFD01D1A 4B7E77E8 JALS vAssertCalled
-BFD01D1C 4B7E LW K1, 120(SP)
-BFD01D1E 0C00 NOP
+BFD01D06 0028FC5E LW V0, 40(S8)\r
+BFD01D0A 000940A2 BNEZC V0, 0xBFD01D20\r
+BFD01D0E BFD141A2 LUI V0, 0xBFD1\r
+BFD01D10 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD01D12 98103082 ADDIU A0, V0, -26608\r
+BFD01D14 30A09810 SWC1 F0, 12448(S0)\r
+BFD01D16 102C30A0 ADDIU A1, ZERO, 4140\r
+BFD01D18 77E8102C ADDI AT, T4, 30696\r
+BFD01D1A 4B7E77E8 JALS vAssertCalled\r
+BFD01D1C 4B7E LW K1, 120(SP)\r
+BFD01D1E 0C00 NOP\r
4141: pxTCB = ( TCB_t * ) xTaskToNotify;\r
-BFD01D20 0028FC5E LW V0, 40(S8)
-BFD01D24 0014F85E SW V0, 20(S8)
+BFD01D20 0028FC5E LW V0, 40(S8)\r
+BFD01D24 0014F85E SW V0, 20(S8)\r
4142: \r
4143: taskENTER_CRITICAL();\r
-BFD01D28 33B877E8 JALS vTaskEnterCritical
-BFD01D2A 0C0033B8 ADDIU SP, T8, 3072
-BFD01D2C 0C00 NOP
+BFD01D28 33B877E8 JALS vTaskEnterCritical\r
+BFD01D2A 0C0033B8 ADDIU SP, T8, 3072\r
+BFD01D2C 0C00 NOP\r
4144: {\r
4145: if( pulPreviousNotificationValue != NULL )\r
-BFD01D2E 0034FC5E LW V0, 52(S8)
-BFD01D32 000740E2 BEQZC V0, 0xBFD01D44
+BFD01D2E 0034FC5E LW V0, 52(S8)\r
+BFD01D32 000740E2 BEQZC V0, 0xBFD01D44\r
4146: {\r
4147: *pulPreviousNotificationValue = pxTCB->ulNotifiedValue;\r
-BFD01D36 0014FC5E LW V0, 20(S8)
-BFD01D3A 0048FC62 LW V1, 72(V0)
-BFD01D3E 0034FC5E LW V0, 52(S8)
-BFD01D42 E9A0 SW V1, 0(V0)
+BFD01D36 0014FC5E LW V0, 20(S8)\r
+BFD01D3A 0048FC62 LW V1, 72(V0)\r
+BFD01D3E 0034FC5E LW V0, 52(S8)\r
+BFD01D42 E9A0 SW V1, 0(V0)\r
4148: }\r
4149: \r
4150: eOriginalNotifyState = pxTCB->eNotifyState;\r
-BFD01D44 0014FC5E LW V0, 20(S8)
-BFD01D48 004CFC42 LW V0, 76(V0)
-BFD01D4C 0018F85E SW V0, 24(S8)
+BFD01D44 0014FC5E LW V0, 20(S8)\r
+BFD01D48 004CFC42 LW V0, 76(V0)\r
+BFD01D4C 0018F85E SW V0, 24(S8)\r
4151: \r
4152: pxTCB->eNotifyState = eNotified;\r
-BFD01D50 0014FC5E LW V0, 20(S8)
-BFD01D54 ED82 LI V1, 2
-BFD01D56 004CF862 SW V1, 76(V0)
+BFD01D50 0014FC5E LW V0, 20(S8)\r
+BFD01D54 ED82 LI V1, 2\r
+BFD01D56 004CF862 SW V1, 76(V0)\r
4153: \r
4154: switch( eAction )\r
-BFD01D5A 0030FC5E LW V0, 48(S8)
-BFD01D5E 0005B042 SLTIU V0, V0, 5
-BFD01D62 004840E2 BEQZC V0, 0xBFD01DF6
-BFD01D66 0030FC5E LW V0, 48(S8)
-BFD01D6A 25A4 SLL V1, V0, 2
-BFD01D6C BFD041A2 LUI V0, 0xBFD0
-BFD01D6E 3042BFD0 LDC1 F30, 12354(S0)
-BFD01D70 1D7C3042 ADDIU V0, V0, 7548
-BFD01D72 05261D7C LB T3, 1318(GP)
-BFD01D74 0526 ADDU V0, V1, V0
-BFD01D76 6920 LW V0, 0(V0)
-BFD01D78 45A2 JRC V0
-BFD01D7A 0C00 NOP
-BFD01D7C BFD01DF5 LB T7, -16432(S5)
-BFD01D7E 1D91BFD0 LDC1 F30, 7569(S0)
-BFD01D80 BFD01D91 LB T4, -16432(S1)
-BFD01D82 1DABBFD0 LDC1 F30, 7595(S0)
-BFD01D84 BFD01DAB LB T5, -16432(T3)
-BFD01D86 1DC1BFD0 LDC1 F30, 7617(S0)
-BFD01D88 BFD01DC1 LB T6, -16432(AT)
-BFD01D8A 1DD1BFD0 LDC1 F30, 7633(S0)
-BFD01D8C BFD01DD1 LB T6, -16432(S1)
-BFD01D8E FC5EBFD0 LDC1 F30, -930(S0)
+BFD01D5A 0030FC5E LW V0, 48(S8)\r
+BFD01D5E 0005B042 SLTIU V0, V0, 5\r
+BFD01D62 004840E2 BEQZC V0, 0xBFD01DF6\r
+BFD01D66 0030FC5E LW V0, 48(S8)\r
+BFD01D6A 25A4 SLL V1, V0, 2\r
+BFD01D6C BFD041A2 LUI V0, 0xBFD0\r
+BFD01D6E 3042BFD0 LDC1 F30, 12354(S0)\r
+BFD01D70 1D7C3042 ADDIU V0, V0, 7548\r
+BFD01D72 05261D7C LB T3, 1318(GP)\r
+BFD01D74 0526 ADDU V0, V1, V0\r
+BFD01D76 6920 LW V0, 0(V0)\r
+BFD01D78 45A2 JRC V0\r
+BFD01D7A 0C00 NOP\r
+BFD01D7C BFD01DF5 LB T7, -16432(S5)\r
+BFD01D7E 1D91BFD0 LDC1 F30, 7569(S0)\r
+BFD01D80 BFD01D91 LB T4, -16432(S1)\r
+BFD01D82 1DABBFD0 LDC1 F30, 7595(S0)\r
+BFD01D84 BFD01DAB LB T5, -16432(T3)\r
+BFD01D86 1DC1BFD0 LDC1 F30, 7617(S0)\r
+BFD01D88 BFD01DC1 LB T6, -16432(AT)\r
+BFD01D8A 1DD1BFD0 LDC1 F30, 7633(S0)\r
+BFD01D8C BFD01DD1 LB T6, -16432(S1)\r
+BFD01D8E FC5EBFD0 LDC1 F30, -930(S0)\r
4155: {\r
4156: case eSetBits :\r
4157: pxTCB->ulNotifiedValue |= ulValue;\r
-BFD01D90 0014FC5E LW V0, 20(S8)
-BFD01D94 0048FC62 LW V1, 72(V0)
-BFD01D98 002CFC5E LW V0, 44(S8)
-BFD01D9C 44DA OR16 V1, V0
-BFD01D9E 0014FC5E LW V0, 20(S8)
-BFD01DA2 0048F862 SW V1, 72(V0)
+BFD01D90 0014FC5E LW V0, 20(S8)\r
+BFD01D94 0048FC62 LW V1, 72(V0)\r
+BFD01D98 002CFC5E LW V0, 44(S8)\r
+BFD01D9C 44DA OR16 V1, V0\r
+BFD01D9E 0014FC5E LW V0, 20(S8)\r
+BFD01DA2 0048F862 SW V1, 72(V0)\r
4158: break;\r
-BFD01DA6 CC27 B 0xBFD01DF6
-BFD01DA8 0C00 NOP
+BFD01DA6 CC27 B 0xBFD01DF6\r
+BFD01DA8 0C00 NOP\r
4159: \r
4160: case eIncrement :\r
4161: ( pxTCB->ulNotifiedValue )++;\r
-BFD01DAA 0014FC5E LW V0, 20(S8)
-BFD01DAE 0048FC42 LW V0, 72(V0)
-BFD01DB2 6DA0 ADDIU V1, V0, 1
-BFD01DB4 0014FC5E LW V0, 20(S8)
-BFD01DB8 0048F862 SW V1, 72(V0)
+BFD01DAA 0014FC5E LW V0, 20(S8)\r
+BFD01DAE 0048FC42 LW V0, 72(V0)\r
+BFD01DB2 6DA0 ADDIU V1, V0, 1\r
+BFD01DB4 0014FC5E LW V0, 20(S8)\r
+BFD01DB8 0048F862 SW V1, 72(V0)\r
4162: break;\r
-BFD01DBC CC1C B 0xBFD01DF6
-BFD01DBE 0C00 NOP
+BFD01DBC CC1C B 0xBFD01DF6\r
+BFD01DBE 0C00 NOP\r
4163: \r
4164: case eSetValueWithOverwrite :\r
4165: pxTCB->ulNotifiedValue = ulValue;\r
-BFD01DC0 0014FC5E LW V0, 20(S8)
-BFD01DC4 002CFC7E LW V1, 44(S8)
-BFD01DC8 0048F862 SW V1, 72(V0)
+BFD01DC0 0014FC5E LW V0, 20(S8)\r
+BFD01DC4 002CFC7E LW V1, 44(S8)\r
+BFD01DC8 0048F862 SW V1, 72(V0)\r
4166: break;\r
-BFD01DCC CC14 B 0xBFD01DF6
-BFD01DCE 0C00 NOP
+BFD01DCC CC14 B 0xBFD01DF6\r
+BFD01DCE 0C00 NOP\r
4167: \r
4168: case eSetValueWithoutOverwrite :\r
4169: if( eOriginalNotifyState != eNotified )\r
-BFD01DD0 0018FC7E LW V1, 24(S8)
-BFD01DD4 ED02 LI V0, 2
-BFD01DD6 00099443 BEQ V1, V0, 0xBFD01DEC
-BFD01DD8 0C000009 SLL ZERO, T1, 1
-BFD01DDA 0C00 NOP
+BFD01DD0 0018FC7E LW V1, 24(S8)\r
+BFD01DD4 ED02 LI V0, 2\r
+BFD01DD6 00099443 BEQ V1, V0, 0xBFD01DEC\r
+BFD01DD8 0C000009 SLL ZERO, T1, 1\r
+BFD01DDA 0C00 NOP\r
4170: {\r
4171: pxTCB->ulNotifiedValue = ulValue;\r
-BFD01DDC 0014FC5E LW V0, 20(S8)
-BFD01DE0 002CFC7E LW V1, 44(S8)
-BFD01DE4 0048F862 SW V1, 72(V0)
+BFD01DDC 0014FC5E LW V0, 20(S8)\r
+BFD01DE0 002CFC7E LW V1, 44(S8)\r
+BFD01DE4 0048F862 SW V1, 72(V0)\r
4172: }\r
4173: else\r
4174: {\r
4175: /* The value could not be written to the task. */\r
4176: xReturn = pdFAIL;\r
-BFD01DEC 0010F81E SW ZERO, 16(S8)
+BFD01DEC 0010F81E SW ZERO, 16(S8)\r
4177: }\r
4178: break;\r
-BFD01DE8 CC06 B 0xBFD01DF6
-BFD01DEA 0C00 NOP
-BFD01DF0 CC02 B 0xBFD01DF6
-BFD01DF2 0C00 NOP
+BFD01DE8 CC06 B 0xBFD01DF6\r
+BFD01DEA 0C00 NOP\r
+BFD01DF0 CC02 B 0xBFD01DF6\r
+BFD01DF2 0C00 NOP\r
4179: \r
4180: case eNoAction:\r
4181: /* The task is being notified without its notify value being\r
4182: updated. */\r
4183: break;\r
-BFD01DF4 0C00 NOP
+BFD01DF4 0C00 NOP\r
4184: }\r
4185: \r
4186: \r
4187: /* If the task is in the blocked state specifically to wait for a\r
4188: notification then unblock it now. */\r
4189: if( eOriginalNotifyState == eWaitingNotification )\r
-BFD01DF6 0018FC7E LW V1, 24(S8)
-BFD01DFA ED01 LI V0, 1
-BFD01DFC 004EB443 BNE V1, V0, 0xBFD01E9C
-BFD01DFE 0C00004E SLL V0, T6, 1
-BFD01E00 0C00 NOP
+BFD01DF6 0018FC7E LW V1, 24(S8)\r
+BFD01DFA ED01 LI V0, 1\r
+BFD01DFC 004EB443 BNE V1, V0, 0xBFD01E9C\r
+BFD01DFE 0C00004E SLL V0, T6, 1\r
+BFD01E00 0C00 NOP\r
4190: {\r
4191: ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );\r
-BFD01E02 0014FC5E LW V0, 20(S8)
-BFD01E06 6D22 ADDIU V0, V0, 4
-BFD01E08 0C82 MOVE A0, V0
-BFD01E0A 00C877E8 JALS uxListRemove
-BFD01E0C 0C0000C8 SLL A2, T0, 1
-BFD01E0E 0C00 NOP
+BFD01E02 0014FC5E LW V0, 20(S8)\r
+BFD01E06 6D22 ADDIU V0, V0, 4\r
+BFD01E08 0C82 MOVE A0, V0\r
+BFD01E0A 00C877E8 JALS uxListRemove\r
+BFD01E0C 0C0000C8 SLL A2, T0, 1\r
+BFD01E0E 0C00 NOP\r
4192: prvAddTaskToReadyList( pxTCB );\r
-BFD01E10 0014FC5E LW V0, 20(S8)
-BFD01E14 692B LW V0, 44(V0)
-BFD01E16 ED81 LI V1, 1
-BFD01E18 18100062 SLLV V1, V0, V1
-BFD01E1A FC5C1810 SB ZERO, -932(S0)
-BFD01E1C 8040FC5C LW V0, -32704(GP)
-BFD01E20 44D3 OR16 V0, V1
-BFD01E22 8040F85C SW V0, -32704(GP)
-BFD01E26 0014FC5E LW V0, 20(S8)
-BFD01E2A 692B LW V0, 44(V0)
-BFD01E2C 2524 SLL V0, V0, 2
-BFD01E2E 25A4 SLL V1, V0, 2
-BFD01E30 05B4 ADDU V1, V0, V1
-BFD01E32 BFD241A2 LUI V0, 0xBFD2
-BFD01E34 3042BFD2 LDC1 F30, 12354(S2)
-BFD01E36 806C3042 ADDIU V0, V0, -32660
-BFD01E3A 05A6 ADDU V1, V1, V0
-BFD01E3C 0014FC5E LW V0, 20(S8)
-BFD01E40 6D22 ADDIU V0, V0, 4
-BFD01E42 0C83 MOVE A0, V1
-BFD01E44 0CA2 MOVE A1, V0
-BFD01E46 3E4A77E8 JALS vListInsertEnd
-BFD01E48 0C003E4A LH S2, 3072(T2)
-BFD01E4A 0C00 NOP
+BFD01E10 0014FC5E LW V0, 20(S8)\r
+BFD01E14 692B LW V0, 44(V0)\r
+BFD01E16 ED81 LI V1, 1\r
+BFD01E18 18100062 SLLV V1, V0, V1\r
+BFD01E1A FC5C1810 SB ZERO, -932(S0)\r
+BFD01E1C 8040FC5C LW V0, -32704(GP)\r
+BFD01E20 44D3 OR16 V0, V1\r
+BFD01E22 8040F85C SW V0, -32704(GP)\r
+BFD01E26 0014FC5E LW V0, 20(S8)\r
+BFD01E2A 692B LW V0, 44(V0)\r
+BFD01E2C 2524 SLL V0, V0, 2\r
+BFD01E2E 25A4 SLL V1, V0, 2\r
+BFD01E30 05B4 ADDU V1, V0, V1\r
+BFD01E32 BFD241A2 LUI V0, 0xBFD2\r
+BFD01E34 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD01E36 806C3042 ADDIU V0, V0, -32660\r
+BFD01E3A 05A6 ADDU V1, V1, V0\r
+BFD01E3C 0014FC5E LW V0, 20(S8)\r
+BFD01E40 6D22 ADDIU V0, V0, 4\r
+BFD01E42 0C83 MOVE A0, V1\r
+BFD01E44 0CA2 MOVE A1, V0\r
+BFD01E46 3E4A77E8 JALS vListInsertEnd\r
+BFD01E48 0C003E4A LH S2, 3072(T2)\r
+BFD01E4A 0C00 NOP\r
4193: \r
4194: /* The task should not have been on an event list. */\r
4195: configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );\r
-BFD01E4C 0014FC5E LW V0, 20(S8)
-BFD01E50 692A LW V0, 40(V0)
-BFD01E52 000940E2 BEQZC V0, 0xBFD01E68
-BFD01E56 BFD141A2 LUI V0, 0xBFD1
-BFD01E58 3082BFD1 LDC1 F30, 12418(S1)
-BFD01E5A 98103082 ADDIU A0, V0, -26608
-BFD01E5C 30A09810 SWC1 F0, 12448(S0)
-BFD01E5E 106330A0 ADDIU A1, ZERO, 4195
-BFD01E60 77E81063 ADDI V1, V1, 30696
-BFD01E62 4B7E77E8 JALS vAssertCalled
-BFD01E64 4B7E LW K1, 120(SP)
-BFD01E66 0C00 NOP
+BFD01E4C 0014FC5E LW V0, 20(S8)\r
+BFD01E50 692A LW V0, 40(V0)\r
+BFD01E52 000940E2 BEQZC V0, 0xBFD01E68\r
+BFD01E56 BFD141A2 LUI V0, 0xBFD1\r
+BFD01E58 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD01E5A 98103082 ADDIU A0, V0, -26608\r
+BFD01E5C 30A09810 SWC1 F0, 12448(S0)\r
+BFD01E5E 106330A0 ADDIU A1, ZERO, 4195\r
+BFD01E60 77E81063 ADDI V1, V1, 30696\r
+BFD01E62 4B7E77E8 JALS vAssertCalled\r
+BFD01E64 4B7E LW K1, 120(SP)\r
+BFD01E66 0C00 NOP\r
4196: \r
4197: #if( configUSE_TICKLESS_IDLE != 0 )\r
4198: {\r
4211: #endif\r
4212: \r
4213: if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )\r
-BFD01E68 0014FC5E LW V0, 20(S8)
-BFD01E6C 69AB LW V1, 44(V0)
-BFD01E6E 8030FC5C LW V0, -32720(GP)
-BFD01E72 692B LW V0, 44(V0)
-BFD01E74 13900062 SLTU V0, V0, V1
-BFD01E76 40E21390 ADDI GP, S0, 16610
-BFD01E78 001040E2 BEQZC V0, 0xBFD01E9C
+BFD01E68 0014FC5E LW V0, 20(S8)\r
+BFD01E6C 69AB LW V1, 44(V0)\r
+BFD01E6E 8030FC5C LW V0, -32720(GP)\r
+BFD01E72 692B LW V0, 44(V0)\r
+BFD01E74 13900062 SLTU V0, V0, V1\r
+BFD01E76 40E21390 ADDI GP, S0, 16610\r
+BFD01E78 001040E2 BEQZC V0, 0xBFD01E9C\r
4214: {\r
4215: /* The notified task has a priority above the currently\r
4216: executing task so a yield is required. */\r
4217: taskYIELD_IF_USING_PREEMPTION();\r
-BFD01E7C 4E5677E8 JALS ulPortGetCP0Cause
-BFD01E7E 4E56 ADDIU S2, S2, -5
-BFD01E80 0C00 NOP
-BFD01E82 001CF85E SW V0, 28(S8)
-BFD01E86 001CFC5E LW V0, 28(S8)
-BFD01E8A 01005042 ORI V0, V0, 256
-BFD01E8E 001CF85E SW V0, 28(S8)
-BFD01E92 001CFC9E LW A0, 28(S8)
-BFD01E96 4E6677E8 JALS vPortSetCP0Cause
-BFD01E98 4E66 ADDIU S3, S3, 3
-BFD01E9A 0C00 NOP
+BFD01E7C 4E5677E8 JALS ulPortGetCP0Cause\r
+BFD01E7E 4E56 ADDIU S2, S2, -5\r
+BFD01E80 0C00 NOP\r
+BFD01E82 001CF85E SW V0, 28(S8)\r
+BFD01E86 001CFC5E LW V0, 28(S8)\r
+BFD01E8A 01005042 ORI V0, V0, 256\r
+BFD01E8E 001CF85E SW V0, 28(S8)\r
+BFD01E92 001CFC9E LW A0, 28(S8)\r
+BFD01E96 4E6677E8 JALS vPortSetCP0Cause\r
+BFD01E98 4E66 ADDIU S3, S3, 3\r
+BFD01E9A 0C00 NOP\r
4218: }\r
4219: else\r
4220: {\r
4227: }\r
4228: }\r
4229: taskEXIT_CRITICAL();\r
-BFD01E9C 40AA77E8 JALS vTaskExitCritical
-BFD01E9E 0C0040AA BNEZC T2, 0xBFD036A2
-BFD01EA0 0C00 NOP
+BFD01E9C 40AA77E8 JALS vTaskExitCritical\r
+BFD01E9E 0C0040AA BNEZC T2, 0xBFD036A2\r
+BFD01EA0 0C00 NOP\r
4230: \r
4231: return xReturn;\r
-BFD01EA2 0010FC5E LW V0, 16(S8)
+BFD01EA2 0010FC5E LW V0, 16(S8)\r
4232: }\r
-BFD01EA6 0FBE MOVE SP, S8
-BFD01EA8 4BE9 LW RA, 36(SP)
-BFD01EAA 4BC8 LW S8, 32(SP)
-BFD01EAC 4C15 ADDIU SP, SP, 40
-BFD01EAE 459F JR16 RA
-BFD01EB0 0C00 NOP
+BFD01EA6 0FBE MOVE SP, S8\r
+BFD01EA8 4BE9 LW RA, 36(SP)\r
+BFD01EAA 4BC8 LW S8, 32(SP)\r
+BFD01EAC 4C15 ADDIU SP, SP, 40\r
+BFD01EAE 459F JR16 RA\r
+BFD01EB0 0C00 NOP\r
4233: \r
4234: #endif /* configUSE_TASK_NOTIFICATIONS */\r
4235: /*-----------------------------------------------------------*/\r
4238: \r
4239: BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken )\r
4240: {\r
-BFD01EB4 4FED ADDIU SP, SP, -40
-BFD01EB6 CBE9 SW RA, 36(SP)
-BFD01EB8 CBC8 SW S8, 32(SP)
-BFD01EBA 0FDD MOVE S8, SP
-BFD01EBC 0028F89E SW A0, 40(S8)
-BFD01EC0 002CF8BE SW A1, 44(S8)
-BFD01EC4 0030F8DE SW A2, 48(S8)
-BFD01EC8 0034F8FE SW A3, 52(S8)
+BFD01EB4 4FED ADDIU SP, SP, -40\r
+BFD01EB6 CBE9 SW RA, 36(SP)\r
+BFD01EB8 CBC8 SW S8, 32(SP)\r
+BFD01EBA 0FDD MOVE S8, SP\r
+BFD01EBC 0028F89E SW A0, 40(S8)\r
+BFD01EC0 002CF8BE SW A1, 44(S8)\r
+BFD01EC4 0030F8DE SW A2, 48(S8)\r
+BFD01EC8 0034F8FE SW A3, 52(S8)\r
4241: TCB_t * pxTCB;\r
4242: eNotifyValue eOriginalNotifyState;\r
4243: BaseType_t xReturn = pdPASS;\r
-BFD01ECC ED01 LI V0, 1
-BFD01ECE 0010F85E SW V0, 16(S8)
+BFD01ECC ED01 LI V0, 1\r
+BFD01ECE 0010F85E SW V0, 16(S8)\r
4244: UBaseType_t uxSavedInterruptStatus;\r
4245: \r
4246: configASSERT( xTaskToNotify );\r
-BFD01ED2 0028FC5E LW V0, 40(S8)
-BFD01ED6 000940A2 BNEZC V0, 0xBFD01EEC
-BFD01EDA BFD141A2 LUI V0, 0xBFD1
-BFD01EDC 3082BFD1 LDC1 F30, 12418(S1)
-BFD01EDE 98103082 ADDIU A0, V0, -26608
-BFD01EE0 30A09810 SWC1 F0, 12448(S0)
-BFD01EE2 109630A0 ADDIU A1, ZERO, 4246
-BFD01EE4 77E81096 ADDI A0, S6, 30696
-BFD01EE6 4B7E77E8 JALS vAssertCalled
-BFD01EE8 4B7E LW K1, 120(SP)
-BFD01EEA 0C00 NOP
+BFD01ED2 0028FC5E LW V0, 40(S8)\r
+BFD01ED6 000940A2 BNEZC V0, 0xBFD01EEC\r
+BFD01EDA BFD141A2 LUI V0, 0xBFD1\r
+BFD01EDC 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD01EDE 98103082 ADDIU A0, V0, -26608\r
+BFD01EE0 30A09810 SWC1 F0, 12448(S0)\r
+BFD01EE2 109630A0 ADDIU A1, ZERO, 4246\r
+BFD01EE4 77E81096 ADDI A0, S6, 30696\r
+BFD01EE6 4B7E77E8 JALS vAssertCalled\r
+BFD01EE8 4B7E LW K1, 120(SP)\r
+BFD01EEA 0C00 NOP\r
4247: \r
4248: /* RTOS ports that support interrupt nesting have the concept of a\r
4249: maximum system call (or maximum API call) interrupt priority.\r
4264: portASSERT_IF_INTERRUPT_PRIORITY_INVALID();\r
4265: \r
4266: pxTCB = ( TCB_t * ) xTaskToNotify;\r
-BFD01EEC 0028FC5E LW V0, 40(S8)
-BFD01EF0 0014F85E SW V0, 20(S8)
+BFD01EEC 0028FC5E LW V0, 40(S8)\r
+BFD01EF0 0014F85E SW V0, 20(S8)\r
4267: \r
4268: uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r
-BFD01EF4 475E77E8 JALS uxPortSetInterruptMaskFromISR
-BFD01EF8 0C00 NOP
-BFD01EFA 0018F85E SW V0, 24(S8)
+BFD01EF4 475E77E8 JALS uxPortSetInterruptMaskFromISR\r
+BFD01EF8 0C00 NOP\r
+BFD01EFA 0018F85E SW V0, 24(S8)\r
4269: {\r
4270: eOriginalNotifyState = pxTCB->eNotifyState;\r
-BFD01EFE 0014FC5E LW V0, 20(S8)
-BFD01F02 004CFC42 LW V0, 76(V0)
-BFD01F06 001CF85E SW V0, 28(S8)
+BFD01EFE 0014FC5E LW V0, 20(S8)\r
+BFD01F02 004CFC42 LW V0, 76(V0)\r
+BFD01F06 001CF85E SW V0, 28(S8)\r
4271: \r
4272: pxTCB->eNotifyState = eNotified;\r
-BFD01F0A 0014FC5E LW V0, 20(S8)
-BFD01F0E ED82 LI V1, 2
-BFD01F10 004CF862 SW V1, 76(V0)
+BFD01F0A 0014FC5E LW V0, 20(S8)\r
+BFD01F0E ED82 LI V1, 2\r
+BFD01F10 004CF862 SW V1, 76(V0)\r
4273: \r
4274: switch( eAction )\r
-BFD01F14 0030FC5E LW V0, 48(S8)
-BFD01F18 0005B042 SLTIU V0, V0, 5
-BFD01F1C 004740E2 BEQZC V0, 0xBFD01FAE
-BFD01F20 0030FC5E LW V0, 48(S8)
-BFD01F24 25A4 SLL V1, V0, 2
-BFD01F26 BFD041A2 LUI V0, 0xBFD0
-BFD01F28 3042BFD0 LDC1 F30, 12354(S0)
-BFD01F2A 1F343042 ADDIU V0, V0, 7988
-BFD01F2C 05261F34 LB T9, 1318(S4)
-BFD01F2E 0526 ADDU V0, V1, V0
-BFD01F30 6920 LW V0, 0(V0)
-BFD01F32 45A2 JRC V0
-BFD01F34 BFD01FAD LB SP, -16432(T5)
-BFD01F36 1F49BFD0 LDC1 F30, 8009(S0)
-BFD01F38 BFD01F49 LB K0, -16432(T1)
-BFD01F3A 1F63BFD0 LDC1 F30, 8035(S0)
-BFD01F3C BFD01F63 LB K1, -16432(V1)
-BFD01F3E 1F79BFD0 LDC1 F30, 8057(S0)
-BFD01F40 BFD01F79 LB K1, -16432(T9)
-BFD01F42 1F89BFD0 LDC1 F30, 8073(S0)
-BFD01F44 BFD01F89 LB GP, -16432(T1)
-BFD01F46 FC5EBFD0 LDC1 F30, -930(S0)
+BFD01F14 0030FC5E LW V0, 48(S8)\r
+BFD01F18 0005B042 SLTIU V0, V0, 5\r
+BFD01F1C 004740E2 BEQZC V0, 0xBFD01FAE\r
+BFD01F20 0030FC5E LW V0, 48(S8)\r
+BFD01F24 25A4 SLL V1, V0, 2\r
+BFD01F26 BFD041A2 LUI V0, 0xBFD0\r
+BFD01F28 3042BFD0 LDC1 F30, 12354(S0)\r
+BFD01F2A 1F343042 ADDIU V0, V0, 7988\r
+BFD01F2C 05261F34 LB T9, 1318(S4)\r
+BFD01F2E 0526 ADDU V0, V1, V0\r
+BFD01F30 6920 LW V0, 0(V0)\r
+BFD01F32 45A2 JRC V0\r
+BFD01F34 BFD01FAD LB SP, -16432(T5)\r
+BFD01F36 1F49BFD0 LDC1 F30, 8009(S0)\r
+BFD01F38 BFD01F49 LB K0, -16432(T1)\r
+BFD01F3A 1F63BFD0 LDC1 F30, 8035(S0)\r
+BFD01F3C BFD01F63 LB K1, -16432(V1)\r
+BFD01F3E 1F79BFD0 LDC1 F30, 8057(S0)\r
+BFD01F40 BFD01F79 LB K1, -16432(T9)\r
+BFD01F42 1F89BFD0 LDC1 F30, 8073(S0)\r
+BFD01F44 BFD01F89 LB GP, -16432(T1)\r
+BFD01F46 FC5EBFD0 LDC1 F30, -930(S0)\r
4275: {\r
4276: case eSetBits :\r
4277: pxTCB->ulNotifiedValue |= ulValue;\r
-BFD01F48 0014FC5E LW V0, 20(S8)
-BFD01F4C 0048FC62 LW V1, 72(V0)
-BFD01F50 002CFC5E LW V0, 44(S8)
-BFD01F54 44DA OR16 V1, V0
-BFD01F56 0014FC5E LW V0, 20(S8)
-BFD01F5A 0048F862 SW V1, 72(V0)
+BFD01F48 0014FC5E LW V0, 20(S8)\r
+BFD01F4C 0048FC62 LW V1, 72(V0)\r
+BFD01F50 002CFC5E LW V0, 44(S8)\r
+BFD01F54 44DA OR16 V1, V0\r
+BFD01F56 0014FC5E LW V0, 20(S8)\r
+BFD01F5A 0048F862 SW V1, 72(V0)\r
4278: break;\r
-BFD01F5E CC27 B 0xBFD01FAE
-BFD01F60 0C00 NOP
+BFD01F5E CC27 B 0xBFD01FAE\r
+BFD01F60 0C00 NOP\r
4279: \r
4280: case eIncrement :\r
4281: ( pxTCB->ulNotifiedValue )++;\r
-BFD01F62 0014FC5E LW V0, 20(S8)
-BFD01F66 0048FC42 LW V0, 72(V0)
-BFD01F6A 6DA0 ADDIU V1, V0, 1
-BFD01F6C 0014FC5E LW V0, 20(S8)
-BFD01F70 0048F862 SW V1, 72(V0)
+BFD01F62 0014FC5E LW V0, 20(S8)\r
+BFD01F66 0048FC42 LW V0, 72(V0)\r
+BFD01F6A 6DA0 ADDIU V1, V0, 1\r
+BFD01F6C 0014FC5E LW V0, 20(S8)\r
+BFD01F70 0048F862 SW V1, 72(V0)\r
4282: break;\r
-BFD01F74 CC1C B 0xBFD01FAE
-BFD01F76 0C00 NOP
+BFD01F74 CC1C B 0xBFD01FAE\r
+BFD01F76 0C00 NOP\r
4283: \r
4284: case eSetValueWithOverwrite :\r
4285: pxTCB->ulNotifiedValue = ulValue;\r
-BFD01F78 0014FC5E LW V0, 20(S8)
-BFD01F7C 002CFC7E LW V1, 44(S8)
-BFD01F80 0048F862 SW V1, 72(V0)
+BFD01F78 0014FC5E LW V0, 20(S8)\r
+BFD01F7C 002CFC7E LW V1, 44(S8)\r
+BFD01F80 0048F862 SW V1, 72(V0)\r
4286: break;\r
-BFD01F84 CC14 B 0xBFD01FAE
-BFD01F86 0C00 NOP
+BFD01F84 CC14 B 0xBFD01FAE\r
+BFD01F86 0C00 NOP\r
4287: \r
4288: case eSetValueWithoutOverwrite :\r
4289: if( eOriginalNotifyState != eNotified )\r
-BFD01F88 001CFC7E LW V1, 28(S8)
-BFD01F8C ED02 LI V0, 2
-BFD01F8E 00099443 BEQ V1, V0, 0xBFD01FA4
-BFD01F90 0C000009 SLL ZERO, T1, 1
-BFD01F92 0C00 NOP
+BFD01F88 001CFC7E LW V1, 28(S8)\r
+BFD01F8C ED02 LI V0, 2\r
+BFD01F8E 00099443 BEQ V1, V0, 0xBFD01FA4\r
+BFD01F90 0C000009 SLL ZERO, T1, 1\r
+BFD01F92 0C00 NOP\r
4290: {\r
4291: pxTCB->ulNotifiedValue = ulValue;\r
-BFD01F94 0014FC5E LW V0, 20(S8)
-BFD01F98 002CFC7E LW V1, 44(S8)
-BFD01F9C 0048F862 SW V1, 72(V0)
+BFD01F94 0014FC5E LW V0, 20(S8)\r
+BFD01F98 002CFC7E LW V1, 44(S8)\r
+BFD01F9C 0048F862 SW V1, 72(V0)\r
4292: }\r
4293: else\r
4294: {\r
4295: /* The value could not be written to the task. */\r
4296: xReturn = pdFAIL;\r
-BFD01FA4 0010F81E SW ZERO, 16(S8)
+BFD01FA4 0010F81E SW ZERO, 16(S8)\r
4297: }\r
4298: break;\r
-BFD01FA0 CC06 B 0xBFD01FAE
-BFD01FA2 0C00 NOP
-BFD01FA8 CC02 B 0xBFD01FAE
-BFD01FAA 0C00 NOP
+BFD01FA0 CC06 B 0xBFD01FAE\r
+BFD01FA2 0C00 NOP\r
+BFD01FA8 CC02 B 0xBFD01FAE\r
+BFD01FAA 0C00 NOP\r
4299: \r
4300: case eNoAction :\r
4301: /* The task is being notified without its notify value being\r
4302: updated. */\r
4303: break;\r
-BFD01FAC 0C00 NOP
+BFD01FAC 0C00 NOP\r
4304: }\r
4305: \r
4306: \r
4307: /* If the task is in the blocked state specifically to wait for a\r
4308: notification then unblock it now. */\r
4309: if( eOriginalNotifyState == eWaitingNotification )\r
-BFD01FAE 001CFC7E LW V1, 28(S8)
-BFD01FB2 ED01 LI V0, 1
-BFD01FB4 0057B443 BNE V1, V0, 0xBFD02066
-BFD01FB6 0C000057 SLL V0, S7, 1
-BFD01FB8 0C00 NOP
+BFD01FAE 001CFC7E LW V1, 28(S8)\r
+BFD01FB2 ED01 LI V0, 1\r
+BFD01FB4 0057B443 BNE V1, V0, 0xBFD02066\r
+BFD01FB6 0C000057 SLL V0, S7, 1\r
+BFD01FB8 0C00 NOP\r
4310: {\r
4311: /* The task should not have been on an event list. */\r
4312: configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );\r
-BFD01FBA 0014FC5E LW V0, 20(S8)
-BFD01FBE 692A LW V0, 40(V0)
-BFD01FC0 000940E2 BEQZC V0, 0xBFD01FD6
-BFD01FC4 BFD141A2 LUI V0, 0xBFD1
-BFD01FC6 3082BFD1 LDC1 F30, 12418(S1)
-BFD01FC8 98103082 ADDIU A0, V0, -26608
-BFD01FCA 30A09810 SWC1 F0, 12448(S0)
-BFD01FCC 10D830A0 ADDIU A1, ZERO, 4312
-BFD01FCE 77E810D8 ADDI A2, T8, 30696
-BFD01FD0 4B7E77E8 JALS vAssertCalled
-BFD01FD2 4B7E LW K1, 120(SP)
-BFD01FD4 0C00 NOP
+BFD01FBA 0014FC5E LW V0, 20(S8)\r
+BFD01FBE 692A LW V0, 40(V0)\r
+BFD01FC0 000940E2 BEQZC V0, 0xBFD01FD6\r
+BFD01FC4 BFD141A2 LUI V0, 0xBFD1\r
+BFD01FC6 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD01FC8 98103082 ADDIU A0, V0, -26608\r
+BFD01FCA 30A09810 SWC1 F0, 12448(S0)\r
+BFD01FCC 10D830A0 ADDIU A1, ZERO, 4312\r
+BFD01FCE 77E810D8 ADDI A2, T8, 30696\r
+BFD01FD0 4B7E77E8 JALS vAssertCalled\r
+BFD01FD2 4B7E LW K1, 120(SP)\r
+BFD01FD4 0C00 NOP\r
4313: \r
4314: if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\r
-BFD01FD6 805CFC5C LW V0, -32676(GP)
-BFD01FDA 002740A2 BNEZC V0, 0xBFD0202C
+BFD01FD6 805CFC5C LW V0, -32676(GP)\r
+BFD01FDA 002740A2 BNEZC V0, 0xBFD0202C\r
4315: {\r
4316: ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );\r
-BFD01FDE 0014FC5E LW V0, 20(S8)
-BFD01FE2 6D22 ADDIU V0, V0, 4
-BFD01FE4 0C82 MOVE A0, V0
-BFD01FE6 00C877E8 JALS uxListRemove
-BFD01FE8 0C0000C8 SLL A2, T0, 1
-BFD01FEA 0C00 NOP
+BFD01FDE 0014FC5E LW V0, 20(S8)\r
+BFD01FE2 6D22 ADDIU V0, V0, 4\r
+BFD01FE4 0C82 MOVE A0, V0\r
+BFD01FE6 00C877E8 JALS uxListRemove\r
+BFD01FE8 0C0000C8 SLL A2, T0, 1\r
+BFD01FEA 0C00 NOP\r
4317: prvAddTaskToReadyList( pxTCB );\r
-BFD01FEC 0014FC5E LW V0, 20(S8)
-BFD01FF0 692B LW V0, 44(V0)
-BFD01FF2 ED81 LI V1, 1
-BFD01FF4 18100062 SLLV V1, V0, V1
-BFD01FF6 FC5C1810 SB ZERO, -932(S0)
-BFD01FF8 8040FC5C LW V0, -32704(GP)
-BFD01FFC 44D3 OR16 V0, V1
-BFD01FFE 8040F85C SW V0, -32704(GP)
-BFD02002 0014FC5E LW V0, 20(S8)
-BFD02006 692B LW V0, 44(V0)
-BFD02008 2524 SLL V0, V0, 2
-BFD0200A 25A4 SLL V1, V0, 2
-BFD0200C 05B4 ADDU V1, V0, V1
-BFD0200E BFD241A2 LUI V0, 0xBFD2
-BFD02010 3042BFD2 LDC1 F30, 12354(S2)
-BFD02012 806C3042 ADDIU V0, V0, -32660
-BFD02016 05A6 ADDU V1, V1, V0
-BFD02018 0014FC5E LW V0, 20(S8)
-BFD0201C 6D22 ADDIU V0, V0, 4
-BFD0201E 0C83 MOVE A0, V1
-BFD02020 0CA2 MOVE A1, V0
-BFD02022 3E4A77E8 JALS vListInsertEnd
-BFD02024 0C003E4A LH S2, 3072(T2)
-BFD02026 0C00 NOP
-BFD02028 CC0C B 0xBFD02042
-BFD0202A 0C00 NOP
+BFD01FEC 0014FC5E LW V0, 20(S8)\r
+BFD01FF0 692B LW V0, 44(V0)\r
+BFD01FF2 ED81 LI V1, 1\r
+BFD01FF4 18100062 SLLV V1, V0, V1\r
+BFD01FF6 FC5C1810 SB ZERO, -932(S0)\r
+BFD01FF8 8040FC5C LW V0, -32704(GP)\r
+BFD01FFC 44D3 OR16 V0, V1\r
+BFD01FFE 8040F85C SW V0, -32704(GP)\r
+BFD02002 0014FC5E LW V0, 20(S8)\r
+BFD02006 692B LW V0, 44(V0)\r
+BFD02008 2524 SLL V0, V0, 2\r
+BFD0200A 25A4 SLL V1, V0, 2\r
+BFD0200C 05B4 ADDU V1, V0, V1\r
+BFD0200E BFD241A2 LUI V0, 0xBFD2\r
+BFD02010 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD02012 806C3042 ADDIU V0, V0, -32660\r
+BFD02016 05A6 ADDU V1, V1, V0\r
+BFD02018 0014FC5E LW V0, 20(S8)\r
+BFD0201C 6D22 ADDIU V0, V0, 4\r
+BFD0201E 0C83 MOVE A0, V1\r
+BFD02020 0CA2 MOVE A1, V0\r
+BFD02022 3E4A77E8 JALS vListInsertEnd\r
+BFD02024 0C003E4A LH S2, 3072(T2)\r
+BFD02026 0C00 NOP\r
+BFD02028 CC0C B 0xBFD02042\r
+BFD0202A 0C00 NOP\r
4318: }\r
4319: else\r
4320: {\r
4321: /* The delayed and ready lists cannot be accessed, so hold\r
4322: this task pending until the scheduler is resumed. */\r
4323: vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );\r
-BFD0202C 0014FC5E LW V0, 20(S8)
-BFD0202E 6D2C0014 EXT ZERO, S4, 20, 14
-BFD02030 6D2C ADDIU V0, V0, 24
-BFD02032 BFD241A3 LUI V1, 0xBFD2
-BFD02034 3083BFD2 LDC1 F30, 12419(S2)
-BFD02036 80D03083 ADDIU A0, V1, -32560
-BFD0203A 0CA2 MOVE A1, V0
-BFD0203C 3E4A77E8 JALS vListInsertEnd
-BFD0203E 0C003E4A LH S2, 3072(T2)
-BFD02040 0C00 NOP
+BFD0202C 0014FC5E LW V0, 20(S8)\r
+BFD0202E 6D2C0014 EXT ZERO, S4, 20, 14\r
+BFD02030 6D2C ADDIU V0, V0, 24\r
+BFD02032 BFD241A3 LUI V1, 0xBFD2\r
+BFD02034 3083BFD2 LDC1 F30, 12419(S2)\r
+BFD02036 80D03083 ADDIU A0, V1, -32560\r
+BFD0203A 0CA2 MOVE A1, V0\r
+BFD0203C 3E4A77E8 JALS vListInsertEnd\r
+BFD0203E 0C003E4A LH S2, 3072(T2)\r
+BFD02040 0C00 NOP\r
4324: }\r
4325: \r
4326: if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )\r
-BFD02042 0014FC5E LW V0, 20(S8)
-BFD02046 69AB LW V1, 44(V0)
-BFD02048 8030FC5C LW V0, -32720(GP)
-BFD0204C 692B LW V0, 44(V0)
-BFD0204E 13900062 SLTU V0, V0, V1
-BFD02050 40E21390 ADDI GP, S0, 16610
-BFD02052 000840E2 BEQZC V0, 0xBFD02066
+BFD02042 0014FC5E LW V0, 20(S8)\r
+BFD02046 69AB LW V1, 44(V0)\r
+BFD02048 8030FC5C LW V0, -32720(GP)\r
+BFD0204C 692B LW V0, 44(V0)\r
+BFD0204E 13900062 SLTU V0, V0, V1\r
+BFD02050 40E21390 ADDI GP, S0, 16610\r
+BFD02052 000840E2 BEQZC V0, 0xBFD02066\r
4327: {\r
4328: /* The notified task has a priority above the currently\r
4329: executing task so a yield is required. */\r
4330: if( pxHigherPriorityTaskWoken != NULL )\r
-BFD02056 0034FC5E LW V0, 52(S8)
-BFD0205A 000440E2 BEQZC V0, 0xBFD02066
+BFD02056 0034FC5E LW V0, 52(S8)\r
+BFD0205A 000440E2 BEQZC V0, 0xBFD02066\r
4331: {\r
4332: *pxHigherPriorityTaskWoken = pdTRUE;\r
-BFD0205E 0034FC5E LW V0, 52(S8)
-BFD02062 ED81 LI V1, 1
-BFD02064 E9A0 SW V1, 0(V0)
+BFD0205E 0034FC5E LW V0, 52(S8)\r
+BFD02062 ED81 LI V1, 1\r
+BFD02064 E9A0 SW V1, 0(V0)\r
4333: }\r
4334: }\r
4335: else\r
4339: }\r
4340: }\r
4341: portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r
-BFD02066 0018FC9E LW A0, 24(S8)
-BFD0206A 4D5E77E8 JALS vPortClearInterruptMaskFromISR
-BFD0206C 4D5E ADDIU T2, T2, -1
-BFD0206E 0C00 NOP
+BFD02066 0018FC9E LW A0, 24(S8)\r
+BFD0206A 4D5E77E8 JALS vPortClearInterruptMaskFromISR\r
+BFD0206C 4D5E ADDIU T2, T2, -1\r
+BFD0206E 0C00 NOP\r
4342: \r
4343: return xReturn;\r
-BFD02070 0010FC5E LW V0, 16(S8)
+BFD02070 0010FC5E LW V0, 16(S8)\r
4344: }\r
-BFD02074 0FBE MOVE SP, S8
-BFD02076 4BE9 LW RA, 36(SP)
-BFD02078 4BC8 LW S8, 32(SP)
-BFD0207A 4C15 ADDIU SP, SP, 40
-BFD0207C 459F JR16 RA
-BFD0207E 0C00 NOP
+BFD02074 0FBE MOVE SP, S8\r
+BFD02076 4BE9 LW RA, 36(SP)\r
+BFD02078 4BC8 LW S8, 32(SP)\r
+BFD0207A 4C15 ADDIU SP, SP, 40\r
+BFD0207C 459F JR16 RA\r
+BFD0207E 0C00 NOP\r
4345: \r
4346: #endif /* configUSE_TASK_NOTIFICATIONS */\r
4347: /*-----------------------------------------------------------*/\r
4350: \r
4351: void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken )\r
4352: {\r
-BFD03190 4FED ADDIU SP, SP, -40
-BFD03192 CBE9 SW RA, 36(SP)
-BFD03194 CBC8 SW S8, 32(SP)
-BFD03196 0FDD MOVE S8, SP
-BFD03198 0028F89E SW A0, 40(S8)
-BFD0319C 002CF8BE SW A1, 44(S8)
+BFD03190 4FED ADDIU SP, SP, -40\r
+BFD03192 CBE9 SW RA, 36(SP)\r
+BFD03194 CBC8 SW S8, 32(SP)\r
+BFD03196 0FDD MOVE S8, SP\r
+BFD03198 0028F89E SW A0, 40(S8)\r
+BFD0319C 002CF8BE SW A1, 44(S8)\r
4353: TCB_t * pxTCB;\r
4354: eNotifyValue eOriginalNotifyState;\r
4355: UBaseType_t uxSavedInterruptStatus;\r
4356: \r
4357: configASSERT( xTaskToNotify );\r
-BFD031A0 0028FC5E LW V0, 40(S8)
-BFD031A4 000940A2 BNEZC V0, 0xBFD031BA
-BFD031A8 BFD141A2 LUI V0, 0xBFD1
-BFD031AA 3082BFD1 LDC1 F30, 12418(S1)
-BFD031AC 98103082 ADDIU A0, V0, -26608
-BFD031AE 30A09810 SWC1 F0, 12448(S0)
-BFD031B0 110530A0 ADDIU A1, ZERO, 4357
-BFD031B2 77E81105 ADDI T0, A1, 30696
-BFD031B4 4B7E77E8 JALS vAssertCalled
-BFD031B6 4B7E LW K1, 120(SP)
-BFD031B8 0C00 NOP
+BFD031A0 0028FC5E LW V0, 40(S8)\r
+BFD031A4 000940A2 BNEZC V0, 0xBFD031BA\r
+BFD031A8 BFD141A2 LUI V0, 0xBFD1\r
+BFD031AA 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD031AC 98103082 ADDIU A0, V0, -26608\r
+BFD031AE 30A09810 SWC1 F0, 12448(S0)\r
+BFD031B0 110530A0 ADDIU A1, ZERO, 4357\r
+BFD031B2 77E81105 ADDI T0, A1, 30696\r
+BFD031B4 4B7E77E8 JALS vAssertCalled\r
+BFD031B6 4B7E LW K1, 120(SP)\r
+BFD031B8 0C00 NOP\r
4358: \r
4359: /* RTOS ports that support interrupt nesting have the concept of a\r
4360: maximum system call (or maximum API call) interrupt priority.\r
4375: portASSERT_IF_INTERRUPT_PRIORITY_INVALID();\r
4376: \r
4377: pxTCB = ( TCB_t * ) xTaskToNotify;\r
-BFD031BA 0028FC5E LW V0, 40(S8)
-BFD031BE 0010F85E SW V0, 16(S8)
+BFD031BA 0028FC5E LW V0, 40(S8)\r
+BFD031BE 0010F85E SW V0, 16(S8)\r
4378: \r
4379: uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r
-BFD031C2 475E77E8 JALS uxPortSetInterruptMaskFromISR
-BFD031C6 0C00 NOP
-BFD031C8 0014F85E SW V0, 20(S8)
+BFD031C2 475E77E8 JALS uxPortSetInterruptMaskFromISR\r
+BFD031C6 0C00 NOP\r
+BFD031C8 0014F85E SW V0, 20(S8)\r
4380: {\r
4381: eOriginalNotifyState = pxTCB->eNotifyState;\r
-BFD031CC 0010FC5E LW V0, 16(S8)
-BFD031D0 004CFC42 LW V0, 76(V0)
-BFD031D4 0018F85E SW V0, 24(S8)
+BFD031CC 0010FC5E LW V0, 16(S8)\r
+BFD031D0 004CFC42 LW V0, 76(V0)\r
+BFD031D4 0018F85E SW V0, 24(S8)\r
4382: pxTCB->eNotifyState = eNotified;\r
-BFD031D8 0010FC5E LW V0, 16(S8)
-BFD031DC ED82 LI V1, 2
-BFD031DE 004CF862 SW V1, 76(V0)
+BFD031D8 0010FC5E LW V0, 16(S8)\r
+BFD031DC ED82 LI V1, 2\r
+BFD031DE 004CF862 SW V1, 76(V0)\r
4383: \r
4384: /* 'Giving' is equivalent to incrementing a count in a counting\r
4385: semaphore. */\r
4386: ( pxTCB->ulNotifiedValue )++;\r
-BFD031E2 0010FC5E LW V0, 16(S8)
-BFD031E6 0048FC42 LW V0, 72(V0)
-BFD031EA 6DA0 ADDIU V1, V0, 1
-BFD031EC 0010FC5E LW V0, 16(S8)
-BFD031F0 0048F862 SW V1, 72(V0)
+BFD031E2 0010FC5E LW V0, 16(S8)\r
+BFD031E6 0048FC42 LW V0, 72(V0)\r
+BFD031EA 6DA0 ADDIU V1, V0, 1\r
+BFD031EC 0010FC5E LW V0, 16(S8)\r
+BFD031F0 0048F862 SW V1, 72(V0)\r
4387: \r
4388: /* If the task is in the blocked state specifically to wait for a\r
4389: notification then unblock it now. */\r
4390: if( eOriginalNotifyState == eWaitingNotification )\r
-BFD031F4 0018FC7E LW V1, 24(S8)
-BFD031F8 ED01 LI V0, 1
-BFD031FA 0057B443 BNE V1, V0, 0xBFD032AC
-BFD031FC 0C000057 SLL V0, S7, 1
-BFD031FE 0C00 NOP
+BFD031F4 0018FC7E LW V1, 24(S8)\r
+BFD031F8 ED01 LI V0, 1\r
+BFD031FA 0057B443 BNE V1, V0, 0xBFD032AC\r
+BFD031FC 0C000057 SLL V0, S7, 1\r
+BFD031FE 0C00 NOP\r
4391: {\r
4392: /* The task should not have been on an event list. */\r
4393: configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );\r
-BFD03200 0010FC5E LW V0, 16(S8)
-BFD03204 692A LW V0, 40(V0)
-BFD03206 000940E2 BEQZC V0, 0xBFD0321C
-BFD0320A BFD141A2 LUI V0, 0xBFD1
-BFD0320C 3082BFD1 LDC1 F30, 12418(S1)
-BFD0320E 98103082 ADDIU A0, V0, -26608
-BFD03210 30A09810 SWC1 F0, 12448(S0)
-BFD03212 112930A0 ADDIU A1, ZERO, 4393
-BFD03214 77E81129 ADDI T1, T1, 30696
-BFD03216 4B7E77E8 JALS vAssertCalled
-BFD03218 4B7E LW K1, 120(SP)
-BFD0321A 0C00 NOP
+BFD03200 0010FC5E LW V0, 16(S8)\r
+BFD03204 692A LW V0, 40(V0)\r
+BFD03206 000940E2 BEQZC V0, 0xBFD0321C\r
+BFD0320A BFD141A2 LUI V0, 0xBFD1\r
+BFD0320C 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD0320E 98103082 ADDIU A0, V0, -26608\r
+BFD03210 30A09810 SWC1 F0, 12448(S0)\r
+BFD03212 112930A0 ADDIU A1, ZERO, 4393\r
+BFD03214 77E81129 ADDI T1, T1, 30696\r
+BFD03216 4B7E77E8 JALS vAssertCalled\r
+BFD03218 4B7E LW K1, 120(SP)\r
+BFD0321A 0C00 NOP\r
4394: \r
4395: if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\r
-BFD0321C 805CFC5C LW V0, -32676(GP)
-BFD03220 002740A2 BNEZC V0, 0xBFD03272
+BFD0321C 805CFC5C LW V0, -32676(GP)\r
+BFD03220 002740A2 BNEZC V0, 0xBFD03272\r
4396: {\r
4397: ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );\r
-BFD03224 0010FC5E LW V0, 16(S8)
-BFD03228 6D22 ADDIU V0, V0, 4
-BFD0322A 0C82 MOVE A0, V0
-BFD0322C 00C877E8 JALS uxListRemove
-BFD0322E 0C0000C8 SLL A2, T0, 1
-BFD03230 0C00 NOP
+BFD03224 0010FC5E LW V0, 16(S8)\r
+BFD03228 6D22 ADDIU V0, V0, 4\r
+BFD0322A 0C82 MOVE A0, V0\r
+BFD0322C 00C877E8 JALS uxListRemove\r
+BFD0322E 0C0000C8 SLL A2, T0, 1\r
+BFD03230 0C00 NOP\r
4398: prvAddTaskToReadyList( pxTCB );\r
-BFD03232 0010FC5E LW V0, 16(S8)
-BFD03236 692B LW V0, 44(V0)
-BFD03238 ED81 LI V1, 1
-BFD0323A 18100062 SLLV V1, V0, V1
-BFD0323C FC5C1810 SB ZERO, -932(S0)
-BFD0323E 8040FC5C LW V0, -32704(GP)
-BFD03242 44D3 OR16 V0, V1
-BFD03244 8040F85C SW V0, -32704(GP)
-BFD03248 0010FC5E LW V0, 16(S8)
-BFD0324C 692B LW V0, 44(V0)
-BFD0324E 2524 SLL V0, V0, 2
-BFD03250 25A4 SLL V1, V0, 2
-BFD03252 05B4 ADDU V1, V0, V1
-BFD03254 BFD241A2 LUI V0, 0xBFD2
-BFD03256 3042BFD2 LDC1 F30, 12354(S2)
-BFD03258 806C3042 ADDIU V0, V0, -32660
-BFD0325C 05A6 ADDU V1, V1, V0
-BFD0325E 0010FC5E LW V0, 16(S8)
-BFD03262 6D22 ADDIU V0, V0, 4
-BFD03264 0C83 MOVE A0, V1
-BFD03266 0CA2 MOVE A1, V0
-BFD03268 3E4A77E8 JALS vListInsertEnd
-BFD0326A 0C003E4A LH S2, 3072(T2)
-BFD0326C 0C00 NOP
-BFD0326E CC0C B 0xBFD03288
-BFD03270 0C00 NOP
+BFD03232 0010FC5E LW V0, 16(S8)\r
+BFD03236 692B LW V0, 44(V0)\r
+BFD03238 ED81 LI V1, 1\r
+BFD0323A 18100062 SLLV V1, V0, V1\r
+BFD0323C FC5C1810 SB ZERO, -932(S0)\r
+BFD0323E 8040FC5C LW V0, -32704(GP)\r
+BFD03242 44D3 OR16 V0, V1\r
+BFD03244 8040F85C SW V0, -32704(GP)\r
+BFD03248 0010FC5E LW V0, 16(S8)\r
+BFD0324C 692B LW V0, 44(V0)\r
+BFD0324E 2524 SLL V0, V0, 2\r
+BFD03250 25A4 SLL V1, V0, 2\r
+BFD03252 05B4 ADDU V1, V0, V1\r
+BFD03254 BFD241A2 LUI V0, 0xBFD2\r
+BFD03256 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD03258 806C3042 ADDIU V0, V0, -32660\r
+BFD0325C 05A6 ADDU V1, V1, V0\r
+BFD0325E 0010FC5E LW V0, 16(S8)\r
+BFD03262 6D22 ADDIU V0, V0, 4\r
+BFD03264 0C83 MOVE A0, V1\r
+BFD03266 0CA2 MOVE A1, V0\r
+BFD03268 3E4A77E8 JALS vListInsertEnd\r
+BFD0326A 0C003E4A LH S2, 3072(T2)\r
+BFD0326C 0C00 NOP\r
+BFD0326E CC0C B 0xBFD03288\r
+BFD03270 0C00 NOP\r
4399: }\r
4400: else\r
4401: {\r
4402: /* The delayed and ready lists cannot be accessed, so hold\r
4403: this task pending until the scheduler is resumed. */\r
4404: vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );\r
-BFD03272 0010FC5E LW V0, 16(S8)
-BFD03274 6D2C0010 EXT ZERO, S0, 20, 14
-BFD03276 6D2C ADDIU V0, V0, 24
-BFD03278 BFD241A3 LUI V1, 0xBFD2
-BFD0327A 3083BFD2 LDC1 F30, 12419(S2)
-BFD0327C 80D03083 ADDIU A0, V1, -32560
-BFD03280 0CA2 MOVE A1, V0
-BFD03282 3E4A77E8 JALS vListInsertEnd
-BFD03284 0C003E4A LH S2, 3072(T2)
-BFD03286 0C00 NOP
+BFD03272 0010FC5E LW V0, 16(S8)\r
+BFD03274 6D2C0010 EXT ZERO, S0, 20, 14\r
+BFD03276 6D2C ADDIU V0, V0, 24\r
+BFD03278 BFD241A3 LUI V1, 0xBFD2\r
+BFD0327A 3083BFD2 LDC1 F30, 12419(S2)\r
+BFD0327C 80D03083 ADDIU A0, V1, -32560\r
+BFD03280 0CA2 MOVE A1, V0\r
+BFD03282 3E4A77E8 JALS vListInsertEnd\r
+BFD03284 0C003E4A LH S2, 3072(T2)\r
+BFD03286 0C00 NOP\r
4405: }\r
4406: \r
4407: if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )\r
-BFD03288 0010FC5E LW V0, 16(S8)
-BFD0328C 69AB LW V1, 44(V0)
-BFD0328E 8030FC5C LW V0, -32720(GP)
-BFD03292 692B LW V0, 44(V0)
-BFD03294 13900062 SLTU V0, V0, V1
-BFD03296 40E21390 ADDI GP, S0, 16610
-BFD03298 000840E2 BEQZC V0, 0xBFD032AC
+BFD03288 0010FC5E LW V0, 16(S8)\r
+BFD0328C 69AB LW V1, 44(V0)\r
+BFD0328E 8030FC5C LW V0, -32720(GP)\r
+BFD03292 692B LW V0, 44(V0)\r
+BFD03294 13900062 SLTU V0, V0, V1\r
+BFD03296 40E21390 ADDI GP, S0, 16610\r
+BFD03298 000840E2 BEQZC V0, 0xBFD032AC\r
4408: {\r
4409: /* The notified task has a priority above the currently\r
4410: executing task so a yield is required. */\r
4411: if( pxHigherPriorityTaskWoken != NULL )\r
-BFD0329C 002CFC5E LW V0, 44(S8)
-BFD032A0 000440E2 BEQZC V0, 0xBFD032AC
+BFD0329C 002CFC5E LW V0, 44(S8)\r
+BFD032A0 000440E2 BEQZC V0, 0xBFD032AC\r
4412: {\r
4413: *pxHigherPriorityTaskWoken = pdTRUE;\r
-BFD032A4 002CFC5E LW V0, 44(S8)
-BFD032A8 ED81 LI V1, 1
-BFD032AA E9A0 SW V1, 0(V0)
+BFD032A4 002CFC5E LW V0, 44(S8)\r
+BFD032A8 ED81 LI V1, 1\r
+BFD032AA E9A0 SW V1, 0(V0)\r
4414: }\r
4415: }\r
4416: else\r
4420: }\r
4421: }\r
4422: portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r
-BFD032AC 0014FC9E LW A0, 20(S8)
-BFD032B0 4D5E77E8 JALS vPortClearInterruptMaskFromISR
-BFD032B2 4D5E ADDIU T2, T2, -1
-BFD032B4 0C00 NOP
+BFD032AC 0014FC9E LW A0, 20(S8)\r
+BFD032B0 4D5E77E8 JALS vPortClearInterruptMaskFromISR\r
+BFD032B2 4D5E ADDIU T2, T2, -1\r
+BFD032B4 0C00 NOP\r
4423: }\r
-BFD032B6 0FBE MOVE SP, S8
-BFD032B8 4BE9 LW RA, 36(SP)
-BFD032BA 4BC8 LW S8, 32(SP)
-BFD032BC 4C15 ADDIU SP, SP, 40
-BFD032BE 459F JR16 RA
-BFD032C0 0C00 NOP
+BFD032B6 0FBE MOVE SP, S8\r
+BFD032B8 4BE9 LW RA, 36(SP)\r
+BFD032BA 4BC8 LW S8, 32(SP)\r
+BFD032BC 4C15 ADDIU SP, SP, 40\r
+BFD032BE 459F JR16 RA\r
+BFD032C0 0C00 NOP\r
4424: \r
4425: #endif /* configUSE_TASK_NOTIFICATIONS */\r
4426: \r
4431: #include "tasks_test_access_functions.h"\r
4432: #endif\r
4433: \r
---- c:/e/dev/freertos/workingcopy/freertos/source/queue.c ---------------------------------------------
+--- c:/e/dev/freertos/workingcopy/freertos/source/queue.c ---------------------------------------------\r
1: /*\r
2: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
3: All rights reserved\r
8: \r
9: FreeRTOS is free software; you can redistribute it and/or modify it under\r
10: the terms of the GNU General Public License (version 2) as published by the\r
-11: Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+11: Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
12: \r
13: ***************************************************************************\r
14: >>! NOTE: The modification to the GPL is included to allow you to !<<\r
259: \r
260: BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )\r
261: {\r
-BFD0388C 4FF1 ADDIU SP, SP, -32
-BFD0388E CBE7 SW RA, 28(SP)
-BFD03890 CBC6 SW S8, 24(SP)
-BFD03892 0FDD MOVE S8, SP
-BFD03894 0020F89E SW A0, 32(S8)
-BFD03898 0024F8BE SW A1, 36(S8)
+BFD0388C 4FF1 ADDIU SP, SP, -32\r
+BFD0388E CBE7 SW RA, 28(SP)\r
+BFD03890 CBC6 SW S8, 24(SP)\r
+BFD03892 0FDD MOVE S8, SP\r
+BFD03894 0020F89E SW A0, 32(S8)\r
+BFD03898 0024F8BE SW A1, 36(S8)\r
262: Queue_t * const pxQueue = ( Queue_t * ) xQueue;\r
-BFD0389C 0020FC5E LW V0, 32(S8)
-BFD038A0 0010F85E SW V0, 16(S8)
+BFD0389C 0020FC5E LW V0, 32(S8)\r
+BFD038A0 0010F85E SW V0, 16(S8)\r
263: \r
264: configASSERT( pxQueue );\r
-BFD038A4 0010FC5E LW V0, 16(S8)
-BFD038A8 000940A2 BNEZC V0, 0xBFD038BE
-BFD038AC BFD141A2 LUI V0, 0xBFD1
-BFD038AE 3082BFD1 LDC1 F30, 12418(S1)
-BFD038B0 9E3C3082 ADDIU A0, V0, -25028
-BFD038B2 30A09E3C LWC1 F17, 12448(GP)
-BFD038B4 010830A0 ADDIU A1, ZERO, 264
-BFD038B8 4B7E77E8 JALS vAssertCalled
-BFD038BA 4B7E LW K1, 120(SP)
-BFD038BC 0C00 NOP
+BFD038A4 0010FC5E LW V0, 16(S8)\r
+BFD038A8 000940A2 BNEZC V0, 0xBFD038BE\r
+BFD038AC BFD141A2 LUI V0, 0xBFD1\r
+BFD038AE 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD038B0 9E3C3082 ADDIU A0, V0, -25028\r
+BFD038B2 30A09E3C LWC1 F17, 12448(GP)\r
+BFD038B4 010830A0 ADDIU A1, ZERO, 264\r
+BFD038B8 4B7E77E8 JALS vAssertCalled\r
+BFD038BA 4B7E LW K1, 120(SP)\r
+BFD038BC 0C00 NOP\r
265: \r
266: taskENTER_CRITICAL();\r
-BFD038BE 33B877E8 JALS vTaskEnterCritical
-BFD038C0 0C0033B8 ADDIU SP, T8, 3072
-BFD038C2 0C00 NOP
+BFD038BE 33B877E8 JALS vTaskEnterCritical\r
+BFD038C0 0C0033B8 ADDIU SP, T8, 3072\r
+BFD038C2 0C00 NOP\r
267: {\r
268: pxQueue->pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize );\r
-BFD038C4 0010FC5E LW V0, 16(S8)
-BFD038C8 6920 LW V0, 0(V0)
-BFD038CA 0010FC7E LW V1, 16(S8)
-BFD038CE 6A3F LW A0, 60(V1)
-BFD038D0 0010FC7E LW V1, 16(S8)
-BFD038D4 0040FC63 LW V1, 64(V1)
-BFD038D8 1A100064 MUL V1, A0, V1
-BFD038DA 05B41A10 SB S0, 1460(S0)
-BFD038DC 05B4 ADDU V1, V0, V1
-BFD038DE 0010FC5E LW V0, 16(S8)
-BFD038E2 E9A1 SW V1, 4(V0)
+BFD038C4 0010FC5E LW V0, 16(S8)\r
+BFD038C8 6920 LW V0, 0(V0)\r
+BFD038CA 0010FC7E LW V1, 16(S8)\r
+BFD038CE 6A3F LW A0, 60(V1)\r
+BFD038D0 0010FC7E LW V1, 16(S8)\r
+BFD038D4 0040FC63 LW V1, 64(V1)\r
+BFD038D8 1A100064 MUL V1, A0, V1\r
+BFD038DA 05B41A10 SB S0, 1460(S0)\r
+BFD038DC 05B4 ADDU V1, V0, V1\r
+BFD038DE 0010FC5E LW V0, 16(S8)\r
+BFD038E2 E9A1 SW V1, 4(V0)\r
269: pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;\r
-BFD038E4 0010FC5E LW V0, 16(S8)
-BFD038E8 E82E SW S0, 56(V0)
+BFD038E4 0010FC5E LW V0, 16(S8)\r
+BFD038E8 E82E SW S0, 56(V0)\r
270: pxQueue->pcWriteTo = pxQueue->pcHead;\r
-BFD038EA 0010FC5E LW V0, 16(S8)
-BFD038EE 69A0 LW V1, 0(V0)
-BFD038F0 0010FC5E LW V0, 16(S8)
-BFD038F4 E9A2 SW V1, 8(V0)
+BFD038EA 0010FC5E LW V0, 16(S8)\r
+BFD038EE 69A0 LW V1, 0(V0)\r
+BFD038F0 0010FC5E LW V0, 16(S8)\r
+BFD038F4 E9A2 SW V1, 8(V0)\r
271: pxQueue->u.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - ( UBaseType_t ) 1U ) * pxQueue->uxItemSize );\r
-BFD038F6 0010FC5E LW V0, 16(S8)
-BFD038FA 6920 LW V0, 0(V0)
-BFD038FC 0010FC7E LW V1, 16(S8)
-BFD03900 69BF LW V1, 60(V1)
-BFD03902 6E3E ADDIU A0, V1, -1
-BFD03904 0010FC7E LW V1, 16(S8)
-BFD03908 0040FC63 LW V1, 64(V1)
-BFD0390C 1A100064 MUL V1, A0, V1
-BFD0390E 05B41A10 SB S0, 1460(S0)
-BFD03910 05B4 ADDU V1, V0, V1
-BFD03912 0010FC5E LW V0, 16(S8)
-BFD03916 E9A3 SW V1, 12(V0)
+BFD038F6 0010FC5E LW V0, 16(S8)\r
+BFD038FA 6920 LW V0, 0(V0)\r
+BFD038FC 0010FC7E LW V1, 16(S8)\r
+BFD03900 69BF LW V1, 60(V1)\r
+BFD03902 6E3E ADDIU A0, V1, -1\r
+BFD03904 0010FC7E LW V1, 16(S8)\r
+BFD03908 0040FC63 LW V1, 64(V1)\r
+BFD0390C 1A100064 MUL V1, A0, V1\r
+BFD0390E 05B41A10 SB S0, 1460(S0)\r
+BFD03910 05B4 ADDU V1, V0, V1\r
+BFD03912 0010FC5E LW V0, 16(S8)\r
+BFD03916 E9A3 SW V1, 12(V0)\r
272: pxQueue->xRxLock = queueUNLOCKED;\r
-BFD03918 0010FC5E LW V0, 16(S8)
-BFD0391C EDFF LI V1, -1
-BFD0391E 0044F862 SW V1, 68(V0)
+BFD03918 0010FC5E LW V0, 16(S8)\r
+BFD0391C EDFF LI V1, -1\r
+BFD0391E 0044F862 SW V1, 68(V0)\r
273: pxQueue->xTxLock = queueUNLOCKED;\r
-BFD03922 0010FC5E LW V0, 16(S8)
-BFD03926 EDFF LI V1, -1
-BFD03928 0048F862 SW V1, 72(V0)
+BFD03922 0010FC5E LW V0, 16(S8)\r
+BFD03926 EDFF LI V1, -1\r
+BFD03928 0048F862 SW V1, 72(V0)\r
274: \r
275: if( xNewQueue == pdFALSE )\r
-BFD0392C 0024FC5E LW V0, 36(S8)
-BFD03930 002340A2 BNEZC V0, 0xBFD0397A
+BFD0392C 0024FC5E LW V0, 36(S8)\r
+BFD03930 002340A2 BNEZC V0, 0xBFD0397A\r
276: {\r
277: /* If there are tasks blocked waiting to read from the queue, then\r
278: the tasks will remain blocked as after this function exits the queue\r
280: the queue, then one should be unblocked as after this function exits\r
281: it will be possible to write to it. */\r
282: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r
-BFD03934 0010FC5E LW V0, 16(S8)
-BFD03938 6924 LW V0, 16(V0)
-BFD0393A 002D40E2 BEQZC V0, 0xBFD03998
+BFD03934 0010FC5E LW V0, 16(S8)\r
+BFD03938 6924 LW V0, 16(V0)\r
+BFD0393A 002D40E2 BEQZC V0, 0xBFD03998\r
283: {\r
284: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) == pdTRUE )\r
-BFD0393E 0010FC5E LW V0, 16(S8)
-BFD03942 6D28 ADDIU V0, V0, 16
-BFD03944 0C82 MOVE A0, V0
-BFD03946 22BC77E8 JALS xTaskRemoveFromEventList
-BFD03948 0C0022BC LWC2 S5, 3072(GP)
-BFD0394A 0C00 NOP
-BFD0394C 0C62 MOVE V1, V0
-BFD0394E ED01 LI V0, 1
-BFD03950 0022B443 BNE V1, V0, 0xBFD03998
-BFD03952 0C000022 SLL AT, V0, 1
-BFD03954 0C00 NOP
+BFD0393E 0010FC5E LW V0, 16(S8)\r
+BFD03942 6D28 ADDIU V0, V0, 16\r
+BFD03944 0C82 MOVE A0, V0\r
+BFD03946 22BC77E8 JALS xTaskRemoveFromEventList\r
+BFD03948 0C0022BC LWC2 S5, 3072(GP)\r
+BFD0394A 0C00 NOP\r
+BFD0394C 0C62 MOVE V1, V0\r
+BFD0394E ED01 LI V0, 1\r
+BFD03950 0022B443 BNE V1, V0, 0xBFD03998\r
+BFD03952 0C000022 SLL AT, V0, 1\r
+BFD03954 0C00 NOP\r
285: {\r
286: queueYIELD_IF_USING_PREEMPTION();\r
-BFD03956 4E1677E8 JALS ulPortGetCP0Cause
-BFD03958 4E16 ADDIU S0, S0, -5
-BFD0395A 0C00 NOP
-BFD0395C 0014F85E SW V0, 20(S8)
-BFD03960 0014FC5E LW V0, 20(S8)
-BFD03964 01005042 ORI V0, V0, 256
-BFD03968 0014F85E SW V0, 20(S8)
-BFD0396C 0014FC9E LW A0, 20(S8)
-BFD03970 4E2677E8 JALS vPortSetCP0Cause
-BFD03972 4E26 ADDIU S1, S1, 3
-BFD03974 0C00 NOP
-BFD03976 CC10 B 0xBFD03998
-BFD03978 0C00 NOP
+BFD03956 4E1677E8 JALS ulPortGetCP0Cause\r
+BFD03958 4E16 ADDIU S0, S0, -5\r
+BFD0395A 0C00 NOP\r
+BFD0395C 0014F85E SW V0, 20(S8)\r
+BFD03960 0014FC5E LW V0, 20(S8)\r
+BFD03964 01005042 ORI V0, V0, 256\r
+BFD03968 0014F85E SW V0, 20(S8)\r
+BFD0396C 0014FC9E LW A0, 20(S8)\r
+BFD03970 4E2677E8 JALS vPortSetCP0Cause\r
+BFD03972 4E26 ADDIU S1, S1, 3\r
+BFD03974 0C00 NOP\r
+BFD03976 CC10 B 0xBFD03998\r
+BFD03978 0C00 NOP\r
287: }\r
288: else\r
289: {\r
299: {\r
300: /* Ensure the event queues start in the correct state. */\r
301: vListInitialise( &( pxQueue->xTasksWaitingToSend ) );\r
-BFD0397A 0010FC5E LW V0, 16(S8)
-BFD0397E 6D28 ADDIU V0, V0, 16
-BFD03980 0C82 MOVE A0, V0
-BFD03982 457077E8 JALS vListInitialise
-BFD03984 4570 SWM16 0x3, 0(SP)
-BFD03986 0C00 NOP
+BFD0397A 0010FC5E LW V0, 16(S8)\r
+BFD0397E 6D28 ADDIU V0, V0, 16\r
+BFD03980 0C82 MOVE A0, V0\r
+BFD03982 457077E8 JALS vListInitialise\r
+BFD03984 4570 SWM16 0x3, 0(SP)\r
+BFD03986 0C00 NOP\r
302: vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );\r
-BFD03988 0010FC5E LW V0, 16(S8)
-BFD0398C 00243042 ADDIU V0, V0, 36
-BFD03990 0C82 MOVE A0, V0
-BFD03992 457077E8 JALS vListInitialise
-BFD03994 4570 SWM16 0x3, 0(SP)
-BFD03996 0C00 NOP
+BFD03988 0010FC5E LW V0, 16(S8)\r
+BFD0398C 00243042 ADDIU V0, V0, 36\r
+BFD03990 0C82 MOVE A0, V0\r
+BFD03992 457077E8 JALS vListInitialise\r
+BFD03994 4570 SWM16 0x3, 0(SP)\r
+BFD03996 0C00 NOP\r
303: }\r
304: }\r
305: taskEXIT_CRITICAL();\r
-BFD03998 40AA77E8 JALS vTaskExitCritical
-BFD0399A 0C0040AA BNEZC T2, 0xBFD0519E
-BFD0399C 0C00 NOP
+BFD03998 40AA77E8 JALS vTaskExitCritical\r
+BFD0399A 0C0040AA BNEZC T2, 0xBFD0519E\r
+BFD0399C 0C00 NOP\r
306: \r
307: /* A value is returned for calling semantic consistency with previous\r
308: versions. */\r
309: return pdPASS;\r
-BFD0399E ED01 LI V0, 1
+BFD0399E ED01 LI V0, 1\r
310: }\r
-BFD039A0 0FBE MOVE SP, S8
-BFD039A2 4BE7 LW RA, 28(SP)
-BFD039A4 4BC6 LW S8, 24(SP)
-BFD039A6 4C11 ADDIU SP, SP, 32
-BFD039A8 459F JR16 RA
-BFD039AA 0C00 NOP
+BFD039A0 0FBE MOVE SP, S8\r
+BFD039A2 4BE7 LW RA, 28(SP)\r
+BFD039A4 4BC6 LW S8, 24(SP)\r
+BFD039A6 4C11 ADDIU SP, SP, 32\r
+BFD039A8 459F JR16 RA\r
+BFD039AA 0C00 NOP\r
311: /*-----------------------------------------------------------*/\r
312: \r
313: QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )\r
314: {\r
-BFD03DF4 4FED ADDIU SP, SP, -40
-BFD03DF6 CBE9 SW RA, 36(SP)
-BFD03DF8 CBC8 SW S8, 32(SP)
-BFD03DFA 0FDD MOVE S8, SP
-BFD03DFC 0028F89E SW A0, 40(S8)
-BFD03E00 002CF8BE SW A1, 44(S8)
-BFD03E04 0C46 MOVE V0, A2
-BFD03E06 0030185E SB V0, 48(S8)
+BFD03DF4 4FED ADDIU SP, SP, -40\r
+BFD03DF6 CBE9 SW RA, 36(SP)\r
+BFD03DF8 CBC8 SW S8, 32(SP)\r
+BFD03DFA 0FDD MOVE S8, SP\r
+BFD03DFC 0028F89E SW A0, 40(S8)\r
+BFD03E00 002CF8BE SW A1, 44(S8)\r
+BFD03E04 0C46 MOVE V0, A2\r
+BFD03E06 0030185E SB V0, 48(S8)\r
315: Queue_t *pxNewQueue;\r
316: size_t xQueueSizeInBytes;\r
317: QueueHandle_t xReturn = NULL;\r
-BFD03E0A 0014F81E SW ZERO, 20(S8)
+BFD03E0A 0014F81E SW ZERO, 20(S8)\r
318: int8_t *pcAllocatedBuffer;\r
319: \r
320: /* Remove compiler warnings about unused parameters should\r
322: ( void ) ucQueueType;\r
323: \r
324: configASSERT( uxQueueLength > ( UBaseType_t ) 0 );\r
-BFD03E0E 0028FC5E LW V0, 40(S8)
-BFD03E12 000940A2 BNEZC V0, 0xBFD03E28
-BFD03E16 BFD141A2 LUI V0, 0xBFD1
-BFD03E18 3082BFD1 LDC1 F30, 12418(S1)
-BFD03E1A 9E3C3082 ADDIU A0, V0, -25028
-BFD03E1C 30A09E3C LWC1 F17, 12448(GP)
-BFD03E1E 014430A0 ADDIU A1, ZERO, 324
-BFD03E22 4B7E77E8 JALS vAssertCalled
-BFD03E24 4B7E LW K1, 120(SP)
-BFD03E26 0C00 NOP
+BFD03E0E 0028FC5E LW V0, 40(S8)\r
+BFD03E12 000940A2 BNEZC V0, 0xBFD03E28\r
+BFD03E16 BFD141A2 LUI V0, 0xBFD1\r
+BFD03E18 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD03E1A 9E3C3082 ADDIU A0, V0, -25028\r
+BFD03E1C 30A09E3C LWC1 F17, 12448(GP)\r
+BFD03E1E 014430A0 ADDIU A1, ZERO, 324\r
+BFD03E22 4B7E77E8 JALS vAssertCalled\r
+BFD03E24 4B7E LW K1, 120(SP)\r
+BFD03E26 0C00 NOP\r
325: \r
326: if( uxItemSize == ( UBaseType_t ) 0 )\r
-BFD03E28 002CFC5E LW V0, 44(S8)
-BFD03E2C 000440A2 BNEZC V0, 0xBFD03E38
+BFD03E28 002CFC5E LW V0, 44(S8)\r
+BFD03E2C 000440A2 BNEZC V0, 0xBFD03E38\r
327: {\r
328: /* There is not going to be a queue storage area. */\r
329: xQueueSizeInBytes = ( size_t ) 0;\r
-BFD03E30 0010F81E SW ZERO, 16(S8)
-BFD03E34 CC0A B 0xBFD03E4A
-BFD03E36 0C00 NOP
+BFD03E30 0010F81E SW ZERO, 16(S8)\r
+BFD03E34 CC0A B 0xBFD03E4A\r
+BFD03E36 0C00 NOP\r
330: }\r
331: else\r
332: {\r
333: /* The queue is one byte longer than asked for to make wrap checking\r
334: easier/faster. */\r
335: xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ) + ( size_t ) 1; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\r
-BFD03E38 0028FC7E LW V1, 40(S8)
-BFD03E3C 002CFC5E LW V0, 44(S8)
-BFD03E40 12100043 MUL V0, V1, V0
-BFD03E42 6D201210 ADDI S0, S0, 27936
-BFD03E44 6D20 ADDIU V0, V0, 1
-BFD03E46 0010F85E SW V0, 16(S8)
+BFD03E38 0028FC7E LW V1, 40(S8)\r
+BFD03E3C 002CFC5E LW V0, 44(S8)\r
+BFD03E40 12100043 MUL V0, V1, V0\r
+BFD03E42 6D201210 ADDI S0, S0, 27936\r
+BFD03E44 6D20 ADDIU V0, V0, 1\r
+BFD03E46 0010F85E SW V0, 16(S8)\r
336: }\r
337: \r
338: /* Allocate the new queue structure and storage area. */\r
339: pcAllocatedBuffer = ( int8_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes );\r
-BFD03E4A 0010FC5E LW V0, 16(S8)
-BFD03E4E 00503042 ADDIU V0, V0, 80
-BFD03E52 0C82 MOVE A0, V0
-BFD03E54 111677E8 JALS pvPortMalloc
-BFD03E56 0C001116 ADDI T0, S6, 3072
-BFD03E58 0C00 NOP
-BFD03E5A 0018F85E SW V0, 24(S8)
+BFD03E4A 0010FC5E LW V0, 16(S8)\r
+BFD03E4E 00503042 ADDIU V0, V0, 80\r
+BFD03E52 0C82 MOVE A0, V0\r
+BFD03E54 111677E8 JALS pvPortMalloc\r
+BFD03E56 0C001116 ADDI T0, S6, 3072\r
+BFD03E58 0C00 NOP\r
+BFD03E5A 0018F85E SW V0, 24(S8)\r
340: \r
341: if( pcAllocatedBuffer != NULL )\r
-BFD03E5E 0018FC5E LW V0, 24(S8)
-BFD03E62 002F40E2 BEQZC V0, 0xBFD03EC4
+BFD03E5E 0018FC5E LW V0, 24(S8)\r
+BFD03E62 002F40E2 BEQZC V0, 0xBFD03EC4\r
342: {\r
343: pxNewQueue = ( Queue_t * ) pcAllocatedBuffer; /*lint !e826 MISRA The buffer cannot be too small because it was dimensioned by sizeof( Queue_t ) + xQueueSizeInBytes. */\r
-BFD03E66 0018FC5E LW V0, 24(S8)
-BFD03E6A 001CF85E SW V0, 28(S8)
+BFD03E66 0018FC5E LW V0, 24(S8)\r
+BFD03E6A 001CF85E SW V0, 28(S8)\r
344: \r
345: if( uxItemSize == ( UBaseType_t ) 0 )\r
-BFD03E6E 002CFC5E LW V0, 44(S8)
-BFD03E72 000740A2 BNEZC V0, 0xBFD03E84
+BFD03E6E 002CFC5E LW V0, 44(S8)\r
+BFD03E72 000740A2 BNEZC V0, 0xBFD03E84\r
346: {\r
347: /* No RAM was allocated for the queue storage area, but PC head\r
348: cannot be set to NULL because NULL is used as a key to say the queue\r
349: is used as a mutex. Therefore just set pcHead to point to the queue\r
350: as a benign value that is known to be within the memory map. */\r
351: pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;\r
-BFD03E76 001CFC7E LW V1, 28(S8)
-BFD03E7A 001CFC5E LW V0, 28(S8)
-BFD03E7E E9A0 SW V1, 0(V0)
-BFD03E80 CC08 B 0xBFD03E92
-BFD03E82 0C00 NOP
+BFD03E76 001CFC7E LW V1, 28(S8)\r
+BFD03E7A 001CFC5E LW V0, 28(S8)\r
+BFD03E7E E9A0 SW V1, 0(V0)\r
+BFD03E80 CC08 B 0xBFD03E92\r
+BFD03E82 0C00 NOP\r
352: }\r
353: else\r
354: {\r
355: /* Jump past the queue structure to find the location of the queue\r
356: storage area - adding the padding bytes to get a better alignment. */\r
357: pxNewQueue->pcHead = pcAllocatedBuffer + sizeof( Queue_t );\r
-BFD03E84 0018FC5E LW V0, 24(S8)
-BFD03E88 00503062 ADDIU V1, V0, 80
-BFD03E8C 001CFC5E LW V0, 28(S8)
-BFD03E90 E9A0 SW V1, 0(V0)
+BFD03E84 0018FC5E LW V0, 24(S8)\r
+BFD03E88 00503062 ADDIU V1, V0, 80\r
+BFD03E8C 001CFC5E LW V0, 28(S8)\r
+BFD03E90 E9A0 SW V1, 0(V0)\r
358: }\r
359: \r
360: /* Initialise the queue members as described above where the queue type\r
361: is defined. */\r
362: pxNewQueue->uxLength = uxQueueLength;\r
-BFD03E92 001CFC5E LW V0, 28(S8)
-BFD03E96 0028FC7E LW V1, 40(S8)
-BFD03E9A E9AF SW V1, 60(V0)
+BFD03E92 001CFC5E LW V0, 28(S8)\r
+BFD03E96 0028FC7E LW V1, 40(S8)\r
+BFD03E9A E9AF SW V1, 60(V0)\r
363: pxNewQueue->uxItemSize = uxItemSize;\r
-BFD03E9C 001CFC5E LW V0, 28(S8)
-BFD03EA0 002CFC7E LW V1, 44(S8)
-BFD03EA4 0040F862 SW V1, 64(V0)
+BFD03E9C 001CFC5E LW V0, 28(S8)\r
+BFD03EA0 002CFC7E LW V1, 44(S8)\r
+BFD03EA4 0040F862 SW V1, 64(V0)\r
364: ( void ) xQueueGenericReset( pxNewQueue, pdTRUE );\r
-BFD03EA8 001CFC9E LW A0, 28(S8)
-BFD03EAC EE81 LI A1, 1
-BFD03EAE 1C4677E8 JALS xQueueGenericReset
-BFD03EB0 0C001C46 LB V0, 3072(A2)
-BFD03EB2 0C00 NOP
+BFD03EA8 001CFC9E LW A0, 28(S8)\r
+BFD03EAC EE81 LI A1, 1\r
+BFD03EAE 1C4677E8 JALS xQueueGenericReset\r
+BFD03EB0 0C001C46 LB V0, 3072(A2)\r
+BFD03EB2 0C00 NOP\r
365: \r
366: #if ( configUSE_TRACE_FACILITY == 1 )\r
367: {\r
372: #if( configUSE_QUEUE_SETS == 1 )\r
373: {\r
374: pxNewQueue->pxQueueSetContainer = NULL;\r
-BFD03EB4 001CFC5E LW V0, 28(S8)
-BFD03EB8 004CF802 SW ZERO, 76(V0)
+BFD03EB4 001CFC5E LW V0, 28(S8)\r
+BFD03EB8 004CF802 SW ZERO, 76(V0)\r
375: }\r
376: #endif /* configUSE_QUEUE_SETS */\r
377: \r
378: traceQUEUE_CREATE( pxNewQueue );\r
379: xReturn = pxNewQueue;\r
-BFD03EBC 001CFC5E LW V0, 28(S8)
-BFD03EC0 0014F85E SW V0, 20(S8)
+BFD03EBC 001CFC5E LW V0, 28(S8)\r
+BFD03EC0 0014F85E SW V0, 20(S8)\r
380: }\r
381: else\r
382: {\r
384: }\r
385: \r
386: configASSERT( xReturn );\r
-BFD03EC4 0014FC5E LW V0, 20(S8)
-BFD03EC8 000940A2 BNEZC V0, 0xBFD03EDE
-BFD03ECC BFD141A2 LUI V0, 0xBFD1
-BFD03ECE 3082BFD1 LDC1 F30, 12418(S1)
-BFD03ED0 9E3C3082 ADDIU A0, V0, -25028
-BFD03ED2 30A09E3C LWC1 F17, 12448(GP)
-BFD03ED4 018230A0 ADDIU A1, ZERO, 386
-BFD03ED8 4B7E77E8 JALS vAssertCalled
-BFD03EDA 4B7E LW K1, 120(SP)
-BFD03EDC 0C00 NOP
+BFD03EC4 0014FC5E LW V0, 20(S8)\r
+BFD03EC8 000940A2 BNEZC V0, 0xBFD03EDE\r
+BFD03ECC BFD141A2 LUI V0, 0xBFD1\r
+BFD03ECE 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD03ED0 9E3C3082 ADDIU A0, V0, -25028\r
+BFD03ED2 30A09E3C LWC1 F17, 12448(GP)\r
+BFD03ED4 018230A0 ADDIU A1, ZERO, 386\r
+BFD03ED8 4B7E77E8 JALS vAssertCalled\r
+BFD03EDA 4B7E LW K1, 120(SP)\r
+BFD03EDC 0C00 NOP\r
387: \r
388: return xReturn;\r
-BFD03EDE 0014FC5E LW V0, 20(S8)
+BFD03EDE 0014FC5E LW V0, 20(S8)\r
389: }\r
-BFD03EE2 0FBE MOVE SP, S8
-BFD03EE4 4BE9 LW RA, 36(SP)
-BFD03EE6 4BC8 LW S8, 32(SP)
-BFD03EE8 4C15 ADDIU SP, SP, 40
-BFD03EEA 459F JR16 RA
-BFD03EEC 0C00 NOP
+BFD03EE2 0FBE MOVE SP, S8\r
+BFD03EE4 4BE9 LW RA, 36(SP)\r
+BFD03EE6 4BC8 LW S8, 32(SP)\r
+BFD03EE8 4C15 ADDIU SP, SP, 40\r
+BFD03EEA 459F JR16 RA\r
+BFD03EEC 0C00 NOP\r
390: /*-----------------------------------------------------------*/\r
391: \r
392: #if ( configUSE_MUTEXES == 1 )\r
393: \r
394: QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )\r
395: {\r
-BFD05958 4FF1 ADDIU SP, SP, -32
-BFD0595A CBE7 SW RA, 28(SP)
-BFD0595C CBC6 SW S8, 24(SP)
-BFD0595E 0FDD MOVE S8, SP
-BFD05960 0C44 MOVE V0, A0
-BFD05962 0020185E SB V0, 32(S8)
-BFD05964 EE500020 AND SP, ZERO, AT
+BFD05958 4FF1 ADDIU SP, SP, -32\r
+BFD0595A CBE7 SW RA, 28(SP)\r
+BFD0595C CBC6 SW S8, 24(SP)\r
+BFD0595E 0FDD MOVE S8, SP\r
+BFD05960 0C44 MOVE V0, A0\r
+BFD05962 0020185E SB V0, 32(S8)\r
+BFD05964 EE500020 AND SP, ZERO, AT\r
396: Queue_t *pxNewQueue;\r
397: \r
398: /* Prevent compiler warnings about unused parameters if\r
401: \r
402: /* Allocate the new queue structure. */\r
403: pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) );\r
-BFD05966 EE50 LI A0, 80
-BFD05968 111677E8 JALS pvPortMalloc
-BFD0596A 0C001116 ADDI T0, S6, 3072
-BFD0596C 0C00 NOP
-BFD0596E 0010F85E SW V0, 16(S8)
+BFD05966 EE50 LI A0, 80\r
+BFD05968 111677E8 JALS pvPortMalloc\r
+BFD0596A 0C001116 ADDI T0, S6, 3072\r
+BFD0596C 0C00 NOP\r
+BFD0596E 0010F85E SW V0, 16(S8)\r
404: if( pxNewQueue != NULL )\r
-BFD05972 0010FC5E LW V0, 16(S8)
-BFD05976 003C40E2 BEQZC V0, 0xBFD059F2
+BFD05972 0010FC5E LW V0, 16(S8)\r
+BFD05976 003C40E2 BEQZC V0, 0xBFD059F2\r
405: {\r
406: /* Information required for priority inheritance. */\r
407: pxNewQueue->pxMutexHolder = NULL;\r
-BFD0597A 0010FC5E LW V0, 16(S8)
-BFD0597E E821 SW S0, 4(V0)
+BFD0597A 0010FC5E LW V0, 16(S8)\r
+BFD0597E E821 SW S0, 4(V0)\r
408: pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;\r
-BFD05980 0010FC5E LW V0, 16(S8)
-BFD05984 E820 SW S0, 0(V0)
+BFD05980 0010FC5E LW V0, 16(S8)\r
+BFD05984 E820 SW S0, 0(V0)\r
409: \r
410: /* Queues used as a mutex no data is actually copied into or out\r
411: of the queue. */\r
412: pxNewQueue->pcWriteTo = NULL;\r
-BFD05986 0010FC5E LW V0, 16(S8)
-BFD0598A E822 SW S0, 8(V0)
+BFD05986 0010FC5E LW V0, 16(S8)\r
+BFD0598A E822 SW S0, 8(V0)\r
413: pxNewQueue->u.pcReadFrom = NULL;\r
-BFD0598C 0010FC5E LW V0, 16(S8)
-BFD05990 E823 SW S0, 12(V0)
+BFD0598C 0010FC5E LW V0, 16(S8)\r
+BFD05990 E823 SW S0, 12(V0)\r
414: \r
415: /* Each mutex has a length of 1 (like a binary semaphore) and\r
416: an item size of 0 as nothing is actually copied into or out\r
417: of the mutex. */\r
418: pxNewQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;\r
-BFD05992 0010FC5E LW V0, 16(S8)
-BFD05996 E82E SW S0, 56(V0)
+BFD05992 0010FC5E LW V0, 16(S8)\r
+BFD05996 E82E SW S0, 56(V0)\r
419: pxNewQueue->uxLength = ( UBaseType_t ) 1U;\r
-BFD05998 0010FC5E LW V0, 16(S8)
-BFD0599C ED81 LI V1, 1
-BFD0599E E9AF SW V1, 60(V0)
+BFD05998 0010FC5E LW V0, 16(S8)\r
+BFD0599C ED81 LI V1, 1\r
+BFD0599E E9AF SW V1, 60(V0)\r
420: pxNewQueue->uxItemSize = ( UBaseType_t ) 0U;\r
-BFD059A0 0010FC5E LW V0, 16(S8)
-BFD059A4 0040F802 SW ZERO, 64(V0)
+BFD059A0 0010FC5E LW V0, 16(S8)\r
+BFD059A4 0040F802 SW ZERO, 64(V0)\r
421: pxNewQueue->xRxLock = queueUNLOCKED;\r
-BFD059A8 0010FC5E LW V0, 16(S8)
-BFD059AC EDFF LI V1, -1
-BFD059AE 0044F862 SW V1, 68(V0)
+BFD059A8 0010FC5E LW V0, 16(S8)\r
+BFD059AC EDFF LI V1, -1\r
+BFD059AE 0044F862 SW V1, 68(V0)\r
422: pxNewQueue->xTxLock = queueUNLOCKED;\r
-BFD059B2 0010FC5E LW V0, 16(S8)
-BFD059B6 EDFF LI V1, -1
-BFD059B8 0048F862 SW V1, 72(V0)
+BFD059B2 0010FC5E LW V0, 16(S8)\r
+BFD059B6 EDFF LI V1, -1\r
+BFD059B8 0048F862 SW V1, 72(V0)\r
423: \r
424: #if ( configUSE_TRACE_FACILITY == 1 )\r
425: {\r
430: #if ( configUSE_QUEUE_SETS == 1 )\r
431: {\r
432: pxNewQueue->pxQueueSetContainer = NULL;\r
-BFD059BC 0010FC5E LW V0, 16(S8)
-BFD059C0 004CF802 SW ZERO, 76(V0)
+BFD059BC 0010FC5E LW V0, 16(S8)\r
+BFD059C0 004CF802 SW ZERO, 76(V0)\r
433: }\r
434: #endif\r
435: \r
436: /* Ensure the event queues start with the correct state. */\r
437: vListInitialise( &( pxNewQueue->xTasksWaitingToSend ) );\r
-BFD059C4 0010FC5E LW V0, 16(S8)
-BFD059C8 6D28 ADDIU V0, V0, 16
-BFD059CA 0C82 MOVE A0, V0
-BFD059CC 457077E8 JALS vListInitialise
-BFD059CE 4570 SWM16 0x3, 0(SP)
-BFD059D0 0C00 NOP
+BFD059C4 0010FC5E LW V0, 16(S8)\r
+BFD059C8 6D28 ADDIU V0, V0, 16\r
+BFD059CA 0C82 MOVE A0, V0\r
+BFD059CC 457077E8 JALS vListInitialise\r
+BFD059CE 4570 SWM16 0x3, 0(SP)\r
+BFD059D0 0C00 NOP\r
438: vListInitialise( &( pxNewQueue->xTasksWaitingToReceive ) );\r
-BFD059D2 0010FC5E LW V0, 16(S8)
-BFD059D6 00243042 ADDIU V0, V0, 36
-BFD059DA 0C82 MOVE A0, V0
-BFD059DC 457077E8 JALS vListInitialise
-BFD059DE 4570 SWM16 0x3, 0(SP)
-BFD059E0 0C00 NOP
+BFD059D2 0010FC5E LW V0, 16(S8)\r
+BFD059D6 00243042 ADDIU V0, V0, 36\r
+BFD059DA 0C82 MOVE A0, V0\r
+BFD059DC 457077E8 JALS vListInitialise\r
+BFD059DE 4570 SWM16 0x3, 0(SP)\r
+BFD059E0 0C00 NOP\r
439: \r
440: traceCREATE_MUTEX( pxNewQueue );\r
441: \r
442: /* Start with the semaphore in the expected state. */\r
443: ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );\r
-BFD059E2 0010FC9E LW A0, 16(S8)
-BFD059E6 0CA0 MOVE A1, ZERO
-BFD059E8 0CC0 MOVE A2, ZERO
-BFD059EA 0CE0 MOVE A3, ZERO
-BFD059EC 06A277E8 JALS xQueueGenericSend
-BFD059EE 06A2 ADDU A1, S1, V0
-BFD059F0 0C00 NOP
+BFD059E2 0010FC9E LW A0, 16(S8)\r
+BFD059E6 0CA0 MOVE A1, ZERO\r
+BFD059E8 0CC0 MOVE A2, ZERO\r
+BFD059EA 0CE0 MOVE A3, ZERO\r
+BFD059EC 06A277E8 JALS xQueueGenericSend\r
+BFD059EE 06A2 ADDU A1, S1, V0\r
+BFD059F0 0C00 NOP\r
444: }\r
445: else\r
446: {\r
448: }\r
449: \r
450: configASSERT( pxNewQueue );\r
-BFD059F2 0010FC5E LW V0, 16(S8)
-BFD059F6 000940A2 BNEZC V0, 0xBFD05A0C
-BFD059FA BFD141A2 LUI V0, 0xBFD1
-BFD059FC 3082BFD1 LDC1 F30, 12418(S1)
-BFD059FE 9E3C3082 ADDIU A0, V0, -25028
-BFD05A00 30A09E3C LWC1 F17, 12448(GP)
-BFD05A02 01C230A0 ADDIU A1, ZERO, 450
-BFD05A06 4B7E77E8 JALS vAssertCalled
-BFD05A08 4B7E LW K1, 120(SP)
-BFD05A0A 0C00 NOP
+BFD059F2 0010FC5E LW V0, 16(S8)\r
+BFD059F6 000940A2 BNEZC V0, 0xBFD05A0C\r
+BFD059FA BFD141A2 LUI V0, 0xBFD1\r
+BFD059FC 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD059FE 9E3C3082 ADDIU A0, V0, -25028\r
+BFD05A00 30A09E3C LWC1 F17, 12448(GP)\r
+BFD05A02 01C230A0 ADDIU A1, ZERO, 450\r
+BFD05A06 4B7E77E8 JALS vAssertCalled\r
+BFD05A08 4B7E LW K1, 120(SP)\r
+BFD05A0A 0C00 NOP\r
451: return pxNewQueue;\r
-BFD05A0C 0010FC5E LW V0, 16(S8)
+BFD05A0C 0010FC5E LW V0, 16(S8)\r
452: }\r
-BFD05A10 0FBE MOVE SP, S8
-BFD05A12 4BE7 LW RA, 28(SP)
-BFD05A14 4BC6 LW S8, 24(SP)
-BFD05A16 4C11 ADDIU SP, SP, 32
-BFD05A18 459F JR16 RA
-BFD05A1A 0C00 NOP
+BFD05A10 0FBE MOVE SP, S8\r
+BFD05A12 4BE7 LW RA, 28(SP)\r
+BFD05A14 4BC6 LW S8, 24(SP)\r
+BFD05A16 4C11 ADDIU SP, SP, 32\r
+BFD05A18 459F JR16 RA\r
+BFD05A1A 0C00 NOP\r
453: \r
454: #endif /* configUSE_MUTEXES */\r
455: /*-----------------------------------------------------------*/\r
488: \r
489: BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )\r
490: {\r
-BFD06AD0 4FED ADDIU SP, SP, -40
-BFD06AD2 CBE9 SW RA, 36(SP)
-BFD06AD4 CBC8 SW S8, 32(SP)
-BFD06AD6 CA07 SW S0, 28(SP)
-BFD06AD8 0FDD MOVE S8, SP
-BFD06ADA 0028F89E SW A0, 40(S8)
+BFD06AD0 4FED ADDIU SP, SP, -40\r
+BFD06AD2 CBE9 SW RA, 36(SP)\r
+BFD06AD4 CBC8 SW S8, 32(SP)\r
+BFD06AD6 CA07 SW S0, 28(SP)\r
+BFD06AD8 0FDD MOVE S8, SP\r
+BFD06ADA 0028F89E SW A0, 40(S8)\r
491: BaseType_t xReturn;\r
492: Queue_t * const pxMutex = ( Queue_t * ) xMutex;\r
-BFD06ADE 0028FC5E LW V0, 40(S8)
-BFD06AE2 0014F85E SW V0, 20(S8)
+BFD06ADE 0028FC5E LW V0, 40(S8)\r
+BFD06AE2 0014F85E SW V0, 20(S8)\r
493: \r
494: configASSERT( pxMutex );\r
-BFD06AE6 0014FC5E LW V0, 20(S8)
-BFD06AEA 000940A2 BNEZC V0, 0xBFD06B00
-BFD06AEE BFD141A2 LUI V0, 0xBFD1
-BFD06AF0 3082BFD1 LDC1 F30, 12418(S1)
-BFD06AF2 9E3C3082 ADDIU A0, V0, -25028
-BFD06AF4 30A09E3C LWC1 F17, 12448(GP)
-BFD06AF6 01EE30A0 ADDIU A1, ZERO, 494
-BFD06AFA 4B7E77E8 JALS vAssertCalled
-BFD06AFC 4B7E LW K1, 120(SP)
-BFD06AFE 0C00 NOP
+BFD06AE6 0014FC5E LW V0, 20(S8)\r
+BFD06AEA 000940A2 BNEZC V0, 0xBFD06B00\r
+BFD06AEE BFD141A2 LUI V0, 0xBFD1\r
+BFD06AF0 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD06AF2 9E3C3082 ADDIU A0, V0, -25028\r
+BFD06AF4 30A09E3C LWC1 F17, 12448(GP)\r
+BFD06AF6 01EE30A0 ADDIU A1, ZERO, 494\r
+BFD06AFA 4B7E77E8 JALS vAssertCalled\r
+BFD06AFC 4B7E LW K1, 120(SP)\r
+BFD06AFE 0C00 NOP\r
495: \r
496: /* If this is the task that holds the mutex then pxMutexHolder will not\r
497: change outside of this task. If this task does not hold the mutex then\r
500: pxMutexHolder is accessed simultaneously by another task. Therefore no\r
501: mutual exclusion is required to test the pxMutexHolder variable. */\r
502: if( pxMutex->pxMutexHolder == ( void * ) xTaskGetCurrentTaskHandle() ) /*lint !e961 Not a redundant cast as TaskHandle_t is a typedef. */\r
-BFD06B00 0014FC5E LW V0, 20(S8)
-BFD06B04 6821 LW S0, 4(V0)
-BFD06B06 4F0277E8 JALS xTaskGetCurrentTaskHandle
-BFD06B08 4F02 ADDIU T8, T8, 1
-BFD06B0A 0C00 NOP
-BFD06B0C 001AB450 BNE S0, V0, 0xBFD06B44
-BFD06B0E 0C00001A SLL ZERO, K0, 1
-BFD06B10 0C00 NOP
+BFD06B00 0014FC5E LW V0, 20(S8)\r
+BFD06B04 6821 LW S0, 4(V0)\r
+BFD06B06 4F0277E8 JALS xTaskGetCurrentTaskHandle\r
+BFD06B08 4F02 ADDIU T8, T8, 1\r
+BFD06B0A 0C00 NOP\r
+BFD06B0C 001AB450 BNE S0, V0, 0xBFD06B44\r
+BFD06B0E 0C00001A SLL ZERO, K0, 1\r
+BFD06B10 0C00 NOP\r
503: {\r
504: traceGIVE_MUTEX_RECURSIVE( pxMutex );\r
505: \r
509: there can only be one, no mutual exclusion is required to modify the\r
510: uxRecursiveCallCount member. */\r
511: ( pxMutex->u.uxRecursiveCallCount )--;\r
-BFD06B12 0014FC5E LW V0, 20(S8)
-BFD06B16 6923 LW V0, 12(V0)
-BFD06B18 6DAE ADDIU V1, V0, -1
-BFD06B1A 0014FC5E LW V0, 20(S8)
-BFD06B1E E9A3 SW V1, 12(V0)
+BFD06B12 0014FC5E LW V0, 20(S8)\r
+BFD06B16 6923 LW V0, 12(V0)\r
+BFD06B18 6DAE ADDIU V1, V0, -1\r
+BFD06B1A 0014FC5E LW V0, 20(S8)\r
+BFD06B1E E9A3 SW V1, 12(V0)\r
512: \r
513: /* Have we unwound the call count? */\r
514: if( pxMutex->u.uxRecursiveCallCount == ( UBaseType_t ) 0 )\r
-BFD06B20 0014FC5E LW V0, 20(S8)
-BFD06B24 6923 LW V0, 12(V0)
-BFD06B26 000840A2 BNEZC V0, 0xBFD06B3A
+BFD06B20 0014FC5E LW V0, 20(S8)\r
+BFD06B24 6923 LW V0, 12(V0)\r
+BFD06B26 000840A2 BNEZC V0, 0xBFD06B3A\r
515: {\r
516: /* Return the mutex. This will automatically unblock any other\r
517: task that might be waiting to access the mutex. */\r
518: ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );\r
-BFD06B2A 0014FC9E LW A0, 20(S8)
-BFD06B2E 0CA0 MOVE A1, ZERO
-BFD06B30 0CC0 MOVE A2, ZERO
-BFD06B32 0CE0 MOVE A3, ZERO
-BFD06B34 06A277E8 JALS xQueueGenericSend
-BFD06B36 06A2 ADDU A1, S1, V0
-BFD06B38 0C00 NOP
+BFD06B2A 0014FC9E LW A0, 20(S8)\r
+BFD06B2E 0CA0 MOVE A1, ZERO\r
+BFD06B30 0CC0 MOVE A2, ZERO\r
+BFD06B32 0CE0 MOVE A3, ZERO\r
+BFD06B34 06A277E8 JALS xQueueGenericSend\r
+BFD06B36 06A2 ADDU A1, S1, V0\r
+BFD06B38 0C00 NOP\r
519: }\r
520: else\r
521: {\r
523: }\r
524: \r
525: xReturn = pdPASS;\r
-BFD06B3A ED01 LI V0, 1
-BFD06B3C 0010F85E SW V0, 16(S8)
-BFD06B40 CC03 B 0xBFD06B48
-BFD06B42 0C00 NOP
+BFD06B3A ED01 LI V0, 1\r
+BFD06B3C 0010F85E SW V0, 16(S8)\r
+BFD06B40 CC03 B 0xBFD06B48\r
+BFD06B42 0C00 NOP\r
526: }\r
527: else\r
528: {\r
529: /* The mutex cannot be given because the calling task is not the\r
530: holder. */\r
531: xReturn = pdFAIL;\r
-BFD06B44 0010F81E SW ZERO, 16(S8)
+BFD06B44 0010F81E SW ZERO, 16(S8)\r
532: \r
533: traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );\r
534: }\r
535: \r
536: return xReturn;\r
-BFD06B48 0010FC5E LW V0, 16(S8)
+BFD06B48 0010FC5E LW V0, 16(S8)\r
537: }\r
-BFD06B4C 0FBE MOVE SP, S8
-BFD06B4E 4BE9 LW RA, 36(SP)
-BFD06B50 4BC8 LW S8, 32(SP)
-BFD06B52 4A07 LW S0, 28(SP)
-BFD06B54 4C15 ADDIU SP, SP, 40
-BFD06B56 459F JR16 RA
-BFD06B58 0C00 NOP
+BFD06B4C 0FBE MOVE SP, S8\r
+BFD06B4E 4BE9 LW RA, 36(SP)\r
+BFD06B50 4BC8 LW S8, 32(SP)\r
+BFD06B52 4A07 LW S0, 28(SP)\r
+BFD06B54 4C15 ADDIU SP, SP, 40\r
+BFD06B56 459F JR16 RA\r
+BFD06B58 0C00 NOP\r
538: \r
539: #endif /* configUSE_RECURSIVE_MUTEXES */\r
540: /*-----------------------------------------------------------*/\r
543: \r
544: BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait )\r
545: {\r
-BFD063CC 4FED ADDIU SP, SP, -40
-BFD063CE CBE9 SW RA, 36(SP)
-BFD063D0 CBC8 SW S8, 32(SP)
-BFD063D2 CA07 SW S0, 28(SP)
-BFD063D4 0FDD MOVE S8, SP
-BFD063D6 0028F89E SW A0, 40(S8)
-BFD063DA 002CF8BE SW A1, 44(S8)
+BFD063CC 4FED ADDIU SP, SP, -40\r
+BFD063CE CBE9 SW RA, 36(SP)\r
+BFD063D0 CBC8 SW S8, 32(SP)\r
+BFD063D2 CA07 SW S0, 28(SP)\r
+BFD063D4 0FDD MOVE S8, SP\r
+BFD063D6 0028F89E SW A0, 40(S8)\r
+BFD063DA 002CF8BE SW A1, 44(S8)\r
546: BaseType_t xReturn;\r
547: Queue_t * const pxMutex = ( Queue_t * ) xMutex;\r
-BFD063DE 0028FC5E LW V0, 40(S8)
-BFD063E2 0014F85E SW V0, 20(S8)
+BFD063DE 0028FC5E LW V0, 40(S8)\r
+BFD063E2 0014F85E SW V0, 20(S8)\r
548: \r
549: configASSERT( pxMutex );\r
-BFD063E6 0014FC5E LW V0, 20(S8)
-BFD063EA 000940A2 BNEZC V0, 0xBFD06400
-BFD063EE BFD141A2 LUI V0, 0xBFD1
-BFD063F0 3082BFD1 LDC1 F30, 12418(S1)
-BFD063F2 9E3C3082 ADDIU A0, V0, -25028
-BFD063F4 30A09E3C LWC1 F17, 12448(GP)
-BFD063F6 022530A0 ADDIU A1, ZERO, 549
-BFD063FA 4B7E77E8 JALS vAssertCalled
-BFD063FC 4B7E LW K1, 120(SP)
-BFD063FE 0C00 NOP
+BFD063E6 0014FC5E LW V0, 20(S8)\r
+BFD063EA 000940A2 BNEZC V0, 0xBFD06400\r
+BFD063EE BFD141A2 LUI V0, 0xBFD1\r
+BFD063F0 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD063F2 9E3C3082 ADDIU A0, V0, -25028\r
+BFD063F4 30A09E3C LWC1 F17, 12448(GP)\r
+BFD063F6 022530A0 ADDIU A1, ZERO, 549\r
+BFD063FA 4B7E77E8 JALS vAssertCalled\r
+BFD063FC 4B7E LW K1, 120(SP)\r
+BFD063FE 0C00 NOP\r
550: \r
551: /* Comments regarding mutual exclusion as per those within\r
552: xQueueGiveMutexRecursive(). */\r
554: traceTAKE_MUTEX_RECURSIVE( pxMutex );\r
555: \r
556: if( pxMutex->pxMutexHolder == ( void * ) xTaskGetCurrentTaskHandle() ) /*lint !e961 Cast is not redundant as TaskHandle_t is a typedef. */\r
-BFD06400 0014FC5E LW V0, 20(S8)
-BFD06404 6821 LW S0, 4(V0)
-BFD06406 4F0277E8 JALS xTaskGetCurrentTaskHandle
-BFD06408 4F02 ADDIU T8, T8, 1
-BFD0640A 0C00 NOP
-BFD0640C 000DB450 BNE S0, V0, 0xBFD0642A
-BFD0640E 0C00000D SLL ZERO, T5, 1
-BFD06410 0C00 NOP
+BFD06400 0014FC5E LW V0, 20(S8)\r
+BFD06404 6821 LW S0, 4(V0)\r
+BFD06406 4F0277E8 JALS xTaskGetCurrentTaskHandle\r
+BFD06408 4F02 ADDIU T8, T8, 1\r
+BFD0640A 0C00 NOP\r
+BFD0640C 000DB450 BNE S0, V0, 0xBFD0642A\r
+BFD0640E 0C00000D SLL ZERO, T5, 1\r
+BFD06410 0C00 NOP\r
557: {\r
558: ( pxMutex->u.uxRecursiveCallCount )++;\r
-BFD06412 0014FC5E LW V0, 20(S8)
-BFD06416 6923 LW V0, 12(V0)
-BFD06418 6DA0 ADDIU V1, V0, 1
-BFD0641A 0014FC5E LW V0, 20(S8)
-BFD0641E E9A3 SW V1, 12(V0)
+BFD06412 0014FC5E LW V0, 20(S8)\r
+BFD06416 6923 LW V0, 12(V0)\r
+BFD06418 6DA0 ADDIU V1, V0, 1\r
+BFD0641A 0014FC5E LW V0, 20(S8)\r
+BFD0641E E9A3 SW V1, 12(V0)\r
559: xReturn = pdPASS;\r
-BFD06420 ED01 LI V0, 1
-BFD06422 0010F85E SW V0, 16(S8)
-BFD06426 CC19 B 0xBFD0645A
-BFD06428 0C00 NOP
+BFD06420 ED01 LI V0, 1\r
+BFD06422 0010F85E SW V0, 16(S8)\r
+BFD06426 CC19 B 0xBFD0645A\r
+BFD06428 0C00 NOP\r
560: }\r
561: else\r
562: {\r
563: xReturn = xQueueGenericReceive( pxMutex, NULL, xTicksToWait, pdFALSE );\r
-BFD0642A 0014FC9E LW A0, 20(S8)
-BFD0642E 0CA0 MOVE A1, ZERO
-BFD06430 002CFCDE LW A2, 44(S8)
-BFD06434 0CE0 MOVE A3, ZERO
-BFD06436 081E77E8 JALS xQueueGenericReceive
-BFD06438 081E LBU S0, 14(S1)
-BFD0643A 0C00 NOP
-BFD0643C 0010F85E SW V0, 16(S8)
+BFD0642A 0014FC9E LW A0, 20(S8)\r
+BFD0642E 0CA0 MOVE A1, ZERO\r
+BFD06430 002CFCDE LW A2, 44(S8)\r
+BFD06434 0CE0 MOVE A3, ZERO\r
+BFD06436 081E77E8 JALS xQueueGenericReceive\r
+BFD06438 081E LBU S0, 14(S1)\r
+BFD0643A 0C00 NOP\r
+BFD0643C 0010F85E SW V0, 16(S8)\r
564: \r
565: /* pdPASS will only be returned if the mutex was successfully\r
566: obtained. The calling task may have entered the Blocked state\r
567: before reaching here. */\r
568: if( xReturn == pdPASS )\r
-BFD06440 0010FC7E LW V1, 16(S8)
-BFD06444 ED01 LI V0, 1
-BFD06446 0008B443 BNE V1, V0, 0xBFD0645A
-BFD06448 0C000008 SLL ZERO, T0, 1
-BFD0644A 0C00 NOP
+BFD06440 0010FC7E LW V1, 16(S8)\r
+BFD06444 ED01 LI V0, 1\r
+BFD06446 0008B443 BNE V1, V0, 0xBFD0645A\r
+BFD06448 0C000008 SLL ZERO, T0, 1\r
+BFD0644A 0C00 NOP\r
569: {\r
570: ( pxMutex->u.uxRecursiveCallCount )++;\r
-BFD0644C 0014FC5E LW V0, 20(S8)
-BFD06450 6923 LW V0, 12(V0)
-BFD06452 6DA0 ADDIU V1, V0, 1
-BFD06454 0014FC5E LW V0, 20(S8)
-BFD06458 E9A3 SW V1, 12(V0)
+BFD0644C 0014FC5E LW V0, 20(S8)\r
+BFD06450 6923 LW V0, 12(V0)\r
+BFD06452 6DA0 ADDIU V1, V0, 1\r
+BFD06454 0014FC5E LW V0, 20(S8)\r
+BFD06458 E9A3 SW V1, 12(V0)\r
571: }\r
572: else\r
573: {\r
576: }\r
577: \r
578: return xReturn;\r
-BFD0645A 0010FC5E LW V0, 16(S8)
+BFD0645A 0010FC5E LW V0, 16(S8)\r
579: }\r
-BFD0645E 0FBE MOVE SP, S8
-BFD06460 4BE9 LW RA, 36(SP)
-BFD06462 4BC8 LW S8, 32(SP)
-BFD06464 4A07 LW S0, 28(SP)
-BFD06466 4C15 ADDIU SP, SP, 40
-BFD06468 459F JR16 RA
-BFD0646A 0C00 NOP
+BFD0645E 0FBE MOVE SP, S8\r
+BFD06460 4BE9 LW RA, 36(SP)\r
+BFD06462 4BC8 LW S8, 32(SP)\r
+BFD06464 4A07 LW S0, 28(SP)\r
+BFD06466 4C15 ADDIU SP, SP, 40\r
+BFD06468 459F JR16 RA\r
+BFD0646A 0C00 NOP\r
580: \r
581: #endif /* configUSE_RECURSIVE_MUTEXES */\r
582: /*-----------------------------------------------------------*/\r
585: \r
586: QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount )\r
587: {\r
-BFD0650C 4FF1 ADDIU SP, SP, -32
-BFD0650E CBE7 SW RA, 28(SP)
-BFD06510 CBC6 SW S8, 24(SP)
-BFD06512 0FDD MOVE S8, SP
-BFD06514 0020F89E SW A0, 32(S8)
-BFD06518 0024F8BE SW A1, 36(S8)
+BFD0650C 4FF1 ADDIU SP, SP, -32\r
+BFD0650E CBE7 SW RA, 28(SP)\r
+BFD06510 CBC6 SW S8, 24(SP)\r
+BFD06512 0FDD MOVE S8, SP\r
+BFD06514 0020F89E SW A0, 32(S8)\r
+BFD06518 0024F8BE SW A1, 36(S8)\r
588: QueueHandle_t xHandle;\r
589: \r
590: configASSERT( uxMaxCount != 0 );\r
-BFD0651C 0020FC5E LW V0, 32(S8)
-BFD06520 000940A2 BNEZC V0, 0xBFD06536
-BFD06524 BFD141A2 LUI V0, 0xBFD1
-BFD06526 3082BFD1 LDC1 F30, 12418(S1)
-BFD06528 9E3C3082 ADDIU A0, V0, -25028
-BFD0652A 30A09E3C LWC1 F17, 12448(GP)
-BFD0652C 024E30A0 ADDIU A1, ZERO, 590
-BFD06530 4B7E77E8 JALS vAssertCalled
-BFD06532 4B7E LW K1, 120(SP)
-BFD06534 0C00 NOP
+BFD0651C 0020FC5E LW V0, 32(S8)\r
+BFD06520 000940A2 BNEZC V0, 0xBFD06536\r
+BFD06524 BFD141A2 LUI V0, 0xBFD1\r
+BFD06526 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD06528 9E3C3082 ADDIU A0, V0, -25028\r
+BFD0652A 30A09E3C LWC1 F17, 12448(GP)\r
+BFD0652C 024E30A0 ADDIU A1, ZERO, 590\r
+BFD06530 4B7E77E8 JALS vAssertCalled\r
+BFD06532 4B7E LW K1, 120(SP)\r
+BFD06534 0C00 NOP\r
591: configASSERT( uxInitialCount <= uxMaxCount );\r
-BFD06536 0024FC7E LW V1, 36(S8)
-BFD0653A 0020FC5E LW V0, 32(S8)
-BFD0653E 13900062 SLTU V0, V0, V1
-BFD06540 40E21390 ADDI GP, S0, 16610
-BFD06542 000940E2 BEQZC V0, 0xBFD06558
-BFD06546 BFD141A2 LUI V0, 0xBFD1
-BFD06548 3082BFD1 LDC1 F30, 12418(S1)
-BFD0654A 9E3C3082 ADDIU A0, V0, -25028
-BFD0654C 30A09E3C LWC1 F17, 12448(GP)
-BFD0654E 024F30A0 ADDIU A1, ZERO, 591
-BFD06552 4B7E77E8 JALS vAssertCalled
-BFD06554 4B7E LW K1, 120(SP)
-BFD06556 0C00 NOP
+BFD06536 0024FC7E LW V1, 36(S8)\r
+BFD0653A 0020FC5E LW V0, 32(S8)\r
+BFD0653E 13900062 SLTU V0, V0, V1\r
+BFD06540 40E21390 ADDI GP, S0, 16610\r
+BFD06542 000940E2 BEQZC V0, 0xBFD06558\r
+BFD06546 BFD141A2 LUI V0, 0xBFD1\r
+BFD06548 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD0654A 9E3C3082 ADDIU A0, V0, -25028\r
+BFD0654C 30A09E3C LWC1 F17, 12448(GP)\r
+BFD0654E 024F30A0 ADDIU A1, ZERO, 591\r
+BFD06552 4B7E77E8 JALS vAssertCalled\r
+BFD06554 4B7E LW K1, 120(SP)\r
+BFD06556 0C00 NOP\r
592: \r
593: xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );\r
-BFD06558 0020FC9E LW A0, 32(S8)
-BFD0655C 0CA0 MOVE A1, ZERO
-BFD0655E EF02 LI A2, 2
-BFD06560 1EFA77E8 JALS xQueueGenericCreate
-BFD06562 0C001EFA LB S7, 3072(K0)
-BFD06564 0C00 NOP
-BFD06566 0010F85E SW V0, 16(S8)
+BFD06558 0020FC9E LW A0, 32(S8)\r
+BFD0655C 0CA0 MOVE A1, ZERO\r
+BFD0655E EF02 LI A2, 2\r
+BFD06560 1EFA77E8 JALS xQueueGenericCreate\r
+BFD06562 0C001EFA LB S7, 3072(K0)\r
+BFD06564 0C00 NOP\r
+BFD06566 0010F85E SW V0, 16(S8)\r
594: \r
595: if( xHandle != NULL )\r
-BFD0656A 0010FC5E LW V0, 16(S8)
-BFD0656E 000540E2 BEQZC V0, 0xBFD0657C
+BFD0656A 0010FC5E LW V0, 16(S8)\r
+BFD0656E 000540E2 BEQZC V0, 0xBFD0657C\r
596: {\r
597: ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;\r
-BFD06572 0010FC5E LW V0, 16(S8)
-BFD06576 0024FC7E LW V1, 36(S8)
-BFD0657A E9AE SW V1, 56(V0)
+BFD06572 0010FC5E LW V0, 16(S8)\r
+BFD06576 0024FC7E LW V1, 36(S8)\r
+BFD0657A E9AE SW V1, 56(V0)\r
598: \r
599: traceCREATE_COUNTING_SEMAPHORE();\r
600: }\r
604: }\r
605: \r
606: configASSERT( xHandle );\r
-BFD0657C 0010FC5E LW V0, 16(S8)
-BFD06580 000940A2 BNEZC V0, 0xBFD06596
-BFD06584 BFD141A2 LUI V0, 0xBFD1
-BFD06586 3082BFD1 LDC1 F30, 12418(S1)
-BFD06588 9E3C3082 ADDIU A0, V0, -25028
-BFD0658A 30A09E3C LWC1 F17, 12448(GP)
-BFD0658C 025E30A0 ADDIU A1, ZERO, 606
-BFD06590 4B7E77E8 JALS vAssertCalled
-BFD06592 4B7E LW K1, 120(SP)
-BFD06594 0C00 NOP
+BFD0657C 0010FC5E LW V0, 16(S8)\r
+BFD06580 000940A2 BNEZC V0, 0xBFD06596\r
+BFD06584 BFD141A2 LUI V0, 0xBFD1\r
+BFD06586 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD06588 9E3C3082 ADDIU A0, V0, -25028\r
+BFD0658A 30A09E3C LWC1 F17, 12448(GP)\r
+BFD0658C 025E30A0 ADDIU A1, ZERO, 606\r
+BFD06590 4B7E77E8 JALS vAssertCalled\r
+BFD06592 4B7E LW K1, 120(SP)\r
+BFD06594 0C00 NOP\r
607: return xHandle;\r
-BFD06596 0010FC5E LW V0, 16(S8)
+BFD06596 0010FC5E LW V0, 16(S8)\r
608: }\r
-BFD0659A 0FBE MOVE SP, S8
-BFD0659C 4BE7 LW RA, 28(SP)
-BFD0659E 4BC6 LW S8, 24(SP)
-BFD065A0 4C11 ADDIU SP, SP, 32
-BFD065A2 459F JR16 RA
-BFD065A4 0C00 NOP
+BFD0659A 0FBE MOVE SP, S8\r
+BFD0659C 4BE7 LW RA, 28(SP)\r
+BFD0659E 4BC6 LW S8, 24(SP)\r
+BFD065A0 4C11 ADDIU SP, SP, 32\r
+BFD065A2 459F JR16 RA\r
+BFD065A4 0C00 NOP\r
609: \r
610: #endif /* configUSE_COUNTING_SEMAPHORES */\r
611: /*-----------------------------------------------------------*/\r
612: \r
613: BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )\r
614: {\r
-BFD00D44 4FE1 ADDIU SP, SP, -64
-BFD00D46 CBEF SW RA, 60(SP)
-BFD00D48 CBCE SW S8, 56(SP)
-BFD00D4A 0FDD MOVE S8, SP
-BFD00D4C 0040F89E SW A0, 64(S8)
-BFD00D50 0044F8BE SW A1, 68(S8)
-BFD00D54 0048F8DE SW A2, 72(S8)
-BFD00D58 004CF8FE SW A3, 76(S8)
+BFD00D44 4FE1 ADDIU SP, SP, -64\r
+BFD00D46 CBEF SW RA, 60(SP)\r
+BFD00D48 CBCE SW S8, 56(SP)\r
+BFD00D4A 0FDD MOVE S8, SP\r
+BFD00D4C 0040F89E SW A0, 64(S8)\r
+BFD00D50 0044F8BE SW A1, 68(S8)\r
+BFD00D54 0048F8DE SW A2, 72(S8)\r
+BFD00D58 004CF8FE SW A3, 76(S8)\r
615: BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;\r
-BFD00D5C 0010F81E SW ZERO, 16(S8)
+BFD00D5C 0010F81E SW ZERO, 16(S8)\r
616: TimeOut_t xTimeOut;\r
617: Queue_t * const pxQueue = ( Queue_t * ) xQueue;\r
-BFD00D60 0040FC5E LW V0, 64(S8)
-BFD00D64 0014F85E SW V0, 20(S8)
+BFD00D60 0040FC5E LW V0, 64(S8)\r
+BFD00D64 0014F85E SW V0, 20(S8)\r
618: \r
619: configASSERT( pxQueue );\r
-BFD00D68 0014FC5E LW V0, 20(S8)
-BFD00D6C 000940A2 BNEZC V0, 0xBFD00D82
-BFD00D70 BFD141A2 LUI V0, 0xBFD1
-BFD00D72 3082BFD1 LDC1 F30, 12418(S1)
-BFD00D74 9E3C3082 ADDIU A0, V0, -25028
-BFD00D76 30A09E3C LWC1 F17, 12448(GP)
-BFD00D78 026B30A0 ADDIU A1, ZERO, 619
-BFD00D7C 4B7E77E8 JALS vAssertCalled
-BFD00D7E 4B7E LW K1, 120(SP)
-BFD00D80 0C00 NOP
+BFD00D68 0014FC5E LW V0, 20(S8)\r
+BFD00D6C 000940A2 BNEZC V0, 0xBFD00D82\r
+BFD00D70 BFD141A2 LUI V0, 0xBFD1\r
+BFD00D72 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD00D74 9E3C3082 ADDIU A0, V0, -25028\r
+BFD00D76 30A09E3C LWC1 F17, 12448(GP)\r
+BFD00D78 026B30A0 ADDIU A1, ZERO, 619\r
+BFD00D7C 4B7E77E8 JALS vAssertCalled\r
+BFD00D7E 4B7E LW K1, 120(SP)\r
+BFD00D80 0C00 NOP\r
620: configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\r
-BFD00D82 0044FC5E LW V0, 68(S8)
-BFD00D86 000640A2 BNEZC V0, 0xBFD00D96
-BFD00D8A 0014FC5E LW V0, 20(S8)
-BFD00D8E 0040FC42 LW V0, 64(V0)
-BFD00D92 000340A2 BNEZC V0, 0xBFD00D9C
-BFD00D96 ED01 LI V0, 1
-BFD00D98 CC02 B 0xBFD00D9E
-BFD00D9A 0C00 NOP
-BFD00D9C 0C40 MOVE V0, ZERO
-BFD00D9E 000940A2 BNEZC V0, 0xBFD00DB4
-BFD00DA2 BFD141A2 LUI V0, 0xBFD1
-BFD00DA4 3082BFD1 LDC1 F30, 12418(S1)
-BFD00DA6 9E3C3082 ADDIU A0, V0, -25028
-BFD00DA8 30A09E3C LWC1 F17, 12448(GP)
-BFD00DAA 026C30A0 ADDIU A1, ZERO, 620
-BFD00DAE 4B7E77E8 JALS vAssertCalled
-BFD00DB0 4B7E LW K1, 120(SP)
-BFD00DB2 0C00 NOP
+BFD00D82 0044FC5E LW V0, 68(S8)\r
+BFD00D86 000640A2 BNEZC V0, 0xBFD00D96\r
+BFD00D8A 0014FC5E LW V0, 20(S8)\r
+BFD00D8E 0040FC42 LW V0, 64(V0)\r
+BFD00D92 000340A2 BNEZC V0, 0xBFD00D9C\r
+BFD00D96 ED01 LI V0, 1\r
+BFD00D98 CC02 B 0xBFD00D9E\r
+BFD00D9A 0C00 NOP\r
+BFD00D9C 0C40 MOVE V0, ZERO\r
+BFD00D9E 000940A2 BNEZC V0, 0xBFD00DB4\r
+BFD00DA2 BFD141A2 LUI V0, 0xBFD1\r
+BFD00DA4 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD00DA6 9E3C3082 ADDIU A0, V0, -25028\r
+BFD00DA8 30A09E3C LWC1 F17, 12448(GP)\r
+BFD00DAA 026C30A0 ADDIU A1, ZERO, 620\r
+BFD00DAE 4B7E77E8 JALS vAssertCalled\r
+BFD00DB0 4B7E LW K1, 120(SP)\r
+BFD00DB2 0C00 NOP\r
621: configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );\r
-BFD00DB4 004CFC7E LW V1, 76(S8)
-BFD00DB8 ED02 LI V0, 2
-BFD00DBA 0008B443 BNE V1, V0, 0xBFD00DCE
-BFD00DBC 0C000008 SLL ZERO, T0, 1
-BFD00DBE 0C00 NOP
-BFD00DC0 0014FC5E LW V0, 20(S8)
-BFD00DC4 69AF LW V1, 60(V0)
-BFD00DC6 ED01 LI V0, 1
-BFD00DC8 0004B443 BNE V1, V0, 0xBFD00DD4
-BFD00DCA 0C000004 SLL ZERO, A0, 1
-BFD00DCC 0C00 NOP
-BFD00DCE ED01 LI V0, 1
-BFD00DD0 CC02 B 0xBFD00DD6
-BFD00DD2 0C00 NOP
-BFD00DD4 0C40 MOVE V0, ZERO
-BFD00DD6 000940A2 BNEZC V0, 0xBFD00DEC
-BFD00DDA BFD141A2 LUI V0, 0xBFD1
-BFD00DDC 3082BFD1 LDC1 F30, 12418(S1)
-BFD00DDE 9E3C3082 ADDIU A0, V0, -25028
-BFD00DE0 30A09E3C LWC1 F17, 12448(GP)
-BFD00DE2 026D30A0 ADDIU A1, ZERO, 621
-BFD00DE6 4B7E77E8 JALS vAssertCalled
-BFD00DE8 4B7E LW K1, 120(SP)
-BFD00DEA 0C00 NOP
+BFD00DB4 004CFC7E LW V1, 76(S8)\r
+BFD00DB8 ED02 LI V0, 2\r
+BFD00DBA 0008B443 BNE V1, V0, 0xBFD00DCE\r
+BFD00DBC 0C000008 SLL ZERO, T0, 1\r
+BFD00DBE 0C00 NOP\r
+BFD00DC0 0014FC5E LW V0, 20(S8)\r
+BFD00DC4 69AF LW V1, 60(V0)\r
+BFD00DC6 ED01 LI V0, 1\r
+BFD00DC8 0004B443 BNE V1, V0, 0xBFD00DD4\r
+BFD00DCA 0C000004 SLL ZERO, A0, 1\r
+BFD00DCC 0C00 NOP\r
+BFD00DCE ED01 LI V0, 1\r
+BFD00DD0 CC02 B 0xBFD00DD6\r
+BFD00DD2 0C00 NOP\r
+BFD00DD4 0C40 MOVE V0, ZERO\r
+BFD00DD6 000940A2 BNEZC V0, 0xBFD00DEC\r
+BFD00DDA BFD141A2 LUI V0, 0xBFD1\r
+BFD00DDC 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD00DDE 9E3C3082 ADDIU A0, V0, -25028\r
+BFD00DE0 30A09E3C LWC1 F17, 12448(GP)\r
+BFD00DE2 026D30A0 ADDIU A1, ZERO, 621\r
+BFD00DE6 4B7E77E8 JALS vAssertCalled\r
+BFD00DE8 4B7E LW K1, 120(SP)\r
+BFD00DEA 0C00 NOP\r
622: #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\r
623: {\r
624: configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\r
-BFD00DEC 4A8E77E8 JALS xTaskGetSchedulerState
-BFD00DEE 4A8E LW S4, 56(SP)
-BFD00DF0 0C00 NOP
-BFD00DF2 000440A2 BNEZC V0, 0xBFD00DFE
-BFD00DF6 0048FC5E LW V0, 72(S8)
-BFD00DFA 000340A2 BNEZC V0, 0xBFD00E04
-BFD00DFE ED01 LI V0, 1
-BFD00E00 CC02 B 0xBFD00E06
-BFD00E02 0C00 NOP
-BFD00E04 0C40 MOVE V0, ZERO
-BFD00E06 000C40A2 BNEZC V0, 0xBFD00E22
-BFD00E0A BFD141A2 LUI V0, 0xBFD1
-BFD00E0C 3082BFD1 LDC1 F30, 12418(S1)
-BFD00E0E 9E3C3082 ADDIU A0, V0, -25028
-BFD00E10 30A09E3C LWC1 F17, 12448(GP)
-BFD00E12 027030A0 ADDIU A1, ZERO, 624
-BFD00E16 4B7E77E8 JALS vAssertCalled
-BFD00E18 4B7E LW K1, 120(SP)
-BFD00E1A 0C00 NOP
-BFD00E1C CC02 B 0xBFD00E22
-BFD00E1E 0C00 NOP
+BFD00DEC 4A8E77E8 JALS xTaskGetSchedulerState\r
+BFD00DEE 4A8E LW S4, 56(SP)\r
+BFD00DF0 0C00 NOP\r
+BFD00DF2 000440A2 BNEZC V0, 0xBFD00DFE\r
+BFD00DF6 0048FC5E LW V0, 72(S8)\r
+BFD00DFA 000340A2 BNEZC V0, 0xBFD00E04\r
+BFD00DFE ED01 LI V0, 1\r
+BFD00E00 CC02 B 0xBFD00E06\r
+BFD00E02 0C00 NOP\r
+BFD00E04 0C40 MOVE V0, ZERO\r
+BFD00E06 000C40A2 BNEZC V0, 0xBFD00E22\r
+BFD00E0A BFD141A2 LUI V0, 0xBFD1\r
+BFD00E0C 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD00E0E 9E3C3082 ADDIU A0, V0, -25028\r
+BFD00E10 30A09E3C LWC1 F17, 12448(GP)\r
+BFD00E12 027030A0 ADDIU A1, ZERO, 624\r
+BFD00E16 4B7E77E8 JALS vAssertCalled\r
+BFD00E18 4B7E LW K1, 120(SP)\r
+BFD00E1A 0C00 NOP\r
+BFD00E1C CC02 B 0xBFD00E22\r
+BFD00E1E 0C00 NOP\r
625: }\r
626: #endif\r
627: \r
632: for( ;; )\r
633: {\r
634: taskENTER_CRITICAL();\r
-BFD00E22 33B877E8 JALS vTaskEnterCritical
-BFD00E24 0C0033B8 ADDIU SP, T8, 3072
-BFD00E26 0C00 NOP
+BFD00E22 33B877E8 JALS vTaskEnterCritical\r
+BFD00E24 0C0033B8 ADDIU SP, T8, 3072\r
+BFD00E26 0C00 NOP\r
635: {\r
636: /* Is there room on the queue now? The running task must be the\r
637: highest priority task wanting to access the queue. If the head item\r
638: in the queue is to be overwritten then it does not matter if the\r
639: queue is full. */\r
640: if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )\r
-BFD00E28 0014FC5E LW V0, 20(S8)
-BFD00E2C 69AE LW V1, 56(V0)
-BFD00E2E 0014FC5E LW V0, 20(S8)
-BFD00E32 692F LW V0, 60(V0)
-BFD00E34 13900043 SLTU V0, V1, V0
-BFD00E36 40A21390 ADDI GP, S0, 16546
-BFD00E38 000640A2 BNEZC V0, 0xBFD00E48
-BFD00E3C 004CFC7E LW V1, 76(S8)
-BFD00E40 ED02 LI V0, 2
-BFD00E42 006EB443 BNE V1, V0, 0xBFD00F22
-BFD00E44 0C00006E SLL V1, T6, 1
-BFD00E46 0C00 NOP
+BFD00E28 0014FC5E LW V0, 20(S8)\r
+BFD00E2C 69AE LW V1, 56(V0)\r
+BFD00E2E 0014FC5E LW V0, 20(S8)\r
+BFD00E32 692F LW V0, 60(V0)\r
+BFD00E34 13900043 SLTU V0, V1, V0\r
+BFD00E36 40A21390 ADDI GP, S0, 16546\r
+BFD00E38 000640A2 BNEZC V0, 0xBFD00E48\r
+BFD00E3C 004CFC7E LW V1, 76(S8)\r
+BFD00E40 ED02 LI V0, 2\r
+BFD00E42 006EB443 BNE V1, V0, 0xBFD00F22\r
+BFD00E44 0C00006E SLL V1, T6, 1\r
+BFD00E46 0C00 NOP\r
641: {\r
642: traceQUEUE_SEND( pxQueue );\r
643: xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );\r
-BFD00E48 0014FC9E LW A0, 20(S8)
-BFD00E4C 0044FCBE LW A1, 68(S8)
-BFD00E50 004CFCDE LW A2, 76(S8)
-BFD00E54 14E677E8 JALS prvCopyDataToQueue
-BFD00E56 0C0014E6 LBU A3, 3072(A2)
-BFD00E58 0C00 NOP
-BFD00E5A 001CF85E SW V0, 28(S8)
+BFD00E48 0014FC9E LW A0, 20(S8)\r
+BFD00E4C 0044FCBE LW A1, 68(S8)\r
+BFD00E50 004CFCDE LW A2, 76(S8)\r
+BFD00E54 14E677E8 JALS prvCopyDataToQueue\r
+BFD00E56 0C0014E6 LBU A3, 3072(A2)\r
+BFD00E58 0C00 NOP\r
+BFD00E5A 001CF85E SW V0, 28(S8)\r
644: \r
645: #if ( configUSE_QUEUE_SETS == 1 )\r
646: {\r
647: if( pxQueue->pxQueueSetContainer != NULL )\r
-BFD00E5E 0014FC5E LW V0, 20(S8)
-BFD00E62 004CFC42 LW V0, 76(V0)
-BFD00E66 001E40E2 BEQZC V0, 0xBFD00EA6
+BFD00E5E 0014FC5E LW V0, 20(S8)\r
+BFD00E62 004CFC42 LW V0, 76(V0)\r
+BFD00E66 001E40E2 BEQZC V0, 0xBFD00EA6\r
648: {\r
649: if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) == pdTRUE )\r
-BFD00E6A 0014FC9E LW A0, 20(S8)
-BFD00E6E 004CFCBE LW A1, 76(S8)
-BFD00E72 21D877E8 JALS prvNotifyQueueSetContainer
-BFD00E74 0C0021D8 LWC2 T6, 3072(T8)
-BFD00E76 0C00 NOP
-BFD00E78 0C62 MOVE V1, V0
-BFD00E7A ED01 LI V0, 1
-BFD00E7C 004BB443 BNE V1, V0, 0xBFD00F16
-BFD00E7E 0C00004B SLL V0, T3, 1
-BFD00E80 0C00 NOP
+BFD00E6A 0014FC9E LW A0, 20(S8)\r
+BFD00E6E 004CFCBE LW A1, 76(S8)\r
+BFD00E72 21D877E8 JALS prvNotifyQueueSetContainer\r
+BFD00E74 0C0021D8 LWC2 T6, 3072(T8)\r
+BFD00E76 0C00 NOP\r
+BFD00E78 0C62 MOVE V1, V0\r
+BFD00E7A ED01 LI V0, 1\r
+BFD00E7C 004BB443 BNE V1, V0, 0xBFD00F16\r
+BFD00E7E 0C00004B SLL V0, T3, 1\r
+BFD00E80 0C00 NOP\r
650: {\r
651: /* The queue is a member of a queue set, and posting\r
652: to the queue set caused a higher priority task to\r
653: unblock. A context switch is required. */\r
654: queueYIELD_IF_USING_PREEMPTION();\r
-BFD00E82 4E1677E8 JALS ulPortGetCP0Cause
-BFD00E84 4E16 ADDIU S0, S0, -5
-BFD00E86 0C00 NOP
-BFD00E88 0020F85E SW V0, 32(S8)
-BFD00E8C 0020FC5E LW V0, 32(S8)
-BFD00E90 01005042 ORI V0, V0, 256
-BFD00E94 0020F85E SW V0, 32(S8)
-BFD00E98 0020FC9E LW A0, 32(S8)
-BFD00E9C 4E2677E8 JALS vPortSetCP0Cause
-BFD00E9E 4E26 ADDIU S1, S1, 3
-BFD00EA0 0C00 NOP
-BFD00EA2 CC39 B 0xBFD00F16
-BFD00EA4 0C00 NOP
+BFD00E82 4E1677E8 JALS ulPortGetCP0Cause\r
+BFD00E84 4E16 ADDIU S0, S0, -5\r
+BFD00E86 0C00 NOP\r
+BFD00E88 0020F85E SW V0, 32(S8)\r
+BFD00E8C 0020FC5E LW V0, 32(S8)\r
+BFD00E90 01005042 ORI V0, V0, 256\r
+BFD00E94 0020F85E SW V0, 32(S8)\r
+BFD00E98 0020FC9E LW A0, 32(S8)\r
+BFD00E9C 4E2677E8 JALS vPortSetCP0Cause\r
+BFD00E9E 4E26 ADDIU S1, S1, 3\r
+BFD00EA0 0C00 NOP\r
+BFD00EA2 CC39 B 0xBFD00F16\r
+BFD00EA4 0C00 NOP\r
655: }\r
656: else\r
657: {\r
663: /* If there was a task waiting for data to arrive on the\r
664: queue then unblock it now. */\r
665: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
-BFD00EA6 0014FC5E LW V0, 20(S8)
-BFD00EAA 6929 LW V0, 36(V0)
-BFD00EAC 001F40E2 BEQZC V0, 0xBFD00EEE
+BFD00EA6 0014FC5E LW V0, 20(S8)\r
+BFD00EAA 6929 LW V0, 36(V0)\r
+BFD00EAC 001F40E2 BEQZC V0, 0xBFD00EEE\r
666: {\r
667: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) == pdTRUE )\r
-BFD00EB0 0014FC5E LW V0, 20(S8)
-BFD00EB4 00243042 ADDIU V0, V0, 36
-BFD00EB8 0C82 MOVE A0, V0
-BFD00EBA 22BC77E8 JALS xTaskRemoveFromEventList
-BFD00EBC 0C0022BC LWC2 S5, 3072(GP)
-BFD00EBE 0C00 NOP
-BFD00EC0 0C62 MOVE V1, V0
-BFD00EC2 ED01 LI V0, 1
-BFD00EC4 0027B443 BNE V1, V0, 0xBFD00F16
-BFD00EC6 0C000027 SLL AT, A3, 1
-BFD00EC8 0C00 NOP
+BFD00EB0 0014FC5E LW V0, 20(S8)\r
+BFD00EB4 00243042 ADDIU V0, V0, 36\r
+BFD00EB8 0C82 MOVE A0, V0\r
+BFD00EBA 22BC77E8 JALS xTaskRemoveFromEventList\r
+BFD00EBC 0C0022BC LWC2 S5, 3072(GP)\r
+BFD00EBE 0C00 NOP\r
+BFD00EC0 0C62 MOVE V1, V0\r
+BFD00EC2 ED01 LI V0, 1\r
+BFD00EC4 0027B443 BNE V1, V0, 0xBFD00F16\r
+BFD00EC6 0C000027 SLL AT, A3, 1\r
+BFD00EC8 0C00 NOP\r
668: {\r
669: /* The unblocked task has a priority higher than\r
670: our own so yield immediately. Yes it is ok to\r
671: do this from within the critical section - the\r
672: kernel takes care of that. */\r
673: queueYIELD_IF_USING_PREEMPTION();\r
-BFD00ECA 4E1677E8 JALS ulPortGetCP0Cause
-BFD00ECC 4E16 ADDIU S0, S0, -5
-BFD00ECE 0C00 NOP
-BFD00ED0 0024F85E SW V0, 36(S8)
-BFD00ED4 0024FC5E LW V0, 36(S8)
-BFD00ED8 01005042 ORI V0, V0, 256
-BFD00EDC 0024F85E SW V0, 36(S8)
-BFD00EE0 0024FC9E LW A0, 36(S8)
-BFD00EE4 4E2677E8 JALS vPortSetCP0Cause
-BFD00EE6 4E26 ADDIU S1, S1, 3
-BFD00EE8 0C00 NOP
-BFD00EEA CC15 B 0xBFD00F16
-BFD00EEC 0C00 NOP
+BFD00ECA 4E1677E8 JALS ulPortGetCP0Cause\r
+BFD00ECC 4E16 ADDIU S0, S0, -5\r
+BFD00ECE 0C00 NOP\r
+BFD00ED0 0024F85E SW V0, 36(S8)\r
+BFD00ED4 0024FC5E LW V0, 36(S8)\r
+BFD00ED8 01005042 ORI V0, V0, 256\r
+BFD00EDC 0024F85E SW V0, 36(S8)\r
+BFD00EE0 0024FC9E LW A0, 36(S8)\r
+BFD00EE4 4E2677E8 JALS vPortSetCP0Cause\r
+BFD00EE6 4E26 ADDIU S1, S1, 3\r
+BFD00EE8 0C00 NOP\r
+BFD00EEA CC15 B 0xBFD00F16\r
+BFD00EEC 0C00 NOP\r
674: }\r
675: else\r
676: {\r
678: }\r
679: }\r
680: else if( xYieldRequired != pdFALSE )\r
-BFD00EEE 001CFC5E LW V0, 28(S8)
-BFD00EF2 001040E2 BEQZC V0, 0xBFD00F16
+BFD00EEE 001CFC5E LW V0, 28(S8)\r
+BFD00EF2 001040E2 BEQZC V0, 0xBFD00F16\r
681: {\r
682: /* This path is a special case that will only get\r
683: executed if the task was holding multiple mutexes\r
684: and the mutexes were given back in an order that is\r
685: different to that in which they were taken. */\r
686: queueYIELD_IF_USING_PREEMPTION();\r
-BFD00EF6 4E1677E8 JALS ulPortGetCP0Cause
-BFD00EF8 4E16 ADDIU S0, S0, -5
-BFD00EFA 0C00 NOP
-BFD00EFC 0028F85E SW V0, 40(S8)
-BFD00F00 0028FC5E LW V0, 40(S8)
-BFD00F04 01005042 ORI V0, V0, 256
-BFD00F08 0028F85E SW V0, 40(S8)
-BFD00F0C 0028FC9E LW A0, 40(S8)
-BFD00F10 4E2677E8 JALS vPortSetCP0Cause
-BFD00F12 4E26 ADDIU S1, S1, 3
-BFD00F14 0C00 NOP
+BFD00EF6 4E1677E8 JALS ulPortGetCP0Cause\r
+BFD00EF8 4E16 ADDIU S0, S0, -5\r
+BFD00EFA 0C00 NOP\r
+BFD00EFC 0028F85E SW V0, 40(S8)\r
+BFD00F00 0028FC5E LW V0, 40(S8)\r
+BFD00F04 01005042 ORI V0, V0, 256\r
+BFD00F08 0028F85E SW V0, 40(S8)\r
+BFD00F0C 0028FC9E LW A0, 40(S8)\r
+BFD00F10 4E2677E8 JALS vPortSetCP0Cause\r
+BFD00F12 4E26 ADDIU S1, S1, 3\r
+BFD00F14 0C00 NOP\r
687: }\r
688: else\r
689: {\r
726: #endif /* configUSE_QUEUE_SETS */\r
727: \r
728: taskEXIT_CRITICAL();\r
-BFD00F16 40AA77E8 JALS vTaskExitCritical
-BFD00F18 0C0040AA BNEZC T2, 0xBFD0271C
-BFD00F1A 0C00 NOP
+BFD00F16 40AA77E8 JALS vTaskExitCritical\r
+BFD00F18 0C0040AA BNEZC T2, 0xBFD0271C\r
+BFD00F1A 0C00 NOP\r
729: return pdPASS;\r
-BFD00F1C ED01 LI V0, 1
-BFD00F1E CC87 B 0xBFD0102E
-BFD00F20 0C00 NOP
+BFD00F1C ED01 LI V0, 1\r
+BFD00F1E CC87 B 0xBFD0102E\r
+BFD00F20 0C00 NOP\r
730: }\r
731: else\r
732: {\r
733: if( xTicksToWait == ( TickType_t ) 0 )\r
-BFD00F22 0048FC5E LW V0, 72(S8)
-BFD00F26 000640A2 BNEZC V0, 0xBFD00F36
+BFD00F22 0048FC5E LW V0, 72(S8)\r
+BFD00F26 000640A2 BNEZC V0, 0xBFD00F36\r
734: {\r
735: /* The queue was full and no block time is specified (or\r
736: the block time has expired) so leave now. */\r
737: taskEXIT_CRITICAL();\r
-BFD00F2A 40AA77E8 JALS vTaskExitCritical
-BFD00F2C 0C0040AA BNEZC T2, 0xBFD02730
-BFD00F2E 0C00 NOP
+BFD00F2A 40AA77E8 JALS vTaskExitCritical\r
+BFD00F2C 0C0040AA BNEZC T2, 0xBFD02730\r
+BFD00F2E 0C00 NOP\r
738: \r
739: /* Return to the original privilege level before exiting\r
740: the function. */\r
741: traceQUEUE_SEND_FAILED( pxQueue );\r
742: return errQUEUE_FULL;\r
-BFD00F30 0C40 MOVE V0, ZERO
-BFD00F32 CC7D B 0xBFD0102E
-BFD00F34 0C00 NOP
+BFD00F30 0C40 MOVE V0, ZERO\r
+BFD00F32 CC7D B 0xBFD0102E\r
+BFD00F34 0C00 NOP\r
743: }\r
744: else if( xEntryTimeSet == pdFALSE )\r
-BFD00F36 0010FC5E LW V0, 16(S8)
-BFD00F3A 000940A2 BNEZC V0, 0xBFD00F50
+BFD00F36 0010FC5E LW V0, 16(S8)\r
+BFD00F3A 000940A2 BNEZC V0, 0xBFD00F50\r
745: {\r
746: /* The queue was full and a block time was specified so\r
747: configure the timeout structure. */\r
748: vTaskSetTimeOutState( &xTimeOut );\r
-BFD00F3E 002C305E ADDIU V0, S8, 44
-BFD00F42 0C82 MOVE A0, V0
-BFD00F44 47A677E8 JALS vTaskSetTimeOutState
-BFD00F48 0C00 NOP
+BFD00F3E 002C305E ADDIU V0, S8, 44\r
+BFD00F42 0C82 MOVE A0, V0\r
+BFD00F44 47A677E8 JALS vTaskSetTimeOutState\r
+BFD00F48 0C00 NOP\r
749: xEntryTimeSet = pdTRUE;\r
-BFD00F4A ED01 LI V0, 1
-BFD00F4C 0010F85E SW V0, 16(S8)
+BFD00F4A ED01 LI V0, 1\r
+BFD00F4C 0010F85E SW V0, 16(S8)\r
750: }\r
751: else\r
752: {\r
756: }\r
757: }\r
758: taskEXIT_CRITICAL();\r
-BFD00F50 40AA77E8 JALS vTaskExitCritical
-BFD00F52 0C0040AA BNEZC T2, 0xBFD02756
-BFD00F54 0C00 NOP
+BFD00F50 40AA77E8 JALS vTaskExitCritical\r
+BFD00F52 0C0040AA BNEZC T2, 0xBFD02756\r
+BFD00F54 0C00 NOP\r
759: \r
760: /* Interrupts and other tasks can send to and receive from the queue\r
761: now the critical section has been exited. */\r
762: \r
763: vTaskSuspendAll();\r
-BFD00F56 4EF477E8 JALS vTaskSuspendAll
-BFD00F58 4EF4 ADDIU S7, S7, -6
-BFD00F5A 0C00 NOP
+BFD00F56 4EF477E8 JALS vTaskSuspendAll\r
+BFD00F58 4EF4 ADDIU S7, S7, -6\r
+BFD00F5A 0C00 NOP\r
764: prvLockQueue( pxQueue );\r
-BFD00F5C 33B877E8 JALS vTaskEnterCritical
-BFD00F5E 0C0033B8 ADDIU SP, T8, 3072
-BFD00F60 0C00 NOP
-BFD00F62 0014FC5E LW V0, 20(S8)
-BFD00F66 0044FC62 LW V1, 68(V0)
-BFD00F6A ED7F LI V0, -1
-BFD00F6C 0005B443 BNE V1, V0, 0xBFD00F7A
-BFD00F6E 0C000005 SLL ZERO, A1, 1
-BFD00F70 0C00 NOP
-BFD00F72 0014FC5E LW V0, 20(S8)
-BFD00F76 0044F802 SW ZERO, 68(V0)
-BFD00F7A 0014FC5E LW V0, 20(S8)
-BFD00F7E 0048FC62 LW V1, 72(V0)
-BFD00F82 ED7F LI V0, -1
-BFD00F84 0005B443 BNE V1, V0, 0xBFD00F92
-BFD00F86 0C000005 SLL ZERO, A1, 1
-BFD00F88 0C00 NOP
-BFD00F8A 0014FC5E LW V0, 20(S8)
-BFD00F8E 0048F802 SW ZERO, 72(V0)
-BFD00F92 40AA77E8 JALS vTaskExitCritical
-BFD00F94 0C0040AA BNEZC T2, 0xBFD02798
-BFD00F96 0C00 NOP
+BFD00F5C 33B877E8 JALS vTaskEnterCritical\r
+BFD00F5E 0C0033B8 ADDIU SP, T8, 3072\r
+BFD00F60 0C00 NOP\r
+BFD00F62 0014FC5E LW V0, 20(S8)\r
+BFD00F66 0044FC62 LW V1, 68(V0)\r
+BFD00F6A ED7F LI V0, -1\r
+BFD00F6C 0005B443 BNE V1, V0, 0xBFD00F7A\r
+BFD00F6E 0C000005 SLL ZERO, A1, 1\r
+BFD00F70 0C00 NOP\r
+BFD00F72 0014FC5E LW V0, 20(S8)\r
+BFD00F76 0044F802 SW ZERO, 68(V0)\r
+BFD00F7A 0014FC5E LW V0, 20(S8)\r
+BFD00F7E 0048FC62 LW V1, 72(V0)\r
+BFD00F82 ED7F LI V0, -1\r
+BFD00F84 0005B443 BNE V1, V0, 0xBFD00F92\r
+BFD00F86 0C000005 SLL ZERO, A1, 1\r
+BFD00F88 0C00 NOP\r
+BFD00F8A 0014FC5E LW V0, 20(S8)\r
+BFD00F8E 0048F802 SW ZERO, 72(V0)\r
+BFD00F92 40AA77E8 JALS vTaskExitCritical\r
+BFD00F94 0C0040AA BNEZC T2, 0xBFD02798\r
+BFD00F96 0C00 NOP\r
765: \r
766: /* Update the timeout state to see if it has expired yet. */\r
767: if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\r
-BFD00F98 002C307E ADDIU V1, S8, 44
-BFD00F9C 0048305E ADDIU V0, S8, 72
-BFD00FA0 0C83 MOVE A0, V1
-BFD00FA2 0CA2 MOVE A1, V0
-BFD00FA4 1FF677E8 JALS xTaskCheckForTimeOut
-BFD00FA6 0C001FF6 LB RA, 3072(S6)
-BFD00FA8 0C00 NOP
-BFD00FAA 003740A2 BNEZC V0, 0xBFD0101C
+BFD00F98 002C307E ADDIU V1, S8, 44\r
+BFD00F9C 0048305E ADDIU V0, S8, 72\r
+BFD00FA0 0C83 MOVE A0, V1\r
+BFD00FA2 0CA2 MOVE A1, V0\r
+BFD00FA4 1FF677E8 JALS xTaskCheckForTimeOut\r
+BFD00FA6 0C001FF6 LB RA, 3072(S6)\r
+BFD00FA8 0C00 NOP\r
+BFD00FAA 003740A2 BNEZC V0, 0xBFD0101C\r
768: {\r
769: if( prvIsQueueFull( pxQueue ) != pdFALSE )\r
-BFD00FAE 0014FC9E LW A0, 20(S8)
-BFD00FB2 478277E8 JALS prvIsQueueFull
-BFD00FB6 0C00 NOP
-BFD00FB8 002640E2 BEQZC V0, 0xBFD01008
+BFD00FAE 0014FC9E LW A0, 20(S8)\r
+BFD00FB2 478277E8 JALS prvIsQueueFull\r
+BFD00FB6 0C00 NOP\r
+BFD00FB8 002640E2 BEQZC V0, 0xBFD01008\r
770: {\r
771: traceBLOCKING_ON_QUEUE_SEND( pxQueue );\r
772: vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );\r
-BFD00FBC 0014FC5E LW V0, 20(S8)
-BFD00FC0 6DA8 ADDIU V1, V0, 16
-BFD00FC2 0048FC5E LW V0, 72(S8)
-BFD00FC6 0C83 MOVE A0, V1
-BFD00FC8 0CA2 MOVE A1, V0
-BFD00FCA 2F3A77E8 JALS vTaskPlaceOnEventList
-BFD00FCC 2F3A ANDI A2, V1, 0x20
-BFD00FCE 0C00 NOP
+BFD00FBC 0014FC5E LW V0, 20(S8)\r
+BFD00FC0 6DA8 ADDIU V1, V0, 16\r
+BFD00FC2 0048FC5E LW V0, 72(S8)\r
+BFD00FC6 0C83 MOVE A0, V1\r
+BFD00FC8 0CA2 MOVE A1, V0\r
+BFD00FCA 2F3A77E8 JALS vTaskPlaceOnEventList\r
+BFD00FCC 2F3A ANDI A2, V1, 0x20\r
+BFD00FCE 0C00 NOP\r
773: \r
774: /* Unlocking the queue means queue events can effect the\r
775: event list. It is possible that interrupts occurring now\r
777: scheduler is suspended the task will go onto the pending\r
778: ready last instead of the actual ready list. */\r
779: prvUnlockQueue( pxQueue );\r
-BFD00FD0 0014FC9E LW A0, 20(S8)
-BFD00FD4 1DEE77E8 JALS prvUnlockQueue
-BFD00FD6 0C001DEE LB T7, 3072(T6)
-BFD00FD8 0C00 NOP
+BFD00FD0 0014FC9E LW A0, 20(S8)\r
+BFD00FD4 1DEE77E8 JALS prvUnlockQueue\r
+BFD00FD6 0C001DEE LB T7, 3072(T6)\r
+BFD00FD8 0C00 NOP\r
780: \r
781: /* Resuming the scheduler will move tasks from the pending\r
782: ready list into the ready list - so it is feasible that this\r
784: case the yield will not cause a context switch unless there\r
785: is also a higher priority task in the pending ready list. */\r
786: if( xTaskResumeAll() == pdFALSE )\r
-BFD00FDA 158E77E8 JALS xTaskResumeAll
-BFD00FDC 0C00158E LBU T4, 3072(T6)
-BFD00FDE 0C00 NOP
-BFD00FE0 FF1E40A2 BNEZC V0, 0xBFD00E20
-BFD00FE2 77E8FF1E LW T8, 30696(S8)
+BFD00FDA 158E77E8 JALS xTaskResumeAll\r
+BFD00FDC 0C00158E LBU T4, 3072(T6)\r
+BFD00FDE 0C00 NOP\r
+BFD00FE0 FF1E40A2 BNEZC V0, 0xBFD00E20\r
+BFD00FE2 77E8FF1E LW T8, 30696(S8)\r
787: {\r
788: portYIELD_WITHIN_API();\r
-BFD00FE4 4E1677E8 JALS ulPortGetCP0Cause
-BFD00FE6 4E16 ADDIU S0, S0, -5
-BFD00FE8 0C00 NOP
-BFD00FEA 0018F85E SW V0, 24(S8)
-BFD00FEE 0018FC5E LW V0, 24(S8)
-BFD00FF2 01005042 ORI V0, V0, 256
-BFD00FF6 0018F85E SW V0, 24(S8)
-BFD00FFA 0018FC9E LW A0, 24(S8)
-BFD00FFE 4E2677E8 JALS vPortSetCP0Cause
-BFD01000 4E26 ADDIU S1, S1, 3
-BFD01002 0C00 NOP
+BFD00FE4 4E1677E8 JALS ulPortGetCP0Cause\r
+BFD00FE6 4E16 ADDIU S0, S0, -5\r
+BFD00FE8 0C00 NOP\r
+BFD00FEA 0018F85E SW V0, 24(S8)\r
+BFD00FEE 0018FC5E LW V0, 24(S8)\r
+BFD00FF2 01005042 ORI V0, V0, 256\r
+BFD00FF6 0018F85E SW V0, 24(S8)\r
+BFD00FFA 0018FC9E LW A0, 24(S8)\r
+BFD00FFE 4E2677E8 JALS vPortSetCP0Cause\r
+BFD01000 4E26 ADDIU S1, S1, 3\r
+BFD01002 0C00 NOP\r
789: }\r
790: }\r
791: else\r
792: {\r
793: /* Try again. */\r
794: prvUnlockQueue( pxQueue );\r
-BFD01008 0014FC9E LW A0, 20(S8)
-BFD0100C 1DEE77E8 JALS prvUnlockQueue
-BFD0100E 0C001DEE LB T7, 3072(T6)
-BFD01010 0C00 NOP
+BFD01008 0014FC9E LW A0, 20(S8)\r
+BFD0100C 1DEE77E8 JALS prvUnlockQueue\r
+BFD0100E 0C001DEE LB T7, 3072(T6)\r
+BFD01010 0C00 NOP\r
795: ( void ) xTaskResumeAll();\r
-BFD01012 158E77E8 JALS xTaskResumeAll
-BFD01014 0C00158E LBU T4, 3072(T6)
-BFD01016 0C00 NOP
+BFD01012 158E77E8 JALS xTaskResumeAll\r
+BFD01014 0C00158E LBU T4, 3072(T6)\r
+BFD01016 0C00 NOP\r
796: }\r
797: }\r
798: else\r
799: {\r
800: /* The timeout has expired. */\r
801: prvUnlockQueue( pxQueue );\r
-BFD0101C 0014FC9E LW A0, 20(S8)
-BFD01020 1DEE77E8 JALS prvUnlockQueue
-BFD01022 0C001DEE LB T7, 3072(T6)
-BFD01024 0C00 NOP
+BFD0101C 0014FC9E LW A0, 20(S8)\r
+BFD01020 1DEE77E8 JALS prvUnlockQueue\r
+BFD01022 0C001DEE LB T7, 3072(T6)\r
+BFD01024 0C00 NOP\r
802: ( void ) xTaskResumeAll();\r
-BFD01026 158E77E8 JALS xTaskResumeAll
-BFD01028 0C00158E LBU T4, 3072(T6)
-BFD0102A 0C00 NOP
+BFD01026 158E77E8 JALS xTaskResumeAll\r
+BFD01028 0C00158E LBU T4, 3072(T6)\r
+BFD0102A 0C00 NOP\r
803: \r
804: /* Return to the original privilege level before exiting the\r
805: function. */\r
806: traceQUEUE_SEND_FAILED( pxQueue );\r
807: return errQUEUE_FULL;\r
-BFD0102C 0C40 MOVE V0, ZERO
+BFD0102C 0C40 MOVE V0, ZERO\r
808: }\r
809: }\r
-BFD00E20 0C00 NOP
-BFD01004 CF0E B 0xBFD00E22
-BFD01006 0C00 NOP
-BFD01018 CF04 B 0xBFD00E22
-BFD0101A 0C00 NOP
+BFD00E20 0C00 NOP\r
+BFD01004 CF0E B 0xBFD00E22\r
+BFD01006 0C00 NOP\r
+BFD01018 CF04 B 0xBFD00E22\r
+BFD0101A 0C00 NOP\r
810: }\r
-BFD0102E 0FBE MOVE SP, S8
-BFD01030 4BEF LW RA, 60(SP)
-BFD01032 4BCE LW S8, 56(SP)
-BFD01034 4C21 ADDIU SP, SP, 64
-BFD01036 459F JR16 RA
-BFD01038 0C00 NOP
+BFD0102E 0FBE MOVE SP, S8\r
+BFD01030 4BEF LW RA, 60(SP)\r
+BFD01032 4BCE LW S8, 56(SP)\r
+BFD01034 4C21 ADDIU SP, SP, 64\r
+BFD01036 459F JR16 RA\r
+BFD01038 0C00 NOP\r
811: /*-----------------------------------------------------------*/\r
812: \r
813: #if ( configUSE_ALTERNATIVE_API == 1 )\r
1057: \r
1058: BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )\r
1059: {\r
-BFD023D4 4FED ADDIU SP, SP, -40
-BFD023D6 CBE9 SW RA, 36(SP)
-BFD023D8 CBC8 SW S8, 32(SP)
-BFD023DA 0FDD MOVE S8, SP
-BFD023DC 0028F89E SW A0, 40(S8)
-BFD023E0 002CF8BE SW A1, 44(S8)
-BFD023E4 0030F8DE SW A2, 48(S8)
-BFD023E8 0034F8FE SW A3, 52(S8)
+BFD023D4 4FED ADDIU SP, SP, -40\r
+BFD023D6 CBE9 SW RA, 36(SP)\r
+BFD023D8 CBC8 SW S8, 32(SP)\r
+BFD023DA 0FDD MOVE S8, SP\r
+BFD023DC 0028F89E SW A0, 40(S8)\r
+BFD023E0 002CF8BE SW A1, 44(S8)\r
+BFD023E4 0030F8DE SW A2, 48(S8)\r
+BFD023E8 0034F8FE SW A3, 52(S8)\r
1060: BaseType_t xReturn;\r
1061: UBaseType_t uxSavedInterruptStatus;\r
1062: Queue_t * const pxQueue = ( Queue_t * ) xQueue;\r
-BFD023EC 0028FC5E LW V0, 40(S8)
-BFD023F0 0014F85E SW V0, 20(S8)
+BFD023EC 0028FC5E LW V0, 40(S8)\r
+BFD023F0 0014F85E SW V0, 20(S8)\r
1063: \r
1064: configASSERT( pxQueue );\r
-BFD023F4 0014FC5E LW V0, 20(S8)
-BFD023F8 000940A2 BNEZC V0, 0xBFD0240E
-BFD023FC BFD141A2 LUI V0, 0xBFD1
-BFD023FE 3082BFD1 LDC1 F30, 12418(S1)
-BFD02400 9E3C3082 ADDIU A0, V0, -25028
-BFD02402 30A09E3C LWC1 F17, 12448(GP)
-BFD02404 042830A0 ADDIU A1, ZERO, 1064
-BFD02406 0428 ADDU S0, A0, V0
-BFD02408 4B7E77E8 JALS vAssertCalled
-BFD0240A 4B7E LW K1, 120(SP)
-BFD0240C 0C00 NOP
+BFD023F4 0014FC5E LW V0, 20(S8)\r
+BFD023F8 000940A2 BNEZC V0, 0xBFD0240E\r
+BFD023FC BFD141A2 LUI V0, 0xBFD1\r
+BFD023FE 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD02400 9E3C3082 ADDIU A0, V0, -25028\r
+BFD02402 30A09E3C LWC1 F17, 12448(GP)\r
+BFD02404 042830A0 ADDIU A1, ZERO, 1064\r
+BFD02406 0428 ADDU S0, A0, V0\r
+BFD02408 4B7E77E8 JALS vAssertCalled\r
+BFD0240A 4B7E LW K1, 120(SP)\r
+BFD0240C 0C00 NOP\r
1065: configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\r
-BFD0240E 002CFC5E LW V0, 44(S8)
-BFD02412 000640A2 BNEZC V0, 0xBFD02422
-BFD02416 0014FC5E LW V0, 20(S8)
-BFD0241A 0040FC42 LW V0, 64(V0)
-BFD0241E 000340A2 BNEZC V0, 0xBFD02428
-BFD02422 ED01 LI V0, 1
-BFD02424 CC02 B 0xBFD0242A
-BFD02426 0C00 NOP
-BFD02428 0C40 MOVE V0, ZERO
-BFD0242A 000940A2 BNEZC V0, 0xBFD02440
-BFD0242E BFD141A2 LUI V0, 0xBFD1
-BFD02430 3082BFD1 LDC1 F30, 12418(S1)
-BFD02432 9E3C3082 ADDIU A0, V0, -25028
-BFD02434 30A09E3C LWC1 F17, 12448(GP)
-BFD02436 042930A0 ADDIU A1, ZERO, 1065
-BFD02438 0429 SUBU S0, A0, V0
-BFD0243A 4B7E77E8 JALS vAssertCalled
-BFD0243C 4B7E LW K1, 120(SP)
-BFD0243E 0C00 NOP
+BFD0240E 002CFC5E LW V0, 44(S8)\r
+BFD02412 000640A2 BNEZC V0, 0xBFD02422\r
+BFD02416 0014FC5E LW V0, 20(S8)\r
+BFD0241A 0040FC42 LW V0, 64(V0)\r
+BFD0241E 000340A2 BNEZC V0, 0xBFD02428\r
+BFD02422 ED01 LI V0, 1\r
+BFD02424 CC02 B 0xBFD0242A\r
+BFD02426 0C00 NOP\r
+BFD02428 0C40 MOVE V0, ZERO\r
+BFD0242A 000940A2 BNEZC V0, 0xBFD02440\r
+BFD0242E BFD141A2 LUI V0, 0xBFD1\r
+BFD02430 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD02432 9E3C3082 ADDIU A0, V0, -25028\r
+BFD02434 30A09E3C LWC1 F17, 12448(GP)\r
+BFD02436 042930A0 ADDIU A1, ZERO, 1065\r
+BFD02438 0429 SUBU S0, A0, V0\r
+BFD0243A 4B7E77E8 JALS vAssertCalled\r
+BFD0243C 4B7E LW K1, 120(SP)\r
+BFD0243E 0C00 NOP\r
1066: configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );\r
-BFD02440 0034FC7E LW V1, 52(S8)
-BFD02444 ED02 LI V0, 2
-BFD02446 0008B443 BNE V1, V0, 0xBFD0245A
-BFD02448 0C000008 SLL ZERO, T0, 1
-BFD0244A 0C00 NOP
-BFD0244C 0014FC5E LW V0, 20(S8)
-BFD02450 69AF LW V1, 60(V0)
-BFD02452 ED01 LI V0, 1
-BFD02454 0004B443 BNE V1, V0, 0xBFD02460
-BFD02456 0C000004 SLL ZERO, A0, 1
-BFD02458 0C00 NOP
-BFD0245A ED01 LI V0, 1
-BFD0245C CC02 B 0xBFD02462
-BFD0245E 0C00 NOP
-BFD02460 0C40 MOVE V0, ZERO
-BFD02462 000940A2 BNEZC V0, 0xBFD02478
-BFD02466 BFD141A2 LUI V0, 0xBFD1
-BFD02468 3082BFD1 LDC1 F30, 12418(S1)
-BFD0246A 9E3C3082 ADDIU A0, V0, -25028
-BFD0246C 30A09E3C LWC1 F17, 12448(GP)
-BFD0246E 042A30A0 ADDIU A1, ZERO, 1066
-BFD02470 042A ADDU S0, A1, V0
-BFD02472 4B7E77E8 JALS vAssertCalled
-BFD02474 4B7E LW K1, 120(SP)
-BFD02476 0C00 NOP
+BFD02440 0034FC7E LW V1, 52(S8)\r
+BFD02444 ED02 LI V0, 2\r
+BFD02446 0008B443 BNE V1, V0, 0xBFD0245A\r
+BFD02448 0C000008 SLL ZERO, T0, 1\r
+BFD0244A 0C00 NOP\r
+BFD0244C 0014FC5E LW V0, 20(S8)\r
+BFD02450 69AF LW V1, 60(V0)\r
+BFD02452 ED01 LI V0, 1\r
+BFD02454 0004B443 BNE V1, V0, 0xBFD02460\r
+BFD02456 0C000004 SLL ZERO, A0, 1\r
+BFD02458 0C00 NOP\r
+BFD0245A ED01 LI V0, 1\r
+BFD0245C CC02 B 0xBFD02462\r
+BFD0245E 0C00 NOP\r
+BFD02460 0C40 MOVE V0, ZERO\r
+BFD02462 000940A2 BNEZC V0, 0xBFD02478\r
+BFD02466 BFD141A2 LUI V0, 0xBFD1\r
+BFD02468 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD0246A 9E3C3082 ADDIU A0, V0, -25028\r
+BFD0246C 30A09E3C LWC1 F17, 12448(GP)\r
+BFD0246E 042A30A0 ADDIU A1, ZERO, 1066\r
+BFD02470 042A ADDU S0, A1, V0\r
+BFD02472 4B7E77E8 JALS vAssertCalled\r
+BFD02474 4B7E LW K1, 120(SP)\r
+BFD02476 0C00 NOP\r
1067: \r
1068: /* RTOS ports that support interrupt nesting have the concept of a maximum\r
1069: system call (or maximum API call) interrupt priority. Interrupts that are\r
1087: not (i.e. has a task with a higher priority than us been woken by this\r
1088: post). */\r
1089: uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r
-BFD02478 475E77E8 JALS uxPortSetInterruptMaskFromISR
-BFD0247C 0C00 NOP
-BFD0247E 0018F85E SW V0, 24(S8)
+BFD02478 475E77E8 JALS uxPortSetInterruptMaskFromISR\r
+BFD0247C 0C00 NOP\r
+BFD0247E 0018F85E SW V0, 24(S8)\r
1090: {\r
1091: if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )\r
-BFD02482 0014FC5E LW V0, 20(S8)
-BFD02486 69AE LW V1, 56(V0)
-BFD02488 0014FC5E LW V0, 20(S8)
-BFD0248C 692F LW V0, 60(V0)
-BFD0248E 13900043 SLTU V0, V1, V0
-BFD02490 40A21390 ADDI GP, S0, 16546
-BFD02492 000640A2 BNEZC V0, 0xBFD024A2
-BFD02496 0034FC7E LW V1, 52(S8)
-BFD0249A ED02 LI V0, 2
-BFD0249C 0055B443 BNE V1, V0, 0xBFD0254A
-BFD0249E 0C000055 SLL V0, S5, 1
-BFD024A0 0C00 NOP
+BFD02482 0014FC5E LW V0, 20(S8)\r
+BFD02486 69AE LW V1, 56(V0)\r
+BFD02488 0014FC5E LW V0, 20(S8)\r
+BFD0248C 692F LW V0, 60(V0)\r
+BFD0248E 13900043 SLTU V0, V1, V0\r
+BFD02490 40A21390 ADDI GP, S0, 16546\r
+BFD02492 000640A2 BNEZC V0, 0xBFD024A2\r
+BFD02496 0034FC7E LW V1, 52(S8)\r
+BFD0249A ED02 LI V0, 2\r
+BFD0249C 0055B443 BNE V1, V0, 0xBFD0254A\r
+BFD0249E 0C000055 SLL V0, S5, 1\r
+BFD024A0 0C00 NOP\r
1092: {\r
1093: traceQUEUE_SEND_FROM_ISR( pxQueue );\r
1094: \r
1098: called here even though the disinherit function does not check if\r
1099: the scheduler is suspended before accessing the ready lists. */\r
1100: ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );\r
-BFD024A2 0014FC9E LW A0, 20(S8)
-BFD024A6 002CFCBE LW A1, 44(S8)
-BFD024AA 0034FCDE LW A2, 52(S8)
-BFD024AE 14E677E8 JALS prvCopyDataToQueue
-BFD024B0 0C0014E6 LBU A3, 3072(A2)
-BFD024B2 0C00 NOP
+BFD024A2 0014FC9E LW A0, 20(S8)\r
+BFD024A6 002CFCBE LW A1, 44(S8)\r
+BFD024AA 0034FCDE LW A2, 52(S8)\r
+BFD024AE 14E677E8 JALS prvCopyDataToQueue\r
+BFD024B0 0C0014E6 LBU A3, 3072(A2)\r
+BFD024B2 0C00 NOP\r
1101: \r
1102: /* The event list is not altered if the queue is locked. This will\r
1103: be done when the queue is unlocked later. */\r
1104: if( pxQueue->xTxLock == queueUNLOCKED )\r
-BFD024B4 0014FC5E LW V0, 20(S8)
-BFD024B8 0048FC62 LW V1, 72(V0)
-BFD024BC ED7F LI V0, -1
-BFD024BE 0036B443 BNE V1, V0, 0xBFD0252E
-BFD024C0 0C000036 SLL AT, S6, 1
-BFD024C2 0C00 NOP
+BFD024B4 0014FC5E LW V0, 20(S8)\r
+BFD024B8 0048FC62 LW V1, 72(V0)\r
+BFD024BC ED7F LI V0, -1\r
+BFD024BE 0036B443 BNE V1, V0, 0xBFD0252E\r
+BFD024C0 0C000036 SLL AT, S6, 1\r
+BFD024C2 0C00 NOP\r
1105: {\r
1106: #if ( configUSE_QUEUE_SETS == 1 )\r
1107: {\r
1108: if( pxQueue->pxQueueSetContainer != NULL )\r
-BFD024C4 0014FC5E LW V0, 20(S8)
-BFD024C8 004CFC42 LW V0, 76(V0)
-BFD024CC 001640E2 BEQZC V0, 0xBFD024FC
+BFD024C4 0014FC5E LW V0, 20(S8)\r
+BFD024C8 004CFC42 LW V0, 76(V0)\r
+BFD024CC 001640E2 BEQZC V0, 0xBFD024FC\r
1109: {\r
1110: if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) == pdTRUE )\r
-BFD024D0 0014FC9E LW A0, 20(S8)
-BFD024D4 0034FCBE LW A1, 52(S8)
-BFD024D8 21D877E8 JALS prvNotifyQueueSetContainer
-BFD024DA 0C0021D8 LWC2 T6, 3072(T8)
-BFD024DC 0C00 NOP
-BFD024DE 0C62 MOVE V1, V0
-BFD024E0 ED01 LI V0, 1
-BFD024E2 002DB443 BNE V1, V0, 0xBFD02540
-BFD024E4 0C00002D SLL AT, T5, 1
-BFD024E6 0C00 NOP
+BFD024D0 0014FC9E LW A0, 20(S8)\r
+BFD024D4 0034FCBE LW A1, 52(S8)\r
+BFD024D8 21D877E8 JALS prvNotifyQueueSetContainer\r
+BFD024DA 0C0021D8 LWC2 T6, 3072(T8)\r
+BFD024DC 0C00 NOP\r
+BFD024DE 0C62 MOVE V1, V0\r
+BFD024E0 ED01 LI V0, 1\r
+BFD024E2 002DB443 BNE V1, V0, 0xBFD02540\r
+BFD024E4 0C00002D SLL AT, T5, 1\r
+BFD024E6 0C00 NOP\r
1111: {\r
1112: /* The queue is a member of a queue set, and posting\r
1113: to the queue set caused a higher priority task to\r
1114: unblock. A context switch is required. */\r
1115: if( pxHigherPriorityTaskWoken != NULL )\r
-BFD024E8 0030FC5E LW V0, 48(S8)
-BFD024EC 002840E2 BEQZC V0, 0xBFD02540
+BFD024E8 0030FC5E LW V0, 48(S8)\r
+BFD024EC 002840E2 BEQZC V0, 0xBFD02540\r
1116: {\r
1117: *pxHigherPriorityTaskWoken = pdTRUE;\r
-BFD024F0 0030FC5E LW V0, 48(S8)
-BFD024F4 ED81 LI V1, 1
-BFD024F6 E9A0 SW V1, 0(V0)
-BFD024F8 CC23 B 0xBFD02540
-BFD024FA 0C00 NOP
+BFD024F0 0030FC5E LW V0, 48(S8)\r
+BFD024F4 ED81 LI V1, 1\r
+BFD024F6 E9A0 SW V1, 0(V0)\r
+BFD024F8 CC23 B 0xBFD02540\r
+BFD024FA 0C00 NOP\r
1118: }\r
1119: else\r
1120: {\r
1129: else\r
1130: {\r
1131: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
-BFD024FC 0014FC5E LW V0, 20(S8)
-BFD02500 6929 LW V0, 36(V0)
-BFD02502 001D40E2 BEQZC V0, 0xBFD02540
+BFD024FC 0014FC5E LW V0, 20(S8)\r
+BFD02500 6929 LW V0, 36(V0)\r
+BFD02502 001D40E2 BEQZC V0, 0xBFD02540\r
1132: {\r
1133: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
-BFD02506 0014FC5E LW V0, 20(S8)
-BFD0250A 00243042 ADDIU V0, V0, 36
-BFD0250E 0C82 MOVE A0, V0
-BFD02510 22BC77E8 JALS xTaskRemoveFromEventList
-BFD02512 0C0022BC LWC2 S5, 3072(GP)
-BFD02514 0C00 NOP
-BFD02516 001340E2 BEQZC V0, 0xBFD02540
+BFD02506 0014FC5E LW V0, 20(S8)\r
+BFD0250A 00243042 ADDIU V0, V0, 36\r
+BFD0250E 0C82 MOVE A0, V0\r
+BFD02510 22BC77E8 JALS xTaskRemoveFromEventList\r
+BFD02512 0C0022BC LWC2 S5, 3072(GP)\r
+BFD02514 0C00 NOP\r
+BFD02516 001340E2 BEQZC V0, 0xBFD02540\r
1134: {\r
1135: /* The task waiting has a higher priority so\r
1136: record that a context switch is required. */\r
1137: if( pxHigherPriorityTaskWoken != NULL )\r
-BFD0251A 0030FC5E LW V0, 48(S8)
-BFD0251E 000F40E2 BEQZC V0, 0xBFD02540
+BFD0251A 0030FC5E LW V0, 48(S8)\r
+BFD0251E 000F40E2 BEQZC V0, 0xBFD02540\r
1138: {\r
1139: *pxHigherPriorityTaskWoken = pdTRUE;\r
-BFD02522 0030FC5E LW V0, 48(S8)
-BFD02526 ED81 LI V1, 1
-BFD02528 E9A0 SW V1, 0(V0)
-BFD0252A CC0A B 0xBFD02540
-BFD0252C 0C00 NOP
+BFD02522 0030FC5E LW V0, 48(S8)\r
+BFD02526 ED81 LI V1, 1\r
+BFD02528 E9A0 SW V1, 0(V0)\r
+BFD0252A CC0A B 0xBFD02540\r
+BFD0252C 0C00 NOP\r
1140: }\r
1141: else\r
1142: {\r
1188: /* Increment the lock count so the task that unlocks the queue\r
1189: knows that data was posted while it was locked. */\r
1190: ++( pxQueue->xTxLock );\r
-BFD0252E 0014FC5E LW V0, 20(S8)
-BFD02532 0048FC42 LW V0, 72(V0)
-BFD02536 6DA0 ADDIU V1, V0, 1
-BFD02538 0014FC5E LW V0, 20(S8)
-BFD0253C 0048F862 SW V1, 72(V0)
+BFD0252E 0014FC5E LW V0, 20(S8)\r
+BFD02532 0048FC42 LW V0, 72(V0)\r
+BFD02536 6DA0 ADDIU V1, V0, 1\r
+BFD02538 0014FC5E LW V0, 20(S8)\r
+BFD0253C 0048F862 SW V1, 72(V0)\r
1191: }\r
1192: \r
1193: xReturn = pdPASS;\r
-BFD02540 ED01 LI V0, 1
-BFD02542 0010F85E SW V0, 16(S8)
-BFD02546 CC03 B 0xBFD0254E
-BFD02548 0C00 NOP
+BFD02540 ED01 LI V0, 1\r
+BFD02542 0010F85E SW V0, 16(S8)\r
+BFD02546 CC03 B 0xBFD0254E\r
+BFD02548 0C00 NOP\r
1194: }\r
1195: else\r
1196: {\r
1197: traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );\r
1198: xReturn = errQUEUE_FULL;\r
-BFD0254A 0010F81E SW ZERO, 16(S8)
+BFD0254A 0010F81E SW ZERO, 16(S8)\r
1199: }\r
1200: }\r
1201: portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r
-BFD0254E 0018FC9E LW A0, 24(S8)
-BFD02552 4D5E77E8 JALS vPortClearInterruptMaskFromISR
-BFD02554 4D5E ADDIU T2, T2, -1
-BFD02556 0C00 NOP
+BFD0254E 0018FC9E LW A0, 24(S8)\r
+BFD02552 4D5E77E8 JALS vPortClearInterruptMaskFromISR\r
+BFD02554 4D5E ADDIU T2, T2, -1\r
+BFD02556 0C00 NOP\r
1202: \r
1203: return xReturn;\r
-BFD02558 0010FC5E LW V0, 16(S8)
+BFD02558 0010FC5E LW V0, 16(S8)\r
1204: }\r
-BFD0255C 0FBE MOVE SP, S8
-BFD0255E 4BE9 LW RA, 36(SP)
-BFD02560 4BC8 LW S8, 32(SP)
-BFD02562 4C15 ADDIU SP, SP, 40
-BFD02564 459F JR16 RA
-BFD02566 0C00 NOP
+BFD0255C 0FBE MOVE SP, S8\r
+BFD0255E 4BE9 LW RA, 36(SP)\r
+BFD02560 4BC8 LW S8, 32(SP)\r
+BFD02562 4C15 ADDIU SP, SP, 40\r
+BFD02564 459F JR16 RA\r
+BFD02566 0C00 NOP\r
1205: /*-----------------------------------------------------------*/\r
1206: \r
1207: BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken )\r
1208: {\r
-BFD0286C 4FED ADDIU SP, SP, -40
-BFD0286E CBE9 SW RA, 36(SP)
-BFD02870 CBC8 SW S8, 32(SP)
-BFD02872 0FDD MOVE S8, SP
-BFD02874 0028F89E SW A0, 40(S8)
-BFD02878 002CF8BE SW A1, 44(S8)
+BFD0286C 4FED ADDIU SP, SP, -40\r
+BFD0286E CBE9 SW RA, 36(SP)\r
+BFD02870 CBC8 SW S8, 32(SP)\r
+BFD02872 0FDD MOVE S8, SP\r
+BFD02874 0028F89E SW A0, 40(S8)\r
+BFD02878 002CF8BE SW A1, 44(S8)\r
1209: BaseType_t xReturn;\r
1210: UBaseType_t uxSavedInterruptStatus;\r
1211: Queue_t * const pxQueue = ( Queue_t * ) xQueue;\r
-BFD0287C 0028FC5E LW V0, 40(S8)
-BFD02880 0014F85E SW V0, 20(S8)
+BFD0287C 0028FC5E LW V0, 40(S8)\r
+BFD02880 0014F85E SW V0, 20(S8)\r
1212: \r
1213: /* Similar to xQueueGenericSendFromISR() but used with semaphores where the\r
1214: item size is 0. Don't directly wake a task that was blocked on a queue\r
1217: post). */\r
1218: \r
1219: configASSERT( pxQueue );\r
-BFD02884 0014FC5E LW V0, 20(S8)
-BFD02888 000940A2 BNEZC V0, 0xBFD0289E
-BFD0288C BFD141A2 LUI V0, 0xBFD1
-BFD0288E 3082BFD1 LDC1 F30, 12418(S1)
-BFD02890 9E3C3082 ADDIU A0, V0, -25028
-BFD02892 30A09E3C LWC1 F17, 12448(GP)
-BFD02894 04C330A0 ADDIU A1, ZERO, 1219
-BFD02896 04C3 SUBU S1, S1, A0
-BFD02898 4B7E77E8 JALS vAssertCalled
-BFD0289A 4B7E LW K1, 120(SP)
-BFD0289C 0C00 NOP
+BFD02884 0014FC5E LW V0, 20(S8)\r
+BFD02888 000940A2 BNEZC V0, 0xBFD0289E\r
+BFD0288C BFD141A2 LUI V0, 0xBFD1\r
+BFD0288E 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD02890 9E3C3082 ADDIU A0, V0, -25028\r
+BFD02892 30A09E3C LWC1 F17, 12448(GP)\r
+BFD02894 04C330A0 ADDIU A1, ZERO, 1219\r
+BFD02896 04C3 SUBU S1, S1, A0\r
+BFD02898 4B7E77E8 JALS vAssertCalled\r
+BFD0289A 4B7E LW K1, 120(SP)\r
+BFD0289C 0C00 NOP\r
1220: \r
1221: /* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()\r
1222: if the item size is not 0. */\r
1223: configASSERT( pxQueue->uxItemSize == 0 );\r
-BFD0289E 0014FC5E LW V0, 20(S8)
-BFD028A2 0040FC42 LW V0, 64(V0)
-BFD028A6 000940E2 BEQZC V0, 0xBFD028BC
-BFD028AA BFD141A2 LUI V0, 0xBFD1
-BFD028AC 3082BFD1 LDC1 F30, 12418(S1)
-BFD028AE 9E3C3082 ADDIU A0, V0, -25028
-BFD028B0 30A09E3C LWC1 F17, 12448(GP)
-BFD028B2 04C730A0 ADDIU A1, ZERO, 1223
-BFD028B4 04C7 SUBU S1, V1, A0
-BFD028B6 4B7E77E8 JALS vAssertCalled
-BFD028B8 4B7E LW K1, 120(SP)
-BFD028BA 0C00 NOP
+BFD0289E 0014FC5E LW V0, 20(S8)\r
+BFD028A2 0040FC42 LW V0, 64(V0)\r
+BFD028A6 000940E2 BEQZC V0, 0xBFD028BC\r
+BFD028AA BFD141A2 LUI V0, 0xBFD1\r
+BFD028AC 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD028AE 9E3C3082 ADDIU A0, V0, -25028\r
+BFD028B0 30A09E3C LWC1 F17, 12448(GP)\r
+BFD028B2 04C730A0 ADDIU A1, ZERO, 1223\r
+BFD028B4 04C7 SUBU S1, V1, A0\r
+BFD028B6 4B7E77E8 JALS vAssertCalled\r
+BFD028B8 4B7E LW K1, 120(SP)\r
+BFD028BA 0C00 NOP\r
1224: \r
1225: /* Normally a mutex would not be given from an interrupt, and doing so is\r
1226: definitely wrong if there is a mutex holder as priority inheritance makes no\r
1227: sense for an interrupts, only tasks. */\r
1228: configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->pxMutexHolder != NULL ) ) );\r
-BFD028BC 0014FC5E LW V0, 20(S8)
-BFD028C0 6920 LW V0, 0(V0)
-BFD028C2 000540A2 BNEZC V0, 0xBFD028D0
-BFD028C6 0014FC5E LW V0, 20(S8)
-BFD028CA 6921 LW V0, 4(V0)
-BFD028CC 000340A2 BNEZC V0, 0xBFD028D6
-BFD028D0 ED01 LI V0, 1
-BFD028D2 CC02 B 0xBFD028D8
-BFD028D4 0C00 NOP
-BFD028D6 0C40 MOVE V0, ZERO
-BFD028D8 000940A2 BNEZC V0, 0xBFD028EE
-BFD028DC BFD141A2 LUI V0, 0xBFD1
-BFD028DE 3082BFD1 LDC1 F30, 12418(S1)
-BFD028E0 9E3C3082 ADDIU A0, V0, -25028
-BFD028E2 30A09E3C LWC1 F17, 12448(GP)
-BFD028E4 04CC30A0 ADDIU A1, ZERO, 1228
-BFD028E6 04CC ADDU S1, A2, A0
-BFD028E8 4B7E77E8 JALS vAssertCalled
-BFD028EA 4B7E LW K1, 120(SP)
-BFD028EC 0C00 NOP
+BFD028BC 0014FC5E LW V0, 20(S8)\r
+BFD028C0 6920 LW V0, 0(V0)\r
+BFD028C2 000540A2 BNEZC V0, 0xBFD028D0\r
+BFD028C6 0014FC5E LW V0, 20(S8)\r
+BFD028CA 6921 LW V0, 4(V0)\r
+BFD028CC 000340A2 BNEZC V0, 0xBFD028D6\r
+BFD028D0 ED01 LI V0, 1\r
+BFD028D2 CC02 B 0xBFD028D8\r
+BFD028D4 0C00 NOP\r
+BFD028D6 0C40 MOVE V0, ZERO\r
+BFD028D8 000940A2 BNEZC V0, 0xBFD028EE\r
+BFD028DC BFD141A2 LUI V0, 0xBFD1\r
+BFD028DE 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD028E0 9E3C3082 ADDIU A0, V0, -25028\r
+BFD028E2 30A09E3C LWC1 F17, 12448(GP)\r
+BFD028E4 04CC30A0 ADDIU A1, ZERO, 1228\r
+BFD028E6 04CC ADDU S1, A2, A0\r
+BFD028E8 4B7E77E8 JALS vAssertCalled\r
+BFD028EA 4B7E LW K1, 120(SP)\r
+BFD028EC 0C00 NOP\r
1229: \r
1230: /* RTOS ports that support interrupt nesting have the concept of a maximum\r
1231: system call (or maximum API call) interrupt priority. Interrupts that are\r
1244: portASSERT_IF_INTERRUPT_PRIORITY_INVALID();\r
1245: \r
1246: uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r
-BFD028EE 475E77E8 JALS uxPortSetInterruptMaskFromISR
-BFD028F2 0C00 NOP
-BFD028F4 0018F85E SW V0, 24(S8)
+BFD028EE 475E77E8 JALS uxPortSetInterruptMaskFromISR\r
+BFD028F2 0C00 NOP\r
+BFD028F4 0018F85E SW V0, 24(S8)\r
1247: {\r
1248: /* When the queue is used to implement a semaphore no data is ever\r
1249: moved through the queue but it is still valid to see if the queue 'has\r
1250: space'. */\r
1251: if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\r
-BFD028F8 0014FC5E LW V0, 20(S8)
-BFD028FC 69AE LW V1, 56(V0)
-BFD028FE 0014FC5E LW V0, 20(S8)
-BFD02902 692F LW V0, 60(V0)
-BFD02904 13900043 SLTU V0, V1, V0
-BFD02906 40E21390 ADDI GP, S0, 16610
-BFD02908 005140E2 BEQZC V0, 0xBFD029AE
+BFD028F8 0014FC5E LW V0, 20(S8)\r
+BFD028FC 69AE LW V1, 56(V0)\r
+BFD028FE 0014FC5E LW V0, 20(S8)\r
+BFD02902 692F LW V0, 60(V0)\r
+BFD02904 13900043 SLTU V0, V1, V0\r
+BFD02906 40E21390 ADDI GP, S0, 16610\r
+BFD02908 005140E2 BEQZC V0, 0xBFD029AE\r
1252: {\r
1253: traceQUEUE_SEND_FROM_ISR( pxQueue );\r
1254: \r
1259: priority disinheritance is needed. Simply increase the count of\r
1260: messages (semaphores) available. */\r
1261: ++( pxQueue->uxMessagesWaiting );\r
-BFD0290C 0014FC5E LW V0, 20(S8)
-BFD02910 692E LW V0, 56(V0)
-BFD02912 6DA0 ADDIU V1, V0, 1
-BFD02914 0014FC5E LW V0, 20(S8)
-BFD02918 E9AE SW V1, 56(V0)
+BFD0290C 0014FC5E LW V0, 20(S8)\r
+BFD02910 692E LW V0, 56(V0)\r
+BFD02912 6DA0 ADDIU V1, V0, 1\r
+BFD02914 0014FC5E LW V0, 20(S8)\r
+BFD02918 E9AE SW V1, 56(V0)\r
1262: \r
1263: /* The event list is not altered if the queue is locked. This will\r
1264: be done when the queue is unlocked later. */\r
1265: if( pxQueue->xTxLock == queueUNLOCKED )\r
-BFD0291A 0014FC5E LW V0, 20(S8)
-BFD0291E 0048FC62 LW V1, 72(V0)
-BFD02922 ED7F LI V0, -1
-BFD02924 0035B443 BNE V1, V0, 0xBFD02992
-BFD02926 0C000035 SLL AT, S5, 1
-BFD02928 0C00 NOP
+BFD0291A 0014FC5E LW V0, 20(S8)\r
+BFD0291E 0048FC62 LW V1, 72(V0)\r
+BFD02922 ED7F LI V0, -1\r
+BFD02924 0035B443 BNE V1, V0, 0xBFD02992\r
+BFD02926 0C000035 SLL AT, S5, 1\r
+BFD02928 0C00 NOP\r
1266: {\r
1267: #if ( configUSE_QUEUE_SETS == 1 )\r
1268: {\r
1269: if( pxQueue->pxQueueSetContainer != NULL )\r
-BFD0292A 0014FC5E LW V0, 20(S8)
-BFD0292E 004CFC42 LW V0, 76(V0)
-BFD02932 001540E2 BEQZC V0, 0xBFD02960
+BFD0292A 0014FC5E LW V0, 20(S8)\r
+BFD0292E 004CFC42 LW V0, 76(V0)\r
+BFD02932 001540E2 BEQZC V0, 0xBFD02960\r
1270: {\r
1271: if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) == pdTRUE )\r
-BFD02936 0014FC9E LW A0, 20(S8)
-BFD0293A 0CA0 MOVE A1, ZERO
-BFD0293C 21D877E8 JALS prvNotifyQueueSetContainer
-BFD0293E 0C0021D8 LWC2 T6, 3072(T8)
-BFD02940 0C00 NOP
-BFD02942 0C62 MOVE V1, V0
-BFD02944 ED01 LI V0, 1
-BFD02946 002DB443 BNE V1, V0, 0xBFD029A4
-BFD02948 0C00002D SLL AT, T5, 1
-BFD0294A 0C00 NOP
+BFD02936 0014FC9E LW A0, 20(S8)\r
+BFD0293A 0CA0 MOVE A1, ZERO\r
+BFD0293C 21D877E8 JALS prvNotifyQueueSetContainer\r
+BFD0293E 0C0021D8 LWC2 T6, 3072(T8)\r
+BFD02940 0C00 NOP\r
+BFD02942 0C62 MOVE V1, V0\r
+BFD02944 ED01 LI V0, 1\r
+BFD02946 002DB443 BNE V1, V0, 0xBFD029A4\r
+BFD02948 0C00002D SLL AT, T5, 1\r
+BFD0294A 0C00 NOP\r
1272: {\r
1273: /* The semaphore is a member of a queue set, and\r
1274: posting to the queue set caused a higher priority\r
1275: task to unblock. A context switch is required. */\r
1276: if( pxHigherPriorityTaskWoken != NULL )\r
-BFD0294C 002CFC5E LW V0, 44(S8)
-BFD02950 002840E2 BEQZC V0, 0xBFD029A4
+BFD0294C 002CFC5E LW V0, 44(S8)\r
+BFD02950 002840E2 BEQZC V0, 0xBFD029A4\r
1277: {\r
1278: *pxHigherPriorityTaskWoken = pdTRUE;\r
-BFD02954 002CFC5E LW V0, 44(S8)
-BFD02958 ED81 LI V1, 1
-BFD0295A E9A0 SW V1, 0(V0)
-BFD0295C CC23 B 0xBFD029A4
-BFD0295E 0C00 NOP
+BFD02954 002CFC5E LW V0, 44(S8)\r
+BFD02958 ED81 LI V1, 1\r
+BFD0295A E9A0 SW V1, 0(V0)\r
+BFD0295C CC23 B 0xBFD029A4\r
+BFD0295E 0C00 NOP\r
1279: }\r
1280: else\r
1281: {\r
1290: else\r
1291: {\r
1292: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
-BFD02960 0014FC5E LW V0, 20(S8)
-BFD02964 6929 LW V0, 36(V0)
-BFD02966 001D40E2 BEQZC V0, 0xBFD029A4
+BFD02960 0014FC5E LW V0, 20(S8)\r
+BFD02964 6929 LW V0, 36(V0)\r
+BFD02966 001D40E2 BEQZC V0, 0xBFD029A4\r
1293: {\r
1294: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
-BFD0296A 0014FC5E LW V0, 20(S8)
-BFD0296E 00243042 ADDIU V0, V0, 36
-BFD02972 0C82 MOVE A0, V0
-BFD02974 22BC77E8 JALS xTaskRemoveFromEventList
-BFD02976 0C0022BC LWC2 S5, 3072(GP)
-BFD02978 0C00 NOP
-BFD0297A 001340E2 BEQZC V0, 0xBFD029A4
+BFD0296A 0014FC5E LW V0, 20(S8)\r
+BFD0296E 00243042 ADDIU V0, V0, 36\r
+BFD02972 0C82 MOVE A0, V0\r
+BFD02974 22BC77E8 JALS xTaskRemoveFromEventList\r
+BFD02976 0C0022BC LWC2 S5, 3072(GP)\r
+BFD02978 0C00 NOP\r
+BFD0297A 001340E2 BEQZC V0, 0xBFD029A4\r
1295: {\r
1296: /* The task waiting has a higher priority so\r
1297: record that a context switch is required. */\r
1298: if( pxHigherPriorityTaskWoken != NULL )\r
-BFD0297E 002CFC5E LW V0, 44(S8)
-BFD02982 000F40E2 BEQZC V0, 0xBFD029A4
+BFD0297E 002CFC5E LW V0, 44(S8)\r
+BFD02982 000F40E2 BEQZC V0, 0xBFD029A4\r
1299: {\r
1300: *pxHigherPriorityTaskWoken = pdTRUE;\r
-BFD02986 002CFC5E LW V0, 44(S8)
-BFD0298A ED81 LI V1, 1
-BFD0298C E9A0 SW V1, 0(V0)
-BFD0298E CC0A B 0xBFD029A4
-BFD02990 0C00 NOP
+BFD02986 002CFC5E LW V0, 44(S8)\r
+BFD0298A ED81 LI V1, 1\r
+BFD0298C E9A0 SW V1, 0(V0)\r
+BFD0298E CC0A B 0xBFD029A4\r
+BFD02990 0C00 NOP\r
1301: }\r
1302: else\r
1303: {\r
1349: /* Increment the lock count so the task that unlocks the queue\r
1350: knows that data was posted while it was locked. */\r
1351: ++( pxQueue->xTxLock );\r
-BFD02992 0014FC5E LW V0, 20(S8)
-BFD02996 0048FC42 LW V0, 72(V0)
-BFD0299A 6DA0 ADDIU V1, V0, 1
-BFD0299C 0014FC5E LW V0, 20(S8)
-BFD029A0 0048F862 SW V1, 72(V0)
+BFD02992 0014FC5E LW V0, 20(S8)\r
+BFD02996 0048FC42 LW V0, 72(V0)\r
+BFD0299A 6DA0 ADDIU V1, V0, 1\r
+BFD0299C 0014FC5E LW V0, 20(S8)\r
+BFD029A0 0048F862 SW V1, 72(V0)\r
1352: }\r
1353: \r
1354: xReturn = pdPASS;\r
-BFD029A4 ED01 LI V0, 1
-BFD029A6 0010F85E SW V0, 16(S8)
-BFD029AA CC03 B 0xBFD029B2
-BFD029AC 0C00 NOP
+BFD029A4 ED01 LI V0, 1\r
+BFD029A6 0010F85E SW V0, 16(S8)\r
+BFD029AA CC03 B 0xBFD029B2\r
+BFD029AC 0C00 NOP\r
1355: }\r
1356: else\r
1357: {\r
1358: traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );\r
1359: xReturn = errQUEUE_FULL;\r
-BFD029AE 0010F81E SW ZERO, 16(S8)
+BFD029AE 0010F81E SW ZERO, 16(S8)\r
1360: }\r
1361: }\r
1362: portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r
-BFD029B2 0018FC9E LW A0, 24(S8)
-BFD029B6 4D5E77E8 JALS vPortClearInterruptMaskFromISR
-BFD029B8 4D5E ADDIU T2, T2, -1
-BFD029BA 0C00 NOP
+BFD029B2 0018FC9E LW A0, 24(S8)\r
+BFD029B6 4D5E77E8 JALS vPortClearInterruptMaskFromISR\r
+BFD029B8 4D5E ADDIU T2, T2, -1\r
+BFD029BA 0C00 NOP\r
1363: \r
1364: return xReturn;\r
-BFD029BC 0010FC5E LW V0, 16(S8)
+BFD029BC 0010FC5E LW V0, 16(S8)\r
1365: }\r
-BFD029C0 0FBE MOVE SP, S8
-BFD029C2 4BE9 LW RA, 36(SP)
-BFD029C4 4BC8 LW S8, 32(SP)
-BFD029C6 4C15 ADDIU SP, SP, 40
-BFD029C8 459F JR16 RA
-BFD029CA 0C00 NOP
+BFD029C0 0FBE MOVE SP, S8\r
+BFD029C2 4BE9 LW RA, 36(SP)\r
+BFD029C4 4BC8 LW S8, 32(SP)\r
+BFD029C6 4C15 ADDIU SP, SP, 40\r
+BFD029C8 459F JR16 RA\r
+BFD029CA 0C00 NOP\r
1366: /*-----------------------------------------------------------*/\r
1367: \r
1368: BaseType_t xQueueGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, const BaseType_t xJustPeeking )\r
1369: {\r
-BFD0103C 4FE5 ADDIU SP, SP, -56
-BFD0103E CBED SW RA, 52(SP)
-BFD01040 CBCC SW S8, 48(SP)
-BFD01042 0FDD MOVE S8, SP
-BFD01044 0038F89E SW A0, 56(S8)
-BFD01048 003CF8BE SW A1, 60(S8)
-BFD0104C 0040F8DE SW A2, 64(S8)
-BFD01050 0044F8FE SW A3, 68(S8)
+BFD0103C 4FE5 ADDIU SP, SP, -56\r
+BFD0103E CBED SW RA, 52(SP)\r
+BFD01040 CBCC SW S8, 48(SP)\r
+BFD01042 0FDD MOVE S8, SP\r
+BFD01044 0038F89E SW A0, 56(S8)\r
+BFD01048 003CF8BE SW A1, 60(S8)\r
+BFD0104C 0040F8DE SW A2, 64(S8)\r
+BFD01050 0044F8FE SW A3, 68(S8)\r
1370: BaseType_t xEntryTimeSet = pdFALSE;\r
-BFD01054 0010F81E SW ZERO, 16(S8)
+BFD01054 0010F81E SW ZERO, 16(S8)\r
1371: TimeOut_t xTimeOut;\r
1372: int8_t *pcOriginalReadPosition;\r
1373: Queue_t * const pxQueue = ( Queue_t * ) xQueue;\r
-BFD01058 0038FC5E LW V0, 56(S8)
-BFD0105C 0014F85E SW V0, 20(S8)
+BFD01058 0038FC5E LW V0, 56(S8)\r
+BFD0105C 0014F85E SW V0, 20(S8)\r
1374: \r
1375: configASSERT( pxQueue );\r
-BFD01060 0014FC5E LW V0, 20(S8)
-BFD01064 000940A2 BNEZC V0, 0xBFD0107A
-BFD01068 BFD141A2 LUI V0, 0xBFD1
-BFD0106A 3082BFD1 LDC1 F30, 12418(S1)
-BFD0106C 9E3C3082 ADDIU A0, V0, -25028
-BFD0106E 30A09E3C LWC1 F17, 12448(GP)
-BFD01070 055F30A0 ADDIU A1, ZERO, 1375
-BFD01072 055F SUBU V0, A3, A1
-BFD01074 4B7E77E8 JALS vAssertCalled
-BFD01076 4B7E LW K1, 120(SP)
-BFD01078 0C00 NOP
+BFD01060 0014FC5E LW V0, 20(S8)\r
+BFD01064 000940A2 BNEZC V0, 0xBFD0107A\r
+BFD01068 BFD141A2 LUI V0, 0xBFD1\r
+BFD0106A 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD0106C 9E3C3082 ADDIU A0, V0, -25028\r
+BFD0106E 30A09E3C LWC1 F17, 12448(GP)\r
+BFD01070 055F30A0 ADDIU A1, ZERO, 1375\r
+BFD01072 055F SUBU V0, A3, A1\r
+BFD01074 4B7E77E8 JALS vAssertCalled\r
+BFD01076 4B7E LW K1, 120(SP)\r
+BFD01078 0C00 NOP\r
1376: configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\r
-BFD0107A 003CFC5E LW V0, 60(S8)
-BFD0107E 000640A2 BNEZC V0, 0xBFD0108E
-BFD01082 0014FC5E LW V0, 20(S8)
-BFD01086 0040FC42 LW V0, 64(V0)
-BFD0108A 000340A2 BNEZC V0, 0xBFD01094
-BFD0108E ED01 LI V0, 1
-BFD01090 CC02 B 0xBFD01096
-BFD01092 0C00 NOP
-BFD01094 0C40 MOVE V0, ZERO
-BFD01096 000940A2 BNEZC V0, 0xBFD010AC
-BFD0109A BFD141A2 LUI V0, 0xBFD1
-BFD0109C 3082BFD1 LDC1 F30, 12418(S1)
-BFD0109E 9E3C3082 ADDIU A0, V0, -25028
-BFD010A0 30A09E3C LWC1 F17, 12448(GP)
-BFD010A2 056030A0 ADDIU A1, ZERO, 1376
-BFD010A4 0560 ADDU V0, S0, A2
-BFD010A6 4B7E77E8 JALS vAssertCalled
-BFD010A8 4B7E LW K1, 120(SP)
-BFD010AA 0C00 NOP
+BFD0107A 003CFC5E LW V0, 60(S8)\r
+BFD0107E 000640A2 BNEZC V0, 0xBFD0108E\r
+BFD01082 0014FC5E LW V0, 20(S8)\r
+BFD01086 0040FC42 LW V0, 64(V0)\r
+BFD0108A 000340A2 BNEZC V0, 0xBFD01094\r
+BFD0108E ED01 LI V0, 1\r
+BFD01090 CC02 B 0xBFD01096\r
+BFD01092 0C00 NOP\r
+BFD01094 0C40 MOVE V0, ZERO\r
+BFD01096 000940A2 BNEZC V0, 0xBFD010AC\r
+BFD0109A BFD141A2 LUI V0, 0xBFD1\r
+BFD0109C 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD0109E 9E3C3082 ADDIU A0, V0, -25028\r
+BFD010A0 30A09E3C LWC1 F17, 12448(GP)\r
+BFD010A2 056030A0 ADDIU A1, ZERO, 1376\r
+BFD010A4 0560 ADDU V0, S0, A2\r
+BFD010A6 4B7E77E8 JALS vAssertCalled\r
+BFD010A8 4B7E LW K1, 120(SP)\r
+BFD010AA 0C00 NOP\r
1377: #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\r
1378: {\r
1379: configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\r
-BFD010AC 4A8E77E8 JALS xTaskGetSchedulerState
-BFD010AE 4A8E LW S4, 56(SP)
-BFD010B0 0C00 NOP
-BFD010B2 000440A2 BNEZC V0, 0xBFD010BE
-BFD010B6 0040FC5E LW V0, 64(S8)
-BFD010BA 000340A2 BNEZC V0, 0xBFD010C4
-BFD010BE ED01 LI V0, 1
-BFD010C0 CC02 B 0xBFD010C6
-BFD010C2 0C00 NOP
-BFD010C4 0C40 MOVE V0, ZERO
-BFD010C6 000C40A2 BNEZC V0, 0xBFD010E2
-BFD010CA BFD141A2 LUI V0, 0xBFD1
-BFD010CC 3082BFD1 LDC1 F30, 12418(S1)
-BFD010CE 9E3C3082 ADDIU A0, V0, -25028
-BFD010D0 30A09E3C LWC1 F17, 12448(GP)
-BFD010D2 056330A0 ADDIU A1, ZERO, 1379
-BFD010D4 0563 SUBU V0, S1, A2
-BFD010D6 4B7E77E8 JALS vAssertCalled
-BFD010D8 4B7E LW K1, 120(SP)
-BFD010DA 0C00 NOP
-BFD010DC CC02 B 0xBFD010E2
-BFD010DE 0C00 NOP
+BFD010AC 4A8E77E8 JALS xTaskGetSchedulerState\r
+BFD010AE 4A8E LW S4, 56(SP)\r
+BFD010B0 0C00 NOP\r
+BFD010B2 000440A2 BNEZC V0, 0xBFD010BE\r
+BFD010B6 0040FC5E LW V0, 64(S8)\r
+BFD010BA 000340A2 BNEZC V0, 0xBFD010C4\r
+BFD010BE ED01 LI V0, 1\r
+BFD010C0 CC02 B 0xBFD010C6\r
+BFD010C2 0C00 NOP\r
+BFD010C4 0C40 MOVE V0, ZERO\r
+BFD010C6 000C40A2 BNEZC V0, 0xBFD010E2\r
+BFD010CA BFD141A2 LUI V0, 0xBFD1\r
+BFD010CC 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD010CE 9E3C3082 ADDIU A0, V0, -25028\r
+BFD010D0 30A09E3C LWC1 F17, 12448(GP)\r
+BFD010D2 056330A0 ADDIU A1, ZERO, 1379\r
+BFD010D4 0563 SUBU V0, S1, A2\r
+BFD010D6 4B7E77E8 JALS vAssertCalled\r
+BFD010D8 4B7E LW K1, 120(SP)\r
+BFD010DA 0C00 NOP\r
+BFD010DC CC02 B 0xBFD010E2\r
+BFD010DE 0C00 NOP\r
1380: }\r
1381: #endif\r
1382: \r
1387: for( ;; )\r
1388: {\r
1389: taskENTER_CRITICAL();\r
-BFD010E2 33B877E8 JALS vTaskEnterCritical
-BFD010E4 0C0033B8 ADDIU SP, T8, 3072
-BFD010E6 0C00 NOP
+BFD010E2 33B877E8 JALS vTaskEnterCritical\r
+BFD010E4 0C0033B8 ADDIU SP, T8, 3072\r
+BFD010E6 0C00 NOP\r
1390: {\r
1391: /* Is there data in the queue now? To be running the calling task\r
1392: must be the highest priority task wanting to access the queue. */\r
1393: if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )\r
-BFD010E8 0014FC5E LW V0, 20(S8)
-BFD010EC 692E LW V0, 56(V0)
-BFD010EE 007040E2 BEQZC V0, 0xBFD011D2
+BFD010E8 0014FC5E LW V0, 20(S8)\r
+BFD010EC 692E LW V0, 56(V0)\r
+BFD010EE 007040E2 BEQZC V0, 0xBFD011D2\r
1394: {\r
1395: /* Remember the read position in case the queue is only being\r
1396: peeked. */\r
1397: pcOriginalReadPosition = pxQueue->u.pcReadFrom;\r
-BFD010F2 0014FC5E LW V0, 20(S8)
-BFD010F6 6923 LW V0, 12(V0)
-BFD010F8 0018F85E SW V0, 24(S8)
+BFD010F2 0014FC5E LW V0, 20(S8)\r
+BFD010F6 6923 LW V0, 12(V0)\r
+BFD010F8 0018F85E SW V0, 24(S8)\r
1398: \r
1399: prvCopyDataFromQueue( pxQueue, pvBuffer );\r
-BFD010FC 0014FC9E LW A0, 20(S8)
-BFD01100 003CFCBE LW A1, 60(S8)
-BFD01104 367A77E8 JALS prvCopyDataFromQueue
-BFD01106 0C00367A LHU S3, 3072(K0)
-BFD01108 0C00 NOP
+BFD010FC 0014FC9E LW A0, 20(S8)\r
+BFD01100 003CFCBE LW A1, 60(S8)\r
+BFD01104 367A77E8 JALS prvCopyDataFromQueue\r
+BFD01106 0C00367A LHU S3, 3072(K0)\r
+BFD01108 0C00 NOP\r
1400: \r
1401: if( xJustPeeking == pdFALSE )\r
-BFD0110A 0044FC5E LW V0, 68(S8)
-BFD0110E 003640A2 BNEZC V0, 0xBFD0117E
+BFD0110A 0044FC5E LW V0, 68(S8)\r
+BFD0110E 003640A2 BNEZC V0, 0xBFD0117E\r
1402: {\r
1403: traceQUEUE_RECEIVE( pxQueue );\r
1404: \r
1405: /* Actually removing data, not just peeking. */\r
1406: --( pxQueue->uxMessagesWaiting );\r
-BFD01112 0014FC5E LW V0, 20(S8)
-BFD01116 692E LW V0, 56(V0)
-BFD01118 6DAE ADDIU V1, V0, -1
-BFD0111A 0014FC5E LW V0, 20(S8)
-BFD0111E E9AE SW V1, 56(V0)
+BFD01112 0014FC5E LW V0, 20(S8)\r
+BFD01116 692E LW V0, 56(V0)\r
+BFD01118 6DAE ADDIU V1, V0, -1\r
+BFD0111A 0014FC5E LW V0, 20(S8)\r
+BFD0111E E9AE SW V1, 56(V0)\r
1407: \r
1408: #if ( configUSE_MUTEXES == 1 )\r
1409: {\r
1410: if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\r
-BFD01120 0014FC5E LW V0, 20(S8)
-BFD01124 6920 LW V0, 0(V0)
-BFD01126 000740A2 BNEZC V0, 0xBFD01138
+BFD01120 0014FC5E LW V0, 20(S8)\r
+BFD01124 6920 LW V0, 0(V0)\r
+BFD01126 000740A2 BNEZC V0, 0xBFD01138\r
1411: {\r
1412: /* Record the information required to implement\r
1413: priority inheritance should it become necessary. */\r
1414: pxQueue->pxMutexHolder = ( int8_t * ) pvTaskIncrementMutexHeldCount(); /*lint !e961 Cast is not redundant as TaskHandle_t is a typedef. */\r
-BFD0112A 4CE077E8 JALS pvTaskIncrementMutexHeldCount
-BFD0112C 4CE0 ADDIU A3, A3, 0
-BFD0112E 0C00 NOP
-BFD01130 0C62 MOVE V1, V0
-BFD01132 0014FC5E LW V0, 20(S8)
-BFD01136 E9A1 SW V1, 4(V0)
+BFD0112A 4CE077E8 JALS pvTaskIncrementMutexHeldCount\r
+BFD0112C 4CE0 ADDIU A3, A3, 0\r
+BFD0112E 0C00 NOP\r
+BFD01130 0C62 MOVE V1, V0\r
+BFD01132 0014FC5E LW V0, 20(S8)\r
+BFD01136 E9A1 SW V1, 4(V0)\r
1415: }\r
1416: else\r
1417: {\r
1421: #endif /* configUSE_MUTEXES */\r
1422: \r
1423: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r
-BFD01138 0014FC5E LW V0, 20(S8)
-BFD0113C 6924 LW V0, 16(V0)
-BFD0113E 004240E2 BEQZC V0, 0xBFD011C6
+BFD01138 0014FC5E LW V0, 20(S8)\r
+BFD0113C 6924 LW V0, 16(V0)\r
+BFD0113E 004240E2 BEQZC V0, 0xBFD011C6\r
1424: {\r
1425: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) == pdTRUE )\r
-BFD01142 0014FC5E LW V0, 20(S8)
-BFD01146 6D28 ADDIU V0, V0, 16
-BFD01148 0C82 MOVE A0, V0
-BFD0114A 22BC77E8 JALS xTaskRemoveFromEventList
-BFD0114C 0C0022BC LWC2 S5, 3072(GP)
-BFD0114E 0C00 NOP
-BFD01150 0C62 MOVE V1, V0
-BFD01152 ED01 LI V0, 1
-BFD01154 0037B443 BNE V1, V0, 0xBFD011C6
-BFD01156 0C000037 SLL AT, S7, 1
-BFD01158 0C00 NOP
+BFD01142 0014FC5E LW V0, 20(S8)\r
+BFD01146 6D28 ADDIU V0, V0, 16\r
+BFD01148 0C82 MOVE A0, V0\r
+BFD0114A 22BC77E8 JALS xTaskRemoveFromEventList\r
+BFD0114C 0C0022BC LWC2 S5, 3072(GP)\r
+BFD0114E 0C00 NOP\r
+BFD01150 0C62 MOVE V1, V0\r
+BFD01152 ED01 LI V0, 1\r
+BFD01154 0037B443 BNE V1, V0, 0xBFD011C6\r
+BFD01156 0C000037 SLL AT, S7, 1\r
+BFD01158 0C00 NOP\r
1426: {\r
1427: queueYIELD_IF_USING_PREEMPTION();\r
-BFD0115A 4E1677E8 JALS ulPortGetCP0Cause
-BFD0115C 4E16 ADDIU S0, S0, -5
-BFD0115E 0C00 NOP
-BFD01160 001CF85E SW V0, 28(S8)
-BFD01164 001CFC5E LW V0, 28(S8)
-BFD01168 01005042 ORI V0, V0, 256
-BFD0116C 001CF85E SW V0, 28(S8)
-BFD01170 001CFC9E LW A0, 28(S8)
-BFD01174 4E2677E8 JALS vPortSetCP0Cause
-BFD01176 4E26 ADDIU S1, S1, 3
-BFD01178 0C00 NOP
-BFD0117A CC25 B 0xBFD011C6
-BFD0117C 0C00 NOP
+BFD0115A 4E1677E8 JALS ulPortGetCP0Cause\r
+BFD0115C 4E16 ADDIU S0, S0, -5\r
+BFD0115E 0C00 NOP\r
+BFD01160 001CF85E SW V0, 28(S8)\r
+BFD01164 001CFC5E LW V0, 28(S8)\r
+BFD01168 01005042 ORI V0, V0, 256\r
+BFD0116C 001CF85E SW V0, 28(S8)\r
+BFD01170 001CFC9E LW A0, 28(S8)\r
+BFD01174 4E2677E8 JALS vPortSetCP0Cause\r
+BFD01176 4E26 ADDIU S1, S1, 3\r
+BFD01178 0C00 NOP\r
+BFD0117A CC25 B 0xBFD011C6\r
+BFD0117C 0C00 NOP\r
1428: }\r
1429: else\r
1430: {\r
1443: /* The data is not being removed, so reset the read\r
1444: pointer. */\r
1445: pxQueue->u.pcReadFrom = pcOriginalReadPosition;\r
-BFD0117E 0014FC5E LW V0, 20(S8)
-BFD01182 0018FC7E LW V1, 24(S8)
-BFD01186 E9A3 SW V1, 12(V0)
+BFD0117E 0014FC5E LW V0, 20(S8)\r
+BFD01182 0018FC7E LW V1, 24(S8)\r
+BFD01186 E9A3 SW V1, 12(V0)\r
1446: \r
1447: /* The data is being left in the queue, so see if there are\r
1448: any other tasks waiting for the data. */\r
1449: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
-BFD01188 0014FC5E LW V0, 20(S8)
-BFD0118C 6929 LW V0, 36(V0)
-BFD0118E 001A40E2 BEQZC V0, 0xBFD011C6
+BFD01188 0014FC5E LW V0, 20(S8)\r
+BFD0118C 6929 LW V0, 36(V0)\r
+BFD0118E 001A40E2 BEQZC V0, 0xBFD011C6\r
1450: {\r
1451: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
-BFD01192 0014FC5E LW V0, 20(S8)
-BFD01196 00243042 ADDIU V0, V0, 36
-BFD0119A 0C82 MOVE A0, V0
-BFD0119C 22BC77E8 JALS xTaskRemoveFromEventList
-BFD0119E 0C0022BC LWC2 S5, 3072(GP)
-BFD011A0 0C00 NOP
-BFD011A2 001040E2 BEQZC V0, 0xBFD011C6
+BFD01192 0014FC5E LW V0, 20(S8)\r
+BFD01196 00243042 ADDIU V0, V0, 36\r
+BFD0119A 0C82 MOVE A0, V0\r
+BFD0119C 22BC77E8 JALS xTaskRemoveFromEventList\r
+BFD0119E 0C0022BC LWC2 S5, 3072(GP)\r
+BFD011A0 0C00 NOP\r
+BFD011A2 001040E2 BEQZC V0, 0xBFD011C6\r
1452: {\r
1453: /* The task waiting has a higher priority than this task. */\r
1454: queueYIELD_IF_USING_PREEMPTION();\r
-BFD011A6 4E1677E8 JALS ulPortGetCP0Cause
-BFD011A8 4E16 ADDIU S0, S0, -5
-BFD011AA 0C00 NOP
-BFD011AC 0020F85E SW V0, 32(S8)
-BFD011B0 0020FC5E LW V0, 32(S8)
-BFD011B4 01005042 ORI V0, V0, 256
-BFD011B8 0020F85E SW V0, 32(S8)
-BFD011BC 0020FC9E LW A0, 32(S8)
-BFD011C0 4E2677E8 JALS vPortSetCP0Cause
-BFD011C2 4E26 ADDIU S1, S1, 3
-BFD011C4 0C00 NOP
+BFD011A6 4E1677E8 JALS ulPortGetCP0Cause\r
+BFD011A8 4E16 ADDIU S0, S0, -5\r
+BFD011AA 0C00 NOP\r
+BFD011AC 0020F85E SW V0, 32(S8)\r
+BFD011B0 0020FC5E LW V0, 32(S8)\r
+BFD011B4 01005042 ORI V0, V0, 256\r
+BFD011B8 0020F85E SW V0, 32(S8)\r
+BFD011BC 0020FC9E LW A0, 32(S8)\r
+BFD011C0 4E2677E8 JALS vPortSetCP0Cause\r
+BFD011C2 4E26 ADDIU S1, S1, 3\r
+BFD011C4 0C00 NOP\r
1455: }\r
1456: else\r
1457: {\r
1465: }\r
1466: \r
1467: taskEXIT_CRITICAL();\r
-BFD011C6 40AA77E8 JALS vTaskExitCritical
-BFD011C8 0C0040AA BNEZC T2, prvCopyDataToQueue
-BFD011CA 0C00 NOP
+BFD011C6 40AA77E8 JALS vTaskExitCritical\r
+BFD011C8 0C0040AA BNEZC T2, prvCopyDataToQueue\r
+BFD011CA 0C00 NOP\r
1468: return pdPASS;\r
-BFD011CC ED01 LI V0, 1
-BFD011CE CC9A B 0xBFD01304
-BFD011D0 0C00 NOP
+BFD011CC ED01 LI V0, 1\r
+BFD011CE CC9A B 0xBFD01304\r
+BFD011D0 0C00 NOP\r
1469: }\r
1470: else\r
1471: {\r
1472: if( xTicksToWait == ( TickType_t ) 0 )\r
-BFD011D2 0040FC5E LW V0, 64(S8)
-BFD011D6 000640A2 BNEZC V0, 0xBFD011E6
+BFD011D2 0040FC5E LW V0, 64(S8)\r
+BFD011D6 000640A2 BNEZC V0, 0xBFD011E6\r
1473: {\r
1474: /* The queue was empty and no block time is specified (or\r
1475: the block time has expired) so leave now. */\r
1476: taskEXIT_CRITICAL();\r
-BFD011DA 40AA77E8 JALS vTaskExitCritical
-BFD011DC 0C0040AA BNEZC T2, 0xBFD029E0
-BFD011DE 0C00 NOP
+BFD011DA 40AA77E8 JALS vTaskExitCritical\r
+BFD011DC 0C0040AA BNEZC T2, 0xBFD029E0\r
+BFD011DE 0C00 NOP\r
1477: traceQUEUE_RECEIVE_FAILED( pxQueue );\r
1478: return errQUEUE_EMPTY;\r
-BFD011E0 0C40 MOVE V0, ZERO
-BFD011E2 CC90 B 0xBFD01304
-BFD011E4 0C00 NOP
+BFD011E0 0C40 MOVE V0, ZERO\r
+BFD011E2 CC90 B 0xBFD01304\r
+BFD011E4 0C00 NOP\r
1479: }\r
1480: else if( xEntryTimeSet == pdFALSE )\r
-BFD011E6 0010FC5E LW V0, 16(S8)
-BFD011EA 000940A2 BNEZC V0, 0xBFD01200
+BFD011E6 0010FC5E LW V0, 16(S8)\r
+BFD011EA 000940A2 BNEZC V0, 0xBFD01200\r
1481: {\r
1482: /* The queue was empty and a block time was specified so\r
1483: configure the timeout structure. */\r
1484: vTaskSetTimeOutState( &xTimeOut );\r
-BFD011EE 0028305E ADDIU V0, S8, 40
-BFD011F2 0C82 MOVE A0, V0
-BFD011F4 47A677E8 JALS vTaskSetTimeOutState
-BFD011F8 0C00 NOP
+BFD011EE 0028305E ADDIU V0, S8, 40\r
+BFD011F2 0C82 MOVE A0, V0\r
+BFD011F4 47A677E8 JALS vTaskSetTimeOutState\r
+BFD011F8 0C00 NOP\r
1485: xEntryTimeSet = pdTRUE;\r
-BFD011FA ED01 LI V0, 1
-BFD011FC 0010F85E SW V0, 16(S8)
+BFD011FA ED01 LI V0, 1\r
+BFD011FC 0010F85E SW V0, 16(S8)\r
1486: }\r
1487: else\r
1488: {\r
1492: }\r
1493: }\r
1494: taskEXIT_CRITICAL();\r
-BFD01200 40AA77E8 JALS vTaskExitCritical
-BFD01202 0C0040AA BNEZC T2, 0xBFD02A06
-BFD01204 0C00 NOP
+BFD01200 40AA77E8 JALS vTaskExitCritical\r
+BFD01202 0C0040AA BNEZC T2, 0xBFD02A06\r
+BFD01204 0C00 NOP\r
1495: \r
1496: /* Interrupts and other tasks can send to and receive from the queue\r
1497: now the critical section has been exited. */\r
1498: \r
1499: vTaskSuspendAll();\r
-BFD01206 4EF477E8 JALS vTaskSuspendAll
-BFD01208 4EF4 ADDIU S7, S7, -6
-BFD0120A 0C00 NOP
+BFD01206 4EF477E8 JALS vTaskSuspendAll\r
+BFD01208 4EF4 ADDIU S7, S7, -6\r
+BFD0120A 0C00 NOP\r
1500: prvLockQueue( pxQueue );\r
-BFD0120C 33B877E8 JALS vTaskEnterCritical
-BFD0120E 0C0033B8 ADDIU SP, T8, 3072
-BFD01210 0C00 NOP
-BFD01212 0014FC5E LW V0, 20(S8)
-BFD01216 0044FC62 LW V1, 68(V0)
-BFD0121A ED7F LI V0, -1
-BFD0121C 0005B443 BNE V1, V0, 0xBFD0122A
-BFD0121E 0C000005 SLL ZERO, A1, 1
-BFD01220 0C00 NOP
-BFD01222 0014FC5E LW V0, 20(S8)
-BFD01226 0044F802 SW ZERO, 68(V0)
-BFD0122A 0014FC5E LW V0, 20(S8)
-BFD0122E 0048FC62 LW V1, 72(V0)
-BFD01232 ED7F LI V0, -1
-BFD01234 0005B443 BNE V1, V0, 0xBFD01242
-BFD01236 0C000005 SLL ZERO, A1, 1
-BFD01238 0C00 NOP
-BFD0123A 0014FC5E LW V0, 20(S8)
-BFD0123E 0048F802 SW ZERO, 72(V0)
-BFD01242 40AA77E8 JALS vTaskExitCritical
-BFD01244 0C0040AA BNEZC T2, 0xBFD02A48
-BFD01246 0C00 NOP
+BFD0120C 33B877E8 JALS vTaskEnterCritical\r
+BFD0120E 0C0033B8 ADDIU SP, T8, 3072\r
+BFD01210 0C00 NOP\r
+BFD01212 0014FC5E LW V0, 20(S8)\r
+BFD01216 0044FC62 LW V1, 68(V0)\r
+BFD0121A ED7F LI V0, -1\r
+BFD0121C 0005B443 BNE V1, V0, 0xBFD0122A\r
+BFD0121E 0C000005 SLL ZERO, A1, 1\r
+BFD01220 0C00 NOP\r
+BFD01222 0014FC5E LW V0, 20(S8)\r
+BFD01226 0044F802 SW ZERO, 68(V0)\r
+BFD0122A 0014FC5E LW V0, 20(S8)\r
+BFD0122E 0048FC62 LW V1, 72(V0)\r
+BFD01232 ED7F LI V0, -1\r
+BFD01234 0005B443 BNE V1, V0, 0xBFD01242\r
+BFD01236 0C000005 SLL ZERO, A1, 1\r
+BFD01238 0C00 NOP\r
+BFD0123A 0014FC5E LW V0, 20(S8)\r
+BFD0123E 0048F802 SW ZERO, 72(V0)\r
+BFD01242 40AA77E8 JALS vTaskExitCritical\r
+BFD01244 0C0040AA BNEZC T2, 0xBFD02A48\r
+BFD01246 0C00 NOP\r
1501: \r
1502: /* Update the timeout state to see if it has expired yet. */\r
1503: if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\r
-BFD01248 0028307E ADDIU V1, S8, 40
-BFD0124C 0040305E ADDIU V0, S8, 64
-BFD01250 0C83 MOVE A0, V1
-BFD01252 0CA2 MOVE A1, V0
-BFD01254 1FF677E8 JALS xTaskCheckForTimeOut
-BFD01256 0C001FF6 LB RA, 3072(S6)
-BFD01258 0C00 NOP
-BFD0125A 004A40A2 BNEZC V0, 0xBFD012F2
+BFD01248 0028307E ADDIU V1, S8, 40\r
+BFD0124C 0040305E ADDIU V0, S8, 64\r
+BFD01250 0C83 MOVE A0, V1\r
+BFD01252 0CA2 MOVE A1, V0\r
+BFD01254 1FF677E8 JALS xTaskCheckForTimeOut\r
+BFD01256 0C001FF6 LB RA, 3072(S6)\r
+BFD01258 0C00 NOP\r
+BFD0125A 004A40A2 BNEZC V0, 0xBFD012F2\r
1504: {\r
1505: if( prvIsQueueEmpty( pxQueue ) != pdFALSE )\r
-BFD0125E 0014FC9E LW A0, 20(S8)
-BFD01262 49D077E8 JALS prvIsQueueEmpty
-BFD01264 49D0 LW T6, 64(SP)
-BFD01266 0C00 NOP
-BFD01268 003940E2 BEQZC V0, 0xBFD012DE
+BFD0125E 0014FC9E LW A0, 20(S8)\r
+BFD01262 49D077E8 JALS prvIsQueueEmpty\r
+BFD01264 49D0 LW T6, 64(SP)\r
+BFD01266 0C00 NOP\r
+BFD01268 003940E2 BEQZC V0, 0xBFD012DE\r
1506: {\r
1507: traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );\r
1508: \r
1509: #if ( configUSE_MUTEXES == 1 )\r
1510: {\r
1511: if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\r
-BFD0126C 0014FC5E LW V0, 20(S8)
-BFD01270 6920 LW V0, 0(V0)
-BFD01272 000D40A2 BNEZC V0, 0xBFD01290
+BFD0126C 0014FC5E LW V0, 20(S8)\r
+BFD01270 6920 LW V0, 0(V0)\r
+BFD01272 000D40A2 BNEZC V0, 0xBFD01290\r
1512: {\r
1513: taskENTER_CRITICAL();\r
-BFD01276 33B877E8 JALS vTaskEnterCritical
-BFD01278 0C0033B8 ADDIU SP, T8, 3072
-BFD0127A 0C00 NOP
+BFD01276 33B877E8 JALS vTaskEnterCritical\r
+BFD01278 0C0033B8 ADDIU SP, T8, 3072\r
+BFD0127A 0C00 NOP\r
1514: {\r
1515: vTaskPriorityInherit( ( void * ) pxQueue->pxMutexHolder );\r
-BFD0127C 0014FC5E LW V0, 20(S8)
-BFD01280 6921 LW V0, 4(V0)
-BFD01282 0C82 MOVE A0, V0
-BFD01284 1A9077E8 JALS vTaskPriorityInherit
-BFD01286 0C001A90 SB S4, 3072(S0)
-BFD01288 0C00 NOP
+BFD0127C 0014FC5E LW V0, 20(S8)\r
+BFD01280 6921 LW V0, 4(V0)\r
+BFD01282 0C82 MOVE A0, V0\r
+BFD01284 1A9077E8 JALS vTaskPriorityInherit\r
+BFD01286 0C001A90 SB S4, 3072(S0)\r
+BFD01288 0C00 NOP\r
1516: }\r
1517: taskEXIT_CRITICAL();\r
-BFD0128A 40AA77E8 JALS vTaskExitCritical
-BFD0128C 0C0040AA BNEZC T2, 0xBFD02A90
-BFD0128E 0C00 NOP
+BFD0128A 40AA77E8 JALS vTaskExitCritical\r
+BFD0128C 0C0040AA BNEZC T2, 0xBFD02A90\r
+BFD0128E 0C00 NOP\r
1518: }\r
1519: else\r
1520: {\r
1524: #endif\r
1525: \r
1526: vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );\r
-BFD01290 0014FC5E LW V0, 20(S8)
-BFD01294 00243062 ADDIU V1, V0, 36
-BFD01298 0040FC5E LW V0, 64(S8)
-BFD0129C 0C83 MOVE A0, V1
-BFD0129E 0CA2 MOVE A1, V0
-BFD012A0 2F3A77E8 JALS vTaskPlaceOnEventList
-BFD012A2 2F3A ANDI A2, V1, 0x20
-BFD012A4 0C00 NOP
+BFD01290 0014FC5E LW V0, 20(S8)\r
+BFD01294 00243062 ADDIU V1, V0, 36\r
+BFD01298 0040FC5E LW V0, 64(S8)\r
+BFD0129C 0C83 MOVE A0, V1\r
+BFD0129E 0CA2 MOVE A1, V0\r
+BFD012A0 2F3A77E8 JALS vTaskPlaceOnEventList\r
+BFD012A2 2F3A ANDI A2, V1, 0x20\r
+BFD012A4 0C00 NOP\r
1527: prvUnlockQueue( pxQueue );\r
-BFD012A6 0014FC9E LW A0, 20(S8)
-BFD012AA 1DEE77E8 JALS prvUnlockQueue
-BFD012AC 0C001DEE LB T7, 3072(T6)
-BFD012AE 0C00 NOP
+BFD012A6 0014FC9E LW A0, 20(S8)\r
+BFD012AA 1DEE77E8 JALS prvUnlockQueue\r
+BFD012AC 0C001DEE LB T7, 3072(T6)\r
+BFD012AE 0C00 NOP\r
1528: if( xTaskResumeAll() == pdFALSE )\r
-BFD012B0 158E77E8 JALS xTaskResumeAll
-BFD012B2 0C00158E LBU T4, 3072(T6)
-BFD012B4 0C00 NOP
-BFD012B6 FF1340A2 BNEZC V0, 0xBFD010E0
-BFD012B8 77E8FF13 LW T8, 30696(S3)
+BFD012B0 158E77E8 JALS xTaskResumeAll\r
+BFD012B2 0C00158E LBU T4, 3072(T6)\r
+BFD012B4 0C00 NOP\r
+BFD012B6 FF1340A2 BNEZC V0, 0xBFD010E0\r
+BFD012B8 77E8FF13 LW T8, 30696(S3)\r
1529: {\r
1530: portYIELD_WITHIN_API();\r
-BFD012BA 4E1677E8 JALS ulPortGetCP0Cause
-BFD012BC 4E16 ADDIU S0, S0, -5
-BFD012BE 0C00 NOP
-BFD012C0 0024F85E SW V0, 36(S8)
-BFD012C4 0024FC5E LW V0, 36(S8)
-BFD012C8 01005042 ORI V0, V0, 256
-BFD012CC 0024F85E SW V0, 36(S8)
-BFD012D0 0024FC9E LW A0, 36(S8)
-BFD012D4 4E2677E8 JALS vPortSetCP0Cause
-BFD012D6 4E26 ADDIU S1, S1, 3
-BFD012D8 0C00 NOP
+BFD012BA 4E1677E8 JALS ulPortGetCP0Cause\r
+BFD012BC 4E16 ADDIU S0, S0, -5\r
+BFD012BE 0C00 NOP\r
+BFD012C0 0024F85E SW V0, 36(S8)\r
+BFD012C4 0024FC5E LW V0, 36(S8)\r
+BFD012C8 01005042 ORI V0, V0, 256\r
+BFD012CC 0024F85E SW V0, 36(S8)\r
+BFD012D0 0024FC9E LW A0, 36(S8)\r
+BFD012D4 4E2677E8 JALS vPortSetCP0Cause\r
+BFD012D6 4E26 ADDIU S1, S1, 3\r
+BFD012D8 0C00 NOP\r
1531: }\r
1532: else\r
1533: {\r
1538: {\r
1539: /* Try again. */\r
1540: prvUnlockQueue( pxQueue );\r
-BFD012DE 0014FC9E LW A0, 20(S8)
-BFD012E2 1DEE77E8 JALS prvUnlockQueue
-BFD012E4 0C001DEE LB T7, 3072(T6)
-BFD012E6 0C00 NOP
+BFD012DE 0014FC9E LW A0, 20(S8)\r
+BFD012E2 1DEE77E8 JALS prvUnlockQueue\r
+BFD012E4 0C001DEE LB T7, 3072(T6)\r
+BFD012E6 0C00 NOP\r
1541: ( void ) xTaskResumeAll();\r
-BFD012E8 158E77E8 JALS xTaskResumeAll
-BFD012EA 0C00158E LBU T4, 3072(T6)
-BFD012EC 0C00 NOP
+BFD012E8 158E77E8 JALS xTaskResumeAll\r
+BFD012EA 0C00158E LBU T4, 3072(T6)\r
+BFD012EC 0C00 NOP\r
1542: }\r
1543: }\r
1544: else\r
1545: {\r
1546: prvUnlockQueue( pxQueue );\r
-BFD012F2 0014FC9E LW A0, 20(S8)
-BFD012F6 1DEE77E8 JALS prvUnlockQueue
-BFD012F8 0C001DEE LB T7, 3072(T6)
-BFD012FA 0C00 NOP
+BFD012F2 0014FC9E LW A0, 20(S8)\r
+BFD012F6 1DEE77E8 JALS prvUnlockQueue\r
+BFD012F8 0C001DEE LB T7, 3072(T6)\r
+BFD012FA 0C00 NOP\r
1547: ( void ) xTaskResumeAll();\r
-BFD012FC 158E77E8 JALS xTaskResumeAll
-BFD012FE 0C00158E LBU T4, 3072(T6)
-BFD01300 0C00 NOP
+BFD012FC 158E77E8 JALS xTaskResumeAll\r
+BFD012FE 0C00158E LBU T4, 3072(T6)\r
+BFD01300 0C00 NOP\r
1548: traceQUEUE_RECEIVE_FAILED( pxQueue );\r
1549: return errQUEUE_EMPTY;\r
-BFD01302 0C40 MOVE V0, ZERO
+BFD01302 0C40 MOVE V0, ZERO\r
1550: }\r
1551: }\r
-BFD010E0 0C00 NOP
-BFD012DA CF03 B 0xBFD010E2
-BFD012DC 0C00 NOP
-BFD012EE CEF9 B 0xBFD010E2
-BFD012F0 0C00 NOP
+BFD010E0 0C00 NOP\r
+BFD012DA CF03 B 0xBFD010E2\r
+BFD012DC 0C00 NOP\r
+BFD012EE CEF9 B 0xBFD010E2\r
+BFD012F0 0C00 NOP\r
1552: }\r
-BFD01304 0FBE MOVE SP, S8
-BFD01306 4BED LW RA, 52(SP)
-BFD01308 4BCC LW S8, 48(SP)
-BFD0130A 4C1D ADDIU SP, SP, 56
-BFD0130C 459F JR16 RA
-BFD0130E 0C00 NOP
+BFD01304 0FBE MOVE SP, S8\r
+BFD01306 4BED LW RA, 52(SP)\r
+BFD01308 4BCC LW S8, 48(SP)\r
+BFD0130A 4C1D ADDIU SP, SP, 56\r
+BFD0130C 459F JR16 RA\r
+BFD0130E 0C00 NOP\r
1553: /*-----------------------------------------------------------*/\r
1554: \r
1555: BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )\r
1556: {\r
-BFD03AC8 4FED ADDIU SP, SP, -40
-BFD03ACA CBE9 SW RA, 36(SP)
-BFD03ACC CBC8 SW S8, 32(SP)
-BFD03ACE 0FDD MOVE S8, SP
-BFD03AD0 0028F89E SW A0, 40(S8)
-BFD03AD4 002CF8BE SW A1, 44(S8)
-BFD03AD8 0030F8DE SW A2, 48(S8)
+BFD03AC8 4FED ADDIU SP, SP, -40\r
+BFD03ACA CBE9 SW RA, 36(SP)\r
+BFD03ACC CBC8 SW S8, 32(SP)\r
+BFD03ACE 0FDD MOVE S8, SP\r
+BFD03AD0 0028F89E SW A0, 40(S8)\r
+BFD03AD4 002CF8BE SW A1, 44(S8)\r
+BFD03AD8 0030F8DE SW A2, 48(S8)\r
1557: BaseType_t xReturn;\r
1558: UBaseType_t uxSavedInterruptStatus;\r
1559: Queue_t * const pxQueue = ( Queue_t * ) xQueue;\r
-BFD03ADC 0028FC5E LW V0, 40(S8)
-BFD03AE0 0014F85E SW V0, 20(S8)
+BFD03ADC 0028FC5E LW V0, 40(S8)\r
+BFD03AE0 0014F85E SW V0, 20(S8)\r
1560: \r
1561: configASSERT( pxQueue );\r
-BFD03AE4 0014FC5E LW V0, 20(S8)
-BFD03AE8 000940A2 BNEZC V0, 0xBFD03AFE
-BFD03AEC BFD141A2 LUI V0, 0xBFD1
-BFD03AEE 3082BFD1 LDC1 F30, 12418(S1)
-BFD03AF0 9E3C3082 ADDIU A0, V0, -25028
-BFD03AF2 30A09E3C LWC1 F17, 12448(GP)
-BFD03AF4 061930A0 ADDIU A1, ZERO, 1561
-BFD03AF6 0619 SUBU A0, A0, S1
-BFD03AF8 4B7E77E8 JALS vAssertCalled
-BFD03AFA 4B7E LW K1, 120(SP)
-BFD03AFC 0C00 NOP
+BFD03AE4 0014FC5E LW V0, 20(S8)\r
+BFD03AE8 000940A2 BNEZC V0, 0xBFD03AFE\r
+BFD03AEC BFD141A2 LUI V0, 0xBFD1\r
+BFD03AEE 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD03AF0 9E3C3082 ADDIU A0, V0, -25028\r
+BFD03AF2 30A09E3C LWC1 F17, 12448(GP)\r
+BFD03AF4 061930A0 ADDIU A1, ZERO, 1561\r
+BFD03AF6 0619 SUBU A0, A0, S1\r
+BFD03AF8 4B7E77E8 JALS vAssertCalled\r
+BFD03AFA 4B7E LW K1, 120(SP)\r
+BFD03AFC 0C00 NOP\r
1562: configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\r
-BFD03AFE 002CFC5E LW V0, 44(S8)
-BFD03B02 000640A2 BNEZC V0, 0xBFD03B12
-BFD03B06 0014FC5E LW V0, 20(S8)
-BFD03B0A 0040FC42 LW V0, 64(V0)
-BFD03B0E 000340A2 BNEZC V0, 0xBFD03B18
-BFD03B12 ED01 LI V0, 1
-BFD03B14 CC02 B 0xBFD03B1A
-BFD03B16 0C00 NOP
-BFD03B18 0C40 MOVE V0, ZERO
-BFD03B1A 000940A2 BNEZC V0, 0xBFD03B30
-BFD03B1E BFD141A2 LUI V0, 0xBFD1
-BFD03B20 3082BFD1 LDC1 F30, 12418(S1)
-BFD03B22 9E3C3082 ADDIU A0, V0, -25028
-BFD03B24 30A09E3C LWC1 F17, 12448(GP)
-BFD03B26 061A30A0 ADDIU A1, ZERO, 1562
-BFD03B28 061A ADDU A0, A1, S1
-BFD03B2A 4B7E77E8 JALS vAssertCalled
-BFD03B2C 4B7E LW K1, 120(SP)
-BFD03B2E 0C00 NOP
+BFD03AFE 002CFC5E LW V0, 44(S8)\r
+BFD03B02 000640A2 BNEZC V0, 0xBFD03B12\r
+BFD03B06 0014FC5E LW V0, 20(S8)\r
+BFD03B0A 0040FC42 LW V0, 64(V0)\r
+BFD03B0E 000340A2 BNEZC V0, 0xBFD03B18\r
+BFD03B12 ED01 LI V0, 1\r
+BFD03B14 CC02 B 0xBFD03B1A\r
+BFD03B16 0C00 NOP\r
+BFD03B18 0C40 MOVE V0, ZERO\r
+BFD03B1A 000940A2 BNEZC V0, 0xBFD03B30\r
+BFD03B1E BFD141A2 LUI V0, 0xBFD1\r
+BFD03B20 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD03B22 9E3C3082 ADDIU A0, V0, -25028\r
+BFD03B24 30A09E3C LWC1 F17, 12448(GP)\r
+BFD03B26 061A30A0 ADDIU A1, ZERO, 1562\r
+BFD03B28 061A ADDU A0, A1, S1\r
+BFD03B2A 4B7E77E8 JALS vAssertCalled\r
+BFD03B2C 4B7E LW K1, 120(SP)\r
+BFD03B2E 0C00 NOP\r
1563: \r
1564: /* RTOS ports that support interrupt nesting have the concept of a maximum\r
1565: system call (or maximum API call) interrupt priority. Interrupts that are\r
1578: portASSERT_IF_INTERRUPT_PRIORITY_INVALID();\r
1579: \r
1580: uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r
-BFD03B30 475E77E8 JALS uxPortSetInterruptMaskFromISR
-BFD03B34 0C00 NOP
-BFD03B36 0018F85E SW V0, 24(S8)
+BFD03B30 475E77E8 JALS uxPortSetInterruptMaskFromISR\r
+BFD03B34 0C00 NOP\r
+BFD03B36 0018F85E SW V0, 24(S8)\r
1581: {\r
1582: /* Cannot block in an ISR, so check there is data available. */\r
1583: if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )\r
-BFD03B3A 0014FC5E LW V0, 20(S8)
-BFD03B3E 692E LW V0, 56(V0)
-BFD03B40 003C40E2 BEQZC V0, 0xBFD03BBC
+BFD03B3A 0014FC5E LW V0, 20(S8)\r
+BFD03B3E 692E LW V0, 56(V0)\r
+BFD03B40 003C40E2 BEQZC V0, 0xBFD03BBC\r
1584: {\r
1585: traceQUEUE_RECEIVE_FROM_ISR( pxQueue );\r
1586: \r
1587: prvCopyDataFromQueue( pxQueue, pvBuffer );\r
-BFD03B44 0014FC9E LW A0, 20(S8)
-BFD03B48 002CFCBE LW A1, 44(S8)
-BFD03B4C 367A77E8 JALS prvCopyDataFromQueue
-BFD03B4E 0C00367A LHU S3, 3072(K0)
-BFD03B50 0C00 NOP
+BFD03B44 0014FC9E LW A0, 20(S8)\r
+BFD03B48 002CFCBE LW A1, 44(S8)\r
+BFD03B4C 367A77E8 JALS prvCopyDataFromQueue\r
+BFD03B4E 0C00367A LHU S3, 3072(K0)\r
+BFD03B50 0C00 NOP\r
1588: --( pxQueue->uxMessagesWaiting );\r
-BFD03B52 0014FC5E LW V0, 20(S8)
-BFD03B56 692E LW V0, 56(V0)
-BFD03B58 6DAE ADDIU V1, V0, -1
-BFD03B5A 0014FC5E LW V0, 20(S8)
-BFD03B5E E9AE SW V1, 56(V0)
+BFD03B52 0014FC5E LW V0, 20(S8)\r
+BFD03B56 692E LW V0, 56(V0)\r
+BFD03B58 6DAE ADDIU V1, V0, -1\r
+BFD03B5A 0014FC5E LW V0, 20(S8)\r
+BFD03B5E E9AE SW V1, 56(V0)\r
1589: \r
1590: /* If the queue is locked the event list will not be modified.\r
1591: Instead update the lock count so the task that unlocks the queue\r
1592: will know that an ISR has removed data while the queue was\r
1593: locked. */\r
1594: if( pxQueue->xRxLock == queueUNLOCKED )\r
-BFD03B60 0014FC5E LW V0, 20(S8)
-BFD03B64 0044FC62 LW V1, 68(V0)
-BFD03B68 ED7F LI V0, -1
-BFD03B6A 0019B443 BNE V1, V0, 0xBFD03BA0
-BFD03B6C 0C000019 SLL ZERO, T9, 1
-BFD03B6E 0C00 NOP
+BFD03B60 0014FC5E LW V0, 20(S8)\r
+BFD03B64 0044FC62 LW V1, 68(V0)\r
+BFD03B68 ED7F LI V0, -1\r
+BFD03B6A 0019B443 BNE V1, V0, 0xBFD03BA0\r
+BFD03B6C 0C000019 SLL ZERO, T9, 1\r
+BFD03B6E 0C00 NOP\r
1595: {\r
1596: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r
-BFD03B70 0014FC5E LW V0, 20(S8)
-BFD03B74 6924 LW V0, 16(V0)
-BFD03B76 001C40E2 BEQZC V0, 0xBFD03BB2
+BFD03B70 0014FC5E LW V0, 20(S8)\r
+BFD03B74 6924 LW V0, 16(V0)\r
+BFD03B76 001C40E2 BEQZC V0, 0xBFD03BB2\r
1597: {\r
1598: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\r
-BFD03B7A 0014FC5E LW V0, 20(S8)
-BFD03B7E 6D28 ADDIU V0, V0, 16
-BFD03B80 0C82 MOVE A0, V0
-BFD03B82 22BC77E8 JALS xTaskRemoveFromEventList
-BFD03B84 0C0022BC LWC2 S5, 3072(GP)
-BFD03B86 0C00 NOP
-BFD03B88 001340E2 BEQZC V0, 0xBFD03BB2
+BFD03B7A 0014FC5E LW V0, 20(S8)\r
+BFD03B7E 6D28 ADDIU V0, V0, 16\r
+BFD03B80 0C82 MOVE A0, V0\r
+BFD03B82 22BC77E8 JALS xTaskRemoveFromEventList\r
+BFD03B84 0C0022BC LWC2 S5, 3072(GP)\r
+BFD03B86 0C00 NOP\r
+BFD03B88 001340E2 BEQZC V0, 0xBFD03BB2\r
1599: {\r
1600: /* The task waiting has a higher priority than us so\r
1601: force a context switch. */\r
1602: if( pxHigherPriorityTaskWoken != NULL )\r
-BFD03B8C 0030FC5E LW V0, 48(S8)
-BFD03B90 000F40E2 BEQZC V0, 0xBFD03BB2
+BFD03B8C 0030FC5E LW V0, 48(S8)\r
+BFD03B90 000F40E2 BEQZC V0, 0xBFD03BB2\r
1603: {\r
1604: *pxHigherPriorityTaskWoken = pdTRUE;\r
-BFD03B94 0030FC5E LW V0, 48(S8)
-BFD03B98 ED81 LI V1, 1
-BFD03B9A E9A0 SW V1, 0(V0)
-BFD03B9C CC0A B 0xBFD03BB2
-BFD03B9E 0C00 NOP
+BFD03B94 0030FC5E LW V0, 48(S8)\r
+BFD03B98 ED81 LI V1, 1\r
+BFD03B9A E9A0 SW V1, 0(V0)\r
+BFD03B9C CC0A B 0xBFD03BB2\r
+BFD03B9E 0C00 NOP\r
1605: }\r
1606: else\r
1607: {\r
1623: /* Increment the lock count so the task that unlocks the queue\r
1624: knows that data was removed while it was locked. */\r
1625: ++( pxQueue->xRxLock );\r
-BFD03BA0 0014FC5E LW V0, 20(S8)
-BFD03BA4 0044FC42 LW V0, 68(V0)
-BFD03BA8 6DA0 ADDIU V1, V0, 1
-BFD03BAA 0014FC5E LW V0, 20(S8)
-BFD03BAE 0044F862 SW V1, 68(V0)
+BFD03BA0 0014FC5E LW V0, 20(S8)\r
+BFD03BA4 0044FC42 LW V0, 68(V0)\r
+BFD03BA8 6DA0 ADDIU V1, V0, 1\r
+BFD03BAA 0014FC5E LW V0, 20(S8)\r
+BFD03BAE 0044F862 SW V1, 68(V0)\r
1626: }\r
1627: \r
1628: xReturn = pdPASS;\r
-BFD03BB2 ED01 LI V0, 1
-BFD03BB4 0010F85E SW V0, 16(S8)
-BFD03BB8 CC03 B 0xBFD03BC0
-BFD03BBA 0C00 NOP
+BFD03BB2 ED01 LI V0, 1\r
+BFD03BB4 0010F85E SW V0, 16(S8)\r
+BFD03BB8 CC03 B 0xBFD03BC0\r
+BFD03BBA 0C00 NOP\r
1629: }\r
1630: else\r
1631: {\r
1632: xReturn = pdFAIL;\r
-BFD03BBC 0010F81E SW ZERO, 16(S8)
+BFD03BBC 0010F81E SW ZERO, 16(S8)\r
1633: traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );\r
1634: }\r
1635: }\r
1636: portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r
-BFD03BC0 0018FC9E LW A0, 24(S8)
-BFD03BC4 4D5E77E8 JALS vPortClearInterruptMaskFromISR
-BFD03BC6 4D5E ADDIU T2, T2, -1
-BFD03BC8 0C00 NOP
+BFD03BC0 0018FC9E LW A0, 24(S8)\r
+BFD03BC4 4D5E77E8 JALS vPortClearInterruptMaskFromISR\r
+BFD03BC6 4D5E ADDIU T2, T2, -1\r
+BFD03BC8 0C00 NOP\r
1637: \r
1638: return xReturn;\r
-BFD03BCA 0010FC5E LW V0, 16(S8)
+BFD03BCA 0010FC5E LW V0, 16(S8)\r
1639: }\r
-BFD03BCE 0FBE MOVE SP, S8
-BFD03BD0 4BE9 LW RA, 36(SP)
-BFD03BD2 4BC8 LW S8, 32(SP)
-BFD03BD4 4C15 ADDIU SP, SP, 40
-BFD03BD6 459F JR16 RA
-BFD03BD8 0C00 NOP
+BFD03BCE 0FBE MOVE SP, S8\r
+BFD03BD0 4BE9 LW RA, 36(SP)\r
+BFD03BD2 4BC8 LW S8, 32(SP)\r
+BFD03BD4 4C15 ADDIU SP, SP, 40\r
+BFD03BD6 459F JR16 RA\r
+BFD03BD8 0C00 NOP\r
1640: /*-----------------------------------------------------------*/\r
1641: \r
1642: BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer )\r
1643: {\r
-BFD04824 4FED ADDIU SP, SP, -40
-BFD04826 CBE9 SW RA, 36(SP)
-BFD04828 CBC8 SW S8, 32(SP)
-BFD0482A 0FDD MOVE S8, SP
-BFD0482C 0028F89E SW A0, 40(S8)
-BFD04830 002CF8BE SW A1, 44(S8)
+BFD04824 4FED ADDIU SP, SP, -40\r
+BFD04826 CBE9 SW RA, 36(SP)\r
+BFD04828 CBC8 SW S8, 32(SP)\r
+BFD0482A 0FDD MOVE S8, SP\r
+BFD0482C 0028F89E SW A0, 40(S8)\r
+BFD04830 002CF8BE SW A1, 44(S8)\r
1644: BaseType_t xReturn;\r
1645: UBaseType_t uxSavedInterruptStatus;\r
1646: int8_t *pcOriginalReadPosition;\r
1647: Queue_t * const pxQueue = ( Queue_t * ) xQueue;\r
-BFD04834 0028FC5E LW V0, 40(S8)
-BFD04838 0014F85E SW V0, 20(S8)
+BFD04834 0028FC5E LW V0, 40(S8)\r
+BFD04838 0014F85E SW V0, 20(S8)\r
1648: \r
1649: configASSERT( pxQueue );\r
-BFD0483C 0014FC5E LW V0, 20(S8)
-BFD04840 000940A2 BNEZC V0, 0xBFD04856
-BFD04844 BFD141A2 LUI V0, 0xBFD1
-BFD04846 3082BFD1 LDC1 F30, 12418(S1)
-BFD04848 9E3C3082 ADDIU A0, V0, -25028
-BFD0484A 30A09E3C LWC1 F17, 12448(GP)
-BFD0484C 067130A0 ADDIU A1, ZERO, 1649
-BFD0484E 0671 SUBU A0, S0, A3
-BFD04850 4B7E77E8 JALS vAssertCalled
-BFD04852 4B7E LW K1, 120(SP)
-BFD04854 0C00 NOP
+BFD0483C 0014FC5E LW V0, 20(S8)\r
+BFD04840 000940A2 BNEZC V0, 0xBFD04856\r
+BFD04844 BFD141A2 LUI V0, 0xBFD1\r
+BFD04846 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD04848 9E3C3082 ADDIU A0, V0, -25028\r
+BFD0484A 30A09E3C LWC1 F17, 12448(GP)\r
+BFD0484C 067130A0 ADDIU A1, ZERO, 1649\r
+BFD0484E 0671 SUBU A0, S0, A3\r
+BFD04850 4B7E77E8 JALS vAssertCalled\r
+BFD04852 4B7E LW K1, 120(SP)\r
+BFD04854 0C00 NOP\r
1650: configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\r
-BFD04856 002CFC5E LW V0, 44(S8)
-BFD0485A 000640A2 BNEZC V0, 0xBFD0486A
-BFD0485E 0014FC5E LW V0, 20(S8)
-BFD04862 0040FC42 LW V0, 64(V0)
-BFD04866 000340A2 BNEZC V0, 0xBFD04870
-BFD0486A ED01 LI V0, 1
-BFD0486C CC02 B 0xBFD04872
-BFD0486E 0C00 NOP
-BFD04870 0C40 MOVE V0, ZERO
-BFD04872 000940A2 BNEZC V0, 0xBFD04888
-BFD04876 BFD141A2 LUI V0, 0xBFD1
-BFD04878 3082BFD1 LDC1 F30, 12418(S1)
-BFD0487A 9E3C3082 ADDIU A0, V0, -25028
-BFD0487C 30A09E3C LWC1 F17, 12448(GP)
-BFD0487E 067230A0 ADDIU A1, ZERO, 1650
-BFD04880 0672 ADDU A0, S1, A3
-BFD04882 4B7E77E8 JALS vAssertCalled
-BFD04884 4B7E LW K1, 120(SP)
-BFD04886 0C00 NOP
+BFD04856 002CFC5E LW V0, 44(S8)\r
+BFD0485A 000640A2 BNEZC V0, 0xBFD0486A\r
+BFD0485E 0014FC5E LW V0, 20(S8)\r
+BFD04862 0040FC42 LW V0, 64(V0)\r
+BFD04866 000340A2 BNEZC V0, 0xBFD04870\r
+BFD0486A ED01 LI V0, 1\r
+BFD0486C CC02 B 0xBFD04872\r
+BFD0486E 0C00 NOP\r
+BFD04870 0C40 MOVE V0, ZERO\r
+BFD04872 000940A2 BNEZC V0, 0xBFD04888\r
+BFD04876 BFD141A2 LUI V0, 0xBFD1\r
+BFD04878 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD0487A 9E3C3082 ADDIU A0, V0, -25028\r
+BFD0487C 30A09E3C LWC1 F17, 12448(GP)\r
+BFD0487E 067230A0 ADDIU A1, ZERO, 1650\r
+BFD04880 0672 ADDU A0, S1, A3\r
+BFD04882 4B7E77E8 JALS vAssertCalled\r
+BFD04884 4B7E LW K1, 120(SP)\r
+BFD04886 0C00 NOP\r
1651: configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */\r
-BFD04888 0014FC5E LW V0, 20(S8)
-BFD0488C 0040FC42 LW V0, 64(V0)
-BFD04890 000940A2 BNEZC V0, 0xBFD048A6
-BFD04894 BFD141A2 LUI V0, 0xBFD1
-BFD04896 3082BFD1 LDC1 F30, 12418(S1)
-BFD04898 9E3C3082 ADDIU A0, V0, -25028
-BFD0489A 30A09E3C LWC1 F17, 12448(GP)
-BFD0489C 067330A0 ADDIU A1, ZERO, 1651
-BFD0489E 0673 SUBU A0, S1, A3
-BFD048A0 4B7E77E8 JALS vAssertCalled
-BFD048A2 4B7E LW K1, 120(SP)
-BFD048A4 0C00 NOP
+BFD04888 0014FC5E LW V0, 20(S8)\r
+BFD0488C 0040FC42 LW V0, 64(V0)\r
+BFD04890 000940A2 BNEZC V0, 0xBFD048A6\r
+BFD04894 BFD141A2 LUI V0, 0xBFD1\r
+BFD04896 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD04898 9E3C3082 ADDIU A0, V0, -25028\r
+BFD0489A 30A09E3C LWC1 F17, 12448(GP)\r
+BFD0489C 067330A0 ADDIU A1, ZERO, 1651\r
+BFD0489E 0673 SUBU A0, S1, A3\r
+BFD048A0 4B7E77E8 JALS vAssertCalled\r
+BFD048A2 4B7E LW K1, 120(SP)\r
+BFD048A4 0C00 NOP\r
1652: \r
1653: /* RTOS ports that support interrupt nesting have the concept of a maximum\r
1654: system call (or maximum API call) interrupt priority. Interrupts that are\r
1667: portASSERT_IF_INTERRUPT_PRIORITY_INVALID();\r
1668: \r
1669: uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r
-BFD048A6 475E77E8 JALS uxPortSetInterruptMaskFromISR
-BFD048AA 0C00 NOP
-BFD048AC 0018F85E SW V0, 24(S8)
+BFD048A6 475E77E8 JALS uxPortSetInterruptMaskFromISR\r
+BFD048AA 0C00 NOP\r
+BFD048AC 0018F85E SW V0, 24(S8)\r
1670: {\r
1671: /* Cannot block in an ISR, so check there is data available. */\r
1672: if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )\r
-BFD048B0 0014FC5E LW V0, 20(S8)
-BFD048B4 692E LW V0, 56(V0)
-BFD048B6 001640E2 BEQZC V0, 0xBFD048E6
+BFD048B0 0014FC5E LW V0, 20(S8)\r
+BFD048B4 692E LW V0, 56(V0)\r
+BFD048B6 001640E2 BEQZC V0, 0xBFD048E6\r
1673: {\r
1674: traceQUEUE_PEEK_FROM_ISR( pxQueue );\r
1675: \r
1676: /* Remember the read position so it can be reset as nothing is\r
1677: actually being removed from the queue. */\r
1678: pcOriginalReadPosition = pxQueue->u.pcReadFrom;\r
-BFD048BA 0014FC5E LW V0, 20(S8)
-BFD048BE 6923 LW V0, 12(V0)
-BFD048C0 001CF85E SW V0, 28(S8)
+BFD048BA 0014FC5E LW V0, 20(S8)\r
+BFD048BE 6923 LW V0, 12(V0)\r
+BFD048C0 001CF85E SW V0, 28(S8)\r
1679: prvCopyDataFromQueue( pxQueue, pvBuffer );\r
-BFD048C4 0014FC9E LW A0, 20(S8)
-BFD048C8 002CFCBE LW A1, 44(S8)
-BFD048CC 367A77E8 JALS prvCopyDataFromQueue
-BFD048CE 0C00367A LHU S3, 3072(K0)
-BFD048D0 0C00 NOP
+BFD048C4 0014FC9E LW A0, 20(S8)\r
+BFD048C8 002CFCBE LW A1, 44(S8)\r
+BFD048CC 367A77E8 JALS prvCopyDataFromQueue\r
+BFD048CE 0C00367A LHU S3, 3072(K0)\r
+BFD048D0 0C00 NOP\r
1680: pxQueue->u.pcReadFrom = pcOriginalReadPosition;\r
-BFD048D2 0014FC5E LW V0, 20(S8)
-BFD048D6 001CFC7E LW V1, 28(S8)
-BFD048DA E9A3 SW V1, 12(V0)
+BFD048D2 0014FC5E LW V0, 20(S8)\r
+BFD048D6 001CFC7E LW V1, 28(S8)\r
+BFD048DA E9A3 SW V1, 12(V0)\r
1681: \r
1682: xReturn = pdPASS;\r
-BFD048DC ED01 LI V0, 1
-BFD048DE 0010F85E SW V0, 16(S8)
-BFD048E2 CC03 B 0xBFD048EA
-BFD048E4 0C00 NOP
+BFD048DC ED01 LI V0, 1\r
+BFD048DE 0010F85E SW V0, 16(S8)\r
+BFD048E2 CC03 B 0xBFD048EA\r
+BFD048E4 0C00 NOP\r
1683: }\r
1684: else\r
1685: {\r
1686: xReturn = pdFAIL;\r
-BFD048E6 0010F81E SW ZERO, 16(S8)
+BFD048E6 0010F81E SW ZERO, 16(S8)\r
1687: traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );\r
1688: }\r
1689: }\r
1690: portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r
-BFD048EA 0018FC9E LW A0, 24(S8)
-BFD048EE 4D5E77E8 JALS vPortClearInterruptMaskFromISR
-BFD048F0 4D5E ADDIU T2, T2, -1
-BFD048F2 0C00 NOP
+BFD048EA 0018FC9E LW A0, 24(S8)\r
+BFD048EE 4D5E77E8 JALS vPortClearInterruptMaskFromISR\r
+BFD048F0 4D5E ADDIU T2, T2, -1\r
+BFD048F2 0C00 NOP\r
1691: \r
1692: return xReturn;\r
-BFD048F4 0010FC5E LW V0, 16(S8)
+BFD048F4 0010FC5E LW V0, 16(S8)\r
1693: }\r
-BFD048F8 0FBE MOVE SP, S8
-BFD048FA 4BE9 LW RA, 36(SP)
-BFD048FC 4BC8 LW S8, 32(SP)
-BFD048FE 4C15 ADDIU SP, SP, 40
-BFD04900 459F JR16 RA
-BFD04902 0C00 NOP
+BFD048F8 0FBE MOVE SP, S8\r
+BFD048FA 4BE9 LW RA, 36(SP)\r
+BFD048FC 4BC8 LW S8, 32(SP)\r
+BFD048FE 4C15 ADDIU SP, SP, 40\r
+BFD04900 459F JR16 RA\r
+BFD04902 0C00 NOP\r
1694: /*-----------------------------------------------------------*/\r
1695: \r
1696: UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )\r
1697: {\r
-BFD08B2C 4FF1 ADDIU SP, SP, -32
-BFD08B2E CBE7 SW RA, 28(SP)
-BFD08B30 CBC6 SW S8, 24(SP)
-BFD08B32 0FDD MOVE S8, SP
-BFD08B34 0020F89E SW A0, 32(S8)
+BFD08B2C 4FF1 ADDIU SP, SP, -32\r
+BFD08B2E CBE7 SW RA, 28(SP)\r
+BFD08B30 CBC6 SW S8, 24(SP)\r
+BFD08B32 0FDD MOVE S8, SP\r
+BFD08B34 0020F89E SW A0, 32(S8)\r
1698: UBaseType_t uxReturn;\r
1699: \r
1700: configASSERT( xQueue );\r
-BFD08B38 0020FC5E LW V0, 32(S8)
-BFD08B3C 000940A2 BNEZC V0, 0xBFD08B52
-BFD08B40 BFD141A2 LUI V0, 0xBFD1
-BFD08B42 3082BFD1 LDC1 F30, 12418(S1)
-BFD08B44 9E3C3082 ADDIU A0, V0, -25028
-BFD08B46 30A09E3C LWC1 F17, 12448(GP)
-BFD08B48 06A430A0 ADDIU A1, ZERO, 1700
-BFD08B4A 06A4 ADDU A1, V0, V0
-BFD08B4C 4B7E77E8 JALS vAssertCalled
-BFD08B4E 4B7E LW K1, 120(SP)
-BFD08B50 0C00 NOP
+BFD08B38 0020FC5E LW V0, 32(S8)\r
+BFD08B3C 000940A2 BNEZC V0, 0xBFD08B52\r
+BFD08B40 BFD141A2 LUI V0, 0xBFD1\r
+BFD08B42 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD08B44 9E3C3082 ADDIU A0, V0, -25028\r
+BFD08B46 30A09E3C LWC1 F17, 12448(GP)\r
+BFD08B48 06A430A0 ADDIU A1, ZERO, 1700\r
+BFD08B4A 06A4 ADDU A1, V0, V0\r
+BFD08B4C 4B7E77E8 JALS vAssertCalled\r
+BFD08B4E 4B7E LW K1, 120(SP)\r
+BFD08B50 0C00 NOP\r
1701: \r
1702: taskENTER_CRITICAL();\r
-BFD08B52 33B877E8 JALS vTaskEnterCritical
-BFD08B54 0C0033B8 ADDIU SP, T8, 3072
-BFD08B56 0C00 NOP
+BFD08B52 33B877E8 JALS vTaskEnterCritical\r
+BFD08B54 0C0033B8 ADDIU SP, T8, 3072\r
+BFD08B56 0C00 NOP\r
1703: {\r
1704: uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;\r
-BFD08B58 0020FC5E LW V0, 32(S8)
-BFD08B5C 692E LW V0, 56(V0)
-BFD08B5E 0010F85E SW V0, 16(S8)
+BFD08B58 0020FC5E LW V0, 32(S8)\r
+BFD08B5C 692E LW V0, 56(V0)\r
+BFD08B5E 0010F85E SW V0, 16(S8)\r
1705: }\r
1706: taskEXIT_CRITICAL();\r
-BFD08B62 40AA77E8 JALS vTaskExitCritical
-BFD08B64 0C0040AA BNEZC T2, 0xBFD0A368
-BFD08B66 0C00 NOP
+BFD08B62 40AA77E8 JALS vTaskExitCritical\r
+BFD08B64 0C0040AA BNEZC T2, 0xBFD0A368\r
+BFD08B66 0C00 NOP\r
1707: \r
1708: return uxReturn;\r
-BFD08B68 0010FC5E LW V0, 16(S8)
+BFD08B68 0010FC5E LW V0, 16(S8)\r
1709: } /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */\r
-BFD08B6C 0FBE MOVE SP, S8
-BFD08B6E 4BE7 LW RA, 28(SP)
-BFD08B70 4BC6 LW S8, 24(SP)
-BFD08B72 4C11 ADDIU SP, SP, 32
-BFD08B74 459F JR16 RA
-BFD08B76 0C00 NOP
+BFD08B6C 0FBE MOVE SP, S8\r
+BFD08B6E 4BE7 LW RA, 28(SP)\r
+BFD08B70 4BC6 LW S8, 24(SP)\r
+BFD08B72 4C11 ADDIU SP, SP, 32\r
+BFD08B74 459F JR16 RA\r
+BFD08B76 0C00 NOP\r
1710: /*-----------------------------------------------------------*/\r
1711: \r
1712: UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )\r
1713: {\r
-BFD082D4 4FF1 ADDIU SP, SP, -32
-BFD082D6 CBE7 SW RA, 28(SP)
-BFD082D8 CBC6 SW S8, 24(SP)
-BFD082DA 0FDD MOVE S8, SP
-BFD082DC 0020F89E SW A0, 32(S8)
+BFD082D4 4FF1 ADDIU SP, SP, -32\r
+BFD082D6 CBE7 SW RA, 28(SP)\r
+BFD082D8 CBC6 SW S8, 24(SP)\r
+BFD082DA 0FDD MOVE S8, SP\r
+BFD082DC 0020F89E SW A0, 32(S8)\r
1714: UBaseType_t uxReturn;\r
1715: Queue_t *pxQueue;\r
1716: \r
1717: pxQueue = ( Queue_t * ) xQueue;\r
-BFD082E0 0020FC5E LW V0, 32(S8)
-BFD082E4 0010F85E SW V0, 16(S8)
+BFD082E0 0020FC5E LW V0, 32(S8)\r
+BFD082E4 0010F85E SW V0, 16(S8)\r
1718: configASSERT( pxQueue );\r
-BFD082E8 0010FC5E LW V0, 16(S8)
-BFD082EC 000940A2 BNEZC V0, 0xBFD08302
-BFD082F0 BFD141A2 LUI V0, 0xBFD1
-BFD082F2 3082BFD1 LDC1 F30, 12418(S1)
-BFD082F4 9E3C3082 ADDIU A0, V0, -25028
-BFD082F6 30A09E3C LWC1 F17, 12448(GP)
-BFD082F8 06B630A0 ADDIU A1, ZERO, 1718
-BFD082FA 06B6 ADDU A1, V1, V1
-BFD082FC 4B7E77E8 JALS vAssertCalled
-BFD082FE 4B7E LW K1, 120(SP)
-BFD08300 0C00 NOP
+BFD082E8 0010FC5E LW V0, 16(S8)\r
+BFD082EC 000940A2 BNEZC V0, 0xBFD08302\r
+BFD082F0 BFD141A2 LUI V0, 0xBFD1\r
+BFD082F2 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD082F4 9E3C3082 ADDIU A0, V0, -25028\r
+BFD082F6 30A09E3C LWC1 F17, 12448(GP)\r
+BFD082F8 06B630A0 ADDIU A1, ZERO, 1718\r
+BFD082FA 06B6 ADDU A1, V1, V1\r
+BFD082FC 4B7E77E8 JALS vAssertCalled\r
+BFD082FE 4B7E LW K1, 120(SP)\r
+BFD08300 0C00 NOP\r
1719: \r
1720: taskENTER_CRITICAL();\r
-BFD08302 33B877E8 JALS vTaskEnterCritical
-BFD08304 0C0033B8 ADDIU SP, T8, 3072
-BFD08306 0C00 NOP
+BFD08302 33B877E8 JALS vTaskEnterCritical\r
+BFD08304 0C0033B8 ADDIU SP, T8, 3072\r
+BFD08306 0C00 NOP\r
1721: {\r
1722: uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting;\r
-BFD08308 0010FC5E LW V0, 16(S8)
-BFD0830C 69AF LW V1, 60(V0)
-BFD0830E 0010FC5E LW V0, 16(S8)
-BFD08312 692E LW V0, 56(V0)
-BFD08314 0527 SUBU V0, V1, V0
-BFD08316 0014F85E SW V0, 20(S8)
+BFD08308 0010FC5E LW V0, 16(S8)\r
+BFD0830C 69AF LW V1, 60(V0)\r
+BFD0830E 0010FC5E LW V0, 16(S8)\r
+BFD08312 692E LW V0, 56(V0)\r
+BFD08314 0527 SUBU V0, V1, V0\r
+BFD08316 0014F85E SW V0, 20(S8)\r
1723: }\r
1724: taskEXIT_CRITICAL();\r
-BFD0831A 40AA77E8 JALS vTaskExitCritical
-BFD0831C 0C0040AA BNEZC T2, 0xBFD09B20
-BFD0831E 0C00 NOP
+BFD0831A 40AA77E8 JALS vTaskExitCritical\r
+BFD0831C 0C0040AA BNEZC T2, 0xBFD09B20\r
+BFD0831E 0C00 NOP\r
1725: \r
1726: return uxReturn;\r
-BFD08320 0014FC5E LW V0, 20(S8)
+BFD08320 0014FC5E LW V0, 20(S8)\r
1727: } /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */\r
-BFD08324 0FBE MOVE SP, S8
-BFD08326 4BE7 LW RA, 28(SP)
-BFD08328 4BC6 LW S8, 24(SP)
-BFD0832A 4C11 ADDIU SP, SP, 32
-BFD0832C 459F JR16 RA
-BFD0832E 0C00 NOP
+BFD08324 0FBE MOVE SP, S8\r
+BFD08326 4BE7 LW RA, 28(SP)\r
+BFD08328 4BC6 LW S8, 24(SP)\r
+BFD0832A 4C11 ADDIU SP, SP, 32\r
+BFD0832C 459F JR16 RA\r
+BFD0832E 0C00 NOP\r
1728: /*-----------------------------------------------------------*/\r
1729: \r
1730: UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )\r
1731: {\r
-BFD09360 4FF1 ADDIU SP, SP, -32
-BFD09362 CBE7 SW RA, 28(SP)
-BFD09364 CBC6 SW S8, 24(SP)
-BFD09366 0FDD MOVE S8, SP
-BFD09368 0020F89E SW A0, 32(S8)
+BFD09360 4FF1 ADDIU SP, SP, -32\r
+BFD09362 CBE7 SW RA, 28(SP)\r
+BFD09364 CBC6 SW S8, 24(SP)\r
+BFD09366 0FDD MOVE S8, SP\r
+BFD09368 0020F89E SW A0, 32(S8)\r
1732: UBaseType_t uxReturn;\r
1733: \r
1734: configASSERT( xQueue );\r
-BFD0936C 0020FC5E LW V0, 32(S8)
-BFD09370 000940A2 BNEZC V0, 0xBFD09386
-BFD09374 BFD141A2 LUI V0, 0xBFD1
-BFD09376 3082BFD1 LDC1 F30, 12418(S1)
-BFD09378 9E3C3082 ADDIU A0, V0, -25028
-BFD0937A 30A09E3C LWC1 F17, 12448(GP)
-BFD0937C 06C630A0 ADDIU A1, ZERO, 1734
-BFD0937E 06C6 ADDU A1, V1, A0
-BFD09380 4B7E77E8 JALS vAssertCalled
-BFD09382 4B7E LW K1, 120(SP)
-BFD09384 0C00 NOP
+BFD0936C 0020FC5E LW V0, 32(S8)\r
+BFD09370 000940A2 BNEZC V0, 0xBFD09386\r
+BFD09374 BFD141A2 LUI V0, 0xBFD1\r
+BFD09376 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD09378 9E3C3082 ADDIU A0, V0, -25028\r
+BFD0937A 30A09E3C LWC1 F17, 12448(GP)\r
+BFD0937C 06C630A0 ADDIU A1, ZERO, 1734\r
+BFD0937E 06C6 ADDU A1, V1, A0\r
+BFD09380 4B7E77E8 JALS vAssertCalled\r
+BFD09382 4B7E LW K1, 120(SP)\r
+BFD09384 0C00 NOP\r
1735: \r
1736: uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;\r
-BFD09386 0020FC5E LW V0, 32(S8)
-BFD0938A 692E LW V0, 56(V0)
-BFD0938C 0010F85E SW V0, 16(S8)
+BFD09386 0020FC5E LW V0, 32(S8)\r
+BFD0938A 692E LW V0, 56(V0)\r
+BFD0938C 0010F85E SW V0, 16(S8)\r
1737: \r
1738: return uxReturn;\r
-BFD09390 0010FC5E LW V0, 16(S8)
+BFD09390 0010FC5E LW V0, 16(S8)\r
1739: } /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */\r
-BFD09394 0FBE MOVE SP, S8
-BFD09396 4BE7 LW RA, 28(SP)
-BFD09398 4BC6 LW S8, 24(SP)
-BFD0939A 4C11 ADDIU SP, SP, 32
-BFD0939C 459F JR16 RA
-BFD0939E 0C00 NOP
+BFD09394 0FBE MOVE SP, S8\r
+BFD09396 4BE7 LW RA, 28(SP)\r
+BFD09398 4BC6 LW S8, 24(SP)\r
+BFD0939A 4C11 ADDIU SP, SP, 32\r
+BFD0939C 459F JR16 RA\r
+BFD0939E 0C00 NOP\r
1740: /*-----------------------------------------------------------*/\r
1741: \r
1742: void vQueueDelete( QueueHandle_t xQueue )\r
1743: {\r
-BFD09188 4FF1 ADDIU SP, SP, -32
-BFD0918A CBE7 SW RA, 28(SP)
-BFD0918C CBC6 SW S8, 24(SP)
-BFD0918E 0FDD MOVE S8, SP
-BFD09190 0020F89E SW A0, 32(S8)
+BFD09188 4FF1 ADDIU SP, SP, -32\r
+BFD0918A CBE7 SW RA, 28(SP)\r
+BFD0918C CBC6 SW S8, 24(SP)\r
+BFD0918E 0FDD MOVE S8, SP\r
+BFD09190 0020F89E SW A0, 32(S8)\r
1744: Queue_t * const pxQueue = ( Queue_t * ) xQueue;\r
-BFD09194 0020FC5E LW V0, 32(S8)
-BFD09198 0010F85E SW V0, 16(S8)
+BFD09194 0020FC5E LW V0, 32(S8)\r
+BFD09198 0010F85E SW V0, 16(S8)\r
1745: \r
1746: configASSERT( pxQueue );\r
-BFD0919C 0010FC5E LW V0, 16(S8)
-BFD091A0 000940A2 BNEZC V0, 0xBFD091B6
-BFD091A4 BFD141A2 LUI V0, 0xBFD1
-BFD091A6 3082BFD1 LDC1 F30, 12418(S1)
-BFD091A8 9E3C3082 ADDIU A0, V0, -25028
-BFD091AA 30A09E3C LWC1 F17, 12448(GP)
-BFD091AC 06D230A0 ADDIU A1, ZERO, 1746
-BFD091AE 06D2 ADDU A1, S1, A1
-BFD091B0 4B7E77E8 JALS vAssertCalled
-BFD091B2 4B7E LW K1, 120(SP)
-BFD091B4 0C00 NOP
+BFD0919C 0010FC5E LW V0, 16(S8)\r
+BFD091A0 000940A2 BNEZC V0, 0xBFD091B6\r
+BFD091A4 BFD141A2 LUI V0, 0xBFD1\r
+BFD091A6 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD091A8 9E3C3082 ADDIU A0, V0, -25028\r
+BFD091AA 30A09E3C LWC1 F17, 12448(GP)\r
+BFD091AC 06D230A0 ADDIU A1, ZERO, 1746\r
+BFD091AE 06D2 ADDU A1, S1, A1\r
+BFD091B0 4B7E77E8 JALS vAssertCalled\r
+BFD091B2 4B7E LW K1, 120(SP)\r
+BFD091B4 0C00 NOP\r
1747: \r
1748: traceQUEUE_DELETE( pxQueue );\r
1749: #if ( configQUEUE_REGISTRY_SIZE > 0 )\r
1752: }\r
1753: #endif\r
1754: vPortFree( pxQueue );\r
-BFD091B6 0010FC9E LW A0, 16(S8)
-BFD091BA 2FEA77E8 JALS vPortFree
-BFD091BC 2FEA ANDI A3, A2, 0x20
-BFD091BE 0C00 NOP
+BFD091B6 0010FC9E LW A0, 16(S8)\r
+BFD091BA 2FEA77E8 JALS vPortFree\r
+BFD091BC 2FEA ANDI A3, A2, 0x20\r
+BFD091BE 0C00 NOP\r
1755: }\r
-BFD091C0 0FBE MOVE SP, S8
-BFD091C2 4BE7 LW RA, 28(SP)
-BFD091C4 4BC6 LW S8, 24(SP)
-BFD091C6 4C11 ADDIU SP, SP, 32
-BFD091C8 459F JR16 RA
-BFD091CA 0C00 NOP
+BFD091C0 0FBE MOVE SP, S8\r
+BFD091C2 4BE7 LW RA, 28(SP)\r
+BFD091C4 4BC6 LW S8, 24(SP)\r
+BFD091C6 4C11 ADDIU SP, SP, 32\r
+BFD091C8 459F JR16 RA\r
+BFD091CA 0C00 NOP\r
1756: /*-----------------------------------------------------------*/\r
1757: \r
1758: #if ( configUSE_TRACE_FACILITY == 1 )\r
1787: \r
1788: static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )\r
1789: {\r
-BFD029CC 4FF1 ADDIU SP, SP, -32
-BFD029CE CBE7 SW RA, 28(SP)
-BFD029D0 CBC6 SW S8, 24(SP)
-BFD029D2 0FDD MOVE S8, SP
-BFD029D4 0020F89E SW A0, 32(S8)
-BFD029D8 0024F8BE SW A1, 36(S8)
-BFD029DC 0028F8DE SW A2, 40(S8)
+BFD029CC 4FF1 ADDIU SP, SP, -32\r
+BFD029CE CBE7 SW RA, 28(SP)\r
+BFD029D0 CBC6 SW S8, 24(SP)\r
+BFD029D2 0FDD MOVE S8, SP\r
+BFD029D4 0020F89E SW A0, 32(S8)\r
+BFD029D8 0024F8BE SW A1, 36(S8)\r
+BFD029DC 0028F8DE SW A2, 40(S8)\r
1790: BaseType_t xReturn = pdFALSE;\r
-BFD029E0 0010F81E SW ZERO, 16(S8)
+BFD029E0 0010F81E SW ZERO, 16(S8)\r
1791: \r
1792: if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )\r
-BFD029E4 0020FC5E LW V0, 32(S8)
-BFD029E8 0040FC42 LW V0, 64(V0)
-BFD029EC 001340A2 BNEZC V0, 0xBFD02A16
+BFD029E4 0020FC5E LW V0, 32(S8)\r
+BFD029E8 0040FC42 LW V0, 64(V0)\r
+BFD029EC 001340A2 BNEZC V0, 0xBFD02A16\r
1793: {\r
1794: #if ( configUSE_MUTEXES == 1 )\r
1795: {\r
1796: if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\r
-BFD029F0 0020FC5E LW V0, 32(S8)
-BFD029F4 6920 LW V0, 0(V0)
-BFD029F6 008140A2 BNEZC V0, 0xBFD02AFC
+BFD029F0 0020FC5E LW V0, 32(S8)\r
+BFD029F4 6920 LW V0, 0(V0)\r
+BFD029F6 008140A2 BNEZC V0, 0xBFD02AFC\r
1797: {\r
1798: /* The mutex is no longer being held. */\r
1799: xReturn = xTaskPriorityDisinherit( ( void * ) pxQueue->pxMutexHolder );\r
-BFD029FA 0020FC5E LW V0, 32(S8)
-BFD029FE 6921 LW V0, 4(V0)
-BFD02A00 0C82 MOVE A0, V0
-BFD02A02 178277E8 JALS xTaskPriorityDisinherit
-BFD02A04 0C001782 LBU GP, 3072(V0)
-BFD02A06 0C00 NOP
-BFD02A08 0010F85E SW V0, 16(S8)
+BFD029FA 0020FC5E LW V0, 32(S8)\r
+BFD029FE 6921 LW V0, 4(V0)\r
+BFD02A00 0C82 MOVE A0, V0\r
+BFD02A02 178277E8 JALS xTaskPriorityDisinherit\r
+BFD02A04 0C001782 LBU GP, 3072(V0)\r
+BFD02A06 0C00 NOP\r
+BFD02A08 0010F85E SW V0, 16(S8)\r
1800: pxQueue->pxMutexHolder = NULL;\r
-BFD02A0C 0020FC5E LW V0, 32(S8)
-BFD02A10 E821 SW S0, 4(V0)
-BFD02A12 CC74 B 0xBFD02AFC
-BFD02A14 0C00 NOP
+BFD02A0C 0020FC5E LW V0, 32(S8)\r
+BFD02A10 E821 SW S0, 4(V0)\r
+BFD02A12 CC74 B 0xBFD02AFC\r
+BFD02A14 0C00 NOP\r
1801: }\r
1802: else\r
1803: {\r
1807: #endif /* configUSE_MUTEXES */\r
1808: }\r
1809: else if( xPosition == queueSEND_TO_BACK )\r
-BFD02A16 0028FC5E LW V0, 40(S8)
-BFD02A1A 002B40A2 BNEZC V0, 0xBFD02A74
+BFD02A16 0028FC5E LW V0, 40(S8)\r
+BFD02A1A 002B40A2 BNEZC V0, 0xBFD02A74\r
1810: {\r
1811: ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. */\r
-BFD02A1E 0020FC5E LW V0, 32(S8)
-BFD02A22 69A2 LW V1, 8(V0)
-BFD02A24 0020FC5E LW V0, 32(S8)
-BFD02A28 0040FC42 LW V0, 64(V0)
-BFD02A2C 0C83 MOVE A0, V1
-BFD02A2E 0024FCBE LW A1, 36(S8)
-BFD02A32 0CC2 MOVE A2, V0
-BFD02A34 1BB477E8 JALS 0xBFD03768
-BFD02A36 0C001BB4 SB SP, 3072(S4)
-BFD02A38 0C00 NOP
+BFD02A1E 0020FC5E LW V0, 32(S8)\r
+BFD02A22 69A2 LW V1, 8(V0)\r
+BFD02A24 0020FC5E LW V0, 32(S8)\r
+BFD02A28 0040FC42 LW V0, 64(V0)\r
+BFD02A2C 0C83 MOVE A0, V1\r
+BFD02A2E 0024FCBE LW A1, 36(S8)\r
+BFD02A32 0CC2 MOVE A2, V0\r
+BFD02A34 1BB477E8 JALS 0xBFD03768\r
+BFD02A36 0C001BB4 SB SP, 3072(S4)\r
+BFD02A38 0C00 NOP\r
1812: pxQueue->pcWriteTo += pxQueue->uxItemSize;\r
-BFD02A3A 0020FC5E LW V0, 32(S8)
-BFD02A3E 69A2 LW V1, 8(V0)
-BFD02A40 0020FC5E LW V0, 32(S8)
-BFD02A44 0040FC42 LW V0, 64(V0)
-BFD02A48 05A6 ADDU V1, V1, V0
-BFD02A4A 0020FC5E LW V0, 32(S8)
-BFD02A4E E9A2 SW V1, 8(V0)
+BFD02A3A 0020FC5E LW V0, 32(S8)\r
+BFD02A3E 69A2 LW V1, 8(V0)\r
+BFD02A40 0020FC5E LW V0, 32(S8)\r
+BFD02A44 0040FC42 LW V0, 64(V0)\r
+BFD02A48 05A6 ADDU V1, V1, V0\r
+BFD02A4A 0020FC5E LW V0, 32(S8)\r
+BFD02A4E E9A2 SW V1, 8(V0)\r
1813: if( pxQueue->pcWriteTo >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */\r
-BFD02A50 0020FC5E LW V0, 32(S8)
-BFD02A54 69A2 LW V1, 8(V0)
-BFD02A56 0020FC5E LW V0, 32(S8)
-BFD02A5A 6921 LW V0, 4(V0)
-BFD02A5C 13900043 SLTU V0, V1, V0
-BFD02A5E 40A21390 ADDI GP, S0, 16546
-BFD02A60 004C40A2 BNEZC V0, 0xBFD02AFC
+BFD02A50 0020FC5E LW V0, 32(S8)\r
+BFD02A54 69A2 LW V1, 8(V0)\r
+BFD02A56 0020FC5E LW V0, 32(S8)\r
+BFD02A5A 6921 LW V0, 4(V0)\r
+BFD02A5C 13900043 SLTU V0, V1, V0\r
+BFD02A5E 40A21390 ADDI GP, S0, 16546\r
+BFD02A60 004C40A2 BNEZC V0, 0xBFD02AFC\r
1814: {\r
1815: pxQueue->pcWriteTo = pxQueue->pcHead;\r
-BFD02A64 0020FC5E LW V0, 32(S8)
-BFD02A68 69A0 LW V1, 0(V0)
-BFD02A6A 0020FC5E LW V0, 32(S8)
-BFD02A6E E9A2 SW V1, 8(V0)
-BFD02A70 CC45 B 0xBFD02AFC
-BFD02A72 0C00 NOP
+BFD02A64 0020FC5E LW V0, 32(S8)\r
+BFD02A68 69A0 LW V1, 0(V0)\r
+BFD02A6A 0020FC5E LW V0, 32(S8)\r
+BFD02A6E E9A2 SW V1, 8(V0)\r
+BFD02A70 CC45 B 0xBFD02AFC\r
+BFD02A72 0C00 NOP\r
1816: }\r
1817: else\r
1818: {\r
1822: else\r
1823: {\r
1824: ( void ) memcpy( ( void * ) pxQueue->u.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\r
-BFD02A74 0020FC5E LW V0, 32(S8)
-BFD02A78 69A3 LW V1, 12(V0)
-BFD02A7A 0020FC5E LW V0, 32(S8)
-BFD02A7E 0040FC42 LW V0, 64(V0)
-BFD02A82 0C83 MOVE A0, V1
-BFD02A84 0024FCBE LW A1, 36(S8)
-BFD02A88 0CC2 MOVE A2, V0
-BFD02A8A 1BB477E8 JALS 0xBFD03768
-BFD02A8C 0C001BB4 SB SP, 3072(S4)
-BFD02A8E 0C00 NOP
+BFD02A74 0020FC5E LW V0, 32(S8)\r
+BFD02A78 69A3 LW V1, 12(V0)\r
+BFD02A7A 0020FC5E LW V0, 32(S8)\r
+BFD02A7E 0040FC42 LW V0, 64(V0)\r
+BFD02A82 0C83 MOVE A0, V1\r
+BFD02A84 0024FCBE LW A1, 36(S8)\r
+BFD02A88 0CC2 MOVE A2, V0\r
+BFD02A8A 1BB477E8 JALS 0xBFD03768\r
+BFD02A8C 0C001BB4 SB SP, 3072(S4)\r
+BFD02A8E 0C00 NOP\r
1825: pxQueue->u.pcReadFrom -= pxQueue->uxItemSize;\r
-BFD02A90 0020FC5E LW V0, 32(S8)
-BFD02A94 69A3 LW V1, 12(V0)
-BFD02A96 0020FC5E LW V0, 32(S8)
-BFD02A9A 0040FC42 LW V0, 64(V0)
-BFD02A9C 00400040 SRL V0, ZERO, 0
-BFD02A9E 11D00040 SUBU V0, ZERO, V0
-BFD02AA0 05A611D0 ADDI T6, S0, 1446
-BFD02AA2 05A6 ADDU V1, V1, V0
-BFD02AA4 0020FC5E LW V0, 32(S8)
-BFD02AA8 E9A3 SW V1, 12(V0)
+BFD02A90 0020FC5E LW V0, 32(S8)\r
+BFD02A94 69A3 LW V1, 12(V0)\r
+BFD02A96 0020FC5E LW V0, 32(S8)\r
+BFD02A9A 0040FC42 LW V0, 64(V0)\r
+BFD02A9C 00400040 SRL V0, ZERO, 0\r
+BFD02A9E 11D00040 SUBU V0, ZERO, V0\r
+BFD02AA0 05A611D0 ADDI T6, S0, 1446\r
+BFD02AA2 05A6 ADDU V1, V1, V0\r
+BFD02AA4 0020FC5E LW V0, 32(S8)\r
+BFD02AA8 E9A3 SW V1, 12(V0)\r
1826: if( pxQueue->u.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */\r
-BFD02AAA 0020FC5E LW V0, 32(S8)
-BFD02AAE 69A3 LW V1, 12(V0)
-BFD02AB0 0020FC5E LW V0, 32(S8)
-BFD02AB4 6920 LW V0, 0(V0)
-BFD02AB6 13900043 SLTU V0, V1, V0
-BFD02AB8 40E21390 ADDI GP, S0, 16610
-BFD02ABA 000D40E2 BEQZC V0, 0xBFD02AD8
+BFD02AAA 0020FC5E LW V0, 32(S8)\r
+BFD02AAE 69A3 LW V1, 12(V0)\r
+BFD02AB0 0020FC5E LW V0, 32(S8)\r
+BFD02AB4 6920 LW V0, 0(V0)\r
+BFD02AB6 13900043 SLTU V0, V1, V0\r
+BFD02AB8 40E21390 ADDI GP, S0, 16610\r
+BFD02ABA 000D40E2 BEQZC V0, 0xBFD02AD8\r
1827: {\r
1828: pxQueue->u.pcReadFrom = ( pxQueue->pcTail - pxQueue->uxItemSize );\r
-BFD02ABE 0020FC5E LW V0, 32(S8)
-BFD02AC2 69A1 LW V1, 4(V0)
-BFD02AC4 0020FC5E LW V0, 32(S8)
-BFD02AC8 0040FC42 LW V0, 64(V0)
-BFD02ACA 00400040 SRL V0, ZERO, 0
-BFD02ACC 11D00040 SUBU V0, ZERO, V0
-BFD02ACE 05A611D0 ADDI T6, S0, 1446
-BFD02AD0 05A6 ADDU V1, V1, V0
-BFD02AD2 0020FC5E LW V0, 32(S8)
-BFD02AD6 E9A3 SW V1, 12(V0)
+BFD02ABE 0020FC5E LW V0, 32(S8)\r
+BFD02AC2 69A1 LW V1, 4(V0)\r
+BFD02AC4 0020FC5E LW V0, 32(S8)\r
+BFD02AC8 0040FC42 LW V0, 64(V0)\r
+BFD02ACA 00400040 SRL V0, ZERO, 0\r
+BFD02ACC 11D00040 SUBU V0, ZERO, V0\r
+BFD02ACE 05A611D0 ADDI T6, S0, 1446\r
+BFD02AD0 05A6 ADDU V1, V1, V0\r
+BFD02AD2 0020FC5E LW V0, 32(S8)\r
+BFD02AD6 E9A3 SW V1, 12(V0)\r
1829: }\r
1830: else\r
1831: {\r
1833: }\r
1834: \r
1835: if( xPosition == queueOVERWRITE )\r
-BFD02AD8 0028FC7E LW V1, 40(S8)
-BFD02ADC ED02 LI V0, 2
-BFD02ADE 000DB443 BNE V1, V0, 0xBFD02AFC
-BFD02AE0 0C00000D SLL ZERO, T5, 1
-BFD02AE2 0C00 NOP
+BFD02AD8 0028FC7E LW V1, 40(S8)\r
+BFD02ADC ED02 LI V0, 2\r
+BFD02ADE 000DB443 BNE V1, V0, 0xBFD02AFC\r
+BFD02AE0 0C00000D SLL ZERO, T5, 1\r
+BFD02AE2 0C00 NOP\r
1836: {\r
1837: if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )\r
-BFD02AE4 0020FC5E LW V0, 32(S8)
-BFD02AE8 692E LW V0, 56(V0)
-BFD02AEA 000740E2 BEQZC V0, 0xBFD02AFC
+BFD02AE4 0020FC5E LW V0, 32(S8)\r
+BFD02AE8 692E LW V0, 56(V0)\r
+BFD02AEA 000740E2 BEQZC V0, 0xBFD02AFC\r
1838: {\r
1839: /* An item is not being added but overwritten, so subtract\r
1840: one from the recorded number of items in the queue so when\r
1841: one is added again below the number of recorded items remains\r
1842: correct. */\r
1843: --( pxQueue->uxMessagesWaiting );\r
-BFD02AEE 0020FC5E LW V0, 32(S8)
-BFD02AF2 692E LW V0, 56(V0)
-BFD02AF4 6DAE ADDIU V1, V0, -1
-BFD02AF6 0020FC5E LW V0, 32(S8)
-BFD02AFA E9AE SW V1, 56(V0)
+BFD02AEE 0020FC5E LW V0, 32(S8)\r
+BFD02AF2 692E LW V0, 56(V0)\r
+BFD02AF4 6DAE ADDIU V1, V0, -1\r
+BFD02AF6 0020FC5E LW V0, 32(S8)\r
+BFD02AFA E9AE SW V1, 56(V0)\r
1844: }\r
1845: else\r
1846: {\r
1854: }\r
1855: \r
1856: ++( pxQueue->uxMessagesWaiting );\r
-BFD02AFC 0020FC5E LW V0, 32(S8)
-BFD02B00 692E LW V0, 56(V0)
-BFD02B02 6DA0 ADDIU V1, V0, 1
-BFD02B04 0020FC5E LW V0, 32(S8)
-BFD02B08 E9AE SW V1, 56(V0)
+BFD02AFC 0020FC5E LW V0, 32(S8)\r
+BFD02B00 692E LW V0, 56(V0)\r
+BFD02B02 6DA0 ADDIU V1, V0, 1\r
+BFD02B04 0020FC5E LW V0, 32(S8)\r
+BFD02B08 E9AE SW V1, 56(V0)\r
1857: \r
1858: return xReturn;\r
-BFD02B0A 0010FC5E LW V0, 16(S8)
+BFD02B0A 0010FC5E LW V0, 16(S8)\r
1859: }\r
-BFD02B0E 0FBE MOVE SP, S8
-BFD02B10 4BE7 LW RA, 28(SP)
-BFD02B12 4BC6 LW S8, 24(SP)
-BFD02B14 4C11 ADDIU SP, SP, 32
-BFD02B16 459F JR16 RA
-BFD02B18 0C00 NOP
+BFD02B0E 0FBE MOVE SP, S8\r
+BFD02B10 4BE7 LW RA, 28(SP)\r
+BFD02B12 4BC6 LW S8, 24(SP)\r
+BFD02B14 4C11 ADDIU SP, SP, 32\r
+BFD02B16 459F JR16 RA\r
+BFD02B18 0C00 NOP\r
1860: /*-----------------------------------------------------------*/\r
1861: \r
1862: static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )\r
1863: {\r
-BFD06CF4 4FF5 ADDIU SP, SP, -24
-BFD06CF6 CBE5 SW RA, 20(SP)
-BFD06CF8 CBC4 SW S8, 16(SP)
-BFD06CFA 0FDD MOVE S8, SP
-BFD06CFC 0018F89E SW A0, 24(S8)
-BFD06D00 001CF8BE SW A1, 28(S8)
+BFD06CF4 4FF5 ADDIU SP, SP, -24\r
+BFD06CF6 CBE5 SW RA, 20(SP)\r
+BFD06CF8 CBC4 SW S8, 16(SP)\r
+BFD06CFA 0FDD MOVE S8, SP\r
+BFD06CFC 0018F89E SW A0, 24(S8)\r
+BFD06D00 001CF8BE SW A1, 28(S8)\r
1864: if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )\r
-BFD06D04 0018FC5E LW V0, 24(S8)
-BFD06D08 0040FC42 LW V0, 64(V0)
-BFD06D0C 002940E2 BEQZC V0, 0xBFD06D62
+BFD06D04 0018FC5E LW V0, 24(S8)\r
+BFD06D08 0040FC42 LW V0, 64(V0)\r
+BFD06D0C 002940E2 BEQZC V0, 0xBFD06D62\r
1865: {\r
1866: pxQueue->u.pcReadFrom += pxQueue->uxItemSize;\r
-BFD06D10 0018FC5E LW V0, 24(S8)
-BFD06D14 69A3 LW V1, 12(V0)
-BFD06D16 0018FC5E LW V0, 24(S8)
-BFD06D1A 0040FC42 LW V0, 64(V0)
-BFD06D1E 05A6 ADDU V1, V1, V0
-BFD06D20 0018FC5E LW V0, 24(S8)
-BFD06D24 E9A3 SW V1, 12(V0)
+BFD06D10 0018FC5E LW V0, 24(S8)\r
+BFD06D14 69A3 LW V1, 12(V0)\r
+BFD06D16 0018FC5E LW V0, 24(S8)\r
+BFD06D1A 0040FC42 LW V0, 64(V0)\r
+BFD06D1E 05A6 ADDU V1, V1, V0\r
+BFD06D20 0018FC5E LW V0, 24(S8)\r
+BFD06D24 E9A3 SW V1, 12(V0)\r
1867: if( pxQueue->u.pcReadFrom >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */\r
-BFD06D26 0018FC5E LW V0, 24(S8)
-BFD06D2A 69A3 LW V1, 12(V0)
-BFD06D2C 0018FC5E LW V0, 24(S8)
-BFD06D30 6921 LW V0, 4(V0)
-BFD06D32 13900043 SLTU V0, V1, V0
-BFD06D34 40A21390 ADDI GP, S0, 16546
-BFD06D36 000640A2 BNEZC V0, 0xBFD06D46
+BFD06D26 0018FC5E LW V0, 24(S8)\r
+BFD06D2A 69A3 LW V1, 12(V0)\r
+BFD06D2C 0018FC5E LW V0, 24(S8)\r
+BFD06D30 6921 LW V0, 4(V0)\r
+BFD06D32 13900043 SLTU V0, V1, V0\r
+BFD06D34 40A21390 ADDI GP, S0, 16546\r
+BFD06D36 000640A2 BNEZC V0, 0xBFD06D46\r
1868: {\r
1869: pxQueue->u.pcReadFrom = pxQueue->pcHead;\r
-BFD06D3A 0018FC5E LW V0, 24(S8)
-BFD06D3E 69A0 LW V1, 0(V0)
-BFD06D40 0018FC5E LW V0, 24(S8)
-BFD06D44 E9A3 SW V1, 12(V0)
+BFD06D3A 0018FC5E LW V0, 24(S8)\r
+BFD06D3E 69A0 LW V1, 0(V0)\r
+BFD06D40 0018FC5E LW V0, 24(S8)\r
+BFD06D44 E9A3 SW V1, 12(V0)\r
1870: }\r
1871: else\r
1872: {\r
1873: mtCOVERAGE_TEST_MARKER();\r
1874: }\r
1875: ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. */\r
-BFD06D46 0018FC5E LW V0, 24(S8)
-BFD06D4A 69A3 LW V1, 12(V0)
-BFD06D4C 0018FC5E LW V0, 24(S8)
-BFD06D50 0040FC42 LW V0, 64(V0)
-BFD06D54 001CFC9E LW A0, 28(S8)
-BFD06D58 0CA3 MOVE A1, V1
-BFD06D5A 0CC2 MOVE A2, V0
-BFD06D5C 1BB477E8 JALS 0xBFD03768
-BFD06D5E 0C001BB4 SB SP, 3072(S4)
-BFD06D60 0C00 NOP
+BFD06D46 0018FC5E LW V0, 24(S8)\r
+BFD06D4A 69A3 LW V1, 12(V0)\r
+BFD06D4C 0018FC5E LW V0, 24(S8)\r
+BFD06D50 0040FC42 LW V0, 64(V0)\r
+BFD06D54 001CFC9E LW A0, 28(S8)\r
+BFD06D58 0CA3 MOVE A1, V1\r
+BFD06D5A 0CC2 MOVE A2, V0\r
+BFD06D5C 1BB477E8 JALS 0xBFD03768\r
+BFD06D5E 0C001BB4 SB SP, 3072(S4)\r
+BFD06D60 0C00 NOP\r
1876: }\r
1877: }\r
-BFD06D62 0FBE MOVE SP, S8
-BFD06D64 4BE5 LW RA, 20(SP)
-BFD06D66 4BC4 LW S8, 16(SP)
-BFD06D68 4C0D ADDIU SP, SP, 24
-BFD06D6A 459F JR16 RA
-BFD06D6C 0C00 NOP
+BFD06D62 0FBE MOVE SP, S8\r
+BFD06D64 4BE5 LW RA, 20(SP)\r
+BFD06D66 4BC4 LW S8, 16(SP)\r
+BFD06D68 4C0D ADDIU SP, SP, 24\r
+BFD06D6A 459F JR16 RA\r
+BFD06D6C 0C00 NOP\r
1878: /*-----------------------------------------------------------*/\r
1879: \r
1880: static void prvUnlockQueue( Queue_t * const pxQueue )\r
1881: {\r
-BFD03BDC 4FF5 ADDIU SP, SP, -24
-BFD03BDE CBE5 SW RA, 20(SP)
-BFD03BE0 CBC4 SW S8, 16(SP)
-BFD03BE2 0FDD MOVE S8, SP
-BFD03BE4 0018F89E SW A0, 24(S8)
+BFD03BDC 4FF5 ADDIU SP, SP, -24\r
+BFD03BDE CBE5 SW RA, 20(SP)\r
+BFD03BE0 CBC4 SW S8, 16(SP)\r
+BFD03BE2 0FDD MOVE S8, SP\r
+BFD03BE4 0018F89E SW A0, 24(S8)\r
1882: /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */\r
1883: \r
1884: /* The lock counts contains the number of extra data items placed or\r
1886: locked items can be added or removed, but the event lists cannot be\r
1887: updated. */\r
1888: taskENTER_CRITICAL();\r
-BFD03BE8 33B877E8 JALS vTaskEnterCritical
-BFD03BEA 0C0033B8 ADDIU SP, T8, 3072
-BFD03BEC 0C00 NOP
+BFD03BE8 33B877E8 JALS vTaskEnterCritical\r
+BFD03BEA 0C0033B8 ADDIU SP, T8, 3072\r
+BFD03BEC 0C00 NOP\r
1889: {\r
1890: /* See if data was added to the queue while it was locked. */\r
1891: while( pxQueue->xTxLock > queueLOCKED_UNMODIFIED )\r
-BFD03BEE CC32 B 0xBFD03C54
-BFD03BF0 0C00 NOP
-BFD03C54 0018FC5E LW V0, 24(S8)
-BFD03C58 0048FC42 LW V0, 72(V0)
-BFD03C5C FFC940C2 BGTZ V0, 0xBFD03BF2
-BFD03C5E 0C00FFC9 LW S8, 3072(T1)
-BFD03C60 0C00 NOP
-BFD03C62 CC02 B 0xBFD03C68
-BFD03C64 0C00 NOP
+BFD03BEE CC32 B 0xBFD03C54\r
+BFD03BF0 0C00 NOP\r
+BFD03C54 0018FC5E LW V0, 24(S8)\r
+BFD03C58 0048FC42 LW V0, 72(V0)\r
+BFD03C5C FFC940C2 BGTZ V0, 0xBFD03BF2\r
+BFD03C5E 0C00FFC9 LW S8, 3072(T1)\r
+BFD03C60 0C00 NOP\r
+BFD03C62 CC02 B 0xBFD03C68\r
+BFD03C64 0C00 NOP\r
1892: {\r
1893: /* Data was posted while the queue was locked. Are any tasks\r
1894: blocked waiting for data to become available? */\r
1895: #if ( configUSE_QUEUE_SETS == 1 )\r
1896: {\r
1897: if( pxQueue->pxQueueSetContainer != NULL )\r
-BFD03BF2 0018FC5E LW V0, 24(S8)
-BFD03BF6 004CFC42 LW V0, 76(V0)
-BFD03BFA 001040E2 BEQZC V0, 0xBFD03C1E
+BFD03BF2 0018FC5E LW V0, 24(S8)\r
+BFD03BF6 004CFC42 LW V0, 76(V0)\r
+BFD03BFA 001040E2 BEQZC V0, 0xBFD03C1E\r
1898: {\r
1899: if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) == pdTRUE )\r
-BFD03BFE 0018FC9E LW A0, 24(S8)
-BFD03C02 0CA0 MOVE A1, ZERO
-BFD03C04 21D877E8 JALS prvNotifyQueueSetContainer
-BFD03C06 0C0021D8 LWC2 T6, 3072(T8)
-BFD03C08 0C00 NOP
-BFD03C0A 0C62 MOVE V1, V0
-BFD03C0C ED01 LI V0, 1
-BFD03C0E 0018B443 BNE V1, V0, 0xBFD03C42
-BFD03C10 0C000018 SLL ZERO, T8, 1
-BFD03C12 0C00 NOP
+BFD03BFE 0018FC9E LW A0, 24(S8)\r
+BFD03C02 0CA0 MOVE A1, ZERO\r
+BFD03C04 21D877E8 JALS prvNotifyQueueSetContainer\r
+BFD03C06 0C0021D8 LWC2 T6, 3072(T8)\r
+BFD03C08 0C00 NOP\r
+BFD03C0A 0C62 MOVE V1, V0\r
+BFD03C0C ED01 LI V0, 1\r
+BFD03C0E 0018B443 BNE V1, V0, 0xBFD03C42\r
+BFD03C10 0C000018 SLL ZERO, T8, 1\r
+BFD03C12 0C00 NOP\r
1900: {\r
1901: /* The queue is a member of a queue set, and posting to\r
1902: the queue set caused a higher priority task to unblock.\r
1903: A context switch is required. */\r
1904: vTaskMissedYield();\r
-BFD03C14 4F2A77E8 JALS vTaskMissedYield
-BFD03C16 4F2A ADDIU T9, T9, 5
-BFD03C18 0C00 NOP
-BFD03C1A CC13 B 0xBFD03C42
-BFD03C1C 0C00 NOP
+BFD03C14 4F2A77E8 JALS vTaskMissedYield\r
+BFD03C16 4F2A ADDIU T9, T9, 5\r
+BFD03C18 0C00 NOP\r
+BFD03C1A CC13 B 0xBFD03C42\r
+BFD03C1C 0C00 NOP\r
1905: }\r
1906: else\r
1907: {\r
1913: /* Tasks that are removed from the event list will get added to\r
1914: the pending ready list as the scheduler is still suspended. */\r
1915: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
-BFD03C1E 0018FC5E LW V0, 24(S8)
-BFD03C22 6929 LW V0, 36(V0)
-BFD03C24 001F40E2 BEQZC V0, 0xBFD03C66
+BFD03C1E 0018FC5E LW V0, 24(S8)\r
+BFD03C22 6929 LW V0, 36(V0)\r
+BFD03C24 001F40E2 BEQZC V0, 0xBFD03C66\r
1916: {\r
1917: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
-BFD03C28 0018FC5E LW V0, 24(S8)
-BFD03C2C 00243042 ADDIU V0, V0, 36
-BFD03C30 0C82 MOVE A0, V0
-BFD03C32 22BC77E8 JALS xTaskRemoveFromEventList
-BFD03C34 0C0022BC LWC2 S5, 3072(GP)
-BFD03C36 0C00 NOP
-BFD03C38 000340E2 BEQZC V0, 0xBFD03C42
+BFD03C28 0018FC5E LW V0, 24(S8)\r
+BFD03C2C 00243042 ADDIU V0, V0, 36\r
+BFD03C30 0C82 MOVE A0, V0\r
+BFD03C32 22BC77E8 JALS xTaskRemoveFromEventList\r
+BFD03C34 0C0022BC LWC2 S5, 3072(GP)\r
+BFD03C36 0C00 NOP\r
+BFD03C38 000340E2 BEQZC V0, 0xBFD03C42\r
1918: {\r
1919: /* The task waiting has a higher priority so record that a\r
1920: context switch is required. */\r
1921: vTaskMissedYield();\r
-BFD03C3C 4F2A77E8 JALS vTaskMissedYield
-BFD03C3E 4F2A ADDIU T9, T9, 5
-BFD03C40 0C00 NOP
+BFD03C3C 4F2A77E8 JALS vTaskMissedYield\r
+BFD03C3E 4F2A ADDIU T9, T9, 5\r
+BFD03C40 0C00 NOP\r
1922: }\r
1923: else\r
1924: {\r
1928: else\r
1929: {\r
1930: break;\r
-BFD03C66 0C00 NOP
+BFD03C66 0C00 NOP\r
1931: }\r
1932: }\r
1933: }\r
1956: #endif /* configUSE_QUEUE_SETS */\r
1957: \r
1958: --( pxQueue->xTxLock );\r
-BFD03C42 0018FC5E LW V0, 24(S8)
-BFD03C46 0048FC42 LW V0, 72(V0)
-BFD03C4A 6DAE ADDIU V1, V0, -1
-BFD03C4C 0018FC5E LW V0, 24(S8)
-BFD03C50 0048F862 SW V1, 72(V0)
+BFD03C42 0018FC5E LW V0, 24(S8)\r
+BFD03C46 0048FC42 LW V0, 72(V0)\r
+BFD03C4A 6DAE ADDIU V1, V0, -1\r
+BFD03C4C 0018FC5E LW V0, 24(S8)\r
+BFD03C50 0048F862 SW V1, 72(V0)\r
1959: }\r
1960: \r
1961: pxQueue->xTxLock = queueUNLOCKED;\r
-BFD03C68 0018FC5E LW V0, 24(S8)
-BFD03C6C EDFF LI V1, -1
-BFD03C6E 0048F862 SW V1, 72(V0)
+BFD03C68 0018FC5E LW V0, 24(S8)\r
+BFD03C6C EDFF LI V1, -1\r
+BFD03C6E 0048F862 SW V1, 72(V0)\r
1962: }\r
1963: taskEXIT_CRITICAL();\r
-BFD03C72 40AA77E8 JALS vTaskExitCritical
-BFD03C74 0C0040AA BNEZC T2, 0xBFD05478
-BFD03C76 0C00 NOP
+BFD03C72 40AA77E8 JALS vTaskExitCritical\r
+BFD03C74 0C0040AA BNEZC T2, 0xBFD05478\r
+BFD03C76 0C00 NOP\r
1964: \r
1965: /* Do the same for the Rx lock. */\r
1966: taskENTER_CRITICAL();\r
-BFD03C78 33B877E8 JALS vTaskEnterCritical
-BFD03C7A 0C0033B8 ADDIU SP, T8, 3072
-BFD03C7C 0C00 NOP
+BFD03C78 33B877E8 JALS vTaskEnterCritical\r
+BFD03C7A 0C0033B8 ADDIU SP, T8, 3072\r
+BFD03C7C 0C00 NOP\r
1967: {\r
1968: while( pxQueue->xRxLock > queueLOCKED_UNMODIFIED )\r
-BFD03C7E CC1B B 0xBFD03CB6
-BFD03C80 0C00 NOP
-BFD03CB6 0018FC5E LW V0, 24(S8)
-BFD03CBA 0044FC42 LW V0, 68(V0)
-BFD03CBE FFE040C2 BGTZ V0, 0xBFD03C82
-BFD03CC0 0C00FFE0 LW RA, 3072(ZERO)
-BFD03CC2 0C00 NOP
-BFD03CC4 CC02 B 0xBFD03CCA
-BFD03CC6 0C00 NOP
+BFD03C7E CC1B B 0xBFD03CB6\r
+BFD03C80 0C00 NOP\r
+BFD03CB6 0018FC5E LW V0, 24(S8)\r
+BFD03CBA 0044FC42 LW V0, 68(V0)\r
+BFD03CBE FFE040C2 BGTZ V0, 0xBFD03C82\r
+BFD03CC0 0C00FFE0 LW RA, 3072(ZERO)\r
+BFD03CC2 0C00 NOP\r
+BFD03CC4 CC02 B 0xBFD03CCA\r
+BFD03CC6 0C00 NOP\r
1969: {\r
1970: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r
-BFD03C82 0018FC5E LW V0, 24(S8)
-BFD03C86 6924 LW V0, 16(V0)
-BFD03C88 001E40E2 BEQZC V0, 0xBFD03CC8
+BFD03C82 0018FC5E LW V0, 24(S8)\r
+BFD03C86 6924 LW V0, 16(V0)\r
+BFD03C88 001E40E2 BEQZC V0, 0xBFD03CC8\r
1971: {\r
1972: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\r
-BFD03C8C 0018FC5E LW V0, 24(S8)
-BFD03C90 6D28 ADDIU V0, V0, 16
-BFD03C92 0C82 MOVE A0, V0
-BFD03C94 22BC77E8 JALS xTaskRemoveFromEventList
-BFD03C96 0C0022BC LWC2 S5, 3072(GP)
-BFD03C98 0C00 NOP
-BFD03C9A 000340E2 BEQZC V0, 0xBFD03CA4
+BFD03C8C 0018FC5E LW V0, 24(S8)\r
+BFD03C90 6D28 ADDIU V0, V0, 16\r
+BFD03C92 0C82 MOVE A0, V0\r
+BFD03C94 22BC77E8 JALS xTaskRemoveFromEventList\r
+BFD03C96 0C0022BC LWC2 S5, 3072(GP)\r
+BFD03C98 0C00 NOP\r
+BFD03C9A 000340E2 BEQZC V0, 0xBFD03CA4\r
1973: {\r
1974: vTaskMissedYield();\r
-BFD03C9E 4F2A77E8 JALS vTaskMissedYield
-BFD03CA0 4F2A ADDIU T9, T9, 5
-BFD03CA2 0C00 NOP
+BFD03C9E 4F2A77E8 JALS vTaskMissedYield\r
+BFD03CA0 4F2A ADDIU T9, T9, 5\r
+BFD03CA2 0C00 NOP\r
1975: }\r
1976: else\r
1977: {\r
1979: }\r
1980: \r
1981: --( pxQueue->xRxLock );\r
-BFD03CA4 0018FC5E LW V0, 24(S8)
-BFD03CA8 0044FC42 LW V0, 68(V0)
-BFD03CAC 6DAE ADDIU V1, V0, -1
-BFD03CAE 0018FC5E LW V0, 24(S8)
-BFD03CB2 0044F862 SW V1, 68(V0)
+BFD03CA4 0018FC5E LW V0, 24(S8)\r
+BFD03CA8 0044FC42 LW V0, 68(V0)\r
+BFD03CAC 6DAE ADDIU V1, V0, -1\r
+BFD03CAE 0018FC5E LW V0, 24(S8)\r
+BFD03CB2 0044F862 SW V1, 68(V0)\r
1982: }\r
1983: else\r
1984: {\r
1985: break;\r
-BFD03CC8 0C00 NOP
+BFD03CC8 0C00 NOP\r
1986: }\r
1987: }\r
1988: \r
1989: pxQueue->xRxLock = queueUNLOCKED;\r
-BFD03CCA 0018FC5E LW V0, 24(S8)
-BFD03CCE EDFF LI V1, -1
-BFD03CD0 0044F862 SW V1, 68(V0)
+BFD03CCA 0018FC5E LW V0, 24(S8)\r
+BFD03CCE EDFF LI V1, -1\r
+BFD03CD0 0044F862 SW V1, 68(V0)\r
1990: }\r
1991: taskEXIT_CRITICAL();\r
-BFD03CD4 40AA77E8 JALS vTaskExitCritical
-BFD03CD6 0C0040AA BNEZC T2, 0xBFD054DA
-BFD03CD8 0C00 NOP
+BFD03CD4 40AA77E8 JALS vTaskExitCritical\r
+BFD03CD6 0C0040AA BNEZC T2, 0xBFD054DA\r
+BFD03CD8 0C00 NOP\r
1992: }\r
-BFD03CDA 0FBE MOVE SP, S8
-BFD03CDC 4BE5 LW RA, 20(SP)
-BFD03CDE 4BC4 LW S8, 16(SP)
-BFD03CE0 4C0D ADDIU SP, SP, 24
-BFD03CE2 459F JR16 RA
-BFD03CE4 0C00 NOP
+BFD03CDA 0FBE MOVE SP, S8\r
+BFD03CDC 4BE5 LW RA, 20(SP)\r
+BFD03CDE 4BC4 LW S8, 16(SP)\r
+BFD03CE0 4C0D ADDIU SP, SP, 24\r
+BFD03CE2 459F JR16 RA\r
+BFD03CE4 0C00 NOP\r
1993: /*-----------------------------------------------------------*/\r
1994: \r
1995: static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )\r
1996: {\r
-BFD093A0 4FF1 ADDIU SP, SP, -32
-BFD093A2 CBE7 SW RA, 28(SP)
-BFD093A4 CBC6 SW S8, 24(SP)
-BFD093A6 0FDD MOVE S8, SP
-BFD093A8 0020F89E SW A0, 32(S8)
+BFD093A0 4FF1 ADDIU SP, SP, -32\r
+BFD093A2 CBE7 SW RA, 28(SP)\r
+BFD093A4 CBC6 SW S8, 24(SP)\r
+BFD093A6 0FDD MOVE S8, SP\r
+BFD093A8 0020F89E SW A0, 32(S8)\r
1997: BaseType_t xReturn;\r
1998: \r
1999: taskENTER_CRITICAL();\r
-BFD093AC 33B877E8 JALS vTaskEnterCritical
-BFD093AE 0C0033B8 ADDIU SP, T8, 3072
-BFD093B0 0C00 NOP
+BFD093AC 33B877E8 JALS vTaskEnterCritical\r
+BFD093AE 0C0033B8 ADDIU SP, T8, 3072\r
+BFD093B0 0C00 NOP\r
2000: {\r
2001: if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )\r
-BFD093B2 0020FC5E LW V0, 32(S8)
-BFD093B6 692E LW V0, 56(V0)
-BFD093B8 000540A2 BNEZC V0, 0xBFD093C6
+BFD093B2 0020FC5E LW V0, 32(S8)\r
+BFD093B6 692E LW V0, 56(V0)\r
+BFD093B8 000540A2 BNEZC V0, 0xBFD093C6\r
2002: {\r
2003: xReturn = pdTRUE;\r
-BFD093BC ED01 LI V0, 1
-BFD093BE 0010F85E SW V0, 16(S8)
-BFD093C2 CC03 B 0xBFD093CA
-BFD093C4 0C00 NOP
+BFD093BC ED01 LI V0, 1\r
+BFD093BE 0010F85E SW V0, 16(S8)\r
+BFD093C2 CC03 B 0xBFD093CA\r
+BFD093C4 0C00 NOP\r
2004: }\r
2005: else\r
2006: {\r
2007: xReturn = pdFALSE;\r
-BFD093C6 0010F81E SW ZERO, 16(S8)
+BFD093C6 0010F81E SW ZERO, 16(S8)\r
2008: }\r
2009: }\r
2010: taskEXIT_CRITICAL();\r
-BFD093CA 40AA77E8 JALS vTaskExitCritical
-BFD093CC 0C0040AA BNEZC T2, 0xBFD0ABD0
-BFD093CE 0C00 NOP
+BFD093CA 40AA77E8 JALS vTaskExitCritical\r
+BFD093CC 0C0040AA BNEZC T2, 0xBFD0ABD0\r
+BFD093CE 0C00 NOP\r
2011: \r
2012: return xReturn;\r
-BFD093D0 0010FC5E LW V0, 16(S8)
+BFD093D0 0010FC5E LW V0, 16(S8)\r
2013: }\r
-BFD093D4 0FBE MOVE SP, S8
-BFD093D6 4BE7 LW RA, 28(SP)
-BFD093D8 4BC6 LW S8, 24(SP)
-BFD093DA 4C11 ADDIU SP, SP, 32
-BFD093DC 459F JR16 RA
-BFD093DE 0C00 NOP
+BFD093D4 0FBE MOVE SP, S8\r
+BFD093D6 4BE7 LW RA, 28(SP)\r
+BFD093D8 4BC6 LW S8, 24(SP)\r
+BFD093DA 4C11 ADDIU SP, SP, 32\r
+BFD093DC 459F JR16 RA\r
+BFD093DE 0C00 NOP\r
2014: /*-----------------------------------------------------------*/\r
2015: \r
2016: BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )\r
2017: {\r
-BFD08954 4FF1 ADDIU SP, SP, -32
-BFD08956 CBE7 SW RA, 28(SP)
-BFD08958 CBC6 SW S8, 24(SP)
-BFD0895A 0FDD MOVE S8, SP
-BFD0895C 0020F89E SW A0, 32(S8)
+BFD08954 4FF1 ADDIU SP, SP, -32\r
+BFD08956 CBE7 SW RA, 28(SP)\r
+BFD08958 CBC6 SW S8, 24(SP)\r
+BFD0895A 0FDD MOVE S8, SP\r
+BFD0895C 0020F89E SW A0, 32(S8)\r
2018: BaseType_t xReturn;\r
2019: \r
2020: configASSERT( xQueue );\r
-BFD08960 0020FC5E LW V0, 32(S8)
-BFD08964 000940A2 BNEZC V0, 0xBFD0897A
-BFD08968 BFD141A2 LUI V0, 0xBFD1
-BFD0896A 3082BFD1 LDC1 F30, 12418(S1)
-BFD0896C 9E3C3082 ADDIU A0, V0, -25028
-BFD0896E 30A09E3C LWC1 F17, 12448(GP)
-BFD08970 07E430A0 ADDIU A1, ZERO, 2020
-BFD08972 07E4 ADDU A3, V0, A2
-BFD08974 4B7E77E8 JALS vAssertCalled
-BFD08976 4B7E LW K1, 120(SP)
-BFD08978 0C00 NOP
+BFD08960 0020FC5E LW V0, 32(S8)\r
+BFD08964 000940A2 BNEZC V0, 0xBFD0897A\r
+BFD08968 BFD141A2 LUI V0, 0xBFD1\r
+BFD0896A 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD0896C 9E3C3082 ADDIU A0, V0, -25028\r
+BFD0896E 30A09E3C LWC1 F17, 12448(GP)\r
+BFD08970 07E430A0 ADDIU A1, ZERO, 2020\r
+BFD08972 07E4 ADDU A3, V0, A2\r
+BFD08974 4B7E77E8 JALS vAssertCalled\r
+BFD08976 4B7E LW K1, 120(SP)\r
+BFD08978 0C00 NOP\r
2021: if( ( ( Queue_t * ) xQueue )->uxMessagesWaiting == ( UBaseType_t ) 0 )\r
-BFD0897A 0020FC5E LW V0, 32(S8)
-BFD0897E 692E LW V0, 56(V0)
-BFD08980 000540A2 BNEZC V0, 0xBFD0898E
+BFD0897A 0020FC5E LW V0, 32(S8)\r
+BFD0897E 692E LW V0, 56(V0)\r
+BFD08980 000540A2 BNEZC V0, 0xBFD0898E\r
2022: {\r
2023: xReturn = pdTRUE;\r
-BFD08984 ED01 LI V0, 1
-BFD08986 0010F85E SW V0, 16(S8)
-BFD0898A CC03 B 0xBFD08992
-BFD0898C 0C00 NOP
+BFD08984 ED01 LI V0, 1\r
+BFD08986 0010F85E SW V0, 16(S8)\r
+BFD0898A CC03 B 0xBFD08992\r
+BFD0898C 0C00 NOP\r
2024: }\r
2025: else\r
2026: {\r
2027: xReturn = pdFALSE;\r
-BFD0898E 0010F81E SW ZERO, 16(S8)
+BFD0898E 0010F81E SW ZERO, 16(S8)\r
2028: }\r
2029: \r
2030: return xReturn;\r
-BFD08992 0010FC5E LW V0, 16(S8)
+BFD08992 0010FC5E LW V0, 16(S8)\r
2031: } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */\r
-BFD08996 0FBE MOVE SP, S8
-BFD08998 4BE7 LW RA, 28(SP)
-BFD0899A 4BC6 LW S8, 24(SP)
-BFD0899C 4C11 ADDIU SP, SP, 32
-BFD0899E 459F JR16 RA
-BFD089A0 0C00 NOP
+BFD08996 0FBE MOVE SP, S8\r
+BFD08998 4BE7 LW RA, 28(SP)\r
+BFD0899A 4BC6 LW S8, 24(SP)\r
+BFD0899C 4C11 ADDIU SP, SP, 32\r
+BFD0899E 459F JR16 RA\r
+BFD089A0 0C00 NOP\r
2032: /*-----------------------------------------------------------*/\r
2033: \r
2034: static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )\r
2035: {\r
-BFD08F04 4FF1 ADDIU SP, SP, -32
-BFD08F06 CBE7 SW RA, 28(SP)
-BFD08F08 CBC6 SW S8, 24(SP)
-BFD08F0A 0FDD MOVE S8, SP
-BFD08F0C 0020F89E SW A0, 32(S8)
+BFD08F04 4FF1 ADDIU SP, SP, -32\r
+BFD08F06 CBE7 SW RA, 28(SP)\r
+BFD08F08 CBC6 SW S8, 24(SP)\r
+BFD08F0A 0FDD MOVE S8, SP\r
+BFD08F0C 0020F89E SW A0, 32(S8)\r
2036: BaseType_t xReturn;\r
2037: \r
2038: taskENTER_CRITICAL();\r
-BFD08F10 33B877E8 JALS vTaskEnterCritical
-BFD08F12 0C0033B8 ADDIU SP, T8, 3072
-BFD08F14 0C00 NOP
+BFD08F10 33B877E8 JALS vTaskEnterCritical\r
+BFD08F12 0C0033B8 ADDIU SP, T8, 3072\r
+BFD08F14 0C00 NOP\r
2039: {\r
2040: if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )\r
-BFD08F16 0020FC5E LW V0, 32(S8)
-BFD08F1A 69AE LW V1, 56(V0)
-BFD08F1C 0020FC5E LW V0, 32(S8)
-BFD08F20 692F LW V0, 60(V0)
-BFD08F22 0006B443 BNE V1, V0, 0xBFD08F32
-BFD08F24 0C000006 SLL ZERO, A2, 1
-BFD08F26 0C00 NOP
+BFD08F16 0020FC5E LW V0, 32(S8)\r
+BFD08F1A 69AE LW V1, 56(V0)\r
+BFD08F1C 0020FC5E LW V0, 32(S8)\r
+BFD08F20 692F LW V0, 60(V0)\r
+BFD08F22 0006B443 BNE V1, V0, 0xBFD08F32\r
+BFD08F24 0C000006 SLL ZERO, A2, 1\r
+BFD08F26 0C00 NOP\r
2041: {\r
2042: xReturn = pdTRUE;\r
-BFD08F28 ED01 LI V0, 1
-BFD08F2A 0010F85E SW V0, 16(S8)
-BFD08F2E CC03 B 0xBFD08F36
-BFD08F30 0C00 NOP
+BFD08F28 ED01 LI V0, 1\r
+BFD08F2A 0010F85E SW V0, 16(S8)\r
+BFD08F2E CC03 B 0xBFD08F36\r
+BFD08F30 0C00 NOP\r
2043: }\r
2044: else\r
2045: {\r
2046: xReturn = pdFALSE;\r
-BFD08F32 0010F81E SW ZERO, 16(S8)
+BFD08F32 0010F81E SW ZERO, 16(S8)\r
2047: }\r
2048: }\r
2049: taskEXIT_CRITICAL();\r
-BFD08F36 40AA77E8 JALS vTaskExitCritical
-BFD08F38 0C0040AA BNEZC T2, 0xBFD0A73C
-BFD08F3A 0C00 NOP
+BFD08F36 40AA77E8 JALS vTaskExitCritical\r
+BFD08F38 0C0040AA BNEZC T2, 0xBFD0A73C\r
+BFD08F3A 0C00 NOP\r
2050: \r
2051: return xReturn;\r
-BFD08F3C 0010FC5E LW V0, 16(S8)
+BFD08F3C 0010FC5E LW V0, 16(S8)\r
2052: }\r
-BFD08F40 0FBE MOVE SP, S8
-BFD08F42 4BE7 LW RA, 28(SP)
-BFD08F44 4BC6 LW S8, 24(SP)
-BFD08F46 4C11 ADDIU SP, SP, 32
-BFD08F48 459F JR16 RA
-BFD08F4A 0C00 NOP
+BFD08F40 0FBE MOVE SP, S8\r
+BFD08F42 4BE7 LW RA, 28(SP)\r
+BFD08F44 4BC6 LW S8, 24(SP)\r
+BFD08F46 4C11 ADDIU SP, SP, 32\r
+BFD08F48 459F JR16 RA\r
+BFD08F4A 0C00 NOP\r
2053: /*-----------------------------------------------------------*/\r
2054: \r
2055: BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )\r
2056: {\r
-BFD084F8 4FF1 ADDIU SP, SP, -32
-BFD084FA CBE7 SW RA, 28(SP)
-BFD084FC CBC6 SW S8, 24(SP)
-BFD084FE 0FDD MOVE S8, SP
-BFD08500 0020F89E SW A0, 32(S8)
+BFD084F8 4FF1 ADDIU SP, SP, -32\r
+BFD084FA CBE7 SW RA, 28(SP)\r
+BFD084FC CBC6 SW S8, 24(SP)\r
+BFD084FE 0FDD MOVE S8, SP\r
+BFD08500 0020F89E SW A0, 32(S8)\r
2057: BaseType_t xReturn;\r
2058: \r
2059: configASSERT( xQueue );\r
-BFD08504 0020FC5E LW V0, 32(S8)
-BFD08508 000940A2 BNEZC V0, 0xBFD0851E
-BFD0850C BFD141A2 LUI V0, 0xBFD1
-BFD0850E 3082BFD1 LDC1 F30, 12418(S1)
-BFD08510 9E3C3082 ADDIU A0, V0, -25028
-BFD08512 30A09E3C LWC1 F17, 12448(GP)
-BFD08514 080B30A0 ADDIU A1, ZERO, 2059
-BFD08516 080B LBU S0, 11(S0)
-BFD08518 4B7E77E8 JALS vAssertCalled
-BFD0851A 4B7E LW K1, 120(SP)
-BFD0851C 0C00 NOP
+BFD08504 0020FC5E LW V0, 32(S8)\r
+BFD08508 000940A2 BNEZC V0, 0xBFD0851E\r
+BFD0850C BFD141A2 LUI V0, 0xBFD1\r
+BFD0850E 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD08510 9E3C3082 ADDIU A0, V0, -25028\r
+BFD08512 30A09E3C LWC1 F17, 12448(GP)\r
+BFD08514 080B30A0 ADDIU A1, ZERO, 2059\r
+BFD08516 080B LBU S0, 11(S0)\r
+BFD08518 4B7E77E8 JALS vAssertCalled\r
+BFD0851A 4B7E LW K1, 120(SP)\r
+BFD0851C 0C00 NOP\r
2060: if( ( ( Queue_t * ) xQueue )->uxMessagesWaiting == ( ( Queue_t * ) xQueue )->uxLength )\r
-BFD0851E 0020FC5E LW V0, 32(S8)
-BFD08522 69AE LW V1, 56(V0)
-BFD08524 0020FC5E LW V0, 32(S8)
-BFD08528 692F LW V0, 60(V0)
-BFD0852A 0006B443 BNE V1, V0, 0xBFD0853A
-BFD0852C 0C000006 SLL ZERO, A2, 1
-BFD0852E 0C00 NOP
+BFD0851E 0020FC5E LW V0, 32(S8)\r
+BFD08522 69AE LW V1, 56(V0)\r
+BFD08524 0020FC5E LW V0, 32(S8)\r
+BFD08528 692F LW V0, 60(V0)\r
+BFD0852A 0006B443 BNE V1, V0, 0xBFD0853A\r
+BFD0852C 0C000006 SLL ZERO, A2, 1\r
+BFD0852E 0C00 NOP\r
2061: {\r
2062: xReturn = pdTRUE;\r
-BFD08530 ED01 LI V0, 1
-BFD08532 0010F85E SW V0, 16(S8)
-BFD08536 CC03 B 0xBFD0853E
-BFD08538 0C00 NOP
+BFD08530 ED01 LI V0, 1\r
+BFD08532 0010F85E SW V0, 16(S8)\r
+BFD08536 CC03 B 0xBFD0853E\r
+BFD08538 0C00 NOP\r
2063: }\r
2064: else\r
2065: {\r
2066: xReturn = pdFALSE;\r
-BFD0853A 0010F81E SW ZERO, 16(S8)
+BFD0853A 0010F81E SW ZERO, 16(S8)\r
2067: }\r
2068: \r
2069: return xReturn;\r
-BFD0853E 0010FC5E LW V0, 16(S8)
+BFD0853E 0010FC5E LW V0, 16(S8)\r
2070: } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */\r
-BFD08542 0FBE MOVE SP, S8
-BFD08544 4BE7 LW RA, 28(SP)
-BFD08546 4BC6 LW S8, 24(SP)
-BFD08548 4C11 ADDIU SP, SP, 32
-BFD0854A 459F JR16 RA
-BFD0854C 0C00 NOP
+BFD08542 0FBE MOVE SP, S8\r
+BFD08544 4BE7 LW RA, 28(SP)\r
+BFD08546 4BC6 LW S8, 24(SP)\r
+BFD08548 4C11 ADDIU SP, SP, 32\r
+BFD0854A 459F JR16 RA\r
+BFD0854C 0C00 NOP\r
2071: /*-----------------------------------------------------------*/\r
2072: \r
2073: #if ( configUSE_CO_ROUTINES == 1 )\r
2405: \r
2406: void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )\r
2407: {\r
-BFD06928 4FF1 ADDIU SP, SP, -32
-BFD0692A CBE7 SW RA, 28(SP)
-BFD0692C CBC6 SW S8, 24(SP)
-BFD0692E 0FDD MOVE S8, SP
-BFD06930 0020F89E SW A0, 32(S8)
-BFD06934 0024F8BE SW A1, 36(S8)
-BFD06938 0028F8DE SW A2, 40(S8)
+BFD06928 4FF1 ADDIU SP, SP, -32\r
+BFD0692A CBE7 SW RA, 28(SP)\r
+BFD0692C CBC6 SW S8, 24(SP)\r
+BFD0692E 0FDD MOVE S8, SP\r
+BFD06930 0020F89E SW A0, 32(S8)\r
+BFD06934 0024F8BE SW A1, 36(S8)\r
+BFD06938 0028F8DE SW A2, 40(S8)\r
2408: Queue_t * const pxQueue = ( Queue_t * ) xQueue;\r
-BFD0693C 0020FC5E LW V0, 32(S8)
-BFD06940 0010F85E SW V0, 16(S8)
+BFD0693C 0020FC5E LW V0, 32(S8)\r
+BFD06940 0010F85E SW V0, 16(S8)\r
2409: \r
2410: /* This function should not be called by application code hence the\r
2411: 'Restricted' in its name. It is not part of the public API. It is\r
2422: the queue is locked, and the calling task blocks on the queue, then the\r
2423: calling task will be immediately unblocked when the queue is unlocked. */\r
2424: prvLockQueue( pxQueue );\r
-BFD06944 33B877E8 JALS vTaskEnterCritical
-BFD06946 0C0033B8 ADDIU SP, T8, 3072
-BFD06948 0C00 NOP
-BFD0694A 0010FC5E LW V0, 16(S8)
-BFD0694E 0044FC62 LW V1, 68(V0)
-BFD06952 ED7F LI V0, -1
-BFD06954 0005B443 BNE V1, V0, 0xBFD06962
-BFD06956 0C000005 SLL ZERO, A1, 1
-BFD06958 0C00 NOP
-BFD0695A 0010FC5E LW V0, 16(S8)
-BFD0695E 0044F802 SW ZERO, 68(V0)
-BFD06962 0010FC5E LW V0, 16(S8)
-BFD06966 0048FC62 LW V1, 72(V0)
-BFD0696A ED7F LI V0, -1
-BFD0696C 0005B443 BNE V1, V0, 0xBFD0697A
-BFD0696E 0C000005 SLL ZERO, A1, 1
-BFD06970 0C00 NOP
-BFD06972 0010FC5E LW V0, 16(S8)
-BFD06976 0048F802 SW ZERO, 72(V0)
-BFD0697A 40AA77E8 JALS vTaskExitCritical
-BFD0697C 0C0040AA BNEZC T2, 0xBFD08180
-BFD0697E 0C00 NOP
+BFD06944 33B877E8 JALS vTaskEnterCritical\r
+BFD06946 0C0033B8 ADDIU SP, T8, 3072\r
+BFD06948 0C00 NOP\r
+BFD0694A 0010FC5E LW V0, 16(S8)\r
+BFD0694E 0044FC62 LW V1, 68(V0)\r
+BFD06952 ED7F LI V0, -1\r
+BFD06954 0005B443 BNE V1, V0, 0xBFD06962\r
+BFD06956 0C000005 SLL ZERO, A1, 1\r
+BFD06958 0C00 NOP\r
+BFD0695A 0010FC5E LW V0, 16(S8)\r
+BFD0695E 0044F802 SW ZERO, 68(V0)\r
+BFD06962 0010FC5E LW V0, 16(S8)\r
+BFD06966 0048FC62 LW V1, 72(V0)\r
+BFD0696A ED7F LI V0, -1\r
+BFD0696C 0005B443 BNE V1, V0, 0xBFD0697A\r
+BFD0696E 0C000005 SLL ZERO, A1, 1\r
+BFD06970 0C00 NOP\r
+BFD06972 0010FC5E LW V0, 16(S8)\r
+BFD06976 0048F802 SW ZERO, 72(V0)\r
+BFD0697A 40AA77E8 JALS vTaskExitCritical\r
+BFD0697C 0C0040AA BNEZC T2, 0xBFD08180\r
+BFD0697E 0C00 NOP\r
2425: if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )\r
-BFD06980 0010FC5E LW V0, 16(S8)
-BFD06984 692E LW V0, 56(V0)
-BFD06986 000C40A2 BNEZC V0, 0xBFD069A2
+BFD06980 0010FC5E LW V0, 16(S8)\r
+BFD06984 692E LW V0, 56(V0)\r
+BFD06986 000C40A2 BNEZC V0, 0xBFD069A2\r
2426: {\r
2427: /* There is nothing in the queue, block for the specified period. */\r
2428: vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );\r
-BFD0698A 0010FC5E LW V0, 16(S8)
-BFD0698E 00243042 ADDIU V0, V0, 36
-BFD06992 0C82 MOVE A0, V0
-BFD06994 0024FCBE LW A1, 36(S8)
-BFD06998 0028FCDE LW A2, 40(S8)
-BFD0699C 2E2C77E8 JALS vTaskPlaceOnEventListRestricted
-BFD0699E 2E2C ANDI A0, V0, 0x40
-BFD069A0 0C00 NOP
+BFD0698A 0010FC5E LW V0, 16(S8)\r
+BFD0698E 00243042 ADDIU V0, V0, 36\r
+BFD06992 0C82 MOVE A0, V0\r
+BFD06994 0024FCBE LW A1, 36(S8)\r
+BFD06998 0028FCDE LW A2, 40(S8)\r
+BFD0699C 2E2C77E8 JALS vTaskPlaceOnEventListRestricted\r
+BFD0699E 2E2C ANDI A0, V0, 0x40\r
+BFD069A0 0C00 NOP\r
2429: }\r
2430: else\r
2431: {\r
2432: mtCOVERAGE_TEST_MARKER();\r
2433: }\r
2434: prvUnlockQueue( pxQueue );\r
-BFD069A2 0010FC9E LW A0, 16(S8)
-BFD069A6 1DEE77E8 JALS prvUnlockQueue
-BFD069A8 0C001DEE LB T7, 3072(T6)
-BFD069AA 0C00 NOP
+BFD069A2 0010FC9E LW A0, 16(S8)\r
+BFD069A6 1DEE77E8 JALS prvUnlockQueue\r
+BFD069A8 0C001DEE LB T7, 3072(T6)\r
+BFD069AA 0C00 NOP\r
2435: }\r
-BFD069AC 0FBE MOVE SP, S8
-BFD069AE 4BE7 LW RA, 28(SP)
-BFD069B0 4BC6 LW S8, 24(SP)
-BFD069B2 4C11 ADDIU SP, SP, 32
-BFD069B4 459F JR16 RA
-BFD069B6 0C00 NOP
+BFD069AC 0FBE MOVE SP, S8\r
+BFD069AE 4BE7 LW RA, 28(SP)\r
+BFD069B0 4BC6 LW S8, 24(SP)\r
+BFD069B2 4C11 ADDIU SP, SP, 32\r
+BFD069B4 459F JR16 RA\r
+BFD069B6 0C00 NOP\r
2436: \r
2437: #endif /* configUSE_TIMERS */\r
2438: /*-----------------------------------------------------------*/\r
2441: \r
2442: QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength )\r
2443: {\r
-BFD098AC 4FF1 ADDIU SP, SP, -32
-BFD098AE CBE7 SW RA, 28(SP)
-BFD098B0 CBC6 SW S8, 24(SP)
-BFD098B2 0FDD MOVE S8, SP
-BFD098B4 0020F89E SW A0, 32(S8)
+BFD098AC 4FF1 ADDIU SP, SP, -32\r
+BFD098AE CBE7 SW RA, 28(SP)\r
+BFD098B0 CBC6 SW S8, 24(SP)\r
+BFD098B2 0FDD MOVE S8, SP\r
+BFD098B4 0020F89E SW A0, 32(S8)\r
2444: QueueSetHandle_t pxQueue;\r
2445: \r
2446: pxQueue = xQueueGenericCreate( uxEventQueueLength, sizeof( Queue_t * ), queueQUEUE_TYPE_SET );\r
-BFD098B8 0020FC9E LW A0, 32(S8)
-BFD098BC EE84 LI A1, 4
-BFD098BE 0CC0 MOVE A2, ZERO
-BFD098C0 1EFA77E8 JALS xQueueGenericCreate
-BFD098C2 0C001EFA LB S7, 3072(K0)
-BFD098C4 0C00 NOP
-BFD098C6 0010F85E SW V0, 16(S8)
+BFD098B8 0020FC9E LW A0, 32(S8)\r
+BFD098BC EE84 LI A1, 4\r
+BFD098BE 0CC0 MOVE A2, ZERO\r
+BFD098C0 1EFA77E8 JALS xQueueGenericCreate\r
+BFD098C2 0C001EFA LB S7, 3072(K0)\r
+BFD098C4 0C00 NOP\r
+BFD098C6 0010F85E SW V0, 16(S8)\r
2447: \r
2448: return pxQueue;\r
-BFD098CA 0010FC5E LW V0, 16(S8)
+BFD098CA 0010FC5E LW V0, 16(S8)\r
2449: }\r
-BFD098CE 0FBE MOVE SP, S8
-BFD098D0 4BE7 LW RA, 28(SP)
-BFD098D2 4BC6 LW S8, 24(SP)
-BFD098D4 4C11 ADDIU SP, SP, 32
-BFD098D6 459F JR16 RA
-BFD098D8 0C00 NOP
+BFD098CE 0FBE MOVE SP, S8\r
+BFD098D0 4BE7 LW RA, 28(SP)\r
+BFD098D2 4BC6 LW S8, 24(SP)\r
+BFD098D4 4C11 ADDIU SP, SP, 32\r
+BFD098D6 459F JR16 RA\r
+BFD098D8 0C00 NOP\r
2450: \r
2451: #endif /* configUSE_QUEUE_SETS */\r
2452: /*-----------------------------------------------------------*/\r
2455: \r
2456: BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )\r
2457: {\r
-BFD07E9C 4FF1 ADDIU SP, SP, -32
-BFD07E9E CBE7 SW RA, 28(SP)
-BFD07EA0 CBC6 SW S8, 24(SP)
-BFD07EA2 0FDD MOVE S8, SP
-BFD07EA4 0020F89E SW A0, 32(S8)
-BFD07EA8 0024F8BE SW A1, 36(S8)
+BFD07E9C 4FF1 ADDIU SP, SP, -32\r
+BFD07E9E CBE7 SW RA, 28(SP)\r
+BFD07EA0 CBC6 SW S8, 24(SP)\r
+BFD07EA2 0FDD MOVE S8, SP\r
+BFD07EA4 0020F89E SW A0, 32(S8)\r
+BFD07EA8 0024F8BE SW A1, 36(S8)\r
2458: BaseType_t xReturn;\r
2459: \r
2460: taskENTER_CRITICAL();\r
-BFD07EAC 33B877E8 JALS vTaskEnterCritical
-BFD07EAE 0C0033B8 ADDIU SP, T8, 3072
-BFD07EB0 0C00 NOP
+BFD07EAC 33B877E8 JALS vTaskEnterCritical\r
+BFD07EAE 0C0033B8 ADDIU SP, T8, 3072\r
+BFD07EB0 0C00 NOP\r
2461: {\r
2462: if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )\r
-BFD07EB2 0020FC5E LW V0, 32(S8)
-BFD07EB6 004CFC42 LW V0, 76(V0)
-BFD07EBA 000440E2 BEQZC V0, 0xBFD07EC6
+BFD07EB2 0020FC5E LW V0, 32(S8)\r
+BFD07EB6 004CFC42 LW V0, 76(V0)\r
+BFD07EBA 000440E2 BEQZC V0, 0xBFD07EC6\r
2463: {\r
2464: /* Cannot add a queue/semaphore to more than one queue set. */\r
2465: xReturn = pdFAIL;\r
-BFD07EBE 0010F81E SW ZERO, 16(S8)
-BFD07EC2 CC13 B 0xBFD07EEA
-BFD07EC4 0C00 NOP
+BFD07EBE 0010F81E SW ZERO, 16(S8)\r
+BFD07EC2 CC13 B 0xBFD07EEA\r
+BFD07EC4 0C00 NOP\r
2466: }\r
2467: else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 )\r
-BFD07EC6 0020FC5E LW V0, 32(S8)
-BFD07ECA 692E LW V0, 56(V0)
-BFD07ECC 000440E2 BEQZC V0, 0xBFD07ED8
+BFD07EC6 0020FC5E LW V0, 32(S8)\r
+BFD07ECA 692E LW V0, 56(V0)\r
+BFD07ECC 000440E2 BEQZC V0, 0xBFD07ED8\r
2468: {\r
2469: /* Cannot add a queue/semaphore to a queue set if there are already\r
2470: items in the queue/semaphore. */\r
2471: xReturn = pdFAIL;\r
-BFD07ED0 0010F81E SW ZERO, 16(S8)
-BFD07ED4 CC0A B 0xBFD07EEA
-BFD07ED6 0C00 NOP
+BFD07ED0 0010F81E SW ZERO, 16(S8)\r
+BFD07ED4 CC0A B 0xBFD07EEA\r
+BFD07ED6 0C00 NOP\r
2472: }\r
2473: else\r
2474: {\r
2475: ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet;\r
-BFD07ED8 0020FC5E LW V0, 32(S8)
-BFD07EDC 0024FC7E LW V1, 36(S8)
-BFD07EE0 004CF862 SW V1, 76(V0)
+BFD07ED8 0020FC5E LW V0, 32(S8)\r
+BFD07EDC 0024FC7E LW V1, 36(S8)\r
+BFD07EE0 004CF862 SW V1, 76(V0)\r
2476: xReturn = pdPASS;\r
-BFD07EE4 ED01 LI V0, 1
-BFD07EE6 0010F85E SW V0, 16(S8)
+BFD07EE4 ED01 LI V0, 1\r
+BFD07EE6 0010F85E SW V0, 16(S8)\r
2477: }\r
2478: }\r
2479: taskEXIT_CRITICAL();\r
-BFD07EEA 40AA77E8 JALS vTaskExitCritical
-BFD07EEC 0C0040AA BNEZC T2, 0xBFD096F0
-BFD07EEE 0C00 NOP
+BFD07EEA 40AA77E8 JALS vTaskExitCritical\r
+BFD07EEC 0C0040AA BNEZC T2, 0xBFD096F0\r
+BFD07EEE 0C00 NOP\r
2480: \r
2481: return xReturn;\r
-BFD07EF0 0010FC5E LW V0, 16(S8)
+BFD07EF0 0010FC5E LW V0, 16(S8)\r
2482: }\r
-BFD07EF4 0FBE MOVE SP, S8
-BFD07EF6 4BE7 LW RA, 28(SP)
-BFD07EF8 4BC6 LW S8, 24(SP)
-BFD07EFA 4C11 ADDIU SP, SP, 32
-BFD07EFC 459F JR16 RA
-BFD07EFE 0C00 NOP
+BFD07EF4 0FBE MOVE SP, S8\r
+BFD07EF6 4BE7 LW RA, 28(SP)\r
+BFD07EF8 4BC6 LW S8, 24(SP)\r
+BFD07EFA 4C11 ADDIU SP, SP, 32\r
+BFD07EFC 459F JR16 RA\r
+BFD07EFE 0C00 NOP\r
2483: \r
2484: #endif /* configUSE_QUEUE_SETS */\r
2485: /*-----------------------------------------------------------*/\r
2488: \r
2489: BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )\r
2490: {\r
-BFD079FC 4FF1 ADDIU SP, SP, -32
-BFD079FE CBE7 SW RA, 28(SP)
-BFD07A00 CBC6 SW S8, 24(SP)
-BFD07A02 0FDD MOVE S8, SP
-BFD07A04 0020F89E SW A0, 32(S8)
-BFD07A08 0024F8BE SW A1, 36(S8)
+BFD079FC 4FF1 ADDIU SP, SP, -32\r
+BFD079FE CBE7 SW RA, 28(SP)\r
+BFD07A00 CBC6 SW S8, 24(SP)\r
+BFD07A02 0FDD MOVE S8, SP\r
+BFD07A04 0020F89E SW A0, 32(S8)\r
+BFD07A08 0024F8BE SW A1, 36(S8)\r
2491: BaseType_t xReturn;\r
2492: Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;\r
-BFD07A0C 0020FC5E LW V0, 32(S8)
-BFD07A10 0014F85E SW V0, 20(S8)
+BFD07A0C 0020FC5E LW V0, 32(S8)\r
+BFD07A10 0014F85E SW V0, 20(S8)\r
2493: \r
2494: if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )\r
-BFD07A14 0014FC5E LW V0, 20(S8)
-BFD07A18 004CFC62 LW V1, 76(V0)
-BFD07A1C 0024FC5E LW V0, 36(S8)
-BFD07A20 00059443 BEQ V1, V0, 0xBFD07A2E
-BFD07A22 0C000005 SLL ZERO, A1, 1
-BFD07A24 0C00 NOP
+BFD07A14 0014FC5E LW V0, 20(S8)\r
+BFD07A18 004CFC62 LW V1, 76(V0)\r
+BFD07A1C 0024FC5E LW V0, 36(S8)\r
+BFD07A20 00059443 BEQ V1, V0, 0xBFD07A2E\r
+BFD07A22 0C000005 SLL ZERO, A1, 1\r
+BFD07A24 0C00 NOP\r
2495: {\r
2496: /* The queue was not a member of the set. */\r
2497: xReturn = pdFAIL;\r
-BFD07A26 0010F81E SW ZERO, 16(S8)
-BFD07A2A CC17 B 0xBFD07A5A
-BFD07A2C 0C00 NOP
+BFD07A26 0010F81E SW ZERO, 16(S8)\r
+BFD07A2A CC17 B 0xBFD07A5A\r
+BFD07A2C 0C00 NOP\r
2498: }\r
2499: else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 )\r
-BFD07A2E 0014FC5E LW V0, 20(S8)
-BFD07A32 692E LW V0, 56(V0)
-BFD07A34 000440E2 BEQZC V0, 0xBFD07A40
+BFD07A2E 0014FC5E LW V0, 20(S8)\r
+BFD07A32 692E LW V0, 56(V0)\r
+BFD07A34 000440E2 BEQZC V0, 0xBFD07A40\r
2500: {\r
2501: /* It is dangerous to remove a queue from a set when the queue is\r
2502: not empty because the queue set will still hold pending events for\r
2503: the queue. */\r
2504: xReturn = pdFAIL;\r
-BFD07A38 0010F81E SW ZERO, 16(S8)
-BFD07A3C CC0E B 0xBFD07A5A
-BFD07A3E 0C00 NOP
+BFD07A38 0010F81E SW ZERO, 16(S8)\r
+BFD07A3C CC0E B 0xBFD07A5A\r
+BFD07A3E 0C00 NOP\r
2505: }\r
2506: else\r
2507: {\r
2508: taskENTER_CRITICAL();\r
-BFD07A40 33B877E8 JALS vTaskEnterCritical
-BFD07A42 0C0033B8 ADDIU SP, T8, 3072
-BFD07A44 0C00 NOP
+BFD07A40 33B877E8 JALS vTaskEnterCritical\r
+BFD07A42 0C0033B8 ADDIU SP, T8, 3072\r
+BFD07A44 0C00 NOP\r
2509: {\r
2510: /* The queue is no longer contained in the set. */\r
2511: pxQueueOrSemaphore->pxQueueSetContainer = NULL;\r
-BFD07A46 0014FC5E LW V0, 20(S8)
-BFD07A4A 004CF802 SW ZERO, 76(V0)
+BFD07A46 0014FC5E LW V0, 20(S8)\r
+BFD07A4A 004CF802 SW ZERO, 76(V0)\r
2512: }\r
2513: taskEXIT_CRITICAL();\r
-BFD07A4E 40AA77E8 JALS vTaskExitCritical
-BFD07A50 0C0040AA BNEZC T2, gpio_port_bitmaps
-BFD07A52 0C00 NOP
+BFD07A4E 40AA77E8 JALS vTaskExitCritical\r
+BFD07A50 0C0040AA BNEZC T2, gpio_port_bitmaps\r
+BFD07A52 0C00 NOP\r
2514: xReturn = pdPASS;\r
-BFD07A54 ED01 LI V0, 1
-BFD07A56 0010F85E SW V0, 16(S8)
+BFD07A54 ED01 LI V0, 1\r
+BFD07A56 0010F85E SW V0, 16(S8)\r
2515: }\r
2516: \r
2517: return xReturn;\r
-BFD07A5A 0010FC5E LW V0, 16(S8)
+BFD07A5A 0010FC5E LW V0, 16(S8)\r
2518: } /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */\r
-BFD07A5E 0FBE MOVE SP, S8
-BFD07A60 4BE7 LW RA, 28(SP)
-BFD07A62 4BC6 LW S8, 24(SP)
-BFD07A64 4C11 ADDIU SP, SP, 32
-BFD07A66 459F JR16 RA
-BFD07A68 0C00 NOP
+BFD07A5E 0FBE MOVE SP, S8\r
+BFD07A60 4BE7 LW RA, 28(SP)\r
+BFD07A62 4BC6 LW S8, 24(SP)\r
+BFD07A64 4C11 ADDIU SP, SP, 32\r
+BFD07A66 459F JR16 RA\r
+BFD07A68 0C00 NOP\r
2519: \r
2520: #endif /* configUSE_QUEUE_SETS */\r
2521: /*-----------------------------------------------------------*/\r
2524: \r
2525: QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t const xTicksToWait )\r
2526: {\r
-BFD094E0 4FF1 ADDIU SP, SP, -32
-BFD094E2 CBE7 SW RA, 28(SP)
-BFD094E4 CBC6 SW S8, 24(SP)
-BFD094E6 0FDD MOVE S8, SP
-BFD094E8 0020F89E SW A0, 32(S8)
-BFD094EC 0024F8BE SW A1, 36(S8)
+BFD094E0 4FF1 ADDIU SP, SP, -32\r
+BFD094E2 CBE7 SW RA, 28(SP)\r
+BFD094E4 CBC6 SW S8, 24(SP)\r
+BFD094E6 0FDD MOVE S8, SP\r
+BFD094E8 0020F89E SW A0, 32(S8)\r
+BFD094EC 0024F8BE SW A1, 36(S8)\r
2527: QueueSetMemberHandle_t xReturn = NULL;\r
-BFD094F0 0010F81E SW ZERO, 16(S8)
+BFD094F0 0010F81E SW ZERO, 16(S8)\r
2528: \r
2529: ( void ) xQueueGenericReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait, pdFALSE ); /*lint !e961 Casting from one typedef to another is not redundant. */\r
-BFD094F4 0020FC9E LW A0, 32(S8)
-BFD094F8 0010305E ADDIU V0, S8, 16
-BFD094FC 0CA2 MOVE A1, V0
-BFD094FE 0024FCDE LW A2, 36(S8)
-BFD09502 0CE0 MOVE A3, ZERO
-BFD09504 081E77E8 JALS xQueueGenericReceive
-BFD09506 081E LBU S0, 14(S1)
-BFD09508 0C00 NOP
+BFD094F4 0020FC9E LW A0, 32(S8)\r
+BFD094F8 0010305E ADDIU V0, S8, 16\r
+BFD094FC 0CA2 MOVE A1, V0\r
+BFD094FE 0024FCDE LW A2, 36(S8)\r
+BFD09502 0CE0 MOVE A3, ZERO\r
+BFD09504 081E77E8 JALS xQueueGenericReceive\r
+BFD09506 081E LBU S0, 14(S1)\r
+BFD09508 0C00 NOP\r
2530: return xReturn;\r
-BFD0950A 0010FC5E LW V0, 16(S8)
+BFD0950A 0010FC5E LW V0, 16(S8)\r
2531: }\r
-BFD0950E 0FBE MOVE SP, S8
-BFD09510 4BE7 LW RA, 28(SP)
-BFD09512 4BC6 LW S8, 24(SP)
-BFD09514 4C11 ADDIU SP, SP, 32
-BFD09516 459F JR16 RA
-BFD09518 0C00 NOP
+BFD0950E 0FBE MOVE SP, S8\r
+BFD09510 4BE7 LW RA, 28(SP)\r
+BFD09512 4BC6 LW S8, 24(SP)\r
+BFD09514 4C11 ADDIU SP, SP, 32\r
+BFD09516 459F JR16 RA\r
+BFD09518 0C00 NOP\r
2532: \r
2533: #endif /* configUSE_QUEUE_SETS */\r
2534: /*-----------------------------------------------------------*/\r
2537: \r
2538: QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet )\r
2539: {\r
-BFD097DC 4FF1 ADDIU SP, SP, -32
-BFD097DE CBE7 SW RA, 28(SP)
-BFD097E0 CBC6 SW S8, 24(SP)
-BFD097E2 0FDD MOVE S8, SP
-BFD097E4 0020F89E SW A0, 32(S8)
+BFD097DC 4FF1 ADDIU SP, SP, -32\r
+BFD097DE CBE7 SW RA, 28(SP)\r
+BFD097E0 CBC6 SW S8, 24(SP)\r
+BFD097E2 0FDD MOVE S8, SP\r
+BFD097E4 0020F89E SW A0, 32(S8)\r
2540: QueueSetMemberHandle_t xReturn = NULL;\r
-BFD097E8 0010F81E SW ZERO, 16(S8)
+BFD097E8 0010F81E SW ZERO, 16(S8)\r
2541: \r
2542: ( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */\r
-BFD097EC 0020FC9E LW A0, 32(S8)
-BFD097F0 0010305E ADDIU V0, S8, 16
-BFD097F4 0CA2 MOVE A1, V0
-BFD097F6 0CC0 MOVE A2, ZERO
-BFD097F8 1D6477E8 JALS xQueueReceiveFromISR
-BFD097FA 0C001D64 LB T3, 3072(A0)
-BFD097FC 0C00 NOP
+BFD097EC 0020FC9E LW A0, 32(S8)\r
+BFD097F0 0010305E ADDIU V0, S8, 16\r
+BFD097F4 0CA2 MOVE A1, V0\r
+BFD097F6 0CC0 MOVE A2, ZERO\r
+BFD097F8 1D6477E8 JALS xQueueReceiveFromISR\r
+BFD097FA 0C001D64 LB T3, 3072(A0)\r
+BFD097FC 0C00 NOP\r
2543: return xReturn;\r
-BFD097FE 0010FC5E LW V0, 16(S8)
+BFD097FE 0010FC5E LW V0, 16(S8)\r
2544: }\r
-BFD09802 0FBE MOVE SP, S8
-BFD09804 4BE7 LW RA, 28(SP)
-BFD09806 4BC6 LW S8, 24(SP)
-BFD09808 4C11 ADDIU SP, SP, 32
-BFD0980A 459F JR16 RA
-BFD0980C 0C00 NOP
+BFD09802 0FBE MOVE SP, S8\r
+BFD09804 4BE7 LW RA, 28(SP)\r
+BFD09806 4BC6 LW S8, 24(SP)\r
+BFD09808 4C11 ADDIU SP, SP, 32\r
+BFD0980A 459F JR16 RA\r
+BFD0980C 0C00 NOP\r
2545: \r
2546: #endif /* configUSE_QUEUE_SETS */\r
2547: /*-----------------------------------------------------------*/\r
2550: \r
2551: static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition )\r
2552: {\r
-BFD043B0 4FF1 ADDIU SP, SP, -32
-BFD043B2 CBE7 SW RA, 28(SP)
-BFD043B4 CBC6 SW S8, 24(SP)
-BFD043B6 0FDD MOVE S8, SP
-BFD043B8 0020F89E SW A0, 32(S8)
-BFD043BC 0024F8BE SW A1, 36(S8)
+BFD043B0 4FF1 ADDIU SP, SP, -32\r
+BFD043B2 CBE7 SW RA, 28(SP)\r
+BFD043B4 CBC6 SW S8, 24(SP)\r
+BFD043B6 0FDD MOVE S8, SP\r
+BFD043B8 0020F89E SW A0, 32(S8)\r
+BFD043BC 0024F8BE SW A1, 36(S8)\r
2553: Queue_t *pxQueueSetContainer = pxQueue->pxQueueSetContainer;\r
-BFD043C0 0020FC5E LW V0, 32(S8)
-BFD043C4 004CFC42 LW V0, 76(V0)
-BFD043C8 0014F85E SW V0, 20(S8)
+BFD043C0 0020FC5E LW V0, 32(S8)\r
+BFD043C4 004CFC42 LW V0, 76(V0)\r
+BFD043C8 0014F85E SW V0, 20(S8)\r
2554: BaseType_t xReturn = pdFALSE;\r
-BFD043CC 0010F81E SW ZERO, 16(S8)
+BFD043CC 0010F81E SW ZERO, 16(S8)\r
2555: \r
2556: /* This function must be called form a critical section. */\r
2557: \r
2558: configASSERT( pxQueueSetContainer );\r
-BFD043D0 0014FC5E LW V0, 20(S8)
-BFD043D4 000940A2 BNEZC V0, 0xBFD043EA
-BFD043D8 BFD141A2 LUI V0, 0xBFD1
-BFD043DA 3082BFD1 LDC1 F30, 12418(S1)
-BFD043DC 9E3C3082 ADDIU A0, V0, -25028
-BFD043DE 30A09E3C LWC1 F17, 12448(GP)
-BFD043E0 09FE30A0 ADDIU A1, ZERO, 2558
-BFD043E2 09FE LBU V1, 14(A3)
-BFD043E4 4B7E77E8 JALS vAssertCalled
-BFD043E6 4B7E LW K1, 120(SP)
-BFD043E8 0C00 NOP
+BFD043D0 0014FC5E LW V0, 20(S8)\r
+BFD043D4 000940A2 BNEZC V0, 0xBFD043EA\r
+BFD043D8 BFD141A2 LUI V0, 0xBFD1\r
+BFD043DA 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD043DC 9E3C3082 ADDIU A0, V0, -25028\r
+BFD043DE 30A09E3C LWC1 F17, 12448(GP)\r
+BFD043E0 09FE30A0 ADDIU A1, ZERO, 2558\r
+BFD043E2 09FE LBU V1, 14(A3)\r
+BFD043E4 4B7E77E8 JALS vAssertCalled\r
+BFD043E6 4B7E LW K1, 120(SP)\r
+BFD043E8 0C00 NOP\r
2559: configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength );\r
-BFD043EA 0014FC5E LW V0, 20(S8)
-BFD043EE 69AE LW V1, 56(V0)
-BFD043F0 0014FC5E LW V0, 20(S8)
-BFD043F4 692F LW V0, 60(V0)
-BFD043F6 13900043 SLTU V0, V1, V0
-BFD043F8 40A21390 ADDI GP, S0, 16546
-BFD043FA 000940A2 BNEZC V0, 0xBFD04410
-BFD043FE BFD141A2 LUI V0, 0xBFD1
-BFD04400 3082BFD1 LDC1 F30, 12418(S1)
-BFD04402 9E3C3082 ADDIU A0, V0, -25028
-BFD04404 30A09E3C LWC1 F17, 12448(GP)
-BFD04406 09FF30A0 ADDIU A1, ZERO, 2559
-BFD04408 09FF LBU V1, -1(A3)
-BFD0440A 4B7E77E8 JALS vAssertCalled
-BFD0440C 4B7E LW K1, 120(SP)
-BFD0440E 0C00 NOP
+BFD043EA 0014FC5E LW V0, 20(S8)\r
+BFD043EE 69AE LW V1, 56(V0)\r
+BFD043F0 0014FC5E LW V0, 20(S8)\r
+BFD043F4 692F LW V0, 60(V0)\r
+BFD043F6 13900043 SLTU V0, V1, V0\r
+BFD043F8 40A21390 ADDI GP, S0, 16546\r
+BFD043FA 000940A2 BNEZC V0, 0xBFD04410\r
+BFD043FE BFD141A2 LUI V0, 0xBFD1\r
+BFD04400 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD04402 9E3C3082 ADDIU A0, V0, -25028\r
+BFD04404 30A09E3C LWC1 F17, 12448(GP)\r
+BFD04406 09FF30A0 ADDIU A1, ZERO, 2559\r
+BFD04408 09FF LBU V1, -1(A3)\r
+BFD0440A 4B7E77E8 JALS vAssertCalled\r
+BFD0440C 4B7E LW K1, 120(SP)\r
+BFD0440E 0C00 NOP\r
2560: \r
2561: if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength )\r
-BFD04410 0014FC5E LW V0, 20(S8)
-BFD04414 69AE LW V1, 56(V0)
-BFD04416 0014FC5E LW V0, 20(S8)
-BFD0441A 692F LW V0, 60(V0)
-BFD0441C 13900043 SLTU V0, V1, V0
-BFD0441E 40E21390 ADDI GP, S0, 16610
-BFD04420 003040E2 BEQZC V0, 0xBFD04484
+BFD04410 0014FC5E LW V0, 20(S8)\r
+BFD04414 69AE LW V1, 56(V0)\r
+BFD04416 0014FC5E LW V0, 20(S8)\r
+BFD0441A 692F LW V0, 60(V0)\r
+BFD0441C 13900043 SLTU V0, V1, V0\r
+BFD0441E 40E21390 ADDI GP, S0, 16610\r
+BFD04420 003040E2 BEQZC V0, 0xBFD04484\r
2562: {\r
2563: traceQUEUE_SEND( pxQueueSetContainer );\r
2564: \r
2565: /* The data copied is the handle of the queue that contains data. */\r
2566: xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, xCopyPosition );\r
-BFD04424 0014FC9E LW A0, 20(S8)
-BFD04428 002030BE ADDIU A1, S8, 32
-BFD0442C 0024FCDE LW A2, 36(S8)
-BFD04430 14E677E8 JALS prvCopyDataToQueue
-BFD04432 0C0014E6 LBU A3, 3072(A2)
-BFD04434 0C00 NOP
-BFD04436 0010F85E SW V0, 16(S8)
+BFD04424 0014FC9E LW A0, 20(S8)\r
+BFD04428 002030BE ADDIU A1, S8, 32\r
+BFD0442C 0024FCDE LW A2, 36(S8)\r
+BFD04430 14E677E8 JALS prvCopyDataToQueue\r
+BFD04432 0C0014E6 LBU A3, 3072(A2)\r
+BFD04434 0C00 NOP\r
+BFD04436 0010F85E SW V0, 16(S8)\r
2567: \r
2568: if( pxQueueSetContainer->xTxLock == queueUNLOCKED )\r
-BFD0443A 0014FC5E LW V0, 20(S8)
-BFD0443E 0048FC62 LW V1, 72(V0)
-BFD04442 ED7F LI V0, -1
-BFD04444 0015B443 BNE V1, V0, 0xBFD04472
-BFD04446 0C000015 SLL ZERO, S5, 1
-BFD04448 0C00 NOP
+BFD0443A 0014FC5E LW V0, 20(S8)\r
+BFD0443E 0048FC62 LW V1, 72(V0)\r
+BFD04442 ED7F LI V0, -1\r
+BFD04444 0015B443 BNE V1, V0, 0xBFD04472\r
+BFD04446 0C000015 SLL ZERO, S5, 1\r
+BFD04448 0C00 NOP\r
2569: {\r
2570: if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE )\r
-BFD0444A 0014FC5E LW V0, 20(S8)
-BFD0444E 6929 LW V0, 36(V0)
-BFD04450 001840E2 BEQZC V0, 0xBFD04484
+BFD0444A 0014FC5E LW V0, 20(S8)\r
+BFD0444E 6929 LW V0, 36(V0)\r
+BFD04450 001840E2 BEQZC V0, 0xBFD04484\r
2571: {\r
2572: if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE )\r
-BFD04454 0014FC5E LW V0, 20(S8)
-BFD04458 00243042 ADDIU V0, V0, 36
-BFD0445C 0C82 MOVE A0, V0
-BFD0445E 22BC77E8 JALS xTaskRemoveFromEventList
-BFD04460 0C0022BC LWC2 S5, 3072(GP)
-BFD04462 0C00 NOP
-BFD04464 000E40E2 BEQZC V0, 0xBFD04484
+BFD04454 0014FC5E LW V0, 20(S8)\r
+BFD04458 00243042 ADDIU V0, V0, 36\r
+BFD0445C 0C82 MOVE A0, V0\r
+BFD0445E 22BC77E8 JALS xTaskRemoveFromEventList\r
+BFD04460 0C0022BC LWC2 S5, 3072(GP)\r
+BFD04462 0C00 NOP\r
+BFD04464 000E40E2 BEQZC V0, 0xBFD04484\r
2573: {\r
2574: /* The task waiting has a higher priority. */\r
2575: xReturn = pdTRUE;\r
-BFD04468 ED01 LI V0, 1
-BFD0446A 0010F85E SW V0, 16(S8)
-BFD0446E CC0A B 0xBFD04484
-BFD04470 0C00 NOP
+BFD04468 ED01 LI V0, 1\r
+BFD0446A 0010F85E SW V0, 16(S8)\r
+BFD0446E CC0A B 0xBFD04484\r
+BFD04470 0C00 NOP\r
2576: }\r
2577: else\r
2578: {\r
2587: else\r
2588: {\r
2589: ( pxQueueSetContainer->xTxLock )++;\r
-BFD04472 0014FC5E LW V0, 20(S8)
-BFD04476 0048FC42 LW V0, 72(V0)
-BFD0447A 6DA0 ADDIU V1, V0, 1
-BFD0447C 0014FC5E LW V0, 20(S8)
-BFD04480 0048F862 SW V1, 72(V0)
+BFD04472 0014FC5E LW V0, 20(S8)\r
+BFD04476 0048FC42 LW V0, 72(V0)\r
+BFD0447A 6DA0 ADDIU V1, V0, 1\r
+BFD0447C 0014FC5E LW V0, 20(S8)\r
+BFD04480 0048F862 SW V1, 72(V0)\r
2590: }\r
2591: }\r
2592: else\r
2595: }\r
2596: \r
2597: return xReturn;\r
-BFD04484 0010FC5E LW V0, 16(S8)
+BFD04484 0010FC5E LW V0, 16(S8)\r
2598: }\r
-BFD04488 0FBE MOVE SP, S8
-BFD0448A 4BE7 LW RA, 28(SP)
-BFD0448C 4BC6 LW S8, 24(SP)
-BFD0448E 4C11 ADDIU SP, SP, 32
-BFD04490 459F JR16 RA
-BFD04492 0C00 NOP
+BFD04488 0FBE MOVE SP, S8\r
+BFD0448A 4BE7 LW RA, 28(SP)\r
+BFD0448C 4BC6 LW S8, 24(SP)\r
+BFD0448E 4C11 ADDIU SP, SP, 32\r
+BFD04490 459F JR16 RA\r
+BFD04492 0C00 NOP\r
2599: \r
2600: #endif /* configUSE_QUEUE_SETS */\r
2601: \r
2610: \r
2611: \r
2612: \r
---- c:/e/dev/freertos/workingcopy/freertos/source/portable/mplab/pic32mec14xx/portmacro.h -------------
+--- c:/e/dev/freertos/workingcopy/freertos/source/portable/mplab/pic32mec14xx/portmacro.h -------------\r
1: /*\r
2: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
3: All rights reserved\r
8: \r
9: FreeRTOS is free software; you can redistribute it and/or modify it under\r
10: the terms of the GNU General Public License (version 2) as published by the\r
-11: Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+11: Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
12: \r
13: ***************************************************************************\r
14: >>! NOTE: The modification to the GPL is included to allow you to !<<\r
123: \r
124: static inline uint32_t ulPortGetCP0Status( void )\r
125: {\r
-BFD09B4C 4FF9 ADDIU SP, SP, -16
-BFD09B4E CBC3 SW S8, 12(SP)
-BFD09B50 CA02 SW S0, 8(SP)
-BFD09B52 0FDD MOVE S8, SP
-BFD09C6C 4FF9 ADDIU SP, SP, -16
-BFD09C6E CBC3 SW S8, 12(SP)
-BFD09C70 CA02 SW S0, 8(SP)
-BFD09C72 0FDD MOVE S8, SP
-BFD09D6C 4FF9 ADDIU SP, SP, -16
-BFD09D6E CBC3 SW S8, 12(SP)
-BFD09D70 CA02 SW S0, 8(SP)
-BFD09D72 0FDD MOVE S8, SP
+BFD09B4C 4FF9 ADDIU SP, SP, -16\r
+BFD09B4E CBC3 SW S8, 12(SP)\r
+BFD09B50 CA02 SW S0, 8(SP)\r
+BFD09B52 0FDD MOVE S8, SP\r
+BFD09C6C 4FF9 ADDIU SP, SP, -16\r
+BFD09C6E CBC3 SW S8, 12(SP)\r
+BFD09C70 CA02 SW S0, 8(SP)\r
+BFD09C72 0FDD MOVE S8, SP\r
+BFD09D6C 4FF9 ADDIU SP, SP, -16\r
+BFD09D6E CBC3 SW S8, 12(SP)\r
+BFD09D70 CA02 SW S0, 8(SP)\r
+BFD09D72 0FDD MOVE S8, SP\r
126: uint32_t rv;\r
127: \r
128: __asm volatile(\r
-BFD09B54 00FC020C MFC0 S0, Status
-BFD09B58 0000FA1E SW S0, 0(S8)
-BFD09C74 00FC020C MFC0 S0, Status
-BFD09C78 0000FA1E SW S0, 0(S8)
-BFD09D74 00FC020C MFC0 S0, Status
-BFD09D78 0000FA1E SW S0, 0(S8)
+BFD09B54 00FC020C MFC0 S0, Status\r
+BFD09B58 0000FA1E SW S0, 0(S8)\r
+BFD09C74 00FC020C MFC0 S0, Status\r
+BFD09C78 0000FA1E SW S0, 0(S8)\r
+BFD09D74 00FC020C MFC0 S0, Status\r
+BFD09D78 0000FA1E SW S0, 0(S8)\r
129: "\n\t"\r
130: "mfc0 %0,$12,0 \n\t"\r
131: : "=r" ( rv ) :: );\r
132: \r
133: return rv;\r
-BFD09B5C 0000FC5E LW V0, 0(S8)
-BFD09C7C 0000FC5E LW V0, 0(S8)
-BFD09D7C 0000FC5E LW V0, 0(S8)
+BFD09B5C 0000FC5E LW V0, 0(S8)\r
+BFD09C7C 0000FC5E LW V0, 0(S8)\r
+BFD09D7C 0000FC5E LW V0, 0(S8)\r
134: }\r
-BFD09B60 0FBE MOVE SP, S8
-BFD09B62 4BC3 LW S8, 12(SP)
-BFD09B64 4A02 LW S0, 8(SP)
-BFD09B66 459F JR16 RA
-BFD09B68 4C09 ADDIU SP, SP, 16
-BFD09C80 0FBE MOVE SP, S8
-BFD09C82 4BC3 LW S8, 12(SP)
-BFD09C84 4A02 LW S0, 8(SP)
-BFD09C86 459F JR16 RA
-BFD09C88 4C09 ADDIU SP, SP, 16
-BFD09D80 0FBE MOVE SP, S8
-BFD09D82 4BC3 LW S8, 12(SP)
-BFD09D84 4A02 LW S0, 8(SP)
-BFD09D86 459F JR16 RA
-BFD09D88 4C09 ADDIU SP, SP, 16
+BFD09B60 0FBE MOVE SP, S8\r
+BFD09B62 4BC3 LW S8, 12(SP)\r
+BFD09B64 4A02 LW S0, 8(SP)\r
+BFD09B66 459F JR16 RA\r
+BFD09B68 4C09 ADDIU SP, SP, 16\r
+BFD09C80 0FBE MOVE SP, S8\r
+BFD09C82 4BC3 LW S8, 12(SP)\r
+BFD09C84 4A02 LW S0, 8(SP)\r
+BFD09C86 459F JR16 RA\r
+BFD09C88 4C09 ADDIU SP, SP, 16\r
+BFD09D80 0FBE MOVE SP, S8\r
+BFD09D82 4BC3 LW S8, 12(SP)\r
+BFD09D84 4A02 LW S0, 8(SP)\r
+BFD09D86 459F JR16 RA\r
+BFD09D88 4C09 ADDIU SP, SP, 16\r
135: /*-----------------------------------------------------------*/\r
136: \r
137: static inline void vPortSetCP0Status( uint32_t new_status)\r
138: {\r
-BFD09B6C 4FB0 ADDIU SP, SP, -8
-BFD09B6E CBC1 SW S8, 4(SP)
-BFD09B70 0FDD MOVE S8, SP
-BFD09B72 0008F89E SW A0, 8(S8)
-BFD09C8C 4FB0 ADDIU SP, SP, -8
-BFD09C8E CBC1 SW S8, 4(SP)
-BFD09C90 0FDD MOVE S8, SP
-BFD09C92 0008F89E SW A0, 8(S8)
-BFD09D8C 4FB0 ADDIU SP, SP, -8
-BFD09D8E CBC1 SW S8, 4(SP)
-BFD09D90 0FDD MOVE S8, SP
-BFD09D92 0008F89E SW A0, 8(S8)
+BFD09B6C 4FB0 ADDIU SP, SP, -8\r
+BFD09B6E CBC1 SW S8, 4(SP)\r
+BFD09B70 0FDD MOVE S8, SP\r
+BFD09B72 0008F89E SW A0, 8(S8)\r
+BFD09C8C 4FB0 ADDIU SP, SP, -8\r
+BFD09C8E CBC1 SW S8, 4(SP)\r
+BFD09C90 0FDD MOVE S8, SP\r
+BFD09C92 0008F89E SW A0, 8(S8)\r
+BFD09D8C 4FB0 ADDIU SP, SP, -8\r
+BFD09D8E CBC1 SW S8, 4(SP)\r
+BFD09D90 0FDD MOVE S8, SP\r
+BFD09D92 0008F89E SW A0, 8(S8)\r
139: ( void ) new_status;\r
140: \r
141: __asm__ __volatile__(\r
-BFD09B76 0008FC5E LW V0, 8(S8)
-BFD09B78 004C0008 INS ZERO, T0, 1, 0
-BFD09B7A 02FC004C MTC0 V0, Status
-BFD09B7C 000002FC SLL S7, GP, 0
-BFD09B7E 18000000 SLL ZERO, ZERO, 3
-BFD09B80 0FBE1800 SB ZERO, 4030(ZERO)
-BFD09C96 0008FC5E LW V0, 8(S8)
-BFD09C98 004C0008 INS ZERO, T0, 1, 0
-BFD09C9A 02FC004C MTC0 V0, Status
-BFD09C9C 000002FC SLL S7, GP, 0
-BFD09C9E 18000000 SLL ZERO, ZERO, 3
-BFD09CA0 0FBE1800 SB ZERO, 4030(ZERO)
-BFD09D96 0008FC5E LW V0, 8(S8)
-BFD09D98 004C0008 INS ZERO, T0, 1, 0
-BFD09D9A 02FC004C MTC0 V0, Status
-BFD09D9C 000002FC SLL S7, GP, 0
-BFD09D9E 18000000 SLL ZERO, ZERO, 3
-BFD09DA0 0FBE1800 SB ZERO, 4030(ZERO)
+BFD09B76 0008FC5E LW V0, 8(S8)\r
+BFD09B78 004C0008 INS ZERO, T0, 1, 0\r
+BFD09B7A 02FC004C MTC0 V0, Status\r
+BFD09B7C 000002FC SLL S7, GP, 0\r
+BFD09B7E 18000000 SLL ZERO, ZERO, 3\r
+BFD09B80 0FBE1800 SB ZERO, 4030(ZERO)\r
+BFD09C96 0008FC5E LW V0, 8(S8)\r
+BFD09C98 004C0008 INS ZERO, T0, 1, 0\r
+BFD09C9A 02FC004C MTC0 V0, Status\r
+BFD09C9C 000002FC SLL S7, GP, 0\r
+BFD09C9E 18000000 SLL ZERO, ZERO, 3\r
+BFD09CA0 0FBE1800 SB ZERO, 4030(ZERO)\r
+BFD09D96 0008FC5E LW V0, 8(S8)\r
+BFD09D98 004C0008 INS ZERO, T0, 1, 0\r
+BFD09D9A 02FC004C MTC0 V0, Status\r
+BFD09D9C 000002FC SLL S7, GP, 0\r
+BFD09D9E 18000000 SLL ZERO, ZERO, 3\r
+BFD09DA0 0FBE1800 SB ZERO, 4030(ZERO)\r
142: "\n\t"\r
143: "mtc0 %0,$12,0 \n\t"\r
144: "ehb \n\t"\r
145: :\r
146: :"r" ( new_status ) : );\r
147: }\r
-BFD09B82 0FBE MOVE SP, S8
-BFD09B84 4BC1 LW S8, 4(SP)
-BFD09B86 459F JR16 RA
-BFD09B88 4C05 ADDIU SP, SP, 8
-BFD09CA2 0FBE MOVE SP, S8
-BFD09CA4 4BC1 LW S8, 4(SP)
-BFD09CA6 459F JR16 RA
-BFD09CA8 4C05 ADDIU SP, SP, 8
-BFD09DA2 0FBE MOVE SP, S8
-BFD09DA4 4BC1 LW S8, 4(SP)
-BFD09DA6 459F JR16 RA
-BFD09DA8 4C05 ADDIU SP, SP, 8
+BFD09B82 0FBE MOVE SP, S8\r
+BFD09B84 4BC1 LW S8, 4(SP)\r
+BFD09B86 459F JR16 RA\r
+BFD09B88 4C05 ADDIU SP, SP, 8\r
+BFD09CA2 0FBE MOVE SP, S8\r
+BFD09CA4 4BC1 LW S8, 4(SP)\r
+BFD09CA6 459F JR16 RA\r
+BFD09CA8 4C05 ADDIU SP, SP, 8\r
+BFD09DA2 0FBE MOVE SP, S8\r
+BFD09DA4 4BC1 LW S8, 4(SP)\r
+BFD09DA6 459F JR16 RA\r
+BFD09DA8 4C05 ADDIU SP, SP, 8\r
148: /*-----------------------------------------------------------*/\r
149: \r
150: static inline uint32_t ulPortGetCP0Cause( void )\r
151: {\r
-BFD09B8C 4FF9 ADDIU SP, SP, -16
-BFD09B8E CBC3 SW S8, 12(SP)
-BFD09B90 CA02 SW S0, 8(SP)
-BFD09B92 0FDD MOVE S8, SP
-BFD09BCC 4FF9 ADDIU SP, SP, -16
-BFD09BCE CBC3 SW S8, 12(SP)
-BFD09BD0 CA02 SW S0, 8(SP)
-BFD09BD2 0FDD MOVE S8, SP
-BFD09C2C 4FF9 ADDIU SP, SP, -16
-BFD09C2E CBC3 SW S8, 12(SP)
-BFD09C30 CA02 SW S0, 8(SP)
-BFD09C32 0FDD MOVE S8, SP
-BFD09CAC 4FF9 ADDIU SP, SP, -16
-BFD09CAE CBC3 SW S8, 12(SP)
-BFD09CB0 CA02 SW S0, 8(SP)
-BFD09CB2 0FDD MOVE S8, SP
-BFD09CEC 4FF9 ADDIU SP, SP, -16
-BFD09CEE CBC3 SW S8, 12(SP)
-BFD09CF0 CA02 SW S0, 8(SP)
-BFD09CF2 0FDD MOVE S8, SP
+BFD09B8C 4FF9 ADDIU SP, SP, -16\r
+BFD09B8E CBC3 SW S8, 12(SP)\r
+BFD09B90 CA02 SW S0, 8(SP)\r
+BFD09B92 0FDD MOVE S8, SP\r
+BFD09BCC 4FF9 ADDIU SP, SP, -16\r
+BFD09BCE CBC3 SW S8, 12(SP)\r
+BFD09BD0 CA02 SW S0, 8(SP)\r
+BFD09BD2 0FDD MOVE S8, SP\r
+BFD09C2C 4FF9 ADDIU SP, SP, -16\r
+BFD09C2E CBC3 SW S8, 12(SP)\r
+BFD09C30 CA02 SW S0, 8(SP)\r
+BFD09C32 0FDD MOVE S8, SP\r
+BFD09CAC 4FF9 ADDIU SP, SP, -16\r
+BFD09CAE CBC3 SW S8, 12(SP)\r
+BFD09CB0 CA02 SW S0, 8(SP)\r
+BFD09CB2 0FDD MOVE S8, SP\r
+BFD09CEC 4FF9 ADDIU SP, SP, -16\r
+BFD09CEE CBC3 SW S8, 12(SP)\r
+BFD09CF0 CA02 SW S0, 8(SP)\r
+BFD09CF2 0FDD MOVE S8, SP\r
152: uint32_t rv;\r
153: \r
154: __asm volatile(\r
-BFD09B94 00FC020D MFC0 S0, Cause
-BFD09B98 0000FA1E SW S0, 0(S8)
-BFD09BD4 00FC020D MFC0 S0, Cause
-BFD09BD8 0000FA1E SW S0, 0(S8)
-BFD09C34 00FC020D MFC0 S0, Cause
-BFD09C38 0000FA1E SW S0, 0(S8)
-BFD09CB4 00FC020D MFC0 S0, Cause
-BFD09CB8 0000FA1E SW S0, 0(S8)
-BFD09CF4 00FC020D MFC0 S0, Cause
-BFD09CF8 0000FA1E SW S0, 0(S8)
+BFD09B94 00FC020D MFC0 S0, Cause\r
+BFD09B98 0000FA1E SW S0, 0(S8)\r
+BFD09BD4 00FC020D MFC0 S0, Cause\r
+BFD09BD8 0000FA1E SW S0, 0(S8)\r
+BFD09C34 00FC020D MFC0 S0, Cause\r
+BFD09C38 0000FA1E SW S0, 0(S8)\r
+BFD09CB4 00FC020D MFC0 S0, Cause\r
+BFD09CB8 0000FA1E SW S0, 0(S8)\r
+BFD09CF4 00FC020D MFC0 S0, Cause\r
+BFD09CF8 0000FA1E SW S0, 0(S8)\r
155: "\n\t"\r
156: "mfc0 %0,$13,0 \n\t"\r
157: : "=r" ( rv ) :: );\r
158: \r
159: return rv;\r
-BFD09B9C 0000FC5E LW V0, 0(S8)
-BFD09BDC 0000FC5E LW V0, 0(S8)
-BFD09C3C 0000FC5E LW V0, 0(S8)
-BFD09CBC 0000FC5E LW V0, 0(S8)
-BFD09CFC 0000FC5E LW V0, 0(S8)
+BFD09B9C 0000FC5E LW V0, 0(S8)\r
+BFD09BDC 0000FC5E LW V0, 0(S8)\r
+BFD09C3C 0000FC5E LW V0, 0(S8)\r
+BFD09CBC 0000FC5E LW V0, 0(S8)\r
+BFD09CFC 0000FC5E LW V0, 0(S8)\r
160: }\r
-BFD09BA0 0FBE MOVE SP, S8
-BFD09BA2 4BC3 LW S8, 12(SP)
-BFD09BA4 4A02 LW S0, 8(SP)
-BFD09BA6 459F JR16 RA
-BFD09BA8 4C09 ADDIU SP, SP, 16
-BFD09BE0 0FBE MOVE SP, S8
-BFD09BE2 4BC3 LW S8, 12(SP)
-BFD09BE4 4A02 LW S0, 8(SP)
-BFD09BE6 459F JR16 RA
-BFD09BE8 4C09 ADDIU SP, SP, 16
-BFD09C40 0FBE MOVE SP, S8
-BFD09C42 4BC3 LW S8, 12(SP)
-BFD09C44 4A02 LW S0, 8(SP)
-BFD09C46 459F JR16 RA
-BFD09C48 4C09 ADDIU SP, SP, 16
-BFD09CC0 0FBE MOVE SP, S8
-BFD09CC2 4BC3 LW S8, 12(SP)
-BFD09CC4 4A02 LW S0, 8(SP)
-BFD09CC6 459F JR16 RA
-BFD09CC8 4C09 ADDIU SP, SP, 16
-BFD09D00 0FBE MOVE SP, S8
-BFD09D02 4BC3 LW S8, 12(SP)
-BFD09D04 4A02 LW S0, 8(SP)
-BFD09D06 459F JR16 RA
-BFD09D08 4C09 ADDIU SP, SP, 16
+BFD09BA0 0FBE MOVE SP, S8\r
+BFD09BA2 4BC3 LW S8, 12(SP)\r
+BFD09BA4 4A02 LW S0, 8(SP)\r
+BFD09BA6 459F JR16 RA\r
+BFD09BA8 4C09 ADDIU SP, SP, 16\r
+BFD09BE0 0FBE MOVE SP, S8\r
+BFD09BE2 4BC3 LW S8, 12(SP)\r
+BFD09BE4 4A02 LW S0, 8(SP)\r
+BFD09BE6 459F JR16 RA\r
+BFD09BE8 4C09 ADDIU SP, SP, 16\r
+BFD09C40 0FBE MOVE SP, S8\r
+BFD09C42 4BC3 LW S8, 12(SP)\r
+BFD09C44 4A02 LW S0, 8(SP)\r
+BFD09C46 459F JR16 RA\r
+BFD09C48 4C09 ADDIU SP, SP, 16\r
+BFD09CC0 0FBE MOVE SP, S8\r
+BFD09CC2 4BC3 LW S8, 12(SP)\r
+BFD09CC4 4A02 LW S0, 8(SP)\r
+BFD09CC6 459F JR16 RA\r
+BFD09CC8 4C09 ADDIU SP, SP, 16\r
+BFD09D00 0FBE MOVE SP, S8\r
+BFD09D02 4BC3 LW S8, 12(SP)\r
+BFD09D04 4A02 LW S0, 8(SP)\r
+BFD09D06 459F JR16 RA\r
+BFD09D08 4C09 ADDIU SP, SP, 16\r
161: /*-----------------------------------------------------------*/\r
162: \r
163: static inline void vPortSetCP0Cause( uint32_t new_cause )\r
164: {\r
-BFD09BAC 4FB0 ADDIU SP, SP, -8
-BFD09BAE CBC1 SW S8, 4(SP)
-BFD09BB0 0FDD MOVE S8, SP
-BFD09BB2 0008F89E SW A0, 8(S8)
-BFD09BEC 4FB0 ADDIU SP, SP, -8
-BFD09BEE CBC1 SW S8, 4(SP)
-BFD09BF0 0FDD MOVE S8, SP
-BFD09BF2 0008F89E SW A0, 8(S8)
-BFD09C4C 4FB0 ADDIU SP, SP, -8
-BFD09C4E CBC1 SW S8, 4(SP)
-BFD09C50 0FDD MOVE S8, SP
-BFD09C52 0008F89E SW A0, 8(S8)
-BFD09CCC 4FB0 ADDIU SP, SP, -8
-BFD09CCE CBC1 SW S8, 4(SP)
-BFD09CD0 0FDD MOVE S8, SP
-BFD09CD2 0008F89E SW A0, 8(S8)
-BFD09D0C 4FB0 ADDIU SP, SP, -8
-BFD09D0E CBC1 SW S8, 4(SP)
-BFD09D10 0FDD MOVE S8, SP
-BFD09D12 0008F89E SW A0, 8(S8)
+BFD09BAC 4FB0 ADDIU SP, SP, -8\r
+BFD09BAE CBC1 SW S8, 4(SP)\r
+BFD09BB0 0FDD MOVE S8, SP\r
+BFD09BB2 0008F89E SW A0, 8(S8)\r
+BFD09BEC 4FB0 ADDIU SP, SP, -8\r
+BFD09BEE CBC1 SW S8, 4(SP)\r
+BFD09BF0 0FDD MOVE S8, SP\r
+BFD09BF2 0008F89E SW A0, 8(S8)\r
+BFD09C4C 4FB0 ADDIU SP, SP, -8\r
+BFD09C4E CBC1 SW S8, 4(SP)\r
+BFD09C50 0FDD MOVE S8, SP\r
+BFD09C52 0008F89E SW A0, 8(S8)\r
+BFD09CCC 4FB0 ADDIU SP, SP, -8\r
+BFD09CCE CBC1 SW S8, 4(SP)\r
+BFD09CD0 0FDD MOVE S8, SP\r
+BFD09CD2 0008F89E SW A0, 8(S8)\r
+BFD09D0C 4FB0 ADDIU SP, SP, -8\r
+BFD09D0E CBC1 SW S8, 4(SP)\r
+BFD09D10 0FDD MOVE S8, SP\r
+BFD09D12 0008F89E SW A0, 8(S8)\r
165: ( void ) new_cause;\r
166: \r
167: __asm__ __volatile__(\r
-BFD09BB6 0008FC5E LW V0, 8(S8)
-BFD09BB8 004D0008 ADDQH.PH ZERO, T0, ZERO
-BFD09BBA 02FC004D MTC0 V0, Cause
-BFD09BBC 000002FC SLL S7, GP, 0
-BFD09BBE 18000000 SLL ZERO, ZERO, 3
-BFD09BC0 0FBE1800 SB ZERO, 4030(ZERO)
-BFD09BF6 0008FC5E LW V0, 8(S8)
-BFD09BF8 004D0008 ADDQH.PH ZERO, T0, ZERO
-BFD09BFA 02FC004D MTC0 V0, Cause
-BFD09BFC 000002FC SLL S7, GP, 0
-BFD09BFE 18000000 SLL ZERO, ZERO, 3
-BFD09C00 0FBE1800 SB ZERO, 4030(ZERO)
-BFD09C56 0008FC5E LW V0, 8(S8)
-BFD09C58 004D0008 ADDQH.PH ZERO, T0, ZERO
-BFD09C5A 02FC004D MTC0 V0, Cause
-BFD09C5C 000002FC SLL S7, GP, 0
-BFD09C5E 18000000 SLL ZERO, ZERO, 3
-BFD09C60 0FBE1800 SB ZERO, 4030(ZERO)
-BFD09CD6 0008FC5E LW V0, 8(S8)
-BFD09CD8 004D0008 ADDQH.PH ZERO, T0, ZERO
-BFD09CDA 02FC004D MTC0 V0, Cause
-BFD09CDC 000002FC SLL S7, GP, 0
-BFD09CDE 18000000 SLL ZERO, ZERO, 3
-BFD09CE0 0FBE1800 SB ZERO, 4030(ZERO)
-BFD09D16 0008FC5E LW V0, 8(S8)
-BFD09D18 004D0008 ADDQH.PH ZERO, T0, ZERO
-BFD09D1A 02FC004D MTC0 V0, Cause
-BFD09D1C 000002FC SLL S7, GP, 0
-BFD09D1E 18000000 SLL ZERO, ZERO, 3
-BFD09D20 0FBE1800 SB ZERO, 4030(ZERO)
+BFD09BB6 0008FC5E LW V0, 8(S8)\r
+BFD09BB8 004D0008 ADDQH.PH ZERO, T0, ZERO\r
+BFD09BBA 02FC004D MTC0 V0, Cause\r
+BFD09BBC 000002FC SLL S7, GP, 0\r
+BFD09BBE 18000000 SLL ZERO, ZERO, 3\r
+BFD09BC0 0FBE1800 SB ZERO, 4030(ZERO)\r
+BFD09BF6 0008FC5E LW V0, 8(S8)\r
+BFD09BF8 004D0008 ADDQH.PH ZERO, T0, ZERO\r
+BFD09BFA 02FC004D MTC0 V0, Cause\r
+BFD09BFC 000002FC SLL S7, GP, 0\r
+BFD09BFE 18000000 SLL ZERO, ZERO, 3\r
+BFD09C00 0FBE1800 SB ZERO, 4030(ZERO)\r
+BFD09C56 0008FC5E LW V0, 8(S8)\r
+BFD09C58 004D0008 ADDQH.PH ZERO, T0, ZERO\r
+BFD09C5A 02FC004D MTC0 V0, Cause\r
+BFD09C5C 000002FC SLL S7, GP, 0\r
+BFD09C5E 18000000 SLL ZERO, ZERO, 3\r
+BFD09C60 0FBE1800 SB ZERO, 4030(ZERO)\r
+BFD09CD6 0008FC5E LW V0, 8(S8)\r
+BFD09CD8 004D0008 ADDQH.PH ZERO, T0, ZERO\r
+BFD09CDA 02FC004D MTC0 V0, Cause\r
+BFD09CDC 000002FC SLL S7, GP, 0\r
+BFD09CDE 18000000 SLL ZERO, ZERO, 3\r
+BFD09CE0 0FBE1800 SB ZERO, 4030(ZERO)\r
+BFD09D16 0008FC5E LW V0, 8(S8)\r
+BFD09D18 004D0008 ADDQH.PH ZERO, T0, ZERO\r
+BFD09D1A 02FC004D MTC0 V0, Cause\r
+BFD09D1C 000002FC SLL S7, GP, 0\r
+BFD09D1E 18000000 SLL ZERO, ZERO, 3\r
+BFD09D20 0FBE1800 SB ZERO, 4030(ZERO)\r
168: "\n\t"\r
169: "mtc0 %0,$13,0 \n\t"\r
170: "ehb \n\t"\r
171: :\r
172: :"r" ( new_cause ) : );\r
173: }\r
-BFD09BC2 0FBE MOVE SP, S8
-BFD09BC4 4BC1 LW S8, 4(SP)
-BFD09BC6 459F JR16 RA
-BFD09BC8 4C05 ADDIU SP, SP, 8
-BFD09C02 0FBE MOVE SP, S8
-BFD09C04 4BC1 LW S8, 4(SP)
-BFD09C06 459F JR16 RA
-BFD09C08 4C05 ADDIU SP, SP, 8
-BFD09C62 0FBE MOVE SP, S8
-BFD09C64 4BC1 LW S8, 4(SP)
-BFD09C66 459F JR16 RA
-BFD09C68 4C05 ADDIU SP, SP, 8
-BFD09CE2 0FBE MOVE SP, S8
-BFD09CE4 4BC1 LW S8, 4(SP)
-BFD09CE6 459F JR16 RA
-BFD09CE8 4C05 ADDIU SP, SP, 8
-BFD09D22 0FBE MOVE SP, S8
-BFD09D24 4BC1 LW S8, 4(SP)
-BFD09D26 459F JR16 RA
-BFD09D28 4C05 ADDIU SP, SP, 8
+BFD09BC2 0FBE MOVE SP, S8\r
+BFD09BC4 4BC1 LW S8, 4(SP)\r
+BFD09BC6 459F JR16 RA\r
+BFD09BC8 4C05 ADDIU SP, SP, 8\r
+BFD09C02 0FBE MOVE SP, S8\r
+BFD09C04 4BC1 LW S8, 4(SP)\r
+BFD09C06 459F JR16 RA\r
+BFD09C08 4C05 ADDIU SP, SP, 8\r
+BFD09C62 0FBE MOVE SP, S8\r
+BFD09C64 4BC1 LW S8, 4(SP)\r
+BFD09C66 459F JR16 RA\r
+BFD09C68 4C05 ADDIU SP, SP, 8\r
+BFD09CE2 0FBE MOVE SP, S8\r
+BFD09CE4 4BC1 LW S8, 4(SP)\r
+BFD09CE6 459F JR16 RA\r
+BFD09CE8 4C05 ADDIU SP, SP, 8\r
+BFD09D22 0FBE MOVE SP, S8\r
+BFD09D24 4BC1 LW S8, 4(SP)\r
+BFD09D26 459F JR16 RA\r
+BFD09D28 4C05 ADDIU SP, SP, 8\r
174: /*-----------------------------------------------------------*/\r
175: \r
176: /* This clears the IPL bits, then sets them to\r
288: \r
289: #endif /* PORTMACRO_H */\r
290: \r
---- c:/e/dev/freertos/workingcopy/freertos/source/portable/mplab/pic32mec14xx/port.c ------------------
+--- c:/e/dev/freertos/workingcopy/freertos/source/portable/mplab/pic32mec14xx/port.c ------------------\r
1: /*\r
2: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
3: All rights reserved\r
8: \r
9: FreeRTOS is free software; you can redistribute it and/or modify it under\r
10: the terms of the GNU General Public License (version 2) as published by the\r
-11: Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+11: Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
12: \r
13: ***************************************************************************\r
14: >>! NOTE: The modification to the GPL is included to allow you to !<<\r
225: the need for compiler intrinsics which vary with compiler. */\r
226: static uint32_t prvDisableInterrupt( void )\r
227: {\r
-BFD09A98 4FF9 ADDIU SP, SP, -16
-BFD09A9A CBC3 SW S8, 12(SP)
-BFD09A9C CA02 SW S0, 8(SP)
-BFD09A9E 0FDD MOVE S8, SP
+BFD09A98 4FF9 ADDIU SP, SP, -16\r
+BFD09A9A CBC3 SW S8, 12(SP)\r
+BFD09A9C CA02 SW S0, 8(SP)\r
+BFD09A9E 0FDD MOVE S8, SP\r
228: uint32_t prev_state;\r
229: \r
230: __asm volatile( "di %0; ehb" : "=r" ( prev_state ) :: "memory" );\r
-BFD09AA0 477C0010 DI S0
-BFD09AA4 18000000 SLL ZERO, ZERO, 3
-BFD09AA6 FA1E1800 SB ZERO, -1506(ZERO)
-BFD09AA8 0000FA1E SW S0, 0(S8)
+BFD09AA0 477C0010 DI S0\r
+BFD09AA4 18000000 SLL ZERO, ZERO, 3\r
+BFD09AA6 FA1E1800 SB ZERO, -1506(ZERO)\r
+BFD09AA8 0000FA1E SW S0, 0(S8)\r
231: return prev_state;\r
-BFD09AAC 0000FC5E LW V0, 0(S8)
+BFD09AAC 0000FC5E LW V0, 0(S8)\r
232: }\r
-BFD09AB0 0FBE MOVE SP, S8
-BFD09AB2 4BC3 LW S8, 12(SP)
-BFD09AB4 4A02 LW S0, 8(SP)
-BFD09AB6 459F JR16 RA
-BFD09AB8 4C09 ADDIU SP, SP, 16
+BFD09AB0 0FBE MOVE SP, S8\r
+BFD09AB2 4BC3 LW S8, 12(SP)\r
+BFD09AB4 4A02 LW S0, 8(SP)\r
+BFD09AB6 459F JR16 RA\r
+BFD09AB8 4C09 ADDIU SP, SP, 16\r
233: \r
234: \r
235: /*\r
237: */\r
238: StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
239: {\r
-BFD05630 4FF5 ADDIU SP, SP, -24
-BFD05632 CBE5 SW RA, 20(SP)
-BFD05634 CBC4 SW S8, 16(SP)
-BFD05636 0FDD MOVE S8, SP
-BFD05638 0018F89E SW A0, 24(S8)
-BFD0563C 001CF8BE SW A1, 28(S8)
-BFD05640 0020F8DE SW A2, 32(S8)
+BFD05630 4FF5 ADDIU SP, SP, -24\r
+BFD05632 CBE5 SW RA, 20(SP)\r
+BFD05634 CBC4 SW S8, 16(SP)\r
+BFD05636 0FDD MOVE S8, SP\r
+BFD05638 0018F89E SW A0, 24(S8)\r
+BFD0563C 001CF8BE SW A1, 28(S8)\r
+BFD05640 0020F8DE SW A2, 32(S8)\r
240: /* Ensure byte alignment is maintained when leaving this function. */\r
241: pxTopOfStack--;\r
-BFD05644 0018FC5E LW V0, 24(S8)
-BFD05646 4C580018 MOVZ T1, T8, ZERO
-BFD05648 4C58 ADDIU V0, V0, -4
-BFD0564A 0018F85E SW V0, 24(S8)
+BFD05644 0018FC5E LW V0, 24(S8)\r
+BFD05646 4C580018 MOVZ T1, T8, ZERO\r
+BFD05648 4C58 ADDIU V0, V0, -4\r
+BFD0564A 0018F85E SW V0, 24(S8)\r
242: \r
243: *pxTopOfStack = (StackType_t) 0xDEADBEEF;\r
-BFD0564E 0018FC5E LW V0, 24(S8)
-BFD05652 DEAD41A3 LUI V1, 0xDEAD
-BFD05656 BEEF5063 ORI V1, V1, -16657
-BFD05658 E9A0BEEF LDC1 F23, -5728(T7)
-BFD0565A E9A0 SW V1, 0(V0)
+BFD0564E 0018FC5E LW V0, 24(S8)\r
+BFD05652 DEAD41A3 LUI V1, 0xDEAD\r
+BFD05656 BEEF5063 ORI V1, V1, -16657\r
+BFD05658 E9A0BEEF LDC1 F23, -5728(T7)\r
+BFD0565A E9A0 SW V1, 0(V0)\r
244: pxTopOfStack--;\r
-BFD0565C 0018FC5E LW V0, 24(S8)
-BFD0565E 4C580018 MOVZ T1, T8, ZERO
-BFD05660 4C58 ADDIU V0, V0, -4
-BFD05662 0018F85E SW V0, 24(S8)
+BFD0565C 0018FC5E LW V0, 24(S8)\r
+BFD0565E 4C580018 MOVZ T1, T8, ZERO\r
+BFD05660 4C58 ADDIU V0, V0, -4\r
+BFD05662 0018F85E SW V0, 24(S8)\r
245: \r
246: *pxTopOfStack = (StackType_t) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */\r
-BFD05666 0018FC5E LW V0, 24(S8)
-BFD0566A 123441A3 LUI V1, 0x1234
-BFD0566C 50631234 ADDI S1, S4, 20579
-BFD0566E 56785063 ORI V1, V1, 22136
-BFD05670 E9A05678 PREFX 29, 19(T8)
-BFD05672 E9A0 SW V1, 0(V0)
+BFD05666 0018FC5E LW V0, 24(S8)\r
+BFD0566A 123441A3 LUI V1, 0x1234\r
+BFD0566C 50631234 ADDI S1, S4, 20579\r
+BFD0566E 56785063 ORI V1, V1, 22136\r
+BFD05670 E9A05678 PREFX 29, 19(T8)\r
+BFD05672 E9A0 SW V1, 0(V0)\r
247: pxTopOfStack--;\r
-BFD05674 0018FC5E LW V0, 24(S8)
-BFD05676 4C580018 MOVZ T1, T8, ZERO
-BFD05678 4C58 ADDIU V0, V0, -4
-BFD0567A 0018F85E SW V0, 24(S8)
+BFD05674 0018FC5E LW V0, 24(S8)\r
+BFD05676 4C580018 MOVZ T1, T8, ZERO\r
+BFD05678 4C58 ADDIU V0, V0, -4\r
+BFD0567A 0018F85E SW V0, 24(S8)\r
248: \r
249: *pxTopOfStack = (StackType_t) ulPortGetCP0Cause();\r
-BFD0567E 4DC677E8 JALS ulPortGetCP0Cause
-BFD05680 4DC6 ADDIU T6, T6, 3
-BFD05682 0C00 NOP
-BFD05684 0C62 MOVE V1, V0
-BFD05686 0018FC5E LW V0, 24(S8)
-BFD0568A E9A0 SW V1, 0(V0)
+BFD0567E 4DC677E8 JALS ulPortGetCP0Cause\r
+BFD05680 4DC6 ADDIU T6, T6, 3\r
+BFD05682 0C00 NOP\r
+BFD05684 0C62 MOVE V1, V0\r
+BFD05686 0018FC5E LW V0, 24(S8)\r
+BFD0568A E9A0 SW V1, 0(V0)\r
250: pxTopOfStack--;\r
-BFD0568C 0018FC5E LW V0, 24(S8)
-BFD0568E 4C580018 MOVZ T1, T8, ZERO
-BFD05690 4C58 ADDIU V0, V0, -4
-BFD05692 0018F85E SW V0, 24(S8)
+BFD0568C 0018FC5E LW V0, 24(S8)\r
+BFD0568E 4C580018 MOVZ T1, T8, ZERO\r
+BFD05690 4C58 ADDIU V0, V0, -4\r
+BFD05692 0018F85E SW V0, 24(S8)\r
251: \r
252: *pxTopOfStack = (StackType_t) portINITIAL_SR; /* CP0_STATUS */\r
-BFD05696 0018FC5E LW V0, 24(S8)
-BFD0569A ED83 LI V1, 3
-BFD0569C E9A0 SW V1, 0(V0)
+BFD05696 0018FC5E LW V0, 24(S8)\r
+BFD0569A ED83 LI V1, 3\r
+BFD0569C E9A0 SW V1, 0(V0)\r
253: pxTopOfStack--;\r
-BFD0569E 0018FC5E LW V0, 24(S8)
-BFD056A0 4C580018 MOVZ T1, T8, ZERO
-BFD056A2 4C58 ADDIU V0, V0, -4
-BFD056A4 0018F85E SW V0, 24(S8)
+BFD0569E 0018FC5E LW V0, 24(S8)\r
+BFD056A0 4C580018 MOVZ T1, T8, ZERO\r
+BFD056A2 4C58 ADDIU V0, V0, -4\r
+BFD056A4 0018F85E SW V0, 24(S8)\r
254: \r
255: *pxTopOfStack = (StackType_t) pxCode; /* CP0_EPC */\r
-BFD056A8 001CFC7E LW V1, 28(S8)
-BFD056AC 0018FC5E LW V0, 24(S8)
-BFD056B0 E9A0 SW V1, 0(V0)
+BFD056A8 001CFC7E LW V1, 28(S8)\r
+BFD056AC 0018FC5E LW V0, 24(S8)\r
+BFD056B0 E9A0 SW V1, 0(V0)\r
256: pxTopOfStack--;\r
-BFD056B2 0018FC5E LW V0, 24(S8)
-BFD056B4 4C580018 MOVZ T1, T8, ZERO
-BFD056B6 4C58 ADDIU V0, V0, -4
-BFD056B8 0018F85E SW V0, 24(S8)
+BFD056B2 0018FC5E LW V0, 24(S8)\r
+BFD056B4 4C580018 MOVZ T1, T8, ZERO\r
+BFD056B6 4C58 ADDIU V0, V0, -4\r
+BFD056B8 0018F85E SW V0, 24(S8)\r
257: \r
258: *pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS; /* ra */\r
-BFD056BC BFD041A2 LUI V0, 0xBFD0
-BFD056BE 3062BFD0 LDC1 F30, 12386(S0)
-BFD056C0 7BBD3062 ADDIU V1, V0, 31677
-BFD056C2 FC5E7BBD ADDIUPC A3, 4062302
-BFD056C4 0018FC5E LW V0, 24(S8)
-BFD056C8 E9A0 SW V1, 0(V0)
+BFD056BC BFD041A2 LUI V0, 0xBFD0\r
+BFD056BE 3062BFD0 LDC1 F30, 12386(S0)\r
+BFD056C0 7BBD3062 ADDIU V1, V0, 31677\r
+BFD056C2 FC5E7BBD ADDIUPC A3, 4062302\r
+BFD056C4 0018FC5E LW V0, 24(S8)\r
+BFD056C8 E9A0 SW V1, 0(V0)\r
259: pxTopOfStack -= 15;\r
-BFD056CA 0018FC5E LW V0, 24(S8)
-BFD056CE FFC43042 ADDIU V0, V0, -60
-BFD056D0 F85EFFC4 LW S8, -1954(A0)
-BFD056D2 0018F85E SW V0, 24(S8)
+BFD056CA 0018FC5E LW V0, 24(S8)\r
+BFD056CE FFC43042 ADDIU V0, V0, -60\r
+BFD056D0 F85EFFC4 LW S8, -1954(A0)\r
+BFD056D2 0018F85E SW V0, 24(S8)\r
260: \r
261: *pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */\r
-BFD056D6 0020FC7E LW V1, 32(S8)
-BFD056DA 0018FC5E LW V0, 24(S8)
-BFD056DE E9A0 SW V1, 0(V0)
+BFD056D6 0020FC7E LW V1, 32(S8)\r
+BFD056DA 0018FC5E LW V0, 24(S8)\r
+BFD056DE E9A0 SW V1, 0(V0)\r
262: pxTopOfStack -= 15;\r
-BFD056E0 0018FC5E LW V0, 24(S8)
-BFD056E4 FFC43042 ADDIU V0, V0, -60
-BFD056E6 F85EFFC4 LW S8, -1954(A0)
-BFD056E8 0018F85E SW V0, 24(S8)
+BFD056E0 0018FC5E LW V0, 24(S8)\r
+BFD056E4 FFC43042 ADDIU V0, V0, -60\r
+BFD056E6 F85EFFC4 LW S8, -1954(A0)\r
+BFD056E8 0018F85E SW V0, 24(S8)\r
263: \r
264: return pxTopOfStack;\r
-BFD056EC 0018FC5E LW V0, 24(S8)
+BFD056EC 0018FC5E LW V0, 24(S8)\r
265: }\r
-BFD056F0 0FBE MOVE SP, S8
-BFD056F2 4BE5 LW RA, 20(SP)
-BFD056F4 4BC4 LW S8, 16(SP)
-BFD056F6 4C0D ADDIU SP, SP, 24
-BFD056F8 459F JR16 RA
-BFD056FA 0C00 NOP
+BFD056F0 0FBE MOVE SP, S8\r
+BFD056F2 4BE5 LW RA, 20(SP)\r
+BFD056F4 4BC4 LW S8, 16(SP)\r
+BFD056F6 4C0D ADDIU SP, SP, 24\r
+BFD056F8 459F JR16 RA\r
+BFD056FA 0C00 NOP\r
266: /*-----------------------------------------------------------*/\r
267: \r
268: static void prvTaskExitError( void )\r
269: {\r
-BFD07BBC 4FF1 ADDIU SP, SP, -32
-BFD07BBE CBE7 SW RA, 28(SP)
-BFD07BC0 CBC6 SW S8, 24(SP)
-BFD07BC2 0FDD MOVE S8, SP
+BFD07BBC 4FF1 ADDIU SP, SP, -32\r
+BFD07BBE CBE7 SW RA, 28(SP)\r
+BFD07BC0 CBC6 SW S8, 24(SP)\r
+BFD07BC2 0FDD MOVE S8, SP\r
270: /* A function that implements a task must not exit or attempt to return to\r
271: its caller as there is nothing to return to. If a task wants to exit it\r
272: should instead call vTaskDelete( NULL ).\r
274: Artificially force an assert() to be triggered if configASSERT() is\r
275: defined, then stop here so application writers can catch the error. */\r
276: configASSERT( uxSavedTaskStackPointer == 0UL );\r
-BFD07BC4 802CFC5C LW V0, -32724(GP)
-BFD07BC8 000940E2 BEQZC V0, 0xBFD07BDE
-BFD07BCC BFD141A2 LUI V0, 0xBFD1
-BFD07BCE 3082BFD1 LDC1 F30, 12418(S1)
-BFD07BD0 8AAC3082 ADDIU A0, V0, -30036
-BFD07BD2 8AAC SB A1, 12(V0)
-BFD07BD4 011430A0 ADDIU A1, ZERO, 276
-BFD07BD8 4B7E77E8 JALS vAssertCalled
-BFD07BDA 4B7E LW K1, 120(SP)
-BFD07BDC 0C00 NOP
+BFD07BC4 802CFC5C LW V0, -32724(GP)\r
+BFD07BC8 000940E2 BEQZC V0, 0xBFD07BDE\r
+BFD07BCC BFD141A2 LUI V0, 0xBFD1\r
+BFD07BCE 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD07BD0 8AAC3082 ADDIU A0, V0, -30036\r
+BFD07BD2 8AAC SB A1, 12(V0)\r
+BFD07BD4 011430A0 ADDIU A1, ZERO, 276\r
+BFD07BD8 4B7E77E8 JALS vAssertCalled\r
+BFD07BDA 4B7E LW K1, 120(SP)\r
+BFD07BDC 0C00 NOP\r
277: portDISABLE_INTERRUPTS();\r
-BFD07BDE 4DA677E8 JALS ulPortGetCP0Status
-BFD07BE0 4DA6 ADDIU T5, T5, 3
-BFD07BE2 0C00 NOP
-BFD07BE4 0010F85E SW V0, 16(S8)
-BFD07BE8 0010FC7E LW V1, 16(S8)
-BFD07BEC 000141A2 LUI V0, 0x1
-BFD07BF0 FC005042 ORI V0, V0, -1024
-BFD07BF2 4493FC00 LW ZERO, 17555(ZERO)
-BFD07BF4 4493 AND16 V0, V1
-BFD07BF6 50400042 SRL V0, V0, 10
-BFD07BF8 B0425040 ORI V0, ZERO, -20414
-BFD07BFA 0003B042 SLTIU V0, V0, 3
-BFD07BFE 001140E2 BEQZC V0, 0xBFD07C24
-BFD07C02 0010FC7E LW V1, 16(S8)
-BFD07C06 FFFE41A2 LUI V0, 0xFFFE
-BFD07C08 5042FFFE LW RA, 20546(S8)
-BFD07C0A 03FF5042 ORI V0, V0, 1023
-BFD07C0E 4493 AND16 V0, V1
-BFD07C10 0010F85E SW V0, 16(S8)
-BFD07C14 0010FC5E LW V0, 16(S8)
-BFD07C18 0C005042 ORI V0, V0, 3072
-BFD07C1A 0C00 NOP
-BFD07C1C 0C82 MOVE A0, V0
-BFD07C1E 4DB677E8 JALS vPortSetCP0Status
-BFD07C20 4DB6 ADDIU T5, T5, -5
-BFD07C22 0C00 NOP
+BFD07BDE 4DA677E8 JALS ulPortGetCP0Status\r
+BFD07BE0 4DA6 ADDIU T5, T5, 3\r
+BFD07BE2 0C00 NOP\r
+BFD07BE4 0010F85E SW V0, 16(S8)\r
+BFD07BE8 0010FC7E LW V1, 16(S8)\r
+BFD07BEC 000141A2 LUI V0, 0x1\r
+BFD07BF0 FC005042 ORI V0, V0, -1024\r
+BFD07BF2 4493FC00 LW ZERO, 17555(ZERO)\r
+BFD07BF4 4493 AND16 V0, V1\r
+BFD07BF6 50400042 SRL V0, V0, 10\r
+BFD07BF8 B0425040 ORI V0, ZERO, -20414\r
+BFD07BFA 0003B042 SLTIU V0, V0, 3\r
+BFD07BFE 001140E2 BEQZC V0, 0xBFD07C24\r
+BFD07C02 0010FC7E LW V1, 16(S8)\r
+BFD07C06 FFFE41A2 LUI V0, 0xFFFE\r
+BFD07C08 5042FFFE LW RA, 20546(S8)\r
+BFD07C0A 03FF5042 ORI V0, V0, 1023\r
+BFD07C0E 4493 AND16 V0, V1\r
+BFD07C10 0010F85E SW V0, 16(S8)\r
+BFD07C14 0010FC5E LW V0, 16(S8)\r
+BFD07C18 0C005042 ORI V0, V0, 3072\r
+BFD07C1A 0C00 NOP\r
+BFD07C1C 0C82 MOVE A0, V0\r
+BFD07C1E 4DB677E8 JALS vPortSetCP0Status\r
+BFD07C20 4DB6 ADDIU T5, T5, -5\r
+BFD07C22 0C00 NOP\r
278: for( ;; );\r
-BFD07C24 CFFF B 0xBFD07C24
-BFD07C26 0C00 NOP
+BFD07C24 CFFF B 0xBFD07C24\r
+BFD07C26 0C00 NOP\r
279: }\r
280: /*-----------------------------------------------------------*/\r
281: \r
290: */\r
291: __attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )\r
292: {\r
-BFD06284 4FF1 ADDIU SP, SP, -32
-BFD06286 CBE7 SW RA, 28(SP)
-BFD06288 CBC6 SW S8, 24(SP)
-BFD0628A 0FDD MOVE S8, SP
+BFD06284 4FF1 ADDIU SP, SP, -32\r
+BFD06286 CBE7 SW RA, 28(SP)\r
+BFD06288 CBC6 SW S8, 24(SP)\r
+BFD0628A 0FDD MOVE S8, SP\r
293: /* MEC14xx RTOS Timer whose input clock is 32KHz */\r
294: const uint32_t preload = ( 32768ul / ( configTICK_RATE_HZ ) );\r
-BFD0628C ED20 LI V0, 32
-BFD0628E 0010F85E SW V0, 16(S8)
+BFD0628C ED20 LI V0, 32\r
+BFD0628E 0010F85E SW V0, 16(S8)\r
295: configASSERT( preload != 0UL );\r
-BFD06292 0010FC5E LW V0, 16(S8)
-BFD06296 000940A2 BNEZC V0, 0xBFD062AC
-BFD0629A BFD141A2 LUI V0, 0xBFD1
-BFD0629C 3082BFD1 LDC1 F30, 12418(S1)
-BFD0629E 8AAC3082 ADDIU A0, V0, -30036
-BFD062A0 8AAC SB A1, 12(V0)
-BFD062A2 012730A0 ADDIU A1, ZERO, 295
-BFD062A6 4B7E77E8 JALS vAssertCalled
-BFD062A8 4B7E LW K1, 120(SP)
-BFD062AA 0C00 NOP
+BFD06292 0010FC5E LW V0, 16(S8)\r
+BFD06296 000940A2 BNEZC V0, 0xBFD062AC\r
+BFD0629A BFD141A2 LUI V0, 0xBFD1\r
+BFD0629C 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD0629E 8AAC3082 ADDIU A0, V0, -30036\r
+BFD062A0 8AAC SB A1, 12(V0)\r
+BFD062A2 012730A0 ADDIU A1, ZERO, 295\r
+BFD062A6 4B7E77E8 JALS vAssertCalled\r
+BFD062A8 4B7E LW K1, 120(SP)\r
+BFD062AA 0C00 NOP\r
296: \r
297: portMMCR_RTMR_CONTROL = 0ul;\r
-BFD062AC A00041A2 LUI V0, 0xA000
-BFD062B0 74085042 ORI V0, V0, 29704
-BFD062B2 E8207408 JALS 0xB811D040
-BFD062B4 E820 SW S0, 0(V0)
+BFD062AC A00041A2 LUI V0, 0xA000\r
+BFD062B0 74085042 ORI V0, V0, 29704\r
+BFD062B2 E8207408 JALS 0xB811D040\r
+BFD062B4 E820 SW S0, 0(V0)\r
298: portMMCR_RTMR_PRELOAD = preload;\r
-BFD062B6 A00041A2 LUI V0, 0xA000
-BFD062BA 74045042 ORI V0, V0, 29700
-BFD062BC FC7E7404 JALS 0xB809F8FC
-BFD062BE 0010FC7E LW V1, 16(S8)
-BFD062C2 E9A0 SW V1, 0(V0)
+BFD062B6 A00041A2 LUI V0, 0xA000\r
+BFD062BA 74045042 ORI V0, V0, 29700\r
+BFD062BC FC7E7404 JALS 0xB809F8FC\r
+BFD062BE 0010FC7E LW V1, 16(S8)\r
+BFD062C2 E9A0 SW V1, 0(V0)\r
299: \r
300: portMMCR_JTVIC_GIRQ23_SRC = ( portGIRQ23_RTOS_TIMER_MASK );\r
-BFD062C4 BFFF41A2 LUI V0, 0xBFFF
-BFD062C6 5042BFFF LDC1 F31, 20546(RA)
-BFD062C8 C0F05042 ORI V0, V0, -16144
-BFD062CC ED90 LI V1, 16
-BFD062CE E9A0 SW V1, 0(V0)
+BFD062C4 BFFF41A2 LUI V0, 0xBFFF\r
+BFD062C6 5042BFFF LDC1 F31, 20546(RA)\r
+BFD062C8 C0F05042 ORI V0, V0, -16144\r
+BFD062CC ED90 LI V1, 16\r
+BFD062CE E9A0 SW V1, 0(V0)\r
301: portMMCR_JTVIC_GIRQ23_PRIA &= ~( 0x0Ful << 16 );\r
-BFD062D0 BFFF41A2 LUI V0, 0xBFFF
-BFD062D2 5042BFFF LDC1 F31, 20546(RA)
-BFD062D4 C3F05042 ORI V0, V0, -15376
-BFD062D8 BFFF41A3 LUI V1, 0xBFFF
-BFD062DA 5063BFFF LDC1 F31, 20579(RA)
-BFD062DC C3F05063 ORI V1, V1, -15376
-BFD062E0 6A30 LW A0, 0(V1)
-BFD062E2 FFF041A3 LUI V1, 0xFFF0
-BFD062E4 5063FFF0 LW RA, 20579(S0)
-BFD062E6 FFFF5063 ORI V1, V1, -1
-BFD062E8 449CFFFF LW RA, 17564(RA)
-BFD062EA 449C AND16 V1, A0
-BFD062EC E9A0 SW V1, 0(V0)
+BFD062D0 BFFF41A2 LUI V0, 0xBFFF\r
+BFD062D2 5042BFFF LDC1 F31, 20546(RA)\r
+BFD062D4 C3F05042 ORI V0, V0, -15376\r
+BFD062D8 BFFF41A3 LUI V1, 0xBFFF\r
+BFD062DA 5063BFFF LDC1 F31, 20579(RA)\r
+BFD062DC C3F05063 ORI V1, V1, -15376\r
+BFD062E0 6A30 LW A0, 0(V1)\r
+BFD062E2 FFF041A3 LUI V1, 0xFFF0\r
+BFD062E4 5063FFF0 LW RA, 20579(S0)\r
+BFD062E6 FFFF5063 ORI V1, V1, -1\r
+BFD062E8 449CFFFF LW RA, 17564(RA)\r
+BFD062EA 449C AND16 V1, A0\r
+BFD062EC E9A0 SW V1, 0(V0)\r
302: portMMCR_JTVIC_GIRQ23_PRIA |= ( ( configKERNEL_INTERRUPT_PRIORITY ) << 16 );\r
-BFD062EE BFFF41A2 LUI V0, 0xBFFF
-BFD062F0 5042BFFF LDC1 F31, 20546(RA)
-BFD062F2 C3F05042 ORI V0, V0, -15376
-BFD062F6 BFFF41A3 LUI V1, 0xBFFF
-BFD062F8 5063BFFF LDC1 F31, 20579(RA)
-BFD062FA C3F05063 ORI V1, V1, -15376
-BFD062FE 69B0 LW V1, 0(V1)
-BFD06300 E9A0 SW V1, 0(V0)
+BFD062EE BFFF41A2 LUI V0, 0xBFFF\r
+BFD062F0 5042BFFF LDC1 F31, 20546(RA)\r
+BFD062F2 C3F05042 ORI V0, V0, -15376\r
+BFD062F6 BFFF41A3 LUI V1, 0xBFFF\r
+BFD062F8 5063BFFF LDC1 F31, 20579(RA)\r
+BFD062FA C3F05063 ORI V1, V1, -15376\r
+BFD062FE 69B0 LW V1, 0(V1)\r
+BFD06300 E9A0 SW V1, 0(V0)\r
303: portMMCR_JTVIC_GIRQ23_SETEN = ( portGIRQ23_RTOS_TIMER_MASK );\r
-BFD06302 BFFF41A2 LUI V0, 0xBFFF
-BFD06304 5042BFFF LDC1 F31, 20546(RA)
-BFD06306 C0F45042 ORI V0, V0, -16140
-BFD0630A ED90 LI V1, 16
-BFD0630C E9A0 SW V1, 0(V0)
+BFD06302 BFFF41A2 LUI V0, 0xBFFF\r
+BFD06304 5042BFFF LDC1 F31, 20546(RA)\r
+BFD06306 C0F45042 ORI V0, V0, -16140\r
+BFD0630A ED90 LI V1, 16\r
+BFD0630C E9A0 SW V1, 0(V0)\r
304: \r
305: portMMCR_RTMR_CONTROL = 0x0Fu;\r
-BFD0630E A00041A2 LUI V0, 0xA000
-BFD06312 74085042 ORI V0, V0, 29704
-BFD06314 ED8F7408 JALS 0xB811DB1E
-BFD06316 ED8F LI V1, 15
-BFD06318 E9A0 SW V1, 0(V0)
+BFD0630E A00041A2 LUI V0, 0xA000\r
+BFD06312 74085042 ORI V0, V0, 29704\r
+BFD06314 ED8F7408 JALS 0xB811DB1E\r
+BFD06316 ED8F LI V1, 15\r
+BFD06318 E9A0 SW V1, 0(V0)\r
306: }\r
-BFD0631A 0FBE MOVE SP, S8
-BFD0631C 4BE7 LW RA, 28(SP)
-BFD0631E 4BC6 LW S8, 24(SP)
-BFD06320 4C11 ADDIU SP, SP, 32
-BFD06322 459F JR16 RA
-BFD06324 0C00 NOP
+BFD0631A 0FBE MOVE SP, S8\r
+BFD0631C 4BE7 LW RA, 28(SP)\r
+BFD0631E 4BC6 LW S8, 24(SP)\r
+BFD06320 4C11 ADDIU SP, SP, 32\r
+BFD06322 459F JR16 RA\r
+BFD06324 0C00 NOP\r
307: /*-----------------------------------------------------------*/\r
308: \r
309: void vPortEndScheduler(void)\r
310: {\r
-BFD097A8 4FF5 ADDIU SP, SP, -24
-BFD097AA CBE5 SW RA, 20(SP)
-BFD097AC CBC4 SW S8, 16(SP)
-BFD097AE 0FDD MOVE S8, SP
+BFD097A8 4FF5 ADDIU SP, SP, -24\r
+BFD097AA CBE5 SW RA, 20(SP)\r
+BFD097AC CBC4 SW S8, 16(SP)\r
+BFD097AE 0FDD MOVE S8, SP\r
311: /* Not implemented in ports where there is nothing to return to.\r
312: Artificially force an assert. */\r
313: configASSERT( uxInterruptNesting == 1000UL );\r
-BFD097B0 8014FC7C LW V1, -32748(GP)
-BFD097B4 03E83040 ADDIU V0, ZERO, 1000
-BFD097B8 000A9443 BEQ V1, V0, 0xBFD097D0
-BFD097BA 0C00000A SLL ZERO, T2, 1
-BFD097BC 0C00 NOP
-BFD097BE BFD141A2 LUI V0, 0xBFD1
-BFD097C0 3082BFD1 LDC1 F30, 12418(S1)
-BFD097C2 8AAC3082 ADDIU A0, V0, -30036
-BFD097C4 8AAC SB A1, 12(V0)
-BFD097C6 013930A0 ADDIU A1, ZERO, 313
-BFD097CA 4B7E77E8 JALS vAssertCalled
-BFD097CC 4B7E LW K1, 120(SP)
-BFD097CE 0C00 NOP
+BFD097B0 8014FC7C LW V1, -32748(GP)\r
+BFD097B4 03E83040 ADDIU V0, ZERO, 1000\r
+BFD097B8 000A9443 BEQ V1, V0, 0xBFD097D0\r
+BFD097BA 0C00000A SLL ZERO, T2, 1\r
+BFD097BC 0C00 NOP\r
+BFD097BE BFD141A2 LUI V0, 0xBFD1\r
+BFD097C0 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD097C2 8AAC3082 ADDIU A0, V0, -30036\r
+BFD097C4 8AAC SB A1, 12(V0)\r
+BFD097C6 013930A0 ADDIU A1, ZERO, 313\r
+BFD097CA 4B7E77E8 JALS vAssertCalled\r
+BFD097CC 4B7E LW K1, 120(SP)\r
+BFD097CE 0C00 NOP\r
314: }\r
-BFD097D0 0FBE MOVE SP, S8
-BFD097D2 4BE5 LW RA, 20(SP)
-BFD097D4 4BC4 LW S8, 16(SP)
-BFD097D6 4C0D ADDIU SP, SP, 24
-BFD097D8 459F JR16 RA
-BFD097DA 0C00 NOP
+BFD097D0 0FBE MOVE SP, S8\r
+BFD097D2 4BE5 LW RA, 20(SP)\r
+BFD097D4 4BC4 LW S8, 16(SP)\r
+BFD097D6 4C0D ADDIU SP, SP, 24\r
+BFD097D8 459F JR16 RA\r
+BFD097DA 0C00 NOP\r
315: /*-----------------------------------------------------------*/\r
316: \r
317: BaseType_t xPortStartScheduler( void )\r
318: {\r
-BFD06898 4FF5 ADDIU SP, SP, -24
-BFD0689A CBE5 SW RA, 20(SP)
-BFD0689C CBC4 SW S8, 16(SP)
-BFD0689E 0FDD MOVE S8, SP
+BFD06898 4FF5 ADDIU SP, SP, -24\r
+BFD0689A CBE5 SW RA, 20(SP)\r
+BFD0689C CBC4 SW S8, 16(SP)\r
+BFD0689E 0FDD MOVE S8, SP\r
319: extern void vPortStartFirstTask( void );\r
320: extern void *pxCurrentTCB;\r
321: \r
323: {\r
324: /* Fill the ISR stack to make it easy to asses how much is being used. */\r
325: memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );\r
-BFD068A0 BFD241A2 LUI V0, 0xBFD2
-BFD068A2 3082BFD2 LDC1 F30, 12418(S2)
-BFD068A4 AD683082 ADDIU A0, V0, -21144
-BFD068A6 AD68 BNEZ V0, 0xBFD06978
-BFD068A8 00EE30A0 ADDIU A1, ZERO, 238
-BFD068AA 30C000EE ROTR A3, T6, 6
-BFD068AC 0BE030C0 ADDIU A2, ZERO, 3040
-BFD068AE 0BE0 LBU A3, 0(A2)
-BFD068B0 36F677E8 JALS 0xBFD06DEC
-BFD068B2 0C0036F6 LHU S7, 3072(S6)
-BFD068B4 0C00 NOP
+BFD068A0 BFD241A2 LUI V0, 0xBFD2\r
+BFD068A2 3082BFD2 LDC1 F30, 12418(S2)\r
+BFD068A4 AD683082 ADDIU A0, V0, -21144\r
+BFD068A6 AD68 BNEZ V0, 0xBFD06978\r
+BFD068A8 00EE30A0 ADDIU A1, ZERO, 238\r
+BFD068AA 30C000EE ROTR A3, T6, 6\r
+BFD068AC 0BE030C0 ADDIU A2, ZERO, 3040\r
+BFD068AE 0BE0 LBU A3, 0(A2)\r
+BFD068B0 36F677E8 JALS 0xBFD06DEC\r
+BFD068B2 0C0036F6 LHU S7, 3072(S6)\r
+BFD068B4 0C00 NOP\r
326: }\r
327: #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */\r
328: \r
329: /* Clear the software interrupt flag. */\r
330: portMMCR_JTVIC_GIRQ24_SRC = (portGIRQ24_M14K_SOFTIRQ0_MASK);\r
-BFD068B6 BFFF41A2 LUI V0, 0xBFFF
-BFD068B8 5042BFFF LDC1 F31, 20546(RA)
-BFD068BA C1005042 ORI V0, V0, -16128
-BFD068BE ED82 LI V1, 2
-BFD068C0 E9A0 SW V1, 0(V0)
+BFD068B6 BFFF41A2 LUI V0, 0xBFFF\r
+BFD068B8 5042BFFF LDC1 F31, 20546(RA)\r
+BFD068BA C1005042 ORI V0, V0, -16128\r
+BFD068BE ED82 LI V1, 2\r
+BFD068C0 E9A0 SW V1, 0(V0)\r
331: \r
332: /* Set software timer priority.\r
333: Each GIRQn has one nibble containing its priority */\r
334: portMMCR_JTVIC_GIRQ24_PRIA &= ~(0xF0ul);\r
-BFD068C2 BFFF41A2 LUI V0, 0xBFFF
-BFD068C4 5042BFFF LDC1 F31, 20546(RA)
-BFD068C6 C4005042 ORI V0, V0, -15360
-BFD068CA BFFF41A3 LUI V1, 0xBFFF
-BFD068CC 5063BFFF LDC1 F31, 20579(RA)
-BFD068CE C4005063 ORI V1, V1, -15360
-BFD068D2 6A30 LW A0, 0(V1)
-BFD068D4 FF0F3060 ADDIU V1, ZERO, -241
-BFD068D6 449CFF0F LW T8, 17564(T7)
-BFD068D8 449C AND16 V1, A0
-BFD068DA E9A0 SW V1, 0(V0)
+BFD068C2 BFFF41A2 LUI V0, 0xBFFF\r
+BFD068C4 5042BFFF LDC1 F31, 20546(RA)\r
+BFD068C6 C4005042 ORI V0, V0, -15360\r
+BFD068CA BFFF41A3 LUI V1, 0xBFFF\r
+BFD068CC 5063BFFF LDC1 F31, 20579(RA)\r
+BFD068CE C4005063 ORI V1, V1, -15360\r
+BFD068D2 6A30 LW A0, 0(V1)\r
+BFD068D4 FF0F3060 ADDIU V1, ZERO, -241\r
+BFD068D6 449CFF0F LW T8, 17564(T7)\r
+BFD068D8 449C AND16 V1, A0\r
+BFD068DA E9A0 SW V1, 0(V0)\r
335: portMMCR_JTVIC_GIRQ24_PRIA |= ( configKERNEL_INTERRUPT_PRIORITY << 4 );\r
-BFD068DC BFFF41A2 LUI V0, 0xBFFF
-BFD068DE 5042BFFF LDC1 F31, 20546(RA)
-BFD068E0 C4005042 ORI V0, V0, -15360
-BFD068E4 BFFF41A3 LUI V1, 0xBFFF
-BFD068E6 5063BFFF LDC1 F31, 20579(RA)
-BFD068E8 C4005063 ORI V1, V1, -15360
-BFD068EC 69B0 LW V1, 0(V1)
-BFD068EE E9A0 SW V1, 0(V0)
+BFD068DC BFFF41A2 LUI V0, 0xBFFF\r
+BFD068DE 5042BFFF LDC1 F31, 20546(RA)\r
+BFD068E0 C4005042 ORI V0, V0, -15360\r
+BFD068E4 BFFF41A3 LUI V1, 0xBFFF\r
+BFD068E6 5063BFFF LDC1 F31, 20579(RA)\r
+BFD068E8 C4005063 ORI V1, V1, -15360\r
+BFD068EC 69B0 LW V1, 0(V1)\r
+BFD068EE E9A0 SW V1, 0(V0)\r
336: \r
337: /* Enable software interrupt. */\r
338: portMMCR_JTVIC_GIRQ24_SETEN = ( portGIRQ24_M14K_SOFTIRQ0_MASK );\r
-BFD068F0 BFFF41A2 LUI V0, 0xBFFF
-BFD068F2 5042BFFF LDC1 F31, 20546(RA)
-BFD068F4 C1045042 ORI V0, V0, -16124
-BFD068F8 ED82 LI V1, 2
-BFD068FA E9A0 SW V1, 0(V0)
+BFD068F0 BFFF41A2 LUI V0, 0xBFFF\r
+BFD068F2 5042BFFF LDC1 F31, 20546(RA)\r
+BFD068F4 C1045042 ORI V0, V0, -16124\r
+BFD068F8 ED82 LI V1, 2\r
+BFD068FA E9A0 SW V1, 0(V0)\r
339: \r
340: /* Setup the timer to generate the tick. Interrupts will have been\r
341: disabled by the time we get here. */\r
342: vApplicationSetupTickTimerInterrupt();\r
-BFD068FC 314277E8 JALS vApplicationSetupTickTimerInterrupt
-BFD068FE 0C003142 ADDIU T2, V0, 3072
-BFD06900 0C00 NOP
+BFD068FC 314277E8 JALS vApplicationSetupTickTimerInterrupt\r
+BFD068FE 0C003142 ADDIU T2, V0, 3072\r
+BFD06900 0C00 NOP\r
343: \r
344: /* Kick off the highest priority task that has been created so far.\r
345: Its stack location is loaded into uxSavedTaskStackPointer. */\r
346: uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;\r
-BFD06902 8030FC5C LW V0, -32720(GP)
-BFD06906 6920 LW V0, 0(V0)
-BFD06908 802CF85C SW V0, -32724(GP)
+BFD06902 8030FC5C LW V0, -32720(GP)\r
+BFD06906 6920 LW V0, 0(V0)\r
+BFD06908 802CF85C SW V0, -32724(GP)\r
347: vPortStartFirstTask();\r
-BFD0690C 055A77E8 JALS 0xBFD00AB4
-BFD0690E 055A ADDU V0, A1, A1
-BFD06910 0C00 NOP
+BFD0690C 055A77E8 JALS 0xBFD00AB4\r
+BFD0690E 055A ADDU V0, A1, A1\r
+BFD06910 0C00 NOP\r
348: \r
349: /* Should never get here as the tasks will now be executing! Call the task\r
350: exit error function to prevent compiler warnings about a static function\r
351: not being called in the case that the application writer overrides this\r
352: functionality by defining configTASK_RETURN_ADDRESS. */\r
353: prvTaskExitError();\r
-BFD06912 3DDE77E8 JALS prvTaskExitError
-BFD06914 0C003DDE LH T6, 3072(S8)
-BFD06916 0C00 NOP
+BFD06912 3DDE77E8 JALS prvTaskExitError\r
+BFD06914 0C003DDE LH T6, 3072(S8)\r
+BFD06916 0C00 NOP\r
354: \r
355: return pdFALSE;\r
-BFD06918 0C40 MOVE V0, ZERO
+BFD06918 0C40 MOVE V0, ZERO\r
356: }\r
-BFD0691A 0FBE MOVE SP, S8
-BFD0691C 4BE5 LW RA, 20(SP)
-BFD0691E 4BC4 LW S8, 16(SP)
-BFD06920 4C0D ADDIU SP, SP, 24
-BFD06922 459F JR16 RA
-BFD06924 0C00 NOP
+BFD0691A 0FBE MOVE SP, S8\r
+BFD0691C 4BE5 LW RA, 20(SP)\r
+BFD0691E 4BC4 LW S8, 16(SP)\r
+BFD06920 4C0D ADDIU SP, SP, 24\r
+BFD06922 459F JR16 RA\r
+BFD06924 0C00 NOP\r
357: /*-----------------------------------------------------------*/\r
358: \r
359: void vPortIncrementTick( void )\r
360: {\r
-BFD069B8 4FF1 ADDIU SP, SP, -32
-BFD069BA CBE7 SW RA, 28(SP)
-BFD069BC CBC6 SW S8, 24(SP)
-BFD069BE 0FDD MOVE S8, SP
+BFD069B8 4FF1 ADDIU SP, SP, -32\r
+BFD069BA CBE7 SW RA, 28(SP)\r
+BFD069BC CBC6 SW S8, 24(SP)\r
+BFD069BE 0FDD MOVE S8, SP\r
361: UBaseType_t uxSavedStatus;\r
362: uint32_t ulCause;\r
363: \r
364: uxSavedStatus = uxPortSetInterruptMaskFromISR();\r
-BFD069C0 475E77E8 JALS uxPortSetInterruptMaskFromISR
-BFD069C4 0C00 NOP
-BFD069C6 0010F85E SW V0, 16(S8)
+BFD069C0 475E77E8 JALS uxPortSetInterruptMaskFromISR\r
+BFD069C4 0C00 NOP\r
+BFD069C6 0010F85E SW V0, 16(S8)\r
365: {\r
366: if( xTaskIncrementTick() != pdFALSE )\r
-BFD069CA 104077E8 JALS xTaskIncrementTick
-BFD069CC 0C001040 ADDI V0, ZERO, 3072
-BFD069CE 0C00 NOP
-BFD069D0 001040E2 BEQZC V0, 0xBFD069F4
+BFD069CA 104077E8 JALS xTaskIncrementTick\r
+BFD069CC 0C001040 ADDI V0, ZERO, 3072\r
+BFD069CE 0C00 NOP\r
+BFD069D0 001040E2 BEQZC V0, 0xBFD069F4\r
367: {\r
368: /* Pend a context switch. */\r
369: ulCause = ulPortGetCP0Cause();\r
-BFD069D4 4DC677E8 JALS ulPortGetCP0Cause
-BFD069D6 4DC6 ADDIU T6, T6, 3
-BFD069D8 0C00 NOP
-BFD069DA 0014F85E SW V0, 20(S8)
+BFD069D4 4DC677E8 JALS ulPortGetCP0Cause\r
+BFD069D6 4DC6 ADDIU T6, T6, 3\r
+BFD069D8 0C00 NOP\r
+BFD069DA 0014F85E SW V0, 20(S8)\r
370: ulCause |= ( 1ul << 8UL );\r
-BFD069DE 0014FC5E LW V0, 20(S8)
-BFD069E2 01005042 ORI V0, V0, 256
-BFD069E6 0014F85E SW V0, 20(S8)
+BFD069DE 0014FC5E LW V0, 20(S8)\r
+BFD069E2 01005042 ORI V0, V0, 256\r
+BFD069E6 0014F85E SW V0, 20(S8)\r
371: vPortSetCP0Cause( ulCause );\r
-BFD069EA 0014FC9E LW A0, 20(S8)
-BFD069EE 4DD677E8 JALS vPortSetCP0Cause
-BFD069F0 4DD6 ADDIU T6, T6, -5
-BFD069F2 0C00 NOP
+BFD069EA 0014FC9E LW A0, 20(S8)\r
+BFD069EE 4DD677E8 JALS vPortSetCP0Cause\r
+BFD069F0 4DD6 ADDIU T6, T6, -5\r
+BFD069F2 0C00 NOP\r
372: }\r
373: }\r
374: vPortClearInterruptMaskFromISR( uxSavedStatus );\r
-BFD069F4 0010FC9E LW A0, 16(S8)
-BFD069F8 4D5E77E8 JALS vPortClearInterruptMaskFromISR
-BFD069FA 4D5E ADDIU T2, T2, -1
-BFD069FC 0C00 NOP
+BFD069F4 0010FC9E LW A0, 16(S8)\r
+BFD069F8 4D5E77E8 JALS vPortClearInterruptMaskFromISR\r
+BFD069FA 4D5E ADDIU T2, T2, -1\r
+BFD069FC 0C00 NOP\r
375: \r
376: /* Look for the ISR stack getting near or past its limit. */\r
377: portCHECK_ISR_STACK();\r
-BFD069FE BFD241A2 LUI V0, 0xBFD2
-BFD06A00 3082BFD2 LDC1 F30, 12418(S2)
-BFD06A02 AD683082 ADDIU A0, V0, -21144
-BFD06A04 AD68 BNEZ V0, 0xBFD06AD6
-BFD06A06 BFD141A2 LUI V0, 0xBFD1
-BFD06A08 30A2BFD1 LDC1 F30, 12450(S1)
-BFD06A0A 8A9430A2 ADDIU A1, V0, -30060
-BFD06A0C 8A94 SB A1, 4(S1)
-BFD06A0E EF14 LI A2, 20
-BFD06A10 3DA677E8 JALS 0xBFD07B4C
-BFD06A12 0C003DA6 LH T5, 3072(A2)
-BFD06A14 0C00 NOP
-BFD06A16 000940E2 BEQZC V0, 0xBFD06A2C
-BFD06A1A BFD141A2 LUI V0, 0xBFD1
-BFD06A1C 3082BFD1 LDC1 F30, 12418(S1)
-BFD06A1E 8AAC3082 ADDIU A0, V0, -30036
-BFD06A20 8AAC SB A1, 12(V0)
-BFD06A22 017930A0 ADDIU A1, ZERO, 377
-BFD06A26 4B7E77E8 JALS vAssertCalled
-BFD06A28 4B7E LW K1, 120(SP)
-BFD06A2A 0C00 NOP
+BFD069FE BFD241A2 LUI V0, 0xBFD2\r
+BFD06A00 3082BFD2 LDC1 F30, 12418(S2)\r
+BFD06A02 AD683082 ADDIU A0, V0, -21144\r
+BFD06A04 AD68 BNEZ V0, 0xBFD06AD6\r
+BFD06A06 BFD141A2 LUI V0, 0xBFD1\r
+BFD06A08 30A2BFD1 LDC1 F30, 12450(S1)\r
+BFD06A0A 8A9430A2 ADDIU A1, V0, -30060\r
+BFD06A0C 8A94 SB A1, 4(S1)\r
+BFD06A0E EF14 LI A2, 20\r
+BFD06A10 3DA677E8 JALS 0xBFD07B4C\r
+BFD06A12 0C003DA6 LH T5, 3072(A2)\r
+BFD06A14 0C00 NOP\r
+BFD06A16 000940E2 BEQZC V0, 0xBFD06A2C\r
+BFD06A1A BFD141A2 LUI V0, 0xBFD1\r
+BFD06A1C 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD06A1E 8AAC3082 ADDIU A0, V0, -30036\r
+BFD06A20 8AAC SB A1, 12(V0)\r
+BFD06A22 017930A0 ADDIU A1, ZERO, 377\r
+BFD06A26 4B7E77E8 JALS vAssertCalled\r
+BFD06A28 4B7E LW K1, 120(SP)\r
+BFD06A2A 0C00 NOP\r
378: \r
379: /* Clear timer interrupt. */\r
380: configCLEAR_TICK_TIMER_INTERRUPT();\r
-BFD06A2C BFFF41A2 LUI V0, 0xBFFF
-BFD06A2E 5042BFFF LDC1 F31, 20546(RA)
-BFD06A30 C0F05042 ORI V0, V0, -16144
-BFD06A34 ED90 LI V1, 16
-BFD06A36 E9A0 SW V1, 0(V0)
+BFD06A2C BFFF41A2 LUI V0, 0xBFFF\r
+BFD06A2E 5042BFFF LDC1 F31, 20546(RA)\r
+BFD06A30 C0F05042 ORI V0, V0, -16144\r
+BFD06A34 ED90 LI V1, 16\r
+BFD06A36 E9A0 SW V1, 0(V0)\r
381: }\r
-BFD06A38 0FBE MOVE SP, S8
-BFD06A3A 4BE7 LW RA, 28(SP)
-BFD06A3C 4BC6 LW S8, 24(SP)
-BFD06A3E 4C11 ADDIU SP, SP, 32
-BFD06A40 459F JR16 RA
-BFD06A42 0C00 NOP
+BFD06A38 0FBE MOVE SP, S8\r
+BFD06A3A 4BE7 LW RA, 28(SP)\r
+BFD06A3C 4BC6 LW S8, 24(SP)\r
+BFD06A3E 4C11 ADDIU SP, SP, 32\r
+BFD06A40 459F JR16 RA\r
+BFD06A42 0C00 NOP\r
382: /*-----------------------------------------------------------*/\r
383: \r
384: UBaseType_t uxPortSetInterruptMaskFromISR( void )\r
385: {\r
-BFD08EBC 4FF1 ADDIU SP, SP, -32
-BFD08EBE CBE7 SW RA, 28(SP)
-BFD08EC0 CBC6 SW S8, 24(SP)
-BFD08EC2 0FDD MOVE S8, SP
+BFD08EBC 4FF1 ADDIU SP, SP, -32\r
+BFD08EBE CBE7 SW RA, 28(SP)\r
+BFD08EC0 CBC6 SW S8, 24(SP)\r
+BFD08EC2 0FDD MOVE S8, SP\r
386: UBaseType_t uxSavedStatusRegister;\r
387: \r
388: prvDisableInterrupt();\r
-BFD08EC4 4D4C77E8 JALS prvDisableInterrupt
-BFD08EC6 4D4C ADDIU T2, T2, 6
-BFD08EC8 0C00 NOP
+BFD08EC4 4D4C77E8 JALS prvDisableInterrupt\r
+BFD08EC6 4D4C ADDIU T2, T2, 6\r
+BFD08EC8 0C00 NOP\r
389: uxSavedStatusRegister = ulPortGetCP0Status() | 0x01;\r
-BFD08ECA 4DA677E8 JALS ulPortGetCP0Status
-BFD08ECC 4DA6 ADDIU T5, T5, 3
-BFD08ECE 0C00 NOP
-BFD08ED0 00015042 ORI V0, V0, 1
-BFD08ED4 0010F85E SW V0, 16(S8)
+BFD08ECA 4DA677E8 JALS ulPortGetCP0Status\r
+BFD08ECC 4DA6 ADDIU T5, T5, 3\r
+BFD08ECE 0C00 NOP\r
+BFD08ED0 00015042 ORI V0, V0, 1\r
+BFD08ED4 0010F85E SW V0, 16(S8)\r
390: \r
391: /* This clears the IPL bits, then sets them to\r
392: configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called\r
395: can only result in the IPL being unchanged or raised, and therefore never\r
396: lowered. */\r
397: vPortSetCP0Status( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );\r
-BFD08ED8 0010FC7E LW V1, 16(S8)
-BFD08EDC FFFE41A2 LUI V0, 0xFFFE
-BFD08EDE 5042FFFE LW RA, 20546(S8)
-BFD08EE0 03FF5042 ORI V0, V0, 1023
-BFD08EE4 4493 AND16 V0, V1
-BFD08EE6 0C005042 ORI V0, V0, 3072
-BFD08EE8 0C00 NOP
-BFD08EEA 0C82 MOVE A0, V0
-BFD08EEC 4DB677E8 JALS vPortSetCP0Status
-BFD08EEE 4DB6 ADDIU T5, T5, -5
-BFD08EF0 0C00 NOP
+BFD08ED8 0010FC7E LW V1, 16(S8)\r
+BFD08EDC FFFE41A2 LUI V0, 0xFFFE\r
+BFD08EDE 5042FFFE LW RA, 20546(S8)\r
+BFD08EE0 03FF5042 ORI V0, V0, 1023\r
+BFD08EE4 4493 AND16 V0, V1\r
+BFD08EE6 0C005042 ORI V0, V0, 3072\r
+BFD08EE8 0C00 NOP\r
+BFD08EEA 0C82 MOVE A0, V0\r
+BFD08EEC 4DB677E8 JALS vPortSetCP0Status\r
+BFD08EEE 4DB6 ADDIU T5, T5, -5\r
+BFD08EF0 0C00 NOP\r
398: \r
399: return uxSavedStatusRegister;\r
-BFD08EF2 0010FC5E LW V0, 16(S8)
+BFD08EF2 0010FC5E LW V0, 16(S8)\r
400: }\r
-BFD08EF6 0FBE MOVE SP, S8
-BFD08EF8 4BE7 LW RA, 28(SP)
-BFD08EFA 4BC6 LW S8, 24(SP)
-BFD08EFC 4C11 ADDIU SP, SP, 32
-BFD08EFE 459F JR16 RA
-BFD08F00 0C00 NOP
+BFD08EF6 0FBE MOVE SP, S8\r
+BFD08EF8 4BE7 LW RA, 28(SP)\r
+BFD08EFA 4BC6 LW S8, 24(SP)\r
+BFD08EFC 4C11 ADDIU SP, SP, 32\r
+BFD08EFE 459F JR16 RA\r
+BFD08F00 0C00 NOP\r
401: /*-----------------------------------------------------------*/\r
402: \r
403: void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister )\r
404: {\r
-BFD09ABC 4FF5 ADDIU SP, SP, -24
-BFD09ABE CBE5 SW RA, 20(SP)
-BFD09AC0 CBC4 SW S8, 16(SP)
-BFD09AC2 0FDD MOVE S8, SP
-BFD09AC4 0018F89E SW A0, 24(S8)
+BFD09ABC 4FF5 ADDIU SP, SP, -24\r
+BFD09ABE CBE5 SW RA, 20(SP)\r
+BFD09AC0 CBC4 SW S8, 16(SP)\r
+BFD09AC2 0FDD MOVE S8, SP\r
+BFD09AC4 0018F89E SW A0, 24(S8)\r
405: vPortSetCP0Status( uxSavedStatusRegister );\r
-BFD09AC8 0018FC9E LW A0, 24(S8)
-BFD09ACC 4DB677E8 JALS vPortSetCP0Status
-BFD09ACE 4DB6 ADDIU T5, T5, -5
-BFD09AD0 0C00 NOP
+BFD09AC8 0018FC9E LW A0, 24(S8)\r
+BFD09ACC 4DB677E8 JALS vPortSetCP0Status\r
+BFD09ACE 4DB6 ADDIU T5, T5, -5\r
+BFD09AD0 0C00 NOP\r
406: }\r
-BFD09AD2 0FBE MOVE SP, S8
-BFD09AD4 4BE5 LW RA, 20(SP)
-BFD09AD6 4BC4 LW S8, 16(SP)
-BFD09AD8 4C0D ADDIU SP, SP, 24
-BFD09ADA 459F JR16 RA
-BFD09ADC 0C00 NOP
+BFD09AD2 0FBE MOVE SP, S8\r
+BFD09AD4 4BE5 LW RA, 20(SP)\r
+BFD09AD6 4BC4 LW S8, 16(SP)\r
+BFD09AD8 4C0D ADDIU SP, SP, 24\r
+BFD09ADA 459F JR16 RA\r
+BFD09ADC 0C00 NOP\r
407: /*-----------------------------------------------------------*/\r
408: \r
409: \r
410: \r
411: \r
412: \r
---- c:/e/dev/freertos/workingcopy/freertos/source/portable/memmang/heap_2.c ---------------------------
+--- c:/e/dev/freertos/workingcopy/freertos/source/portable/memmang/heap_2.c ---------------------------\r
1: /*\r
2: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
3: All rights reserved\r
8: \r
9: FreeRTOS is free software; you can redistribute it and/or modify it under\r
10: the terms of the GNU General Public License (version 2) as published by the\r
-11: Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+11: Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
12: \r
13: ***************************************************************************\r
14: >>! NOTE: The modification to the GPL is included to allow you to !<<\r
148: \r
149: void *pvPortMalloc( size_t xWantedSize )\r
150: {\r
-BFD0222C 4FE9 ADDIU SP, SP, -48
-BFD0222E CBEB SW RA, 44(SP)
-BFD02230 CBCA SW S8, 40(SP)
-BFD02232 0FDD MOVE S8, SP
-BFD02234 0030F89E SW A0, 48(S8)
+BFD0222C 4FE9 ADDIU SP, SP, -48\r
+BFD0222E CBEB SW RA, 44(SP)\r
+BFD02230 CBCA SW S8, 40(SP)\r
+BFD02232 0FDD MOVE S8, SP\r
+BFD02234 0030F89E SW A0, 48(S8)\r
151: BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;\r
152: static BaseType_t xHeapHasBeenInitialised = pdFALSE;\r
153: void *pvReturn = NULL;\r
-BFD02238 0018F81E SW ZERO, 24(S8)
+BFD02238 0018F81E SW ZERO, 24(S8)\r
154: \r
155: vTaskSuspendAll();\r
-BFD0223C 4EF477E8 JALS vTaskSuspendAll
-BFD0223E 4EF4 ADDIU S7, S7, -6
-BFD02240 0C00 NOP
+BFD0223C 4EF477E8 JALS vTaskSuspendAll\r
+BFD0223E 4EF4 ADDIU S7, S7, -6\r
+BFD02240 0C00 NOP\r
156: {\r
157: /* If this is the first call to malloc then the heap will require\r
158: initialisation to setup the list of free blocks. */\r
159: if( xHeapHasBeenInitialised == pdFALSE )\r
-BFD02242 8028FC5C LW V0, -32728(GP)
-BFD02246 000640A2 BNEZC V0, 0xBFD02256
+BFD02242 8028FC5C LW V0, -32728(GP)\r
+BFD02246 000640A2 BNEZC V0, 0xBFD02256\r
160: {\r
161: prvHeapInit();\r
-BFD0224A 425077E8 JALS prvHeapInit
-BFD0224E 0C00 NOP
+BFD0224A 425077E8 JALS prvHeapInit\r
+BFD0224E 0C00 NOP\r
162: xHeapHasBeenInitialised = pdTRUE;\r
-BFD02250 ED01 LI V0, 1
-BFD02252 8028F85C SW V0, -32728(GP)
+BFD02250 ED01 LI V0, 1\r
+BFD02252 8028F85C SW V0, -32728(GP)\r
163: }\r
164: \r
165: /* The wanted size is increased so it can contain a BlockLink_t\r
166: structure in addition to the requested amount of bytes. */\r
167: if( xWantedSize > 0 )\r
-BFD02256 0030FC5E LW V0, 48(S8)
-BFD0225A 001640E2 BEQZC V0, 0xBFD0228A
+BFD02256 0030FC5E LW V0, 48(S8)\r
+BFD0225A 001640E2 BEQZC V0, 0xBFD0228A\r
168: {\r
169: xWantedSize += heapSTRUCT_SIZE;\r
-BFD0225E BFD141A2 LUI V0, 0xBFD1
-BFD02260 3442BFD1 LDC1 F30, 13378(S1)
-BFD02262 9F2C3442 LHU V0, -24788(V0)
-BFD02264 FC7E9F2C LWC1 F25, -898(T4)
-BFD02266 0030FC7E LW V1, 48(S8)
-BFD0226A 0526 ADDU V0, V1, V0
-BFD0226C 0030F85E SW V0, 48(S8)
+BFD0225E BFD141A2 LUI V0, 0xBFD1\r
+BFD02260 3442BFD1 LDC1 F30, 13378(S1)\r
+BFD02262 9F2C3442 LHU V0, -24788(V0)\r
+BFD02264 FC7E9F2C LWC1 F25, -898(T4)\r
+BFD02266 0030FC7E LW V1, 48(S8)\r
+BFD0226A 0526 ADDU V0, V1, V0\r
+BFD0226C 0030F85E SW V0, 48(S8)\r
170: \r
171: /* Ensure that blocks are always aligned to the required number of bytes. */\r
172: if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0 )\r
-BFD02270 0030FC5E LW V0, 48(S8)
-BFD02274 2D25 ANDI V0, V0, 0x7
-BFD02276 000840E2 BEQZC V0, 0xBFD0228A
+BFD02270 0030FC5E LW V0, 48(S8)\r
+BFD02274 2D25 ANDI V0, V0, 0x7\r
+BFD02276 000840E2 BEQZC V0, 0xBFD0228A\r
173: {\r
174: /* Byte alignment required. */\r
175: xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );\r
-BFD0227A 0030FC7E LW V1, 48(S8)
-BFD0227C 30400030 SRL AT, S0, 6
-BFD0227E FFF83040 ADDIU V0, ZERO, -8
-BFD02280 4493FFF8 LW RA, 17555(T8)
-BFD02282 4493 AND16 V0, V1
-BFD02284 6D24 ADDIU V0, V0, 8
-BFD02286 0030F85E SW V0, 48(S8)
+BFD0227A 0030FC7E LW V1, 48(S8)\r
+BFD0227C 30400030 SRL AT, S0, 6\r
+BFD0227E FFF83040 ADDIU V0, ZERO, -8\r
+BFD02280 4493FFF8 LW RA, 17555(T8)\r
+BFD02282 4493 AND16 V0, V1\r
+BFD02284 6D24 ADDIU V0, V0, 8\r
+BFD02286 0030F85E SW V0, 48(S8)\r
176: }\r
177: }\r
178: \r
179: if( ( xWantedSize > 0 ) && ( xWantedSize < configADJUSTED_HEAP_SIZE ) )\r
-BFD0228A 0030FC5E LW V0, 48(S8)
-BFD0228E 008F40E2 BEQZC V0, 0xBFD023B0
-BFD02292 0030FC5E LW V0, 48(S8)
-BFD02296 1FF8B042 SLTIU V0, V0, 8184
-BFD02298 40E21FF8 LB RA, 16610(T8)
-BFD0229A 008940E2 BEQZC V0, 0xBFD023B0
+BFD0228A 0030FC5E LW V0, 48(S8)\r
+BFD0228E 008F40E2 BEQZC V0, 0xBFD023B0\r
+BFD02292 0030FC5E LW V0, 48(S8)\r
+BFD02296 1FF8B042 SLTIU V0, V0, 8184\r
+BFD02298 40E21FF8 LB RA, 16610(T8)\r
+BFD0229A 008940E2 BEQZC V0, 0xBFD023B0\r
180: {\r
181: /* Blocks are stored in byte order - traverse the list from the start\r
182: (smallest) block until one of adequate size is found. */\r
183: pxPreviousBlock = &xStart;\r
-BFD0229E 8018305C ADDIU V0, GP, -32744
-BFD022A2 0014F85E SW V0, 20(S8)
+BFD0229E 8018305C ADDIU V0, GP, -32744\r
+BFD022A2 0014F85E SW V0, 20(S8)\r
184: pxBlock = xStart.pxNextFreeBlock;\r
-BFD022A6 8018FC5C LW V0, -32744(GP)
-BFD022AA 0010F85E SW V0, 16(S8)
+BFD022A6 8018FC5C LW V0, -32744(GP)\r
+BFD022AA 0010F85E SW V0, 16(S8)\r
185: while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\r
-BFD022AE CC0A B 0xBFD022C4
-BFD022B0 0C00 NOP
-BFD022C4 0010FC5E LW V0, 16(S8)
-BFD022C8 69A1 LW V1, 4(V0)
-BFD022CA 0030FC5E LW V0, 48(S8)
-BFD022CE 13900043 SLTU V0, V1, V0
-BFD022D0 40E21390 ADDI GP, S0, 16610
-BFD022D2 000540E2 BEQZC V0, 0xBFD022E0
-BFD022D6 0010FC5E LW V0, 16(S8)
-BFD022DA 6920 LW V0, 0(V0)
-BFD022DC FFE940A2 BNEZC V0, 0xBFD022B2
-BFD022DE FC7EFFE9 LW RA, -898(T1)
+BFD022AE CC0A B 0xBFD022C4\r
+BFD022B0 0C00 NOP\r
+BFD022C4 0010FC5E LW V0, 16(S8)\r
+BFD022C8 69A1 LW V1, 4(V0)\r
+BFD022CA 0030FC5E LW V0, 48(S8)\r
+BFD022CE 13900043 SLTU V0, V1, V0\r
+BFD022D0 40E21390 ADDI GP, S0, 16610\r
+BFD022D2 000540E2 BEQZC V0, 0xBFD022E0\r
+BFD022D6 0010FC5E LW V0, 16(S8)\r
+BFD022DA 6920 LW V0, 0(V0)\r
+BFD022DC FFE940A2 BNEZC V0, 0xBFD022B2\r
+BFD022DE FC7EFFE9 LW RA, -898(T1)\r
186: {\r
187: pxPreviousBlock = pxBlock;\r
-BFD022B2 0010FC5E LW V0, 16(S8)
-BFD022B6 0014F85E SW V0, 20(S8)
+BFD022B2 0010FC5E LW V0, 16(S8)\r
+BFD022B6 0014F85E SW V0, 20(S8)\r
188: pxBlock = pxBlock->pxNextFreeBlock;\r
-BFD022BA 0010FC5E LW V0, 16(S8)
-BFD022BE 6920 LW V0, 0(V0)
-BFD022C0 0010F85E SW V0, 16(S8)
+BFD022BA 0010FC5E LW V0, 16(S8)\r
+BFD022BE 6920 LW V0, 0(V0)\r
+BFD022C0 0010F85E SW V0, 16(S8)\r
189: }\r
190: \r
191: /* If we found the end marker then a block of adequate size was not found. */\r
192: if( pxBlock != &xEnd )\r
-BFD022E0 0010FC7E LW V1, 16(S8)
-BFD022E4 8020305C ADDIU V0, GP, -32736
-BFD022E8 00629443 BEQ V1, V0, 0xBFD023B0
-BFD022EA 0C000062 SLL V1, V0, 1
-BFD022EC 0C00 NOP
+BFD022E0 0010FC7E LW V1, 16(S8)\r
+BFD022E4 8020305C ADDIU V0, GP, -32736\r
+BFD022E8 00629443 BEQ V1, V0, 0xBFD023B0\r
+BFD022EA 0C000062 SLL V1, V0, 1\r
+BFD022EC 0C00 NOP\r
193: {\r
194: /* Return the memory space - jumping over the BlockLink_t structure\r
195: at its start. */\r
196: pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE );\r
-BFD022EE 0014FC5E LW V0, 20(S8)
-BFD022F2 69A0 LW V1, 0(V0)
-BFD022F4 BFD141A2 LUI V0, 0xBFD1
-BFD022F6 3442BFD1 LDC1 F30, 13378(S1)
-BFD022F8 9F2C3442 LHU V0, -24788(V0)
-BFD022FA 05269F2C LWC1 F25, 1318(T4)
-BFD022FC 0526 ADDU V0, V1, V0
-BFD022FE 0018F85E SW V0, 24(S8)
+BFD022EE 0014FC5E LW V0, 20(S8)\r
+BFD022F2 69A0 LW V1, 0(V0)\r
+BFD022F4 BFD141A2 LUI V0, 0xBFD1\r
+BFD022F6 3442BFD1 LDC1 F30, 13378(S1)\r
+BFD022F8 9F2C3442 LHU V0, -24788(V0)\r
+BFD022FA 05269F2C LWC1 F25, 1318(T4)\r
+BFD022FC 0526 ADDU V0, V1, V0\r
+BFD022FE 0018F85E SW V0, 24(S8)\r
197: \r
198: /* This block is being returned for use so must be taken out of the\r
199: list of free blocks. */\r
200: pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\r
-BFD02302 0010FC5E LW V0, 16(S8)
-BFD02306 69A0 LW V1, 0(V0)
-BFD02308 0014FC5E LW V0, 20(S8)
-BFD0230C E9A0 SW V1, 0(V0)
+BFD02302 0010FC5E LW V0, 16(S8)\r
+BFD02306 69A0 LW V1, 0(V0)\r
+BFD02308 0014FC5E LW V0, 20(S8)\r
+BFD0230C E9A0 SW V1, 0(V0)\r
201: \r
202: /* If the block is larger than required it can be split into two. */\r
203: if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )\r
-BFD0230E 0010FC5E LW V0, 16(S8)
-BFD02312 69A1 LW V1, 4(V0)
-BFD02314 0030FC5E LW V0, 48(S8)
-BFD02318 05A7 SUBU V1, V1, V0
-BFD0231A BFD141A2 LUI V0, 0xBFD1
-BFD0231C 3442BFD1 LDC1 F30, 13378(S1)
-BFD0231E 9F2C3442 LHU V0, -24788(V0)
-BFD02320 25229F2C LWC1 F25, 9506(T4)
-BFD02322 2522 SLL V0, V0, 1
-BFD02324 13900062 SLTU V0, V0, V1
-BFD02326 40E21390 ADDI GP, S0, 16610
-BFD02328 003A40E2 BEQZC V0, 0xBFD023A0
+BFD0230E 0010FC5E LW V0, 16(S8)\r
+BFD02312 69A1 LW V1, 4(V0)\r
+BFD02314 0030FC5E LW V0, 48(S8)\r
+BFD02318 05A7 SUBU V1, V1, V0\r
+BFD0231A BFD141A2 LUI V0, 0xBFD1\r
+BFD0231C 3442BFD1 LDC1 F30, 13378(S1)\r
+BFD0231E 9F2C3442 LHU V0, -24788(V0)\r
+BFD02320 25229F2C LWC1 F25, 9506(T4)\r
+BFD02322 2522 SLL V0, V0, 1\r
+BFD02324 13900062 SLTU V0, V0, V1\r
+BFD02326 40E21390 ADDI GP, S0, 16610\r
+BFD02328 003A40E2 BEQZC V0, 0xBFD023A0\r
204: {\r
205: /* This block is to be split into two. Create a new block\r
206: following the number of bytes requested. The void cast is\r
207: used to prevent byte alignment warnings from the compiler. */\r
208: pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\r
-BFD0232C 0010FC7E LW V1, 16(S8)
-BFD02330 0030FC5E LW V0, 48(S8)
-BFD02334 0526 ADDU V0, V1, V0
-BFD02336 0020F85E SW V0, 32(S8)
+BFD0232C 0010FC7E LW V1, 16(S8)\r
+BFD02330 0030FC5E LW V0, 48(S8)\r
+BFD02334 0526 ADDU V0, V1, V0\r
+BFD02336 0020F85E SW V0, 32(S8)\r
209: \r
210: /* Calculate the sizes of two blocks split from the single\r
211: block. */\r
212: pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\r
-BFD0233A 0010FC5E LW V0, 16(S8)
-BFD0233E 69A1 LW V1, 4(V0)
-BFD02340 0030FC5E LW V0, 48(S8)
-BFD02344 05A7 SUBU V1, V1, V0
-BFD02346 0020FC5E LW V0, 32(S8)
-BFD0234A E9A1 SW V1, 4(V0)
+BFD0233A 0010FC5E LW V0, 16(S8)\r
+BFD0233E 69A1 LW V1, 4(V0)\r
+BFD02340 0030FC5E LW V0, 48(S8)\r
+BFD02344 05A7 SUBU V1, V1, V0\r
+BFD02346 0020FC5E LW V0, 32(S8)\r
+BFD0234A E9A1 SW V1, 4(V0)\r
213: pxBlock->xBlockSize = xWantedSize;\r
-BFD0234C 0010FC5E LW V0, 16(S8)
-BFD02350 0030FC7E LW V1, 48(S8)
-BFD02354 E9A1 SW V1, 4(V0)
+BFD0234C 0010FC5E LW V0, 16(S8)\r
+BFD02350 0030FC7E LW V1, 48(S8)\r
+BFD02354 E9A1 SW V1, 4(V0)\r
214: \r
215: /* Insert the new block into the list of free blocks. */\r
216: prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );\r
-BFD02356 0020FC5E LW V0, 32(S8)
-BFD0235A 6921 LW V0, 4(V0)
-BFD0235C 0024F85E SW V0, 36(S8)
-BFD02360 8018305C ADDIU V0, GP, -32744
-BFD02364 001CF85E SW V0, 28(S8)
-BFD02368 CC06 B 0xBFD02376
-BFD0236A 0C00 NOP
-BFD0236C 001CFC5E LW V0, 28(S8)
-BFD02370 6920 LW V0, 0(V0)
-BFD02372 001CF85E SW V0, 28(S8)
-BFD02376 001CFC5E LW V0, 28(S8)
-BFD0237A 6920 LW V0, 0(V0)
-BFD0237C 69A1 LW V1, 4(V0)
-BFD0237E 0024FC5E LW V0, 36(S8)
-BFD02382 13900043 SLTU V0, V1, V0
-BFD02384 40A21390 ADDI GP, S0, 16546
-BFD02386 FFF140A2 BNEZC V0, 0xBFD0236C
-BFD02388 FC5EFFF1 LW RA, -930(S1)
-BFD0238A 001CFC5E LW V0, 28(S8)
-BFD0238E 69A0 LW V1, 0(V0)
-BFD02390 0020FC5E LW V0, 32(S8)
-BFD02394 E9A0 SW V1, 0(V0)
-BFD02396 001CFC5E LW V0, 28(S8)
-BFD0239A 0020FC7E LW V1, 32(S8)
-BFD0239E E9A0 SW V1, 0(V0)
+BFD02356 0020FC5E LW V0, 32(S8)\r
+BFD0235A 6921 LW V0, 4(V0)\r
+BFD0235C 0024F85E SW V0, 36(S8)\r
+BFD02360 8018305C ADDIU V0, GP, -32744\r
+BFD02364 001CF85E SW V0, 28(S8)\r
+BFD02368 CC06 B 0xBFD02376\r
+BFD0236A 0C00 NOP\r
+BFD0236C 001CFC5E LW V0, 28(S8)\r
+BFD02370 6920 LW V0, 0(V0)\r
+BFD02372 001CF85E SW V0, 28(S8)\r
+BFD02376 001CFC5E LW V0, 28(S8)\r
+BFD0237A 6920 LW V0, 0(V0)\r
+BFD0237C 69A1 LW V1, 4(V0)\r
+BFD0237E 0024FC5E LW V0, 36(S8)\r
+BFD02382 13900043 SLTU V0, V1, V0\r
+BFD02384 40A21390 ADDI GP, S0, 16546\r
+BFD02386 FFF140A2 BNEZC V0, 0xBFD0236C\r
+BFD02388 FC5EFFF1 LW RA, -930(S1)\r
+BFD0238A 001CFC5E LW V0, 28(S8)\r
+BFD0238E 69A0 LW V1, 0(V0)\r
+BFD02390 0020FC5E LW V0, 32(S8)\r
+BFD02394 E9A0 SW V1, 0(V0)\r
+BFD02396 001CFC5E LW V0, 28(S8)\r
+BFD0239A 0020FC7E LW V1, 32(S8)\r
+BFD0239E E9A0 SW V1, 0(V0)\r
217: }\r
218: \r
219: xFreeBytesRemaining -= pxBlock->xBlockSize;\r
-BFD023A0 8010FC7C LW V1, -32752(GP)
-BFD023A4 0010FC5E LW V0, 16(S8)
-BFD023A8 6921 LW V0, 4(V0)
-BFD023AA 0527 SUBU V0, V1, V0
-BFD023AC 8010F85C SW V0, -32752(GP)
+BFD023A0 8010FC7C LW V1, -32752(GP)\r
+BFD023A4 0010FC5E LW V0, 16(S8)\r
+BFD023A8 6921 LW V0, 4(V0)\r
+BFD023AA 0527 SUBU V0, V1, V0\r
+BFD023AC 8010F85C SW V0, -32752(GP)\r
220: }\r
221: }\r
222: \r
223: traceMALLOC( pvReturn, xWantedSize );\r
224: }\r
225: ( void ) xTaskResumeAll();\r
-BFD023B0 158E77E8 JALS xTaskResumeAll
-BFD023B2 0C00158E LBU T4, 3072(T6)
-BFD023B4 0C00 NOP
+BFD023B0 158E77E8 JALS xTaskResumeAll\r
+BFD023B2 0C00158E LBU T4, 3072(T6)\r
+BFD023B4 0C00 NOP\r
226: \r
227: #if( configUSE_MALLOC_FAILED_HOOK == 1 )\r
228: {\r
229: if( pvReturn == NULL )\r
-BFD023B6 0018FC5E LW V0, 24(S8)
-BFD023BA 000340A2 BNEZC V0, 0xBFD023C4
+BFD023B6 0018FC5E LW V0, 24(S8)\r
+BFD023BA 000340A2 BNEZC V0, 0xBFD023C4\r
230: {\r
231: extern void vApplicationMallocFailedHook( void );\r
232: vApplicationMallocFailedHook();\r
-BFD023BE 448077E8 JALS vApplicationMallocFailedHook
-BFD023C0 4480 AND16 S0, S0
-BFD023C2 0C00 NOP
+BFD023BE 448077E8 JALS vApplicationMallocFailedHook\r
+BFD023C0 4480 AND16 S0, S0\r
+BFD023C2 0C00 NOP\r
233: }\r
234: }\r
235: #endif\r
236: \r
237: return pvReturn;\r
-BFD023C4 0018FC5E LW V0, 24(S8)
+BFD023C4 0018FC5E LW V0, 24(S8)\r
238: }\r
-BFD023C8 0FBE MOVE SP, S8
-BFD023CA 4BEB LW RA, 44(SP)
-BFD023CC 4BCA LW S8, 40(SP)
-BFD023CE 4C19 ADDIU SP, SP, 48
-BFD023D0 459F JR16 RA
-BFD023D2 0C00 NOP
+BFD023C8 0FBE MOVE SP, S8\r
+BFD023CA 4BEB LW RA, 44(SP)\r
+BFD023CC 4BCA LW S8, 40(SP)\r
+BFD023CE 4C19 ADDIU SP, SP, 48\r
+BFD023D0 459F JR16 RA\r
+BFD023D2 0C00 NOP\r
239: /*-----------------------------------------------------------*/\r
240: \r
241: void vPortFree( void *pv )\r
242: {\r
-BFD05FD4 4FED ADDIU SP, SP, -40
-BFD05FD6 CBE9 SW RA, 36(SP)
-BFD05FD8 CBC8 SW S8, 32(SP)
-BFD05FDA 0FDD MOVE S8, SP
-BFD05FDC 0028F89E SW A0, 40(S8)
+BFD05FD4 4FED ADDIU SP, SP, -40\r
+BFD05FD6 CBE9 SW RA, 36(SP)\r
+BFD05FD8 CBC8 SW S8, 32(SP)\r
+BFD05FDA 0FDD MOVE S8, SP\r
+BFD05FDC 0028F89E SW A0, 40(S8)\r
243: uint8_t *puc = ( uint8_t * ) pv;\r
-BFD05FE0 0028FC5E LW V0, 40(S8)
-BFD05FE4 0014F85E SW V0, 20(S8)
+BFD05FE0 0028FC5E LW V0, 40(S8)\r
+BFD05FE4 0014F85E SW V0, 20(S8)\r
244: BlockLink_t *pxLink;\r
245: \r
246: if( pv != NULL )\r
-BFD05FE8 0028FC5E LW V0, 40(S8)
-BFD05FEC 004240E2 BEQZC V0, 0xBFD06074
+BFD05FE8 0028FC5E LW V0, 40(S8)\r
+BFD05FEC 004240E2 BEQZC V0, 0xBFD06074\r
247: {\r
248: /* The memory being freed will have an BlockLink_t structure immediately\r
249: before it. */\r
250: puc -= heapSTRUCT_SIZE;\r
-BFD05FF0 BFD141A2 LUI V0, 0xBFD1
-BFD05FF2 3442BFD1 LDC1 F30, 13378(S1)
-BFD05FF4 9F2C3442 LHU V0, -24788(V0)
-BFD05FF6 00409F2C LWC1 F25, 64(T4)
-BFD05FF8 11D00040 SUBU V0, ZERO, V0
-BFD05FFA FC7E11D0 ADDI T6, S0, -898
-BFD05FFC 0014FC7E LW V1, 20(S8)
-BFD06000 0526 ADDU V0, V1, V0
-BFD06002 0014F85E SW V0, 20(S8)
+BFD05FF0 BFD141A2 LUI V0, 0xBFD1\r
+BFD05FF2 3442BFD1 LDC1 F30, 13378(S1)\r
+BFD05FF4 9F2C3442 LHU V0, -24788(V0)\r
+BFD05FF6 00409F2C LWC1 F25, 64(T4)\r
+BFD05FF8 11D00040 SUBU V0, ZERO, V0\r
+BFD05FFA FC7E11D0 ADDI T6, S0, -898\r
+BFD05FFC 0014FC7E LW V1, 20(S8)\r
+BFD06000 0526 ADDU V0, V1, V0\r
+BFD06002 0014F85E SW V0, 20(S8)\r
251: \r
252: /* This unexpected casting is to keep some compilers from issuing\r
253: byte alignment warnings. */\r
254: pxLink = ( void * ) puc;\r
-BFD06006 0014FC5E LW V0, 20(S8)
-BFD0600A 0018F85E SW V0, 24(S8)
+BFD06006 0014FC5E LW V0, 20(S8)\r
+BFD0600A 0018F85E SW V0, 24(S8)\r
255: \r
256: vTaskSuspendAll();\r
-BFD0600E 4EF477E8 JALS vTaskSuspendAll
-BFD06010 4EF4 ADDIU S7, S7, -6
-BFD06012 0C00 NOP
+BFD0600E 4EF477E8 JALS vTaskSuspendAll\r
+BFD06010 4EF4 ADDIU S7, S7, -6\r
+BFD06012 0C00 NOP\r
257: {\r
258: /* Add this block to the list of free blocks. */\r
259: prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\r
-BFD06014 0018FC5E LW V0, 24(S8)
-BFD06018 6921 LW V0, 4(V0)
-BFD0601A 001CF85E SW V0, 28(S8)
-BFD0601E 8018305C ADDIU V0, GP, -32744
-BFD06022 0010F85E SW V0, 16(S8)
-BFD06026 CC06 B 0xBFD06034
-BFD06028 0C00 NOP
-BFD0602A 0010FC5E LW V0, 16(S8)
-BFD0602E 6920 LW V0, 0(V0)
-BFD06030 0010F85E SW V0, 16(S8)
-BFD06034 0010FC5E LW V0, 16(S8)
-BFD06038 6920 LW V0, 0(V0)
-BFD0603A 69A1 LW V1, 4(V0)
-BFD0603C 001CFC5E LW V0, 28(S8)
-BFD06040 13900043 SLTU V0, V1, V0
-BFD06042 40A21390 ADDI GP, S0, 16546
-BFD06044 FFF140A2 BNEZC V0, 0xBFD0602A
-BFD06046 FC5EFFF1 LW RA, -930(S1)
-BFD06048 0010FC5E LW V0, 16(S8)
-BFD0604C 69A0 LW V1, 0(V0)
-BFD0604E 0018FC5E LW V0, 24(S8)
-BFD06052 E9A0 SW V1, 0(V0)
-BFD06054 0010FC5E LW V0, 16(S8)
-BFD06058 0018FC7E LW V1, 24(S8)
-BFD0605C E9A0 SW V1, 0(V0)
+BFD06014 0018FC5E LW V0, 24(S8)\r
+BFD06018 6921 LW V0, 4(V0)\r
+BFD0601A 001CF85E SW V0, 28(S8)\r
+BFD0601E 8018305C ADDIU V0, GP, -32744\r
+BFD06022 0010F85E SW V0, 16(S8)\r
+BFD06026 CC06 B 0xBFD06034\r
+BFD06028 0C00 NOP\r
+BFD0602A 0010FC5E LW V0, 16(S8)\r
+BFD0602E 6920 LW V0, 0(V0)\r
+BFD06030 0010F85E SW V0, 16(S8)\r
+BFD06034 0010FC5E LW V0, 16(S8)\r
+BFD06038 6920 LW V0, 0(V0)\r
+BFD0603A 69A1 LW V1, 4(V0)\r
+BFD0603C 001CFC5E LW V0, 28(S8)\r
+BFD06040 13900043 SLTU V0, V1, V0\r
+BFD06042 40A21390 ADDI GP, S0, 16546\r
+BFD06044 FFF140A2 BNEZC V0, 0xBFD0602A\r
+BFD06046 FC5EFFF1 LW RA, -930(S1)\r
+BFD06048 0010FC5E LW V0, 16(S8)\r
+BFD0604C 69A0 LW V1, 0(V0)\r
+BFD0604E 0018FC5E LW V0, 24(S8)\r
+BFD06052 E9A0 SW V1, 0(V0)\r
+BFD06054 0010FC5E LW V0, 16(S8)\r
+BFD06058 0018FC7E LW V1, 24(S8)\r
+BFD0605C E9A0 SW V1, 0(V0)\r
260: xFreeBytesRemaining += pxLink->xBlockSize;\r
-BFD0605E 0018FC5E LW V0, 24(S8)
-BFD06062 69A1 LW V1, 4(V0)
-BFD06064 8010FC5C LW V0, -32752(GP)
-BFD06068 0526 ADDU V0, V1, V0
-BFD0606A 8010F85C SW V0, -32752(GP)
+BFD0605E 0018FC5E LW V0, 24(S8)\r
+BFD06062 69A1 LW V1, 4(V0)\r
+BFD06064 8010FC5C LW V0, -32752(GP)\r
+BFD06068 0526 ADDU V0, V1, V0\r
+BFD0606A 8010F85C SW V0, -32752(GP)\r
261: traceFREE( pv, pxLink->xBlockSize );\r
262: }\r
263: ( void ) xTaskResumeAll();\r
-BFD0606E 158E77E8 JALS xTaskResumeAll
-BFD06070 0C00158E LBU T4, 3072(T6)
-BFD06072 0C00 NOP
+BFD0606E 158E77E8 JALS xTaskResumeAll\r
+BFD06070 0C00158E LBU T4, 3072(T6)\r
+BFD06072 0C00 NOP\r
264: }\r
265: }\r
-BFD06074 0FBE MOVE SP, S8
-BFD06076 4BE9 LW RA, 36(SP)
-BFD06078 4BC8 LW S8, 32(SP)
-BFD0607A 4C15 ADDIU SP, SP, 40
-BFD0607C 459F JR16 RA
-BFD0607E 0C00 NOP
+BFD06074 0FBE MOVE SP, S8\r
+BFD06076 4BE9 LW RA, 36(SP)\r
+BFD06078 4BC8 LW S8, 32(SP)\r
+BFD0607A 4C15 ADDIU SP, SP, 40\r
+BFD0607C 459F JR16 RA\r
+BFD0607E 0C00 NOP\r
266: /*-----------------------------------------------------------*/\r
267: \r
268: size_t xPortGetFreeHeapSize( void )\r
269: {\r
-BFD09E84 4FB0 ADDIU SP, SP, -8
-BFD09E86 CBC1 SW S8, 4(SP)
-BFD09E88 0FDD MOVE S8, SP
+BFD09E84 4FB0 ADDIU SP, SP, -8\r
+BFD09E86 CBC1 SW S8, 4(SP)\r
+BFD09E88 0FDD MOVE S8, SP\r
270: return xFreeBytesRemaining;\r
-BFD09E8A 8010FC5C LW V0, -32752(GP)
+BFD09E8A 8010FC5C LW V0, -32752(GP)\r
271: }\r
-BFD09E8E 0FBE MOVE SP, S8
-BFD09E90 4BC1 LW S8, 4(SP)
-BFD09E92 4C05 ADDIU SP, SP, 8
-BFD09E94 459F JR16 RA
-BFD09E96 0C00 NOP
+BFD09E8E 0FBE MOVE SP, S8\r
+BFD09E90 4BC1 LW S8, 4(SP)\r
+BFD09E92 4C05 ADDIU SP, SP, 8\r
+BFD09E94 459F JR16 RA\r
+BFD09E96 0C00 NOP\r
272: /*-----------------------------------------------------------*/\r
273: \r
274: void vPortInitialiseBlocks( void )\r
275: {\r
-BFD09ED4 4FB0 ADDIU SP, SP, -8
-BFD09ED6 CBC1 SW S8, 4(SP)
-BFD09ED8 0FDD MOVE S8, SP
+BFD09ED4 4FB0 ADDIU SP, SP, -8\r
+BFD09ED6 CBC1 SW S8, 4(SP)\r
+BFD09ED8 0FDD MOVE S8, SP\r
276: /* This just exists to keep the linker quiet. */\r
277: }\r
-BFD09EDA 0FBE MOVE SP, S8
-BFD09EDC 4BC1 LW S8, 4(SP)
-BFD09EDE 4C05 ADDIU SP, SP, 8
-BFD09EE0 459F JR16 RA
-BFD09EE2 0C00 NOP
+BFD09EDA 0FBE MOVE SP, S8\r
+BFD09EDC 4BC1 LW S8, 4(SP)\r
+BFD09EDE 4C05 ADDIU SP, SP, 8\r
+BFD09EE0 459F JR16 RA\r
+BFD09EE2 0C00 NOP\r
278: /*-----------------------------------------------------------*/\r
279: \r
280: static void prvHeapInit( void )\r
281: {\r
-BFD084A0 4FF9 ADDIU SP, SP, -16
-BFD084A2 CBC3 SW S8, 12(SP)
-BFD084A4 0FDD MOVE S8, SP
+BFD084A0 4FF9 ADDIU SP, SP, -16\r
+BFD084A2 CBC3 SW S8, 12(SP)\r
+BFD084A4 0FDD MOVE S8, SP\r
282: BlockLink_t *pxFirstFreeBlock;\r
283: uint8_t *pucAlignedHeap;\r
284: \r
285: /* Ensure the heap starts on a correctly aligned boundary. */\r
286: pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) &ucHeap[ portBYTE_ALIGNMENT ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );\r
-BFD084A6 BFD241A2 LUI V0, 0xBFD2
-BFD084A8 3062BFD2 LDC1 F30, 12386(S2)
-BFD084AA 8D703062 ADDIU V1, V0, -29328
-BFD084AC 8D70 BEQZ V0, 0xBFD0858E
-BFD084AE FFF83040 ADDIU V0, ZERO, -8
-BFD084B0 4493FFF8 LW RA, 17555(T8)
-BFD084B2 4493 AND16 V0, V1
-BFD084B4 0000F85E SW V0, 0(S8)
+BFD084A6 BFD241A2 LUI V0, 0xBFD2\r
+BFD084A8 3062BFD2 LDC1 F30, 12386(S2)\r
+BFD084AA 8D703062 ADDIU V1, V0, -29328\r
+BFD084AC 8D70 BEQZ V0, 0xBFD0858E\r
+BFD084AE FFF83040 ADDIU V0, ZERO, -8\r
+BFD084B0 4493FFF8 LW RA, 17555(T8)\r
+BFD084B2 4493 AND16 V0, V1\r
+BFD084B4 0000F85E SW V0, 0(S8)\r
287: \r
288: /* xStart is used to hold a pointer to the first item in the list of free\r
289: blocks. The void cast is used to prevent compiler warnings. */\r
290: xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;\r
-BFD084B8 0000FC5E LW V0, 0(S8)
-BFD084BC 8018F85C SW V0, -32744(GP)
+BFD084B8 0000FC5E LW V0, 0(S8)\r
+BFD084BC 8018F85C SW V0, -32744(GP)\r
291: xStart.xBlockSize = ( size_t ) 0;\r
-BFD084C0 801CF81C SW ZERO, -32740(GP)
+BFD084C0 801CF81C SW ZERO, -32740(GP)\r
292: \r
293: /* xEnd is used to mark the end of the list of free blocks. */\r
294: xEnd.xBlockSize = configADJUSTED_HEAP_SIZE;\r
-BFD084C4 1FF83040 ADDIU V0, ZERO, 8184
-BFD084C6 F85C1FF8 LB RA, -1956(T8)
-BFD084C8 8024F85C SW V0, -32732(GP)
+BFD084C4 1FF83040 ADDIU V0, ZERO, 8184\r
+BFD084C6 F85C1FF8 LB RA, -1956(T8)\r
+BFD084C8 8024F85C SW V0, -32732(GP)\r
295: xEnd.pxNextFreeBlock = NULL;\r
-BFD084CC 8020F81C SW ZERO, -32736(GP)
+BFD084CC 8020F81C SW ZERO, -32736(GP)\r
296: \r
297: /* To start with there is a single free block that is sized to take up the\r
298: entire heap space. */\r
299: pxFirstFreeBlock = ( void * ) pucAlignedHeap;\r
-BFD084D0 0000FC5E LW V0, 0(S8)
-BFD084D4 0004F85E SW V0, 4(S8)
+BFD084D0 0000FC5E LW V0, 0(S8)\r
+BFD084D4 0004F85E SW V0, 4(S8)\r
300: pxFirstFreeBlock->xBlockSize = configADJUSTED_HEAP_SIZE;\r
-BFD084D8 0004FC5E LW V0, 4(S8)
-BFD084DC 1FF83060 ADDIU V1, ZERO, 8184
-BFD084DE E9A11FF8 LB RA, -5727(T8)
-BFD084E0 E9A1 SW V1, 4(V0)
+BFD084D8 0004FC5E LW V0, 4(S8)\r
+BFD084DC 1FF83060 ADDIU V1, ZERO, 8184\r
+BFD084DE E9A11FF8 LB RA, -5727(T8)\r
+BFD084E0 E9A1 SW V1, 4(V0)\r
301: pxFirstFreeBlock->pxNextFreeBlock = &xEnd;\r
-BFD084E2 0004FC5E LW V0, 4(S8)
-BFD084E4 307C0004 MTLO A0, 0
-BFD084E6 8020307C ADDIU V1, GP, -32736
-BFD084EA E9A0 SW V1, 0(V0)
+BFD084E2 0004FC5E LW V0, 4(S8)\r
+BFD084E4 307C0004 MTLO A0, 0\r
+BFD084E6 8020307C ADDIU V1, GP, -32736\r
+BFD084EA E9A0 SW V1, 0(V0)\r
302: }\r
-BFD084EC 0FBE MOVE SP, S8
-BFD084EE 4BC3 LW S8, 12(SP)
-BFD084F0 4C09 ADDIU SP, SP, 16
-BFD084F2 459F JR16 RA
-BFD084F4 0C00 NOP
+BFD084EC 0FBE MOVE SP, S8\r
+BFD084EE 4BC3 LW S8, 12(SP)\r
+BFD084F0 4C09 ADDIU SP, SP, 16\r
+BFD084F2 459F JR16 RA\r
+BFD084F4 0C00 NOP\r
303: /*-----------------------------------------------------------*/\r
---- c:/e/dev/freertos/workingcopy/freertos/source/list.c ----------------------------------------------
+--- c:/e/dev/freertos/workingcopy/freertos/source/list.c ----------------------------------------------\r
1: /*\r
2: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
3: All rights reserved\r
8: \r
9: FreeRTOS is free software; you can redistribute it and/or modify it under\r
10: the terms of the GNU General Public License (version 2) as published by the\r
-11: Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+11: Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
12: \r
13: ***************************************************************************\r
14: >>! NOTE: The modification to the GPL is included to allow you to !<<\r
78: \r
79: void vListInitialise( List_t * const pxList )\r
80: {\r
-BFD08AE0 4FB0 ADDIU SP, SP, -8
-BFD08AE2 CBC1 SW S8, 4(SP)
-BFD08AE4 0FDD MOVE S8, SP
-BFD08AE6 0008F89E SW A0, 8(S8)
+BFD08AE0 4FB0 ADDIU SP, SP, -8\r
+BFD08AE2 CBC1 SW S8, 4(SP)\r
+BFD08AE4 0FDD MOVE S8, SP\r
+BFD08AE6 0008F89E SW A0, 8(S8)\r
81: /* The list structure contains a list item which is used to mark the\r
82: end of the list. To initialise the list the list end is inserted\r
83: as the only list entry. */\r
84: pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */\r
-BFD08AEA 0008FC5E LW V0, 8(S8)
-BFD08AEE 6D24 ADDIU V0, V0, 8
-BFD08AF0 0C62 MOVE V1, V0
-BFD08AF2 0008FC5E LW V0, 8(S8)
-BFD08AF6 E9A1 SW V1, 4(V0)
+BFD08AEA 0008FC5E LW V0, 8(S8)\r
+BFD08AEE 6D24 ADDIU V0, V0, 8\r
+BFD08AF0 0C62 MOVE V1, V0\r
+BFD08AF2 0008FC5E LW V0, 8(S8)\r
+BFD08AF6 E9A1 SW V1, 4(V0)\r
85: \r
86: /* The list end value is the highest possible value in the list to\r
87: ensure it remains at the end of the list. */\r
88: pxList->xListEnd.xItemValue = portMAX_DELAY;\r
-BFD08AF8 0008FC5E LW V0, 8(S8)
-BFD08AFC EDFF LI V1, -1
-BFD08AFE E9A2 SW V1, 8(V0)
+BFD08AF8 0008FC5E LW V0, 8(S8)\r
+BFD08AFC EDFF LI V1, -1\r
+BFD08AFE E9A2 SW V1, 8(V0)\r
89: \r
90: /* The list end next and previous pointers point to itself so we know\r
91: when the list is empty. */\r
92: pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */\r
-BFD08B00 0008FC5E LW V0, 8(S8)
-BFD08B04 6D24 ADDIU V0, V0, 8
-BFD08B06 0C62 MOVE V1, V0
-BFD08B08 0008FC5E LW V0, 8(S8)
-BFD08B0C E9A3 SW V1, 12(V0)
+BFD08B00 0008FC5E LW V0, 8(S8)\r
+BFD08B04 6D24 ADDIU V0, V0, 8\r
+BFD08B06 0C62 MOVE V1, V0\r
+BFD08B08 0008FC5E LW V0, 8(S8)\r
+BFD08B0C E9A3 SW V1, 12(V0)\r
93: pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */\r
-BFD08B0E 0008FC5E LW V0, 8(S8)
-BFD08B12 6D24 ADDIU V0, V0, 8
-BFD08B14 0C62 MOVE V1, V0
-BFD08B16 0008FC5E LW V0, 8(S8)
-BFD08B1A E9A4 SW V1, 16(V0)
+BFD08B0E 0008FC5E LW V0, 8(S8)\r
+BFD08B12 6D24 ADDIU V0, V0, 8\r
+BFD08B14 0C62 MOVE V1, V0\r
+BFD08B16 0008FC5E LW V0, 8(S8)\r
+BFD08B1A E9A4 SW V1, 16(V0)\r
94: \r
95: pxList->uxNumberOfItems = ( UBaseType_t ) 0U;\r
-BFD08B1C 0008FC5E LW V0, 8(S8)
-BFD08B20 E820 SW S0, 0(V0)
+BFD08B1C 0008FC5E LW V0, 8(S8)\r
+BFD08B20 E820 SW S0, 0(V0)\r
96: \r
97: /* Write known values into the list if\r
98: configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\r
99: listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );\r
100: listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );\r
101: }\r
-BFD08B22 0FBE MOVE SP, S8
-BFD08B24 4BC1 LW S8, 4(SP)
-BFD08B26 4C05 ADDIU SP, SP, 8
-BFD08B28 459F JR16 RA
-BFD08B2A 0C00 NOP
+BFD08B22 0FBE MOVE SP, S8\r
+BFD08B24 4BC1 LW S8, 4(SP)\r
+BFD08B26 4C05 ADDIU SP, SP, 8\r
+BFD08B28 459F JR16 RA\r
+BFD08B2A 0C00 NOP\r
102: /*-----------------------------------------------------------*/\r
103: \r
104: void vListInitialiseItem( ListItem_t * const pxItem )\r
105: {\r
-BFD09DCC 4FB0 ADDIU SP, SP, -8
-BFD09DCE CBC1 SW S8, 4(SP)
-BFD09DD0 0FDD MOVE S8, SP
-BFD09DD2 0008F89E SW A0, 8(S8)
+BFD09DCC 4FB0 ADDIU SP, SP, -8\r
+BFD09DCE CBC1 SW S8, 4(SP)\r
+BFD09DD0 0FDD MOVE S8, SP\r
+BFD09DD2 0008F89E SW A0, 8(S8)\r
106: /* Make sure the list item is not recorded as being on a list. */\r
107: pxItem->pvContainer = NULL;\r
-BFD09DD6 0008FC5E LW V0, 8(S8)
-BFD09DDA E824 SW S0, 16(V0)
+BFD09DD6 0008FC5E LW V0, 8(S8)\r
+BFD09DDA E824 SW S0, 16(V0)\r
108: \r
109: /* Write known values into the list item if\r
110: configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\r
111: listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );\r
112: listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );\r
113: }\r
-BFD09DDC 0FBE MOVE SP, S8
-BFD09DDE 4BC1 LW S8, 4(SP)
-BFD09DE0 4C05 ADDIU SP, SP, 8
-BFD09DE2 459F JR16 RA
-BFD09DE4 0C00 NOP
+BFD09DDC 0FBE MOVE SP, S8\r
+BFD09DDE 4BC1 LW S8, 4(SP)\r
+BFD09DE0 4C05 ADDIU SP, SP, 8\r
+BFD09DE2 459F JR16 RA\r
+BFD09DE4 0C00 NOP\r
114: /*-----------------------------------------------------------*/\r
115: \r
116: void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )\r
117: {\r
-BFD07C94 4FF9 ADDIU SP, SP, -16
-BFD07C96 CBC3 SW S8, 12(SP)
-BFD07C98 0FDD MOVE S8, SP
-BFD07C9A 0010F89E SW A0, 16(S8)
-BFD07C9E 0014F8BE SW A1, 20(S8)
+BFD07C94 4FF9 ADDIU SP, SP, -16\r
+BFD07C96 CBC3 SW S8, 12(SP)\r
+BFD07C98 0FDD MOVE S8, SP\r
+BFD07C9A 0010F89E SW A0, 16(S8)\r
+BFD07C9E 0014F8BE SW A1, 20(S8)\r
118: ListItem_t * const pxIndex = pxList->pxIndex;\r
-BFD07CA2 0010FC5E LW V0, 16(S8)
-BFD07CA6 6921 LW V0, 4(V0)
-BFD07CA8 0000F85E SW V0, 0(S8)
+BFD07CA2 0010FC5E LW V0, 16(S8)\r
+BFD07CA6 6921 LW V0, 4(V0)\r
+BFD07CA8 0000F85E SW V0, 0(S8)\r
119: \r
120: /* Only effective when configASSERT() is also defined, these tests may catch\r
121: the list data structures being overwritten in memory. They will not catch\r
127: makes the new list item the last item to be removed by a call to\r
128: listGET_OWNER_OF_NEXT_ENTRY(). */\r
129: pxNewListItem->pxNext = pxIndex;\r
-BFD07CAC 0014FC5E LW V0, 20(S8)
-BFD07CB0 0000FC7E LW V1, 0(S8)
-BFD07CB4 E9A1 SW V1, 4(V0)
+BFD07CAC 0014FC5E LW V0, 20(S8)\r
+BFD07CB0 0000FC7E LW V1, 0(S8)\r
+BFD07CB4 E9A1 SW V1, 4(V0)\r
130: pxNewListItem->pxPrevious = pxIndex->pxPrevious;\r
-BFD07CB6 0000FC5E LW V0, 0(S8)
-BFD07CBA 69A2 LW V1, 8(V0)
-BFD07CBC 0014FC5E LW V0, 20(S8)
-BFD07CC0 E9A2 SW V1, 8(V0)
+BFD07CB6 0000FC5E LW V0, 0(S8)\r
+BFD07CBA 69A2 LW V1, 8(V0)\r
+BFD07CBC 0014FC5E LW V0, 20(S8)\r
+BFD07CC0 E9A2 SW V1, 8(V0)\r
131: \r
132: /* Only used during decision coverage testing. */\r
133: mtCOVERAGE_TEST_DELAY();\r
134: \r
135: pxIndex->pxPrevious->pxNext = pxNewListItem;\r
-BFD07CC2 0000FC5E LW V0, 0(S8)
-BFD07CC6 6922 LW V0, 8(V0)
-BFD07CC8 0014FC7E LW V1, 20(S8)
-BFD07CCC E9A1 SW V1, 4(V0)
+BFD07CC2 0000FC5E LW V0, 0(S8)\r
+BFD07CC6 6922 LW V0, 8(V0)\r
+BFD07CC8 0014FC7E LW V1, 20(S8)\r
+BFD07CCC E9A1 SW V1, 4(V0)\r
136: pxIndex->pxPrevious = pxNewListItem;\r
-BFD07CCE 0000FC5E LW V0, 0(S8)
-BFD07CD2 0014FC7E LW V1, 20(S8)
-BFD07CD6 E9A2 SW V1, 8(V0)
+BFD07CCE 0000FC5E LW V0, 0(S8)\r
+BFD07CD2 0014FC7E LW V1, 20(S8)\r
+BFD07CD6 E9A2 SW V1, 8(V0)\r
137: \r
138: /* Remember which list the item is in. */\r
139: pxNewListItem->pvContainer = ( void * ) pxList;\r
-BFD07CD8 0014FC5E LW V0, 20(S8)
-BFD07CDC 0010FC7E LW V1, 16(S8)
-BFD07CE0 E9A4 SW V1, 16(V0)
+BFD07CD8 0014FC5E LW V0, 20(S8)\r
+BFD07CDC 0010FC7E LW V1, 16(S8)\r
+BFD07CE0 E9A4 SW V1, 16(V0)\r
140: \r
141: ( pxList->uxNumberOfItems )++;\r
-BFD07CE2 0010FC5E LW V0, 16(S8)
-BFD07CE6 6920 LW V0, 0(V0)
-BFD07CE8 6DA0 ADDIU V1, V0, 1
-BFD07CEA 0010FC5E LW V0, 16(S8)
-BFD07CEE E9A0 SW V1, 0(V0)
+BFD07CE2 0010FC5E LW V0, 16(S8)\r
+BFD07CE6 6920 LW V0, 0(V0)\r
+BFD07CE8 6DA0 ADDIU V1, V0, 1\r
+BFD07CEA 0010FC5E LW V0, 16(S8)\r
+BFD07CEE E9A0 SW V1, 0(V0)\r
142: }\r
-BFD07CF0 0FBE MOVE SP, S8
-BFD07CF2 4BC3 LW S8, 12(SP)
-BFD07CF4 4C09 ADDIU SP, SP, 16
-BFD07CF6 459F JR16 RA
-BFD07CF8 0C00 NOP
+BFD07CF0 0FBE MOVE SP, S8\r
+BFD07CF2 4BC3 LW S8, 12(SP)\r
+BFD07CF4 4C09 ADDIU SP, SP, 16\r
+BFD07CF6 459F JR16 RA\r
+BFD07CF8 0C00 NOP\r
143: /*-----------------------------------------------------------*/\r
144: \r
145: void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )\r
146: {\r
-BFD06080 4FF9 ADDIU SP, SP, -16
-BFD06082 CBC3 SW S8, 12(SP)
-BFD06084 0FDD MOVE S8, SP
-BFD06086 0010F89E SW A0, 16(S8)
-BFD0608A 0014F8BE SW A1, 20(S8)
+BFD06080 4FF9 ADDIU SP, SP, -16\r
+BFD06082 CBC3 SW S8, 12(SP)\r
+BFD06084 0FDD MOVE S8, SP\r
+BFD06086 0010F89E SW A0, 16(S8)\r
+BFD0608A 0014F8BE SW A1, 20(S8)\r
147: ListItem_t *pxIterator;\r
148: const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;\r
-BFD0608E 0014FC5E LW V0, 20(S8)
-BFD06092 6920 LW V0, 0(V0)
-BFD06094 0004F85E SW V0, 4(S8)
+BFD0608E 0014FC5E LW V0, 20(S8)\r
+BFD06092 6920 LW V0, 0(V0)\r
+BFD06094 0004F85E SW V0, 4(S8)\r
149: \r
150: /* Only effective when configASSERT() is also defined, these tests may catch\r
151: the list data structures being overwritten in memory. They will not catch\r
162: the iteration loop below will not end. Therefore the value is checked\r
163: first, and the algorithm slightly modified if necessary. */\r
164: if( xValueOfInsertion == portMAX_DELAY )\r
-BFD06098 0004FC7E LW V1, 4(S8)
-BFD0609C ED7F LI V0, -1
-BFD0609E 0008B443 BNE V1, V0, 0xBFD060B2
-BFD060A0 0C000008 SLL ZERO, T0, 1
-BFD060A2 0C00 NOP
+BFD06098 0004FC7E LW V1, 4(S8)\r
+BFD0609C ED7F LI V0, -1\r
+BFD0609E 0008B443 BNE V1, V0, 0xBFD060B2\r
+BFD060A0 0C000008 SLL ZERO, T0, 1\r
+BFD060A2 0C00 NOP\r
165: {\r
166: pxIterator = pxList->xListEnd.pxPrevious;\r
-BFD060A4 0010FC5E LW V0, 16(S8)
-BFD060A8 6924 LW V0, 16(V0)
-BFD060AA 0000F85E SW V0, 0(S8)
-BFD060AE CC17 B 0xBFD060DE
-BFD060B0 0C00 NOP
+BFD060A4 0010FC5E LW V0, 16(S8)\r
+BFD060A8 6924 LW V0, 16(V0)\r
+BFD060AA 0000F85E SW V0, 0(S8)\r
+BFD060AE CC17 B 0xBFD060DE\r
+BFD060B0 0C00 NOP\r
167: }\r
168: else\r
169: {\r
190: **********************************************************************/\r
191: \r
192: for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */\r
-BFD060B2 0010FC5E LW V0, 16(S8)
-BFD060B6 6D24 ADDIU V0, V0, 8
-BFD060B8 0000F85E SW V0, 0(S8)
-BFD060BC CC06 B 0xBFD060CA
-BFD060BE 0C00 NOP
-BFD060C0 0000FC5E LW V0, 0(S8)
-BFD060C4 6921 LW V0, 4(V0)
-BFD060C6 0000F85E SW V0, 0(S8)
-BFD060CA 0000FC5E LW V0, 0(S8)
-BFD060CE 6921 LW V0, 4(V0)
-BFD060D0 69A0 LW V1, 0(V0)
-BFD060D2 0004FC5E LW V0, 4(S8)
-BFD060D6 13900062 SLTU V0, V0, V1
-BFD060D8 40E21390 ADDI GP, S0, 16610
-BFD060DA FFF140E2 BEQZC V0, 0xBFD060C0
-BFD060DC FC5EFFF1 LW RA, -930(S1)
+BFD060B2 0010FC5E LW V0, 16(S8)\r
+BFD060B6 6D24 ADDIU V0, V0, 8\r
+BFD060B8 0000F85E SW V0, 0(S8)\r
+BFD060BC CC06 B 0xBFD060CA\r
+BFD060BE 0C00 NOP\r
+BFD060C0 0000FC5E LW V0, 0(S8)\r
+BFD060C4 6921 LW V0, 4(V0)\r
+BFD060C6 0000F85E SW V0, 0(S8)\r
+BFD060CA 0000FC5E LW V0, 0(S8)\r
+BFD060CE 6921 LW V0, 4(V0)\r
+BFD060D0 69A0 LW V1, 0(V0)\r
+BFD060D2 0004FC5E LW V0, 4(S8)\r
+BFD060D6 13900062 SLTU V0, V0, V1\r
+BFD060D8 40E21390 ADDI GP, S0, 16610\r
+BFD060DA FFF140E2 BEQZC V0, 0xBFD060C0\r
+BFD060DC FC5EFFF1 LW RA, -930(S1)\r
193: {\r
194: /* There is nothing to do here, just iterating to the wanted\r
195: insertion position. */\r
197: }\r
198: \r
199: pxNewListItem->pxNext = pxIterator->pxNext;\r
-BFD060DE 0000FC5E LW V0, 0(S8)
-BFD060E2 69A1 LW V1, 4(V0)
-BFD060E4 0014FC5E LW V0, 20(S8)
-BFD060E8 E9A1 SW V1, 4(V0)
+BFD060DE 0000FC5E LW V0, 0(S8)\r
+BFD060E2 69A1 LW V1, 4(V0)\r
+BFD060E4 0014FC5E LW V0, 20(S8)\r
+BFD060E8 E9A1 SW V1, 4(V0)\r
200: pxNewListItem->pxNext->pxPrevious = pxNewListItem;\r
-BFD060EA 0014FC5E LW V0, 20(S8)
-BFD060EE 6921 LW V0, 4(V0)
-BFD060F0 0014FC7E LW V1, 20(S8)
-BFD060F4 E9A2 SW V1, 8(V0)
+BFD060EA 0014FC5E LW V0, 20(S8)\r
+BFD060EE 6921 LW V0, 4(V0)\r
+BFD060F0 0014FC7E LW V1, 20(S8)\r
+BFD060F4 E9A2 SW V1, 8(V0)\r
201: pxNewListItem->pxPrevious = pxIterator;\r
-BFD060F6 0014FC5E LW V0, 20(S8)
-BFD060FA 0000FC7E LW V1, 0(S8)
-BFD060FE E9A2 SW V1, 8(V0)
+BFD060F6 0014FC5E LW V0, 20(S8)\r
+BFD060FA 0000FC7E LW V1, 0(S8)\r
+BFD060FE E9A2 SW V1, 8(V0)\r
202: pxIterator->pxNext = pxNewListItem;\r
-BFD06100 0000FC5E LW V0, 0(S8)
-BFD06104 0014FC7E LW V1, 20(S8)
-BFD06108 E9A1 SW V1, 4(V0)
+BFD06100 0000FC5E LW V0, 0(S8)\r
+BFD06104 0014FC7E LW V1, 20(S8)\r
+BFD06108 E9A1 SW V1, 4(V0)\r
203: \r
204: /* Remember which list the item is in. This allows fast removal of the\r
205: item later. */\r
206: pxNewListItem->pvContainer = ( void * ) pxList;\r
-BFD0610A 0014FC5E LW V0, 20(S8)
-BFD0610E 0010FC7E LW V1, 16(S8)
-BFD06112 E9A4 SW V1, 16(V0)
+BFD0610A 0014FC5E LW V0, 20(S8)\r
+BFD0610E 0010FC7E LW V1, 16(S8)\r
+BFD06112 E9A4 SW V1, 16(V0)\r
207: \r
208: ( pxList->uxNumberOfItems )++;\r
-BFD06114 0010FC5E LW V0, 16(S8)
-BFD06118 6920 LW V0, 0(V0)
-BFD0611A 6DA0 ADDIU V1, V0, 1
-BFD0611C 0010FC5E LW V0, 16(S8)
-BFD06120 E9A0 SW V1, 0(V0)
+BFD06114 0010FC5E LW V0, 16(S8)\r
+BFD06118 6920 LW V0, 0(V0)\r
+BFD0611A 6DA0 ADDIU V1, V0, 1\r
+BFD0611C 0010FC5E LW V0, 16(S8)\r
+BFD06120 E9A0 SW V1, 0(V0)\r
209: }\r
-BFD06122 0FBE MOVE SP, S8
-BFD06124 4BC3 LW S8, 12(SP)
-BFD06126 4C09 ADDIU SP, SP, 16
-BFD06128 459F JR16 RA
-BFD0612A 0C00 NOP
+BFD06122 0FBE MOVE SP, S8\r
+BFD06124 4BC3 LW S8, 12(SP)\r
+BFD06126 4C09 ADDIU SP, SP, 16\r
+BFD06128 459F JR16 RA\r
+BFD0612A 0C00 NOP\r
210: /*-----------------------------------------------------------*/\r
211: \r
212: UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )\r
213: {\r
-BFD00190 4FF9 ADDIU SP, SP, -16
-BFD00192 CBC3 SW S8, 12(SP)
-BFD00194 0FDD MOVE S8, SP
-BFD00196 0010F89E SW A0, 16(S8)
+BFD00190 4FF9 ADDIU SP, SP, -16\r
+BFD00192 CBC3 SW S8, 12(SP)\r
+BFD00194 0FDD MOVE S8, SP\r
+BFD00196 0010F89E SW A0, 16(S8)\r
214: /* The list item knows which list it is in. Obtain the list from the list\r
215: item. */\r
216: List_t * const pxList = ( List_t * ) pxItemToRemove->pvContainer;\r
-BFD0019A 0010FC5E LW V0, 16(S8)
-BFD0019E 6924 LW V0, 16(V0)
-BFD001A0 0000F85E SW V0, 0(S8)
+BFD0019A 0010FC5E LW V0, 16(S8)\r
+BFD0019E 6924 LW V0, 16(V0)\r
+BFD001A0 0000F85E SW V0, 0(S8)\r
217: \r
218: pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;\r
-BFD001A4 0010FC5E LW V0, 16(S8)
-BFD001A8 6921 LW V0, 4(V0)
-BFD001AA 0010FC7E LW V1, 16(S8)
-BFD001AE 69B2 LW V1, 8(V1)
-BFD001B0 E9A2 SW V1, 8(V0)
+BFD001A4 0010FC5E LW V0, 16(S8)\r
+BFD001A8 6921 LW V0, 4(V0)\r
+BFD001AA 0010FC7E LW V1, 16(S8)\r
+BFD001AE 69B2 LW V1, 8(V1)\r
+BFD001B0 E9A2 SW V1, 8(V0)\r
219: pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;\r
-BFD001B2 0010FC5E LW V0, 16(S8)
-BFD001B6 6922 LW V0, 8(V0)
-BFD001B8 0010FC7E LW V1, 16(S8)
-BFD001BC 69B1 LW V1, 4(V1)
-BFD001BE E9A1 SW V1, 4(V0)
+BFD001B2 0010FC5E LW V0, 16(S8)\r
+BFD001B6 6922 LW V0, 8(V0)\r
+BFD001B8 0010FC7E LW V1, 16(S8)\r
+BFD001BC 69B1 LW V1, 4(V1)\r
+BFD001BE E9A1 SW V1, 4(V0)\r
220: \r
221: /* Only used during decision coverage testing. */\r
222: mtCOVERAGE_TEST_DELAY();\r
223: \r
224: /* Make sure the index is left pointing to a valid item. */\r
225: if( pxList->pxIndex == pxItemToRemove )\r
-BFD001C0 0000FC5E LW V0, 0(S8)
-BFD001C4 69A1 LW V1, 4(V0)
-BFD001C6 0010FC5E LW V0, 16(S8)
-BFD001CA 0007B443 BNE V1, V0, 0xBFD001DC
-BFD001CC 0C000007 SLL ZERO, A3, 1
-BFD001CE 0C00 NOP
+BFD001C0 0000FC5E LW V0, 0(S8)\r
+BFD001C4 69A1 LW V1, 4(V0)\r
+BFD001C6 0010FC5E LW V0, 16(S8)\r
+BFD001CA 0007B443 BNE V1, V0, 0xBFD001DC\r
+BFD001CC 0C000007 SLL ZERO, A3, 1\r
+BFD001CE 0C00 NOP\r
226: {\r
227: pxList->pxIndex = pxItemToRemove->pxPrevious;\r
-BFD001D0 0010FC5E LW V0, 16(S8)
-BFD001D4 69A2 LW V1, 8(V0)
-BFD001D6 0000FC5E LW V0, 0(S8)
-BFD001DA E9A1 SW V1, 4(V0)
+BFD001D0 0010FC5E LW V0, 16(S8)\r
+BFD001D4 69A2 LW V1, 8(V0)\r
+BFD001D6 0000FC5E LW V0, 0(S8)\r
+BFD001DA E9A1 SW V1, 4(V0)\r
228: }\r
229: else\r
230: {\r
232: }\r
233: \r
234: pxItemToRemove->pvContainer = NULL;\r
-BFD001DC 0010FC5E LW V0, 16(S8)
-BFD001E0 E824 SW S0, 16(V0)
+BFD001DC 0010FC5E LW V0, 16(S8)\r
+BFD001E0 E824 SW S0, 16(V0)\r
235: ( pxList->uxNumberOfItems )--;\r
-BFD001E2 0000FC5E LW V0, 0(S8)
-BFD001E6 6920 LW V0, 0(V0)
-BFD001E8 6DAE ADDIU V1, V0, -1
-BFD001EA 0000FC5E LW V0, 0(S8)
-BFD001EE E9A0 SW V1, 0(V0)
+BFD001E2 0000FC5E LW V0, 0(S8)\r
+BFD001E6 6920 LW V0, 0(V0)\r
+BFD001E8 6DAE ADDIU V1, V0, -1\r
+BFD001EA 0000FC5E LW V0, 0(S8)\r
+BFD001EE E9A0 SW V1, 0(V0)\r
236: \r
237: return pxList->uxNumberOfItems;\r
-BFD001F0 0000FC5E LW V0, 0(S8)
-BFD001F4 6920 LW V0, 0(V0)
+BFD001F0 0000FC5E LW V0, 0(S8)\r
+BFD001F4 6920 LW V0, 0(V0)\r
238: }\r
-BFD001F6 0FBE MOVE SP, S8
-BFD001F8 4BC3 LW S8, 12(SP)
-BFD001FA 4C09 ADDIU SP, SP, 16
-BFD001FC 459F JR16 RA
-BFD001FE 0C00 NOP
+BFD001F6 0FBE MOVE SP, S8\r
+BFD001F8 4BC3 LW S8, 12(SP)\r
+BFD001FA 4C09 ADDIU SP, SP, 16\r
+BFD001FC 459F JR16 RA\r
+BFD001FE 0C00 NOP\r
239: /*-----------------------------------------------------------*/\r
240: \r
---- c:/e/dev/freertos/workingcopy/freertos/source/event_groups.c --------------------------------------
+--- c:/e/dev/freertos/workingcopy/freertos/source/event_groups.c --------------------------------------\r
1: /*\r
2: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
3: All rights reserved\r
8: \r
9: FreeRTOS is free software; you can redistribute it and/or modify it under\r
10: the terms of the GNU General Public License (version 2) as published by the\r
-11: Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+11: Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
12: \r
13: ***************************************************************************\r
14: >>! NOTE: The modification to the GPL is included to allow you to !<<\r
137: \r
138: EventGroupHandle_t xEventGroupCreate( void )\r
139: {\r
-BFD09320 4FF1 ADDIU SP, SP, -32
-BFD09322 CBE7 SW RA, 28(SP)
-BFD09324 CBC6 SW S8, 24(SP)
-BFD09326 0FDD MOVE S8, SP
+BFD09320 4FF1 ADDIU SP, SP, -32\r
+BFD09322 CBE7 SW RA, 28(SP)\r
+BFD09324 CBC6 SW S8, 24(SP)\r
+BFD09326 0FDD MOVE S8, SP\r
140: EventGroup_t *pxEventBits;\r
141: \r
142: pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) );\r
-BFD09328 EE18 LI A0, 24
-BFD0932A 111677E8 JALS pvPortMalloc
-BFD0932C 0C001116 ADDI T0, S6, 3072
-BFD0932E 0C00 NOP
-BFD09330 0010F85E SW V0, 16(S8)
+BFD09328 EE18 LI A0, 24\r
+BFD0932A 111677E8 JALS pvPortMalloc\r
+BFD0932C 0C001116 ADDI T0, S6, 3072\r
+BFD0932E 0C00 NOP\r
+BFD09330 0010F85E SW V0, 16(S8)\r
143: if( pxEventBits != NULL )\r
-BFD09334 0010FC5E LW V0, 16(S8)
-BFD09338 000A40E2 BEQZC V0, 0xBFD09350
+BFD09334 0010FC5E LW V0, 16(S8)\r
+BFD09338 000A40E2 BEQZC V0, 0xBFD09350\r
144: {\r
145: pxEventBits->uxEventBits = 0;\r
-BFD0933C 0010FC5E LW V0, 16(S8)
-BFD09340 E820 SW S0, 0(V0)
+BFD0933C 0010FC5E LW V0, 16(S8)\r
+BFD09340 E820 SW S0, 0(V0)\r
146: vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );\r
-BFD09342 0010FC5E LW V0, 16(S8)
-BFD09346 6D22 ADDIU V0, V0, 4
-BFD09348 0C82 MOVE A0, V0
-BFD0934A 457077E8 JALS vListInitialise
-BFD0934C 4570 SWM16 0x3, 0(SP)
-BFD0934E 0C00 NOP
+BFD09342 0010FC5E LW V0, 16(S8)\r
+BFD09346 6D22 ADDIU V0, V0, 4\r
+BFD09348 0C82 MOVE A0, V0\r
+BFD0934A 457077E8 JALS vListInitialise\r
+BFD0934C 4570 SWM16 0x3, 0(SP)\r
+BFD0934E 0C00 NOP\r
147: traceEVENT_GROUP_CREATE( pxEventBits );\r
148: }\r
149: else\r
152: }\r
153: \r
154: return ( EventGroupHandle_t ) pxEventBits;\r
-BFD09350 0010FC5E LW V0, 16(S8)
+BFD09350 0010FC5E LW V0, 16(S8)\r
155: }\r
-BFD09354 0FBE MOVE SP, S8
-BFD09356 4BE7 LW RA, 28(SP)
-BFD09358 4BC6 LW S8, 24(SP)
-BFD0935A 4C11 ADDIU SP, SP, 32
-BFD0935C 459F JR16 RA
-BFD0935E 0C00 NOP
+BFD09354 0FBE MOVE SP, S8\r
+BFD09356 4BE7 LW RA, 28(SP)\r
+BFD09358 4BC6 LW S8, 24(SP)\r
+BFD0935A 4C11 ADDIU SP, SP, 32\r
+BFD0935C 459F JR16 RA\r
+BFD0935E 0C00 NOP\r
156: /*-----------------------------------------------------------*/\r
157: \r
158: EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait )\r
159: {\r
-BFD01B0C 4FE9 ADDIU SP, SP, -48
-BFD01B0E CBEB SW RA, 44(SP)
-BFD01B10 CBCA SW S8, 40(SP)
-BFD01B12 0FDD MOVE S8, SP
-BFD01B14 0030F89E SW A0, 48(S8)
-BFD01B18 0034F8BE SW A1, 52(S8)
-BFD01B1C 0038F8DE SW A2, 56(S8)
-BFD01B20 003CF8FE SW A3, 60(S8)
+BFD01B0C 4FE9 ADDIU SP, SP, -48\r
+BFD01B0E CBEB SW RA, 44(SP)\r
+BFD01B10 CBCA SW S8, 40(SP)\r
+BFD01B12 0FDD MOVE S8, SP\r
+BFD01B14 0030F89E SW A0, 48(S8)\r
+BFD01B18 0034F8BE SW A1, 52(S8)\r
+BFD01B1C 0038F8DE SW A2, 56(S8)\r
+BFD01B20 003CF8FE SW A3, 60(S8)\r
160: EventBits_t uxOriginalBitValue, uxReturn;\r
161: EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;\r
-BFD01B24 0030FC5E LW V0, 48(S8)
-BFD01B28 0014F85E SW V0, 20(S8)
+BFD01B24 0030FC5E LW V0, 48(S8)\r
+BFD01B28 0014F85E SW V0, 20(S8)\r
162: BaseType_t xAlreadyYielded;\r
163: BaseType_t xTimeoutOccurred = pdFALSE;\r
-BFD01B2C 0018F81E SW ZERO, 24(S8)
+BFD01B2C 0018F81E SW ZERO, 24(S8)\r
164: \r
165: configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );\r
-BFD01B30 0038FC7E LW V1, 56(S8)
-BFD01B34 FF0041A2 LUI V0, 0xFF00
-BFD01B36 4493FF00 LW T8, 17555(ZERO)
-BFD01B38 4493 AND16 V0, V1
-BFD01B3A 000940E2 BEQZC V0, 0xBFD01B50
-BFD01B3E BFD141A2 LUI V0, 0xBFD1
-BFD01B40 3082BFD1 LDC1 F30, 12418(S1)
-BFD01B42 9C0C3082 ADDIU A0, V0, -25588
-BFD01B44 30A09C0C LWC1 F0, 12448(T4)
-BFD01B46 00A530A0 ADDIU A1, ZERO, 165
-BFD01B4A 4B7E77E8 JALS vAssertCalled
-BFD01B4C 4B7E LW K1, 120(SP)
-BFD01B4E 0C00 NOP
+BFD01B30 0038FC7E LW V1, 56(S8)\r
+BFD01B34 FF0041A2 LUI V0, 0xFF00\r
+BFD01B36 4493FF00 LW T8, 17555(ZERO)\r
+BFD01B38 4493 AND16 V0, V1\r
+BFD01B3A 000940E2 BEQZC V0, 0xBFD01B50\r
+BFD01B3E BFD141A2 LUI V0, 0xBFD1\r
+BFD01B40 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD01B42 9C0C3082 ADDIU A0, V0, -25588\r
+BFD01B44 30A09C0C LWC1 F0, 12448(T4)\r
+BFD01B46 00A530A0 ADDIU A1, ZERO, 165\r
+BFD01B4A 4B7E77E8 JALS vAssertCalled\r
+BFD01B4C 4B7E LW K1, 120(SP)\r
+BFD01B4E 0C00 NOP\r
166: configASSERT( uxBitsToWaitFor != 0 );\r
-BFD01B50 0038FC5E LW V0, 56(S8)
-BFD01B54 000940A2 BNEZC V0, 0xBFD01B6A
-BFD01B58 BFD141A2 LUI V0, 0xBFD1
-BFD01B5A 3082BFD1 LDC1 F30, 12418(S1)
-BFD01B5C 9C0C3082 ADDIU A0, V0, -25588
-BFD01B5E 30A09C0C LWC1 F0, 12448(T4)
-BFD01B60 00A630A0 ADDIU A1, ZERO, 166
-BFD01B64 4B7E77E8 JALS vAssertCalled
-BFD01B66 4B7E LW K1, 120(SP)
-BFD01B68 0C00 NOP
+BFD01B50 0038FC5E LW V0, 56(S8)\r
+BFD01B54 000940A2 BNEZC V0, 0xBFD01B6A\r
+BFD01B58 BFD141A2 LUI V0, 0xBFD1\r
+BFD01B5A 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD01B5C 9C0C3082 ADDIU A0, V0, -25588\r
+BFD01B5E 30A09C0C LWC1 F0, 12448(T4)\r
+BFD01B60 00A630A0 ADDIU A1, ZERO, 166\r
+BFD01B64 4B7E77E8 JALS vAssertCalled\r
+BFD01B66 4B7E LW K1, 120(SP)\r
+BFD01B68 0C00 NOP\r
167: #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\r
168: {\r
169: configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\r
-BFD01B6A 4A8E77E8 JALS xTaskGetSchedulerState
-BFD01B6C 4A8E LW S4, 56(SP)
-BFD01B6E 0C00 NOP
-BFD01B70 000440A2 BNEZC V0, 0xBFD01B7C
-BFD01B74 003CFC5E LW V0, 60(S8)
-BFD01B78 000340A2 BNEZC V0, 0xBFD01B82
-BFD01B7C ED01 LI V0, 1
-BFD01B7E CC02 B 0xBFD01B84
-BFD01B80 0C00 NOP
-BFD01B82 0C40 MOVE V0, ZERO
-BFD01B84 000940A2 BNEZC V0, 0xBFD01B9A
-BFD01B88 BFD141A2 LUI V0, 0xBFD1
-BFD01B8A 3082BFD1 LDC1 F30, 12418(S1)
-BFD01B8C 9C0C3082 ADDIU A0, V0, -25588
-BFD01B8E 30A09C0C LWC1 F0, 12448(T4)
-BFD01B90 00A930A0 ADDIU A1, ZERO, 169
-BFD01B94 4B7E77E8 JALS vAssertCalled
-BFD01B96 4B7E LW K1, 120(SP)
-BFD01B98 0C00 NOP
+BFD01B6A 4A8E77E8 JALS xTaskGetSchedulerState\r
+BFD01B6C 4A8E LW S4, 56(SP)\r
+BFD01B6E 0C00 NOP\r
+BFD01B70 000440A2 BNEZC V0, 0xBFD01B7C\r
+BFD01B74 003CFC5E LW V0, 60(S8)\r
+BFD01B78 000340A2 BNEZC V0, 0xBFD01B82\r
+BFD01B7C ED01 LI V0, 1\r
+BFD01B7E CC02 B 0xBFD01B84\r
+BFD01B80 0C00 NOP\r
+BFD01B82 0C40 MOVE V0, ZERO\r
+BFD01B84 000940A2 BNEZC V0, 0xBFD01B9A\r
+BFD01B88 BFD141A2 LUI V0, 0xBFD1\r
+BFD01B8A 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD01B8C 9C0C3082 ADDIU A0, V0, -25588\r
+BFD01B8E 30A09C0C LWC1 F0, 12448(T4)\r
+BFD01B90 00A930A0 ADDIU A1, ZERO, 169\r
+BFD01B94 4B7E77E8 JALS vAssertCalled\r
+BFD01B96 4B7E LW K1, 120(SP)\r
+BFD01B98 0C00 NOP\r
170: }\r
171: #endif\r
172: \r
173: vTaskSuspendAll();\r
-BFD01B9A 4EF477E8 JALS vTaskSuspendAll
-BFD01B9C 4EF4 ADDIU S7, S7, -6
-BFD01B9E 0C00 NOP
+BFD01B9A 4EF477E8 JALS vTaskSuspendAll\r
+BFD01B9C 4EF4 ADDIU S7, S7, -6\r
+BFD01B9E 0C00 NOP\r
174: {\r
175: uxOriginalBitValue = pxEventBits->uxEventBits;\r
-BFD01BA0 0014FC5E LW V0, 20(S8)
-BFD01BA4 6920 LW V0, 0(V0)
-BFD01BA6 001CF85E SW V0, 28(S8)
+BFD01BA0 0014FC5E LW V0, 20(S8)\r
+BFD01BA4 6920 LW V0, 0(V0)\r
+BFD01BA6 001CF85E SW V0, 28(S8)\r
176: \r
177: ( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet );\r
-BFD01BAA 0030FC9E LW A0, 48(S8)
-BFD01BAE 0034FCBE LW A1, 52(S8)
-BFD01BB2 12B477E8 JALS xEventGroupSetBits
-BFD01BB4 0C0012B4 ADDI S5, S4, 3072
-BFD01BB6 0C00 NOP
+BFD01BAA 0030FC9E LW A0, 48(S8)\r
+BFD01BAE 0034FCBE LW A1, 52(S8)\r
+BFD01BB2 12B477E8 JALS xEventGroupSetBits\r
+BFD01BB4 0C0012B4 ADDI S5, S4, 3072\r
+BFD01BB6 0C00 NOP\r
178: \r
179: if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor )\r
-BFD01BB8 001CFC7E LW V1, 28(S8)
-BFD01BBC 0034FC5E LW V0, 52(S8)
-BFD01BC0 44DA OR16 V1, V0
-BFD01BC2 0038FC5E LW V0, 56(S8)
-BFD01BC6 449A AND16 V1, V0
-BFD01BC8 0038FC5E LW V0, 56(S8)
-BFD01BCC 0016B443 BNE V1, V0, 0xBFD01BFC
-BFD01BCE 0C000016 SLL ZERO, S6, 1
-BFD01BD0 0C00 NOP
+BFD01BB8 001CFC7E LW V1, 28(S8)\r
+BFD01BBC 0034FC5E LW V0, 52(S8)\r
+BFD01BC0 44DA OR16 V1, V0\r
+BFD01BC2 0038FC5E LW V0, 56(S8)\r
+BFD01BC6 449A AND16 V1, V0\r
+BFD01BC8 0038FC5E LW V0, 56(S8)\r
+BFD01BCC 0016B443 BNE V1, V0, 0xBFD01BFC\r
+BFD01BCE 0C000016 SLL ZERO, S6, 1\r
+BFD01BD0 0C00 NOP\r
180: {\r
181: /* All the rendezvous bits are now set - no need to block. */\r
182: uxReturn = ( uxOriginalBitValue | uxBitsToSet );\r
-BFD01BD2 001CFC7E LW V1, 28(S8)
-BFD01BD6 0034FC5E LW V0, 52(S8)
-BFD01BDA 44D3 OR16 V0, V1
-BFD01BDC 0010F85E SW V0, 16(S8)
+BFD01BD2 001CFC7E LW V1, 28(S8)\r
+BFD01BD6 0034FC5E LW V0, 52(S8)\r
+BFD01BDA 44D3 OR16 V0, V1\r
+BFD01BDC 0010F85E SW V0, 16(S8)\r
183: \r
184: /* Rendezvous always clear the bits. They will have been cleared\r
185: already unless this is the only task in the rendezvous. */\r
186: pxEventBits->uxEventBits &= ~uxBitsToWaitFor;\r
-BFD01BE0 0014FC5E LW V0, 20(S8)
-BFD01BE4 69A0 LW V1, 0(V0)
-BFD01BE6 0038FC5E LW V0, 56(S8)
-BFD01BEA 4412 NOT16 V0, V0
-BFD01BEC 449A AND16 V1, V0
-BFD01BEE 0014FC5E LW V0, 20(S8)
-BFD01BF2 E9A0 SW V1, 0(V0)
+BFD01BE0 0014FC5E LW V0, 20(S8)\r
+BFD01BE4 69A0 LW V1, 0(V0)\r
+BFD01BE6 0038FC5E LW V0, 56(S8)\r
+BFD01BEA 4412 NOT16 V0, V0\r
+BFD01BEC 449A AND16 V1, V0\r
+BFD01BEE 0014FC5E LW V0, 20(S8)\r
+BFD01BF2 E9A0 SW V1, 0(V0)\r
187: \r
188: xTicksToWait = 0;\r
-BFD01BF4 003CF81E SW ZERO, 60(S8)
-BFD01BF6 CC1D003C SHILO null, 60
-BFD01BF8 CC1D B 0xBFD01C34
-BFD01BFA 0C00 NOP
+BFD01BF4 003CF81E SW ZERO, 60(S8)\r
+BFD01BF6 CC1D003C SHILO null, 60\r
+BFD01BF8 CC1D B 0xBFD01C34\r
+BFD01BFA 0C00 NOP\r
189: }\r
190: else\r
191: {\r
192: if( xTicksToWait != ( TickType_t ) 0 )\r
-BFD01BFC 003CFC5E LW V0, 60(S8)
-BFD01C00 001340E2 BEQZC V0, 0xBFD01C2A
+BFD01BFC 003CFC5E LW V0, 60(S8)\r
+BFD01C00 001340E2 BEQZC V0, 0xBFD01C2A\r
193: {\r
194: traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor );\r
195: \r
197: task's event list item so the kernel knows when a match is\r
198: found. Then enter the blocked state. */\r
199: vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait );\r
-BFD01C04 0014FC5E LW V0, 20(S8)
-BFD01C08 6DA2 ADDIU V1, V0, 4
-BFD01C0A 0038FC9E LW A0, 56(S8)
-BFD01C0E 050041A2 LUI V0, 0x500
-BFD01C10 0500 ADDU V0, S0, S0
-BFD01C12 44D4 OR16 V0, A0
-BFD01C14 0C83 MOVE A0, V1
-BFD01C16 0CA2 MOVE A1, V0
-BFD01C18 003CFCDE LW A2, 60(S8)
-BFD01C1C 248277E8 JALS vTaskPlaceOnUnorderedEventList
-BFD01C1E 2482 SLL S1, S0, 1
-BFD01C20 0C00 NOP
+BFD01C04 0014FC5E LW V0, 20(S8)\r
+BFD01C08 6DA2 ADDIU V1, V0, 4\r
+BFD01C0A 0038FC9E LW A0, 56(S8)\r
+BFD01C0E 050041A2 LUI V0, 0x500\r
+BFD01C10 0500 ADDU V0, S0, S0\r
+BFD01C12 44D4 OR16 V0, A0\r
+BFD01C14 0C83 MOVE A0, V1\r
+BFD01C16 0CA2 MOVE A1, V0\r
+BFD01C18 003CFCDE LW A2, 60(S8)\r
+BFD01C1C 248277E8 JALS vTaskPlaceOnUnorderedEventList\r
+BFD01C1E 2482 SLL S1, S0, 1\r
+BFD01C20 0C00 NOP\r
200: \r
201: /* This assignment is obsolete as uxReturn will get set after\r
202: the task unblocks, but some compilers mistakenly generate a\r
203: warning about uxReturn being returned without being set if the\r
204: assignment is omitted. */\r
205: uxReturn = 0;\r
-BFD01C22 0010F81E SW ZERO, 16(S8)
-BFD01C26 CC06 B 0xBFD01C34
-BFD01C28 0C00 NOP
+BFD01C22 0010F81E SW ZERO, 16(S8)\r
+BFD01C26 CC06 B 0xBFD01C34\r
+BFD01C28 0C00 NOP\r
206: }\r
207: else\r
208: {\r
209: /* The rendezvous bits were not set, but no block time was\r
210: specified - just return the current event bit value. */\r
211: uxReturn = pxEventBits->uxEventBits;\r
-BFD01C2A 0014FC5E LW V0, 20(S8)
-BFD01C2E 6920 LW V0, 0(V0)
-BFD01C30 0010F85E SW V0, 16(S8)
+BFD01C2A 0014FC5E LW V0, 20(S8)\r
+BFD01C2E 6920 LW V0, 0(V0)\r
+BFD01C30 0010F85E SW V0, 16(S8)\r
212: }\r
213: }\r
214: }\r
215: xAlreadyYielded = xTaskResumeAll();\r
-BFD01C34 158E77E8 JALS xTaskResumeAll
-BFD01C36 0C00158E LBU T4, 3072(T6)
-BFD01C38 0C00 NOP
-BFD01C3A 0020F85E SW V0, 32(S8)
+BFD01C34 158E77E8 JALS xTaskResumeAll\r
+BFD01C36 0C00158E LBU T4, 3072(T6)\r
+BFD01C38 0C00 NOP\r
+BFD01C3A 0020F85E SW V0, 32(S8)\r
216: \r
217: if( xTicksToWait != ( TickType_t ) 0 )\r
-BFD01C3E 003CFC5E LW V0, 60(S8)
-BFD01C42 004840E2 BEQZC V0, 0xBFD01CD6
+BFD01C3E 003CFC5E LW V0, 60(S8)\r
+BFD01C42 004840E2 BEQZC V0, 0xBFD01CD6\r
218: {\r
219: if( xAlreadyYielded == pdFALSE )\r
-BFD01C46 0020FC5E LW V0, 32(S8)
-BFD01C4A 001040A2 BNEZC V0, 0xBFD01C6E
+BFD01C46 0020FC5E LW V0, 32(S8)\r
+BFD01C4A 001040A2 BNEZC V0, 0xBFD01C6E\r
220: {\r
221: portYIELD_WITHIN_API();\r
-BFD01C4E 4DE677E8 JALS ulPortGetCP0Cause
-BFD01C50 4DE6 ADDIU T7, T7, 3
-BFD01C52 0C00 NOP
-BFD01C54 0024F85E SW V0, 36(S8)
-BFD01C58 0024FC5E LW V0, 36(S8)
-BFD01C5C 01005042 ORI V0, V0, 256
-BFD01C60 0024F85E SW V0, 36(S8)
-BFD01C64 0024FC9E LW A0, 36(S8)
-BFD01C68 4DF677E8 JALS vPortSetCP0Cause
-BFD01C6A 4DF6 ADDIU T7, T7, -5
-BFD01C6C 0C00 NOP
+BFD01C4E 4DE677E8 JALS ulPortGetCP0Cause\r
+BFD01C50 4DE6 ADDIU T7, T7, 3\r
+BFD01C52 0C00 NOP\r
+BFD01C54 0024F85E SW V0, 36(S8)\r
+BFD01C58 0024FC5E LW V0, 36(S8)\r
+BFD01C5C 01005042 ORI V0, V0, 256\r
+BFD01C60 0024F85E SW V0, 36(S8)\r
+BFD01C64 0024FC9E LW A0, 36(S8)\r
+BFD01C68 4DF677E8 JALS vPortSetCP0Cause\r
+BFD01C6A 4DF6 ADDIU T7, T7, -5\r
+BFD01C6C 0C00 NOP\r
222: }\r
223: else\r
224: {\r
230: the required bits were set they will have been stored in the task's\r
231: event list item, and they should now be retrieved then cleared. */\r
232: uxReturn = uxTaskResetEventItemValue();\r
-BFD01C6E 4C8677E8 JALS uxTaskResetEventItemValue
-BFD01C70 4C86 ADDIU A0, A0, 3
-BFD01C72 0C00 NOP
-BFD01C74 0010F85E SW V0, 16(S8)
+BFD01C6E 4C8677E8 JALS uxTaskResetEventItemValue\r
+BFD01C70 4C86 ADDIU A0, A0, 3\r
+BFD01C72 0C00 NOP\r
+BFD01C74 0010F85E SW V0, 16(S8)\r
233: \r
234: if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )\r
-BFD01C78 0010FC7E LW V1, 16(S8)
-BFD01C7C 020041A2 LUI V0, 0x200
-BFD01C80 4493 AND16 V0, V1
-BFD01C82 002240A2 BNEZC V0, 0xBFD01CCA
+BFD01C78 0010FC7E LW V1, 16(S8)\r
+BFD01C7C 020041A2 LUI V0, 0x200\r
+BFD01C80 4493 AND16 V0, V1\r
+BFD01C82 002240A2 BNEZC V0, 0xBFD01CCA\r
235: {\r
236: /* The task timed out, just return the current event bit value. */\r
237: taskENTER_CRITICAL();\r
-BFD01C86 33B877E8 JALS vTaskEnterCritical
-BFD01C88 0C0033B8 ADDIU SP, T8, 3072
-BFD01C8A 0C00 NOP
+BFD01C86 33B877E8 JALS vTaskEnterCritical\r
+BFD01C88 0C0033B8 ADDIU SP, T8, 3072\r
+BFD01C8A 0C00 NOP\r
238: {\r
239: uxReturn = pxEventBits->uxEventBits;\r
-BFD01C8C 0014FC5E LW V0, 20(S8)
-BFD01C90 6920 LW V0, 0(V0)
-BFD01C92 0010F85E SW V0, 16(S8)
+BFD01C8C 0014FC5E LW V0, 20(S8)\r
+BFD01C90 6920 LW V0, 0(V0)\r
+BFD01C92 0010F85E SW V0, 16(S8)\r
240: \r
241: /* Although the task got here because it timed out before the\r
242: bits it was waiting for were set, it is possible that since it\r
243: unblocked another task has set the bits. If this is the case\r
244: then it needs to clear the bits before exiting. */\r
245: if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor )\r
-BFD01C96 0010FC7E LW V1, 16(S8)
-BFD01C9A 0038FC5E LW V0, 56(S8)
-BFD01C9E 449A AND16 V1, V0
-BFD01CA0 0038FC5E LW V0, 56(S8)
-BFD01CA4 000BB443 BNE V1, V0, 0xBFD01CBE
-BFD01CA6 0C00000B SLL ZERO, T3, 1
-BFD01CA8 0C00 NOP
+BFD01C96 0010FC7E LW V1, 16(S8)\r
+BFD01C9A 0038FC5E LW V0, 56(S8)\r
+BFD01C9E 449A AND16 V1, V0\r
+BFD01CA0 0038FC5E LW V0, 56(S8)\r
+BFD01CA4 000BB443 BNE V1, V0, 0xBFD01CBE\r
+BFD01CA6 0C00000B SLL ZERO, T3, 1\r
+BFD01CA8 0C00 NOP\r
246: {\r
247: pxEventBits->uxEventBits &= ~uxBitsToWaitFor;\r
-BFD01CAA 0014FC5E LW V0, 20(S8)
-BFD01CAE 69A0 LW V1, 0(V0)
-BFD01CB0 0038FC5E LW V0, 56(S8)
-BFD01CB4 4412 NOT16 V0, V0
-BFD01CB6 449A AND16 V1, V0
-BFD01CB8 0014FC5E LW V0, 20(S8)
-BFD01CBC E9A0 SW V1, 0(V0)
+BFD01CAA 0014FC5E LW V0, 20(S8)\r
+BFD01CAE 69A0 LW V1, 0(V0)\r
+BFD01CB0 0038FC5E LW V0, 56(S8)\r
+BFD01CB4 4412 NOT16 V0, V0\r
+BFD01CB6 449A AND16 V1, V0\r
+BFD01CB8 0014FC5E LW V0, 20(S8)\r
+BFD01CBC E9A0 SW V1, 0(V0)\r
248: }\r
249: else\r
250: {\r
252: }\r
253: }\r
254: taskEXIT_CRITICAL();\r
-BFD01CBE 40AA77E8 JALS vTaskExitCritical
-BFD01CC0 0C0040AA BNEZC T2, 0xBFD034C4
-BFD01CC2 0C00 NOP
+BFD01CBE 40AA77E8 JALS vTaskExitCritical\r
+BFD01CC0 0C0040AA BNEZC T2, 0xBFD034C4\r
+BFD01CC2 0C00 NOP\r
255: \r
256: xTimeoutOccurred = pdTRUE;\r
-BFD01CC4 ED01 LI V0, 1
-BFD01CC6 0018F85E SW V0, 24(S8)
+BFD01CC4 ED01 LI V0, 1\r
+BFD01CC6 0018F85E SW V0, 24(S8)\r
257: }\r
258: else\r
259: {\r
263: /* Control bits might be set as the task had blocked should not be\r
264: returned. */\r
265: uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;\r
-BFD01CCA 0010FC5E LW V0, 16(S8)
-BFD01CCE B82C0042 EXT V0, V0, 0, 24
-BFD01CD0 F85EB82C SDC1 F1, -1954(T4)
-BFD01CD2 0010F85E SW V0, 16(S8)
+BFD01CCA 0010FC5E LW V0, 16(S8)\r
+BFD01CCE B82C0042 EXT V0, V0, 0, 24\r
+BFD01CD0 F85EB82C SDC1 F1, -1954(T4)\r
+BFD01CD2 0010F85E SW V0, 16(S8)\r
266: }\r
267: \r
268: traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred );\r
269: \r
270: return uxReturn;\r
-BFD01CD6 0010FC5E LW V0, 16(S8)
+BFD01CD6 0010FC5E LW V0, 16(S8)\r
271: }\r
-BFD01CDA 0FBE MOVE SP, S8
-BFD01CDC 4BEB LW RA, 44(SP)
-BFD01CDE 4BCA LW S8, 40(SP)
-BFD01CE0 4C19 ADDIU SP, SP, 48
-BFD01CE2 459F JR16 RA
-BFD01CE4 0C00 NOP
+BFD01CDA 0FBE MOVE SP, S8\r
+BFD01CDC 4BEB LW RA, 44(SP)\r
+BFD01CDE 4BCA LW S8, 40(SP)\r
+BFD01CE0 4C19 ADDIU SP, SP, 48\r
+BFD01CE2 459F JR16 RA\r
+BFD01CE4 0C00 NOP\r
272: /*-----------------------------------------------------------*/\r
273: \r
274: EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait )\r
275: {\r
-BFD01310 4FE5 ADDIU SP, SP, -56
-BFD01312 CBED SW RA, 52(SP)
-BFD01314 CBCC SW S8, 48(SP)
-BFD01316 0FDD MOVE S8, SP
-BFD01318 0038F89E SW A0, 56(S8)
-BFD0131C 003CF8BE SW A1, 60(S8)
-BFD01320 0040F8DE SW A2, 64(S8)
-BFD01324 0044F8FE SW A3, 68(S8)
+BFD01310 4FE5 ADDIU SP, SP, -56\r
+BFD01312 CBED SW RA, 52(SP)\r
+BFD01314 CBCC SW S8, 48(SP)\r
+BFD01316 0FDD MOVE S8, SP\r
+BFD01318 0038F89E SW A0, 56(S8)\r
+BFD0131C 003CF8BE SW A1, 60(S8)\r
+BFD01320 0040F8DE SW A2, 64(S8)\r
+BFD01324 0044F8FE SW A3, 68(S8)\r
276: EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;\r
-BFD01328 0038FC5E LW V0, 56(S8)
-BFD0132C 0018F85E SW V0, 24(S8)
+BFD01328 0038FC5E LW V0, 56(S8)\r
+BFD0132C 0018F85E SW V0, 24(S8)\r
277: EventBits_t uxReturn, uxControlBits = 0;\r
-BFD01330 0014F81E SW ZERO, 20(S8)
+BFD01330 0014F81E SW ZERO, 20(S8)\r
278: BaseType_t xWaitConditionMet, xAlreadyYielded;\r
279: BaseType_t xTimeoutOccurred = pdFALSE;\r
-BFD01334 001CF81E SW ZERO, 28(S8)
+BFD01334 001CF81E SW ZERO, 28(S8)\r
280: \r
281: /* Check the user is not attempting to wait on the bits used by the kernel\r
282: itself, and that at least one bit is being requested. */\r
283: configASSERT( xEventGroup );\r
-BFD01338 0038FC5E LW V0, 56(S8)
-BFD0133C 000940A2 BNEZC V0, 0xBFD01352
-BFD01340 BFD141A2 LUI V0, 0xBFD1
-BFD01342 3082BFD1 LDC1 F30, 12418(S1)
-BFD01344 9C0C3082 ADDIU A0, V0, -25588
-BFD01346 30A09C0C LWC1 F0, 12448(T4)
-BFD01348 011B30A0 ADDIU A1, ZERO, 283
-BFD0134C 4B7E77E8 JALS vAssertCalled
-BFD0134E 4B7E LW K1, 120(SP)
-BFD01350 0C00 NOP
+BFD01338 0038FC5E LW V0, 56(S8)\r
+BFD0133C 000940A2 BNEZC V0, 0xBFD01352\r
+BFD01340 BFD141A2 LUI V0, 0xBFD1\r
+BFD01342 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD01344 9C0C3082 ADDIU A0, V0, -25588\r
+BFD01346 30A09C0C LWC1 F0, 12448(T4)\r
+BFD01348 011B30A0 ADDIU A1, ZERO, 283\r
+BFD0134C 4B7E77E8 JALS vAssertCalled\r
+BFD0134E 4B7E LW K1, 120(SP)\r
+BFD01350 0C00 NOP\r
284: configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );\r
-BFD01352 003CFC7E LW V1, 60(S8)
-BFD01356 FF0041A2 LUI V0, 0xFF00
-BFD01358 4493FF00 LW T8, 17555(ZERO)
-BFD0135A 4493 AND16 V0, V1
-BFD0135C 000940E2 BEQZC V0, 0xBFD01372
-BFD01360 BFD141A2 LUI V0, 0xBFD1
-BFD01362 3082BFD1 LDC1 F30, 12418(S1)
-BFD01364 9C0C3082 ADDIU A0, V0, -25588
-BFD01366 30A09C0C LWC1 F0, 12448(T4)
-BFD01368 011C30A0 ADDIU A1, ZERO, 284
-BFD0136C 4B7E77E8 JALS vAssertCalled
-BFD0136E 4B7E LW K1, 120(SP)
-BFD01370 0C00 NOP
+BFD01352 003CFC7E LW V1, 60(S8)\r
+BFD01356 FF0041A2 LUI V0, 0xFF00\r
+BFD01358 4493FF00 LW T8, 17555(ZERO)\r
+BFD0135A 4493 AND16 V0, V1\r
+BFD0135C 000940E2 BEQZC V0, 0xBFD01372\r
+BFD01360 BFD141A2 LUI V0, 0xBFD1\r
+BFD01362 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD01364 9C0C3082 ADDIU A0, V0, -25588\r
+BFD01366 30A09C0C LWC1 F0, 12448(T4)\r
+BFD01368 011C30A0 ADDIU A1, ZERO, 284\r
+BFD0136C 4B7E77E8 JALS vAssertCalled\r
+BFD0136E 4B7E LW K1, 120(SP)\r
+BFD01370 0C00 NOP\r
285: configASSERT( uxBitsToWaitFor != 0 );\r
-BFD01372 003CFC5E LW V0, 60(S8)
-BFD01376 000940A2 BNEZC V0, 0xBFD0138C
-BFD0137A BFD141A2 LUI V0, 0xBFD1
-BFD0137C 3082BFD1 LDC1 F30, 12418(S1)
-BFD0137E 9C0C3082 ADDIU A0, V0, -25588
-BFD01380 30A09C0C LWC1 F0, 12448(T4)
-BFD01382 011D30A0 ADDIU A1, ZERO, 285
-BFD01386 4B7E77E8 JALS vAssertCalled
-BFD01388 4B7E LW K1, 120(SP)
-BFD0138A 0C00 NOP
+BFD01372 003CFC5E LW V0, 60(S8)\r
+BFD01376 000940A2 BNEZC V0, 0xBFD0138C\r
+BFD0137A BFD141A2 LUI V0, 0xBFD1\r
+BFD0137C 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD0137E 9C0C3082 ADDIU A0, V0, -25588\r
+BFD01380 30A09C0C LWC1 F0, 12448(T4)\r
+BFD01382 011D30A0 ADDIU A1, ZERO, 285\r
+BFD01386 4B7E77E8 JALS vAssertCalled\r
+BFD01388 4B7E LW K1, 120(SP)\r
+BFD0138A 0C00 NOP\r
286: #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\r
287: {\r
288: configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\r
-BFD0138C 4A8E77E8 JALS xTaskGetSchedulerState
-BFD0138E 4A8E LW S4, 56(SP)
-BFD01390 0C00 NOP
-BFD01392 000440A2 BNEZC V0, 0xBFD0139E
-BFD01396 0048FC5E LW V0, 72(S8)
-BFD0139A 000340A2 BNEZC V0, 0xBFD013A4
-BFD0139E ED01 LI V0, 1
-BFD013A0 CC02 B 0xBFD013A6
-BFD013A2 0C00 NOP
-BFD013A4 0C40 MOVE V0, ZERO
-BFD013A6 000940A2 BNEZC V0, 0xBFD013BC
-BFD013AA BFD141A2 LUI V0, 0xBFD1
-BFD013AC 3082BFD1 LDC1 F30, 12418(S1)
-BFD013AE 9C0C3082 ADDIU A0, V0, -25588
-BFD013B0 30A09C0C LWC1 F0, 12448(T4)
-BFD013B2 012030A0 ADDIU A1, ZERO, 288
-BFD013B6 4B7E77E8 JALS vAssertCalled
-BFD013B8 4B7E LW K1, 120(SP)
-BFD013BA 0C00 NOP
+BFD0138C 4A8E77E8 JALS xTaskGetSchedulerState\r
+BFD0138E 4A8E LW S4, 56(SP)\r
+BFD01390 0C00 NOP\r
+BFD01392 000440A2 BNEZC V0, 0xBFD0139E\r
+BFD01396 0048FC5E LW V0, 72(S8)\r
+BFD0139A 000340A2 BNEZC V0, 0xBFD013A4\r
+BFD0139E ED01 LI V0, 1\r
+BFD013A0 CC02 B 0xBFD013A6\r
+BFD013A2 0C00 NOP\r
+BFD013A4 0C40 MOVE V0, ZERO\r
+BFD013A6 000940A2 BNEZC V0, 0xBFD013BC\r
+BFD013AA BFD141A2 LUI V0, 0xBFD1\r
+BFD013AC 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD013AE 9C0C3082 ADDIU A0, V0, -25588\r
+BFD013B0 30A09C0C LWC1 F0, 12448(T4)\r
+BFD013B2 012030A0 ADDIU A1, ZERO, 288\r
+BFD013B6 4B7E77E8 JALS vAssertCalled\r
+BFD013B8 4B7E LW K1, 120(SP)\r
+BFD013BA 0C00 NOP\r
289: }\r
290: #endif\r
291: \r
292: vTaskSuspendAll();\r
-BFD013BC 4EF477E8 JALS vTaskSuspendAll
-BFD013BE 4EF4 ADDIU S7, S7, -6
-BFD013C0 0C00 NOP
+BFD013BC 4EF477E8 JALS vTaskSuspendAll\r
+BFD013BE 4EF4 ADDIU S7, S7, -6\r
+BFD013C0 0C00 NOP\r
293: {\r
294: const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits;\r
-BFD013C2 0018FC5E LW V0, 24(S8)
-BFD013C6 6920 LW V0, 0(V0)
-BFD013C8 0020F85E SW V0, 32(S8)
+BFD013C2 0018FC5E LW V0, 24(S8)\r
+BFD013C6 6920 LW V0, 0(V0)\r
+BFD013C8 0020F85E SW V0, 32(S8)\r
295: \r
296: /* Check to see if the wait condition is already met or not. */\r
297: xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits );\r
-BFD013CC 0020FC9E LW A0, 32(S8)
-BFD013D0 003CFCBE LW A1, 60(S8)
-BFD013D4 0044FCDE LW A2, 68(S8)
-BFD013D8 407A77E8 JALS prvTestWaitCondition
-BFD013DA 0C00407A BGEZAL K0, 0xBFD02BDE
-BFD013DC 0C00 NOP
-BFD013DE 0024F85E SW V0, 36(S8)
+BFD013CC 0020FC9E LW A0, 32(S8)\r
+BFD013D0 003CFCBE LW A1, 60(S8)\r
+BFD013D4 0044FCDE LW A2, 68(S8)\r
+BFD013D8 407A77E8 JALS prvTestWaitCondition\r
+BFD013DA 0C00407A BGEZAL K0, 0xBFD02BDE\r
+BFD013DC 0C00 NOP\r
+BFD013DE 0024F85E SW V0, 36(S8)\r
298: \r
299: if( xWaitConditionMet != pdFALSE )\r
-BFD013E2 0024FC5E LW V0, 36(S8)
-BFD013E6 001640E2 BEQZC V0, 0xBFD01416
+BFD013E2 0024FC5E LW V0, 36(S8)\r
+BFD013E6 001640E2 BEQZC V0, 0xBFD01416\r
300: {\r
301: /* The wait condition has already been met so there is no need to\r
302: block. */\r
303: uxReturn = uxCurrentEventBits;\r
-BFD013EA 0020FC5E LW V0, 32(S8)
-BFD013EE 0010F85E SW V0, 16(S8)
+BFD013EA 0020FC5E LW V0, 32(S8)\r
+BFD013EE 0010F85E SW V0, 16(S8)\r
304: xTicksToWait = ( TickType_t ) 0;\r
-BFD013F2 0048F81E SW ZERO, 72(S8)
+BFD013F2 0048F81E SW ZERO, 72(S8)\r
305: \r
306: /* Clear the wait bits if requested to do so. */\r
307: if( xClearOnExit != pdFALSE )\r
-BFD013F6 0040FC5E LW V0, 64(S8)
-BFD013FA 003D40E2 BEQZC V0, 0xBFD01478
+BFD013F6 0040FC5E LW V0, 64(S8)\r
+BFD013FA 003D40E2 BEQZC V0, 0xBFD01478\r
308: {\r
309: pxEventBits->uxEventBits &= ~uxBitsToWaitFor;\r
-BFD013FE 0018FC5E LW V0, 24(S8)
-BFD01402 69A0 LW V1, 0(V0)
-BFD01404 003CFC5E LW V0, 60(S8)
-BFD01408 4412 NOT16 V0, V0
-BFD0140A 449A AND16 V1, V0
-BFD0140C 0018FC5E LW V0, 24(S8)
-BFD01410 E9A0 SW V1, 0(V0)
-BFD01412 CC32 B 0xBFD01478
-BFD01414 0C00 NOP
+BFD013FE 0018FC5E LW V0, 24(S8)\r
+BFD01402 69A0 LW V1, 0(V0)\r
+BFD01404 003CFC5E LW V0, 60(S8)\r
+BFD01408 4412 NOT16 V0, V0\r
+BFD0140A 449A AND16 V1, V0\r
+BFD0140C 0018FC5E LW V0, 24(S8)\r
+BFD01410 E9A0 SW V1, 0(V0)\r
+BFD01412 CC32 B 0xBFD01478\r
+BFD01414 0C00 NOP\r
310: }\r
311: else\r
312: {\r
314: }\r
315: }\r
316: else if( xTicksToWait == ( TickType_t ) 0 )\r
-BFD01416 0048FC5E LW V0, 72(S8)
-BFD0141A 000640A2 BNEZC V0, 0xBFD0142A
+BFD01416 0048FC5E LW V0, 72(S8)\r
+BFD0141A 000640A2 BNEZC V0, 0xBFD0142A\r
317: {\r
318: /* The wait condition has not been met, but no block time was\r
319: specified, so just return the current value. */\r
320: uxReturn = uxCurrentEventBits;\r
-BFD0141E 0020FC5E LW V0, 32(S8)
-BFD01422 0010F85E SW V0, 16(S8)
-BFD01426 CC28 B 0xBFD01478
-BFD01428 0C00 NOP
+BFD0141E 0020FC5E LW V0, 32(S8)\r
+BFD01422 0010F85E SW V0, 16(S8)\r
+BFD01426 CC28 B 0xBFD01478\r
+BFD01428 0C00 NOP\r
321: }\r
322: else\r
323: {\r
326: this call to xEventGroupWaitBits() - for use when the event bits\r
327: unblock the task. */\r
328: if( xClearOnExit != pdFALSE )\r
-BFD0142A 0040FC5E LW V0, 64(S8)
-BFD0142E 000740E2 BEQZC V0, 0xBFD01440
+BFD0142A 0040FC5E LW V0, 64(S8)\r
+BFD0142E 000740E2 BEQZC V0, 0xBFD01440\r
329: {\r
330: uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT;\r
-BFD01432 0014FC7E LW V1, 20(S8)
-BFD01436 010041A2 LUI V0, 0x100
-BFD0143A 44D3 OR16 V0, V1
-BFD0143C 0014F85E SW V0, 20(S8)
+BFD01432 0014FC7E LW V1, 20(S8)\r
+BFD01436 010041A2 LUI V0, 0x100\r
+BFD0143A 44D3 OR16 V0, V1\r
+BFD0143C 0014F85E SW V0, 20(S8)\r
331: }\r
332: else\r
333: {\r
335: }\r
336: \r
337: if( xWaitForAllBits != pdFALSE )\r
-BFD01440 0044FC5E LW V0, 68(S8)
-BFD01444 000740E2 BEQZC V0, 0xBFD01456
+BFD01440 0044FC5E LW V0, 68(S8)\r
+BFD01444 000740E2 BEQZC V0, 0xBFD01456\r
338: {\r
339: uxControlBits |= eventWAIT_FOR_ALL_BITS;\r
-BFD01448 0014FC7E LW V1, 20(S8)
-BFD0144C 040041A2 LUI V0, 0x400
-BFD0144E 0400 ADDU S0, S0, S0
-BFD01450 44D3 OR16 V0, V1
-BFD01452 0014F85E SW V0, 20(S8)
+BFD01448 0014FC7E LW V1, 20(S8)\r
+BFD0144C 040041A2 LUI V0, 0x400\r
+BFD0144E 0400 ADDU S0, S0, S0\r
+BFD01450 44D3 OR16 V0, V1\r
+BFD01452 0014F85E SW V0, 20(S8)\r
340: }\r
341: else\r
342: {\r
347: task's event list item so the kernel knows when a match is\r
348: found. Then enter the blocked state. */\r
349: vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait );\r
-BFD01456 0018FC5E LW V0, 24(S8)
-BFD0145A 6DA2 ADDIU V1, V0, 4
-BFD0145C 003CFC9E LW A0, 60(S8)
-BFD01460 0014FC5E LW V0, 20(S8)
-BFD01464 44D4 OR16 V0, A0
-BFD01466 0C83 MOVE A0, V1
-BFD01468 0CA2 MOVE A1, V0
-BFD0146A 0048FCDE LW A2, 72(S8)
-BFD0146E 248277E8 JALS vTaskPlaceOnUnorderedEventList
-BFD01470 2482 SLL S1, S0, 1
-BFD01472 0C00 NOP
+BFD01456 0018FC5E LW V0, 24(S8)\r
+BFD0145A 6DA2 ADDIU V1, V0, 4\r
+BFD0145C 003CFC9E LW A0, 60(S8)\r
+BFD01460 0014FC5E LW V0, 20(S8)\r
+BFD01464 44D4 OR16 V0, A0\r
+BFD01466 0C83 MOVE A0, V1\r
+BFD01468 0CA2 MOVE A1, V0\r
+BFD0146A 0048FCDE LW A2, 72(S8)\r
+BFD0146E 248277E8 JALS vTaskPlaceOnUnorderedEventList\r
+BFD01470 2482 SLL S1, S0, 1\r
+BFD01472 0C00 NOP\r
350: \r
351: /* This is obsolete as it will get set after the task unblocks, but\r
352: some compilers mistakenly generate a warning about the variable\r
353: being returned without being set if it is not done. */\r
354: uxReturn = 0;\r
-BFD01474 0010F81E SW ZERO, 16(S8)
+BFD01474 0010F81E SW ZERO, 16(S8)\r
355: \r
356: traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor );\r
357: }\r
358: }\r
359: xAlreadyYielded = xTaskResumeAll();\r
-BFD01478 158E77E8 JALS xTaskResumeAll
-BFD0147A 0C00158E LBU T4, 3072(T6)
-BFD0147C 0C00 NOP
-BFD0147E 0028F85E SW V0, 40(S8)
+BFD01478 158E77E8 JALS xTaskResumeAll\r
+BFD0147A 0C00158E LBU T4, 3072(T6)\r
+BFD0147C 0C00 NOP\r
+BFD0147E 0028F85E SW V0, 40(S8)\r
360: \r
361: if( xTicksToWait != ( TickType_t ) 0 )\r
-BFD01482 0048FC5E LW V0, 72(S8)
-BFD01486 004C40E2 BEQZC V0, 0xBFD01522
+BFD01482 0048FC5E LW V0, 72(S8)\r
+BFD01486 004C40E2 BEQZC V0, 0xBFD01522\r
362: {\r
363: if( xAlreadyYielded == pdFALSE )\r
-BFD0148A 0028FC5E LW V0, 40(S8)
-BFD0148E 001040A2 BNEZC V0, 0xBFD014B2
+BFD0148A 0028FC5E LW V0, 40(S8)\r
+BFD0148E 001040A2 BNEZC V0, 0xBFD014B2\r
364: {\r
365: portYIELD_WITHIN_API();\r
-BFD01492 4DE677E8 JALS ulPortGetCP0Cause
-BFD01494 4DE6 ADDIU T7, T7, 3
-BFD01496 0C00 NOP
-BFD01498 002CF85E SW V0, 44(S8)
-BFD0149C 002CFC5E LW V0, 44(S8)
-BFD014A0 01005042 ORI V0, V0, 256
-BFD014A4 002CF85E SW V0, 44(S8)
-BFD014A8 002CFC9E LW A0, 44(S8)
-BFD014AC 4DF677E8 JALS vPortSetCP0Cause
-BFD014AE 4DF6 ADDIU T7, T7, -5
-BFD014B0 0C00 NOP
+BFD01492 4DE677E8 JALS ulPortGetCP0Cause\r
+BFD01494 4DE6 ADDIU T7, T7, 3\r
+BFD01496 0C00 NOP\r
+BFD01498 002CF85E SW V0, 44(S8)\r
+BFD0149C 002CFC5E LW V0, 44(S8)\r
+BFD014A0 01005042 ORI V0, V0, 256\r
+BFD014A4 002CF85E SW V0, 44(S8)\r
+BFD014A8 002CFC9E LW A0, 44(S8)\r
+BFD014AC 4DF677E8 JALS vPortSetCP0Cause\r
+BFD014AE 4DF6 ADDIU T7, T7, -5\r
+BFD014B0 0C00 NOP\r
366: }\r
367: else\r
368: {\r
374: the required bits were set they will have been stored in the task's\r
375: event list item, and they should now be retrieved then cleared. */\r
376: uxReturn = uxTaskResetEventItemValue();\r
-BFD014B2 4C8677E8 JALS uxTaskResetEventItemValue
-BFD014B4 4C86 ADDIU A0, A0, 3
-BFD014B6 0C00 NOP
-BFD014B8 0010F85E SW V0, 16(S8)
+BFD014B2 4C8677E8 JALS uxTaskResetEventItemValue\r
+BFD014B4 4C86 ADDIU A0, A0, 3\r
+BFD014B6 0C00 NOP\r
+BFD014B8 0010F85E SW V0, 16(S8)\r
377: \r
378: if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )\r
-BFD014BC 0010FC7E LW V1, 16(S8)
-BFD014C0 020041A2 LUI V0, 0x200
-BFD014C4 4493 AND16 V0, V1
-BFD014C6 002640A2 BNEZC V0, 0xBFD01516
+BFD014BC 0010FC7E LW V1, 16(S8)\r
+BFD014C0 020041A2 LUI V0, 0x200\r
+BFD014C4 4493 AND16 V0, V1\r
+BFD014C6 002640A2 BNEZC V0, 0xBFD01516\r
379: {\r
380: taskENTER_CRITICAL();\r
-BFD014CA 33B877E8 JALS vTaskEnterCritical
-BFD014CC 0C0033B8 ADDIU SP, T8, 3072
-BFD014CE 0C00 NOP
+BFD014CA 33B877E8 JALS vTaskEnterCritical\r
+BFD014CC 0C0033B8 ADDIU SP, T8, 3072\r
+BFD014CE 0C00 NOP\r
381: {\r
382: /* The task timed out, just return the current event bit value. */\r
383: uxReturn = pxEventBits->uxEventBits;\r
-BFD014D0 0018FC5E LW V0, 24(S8)
-BFD014D4 6920 LW V0, 0(V0)
-BFD014D6 0010F85E SW V0, 16(S8)
+BFD014D0 0018FC5E LW V0, 24(S8)\r
+BFD014D4 6920 LW V0, 0(V0)\r
+BFD014D6 0010F85E SW V0, 16(S8)\r
384: \r
385: /* It is possible that the event bits were updated between this\r
386: task leaving the Blocked state and running again. */\r
387: if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE )\r
-BFD014DA 0010FC9E LW A0, 16(S8)
-BFD014DE 003CFCBE LW A1, 60(S8)
-BFD014E2 0044FCDE LW A2, 68(S8)
-BFD014E6 407A77E8 JALS prvTestWaitCondition
-BFD014E8 0C00407A BGEZAL K0, 0xBFD02CEC
-BFD014EA 0C00 NOP
-BFD014EC 000E40E2 BEQZC V0, 0xBFD0150C
+BFD014DA 0010FC9E LW A0, 16(S8)\r
+BFD014DE 003CFCBE LW A1, 60(S8)\r
+BFD014E2 0044FCDE LW A2, 68(S8)\r
+BFD014E6 407A77E8 JALS prvTestWaitCondition\r
+BFD014E8 0C00407A BGEZAL K0, 0xBFD02CEC\r
+BFD014EA 0C00 NOP\r
+BFD014EC 000E40E2 BEQZC V0, 0xBFD0150C\r
388: {\r
389: if( xClearOnExit != pdFALSE )\r
-BFD014F0 0040FC5E LW V0, 64(S8)
-BFD014F4 000A40E2 BEQZC V0, 0xBFD0150C
+BFD014F0 0040FC5E LW V0, 64(S8)\r
+BFD014F4 000A40E2 BEQZC V0, 0xBFD0150C\r
390: {\r
391: pxEventBits->uxEventBits &= ~uxBitsToWaitFor;\r
-BFD014F8 0018FC5E LW V0, 24(S8)
-BFD014FC 69A0 LW V1, 0(V0)
-BFD014FE 003CFC5E LW V0, 60(S8)
-BFD01502 4412 NOT16 V0, V0
-BFD01504 449A AND16 V1, V0
-BFD01506 0018FC5E LW V0, 24(S8)
-BFD0150A E9A0 SW V1, 0(V0)
+BFD014F8 0018FC5E LW V0, 24(S8)\r
+BFD014FC 69A0 LW V1, 0(V0)\r
+BFD014FE 003CFC5E LW V0, 60(S8)\r
+BFD01502 4412 NOT16 V0, V0\r
+BFD01504 449A AND16 V1, V0\r
+BFD01506 0018FC5E LW V0, 24(S8)\r
+BFD0150A E9A0 SW V1, 0(V0)\r
392: }\r
393: else\r
394: {\r
401: }\r
402: }\r
403: taskEXIT_CRITICAL();\r
-BFD0150C 40AA77E8 JALS vTaskExitCritical
-BFD0150E 0C0040AA BNEZC T2, 0xBFD02D12
-BFD01510 0C00 NOP
+BFD0150C 40AA77E8 JALS vTaskExitCritical\r
+BFD0150E 0C0040AA BNEZC T2, 0xBFD02D12\r
+BFD01510 0C00 NOP\r
404: \r
405: /* Prevent compiler warnings when trace macros are not used. */\r
406: xTimeoutOccurred = pdFALSE;\r
-BFD01512 001CF81E SW ZERO, 28(S8)
+BFD01512 001CF81E SW ZERO, 28(S8)\r
407: }\r
408: else\r
409: {\r
412: \r
413: /* The task blocked so control bits may have been set. */\r
414: uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;\r
-BFD01516 0010FC5E LW V0, 16(S8)
-BFD0151A B82C0042 EXT V0, V0, 0, 24
-BFD0151C F85EB82C SDC1 F1, -1954(T4)
-BFD0151E 0010F85E SW V0, 16(S8)
+BFD01516 0010FC5E LW V0, 16(S8)\r
+BFD0151A B82C0042 EXT V0, V0, 0, 24\r
+BFD0151C F85EB82C SDC1 F1, -1954(T4)\r
+BFD0151E 0010F85E SW V0, 16(S8)\r
415: }\r
416: traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred );\r
417: \r
418: return uxReturn;\r
-BFD01522 0010FC5E LW V0, 16(S8)
+BFD01522 0010FC5E LW V0, 16(S8)\r
419: }\r
-BFD01526 0FBE MOVE SP, S8
-BFD01528 4BED LW RA, 52(SP)
-BFD0152A 4BCC LW S8, 48(SP)
-BFD0152C 4C1D ADDIU SP, SP, 56
-BFD0152E 459F JR16 RA
-BFD01530 0C00 NOP
+BFD01526 0FBE MOVE SP, S8\r
+BFD01528 4BED LW RA, 52(SP)\r
+BFD0152A 4BCC LW S8, 48(SP)\r
+BFD0152C 4C1D ADDIU SP, SP, 56\r
+BFD0152E 459F JR16 RA\r
+BFD01530 0C00 NOP\r
420: /*-----------------------------------------------------------*/\r
421: \r
422: EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )\r
423: {\r
-BFD06A44 4FF1 ADDIU SP, SP, -32
-BFD06A46 CBE7 SW RA, 28(SP)
-BFD06A48 CBC6 SW S8, 24(SP)
-BFD06A4A 0FDD MOVE S8, SP
-BFD06A4C 0020F89E SW A0, 32(S8)
-BFD06A50 0024F8BE SW A1, 36(S8)
+BFD06A44 4FF1 ADDIU SP, SP, -32\r
+BFD06A46 CBE7 SW RA, 28(SP)\r
+BFD06A48 CBC6 SW S8, 24(SP)\r
+BFD06A4A 0FDD MOVE S8, SP\r
+BFD06A4C 0020F89E SW A0, 32(S8)\r
+BFD06A50 0024F8BE SW A1, 36(S8)\r
424: EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;\r
-BFD06A54 0020FC5E LW V0, 32(S8)
-BFD06A58 0010F85E SW V0, 16(S8)
+BFD06A54 0020FC5E LW V0, 32(S8)\r
+BFD06A58 0010F85E SW V0, 16(S8)\r
425: EventBits_t uxReturn;\r
426: \r
427: /* Check the user is not attempting to clear the bits used by the kernel\r
428: itself. */\r
429: configASSERT( xEventGroup );\r
-BFD06A5C 0020FC5E LW V0, 32(S8)
-BFD06A60 000940A2 BNEZC V0, 0xBFD06A76
-BFD06A64 BFD141A2 LUI V0, 0xBFD1
-BFD06A66 3082BFD1 LDC1 F30, 12418(S1)
-BFD06A68 9C0C3082 ADDIU A0, V0, -25588
-BFD06A6A 30A09C0C LWC1 F0, 12448(T4)
-BFD06A6C 01AD30A0 ADDIU A1, ZERO, 429
-BFD06A70 4B7E77E8 JALS vAssertCalled
-BFD06A72 4B7E LW K1, 120(SP)
-BFD06A74 0C00 NOP
+BFD06A5C 0020FC5E LW V0, 32(S8)\r
+BFD06A60 000940A2 BNEZC V0, 0xBFD06A76\r
+BFD06A64 BFD141A2 LUI V0, 0xBFD1\r
+BFD06A66 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD06A68 9C0C3082 ADDIU A0, V0, -25588\r
+BFD06A6A 30A09C0C LWC1 F0, 12448(T4)\r
+BFD06A6C 01AD30A0 ADDIU A1, ZERO, 429\r
+BFD06A70 4B7E77E8 JALS vAssertCalled\r
+BFD06A72 4B7E LW K1, 120(SP)\r
+BFD06A74 0C00 NOP\r
430: configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 );\r
-BFD06A76 0024FC7E LW V1, 36(S8)
-BFD06A7A FF0041A2 LUI V0, 0xFF00
-BFD06A7C 4493FF00 LW T8, 17555(ZERO)
-BFD06A7E 4493 AND16 V0, V1
-BFD06A80 000940E2 BEQZC V0, 0xBFD06A96
-BFD06A84 BFD141A2 LUI V0, 0xBFD1
-BFD06A86 3082BFD1 LDC1 F30, 12418(S1)
-BFD06A88 9C0C3082 ADDIU A0, V0, -25588
-BFD06A8A 30A09C0C LWC1 F0, 12448(T4)
-BFD06A8C 01AE30A0 ADDIU A1, ZERO, 430
-BFD06A90 4B7E77E8 JALS vAssertCalled
-BFD06A92 4B7E LW K1, 120(SP)
-BFD06A94 0C00 NOP
+BFD06A76 0024FC7E LW V1, 36(S8)\r
+BFD06A7A FF0041A2 LUI V0, 0xFF00\r
+BFD06A7C 4493FF00 LW T8, 17555(ZERO)\r
+BFD06A7E 4493 AND16 V0, V1\r
+BFD06A80 000940E2 BEQZC V0, 0xBFD06A96\r
+BFD06A84 BFD141A2 LUI V0, 0xBFD1\r
+BFD06A86 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD06A88 9C0C3082 ADDIU A0, V0, -25588\r
+BFD06A8A 30A09C0C LWC1 F0, 12448(T4)\r
+BFD06A8C 01AE30A0 ADDIU A1, ZERO, 430\r
+BFD06A90 4B7E77E8 JALS vAssertCalled\r
+BFD06A92 4B7E LW K1, 120(SP)\r
+BFD06A94 0C00 NOP\r
431: \r
432: taskENTER_CRITICAL();\r
-BFD06A96 33B877E8 JALS vTaskEnterCritical
-BFD06A98 0C0033B8 ADDIU SP, T8, 3072
-BFD06A9A 0C00 NOP
+BFD06A96 33B877E8 JALS vTaskEnterCritical\r
+BFD06A98 0C0033B8 ADDIU SP, T8, 3072\r
+BFD06A9A 0C00 NOP\r
433: {\r
434: traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear );\r
435: \r
436: /* The value returned is the event group value prior to the bits being\r
437: cleared. */\r
438: uxReturn = pxEventBits->uxEventBits;\r
-BFD06A9C 0010FC5E LW V0, 16(S8)
-BFD06AA0 6920 LW V0, 0(V0)
-BFD06AA2 0014F85E SW V0, 20(S8)
+BFD06A9C 0010FC5E LW V0, 16(S8)\r
+BFD06AA0 6920 LW V0, 0(V0)\r
+BFD06AA2 0014F85E SW V0, 20(S8)\r
439: \r
440: /* Clear the bits. */\r
441: pxEventBits->uxEventBits &= ~uxBitsToClear;\r
-BFD06AA6 0010FC5E LW V0, 16(S8)
-BFD06AAA 69A0 LW V1, 0(V0)
-BFD06AAC 0024FC5E LW V0, 36(S8)
-BFD06AB0 4412 NOT16 V0, V0
-BFD06AB2 449A AND16 V1, V0
-BFD06AB4 0010FC5E LW V0, 16(S8)
-BFD06AB8 E9A0 SW V1, 0(V0)
+BFD06AA6 0010FC5E LW V0, 16(S8)\r
+BFD06AAA 69A0 LW V1, 0(V0)\r
+BFD06AAC 0024FC5E LW V0, 36(S8)\r
+BFD06AB0 4412 NOT16 V0, V0\r
+BFD06AB2 449A AND16 V1, V0\r
+BFD06AB4 0010FC5E LW V0, 16(S8)\r
+BFD06AB8 E9A0 SW V1, 0(V0)\r
442: }\r
443: taskEXIT_CRITICAL();\r
-BFD06ABA 40AA77E8 JALS vTaskExitCritical
-BFD06ABC 0C0040AA BNEZC T2, 0xBFD082C0
-BFD06ABE 0C00 NOP
+BFD06ABA 40AA77E8 JALS vTaskExitCritical\r
+BFD06ABC 0C0040AA BNEZC T2, 0xBFD082C0\r
+BFD06ABE 0C00 NOP\r
444: \r
445: return uxReturn;\r
-BFD06AC0 0014FC5E LW V0, 20(S8)
+BFD06AC0 0014FC5E LW V0, 20(S8)\r
446: }\r
-BFD06AC4 0FBE MOVE SP, S8
-BFD06AC6 4BE7 LW RA, 28(SP)
-BFD06AC8 4BC6 LW S8, 24(SP)
-BFD06ACA 4C11 ADDIU SP, SP, 32
-BFD06ACC 459F JR16 RA
-BFD06ACE 0C00 NOP
+BFD06AC4 0FBE MOVE SP, S8\r
+BFD06AC6 4BE7 LW RA, 28(SP)\r
+BFD06AC8 4BC6 LW S8, 24(SP)\r
+BFD06ACA 4C11 ADDIU SP, SP, 32\r
+BFD06ACC 459F JR16 RA\r
+BFD06ACE 0C00 NOP\r
447: /*-----------------------------------------------------------*/\r
448: \r
449: #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )\r
463: \r
464: EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )\r
465: {\r
-BFD09144 4FED ADDIU SP, SP, -40
-BFD09146 CBE9 SW RA, 36(SP)
-BFD09148 CBC8 SW S8, 32(SP)
-BFD0914A 0FDD MOVE S8, SP
-BFD0914C 0028F89E SW A0, 40(S8)
+BFD09144 4FED ADDIU SP, SP, -40\r
+BFD09146 CBE9 SW RA, 36(SP)\r
+BFD09148 CBC8 SW S8, 32(SP)\r
+BFD0914A 0FDD MOVE S8, SP\r
+BFD0914C 0028F89E SW A0, 40(S8)\r
466: UBaseType_t uxSavedInterruptStatus;\r
467: EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;\r
-BFD09150 0028FC5E LW V0, 40(S8)
-BFD09154 0010F85E SW V0, 16(S8)
+BFD09150 0028FC5E LW V0, 40(S8)\r
+BFD09154 0010F85E SW V0, 16(S8)\r
468: EventBits_t uxReturn;\r
469: \r
470: uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r
-BFD09158 475E77E8 JALS uxPortSetInterruptMaskFromISR
-BFD0915C 0C00 NOP
-BFD0915E 0014F85E SW V0, 20(S8)
+BFD09158 475E77E8 JALS uxPortSetInterruptMaskFromISR\r
+BFD0915C 0C00 NOP\r
+BFD0915E 0014F85E SW V0, 20(S8)\r
471: {\r
472: uxReturn = pxEventBits->uxEventBits;\r
-BFD09162 0010FC5E LW V0, 16(S8)
-BFD09166 6920 LW V0, 0(V0)
-BFD09168 0018F85E SW V0, 24(S8)
+BFD09162 0010FC5E LW V0, 16(S8)\r
+BFD09166 6920 LW V0, 0(V0)\r
+BFD09168 0018F85E SW V0, 24(S8)\r
473: }\r
474: portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r
-BFD0916C 0014FC9E LW A0, 20(S8)
-BFD09170 4D5E77E8 JALS vPortClearInterruptMaskFromISR
-BFD09172 4D5E ADDIU T2, T2, -1
-BFD09174 0C00 NOP
+BFD0916C 0014FC9E LW A0, 20(S8)\r
+BFD09170 4D5E77E8 JALS vPortClearInterruptMaskFromISR\r
+BFD09172 4D5E ADDIU T2, T2, -1\r
+BFD09174 0C00 NOP\r
475: \r
476: return uxReturn;\r
-BFD09176 0018FC5E LW V0, 24(S8)
+BFD09176 0018FC5E LW V0, 24(S8)\r
477: }\r
-BFD0917A 0FBE MOVE SP, S8
-BFD0917C 4BE9 LW RA, 36(SP)
-BFD0917E 4BC8 LW S8, 32(SP)
-BFD09180 4C15 ADDIU SP, SP, 40
-BFD09182 459F JR16 RA
-BFD09184 0C00 NOP
+BFD0917A 0FBE MOVE SP, S8\r
+BFD0917C 4BE9 LW RA, 36(SP)\r
+BFD0917E 4BC8 LW S8, 32(SP)\r
+BFD09180 4C15 ADDIU SP, SP, 40\r
+BFD09182 459F JR16 RA\r
+BFD09184 0C00 NOP\r
478: /*-----------------------------------------------------------*/\r
479: \r
480: EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet )\r
481: {\r
-BFD02568 4FE1 ADDIU SP, SP, -64
-BFD0256A CBEF SW RA, 60(SP)
-BFD0256C CBCE SW S8, 56(SP)
-BFD0256E 0FDD MOVE S8, SP
-BFD02570 0040F89E SW A0, 64(S8)
-BFD02574 0044F8BE SW A1, 68(S8)
+BFD02568 4FE1 ADDIU SP, SP, -64\r
+BFD0256A CBEF SW RA, 60(SP)\r
+BFD0256C CBCE SW S8, 56(SP)\r
+BFD0256E 0FDD MOVE S8, SP\r
+BFD02570 0040F89E SW A0, 64(S8)\r
+BFD02574 0044F8BE SW A1, 68(S8)\r
482: ListItem_t *pxListItem, *pxNext;\r
483: ListItem_t const *pxListEnd;\r
484: List_t *pxList;\r
485: EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits;\r
-BFD02578 0014F81E SW ZERO, 20(S8)
+BFD02578 0014F81E SW ZERO, 20(S8)\r
486: EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;\r
-BFD0257C 0040FC5E LW V0, 64(S8)
-BFD02580 001CF85E SW V0, 28(S8)
+BFD0257C 0040FC5E LW V0, 64(S8)\r
+BFD02580 001CF85E SW V0, 28(S8)\r
487: BaseType_t xMatchFound = pdFALSE;\r
-BFD02584 0018F81E SW ZERO, 24(S8)
+BFD02584 0018F81E SW ZERO, 24(S8)\r
488: \r
489: /* Check the user is not attempting to set the bits used by the kernel\r
490: itself. */\r
491: configASSERT( xEventGroup );\r
-BFD02588 0040FC5E LW V0, 64(S8)
-BFD0258C 000940A2 BNEZC V0, 0xBFD025A2
-BFD02590 BFD141A2 LUI V0, 0xBFD1
-BFD02592 3082BFD1 LDC1 F30, 12418(S1)
-BFD02594 9C0C3082 ADDIU A0, V0, -25588
-BFD02596 30A09C0C LWC1 F0, 12448(T4)
-BFD02598 01EB30A0 ADDIU A1, ZERO, 491
-BFD0259C 4B7E77E8 JALS vAssertCalled
-BFD0259E 4B7E LW K1, 120(SP)
-BFD025A0 0C00 NOP
+BFD02588 0040FC5E LW V0, 64(S8)\r
+BFD0258C 000940A2 BNEZC V0, 0xBFD025A2\r
+BFD02590 BFD141A2 LUI V0, 0xBFD1\r
+BFD02592 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD02594 9C0C3082 ADDIU A0, V0, -25588\r
+BFD02596 30A09C0C LWC1 F0, 12448(T4)\r
+BFD02598 01EB30A0 ADDIU A1, ZERO, 491\r
+BFD0259C 4B7E77E8 JALS vAssertCalled\r
+BFD0259E 4B7E LW K1, 120(SP)\r
+BFD025A0 0C00 NOP\r
492: configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 );\r
-BFD025A2 0044FC7E LW V1, 68(S8)
-BFD025A6 FF0041A2 LUI V0, 0xFF00
-BFD025A8 4493FF00 LW T8, 17555(ZERO)
-BFD025AA 4493 AND16 V0, V1
-BFD025AC 000940E2 BEQZC V0, 0xBFD025C2
-BFD025B0 BFD141A2 LUI V0, 0xBFD1
-BFD025B2 3082BFD1 LDC1 F30, 12418(S1)
-BFD025B4 9C0C3082 ADDIU A0, V0, -25588
-BFD025B6 30A09C0C LWC1 F0, 12448(T4)
-BFD025B8 01EC30A0 ADDIU A1, ZERO, 492
-BFD025BC 4B7E77E8 JALS vAssertCalled
-BFD025BE 4B7E LW K1, 120(SP)
-BFD025C0 0C00 NOP
+BFD025A2 0044FC7E LW V1, 68(S8)\r
+BFD025A6 FF0041A2 LUI V0, 0xFF00\r
+BFD025A8 4493FF00 LW T8, 17555(ZERO)\r
+BFD025AA 4493 AND16 V0, V1\r
+BFD025AC 000940E2 BEQZC V0, 0xBFD025C2\r
+BFD025B0 BFD141A2 LUI V0, 0xBFD1\r
+BFD025B2 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD025B4 9C0C3082 ADDIU A0, V0, -25588\r
+BFD025B6 30A09C0C LWC1 F0, 12448(T4)\r
+BFD025B8 01EC30A0 ADDIU A1, ZERO, 492\r
+BFD025BC 4B7E77E8 JALS vAssertCalled\r
+BFD025BE 4B7E LW K1, 120(SP)\r
+BFD025C0 0C00 NOP\r
493: \r
494: pxList = &( pxEventBits->xTasksWaitingForBits );\r
-BFD025C2 001CFC5E LW V0, 28(S8)
-BFD025C6 6D22 ADDIU V0, V0, 4
-BFD025C8 0020F85E SW V0, 32(S8)
+BFD025C2 001CFC5E LW V0, 28(S8)\r
+BFD025C6 6D22 ADDIU V0, V0, 4\r
+BFD025C8 0020F85E SW V0, 32(S8)\r
495: pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */\r
-BFD025CC 0020FC5E LW V0, 32(S8)
-BFD025D0 6D24 ADDIU V0, V0, 8
-BFD025D2 0024F85E SW V0, 36(S8)
+BFD025CC 0020FC5E LW V0, 32(S8)\r
+BFD025D0 6D24 ADDIU V0, V0, 8\r
+BFD025D2 0024F85E SW V0, 36(S8)\r
496: vTaskSuspendAll();\r
-BFD025D6 4EF477E8 JALS vTaskSuspendAll
-BFD025D8 4EF4 ADDIU S7, S7, -6
-BFD025DA 0C00 NOP
+BFD025D6 4EF477E8 JALS vTaskSuspendAll\r
+BFD025D8 4EF4 ADDIU S7, S7, -6\r
+BFD025DA 0C00 NOP\r
497: {\r
498: traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet );\r
499: \r
500: pxListItem = listGET_HEAD_ENTRY( pxList );\r
-BFD025DC 0020FC5E LW V0, 32(S8)
-BFD025E0 6923 LW V0, 12(V0)
-BFD025E2 0010F85E SW V0, 16(S8)
+BFD025DC 0020FC5E LW V0, 32(S8)\r
+BFD025E0 6923 LW V0, 12(V0)\r
+BFD025E2 0010F85E SW V0, 16(S8)\r
501: \r
502: /* Set the bits. */\r
503: pxEventBits->uxEventBits |= uxBitsToSet;\r
-BFD025E6 001CFC5E LW V0, 28(S8)
-BFD025EA 69A0 LW V1, 0(V0)
-BFD025EC 0044FC5E LW V0, 68(S8)
-BFD025F0 44DA OR16 V1, V0
-BFD025F2 001CFC5E LW V0, 28(S8)
-BFD025F6 E9A0 SW V1, 0(V0)
+BFD025E6 001CFC5E LW V0, 28(S8)\r
+BFD025EA 69A0 LW V1, 0(V0)\r
+BFD025EC 0044FC5E LW V0, 68(S8)\r
+BFD025F0 44DA OR16 V1, V0\r
+BFD025F2 001CFC5E LW V0, 28(S8)\r
+BFD025F6 E9A0 SW V1, 0(V0)\r
504: \r
505: /* See if the new bit value should unblock any tasks. */\r
506: while( pxListItem != pxListEnd )\r
-BFD025F8 CC5E B 0xBFD026B6
-BFD025FA 0C00 NOP
-BFD026B6 0010FC7E LW V1, 16(S8)
-BFD026BA 0024FC5E LW V0, 36(S8)
-BFD026BE FF9DB443 BNE V1, V0, 0xBFD025FC
-BFD026C0 0C00FF9D LW GP, 3072(SP)
-BFD026C2 0C00 NOP
+BFD025F8 CC5E B 0xBFD026B6\r
+BFD025FA 0C00 NOP\r
+BFD026B6 0010FC7E LW V1, 16(S8)\r
+BFD026BA 0024FC5E LW V0, 36(S8)\r
+BFD026BE FF9DB443 BNE V1, V0, 0xBFD025FC\r
+BFD026C0 0C00FF9D LW GP, 3072(SP)\r
+BFD026C2 0C00 NOP\r
507: {\r
508: pxNext = listGET_NEXT( pxListItem );\r
-BFD025FC 0010FC5E LW V0, 16(S8)
-BFD02600 6921 LW V0, 4(V0)
-BFD02602 0028F85E SW V0, 40(S8)
+BFD025FC 0010FC5E LW V0, 16(S8)\r
+BFD02600 6921 LW V0, 4(V0)\r
+BFD02602 0028F85E SW V0, 40(S8)\r
509: uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem );\r
-BFD02606 0010FC5E LW V0, 16(S8)
-BFD0260A 6920 LW V0, 0(V0)
-BFD0260C 002CF85E SW V0, 44(S8)
+BFD02606 0010FC5E LW V0, 16(S8)\r
+BFD0260A 6920 LW V0, 0(V0)\r
+BFD0260C 002CF85E SW V0, 44(S8)\r
510: xMatchFound = pdFALSE;\r
-BFD02610 0018F81E SW ZERO, 24(S8)
+BFD02610 0018F81E SW ZERO, 24(S8)\r
511: \r
512: /* Split the bits waited for from the control bits. */\r
513: uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES;\r
-BFD02614 002CFC7E LW V1, 44(S8)
-BFD02618 FF0041A2 LUI V0, 0xFF00
-BFD0261A 4493FF00 LW T8, 17555(ZERO)
-BFD0261C 4493 AND16 V0, V1
-BFD0261E 0030F85E SW V0, 48(S8)
+BFD02614 002CFC7E LW V1, 44(S8)\r
+BFD02618 FF0041A2 LUI V0, 0xFF00\r
+BFD0261A 4493FF00 LW T8, 17555(ZERO)\r
+BFD0261C 4493 AND16 V0, V1\r
+BFD0261E 0030F85E SW V0, 48(S8)\r
514: uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES;\r
-BFD02622 002CFC5E LW V0, 44(S8)
-BFD02626 B82C0042 EXT V0, V0, 0, 24
-BFD02628 F85EB82C SDC1 F1, -1954(T4)
-BFD0262A 002CF85E SW V0, 44(S8)
+BFD02622 002CFC5E LW V0, 44(S8)\r
+BFD02626 B82C0042 EXT V0, V0, 0, 24\r
+BFD02628 F85EB82C SDC1 F1, -1954(T4)\r
+BFD0262A 002CF85E SW V0, 44(S8)\r
515: \r
516: if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 )\r
-BFD0262E 0030FC7E LW V1, 48(S8)
-BFD02632 040041A2 LUI V0, 0x400
-BFD02634 0400 ADDU S0, S0, S0
-BFD02636 4493 AND16 V0, V1
-BFD02638 000D40A2 BNEZC V0, 0xBFD02656
+BFD0262E 0030FC7E LW V1, 48(S8)\r
+BFD02632 040041A2 LUI V0, 0x400\r
+BFD02634 0400 ADDU S0, S0, S0\r
+BFD02636 4493 AND16 V0, V1\r
+BFD02638 000D40A2 BNEZC V0, 0xBFD02656\r
517: {\r
518: /* Just looking for single bit being set. */\r
519: if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 )\r
-BFD0263C 001CFC5E LW V0, 28(S8)
-BFD02640 69A0 LW V1, 0(V0)
-BFD02642 002CFC5E LW V0, 44(S8)
-BFD02646 4493 AND16 V0, V1
-BFD02648 001340E2 BEQZC V0, 0xBFD02672
+BFD0263C 001CFC5E LW V0, 28(S8)\r
+BFD02640 69A0 LW V1, 0(V0)\r
+BFD02642 002CFC5E LW V0, 44(S8)\r
+BFD02646 4493 AND16 V0, V1\r
+BFD02648 001340E2 BEQZC V0, 0xBFD02672\r
520: {\r
521: xMatchFound = pdTRUE;\r
-BFD0264C ED01 LI V0, 1
-BFD0264E 0018F85E SW V0, 24(S8)
-BFD02652 CC0F B 0xBFD02672
-BFD02654 0C00 NOP
+BFD0264C ED01 LI V0, 1\r
+BFD0264E 0018F85E SW V0, 24(S8)\r
+BFD02652 CC0F B 0xBFD02672\r
+BFD02654 0C00 NOP\r
522: }\r
523: else\r
524: {\r
526: }\r
527: }\r
528: else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor )\r
-BFD02656 001CFC5E LW V0, 28(S8)
-BFD0265A 69A0 LW V1, 0(V0)
-BFD0265C 002CFC5E LW V0, 44(S8)
-BFD02660 449A AND16 V1, V0
-BFD02662 002CFC5E LW V0, 44(S8)
-BFD02666 0004B443 BNE V1, V0, 0xBFD02672
-BFD02668 0C000004 SLL ZERO, A0, 1
-BFD0266A 0C00 NOP
+BFD02656 001CFC5E LW V0, 28(S8)\r
+BFD0265A 69A0 LW V1, 0(V0)\r
+BFD0265C 002CFC5E LW V0, 44(S8)\r
+BFD02660 449A AND16 V1, V0\r
+BFD02662 002CFC5E LW V0, 44(S8)\r
+BFD02666 0004B443 BNE V1, V0, 0xBFD02672\r
+BFD02668 0C000004 SLL ZERO, A0, 1\r
+BFD0266A 0C00 NOP\r
529: {\r
530: /* All bits are set. */\r
531: xMatchFound = pdTRUE;\r
-BFD0266C ED01 LI V0, 1
-BFD0266E 0018F85E SW V0, 24(S8)
+BFD0266C ED01 LI V0, 1\r
+BFD0266E 0018F85E SW V0, 24(S8)\r
532: }\r
533: else\r
534: {\r
536: }\r
537: \r
538: if( xMatchFound != pdFALSE )\r
-BFD02672 0018FC5E LW V0, 24(S8)
-BFD02676 001A40E2 BEQZC V0, 0xBFD026AE
+BFD02672 0018FC5E LW V0, 24(S8)\r
+BFD02676 001A40E2 BEQZC V0, 0xBFD026AE\r
539: {\r
540: /* The bits match. Should the bits be cleared on exit? */\r
541: if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 )\r
-BFD0267A 0030FC7E LW V1, 48(S8)
-BFD0267E 010041A2 LUI V0, 0x100
-BFD02682 4493 AND16 V0, V1
-BFD02684 000740E2 BEQZC V0, 0xBFD02696
+BFD0267A 0030FC7E LW V1, 48(S8)\r
+BFD0267E 010041A2 LUI V0, 0x100\r
+BFD02682 4493 AND16 V0, V1\r
+BFD02684 000740E2 BEQZC V0, 0xBFD02696\r
542: {\r
543: uxBitsToClear |= uxBitsWaitedFor;\r
-BFD02688 0014FC7E LW V1, 20(S8)
-BFD0268C 002CFC5E LW V0, 44(S8)
-BFD02690 44D3 OR16 V0, V1
-BFD02692 0014F85E SW V0, 20(S8)
+BFD02688 0014FC7E LW V1, 20(S8)\r
+BFD0268C 002CFC5E LW V0, 44(S8)\r
+BFD02690 44D3 OR16 V0, V1\r
+BFD02692 0014F85E SW V0, 20(S8)\r
544: }\r
545: else\r
546: {\r
553: that is was unblocked due to its required bits matching, rather\r
554: than because it timed out. */\r
555: ( void ) xTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET );\r
-BFD02696 001CFC5E LW V0, 28(S8)
-BFD0269A 69A0 LW V1, 0(V0)
-BFD0269C 020041A2 LUI V0, 0x200
-BFD026A0 44D3 OR16 V0, V1
-BFD026A2 0010FC9E LW A0, 16(S8)
-BFD026A6 0CA2 MOVE A1, V0
-BFD026A8 216277E8 JALS xTaskRemoveFromUnorderedEventList
-BFD026AA 0C002162 LWC2 T3, 3072(V0)
-BFD026AC 0C00 NOP
+BFD02696 001CFC5E LW V0, 28(S8)\r
+BFD0269A 69A0 LW V1, 0(V0)\r
+BFD0269C 020041A2 LUI V0, 0x200\r
+BFD026A0 44D3 OR16 V0, V1\r
+BFD026A2 0010FC9E LW A0, 16(S8)\r
+BFD026A6 0CA2 MOVE A1, V0\r
+BFD026A8 216277E8 JALS xTaskRemoveFromUnorderedEventList\r
+BFD026AA 0C002162 LWC2 T3, 3072(V0)\r
+BFD026AC 0C00 NOP\r
556: }\r
557: \r
558: /* Move onto the next list item. Note pxListItem->pxNext is not\r
559: used here as the list item may have been removed from the event list\r
560: and inserted into the ready/pending reading list. */\r
561: pxListItem = pxNext;\r
-BFD026AE 0028FC5E LW V0, 40(S8)
-BFD026B2 0010F85E SW V0, 16(S8)
+BFD026AE 0028FC5E LW V0, 40(S8)\r
+BFD026B2 0010F85E SW V0, 16(S8)\r
562: }\r
563: \r
564: /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT\r
565: bit was set in the control word. */\r
566: pxEventBits->uxEventBits &= ~uxBitsToClear;\r
-BFD026C4 001CFC5E LW V0, 28(S8)
-BFD026C8 69A0 LW V1, 0(V0)
-BFD026CA 0014FC5E LW V0, 20(S8)
-BFD026CE 4412 NOT16 V0, V0
-BFD026D0 449A AND16 V1, V0
-BFD026D2 001CFC5E LW V0, 28(S8)
-BFD026D6 E9A0 SW V1, 0(V0)
+BFD026C4 001CFC5E LW V0, 28(S8)\r
+BFD026C8 69A0 LW V1, 0(V0)\r
+BFD026CA 0014FC5E LW V0, 20(S8)\r
+BFD026CE 4412 NOT16 V0, V0\r
+BFD026D0 449A AND16 V1, V0\r
+BFD026D2 001CFC5E LW V0, 28(S8)\r
+BFD026D6 E9A0 SW V1, 0(V0)\r
567: }\r
568: ( void ) xTaskResumeAll();\r
-BFD026D8 158E77E8 JALS xTaskResumeAll
-BFD026DA 0C00158E LBU T4, 3072(T6)
-BFD026DC 0C00 NOP
+BFD026D8 158E77E8 JALS xTaskResumeAll\r
+BFD026DA 0C00158E LBU T4, 3072(T6)\r
+BFD026DC 0C00 NOP\r
569: \r
570: return pxEventBits->uxEventBits;\r
-BFD026DE 001CFC5E LW V0, 28(S8)
-BFD026E2 6920 LW V0, 0(V0)
+BFD026DE 001CFC5E LW V0, 28(S8)\r
+BFD026E2 6920 LW V0, 0(V0)\r
571: }\r
-BFD026E4 0FBE MOVE SP, S8
-BFD026E6 4BEF LW RA, 60(SP)
-BFD026E8 4BCE LW S8, 56(SP)
-BFD026EA 4C21 ADDIU SP, SP, 64
-BFD026EC 459F JR16 RA
-BFD026EE 0C00 NOP
+BFD026E4 0FBE MOVE SP, S8\r
+BFD026E6 4BEF LW RA, 60(SP)\r
+BFD026E8 4BCE LW S8, 56(SP)\r
+BFD026EA 4C21 ADDIU SP, SP, 64\r
+BFD026EC 459F JR16 RA\r
+BFD026EE 0C00 NOP\r
572: /*-----------------------------------------------------------*/\r
573: \r
574: void vEventGroupDelete( EventGroupHandle_t xEventGroup )\r
575: {\r
-BFD06C70 4FF1 ADDIU SP, SP, -32
-BFD06C72 CBE7 SW RA, 28(SP)
-BFD06C74 CBC6 SW S8, 24(SP)
-BFD06C76 0FDD MOVE S8, SP
-BFD06C78 0020F89E SW A0, 32(S8)
+BFD06C70 4FF1 ADDIU SP, SP, -32\r
+BFD06C72 CBE7 SW RA, 28(SP)\r
+BFD06C74 CBC6 SW S8, 24(SP)\r
+BFD06C76 0FDD MOVE S8, SP\r
+BFD06C78 0020F89E SW A0, 32(S8)\r
576: EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;\r
-BFD06C7C 0020FC5E LW V0, 32(S8)
-BFD06C80 0010F85E SW V0, 16(S8)
+BFD06C7C 0020FC5E LW V0, 32(S8)\r
+BFD06C80 0010F85E SW V0, 16(S8)\r
577: const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits );\r
-BFD06C84 0010FC5E LW V0, 16(S8)
-BFD06C88 6D22 ADDIU V0, V0, 4
-BFD06C8A 0014F85E SW V0, 20(S8)
+BFD06C84 0010FC5E LW V0, 16(S8)\r
+BFD06C88 6D22 ADDIU V0, V0, 4\r
+BFD06C8A 0014F85E SW V0, 20(S8)\r
578: \r
579: vTaskSuspendAll();\r
-BFD06C8E 4EF477E8 JALS vTaskSuspendAll
-BFD06C90 4EF4 ADDIU S7, S7, -6
-BFD06C92 0C00 NOP
+BFD06C8E 4EF477E8 JALS vTaskSuspendAll\r
+BFD06C90 4EF4 ADDIU S7, S7, -6\r
+BFD06C92 0C00 NOP\r
580: {\r
581: traceEVENT_GROUP_DELETE( xEventGroup );\r
582: \r
583: while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 )\r
-BFD06C94 CC1C B 0xBFD06CCE
-BFD06C96 0C00 NOP
-BFD06CCE 0014FC5E LW V0, 20(S8)
-BFD06CD2 6920 LW V0, 0(V0)
-BFD06CD4 FFE040A2 BNEZC V0, 0xBFD06C98
-BFD06CD6 FC9EFFE0 LW RA, -866(ZERO)
+BFD06C94 CC1C B 0xBFD06CCE\r
+BFD06C96 0C00 NOP\r
+BFD06CCE 0014FC5E LW V0, 20(S8)\r
+BFD06CD2 6920 LW V0, 0(V0)\r
+BFD06CD4 FFE040A2 BNEZC V0, 0xBFD06C98\r
+BFD06CD6 FC9EFFE0 LW RA, -866(ZERO)\r
584: {\r
585: /* Unblock the task, returning 0 as the event list is being deleted\r
586: and cannot therefore have any bits set. */\r
587: configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) );\r
-BFD06C98 0014FC5E LW V0, 20(S8)
-BFD06C9C 69A3 LW V1, 12(V0)
-BFD06C9E 0014FC5E LW V0, 20(S8)
-BFD06CA2 6D24 ADDIU V0, V0, 8
-BFD06CA4 000AB443 BNE V1, V0, 0xBFD06CBC
-BFD06CA6 0C00000A SLL ZERO, T2, 1
-BFD06CA8 0C00 NOP
-BFD06CAA BFD141A2 LUI V0, 0xBFD1
-BFD06CAC 3082BFD1 LDC1 F30, 12418(S1)
-BFD06CAE 9C0C3082 ADDIU A0, V0, -25588
-BFD06CB0 30A09C0C LWC1 F0, 12448(T4)
-BFD06CB2 024B30A0 ADDIU A1, ZERO, 587
-BFD06CB6 4B7E77E8 JALS vAssertCalled
-BFD06CB8 4B7E LW K1, 120(SP)
-BFD06CBA 0C00 NOP
+BFD06C98 0014FC5E LW V0, 20(S8)\r
+BFD06C9C 69A3 LW V1, 12(V0)\r
+BFD06C9E 0014FC5E LW V0, 20(S8)\r
+BFD06CA2 6D24 ADDIU V0, V0, 8\r
+BFD06CA4 000AB443 BNE V1, V0, 0xBFD06CBC\r
+BFD06CA6 0C00000A SLL ZERO, T2, 1\r
+BFD06CA8 0C00 NOP\r
+BFD06CAA BFD141A2 LUI V0, 0xBFD1\r
+BFD06CAC 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD06CAE 9C0C3082 ADDIU A0, V0, -25588\r
+BFD06CB0 30A09C0C LWC1 F0, 12448(T4)\r
+BFD06CB2 024B30A0 ADDIU A1, ZERO, 587\r
+BFD06CB6 4B7E77E8 JALS vAssertCalled\r
+BFD06CB8 4B7E LW K1, 120(SP)\r
+BFD06CBA 0C00 NOP\r
588: ( void ) xTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET );\r
-BFD06CBC 0014FC5E LW V0, 20(S8)
-BFD06CC0 6923 LW V0, 12(V0)
-BFD06CC2 0C82 MOVE A0, V0
-BFD06CC4 020041A5 LUI A1, 0x200
-BFD06CC8 216277E8 JALS xTaskRemoveFromUnorderedEventList
-BFD06CCA 0C002162 LWC2 T3, 3072(V0)
-BFD06CCC 0C00 NOP
+BFD06CBC 0014FC5E LW V0, 20(S8)\r
+BFD06CC0 6923 LW V0, 12(V0)\r
+BFD06CC2 0C82 MOVE A0, V0\r
+BFD06CC4 020041A5 LUI A1, 0x200\r
+BFD06CC8 216277E8 JALS xTaskRemoveFromUnorderedEventList\r
+BFD06CCA 0C002162 LWC2 T3, 3072(V0)\r
+BFD06CCC 0C00 NOP\r
589: }\r
590: \r
591: vPortFree( pxEventBits );\r
-BFD06CD8 0010FC9E LW A0, 16(S8)
-BFD06CDC 2FEA77E8 JALS vPortFree
-BFD06CDE 2FEA ANDI A3, A2, 0x20
-BFD06CE0 0C00 NOP
+BFD06CD8 0010FC9E LW A0, 16(S8)\r
+BFD06CDC 2FEA77E8 JALS vPortFree\r
+BFD06CDE 2FEA ANDI A3, A2, 0x20\r
+BFD06CE0 0C00 NOP\r
592: }\r
593: ( void ) xTaskResumeAll();\r
-BFD06CE2 158E77E8 JALS xTaskResumeAll
-BFD06CE4 0C00158E LBU T4, 3072(T6)
-BFD06CE6 0C00 NOP
+BFD06CE2 158E77E8 JALS xTaskResumeAll\r
+BFD06CE4 0C00158E LBU T4, 3072(T6)\r
+BFD06CE6 0C00 NOP\r
594: }\r
-BFD06CE8 0FBE MOVE SP, S8
-BFD06CEA 4BE7 LW RA, 28(SP)
-BFD06CEC 4BC6 LW S8, 24(SP)
-BFD06CEE 4C11 ADDIU SP, SP, 32
-BFD06CF0 459F JR16 RA
-BFD06CF2 0C00 NOP
+BFD06CE8 0FBE MOVE SP, S8\r
+BFD06CEA 4BE7 LW RA, 28(SP)\r
+BFD06CEC 4BC6 LW S8, 24(SP)\r
+BFD06CEE 4C11 ADDIU SP, SP, 32\r
+BFD06CF0 459F JR16 RA\r
+BFD06CF2 0C00 NOP\r
595: /*-----------------------------------------------------------*/\r
596: \r
597: /* For internal use only - execute a 'set bits' command that was pended from\r
598: an interrupt. */\r
599: void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet )\r
600: {\r
-BFD0993C 4FF5 ADDIU SP, SP, -24
-BFD0993E CBE5 SW RA, 20(SP)
-BFD09940 CBC4 SW S8, 16(SP)
-BFD09942 0FDD MOVE S8, SP
-BFD09944 0018F89E SW A0, 24(S8)
-BFD09948 001CF8BE SW A1, 28(S8)
+BFD0993C 4FF5 ADDIU SP, SP, -24\r
+BFD0993E CBE5 SW RA, 20(SP)\r
+BFD09940 CBC4 SW S8, 16(SP)\r
+BFD09942 0FDD MOVE S8, SP\r
+BFD09944 0018F89E SW A0, 24(S8)\r
+BFD09948 001CF8BE SW A1, 28(S8)\r
601: ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet );\r
-BFD0994C 0018FC9E LW A0, 24(S8)
-BFD09950 001CFCBE LW A1, 28(S8)
-BFD09954 12B477E8 JALS xEventGroupSetBits
-BFD09956 0C0012B4 ADDI S5, S4, 3072
-BFD09958 0C00 NOP
+BFD0994C 0018FC9E LW A0, 24(S8)\r
+BFD09950 001CFCBE LW A1, 28(S8)\r
+BFD09954 12B477E8 JALS xEventGroupSetBits\r
+BFD09956 0C0012B4 ADDI S5, S4, 3072\r
+BFD09958 0C00 NOP\r
602: }\r
-BFD0995A 0FBE MOVE SP, S8
-BFD0995C 4BE5 LW RA, 20(SP)
-BFD0995E 4BC4 LW S8, 16(SP)
-BFD09960 4C0D ADDIU SP, SP, 24
-BFD09962 459F JR16 RA
-BFD09964 0C00 NOP
+BFD0995A 0FBE MOVE SP, S8\r
+BFD0995C 4BE5 LW RA, 20(SP)\r
+BFD0995E 4BC4 LW S8, 16(SP)\r
+BFD09960 4C0D ADDIU SP, SP, 24\r
+BFD09962 459F JR16 RA\r
+BFD09964 0C00 NOP\r
603: /*-----------------------------------------------------------*/\r
604: \r
605: /* For internal use only - execute a 'clear bits' command that was pended from\r
606: an interrupt. */\r
607: void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear )\r
608: {\r
-BFD09968 4FF5 ADDIU SP, SP, -24
-BFD0996A CBE5 SW RA, 20(SP)
-BFD0996C CBC4 SW S8, 16(SP)
-BFD0996E 0FDD MOVE S8, SP
-BFD09970 0018F89E SW A0, 24(S8)
-BFD09974 001CF8BE SW A1, 28(S8)
+BFD09968 4FF5 ADDIU SP, SP, -24\r
+BFD0996A CBE5 SW RA, 20(SP)\r
+BFD0996C CBC4 SW S8, 16(SP)\r
+BFD0996E 0FDD MOVE S8, SP\r
+BFD09970 0018F89E SW A0, 24(S8)\r
+BFD09974 001CF8BE SW A1, 28(S8)\r
609: ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear );\r
-BFD09978 0018FC9E LW A0, 24(S8)
-BFD0997C 001CFCBE LW A1, 28(S8)
-BFD09980 352277E8 JALS xEventGroupClearBits
-BFD09982 0C003522 LHU T1, 3072(V0)
-BFD09984 0C00 NOP
+BFD09978 0018FC9E LW A0, 24(S8)\r
+BFD0997C 001CFCBE LW A1, 28(S8)\r
+BFD09980 352277E8 JALS xEventGroupClearBits\r
+BFD09982 0C003522 LHU T1, 3072(V0)\r
+BFD09984 0C00 NOP\r
610: }\r
-BFD09986 0FBE MOVE SP, S8
-BFD09988 4BE5 LW RA, 20(SP)
-BFD0998A 4BC4 LW S8, 16(SP)
-BFD0998C 4C0D ADDIU SP, SP, 24
-BFD0998E 459F JR16 RA
-BFD09990 0C00 NOP
+BFD09986 0FBE MOVE SP, S8\r
+BFD09988 4BE5 LW RA, 20(SP)\r
+BFD0998A 4BC4 LW S8, 16(SP)\r
+BFD0998C 4C0D ADDIU SP, SP, 24\r
+BFD0998E 459F JR16 RA\r
+BFD09990 0C00 NOP\r
611: /*-----------------------------------------------------------*/\r
612: \r
613: static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits )\r
614: {\r
-BFD080F4 4FF9 ADDIU SP, SP, -16
-BFD080F6 CBC3 SW S8, 12(SP)
-BFD080F8 0FDD MOVE S8, SP
-BFD080FA 0010F89E SW A0, 16(S8)
-BFD080FE 0014F8BE SW A1, 20(S8)
-BFD08102 0018F8DE SW A2, 24(S8)
+BFD080F4 4FF9 ADDIU SP, SP, -16\r
+BFD080F6 CBC3 SW S8, 12(SP)\r
+BFD080F8 0FDD MOVE S8, SP\r
+BFD080FA 0010F89E SW A0, 16(S8)\r
+BFD080FE 0014F8BE SW A1, 20(S8)\r
+BFD08102 0018F8DE SW A2, 24(S8)\r
615: BaseType_t xWaitConditionMet = pdFALSE;\r
-BFD08106 0000F81E SW ZERO, 0(S8)
+BFD08106 0000F81E SW ZERO, 0(S8)\r
616: \r
617: if( xWaitForAllBits == pdFALSE )\r
-BFD0810A 0018FC5E LW V0, 24(S8)
-BFD0810E 000C40A2 BNEZC V0, 0xBFD0812A
+BFD0810A 0018FC5E LW V0, 24(S8)\r
+BFD0810E 000C40A2 BNEZC V0, 0xBFD0812A\r
618: {\r
619: /* Task only has to wait for one bit within uxBitsToWaitFor to be\r
620: set. Is one already set? */\r
621: if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 )\r
-BFD08112 0010FC7E LW V1, 16(S8)
-BFD08116 0014FC5E LW V0, 20(S8)
-BFD0811A 4493 AND16 V0, V1
-BFD0811C 001240E2 BEQZC V0, 0xBFD08144
+BFD08112 0010FC7E LW V1, 16(S8)\r
+BFD08116 0014FC5E LW V0, 20(S8)\r
+BFD0811A 4493 AND16 V0, V1\r
+BFD0811C 001240E2 BEQZC V0, 0xBFD08144\r
622: {\r
623: xWaitConditionMet = pdTRUE;\r
-BFD08120 ED01 LI V0, 1
-BFD08122 0000F85E SW V0, 0(S8)
-BFD08126 CC0E B 0xBFD08144
-BFD08128 0C00 NOP
+BFD08120 ED01 LI V0, 1\r
+BFD08122 0000F85E SW V0, 0(S8)\r
+BFD08126 CC0E B 0xBFD08144\r
+BFD08128 0C00 NOP\r
624: }\r
625: else\r
626: {\r
632: /* Task has to wait for all the bits in uxBitsToWaitFor to be set.\r
633: Are they set already? */\r
634: if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor )\r
-BFD0812A 0010FC7E LW V1, 16(S8)
-BFD0812E 0014FC5E LW V0, 20(S8)
-BFD08132 449A AND16 V1, V0
-BFD08134 0014FC5E LW V0, 20(S8)
-BFD08138 0004B443 BNE V1, V0, 0xBFD08144
-BFD0813A 0C000004 SLL ZERO, A0, 1
-BFD0813C 0C00 NOP
+BFD0812A 0010FC7E LW V1, 16(S8)\r
+BFD0812E 0014FC5E LW V0, 20(S8)\r
+BFD08132 449A AND16 V1, V0\r
+BFD08134 0014FC5E LW V0, 20(S8)\r
+BFD08138 0004B443 BNE V1, V0, 0xBFD08144\r
+BFD0813A 0C000004 SLL ZERO, A0, 1\r
+BFD0813C 0C00 NOP\r
635: {\r
636: xWaitConditionMet = pdTRUE;\r
-BFD0813E ED01 LI V0, 1
-BFD08140 0000F85E SW V0, 0(S8)
+BFD0813E ED01 LI V0, 1\r
+BFD08140 0000F85E SW V0, 0(S8)\r
637: }\r
638: else\r
639: {\r
642: }\r
643: \r
644: return xWaitConditionMet;\r
-BFD08144 0000FC5E LW V0, 0(S8)
+BFD08144 0000FC5E LW V0, 0(S8)\r
645: }\r
-BFD08148 0FBE MOVE SP, S8
-BFD0814A 4BC3 LW S8, 12(SP)
-BFD0814C 4C09 ADDIU SP, SP, 16
-BFD0814E 459F JR16 RA
-BFD08150 0C00 NOP
+BFD08148 0FBE MOVE SP, S8\r
+BFD0814A 4BC3 LW S8, 12(SP)\r
+BFD0814C 4C09 ADDIU SP, SP, 16\r
+BFD0814E 459F JR16 RA\r
+BFD08150 0C00 NOP\r
646: /*-----------------------------------------------------------*/\r
647: \r
648: #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )\r
681: \r
682: #endif\r
683: \r
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/startup/mplab/on_reset.c
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/startup/mplab/on_reset.c \r
1: /*****************************************************************************\r
2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
3: * You may use this software and any derivatives exclusively with\r
47: void\r
48: __attribute__((nomips16)) _on_reset (void)\r
49: {\r
-BFD091CC 4FB0 ADDIU SP, SP, -8
-BFD091CE CBC1 SW S8, 4(SP)
-BFD091D0 0FDD MOVE S8, SP
+BFD091CC 4FB0 ADDIU SP, SP, -8\r
+BFD091CE CBC1 SW S8, 4(SP)\r
+BFD091D0 0FDD MOVE S8, SP\r
50: /* Enable JTAG */\r
51: ECS_REG->JTAG_ENABLE |= 1u;\r
-BFD091D2 A00041A2 LUI V0, 0xA000
-BFD091D6 FC205042 ORI V0, V0, -992
-BFD091D8 41A3FC20 LW AT, 16803(ZERO)
-BFD091DA A00041A3 LUI V1, 0xA000
-BFD091DE FC205063 ORI V1, V1, -992
-BFD091E0 69B0FC20 LW AT, 27056(ZERO)
-BFD091E2 69B0 LW V1, 0(V1)
-BFD091E4 00015063 ORI V1, V1, 1
-BFD091E8 E9A0 SW V1, 0(V0)
+BFD091D2 A00041A2 LUI V0, 0xA000\r
+BFD091D6 FC205042 ORI V0, V0, -992\r
+BFD091D8 41A3FC20 LW AT, 16803(ZERO)\r
+BFD091DA A00041A3 LUI V1, 0xA000\r
+BFD091DE FC205063 ORI V1, V1, -992\r
+BFD091E0 69B0FC20 LW AT, 27056(ZERO)\r
+BFD091E2 69B0 LW V1, 0(V1)\r
+BFD091E4 00015063 ORI V1, V1, 1\r
+BFD091E8 E9A0 SW V1, 0(V0)\r
52: \r
53: /* Disable WDT */\r
54: WDT->CONTROL = 0u;\r
-BFD091EA A00041A2 LUI V0, 0xA000
-BFD091EE 04005042 ORI V0, V0, 1024
-BFD091F0 0400 ADDU S0, S0, S0
-BFD091F2 8824 SB S0, 4(V0)
+BFD091EA A00041A2 LUI V0, 0xA000\r
+BFD091EE 04005042 ORI V0, V0, 1024\r
+BFD091F0 0400 ADDU S0, S0, S0\r
+BFD091F2 8824 SB S0, 4(V0)\r
55: \r
56: /* Set CPU clock divider specified in appcfg.h */\r
57: PCR->PROC_CLOCK_CNTRL = ( PCR_CLOCK_DIVIDER );\r
-BFD091F4 A00841A2 LUI V0, 0xA008
-BFD091F8 01005042 ORI V0, V0, 256
-BFD091FC ED81 LI V1, 1
-BFD091FE E9A8 SW V1, 32(V0)
+BFD091F4 A00841A2 LUI V0, 0xA008\r
+BFD091F8 01005042 ORI V0, V0, 256\r
+BFD091FC ED81 LI V1, 1\r
+BFD091FE E9A8 SW V1, 32(V0)\r
58: __EHB();\r
-BFD09200 18000000 SLL ZERO, ZERO, 3
-BFD09202 00001800 SB ZERO, 0(ZERO)
+BFD09200 18000000 SLL ZERO, ZERO, 3\r
+BFD09202 00001800 SB ZERO, 0(ZERO)\r
59: CPU_NOP();\r
-BFD09204 08000000 SSNOP
-BFD09206 0800 LBU S0, 0(S0)
+BFD09204 08000000 SSNOP\r
+BFD09206 0800 LBU S0, 0(S0)\r
60: \r
61: }\r
-BFD09208 0FBE MOVE SP, S8
-BFD0920A 4BC1 LW S8, 4(SP)
-BFD0920C 459F JR16 RA
-BFD0920E 4C05 ADDIU SP, SP, 8
+BFD09208 0FBE MOVE SP, S8\r
+BFD0920A 4BC1 LW S8, 4(SP)\r
+BFD0920C 459F JR16 RA\r
+BFD0920E 4C05 ADDIU SP, SP, 8\r
62: \r
63: \r
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/startup/mplab/default-on-bootstrap.c
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/startup/mplab/default-on-bootstrap.c\r
1: /*********************************************************************\r
2: *\r
3: * Default _on_bootstrap Implementation\r
40: void \r
41: _on_bootstrap (void)\r
42: {\r
-BFD09EE4 4FB0 ADDIU SP, SP, -8
-BFD09EE6 CBC1 SW S8, 4(SP)
-BFD09EE8 0FDD MOVE S8, SP
+BFD09EE4 4FB0 ADDIU SP, SP, -8\r
+BFD09EE6 CBC1 SW S8, 4(SP)\r
+BFD09EE8 0FDD MOVE S8, SP\r
43: }\r
-BFD09EEA 0FBE MOVE SP, S8
-BFD09EEC 4BC1 LW S8, 4(SP)
-BFD09EEE 4C05 ADDIU SP, SP, 8
-BFD09EF0 459F JR16 RA
-BFD09EF2 0C00 NOP
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/mec14xx_timers.c -------
+BFD09EEA 0FBE MOVE SP, S8\r
+BFD09EEC 4BC1 LW S8, 4(SP)\r
+BFD09EEE 4C05 ADDIU SP, SP, 8\r
+BFD09EF0 459F JR16 RA\r
+BFD09EF2 0C00 NOP\r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/mec14xx_timers.c -------\r
1: /*****************************************************************************\r
2: * © 2014 Microchip Technology Inc. and its subsidiaries.\r
3: * You may use this software and any derivatives exclusively with\r
64: */\r
65: static uint8_t btmr_valid(uint8_t tmr_id)\r
66: {\r
-BFD09A44 4FB0 ADDIU SP, SP, -8
-BFD09A46 CBC1 SW S8, 4(SP)
-BFD09A48 0FDD MOVE S8, SP
-BFD09A4A 0C44 MOVE V0, A0
-BFD09A4C 0008185E SB V0, 8(S8)
+BFD09A44 4FB0 ADDIU SP, SP, -8\r
+BFD09A46 CBC1 SW S8, 4(SP)\r
+BFD09A48 0FDD MOVE S8, SP\r
+BFD09A4A 0C44 MOVE V0, A0\r
+BFD09A4C 0008185E SB V0, 8(S8)\r
67: if ( tmr_id < (BTMR_ID_MAX ) ) {\r
-BFD09A50 0008145E LBU V0, 8(S8)
-BFD09A54 0004B042 SLTIU V0, V0, 4
-BFD09A58 000340E2 BEQZC V0, 0xBFD09A62
+BFD09A50 0008145E LBU V0, 8(S8)\r
+BFD09A54 0004B042 SLTIU V0, V0, 4\r
+BFD09A58 000340E2 BEQZC V0, 0xBFD09A62\r
68: return true;\r
-BFD09A5C ED01 LI V0, 1
-BFD09A5E CC02 B 0xBFD09A64
-BFD09A60 0C00 NOP
+BFD09A5C ED01 LI V0, 1\r
+BFD09A5E CC02 B 0xBFD09A64\r
+BFD09A60 0C00 NOP\r
69: }\r
70: return false;\r
-BFD09A62 0C40 MOVE V0, ZERO
+BFD09A62 0C40 MOVE V0, ZERO\r
71: }\r
-BFD09A64 0FBE MOVE SP, S8
-BFD09A66 4BC1 LW S8, 4(SP)
-BFD09A68 4C05 ADDIU SP, SP, 8
-BFD09A6A 459F JR16 RA
-BFD09A6C 0C00 NOP
+BFD09A64 0FBE MOVE SP, S8\r
+BFD09A66 4BC1 LW S8, 4(SP)\r
+BFD09A68 4C05 ADDIU SP, SP, 8\r
+BFD09A6A 459F JR16 RA\r
+BFD09A6C 0C00 NOP\r
72: \r
73: #else\r
74: \r
87: \r
88: uint32_t btmr_get_hw_addr(uint8_t btmr_id)\r
89: {\r
-BFD09A70 4FB0 ADDIU SP, SP, -8
-BFD09A72 CBC1 SW S8, 4(SP)
-BFD09A74 0FDD MOVE S8, SP
-BFD09A76 0C44 MOVE V0, A0
-BFD09A78 0008185E SB V0, 8(S8)
+BFD09A70 4FB0 ADDIU SP, SP, -8\r
+BFD09A72 CBC1 SW S8, 4(SP)\r
+BFD09A74 0FDD MOVE S8, SP\r
+BFD09A76 0C44 MOVE V0, A0\r
+BFD09A78 0008185E SB V0, 8(S8)\r
90: return (uint32_t)(BTMR0_BASE) + \r
-BFD09A82 A00041A2 LUI V0, 0xA000
-BFD09A86 0C005042 ORI V0, V0, 3072
-BFD09A88 0C00 NOP
-BFD09A8A 0526 ADDU V0, V1, V0
+BFD09A82 A00041A2 LUI V0, 0xA000\r
+BFD09A86 0C005042 ORI V0, V0, 3072\r
+BFD09A88 0C00 NOP\r
+BFD09A8A 0526 ADDU V0, V1, V0\r
91: ((uint32_t)(btmr_id) << (BTMR_INSTANCE_BITPOS));\r
-BFD09A7C 0008145E LBU V0, 8(S8)
-BFD09A80 25AA SLL V1, V0, 5
+BFD09A7C 0008145E LBU V0, 8(S8)\r
+BFD09A80 25AA SLL V1, V0, 5\r
92: }\r
-BFD09A8C 0FBE MOVE SP, S8
-BFD09A8E 4BC1 LW S8, 4(SP)
-BFD09A90 4C05 ADDIU SP, SP, 8
-BFD09A92 459F JR16 RA
-BFD09A94 0C00 NOP
+BFD09A8C 0FBE MOVE SP, S8\r
+BFD09A8E 4BC1 LW S8, 4(SP)\r
+BFD09A90 4C05 ADDIU SP, SP, 8\r
+BFD09A92 459F JR16 RA\r
+BFD09A94 0C00 NOP\r
93: \r
94: /**\r
95: * btmr_sleep_en - Enable/Disable clock gating on idle of a \r
102: */\r
103: void btmr_sleep_en(uint8_t tmr_id, uint8_t sleep_en)\r
104: {\r
-BFD05DC0 4FF1 ADDIU SP, SP, -32
-BFD05DC2 CBE7 SW RA, 28(SP)
-BFD05DC4 CBC6 SW S8, 24(SP)
-BFD05DC6 0FDD MOVE S8, SP
-BFD05DC8 0C64 MOVE V1, A0
-BFD05DCA 0C45 MOVE V0, A1
-BFD05DCC 0020187E SB V1, 32(S8)
-BFD05DD0 0024185E SB V0, 36(S8)
+BFD05DC0 4FF1 ADDIU SP, SP, -32\r
+BFD05DC2 CBE7 SW RA, 28(SP)\r
+BFD05DC4 CBC6 SW S8, 24(SP)\r
+BFD05DC6 0FDD MOVE S8, SP\r
+BFD05DC8 0C64 MOVE V1, A0\r
+BFD05DCA 0C45 MOVE V0, A1\r
+BFD05DCC 0020187E SB V1, 32(S8)\r
+BFD05DD0 0024185E SB V0, 36(S8)\r
105: uint32_t sleep_mask;\r
106: uint32_t volatile * p;\r
107: \r
108: sleep_mask = 0ul;\r
-BFD05DD4 0014F81E SW ZERO, 20(S8)
+BFD05DD4 0014F81E SW ZERO, 20(S8)\r
109: if ( btmr_valid(tmr_id) ) {\r
-BFD05DD8 0020145E LBU V0, 32(S8)
-BFD05DDC 0C82 MOVE A0, V0
-BFD05DDE 4D2277E8 JALS btmr_valid
-BFD05DE0 4D22 ADDIU T1, T1, 1
-BFD05DE2 0C00 NOP
-BFD05DE4 004040E2 BEQZC V0, 0xBFD05E68
+BFD05DD8 0020145E LBU V0, 32(S8)\r
+BFD05DDC 0C82 MOVE A0, V0\r
+BFD05DDE 4D2277E8 JALS btmr_valid\r
+BFD05DE0 4D22 ADDIU T1, T1, 1\r
+BFD05DE2 0C00 NOP\r
+BFD05DE4 004040E2 BEQZC V0, 0xBFD05E68\r
110: if (btmr_slp_info[tmr_id].slp_reg) {\r
-BFD05DE8 0020147E LBU V1, 32(S8)
-BFD05DEC BFD141A2 LUI V0, 0xBFD1
-BFD05DEE 25B2BFD1 LDC1 F30, 9650(S1)
-BFD05DF0 25B2 SLL V1, V1, 1
-BFD05DF2 9F243042 ADDIU V0, V0, -24796
-BFD05DF4 05269F24 LWC1 F25, 1318(A0)
-BFD05DF6 0526 ADDU V0, V1, V0
-BFD05DF8 0920 LBU V0, 0(V0)
-BFD05DFA 000840E2 BEQZC V0, 0xBFD05E0E
+BFD05DE8 0020147E LBU V1, 32(S8)\r
+BFD05DEC BFD141A2 LUI V0, 0xBFD1\r
+BFD05DEE 25B2BFD1 LDC1 F30, 9650(S1)\r
+BFD05DF0 25B2 SLL V1, V1, 1\r
+BFD05DF2 9F243042 ADDIU V0, V0, -24796\r
+BFD05DF4 05269F24 LWC1 F25, 1318(A0)\r
+BFD05DF6 0526 ADDU V0, V1, V0\r
+BFD05DF8 0920 LBU V0, 0(V0)\r
+BFD05DFA 000840E2 BEQZC V0, 0xBFD05E0E\r
111: p = (uint32_t volatile *)&(PCR->EC_SLEEP_EN2);\r
-BFD05DFE A00841A2 LUI V0, 0xA008
-BFD05E02 01245042 ORI V0, V0, 292
-BFD05E06 0010F85E SW V0, 16(S8)
-BFD05E08 CC070010 BREAK
-BFD05E0A CC07 B 0xBFD05E1A
-BFD05E0C 0C00 NOP
+BFD05DFE A00841A2 LUI V0, 0xA008\r
+BFD05E02 01245042 ORI V0, V0, 292\r
+BFD05E06 0010F85E SW V0, 16(S8)\r
+BFD05E08 CC070010 BREAK\r
+BFD05E0A CC07 B 0xBFD05E1A\r
+BFD05E0C 0C00 NOP\r
112: } else {\r
113: p = (uint32_t volatile *)&(PCR->EC_SLEEP_EN);\r
-BFD05E0E A00841A2 LUI V0, 0xA008
-BFD05E12 01085042 ORI V0, V0, 264
-BFD05E16 0010F85E SW V0, 16(S8)
+BFD05E0E A00841A2 LUI V0, 0xA008\r
+BFD05E12 01085042 ORI V0, V0, 264\r
+BFD05E16 0010F85E SW V0, 16(S8)\r
114: }\r
115: sleep_mask = (1ul << btmr_slp_info[tmr_id].bit_pos);\r
-BFD05E1A 0020147E LBU V1, 32(S8)
-BFD05E1E BFD141A2 LUI V0, 0xBFD1
-BFD05E20 25B2BFD1 LDC1 F30, 9650(S1)
-BFD05E22 25B2 SLL V1, V1, 1
-BFD05E24 9F243042 ADDIU V0, V0, -24796
-BFD05E26 05269F24 LWC1 F25, 1318(A0)
-BFD05E28 0526 ADDU V0, V1, V0
-BFD05E2A 0921 LBU V0, 1(V0)
-BFD05E2C ED81 LI V1, 1
-BFD05E2E 10100062 SLLV V0, V0, V1
-BFD05E30 F85E1010 ADDI ZERO, S0, -1954
-BFD05E32 0014F85E SW V0, 20(S8)
+BFD05E1A 0020147E LBU V1, 32(S8)\r
+BFD05E1E BFD141A2 LUI V0, 0xBFD1\r
+BFD05E20 25B2BFD1 LDC1 F30, 9650(S1)\r
+BFD05E22 25B2 SLL V1, V1, 1\r
+BFD05E24 9F243042 ADDIU V0, V0, -24796\r
+BFD05E26 05269F24 LWC1 F25, 1318(A0)\r
+BFD05E28 0526 ADDU V0, V1, V0\r
+BFD05E2A 0921 LBU V0, 1(V0)\r
+BFD05E2C ED81 LI V1, 1\r
+BFD05E2E 10100062 SLLV V0, V0, V1\r
+BFD05E30 F85E1010 ADDI ZERO, S0, -1954\r
+BFD05E32 0014F85E SW V0, 20(S8)\r
116: if (sleep_en) {\r
-BFD05E36 0024145E LBU V0, 36(S8)
-BFD05E3A 000B40E2 BEQZC V0, 0xBFD05E54
+BFD05E36 0024145E LBU V0, 36(S8)\r
+BFD05E3A 000B40E2 BEQZC V0, 0xBFD05E54\r
117: *p |= (sleep_mask);\r
-BFD05E3E 0010FC5E LW V0, 16(S8)
-BFD05E42 69A0 LW V1, 0(V0)
-BFD05E44 0014FC5E LW V0, 20(S8)
-BFD05E48 44DA OR16 V1, V0
-BFD05E4A 0010FC5E LW V0, 16(S8)
-BFD05E4E E9A0 SW V1, 0(V0)
-BFD05E50 CC0B B 0xBFD05E68
-BFD05E52 0C00 NOP
+BFD05E3E 0010FC5E LW V0, 16(S8)\r
+BFD05E42 69A0 LW V1, 0(V0)\r
+BFD05E44 0014FC5E LW V0, 20(S8)\r
+BFD05E48 44DA OR16 V1, V0\r
+BFD05E4A 0010FC5E LW V0, 16(S8)\r
+BFD05E4E E9A0 SW V1, 0(V0)\r
+BFD05E50 CC0B B 0xBFD05E68\r
+BFD05E52 0C00 NOP\r
118: } else {\r
119: *p &= ~(sleep_mask);\r
-BFD05E54 0010FC5E LW V0, 16(S8)
-BFD05E58 69A0 LW V1, 0(V0)
-BFD05E5A 0014FC5E LW V0, 20(S8)
-BFD05E5E 4412 NOT16 V0, V0
-BFD05E60 449A AND16 V1, V0
-BFD05E62 0010FC5E LW V0, 16(S8)
-BFD05E66 E9A0 SW V1, 0(V0)
+BFD05E54 0010FC5E LW V0, 16(S8)\r
+BFD05E58 69A0 LW V1, 0(V0)\r
+BFD05E5A 0014FC5E LW V0, 20(S8)\r
+BFD05E5E 4412 NOT16 V0, V0\r
+BFD05E60 449A AND16 V1, V0\r
+BFD05E62 0010FC5E LW V0, 16(S8)\r
+BFD05E66 E9A0 SW V1, 0(V0)\r
120: }\r
121: }\r
122: }\r
-BFD05E68 0FBE MOVE SP, S8
-BFD05E6A 4BE7 LW RA, 28(SP)
-BFD05E6C 4BC6 LW S8, 24(SP)
-BFD05E6E 4C11 ADDIU SP, SP, 32
-BFD05E70 459F JR16 RA
-BFD05E72 0C00 NOP
+BFD05E68 0FBE MOVE SP, S8\r
+BFD05E6A 4BE7 LW RA, 28(SP)\r
+BFD05E6C 4BC6 LW S8, 24(SP)\r
+BFD05E6E 4C11 ADDIU SP, SP, 32\r
+BFD05E70 459F JR16 RA\r
+BFD05E72 0C00 NOP\r
123: \r
124: /**\r
125: * btmr_reset - Peform soft reset of specified timer.\r
132: */\r
133: void btmr_reset(uint8_t tmr_id)\r
134: {\r
-BFD07988 4FF1 ADDIU SP, SP, -32
-BFD0798A CBE7 SW RA, 28(SP)
-BFD0798C CBC6 SW S8, 24(SP)
-BFD0798E 0FDD MOVE S8, SP
-BFD07990 0C44 MOVE V0, A0
-BFD07992 0020185E SB V0, 32(S8)
+BFD07988 4FF1 ADDIU SP, SP, -32\r
+BFD0798A CBE7 SW RA, 28(SP)\r
+BFD0798C CBC6 SW S8, 24(SP)\r
+BFD0798E 0FDD MOVE S8, SP\r
+BFD07990 0C44 MOVE V0, A0\r
+BFD07992 0020185E SB V0, 32(S8)\r
135: BTMR_TypeDef * p;\r
136: uint32_t wait_cnt;\r
137: \r
138: if (btmr_valid(tmr_id)) {\r
-BFD07996 0020145E LBU V0, 32(S8)
-BFD0799A 0C82 MOVE A0, V0
-BFD0799C 4D2277E8 JALS btmr_valid
-BFD0799E 4D22 ADDIU T1, T1, 1
-BFD079A0 0C00 NOP
-BFD079A2 002540E2 BEQZC V0, 0xBFD079F0
+BFD07996 0020145E LBU V0, 32(S8)\r
+BFD0799A 0C82 MOVE A0, V0\r
+BFD0799C 4D2277E8 JALS btmr_valid\r
+BFD0799E 4D22 ADDIU T1, T1, 1\r
+BFD079A0 0C00 NOP\r
+BFD079A2 002540E2 BEQZC V0, 0xBFD079F0\r
139: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);\r
-BFD079A6 0020145E LBU V0, 32(S8)
-BFD079AA 0C82 MOVE A0, V0
-BFD079AC 4D3877E8 JALS btmr_get_hw_addr
-BFD079AE 4D38 ADDIU T1, T1, -4
-BFD079B0 0C00 NOP
-BFD079B2 0014F85E SW V0, 20(S8)
+BFD079A6 0020145E LBU V0, 32(S8)\r
+BFD079AA 0C82 MOVE A0, V0\r
+BFD079AC 4D3877E8 JALS btmr_get_hw_addr\r
+BFD079AE 4D38 ADDIU T1, T1, -4\r
+BFD079B0 0C00 NOP\r
+BFD079B2 0014F85E SW V0, 20(S8)\r
140: \r
141: p->CONTROL = (BTMR_CNTL_SOFT_RESET);\r
-BFD079B6 0014FC5E LW V0, 20(S8)
-BFD079B8 ED900014 SUB SP, S4, ZERO
-BFD079BA ED90 LI V1, 16
-BFD079BC E9A4 SW V1, 16(V0)
+BFD079B6 0014FC5E LW V0, 20(S8)\r
+BFD079B8 ED900014 SUB SP, S4, ZERO\r
+BFD079BA ED90 LI V1, 16\r
+BFD079BC E9A4 SW V1, 16(V0)\r
142: \r
143: wait_cnt = 256ul;\r
-BFD079BE 01003040 ADDIU V0, ZERO, 256
-BFD079C2 0010F85E SW V0, 16(S8)
+BFD079BE 01003040 ADDIU V0, ZERO, 256\r
+BFD079C2 0010F85E SW V0, 16(S8)\r
144: do {\r
145: if ( 0ul == (p->CONTROL & BTMR_CNTL_SOFT_RESET) ) {\r
-BFD079C6 0014FC5E LW V0, 20(S8)
-BFD079CA 6924 LW V0, 16(V0)
-BFD079CC 2D28 ANDI V0, V0, 0x10
-BFD079CE 000E40E2 BEQZC V0, 0xBFD079EE
+BFD079C6 0014FC5E LW V0, 20(S8)\r
+BFD079CA 6924 LW V0, 16(V0)\r
+BFD079CC 2D28 ANDI V0, V0, 0x10\r
+BFD079CE 000E40E2 BEQZC V0, 0xBFD079EE\r
146: break;\r
-BFD079EE 0C00 NOP
+BFD079EE 0C00 NOP\r
147: }\r
148: } \r
149: while ( wait_cnt-- ); \r
-BFD079D2 0010FC5E LW V0, 16(S8)
-BFD079D4 00400010 SRL ZERO, S0, 0
-BFD079D6 13900040 SLTU V0, ZERO, V0
-BFD079D8 2D2D1390 ADDI GP, S0, 11565
-BFD079DA 2D2D ANDI V0, V0, 0xFF
-BFD079DC 0010FC7E LW V1, 16(S8)
-BFD079E0 6DBE ADDIU V1, V1, -1
-BFD079E2 0010F87E SW V1, 16(S8)
-BFD079E6 FFEE40A2 BNEZC V0, 0xBFD079C6
-BFD079E8 CC02FFEE LW RA, -13310(T6)
-BFD079EA CC02 B 0xBFD079F0
-BFD079EC 0C00 NOP
+BFD079D2 0010FC5E LW V0, 16(S8)\r
+BFD079D4 00400010 SRL ZERO, S0, 0\r
+BFD079D6 13900040 SLTU V0, ZERO, V0\r
+BFD079D8 2D2D1390 ADDI GP, S0, 11565\r
+BFD079DA 2D2D ANDI V0, V0, 0xFF\r
+BFD079DC 0010FC7E LW V1, 16(S8)\r
+BFD079E0 6DBE ADDIU V1, V1, -1\r
+BFD079E2 0010F87E SW V1, 16(S8)\r
+BFD079E6 FFEE40A2 BNEZC V0, 0xBFD079C6\r
+BFD079E8 CC02FFEE LW RA, -13310(T6)\r
+BFD079EA CC02 B 0xBFD079F0\r
+BFD079EC 0C00 NOP\r
150: } \r
151: }\r
-BFD079F0 0FBE MOVE SP, S8
-BFD079F2 4BE7 LW RA, 28(SP)
-BFD079F4 4BC6 LW S8, 24(SP)
-BFD079F6 4C11 ADDIU SP, SP, 32
-BFD079F8 459F JR16 RA
-BFD079FA 0C00 NOP
+BFD079F0 0FBE MOVE SP, S8\r
+BFD079F2 4BE7 LW RA, 28(SP)\r
+BFD079F4 4BC6 LW S8, 24(SP)\r
+BFD079F6 4C11 ADDIU SP, SP, 32\r
+BFD079F8 459F JR16 RA\r
+BFD079FA 0C00 NOP\r
152: \r
153: /**\r
154: * btmr_init - Initialize specified timer\r
165: uint32_t initial_count,\r
166: uint32_t preload_count)\r
167: {\r
-BFD056FC 4FF1 ADDIU SP, SP, -32
-BFD056FE CBE7 SW RA, 28(SP)
-BFD05700 CBC6 SW S8, 24(SP)
-BFD05702 0FDD MOVE S8, SP
-BFD05704 0C65 MOVE V1, A1
-BFD05706 0C46 MOVE V0, A2
-BFD05708 002CF8FE SW A3, 44(S8)
-BFD0570C 0020189E SB A0, 32(S8)
-BFD05710 0024387E SH V1, 36(S8)
-BFD05714 0028385E SH V0, 40(S8)
+BFD056FC 4FF1 ADDIU SP, SP, -32\r
+BFD056FE CBE7 SW RA, 28(SP)\r
+BFD05700 CBC6 SW S8, 24(SP)\r
+BFD05702 0FDD MOVE S8, SP\r
+BFD05704 0C65 MOVE V1, A1\r
+BFD05706 0C46 MOVE V0, A2\r
+BFD05708 002CF8FE SW A3, 44(S8)\r
+BFD0570C 0020189E SB A0, 32(S8)\r
+BFD05710 0024387E SH V1, 36(S8)\r
+BFD05714 0028385E SH V0, 40(S8)\r
168: BTMR_TypeDef * pTMR;\r
169: \r
170: pTMR = NULL;\r
-BFD05718 0010F81E SW ZERO, 16(S8)
+BFD05718 0010F81E SW ZERO, 16(S8)\r
171: \r
172: if (btmr_valid(tmr_id)) {\r
-BFD0571C 0020145E LBU V0, 32(S8)
-BFD05720 0C82 MOVE A0, V0
-BFD05722 4D2277E8 JALS btmr_valid
-BFD05724 4D22 ADDIU T1, T1, 1
-BFD05726 0C00 NOP
-BFD05728 004840E2 BEQZC V0, 0xBFD057BC
+BFD0571C 0020145E LBU V0, 32(S8)\r
+BFD05720 0C82 MOVE A0, V0\r
+BFD05722 4D2277E8 JALS btmr_valid\r
+BFD05724 4D22 ADDIU T1, T1, 1\r
+BFD05726 0C00 NOP\r
+BFD05728 004840E2 BEQZC V0, 0xBFD057BC\r
173: btmr_reset(tmr_id);\r
-BFD0572C 0020145E LBU V0, 32(S8)
-BFD05730 0C82 MOVE A0, V0
-BFD05732 3CC477E8 JALS btmr_reset
-BFD05734 0C003CC4 LH A2, 3072(A0)
-BFD05736 0C00 NOP
+BFD0572C 0020145E LBU V0, 32(S8)\r
+BFD05730 0C82 MOVE A0, V0\r
+BFD05732 3CC477E8 JALS btmr_reset\r
+BFD05734 0C003CC4 LH A2, 3072(A0)\r
+BFD05736 0C00 NOP\r
174: \r
175: pTMR = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);\r
-BFD05738 0020145E LBU V0, 32(S8)
-BFD0573C 0C82 MOVE A0, V0
-BFD0573E 4D3877E8 JALS btmr_get_hw_addr
-BFD05740 4D38 ADDIU T1, T1, -4
-BFD05742 0C00 NOP
-BFD05744 0010F85E SW V0, 16(S8)
+BFD05738 0020145E LBU V0, 32(S8)\r
+BFD0573C 0C82 MOVE A0, V0\r
+BFD0573E 4D3877E8 JALS btmr_get_hw_addr\r
+BFD05740 4D38 ADDIU T1, T1, -4\r
+BFD05742 0C00 NOP\r
+BFD05744 0010F85E SW V0, 16(S8)\r
176: \r
177: // Ungate timer clocks and program prescale\r
178: pTMR->CONTROL = ((uint32_t)prescaler << 16) + (BTMR_CNTL_ENABLE);\r
-BFD05748 0028345E LHU V0, 40(S8)
-BFD0574C 80000042 SLL V0, V0, 16
-BFD05750 6DA0 ADDIU V1, V0, 1
-BFD05752 0010FC5E LW V0, 16(S8)
-BFD05756 E9A4 SW V1, 16(V0)
+BFD05748 0028345E LHU V0, 40(S8)\r
+BFD0574C 80000042 SLL V0, V0, 16\r
+BFD05750 6DA0 ADDIU V1, V0, 1\r
+BFD05752 0010FC5E LW V0, 16(S8)\r
+BFD05756 E9A4 SW V1, 16(V0)\r
179: \r
180: // Program Preload & initial counter value\r
181: pTMR->PRELOAD = preload_count;\r
-BFD05758 0010FC5E LW V0, 16(S8)
-BFD0575C 0030FC7E LW V1, 48(S8)
-BFD05760 E9A1 SW V1, 4(V0)
+BFD05758 0010FC5E LW V0, 16(S8)\r
+BFD0575C 0030FC7E LW V1, 48(S8)\r
+BFD05760 E9A1 SW V1, 4(V0)\r
182: pTMR->COUNT = initial_count;\r
-BFD05762 0010FC5E LW V0, 16(S8)
-BFD05766 002CFC7E LW V1, 44(S8)
-BFD0576A E9A0 SW V1, 0(V0)
+BFD05762 0010FC5E LW V0, 16(S8)\r
+BFD05766 002CFC7E LW V1, 44(S8)\r
+BFD0576A E9A0 SW V1, 0(V0)\r
183: \r
184: // Program control register, interrupt enable, and clear status\r
185: if (tmr_cntl & BTMR_COUNT_UP) {\r
-BFD0576C 0024345E LHU V0, 36(S8)
-BFD05770 2D24 ANDI V0, V0, 0x4
-BFD05772 000840E2 BEQZC V0, 0xBFD05786
+BFD0576C 0024345E LHU V0, 36(S8)\r
+BFD05770 2D24 ANDI V0, V0, 0x4\r
+BFD05772 000840E2 BEQZC V0, 0xBFD05786\r
186: pTMR->CONTROL |= BTMR_CNTL_COUNT_UP; \r
-BFD05776 0010FC5E LW V0, 16(S8)
-BFD0577A 6924 LW V0, 16(V0)
-BFD0577C 00045062 ORI V1, V0, 4
-BFD05780 0010FC5E LW V0, 16(S8)
-BFD05784 E9A4 SW V1, 16(V0)
+BFD05776 0010FC5E LW V0, 16(S8)\r
+BFD0577A 6924 LW V0, 16(V0)\r
+BFD0577C 00045062 ORI V1, V0, 4\r
+BFD05780 0010FC5E LW V0, 16(S8)\r
+BFD05784 E9A4 SW V1, 16(V0)\r
187: }\r
188: if (tmr_cntl & BTMR_AUTO_RESTART) {\r
-BFD05786 0024345E LHU V0, 36(S8)
-BFD0578A 2D26 ANDI V0, V0, 0x8
-BFD0578C 000840E2 BEQZC V0, 0xBFD057A0
+BFD05786 0024345E LHU V0, 36(S8)\r
+BFD0578A 2D26 ANDI V0, V0, 0x8\r
+BFD0578C 000840E2 BEQZC V0, 0xBFD057A0\r
189: pTMR->CONTROL |= BTMR_CNTL_AUTO_RESTART; \r
-BFD05790 0010FC5E LW V0, 16(S8)
-BFD05794 6924 LW V0, 16(V0)
-BFD05796 00085062 ORI V1, V0, 8
-BFD0579A 0010FC5E LW V0, 16(S8)
-BFD0579E E9A4 SW V1, 16(V0)
+BFD05790 0010FC5E LW V0, 16(S8)\r
+BFD05794 6924 LW V0, 16(V0)\r
+BFD05796 00085062 ORI V1, V0, 8\r
+BFD0579A 0010FC5E LW V0, 16(S8)\r
+BFD0579E E9A4 SW V1, 16(V0)\r
190: }\r
191: \r
192: if (tmr_cntl & BTMR_INT_EN) {\r
-BFD057A0 0024345E LHU V0, 36(S8)
-BFD057A4 2D21 ANDI V0, V0, 0x1
-BFD057A6 2D2D ANDI V0, V0, 0xFF
-BFD057A8 000840E2 BEQZC V0, 0xBFD057BC
+BFD057A0 0024345E LHU V0, 36(S8)\r
+BFD057A4 2D21 ANDI V0, V0, 0x1\r
+BFD057A6 2D2D ANDI V0, V0, 0xFF\r
+BFD057A8 000840E2 BEQZC V0, 0xBFD057BC\r
193: pTMR->INTEN = 0x01u; // enable first\r
-BFD057AC 0010FC5E LW V0, 16(S8)
-BFD057B0 ED81 LI V1, 1
-BFD057B2 89AC SB V1, 12(V0)
+BFD057AC 0010FC5E LW V0, 16(S8)\r
+BFD057B0 ED81 LI V1, 1\r
+BFD057B2 89AC SB V1, 12(V0)\r
194: pTMR->STATUS = 0x01u; // clear status\r
-BFD057B4 0010FC5E LW V0, 16(S8)
-BFD057B8 ED81 LI V1, 1
-BFD057BA 89A8 SB V1, 8(V0)
+BFD057B4 0010FC5E LW V0, 16(S8)\r
+BFD057B8 ED81 LI V1, 1\r
+BFD057BA 89A8 SB V1, 8(V0)\r
195: }\r
196: }\r
197: }\r
-BFD057BC 0FBE MOVE SP, S8
-BFD057BE 4BE7 LW RA, 28(SP)
-BFD057C0 4BC6 LW S8, 24(SP)
-BFD057C2 4C11 ADDIU SP, SP, 32
-BFD057C4 459F JR16 RA
-BFD057C6 0C00 NOP
+BFD057BC 0FBE MOVE SP, S8\r
+BFD057BE 4BE7 LW RA, 28(SP)\r
+BFD057C0 4BC6 LW S8, 24(SP)\r
+BFD057C2 4C11 ADDIU SP, SP, 32\r
+BFD057C4 459F JR16 RA\r
+BFD057C6 0C00 NOP\r
198: \r
199: /**\r
200: * btmr_ien - Enable specified timer's interrupt.\r
208: */\r
209: void btmr_ien(uint8_t tmr_id, uint8_t ien)\r
210: {\r
-BFD08330 4FF1 ADDIU SP, SP, -32
-BFD08332 CBE7 SW RA, 28(SP)
-BFD08334 CBC6 SW S8, 24(SP)
-BFD08336 0FDD MOVE S8, SP
-BFD08338 0C64 MOVE V1, A0
-BFD0833A 0C45 MOVE V0, A1
-BFD0833C 0020187E SB V1, 32(S8)
-BFD08340 0024185E SB V0, 36(S8)
+BFD08330 4FF1 ADDIU SP, SP, -32\r
+BFD08332 CBE7 SW RA, 28(SP)\r
+BFD08334 CBC6 SW S8, 24(SP)\r
+BFD08336 0FDD MOVE S8, SP\r
+BFD08338 0C64 MOVE V1, A0\r
+BFD0833A 0C45 MOVE V0, A1\r
+BFD0833C 0020187E SB V1, 32(S8)\r
+BFD08340 0024185E SB V0, 36(S8)\r
211: BTMR_TypeDef * p;\r
212: \r
213: if (btmr_valid(tmr_id)) {\r
-BFD08344 0020145E LBU V0, 32(S8)
-BFD08348 0C82 MOVE A0, V0
-BFD0834A 4D2277E8 JALS btmr_valid
-BFD0834C 4D22 ADDIU T1, T1, 1
-BFD0834E 0C00 NOP
-BFD08350 001540E2 BEQZC V0, 0xBFD0837E
+BFD08344 0020145E LBU V0, 32(S8)\r
+BFD08348 0C82 MOVE A0, V0\r
+BFD0834A 4D2277E8 JALS btmr_valid\r
+BFD0834C 4D22 ADDIU T1, T1, 1\r
+BFD0834E 0C00 NOP\r
+BFD08350 001540E2 BEQZC V0, 0xBFD0837E\r
214: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);\r
-BFD08354 0020145E LBU V0, 32(S8)
-BFD08358 0C82 MOVE A0, V0
-BFD0835A 4D3877E8 JALS btmr_get_hw_addr
-BFD0835C 4D38 ADDIU T1, T1, -4
-BFD0835E 0C00 NOP
-BFD08360 0010F85E SW V0, 16(S8)
+BFD08354 0020145E LBU V0, 32(S8)\r
+BFD08358 0C82 MOVE A0, V0\r
+BFD0835A 4D3877E8 JALS btmr_get_hw_addr\r
+BFD0835C 4D38 ADDIU T1, T1, -4\r
+BFD0835E 0C00 NOP\r
+BFD08360 0010F85E SW V0, 16(S8)\r
215: \r
216: if (ien) {\r
-BFD08364 0024145E LBU V0, 36(S8)
-BFD08368 000640E2 BEQZC V0, 0xBFD08378
+BFD08364 0024145E LBU V0, 36(S8)\r
+BFD08368 000640E2 BEQZC V0, 0xBFD08378\r
217: p->INTEN = (BTMR_INTEN); \r
-BFD0836C 0010FC5E LW V0, 16(S8)
-BFD08370 ED81 LI V1, 1
-BFD08372 89AC SB V1, 12(V0)
-BFD08374 CC04 B 0xBFD0837E
-BFD08376 0C00 NOP
+BFD0836C 0010FC5E LW V0, 16(S8)\r
+BFD08370 ED81 LI V1, 1\r
+BFD08372 89AC SB V1, 12(V0)\r
+BFD08374 CC04 B 0xBFD0837E\r
+BFD08376 0C00 NOP\r
218: } else {\r
219: p->INTEN = (BTMR_INTDIS); \r
-BFD08378 0010FC5E LW V0, 16(S8)
-BFD0837A 882C0010 EXT ZERO, S0, 0, 18
-BFD0837C 882C SB S0, 12(V0)
+BFD08378 0010FC5E LW V0, 16(S8)\r
+BFD0837A 882C0010 EXT ZERO, S0, 0, 18\r
+BFD0837C 882C SB S0, 12(V0)\r
220: }\r
221: }\r
222: }\r
-BFD0837E 0FBE MOVE SP, S8
-BFD08380 4BE7 LW RA, 28(SP)
-BFD08382 4BC6 LW S8, 24(SP)
-BFD08384 4C11 ADDIU SP, SP, 32
-BFD08386 459F JR16 RA
-BFD08388 0C00 NOP
+BFD0837E 0FBE MOVE SP, S8\r
+BFD08380 4BE7 LW RA, 28(SP)\r
+BFD08382 4BC6 LW S8, 24(SP)\r
+BFD08384 4C11 ADDIU SP, SP, 32\r
+BFD08386 459F JR16 RA\r
+BFD08388 0C00 NOP\r
223: \r
224: /**\r
225: * tmr_get_clr_ists - Read Timer interrupt status and clear if\r
235: */\r
236: uint8_t btmr_get_clr_ists(uint8_t tmr_id)\r
237: {\r
-BFD0838C 4FF1 ADDIU SP, SP, -32
-BFD0838E CBE7 SW RA, 28(SP)
-BFD08390 CBC6 SW S8, 24(SP)
-BFD08392 0FDD MOVE S8, SP
-BFD08394 0C44 MOVE V0, A0
-BFD08396 0020185E SB V0, 32(S8)
+BFD0838C 4FF1 ADDIU SP, SP, -32\r
+BFD0838E CBE7 SW RA, 28(SP)\r
+BFD08390 CBC6 SW S8, 24(SP)\r
+BFD08392 0FDD MOVE S8, SP\r
+BFD08394 0C44 MOVE V0, A0\r
+BFD08396 0020185E SB V0, 32(S8)\r
238: BTMR_TypeDef * p;\r
239: uint8_t rc;\r
240: \r
241: rc = (MEC14XX_FALSE);\r
-BFD0839A 0010181E SB ZERO, 16(S8)
+BFD0839A 0010181E SB ZERO, 16(S8)\r
242: if (btmr_valid(tmr_id)) {\r
-BFD0839E 0020145E LBU V0, 32(S8)
-BFD083A2 0C82 MOVE A0, V0
-BFD083A4 4D2277E8 JALS btmr_valid
-BFD083A6 4D22 ADDIU T1, T1, 1
-BFD083A8 0C00 NOP
-BFD083AA 001540E2 BEQZC V0, 0xBFD083D8
+BFD0839E 0020145E LBU V0, 32(S8)\r
+BFD083A2 0C82 MOVE A0, V0\r
+BFD083A4 4D2277E8 JALS btmr_valid\r
+BFD083A6 4D22 ADDIU T1, T1, 1\r
+BFD083A8 0C00 NOP\r
+BFD083AA 001540E2 BEQZC V0, 0xBFD083D8\r
243: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);\r
-BFD083AE 0020145E LBU V0, 32(S8)
-BFD083B2 0C82 MOVE A0, V0
-BFD083B4 4D3877E8 JALS btmr_get_hw_addr
-BFD083B6 4D38 ADDIU T1, T1, -4
-BFD083B8 0C00 NOP
-BFD083BA 0014F85E SW V0, 20(S8)
+BFD083AE 0020145E LBU V0, 32(S8)\r
+BFD083B2 0C82 MOVE A0, V0\r
+BFD083B4 4D3877E8 JALS btmr_get_hw_addr\r
+BFD083B6 4D38 ADDIU T1, T1, -4\r
+BFD083B8 0C00 NOP\r
+BFD083BA 0014F85E SW V0, 20(S8)\r
244: \r
245: if ( p->STATUS ) {\r
-BFD083BE 0014FC5E LW V0, 20(S8)
-BFD083C2 0928 LBU V0, 8(V0)
-BFD083C4 2D2D ANDI V0, V0, 0xFF
-BFD083C6 000740E2 BEQZC V0, 0xBFD083D8
+BFD083BE 0014FC5E LW V0, 20(S8)\r
+BFD083C2 0928 LBU V0, 8(V0)\r
+BFD083C4 2D2D ANDI V0, V0, 0xFF\r
+BFD083C6 000740E2 BEQZC V0, 0xBFD083D8\r
246: p->STATUS = (BTMR_STATUS_ACTIVE);\r
-BFD083CA 0014FC5E LW V0, 20(S8)
-BFD083CE ED81 LI V1, 1
-BFD083D0 89A8 SB V1, 8(V0)
+BFD083CA 0014FC5E LW V0, 20(S8)\r
+BFD083CE ED81 LI V1, 1\r
+BFD083D0 89A8 SB V1, 8(V0)\r
247: rc = true;\r
-BFD083D2 ED01 LI V0, 1
-BFD083D4 0010185E SB V0, 16(S8)
+BFD083D2 ED01 LI V0, 1\r
+BFD083D4 0010185E SB V0, 16(S8)\r
248: }\r
249: }\r
250: return rc;\r
-BFD083D8 0010145E LBU V0, 16(S8)
+BFD083D8 0010145E LBU V0, 16(S8)\r
251: }\r
-BFD083DC 0FBE MOVE SP, S8
-BFD083DE 4BE7 LW RA, 28(SP)
-BFD083E0 4BC6 LW S8, 24(SP)
-BFD083E2 4C11 ADDIU SP, SP, 32
-BFD083E4 459F JR16 RA
-BFD083E6 0C00 NOP
+BFD083DC 0FBE MOVE SP, S8\r
+BFD083DE 4BE7 LW RA, 28(SP)\r
+BFD083E0 4BC6 LW S8, 24(SP)\r
+BFD083E2 4C11 ADDIU SP, SP, 32\r
+BFD083E4 459F JR16 RA\r
+BFD083E6 0C00 NOP\r
252: \r
253: /**\r
254: * btmr_reload - Force timer to reload counter from preload \r
259: */\r
260: void btmr_reload(uint8_t tmr_id)\r
261: {\r
-BFD086B0 4FF1 ADDIU SP, SP, -32
-BFD086B2 CBE7 SW RA, 28(SP)
-BFD086B4 CBC6 SW S8, 24(SP)
-BFD086B6 0FDD MOVE S8, SP
-BFD086B8 0C44 MOVE V0, A0
-BFD086BA 0020185E SB V0, 32(S8)
+BFD086B0 4FF1 ADDIU SP, SP, -32\r
+BFD086B2 CBE7 SW RA, 28(SP)\r
+BFD086B4 CBC6 SW S8, 24(SP)\r
+BFD086B6 0FDD MOVE S8, SP\r
+BFD086B8 0C44 MOVE V0, A0\r
+BFD086BA 0020185E SB V0, 32(S8)\r
262: BTMR_TypeDef * p;\r
263: \r
264: if ( btmr_valid(tmr_id) ) {\r
-BFD086BE 0020145E LBU V0, 32(S8)
-BFD086C2 0C82 MOVE A0, V0
-BFD086C4 4D2277E8 JALS btmr_valid
-BFD086C6 4D22 ADDIU T1, T1, 1
-BFD086C8 0C00 NOP
-BFD086CA 001640E2 BEQZC V0, 0xBFD086FA
+BFD086BE 0020145E LBU V0, 32(S8)\r
+BFD086C2 0C82 MOVE A0, V0\r
+BFD086C4 4D2277E8 JALS btmr_valid\r
+BFD086C6 4D22 ADDIU T1, T1, 1\r
+BFD086C8 0C00 NOP\r
+BFD086CA 001640E2 BEQZC V0, 0xBFD086FA\r
265: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);\r
-BFD086CE 0020145E LBU V0, 32(S8)
-BFD086D2 0C82 MOVE A0, V0
-BFD086D4 4D3877E8 JALS btmr_get_hw_addr
-BFD086D6 4D38 ADDIU T1, T1, -4
-BFD086D8 0C00 NOP
-BFD086DA 0010F85E SW V0, 16(S8)
+BFD086CE 0020145E LBU V0, 32(S8)\r
+BFD086D2 0C82 MOVE A0, V0\r
+BFD086D4 4D3877E8 JALS btmr_get_hw_addr\r
+BFD086D6 4D38 ADDIU T1, T1, -4\r
+BFD086D8 0C00 NOP\r
+BFD086DA 0010F85E SW V0, 16(S8)\r
266: \r
267: if (p->CONTROL & BTMR_CNTL_START) {\r
-BFD086DE 0010FC5E LW V0, 16(S8)
-BFD086E2 6924 LW V0, 16(V0)
-BFD086E4 2D2A ANDI V0, V0, 0x20
-BFD086E6 000840E2 BEQZC V0, 0xBFD086FA
+BFD086DE 0010FC5E LW V0, 16(S8)\r
+BFD086E2 6924 LW V0, 16(V0)\r
+BFD086E4 2D2A ANDI V0, V0, 0x20\r
+BFD086E6 000840E2 BEQZC V0, 0xBFD086FA\r
268: p->CONTROL |= BTMR_CNTL_RELOAD;\r
-BFD086EA 0010FC5E LW V0, 16(S8)
-BFD086EE 6924 LW V0, 16(V0)
-BFD086F0 00405062 ORI V1, V0, 64
-BFD086F4 0010FC5E LW V0, 16(S8)
-BFD086F8 E9A4 SW V1, 16(V0)
+BFD086EA 0010FC5E LW V0, 16(S8)\r
+BFD086EE 6924 LW V0, 16(V0)\r
+BFD086F0 00405062 ORI V1, V0, 64\r
+BFD086F4 0010FC5E LW V0, 16(S8)\r
+BFD086F8 E9A4 SW V1, 16(V0)\r
269: }\r
270: }\r
271: }\r
-BFD086FA 0FBE MOVE SP, S8
-BFD086FC 4BE7 LW RA, 28(SP)
-BFD086FE 4BC6 LW S8, 24(SP)
-BFD08700 4C11 ADDIU SP, SP, 32
-BFD08702 459F JR16 RA
-BFD08704 0C00 NOP
+BFD086FA 0FBE MOVE SP, S8\r
+BFD086FC 4BE7 LW RA, 28(SP)\r
+BFD086FE 4BC6 LW S8, 24(SP)\r
+BFD08700 4C11 ADDIU SP, SP, 32\r
+BFD08702 459F JR16 RA\r
+BFD08704 0C00 NOP\r
272: \r
273: /**\r
274: * btmr_set_count - Program timer's counter register.\r
283: */\r
284: void btmr_set_count(uint8_t tmr_id, uint32_t count)\r
285: {\r
-BFD090FC 4FF1 ADDIU SP, SP, -32
-BFD090FE CBE7 SW RA, 28(SP)
-BFD09100 CBC6 SW S8, 24(SP)
-BFD09102 0FDD MOVE S8, SP
-BFD09104 0C44 MOVE V0, A0
-BFD09106 0024F8BE SW A1, 36(S8)
-BFD0910A 0020185E SB V0, 32(S8)
+BFD090FC 4FF1 ADDIU SP, SP, -32\r
+BFD090FE CBE7 SW RA, 28(SP)\r
+BFD09100 CBC6 SW S8, 24(SP)\r
+BFD09102 0FDD MOVE S8, SP\r
+BFD09104 0C44 MOVE V0, A0\r
+BFD09106 0024F8BE SW A1, 36(S8)\r
+BFD0910A 0020185E SB V0, 32(S8)\r
286: BTMR_TypeDef * p;\r
287: \r
288: if (btmr_valid(tmr_id)) {\r
-BFD0910E 0020145E LBU V0, 32(S8)
-BFD09112 0C82 MOVE A0, V0
-BFD09114 4D2277E8 JALS btmr_valid
-BFD09116 4D22 ADDIU T1, T1, 1
-BFD09118 0C00 NOP
-BFD0911A 000D40E2 BEQZC V0, 0xBFD09138
+BFD0910E 0020145E LBU V0, 32(S8)\r
+BFD09112 0C82 MOVE A0, V0\r
+BFD09114 4D2277E8 JALS btmr_valid\r
+BFD09116 4D22 ADDIU T1, T1, 1\r
+BFD09118 0C00 NOP\r
+BFD0911A 000D40E2 BEQZC V0, 0xBFD09138\r
289: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);\r
-BFD0911E 0020145E LBU V0, 32(S8)
-BFD09122 0C82 MOVE A0, V0
-BFD09124 4D3877E8 JALS btmr_get_hw_addr
-BFD09126 4D38 ADDIU T1, T1, -4
-BFD09128 0C00 NOP
-BFD0912A 0010F85E SW V0, 16(S8)
+BFD0911E 0020145E LBU V0, 32(S8)\r
+BFD09122 0C82 MOVE A0, V0\r
+BFD09124 4D3877E8 JALS btmr_get_hw_addr\r
+BFD09126 4D38 ADDIU T1, T1, -4\r
+BFD09128 0C00 NOP\r
+BFD0912A 0010F85E SW V0, 16(S8)\r
290: \r
291: p->COUNT = count;\r
-BFD0912E 0010FC5E LW V0, 16(S8)
-BFD09132 0024FC7E LW V1, 36(S8)
-BFD09136 E9A0 SW V1, 0(V0)
+BFD0912E 0010FC5E LW V0, 16(S8)\r
+BFD09132 0024FC7E LW V1, 36(S8)\r
+BFD09136 E9A0 SW V1, 0(V0)\r
292: }\r
293: }\r
-BFD09138 0FBE MOVE SP, S8
-BFD0913A 4BE7 LW RA, 28(SP)
-BFD0913C 4BC6 LW S8, 24(SP)
-BFD0913E 4C11 ADDIU SP, SP, 32
-BFD09140 459F JR16 RA
-BFD09142 0C00 NOP
+BFD09138 0FBE MOVE SP, S8\r
+BFD0913A 4BE7 LW RA, 28(SP)\r
+BFD0913C 4BC6 LW S8, 24(SP)\r
+BFD0913E 4C11 ADDIU SP, SP, 32\r
+BFD09140 459F JR16 RA\r
+BFD09142 0C00 NOP\r
294: \r
295: /**\r
296: * btmr_count - Return current value of timer's count register.\r
305: */\r
306: uint32_t btmr_count(uint8_t tmr_id)\r
307: {\r
-BFD08D40 4FF1 ADDIU SP, SP, -32
-BFD08D42 CBE7 SW RA, 28(SP)
-BFD08D44 CBC6 SW S8, 24(SP)
-BFD08D46 0FDD MOVE S8, SP
-BFD08D48 0C44 MOVE V0, A0
-BFD08D4A 0020185E SB V0, 32(S8)
+BFD08D40 4FF1 ADDIU SP, SP, -32\r
+BFD08D42 CBE7 SW RA, 28(SP)\r
+BFD08D44 CBC6 SW S8, 24(SP)\r
+BFD08D46 0FDD MOVE S8, SP\r
+BFD08D48 0C44 MOVE V0, A0\r
+BFD08D4A 0020185E SB V0, 32(S8)\r
308: BTMR_TypeDef * p;\r
309: uint32_t cnt;\r
310: \r
311: cnt = 0ul;\r
-BFD08D4E 0010F81E SW ZERO, 16(S8)
+BFD08D4E 0010F81E SW ZERO, 16(S8)\r
312: if ( btmr_valid(tmr_id) ) {\r
-BFD08D52 0020145E LBU V0, 32(S8)
-BFD08D56 0C82 MOVE A0, V0
-BFD08D58 4D2277E8 JALS btmr_valid
-BFD08D5A 4D22 ADDIU T1, T1, 1
-BFD08D5C 0C00 NOP
-BFD08D5E 000D40E2 BEQZC V0, 0xBFD08D7C
+BFD08D52 0020145E LBU V0, 32(S8)\r
+BFD08D56 0C82 MOVE A0, V0\r
+BFD08D58 4D2277E8 JALS btmr_valid\r
+BFD08D5A 4D22 ADDIU T1, T1, 1\r
+BFD08D5C 0C00 NOP\r
+BFD08D5E 000D40E2 BEQZC V0, 0xBFD08D7C\r
313: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);\r
-BFD08D62 0020145E LBU V0, 32(S8)
-BFD08D66 0C82 MOVE A0, V0
-BFD08D68 4D3877E8 JALS btmr_get_hw_addr
-BFD08D6A 4D38 ADDIU T1, T1, -4
-BFD08D6C 0C00 NOP
-BFD08D6E 0014F85E SW V0, 20(S8)
+BFD08D62 0020145E LBU V0, 32(S8)\r
+BFD08D66 0C82 MOVE A0, V0\r
+BFD08D68 4D3877E8 JALS btmr_get_hw_addr\r
+BFD08D6A 4D38 ADDIU T1, T1, -4\r
+BFD08D6C 0C00 NOP\r
+BFD08D6E 0014F85E SW V0, 20(S8)\r
314: cnt = (uint32_t)(p->COUNT);\r
-BFD08D72 0014FC5E LW V0, 20(S8)
-BFD08D76 6920 LW V0, 0(V0)
-BFD08D78 0010F85E SW V0, 16(S8)
+BFD08D72 0014FC5E LW V0, 20(S8)\r
+BFD08D76 6920 LW V0, 0(V0)\r
+BFD08D78 0010F85E SW V0, 16(S8)\r
315: }\r
316: \r
317: return cnt;\r
-BFD08D7C 0010FC5E LW V0, 16(S8)
+BFD08D7C 0010FC5E LW V0, 16(S8)\r
318: }\r
-BFD08D80 0FBE MOVE SP, S8
-BFD08D82 4BE7 LW RA, 28(SP)
-BFD08D84 4BC6 LW S8, 24(SP)
-BFD08D86 4C11 ADDIU SP, SP, 32
-BFD08D88 459F JR16 RA
-BFD08D8A 0C00 NOP
+BFD08D80 0FBE MOVE SP, S8\r
+BFD08D82 4BE7 LW RA, 28(SP)\r
+BFD08D84 4BC6 LW S8, 24(SP)\r
+BFD08D86 4C11 ADDIU SP, SP, 32\r
+BFD08D88 459F JR16 RA\r
+BFD08D8A 0C00 NOP\r
319: \r
320: /**\r
321: * btmr_start - Start timer counting.\r
326: */\r
327: void btmr_start(uint8_t btmr_id)\r
328: {\r
-BFD08D8C 4FF1 ADDIU SP, SP, -32
-BFD08D8E CBE7 SW RA, 28(SP)
-BFD08D90 CBC6 SW S8, 24(SP)
-BFD08D92 0FDD MOVE S8, SP
-BFD08D94 0C44 MOVE V0, A0
-BFD08D96 0020185E SB V0, 32(S8)
+BFD08D8C 4FF1 ADDIU SP, SP, -32\r
+BFD08D8E CBE7 SW RA, 28(SP)\r
+BFD08D90 CBC6 SW S8, 24(SP)\r
+BFD08D92 0FDD MOVE S8, SP\r
+BFD08D94 0C44 MOVE V0, A0\r
+BFD08D96 0020185E SB V0, 32(S8)\r
329: BTMR_TypeDef * p;\r
330: \r
331: if ( btmr_valid(btmr_id) ) {\r
-BFD08D9A 0020145E LBU V0, 32(S8)
-BFD08D9E 0C82 MOVE A0, V0
-BFD08DA0 4D2277E8 JALS btmr_valid
-BFD08DA2 4D22 ADDIU T1, T1, 1
-BFD08DA4 0C00 NOP
-BFD08DA6 001040E2 BEQZC V0, 0xBFD08DCA
+BFD08D9A 0020145E LBU V0, 32(S8)\r
+BFD08D9E 0C82 MOVE A0, V0\r
+BFD08DA0 4D2277E8 JALS btmr_valid\r
+BFD08DA2 4D22 ADDIU T1, T1, 1\r
+BFD08DA4 0C00 NOP\r
+BFD08DA6 001040E2 BEQZC V0, 0xBFD08DCA\r
332: p = (BTMR_TypeDef *)btmr_get_hw_addr(btmr_id);\r
-BFD08DAA 0020145E LBU V0, 32(S8)
-BFD08DAE 0C82 MOVE A0, V0
-BFD08DB0 4D3877E8 JALS btmr_get_hw_addr
-BFD08DB2 4D38 ADDIU T1, T1, -4
-BFD08DB4 0C00 NOP
-BFD08DB6 0010F85E SW V0, 16(S8)
+BFD08DAA 0020145E LBU V0, 32(S8)\r
+BFD08DAE 0C82 MOVE A0, V0\r
+BFD08DB0 4D3877E8 JALS btmr_get_hw_addr\r
+BFD08DB2 4D38 ADDIU T1, T1, -4\r
+BFD08DB4 0C00 NOP\r
+BFD08DB6 0010F85E SW V0, 16(S8)\r
333: p->CONTROL |= BTMR_CNTL_START;\r
-BFD08DBA 0010FC5E LW V0, 16(S8)
-BFD08DBE 6924 LW V0, 16(V0)
-BFD08DC0 00205062 ORI V1, V0, 32
-BFD08DC4 0010FC5E LW V0, 16(S8)
-BFD08DC8 E9A4 SW V1, 16(V0)
+BFD08DBA 0010FC5E LW V0, 16(S8)\r
+BFD08DBE 6924 LW V0, 16(V0)\r
+BFD08DC0 00205062 ORI V1, V0, 32\r
+BFD08DC4 0010FC5E LW V0, 16(S8)\r
+BFD08DC8 E9A4 SW V1, 16(V0)\r
334: }\r
335: }\r
-BFD08DCA 0FBE MOVE SP, S8
-BFD08DCC 4BE7 LW RA, 28(SP)
-BFD08DCE 4BC6 LW S8, 24(SP)
-BFD08DD0 4C11 ADDIU SP, SP, 32
-BFD08DD2 459F JR16 RA
-BFD08DD4 0C00 NOP
+BFD08DCA 0FBE MOVE SP, S8\r
+BFD08DCC 4BE7 LW RA, 28(SP)\r
+BFD08DCE 4BC6 LW S8, 24(SP)\r
+BFD08DD0 4C11 ADDIU SP, SP, 32\r
+BFD08DD2 459F JR16 RA\r
+BFD08DD4 0C00 NOP\r
336: \r
337: /**\r
338: * btmr_stop - Stop timer.\r
345: */\r
346: void btmr_stop(uint8_t tmr_id)\r
347: {\r
-BFD08DD8 4FF1 ADDIU SP, SP, -32
-BFD08DDA CBE7 SW RA, 28(SP)
-BFD08DDC CBC6 SW S8, 24(SP)
-BFD08DDE 0FDD MOVE S8, SP
-BFD08DE0 0C44 MOVE V0, A0
-BFD08DE2 0020185E SB V0, 32(S8)
+BFD08DD8 4FF1 ADDIU SP, SP, -32\r
+BFD08DDA CBE7 SW RA, 28(SP)\r
+BFD08DDC CBC6 SW S8, 24(SP)\r
+BFD08DDE 0FDD MOVE S8, SP\r
+BFD08DE0 0C44 MOVE V0, A0\r
+BFD08DE2 0020185E SB V0, 32(S8)\r
348: BTMR_TypeDef * p;\r
349: \r
350: if (btmr_valid(tmr_id)) {\r
-BFD08DE6 0020145E LBU V0, 32(S8)
-BFD08DEA 0C82 MOVE A0, V0
-BFD08DEC 4D2277E8 JALS btmr_valid
-BFD08DEE 4D22 ADDIU T1, T1, 1
-BFD08DF0 0C00 NOP
-BFD08DF2 001140E2 BEQZC V0, 0xBFD08E18
+BFD08DE6 0020145E LBU V0, 32(S8)\r
+BFD08DEA 0C82 MOVE A0, V0\r
+BFD08DEC 4D2277E8 JALS btmr_valid\r
+BFD08DEE 4D22 ADDIU T1, T1, 1\r
+BFD08DF0 0C00 NOP\r
+BFD08DF2 001140E2 BEQZC V0, 0xBFD08E18\r
351: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);\r
-BFD08DF6 0020145E LBU V0, 32(S8)
-BFD08DFA 0C82 MOVE A0, V0
-BFD08DFC 4D3877E8 JALS btmr_get_hw_addr
-BFD08DFE 4D38 ADDIU T1, T1, -4
-BFD08E00 0C00 NOP
-BFD08E02 0010F85E SW V0, 16(S8)
+BFD08DF6 0020145E LBU V0, 32(S8)\r
+BFD08DFA 0C82 MOVE A0, V0\r
+BFD08DFC 4D3877E8 JALS btmr_get_hw_addr\r
+BFD08DFE 4D38 ADDIU T1, T1, -4\r
+BFD08E00 0C00 NOP\r
+BFD08E02 0010F85E SW V0, 16(S8)\r
352: p->CONTROL &= ~(BTMR_CNTL_START);\r
-BFD08E06 0010FC5E LW V0, 16(S8)
-BFD08E0A 69A4 LW V1, 16(V0)
-BFD08E0C FFDF3040 ADDIU V0, ZERO, -33
-BFD08E0E 449AFFDF LW S8, 17562(RA)
-BFD08E10 449A AND16 V1, V0
-BFD08E12 0010FC5E LW V0, 16(S8)
-BFD08E16 E9A4 SW V1, 16(V0)
+BFD08E06 0010FC5E LW V0, 16(S8)\r
+BFD08E0A 69A4 LW V1, 16(V0)\r
+BFD08E0C FFDF3040 ADDIU V0, ZERO, -33\r
+BFD08E0E 449AFFDF LW S8, 17562(RA)\r
+BFD08E10 449A AND16 V1, V0\r
+BFD08E12 0010FC5E LW V0, 16(S8)\r
+BFD08E16 E9A4 SW V1, 16(V0)\r
353: }\r
354: }\r
-BFD08E18 0FBE MOVE SP, S8
-BFD08E1A 4BE7 LW RA, 28(SP)
-BFD08E1C 4BC6 LW S8, 24(SP)
-BFD08E1E 4C11 ADDIU SP, SP, 32
-BFD08E20 459F JR16 RA
-BFD08E22 0C00 NOP
+BFD08E18 0FBE MOVE SP, S8\r
+BFD08E1A 4BE7 LW RA, 28(SP)\r
+BFD08E1C 4BC6 LW S8, 24(SP)\r
+BFD08E1E 4C11 ADDIU SP, SP, 32\r
+BFD08E20 459F JR16 RA\r
+BFD08E22 0C00 NOP\r
355: \r
356: /**\r
357: * btmr_is_stopped - Return state of timer's START bit.\r
364: */\r
365: uint8_t btmr_is_stopped(uint8_t tmr_id)\r
366: {\r
-BFD083E8 4FF1 ADDIU SP, SP, -32
-BFD083EA CBE7 SW RA, 28(SP)
-BFD083EC CBC6 SW S8, 24(SP)
-BFD083EE 0FDD MOVE S8, SP
-BFD083F0 0C44 MOVE V0, A0
-BFD083F2 0020185E SB V0, 32(S8)
+BFD083E8 4FF1 ADDIU SP, SP, -32\r
+BFD083EA CBE7 SW RA, 28(SP)\r
+BFD083EC CBC6 SW S8, 24(SP)\r
+BFD083EE 0FDD MOVE S8, SP\r
+BFD083F0 0C44 MOVE V0, A0\r
+BFD083F2 0020185E SB V0, 32(S8)\r
367: BTMR_TypeDef * p;\r
368: uint8_t rc;\r
369: \r
370: rc = (MEC14XX_TRUE);\r
-BFD083F6 ED01 LI V0, 1
-BFD083F8 0010185E SB V0, 16(S8)
+BFD083F6 ED01 LI V0, 1\r
+BFD083F8 0010185E SB V0, 16(S8)\r
371: if (btmr_valid(tmr_id)) {\r
-BFD083FC 0020145E LBU V0, 32(S8)
-BFD08400 0C82 MOVE A0, V0
-BFD08402 4D2277E8 JALS btmr_valid
-BFD08404 4D22 ADDIU T1, T1, 1
-BFD08406 0C00 NOP
-BFD08408 001340E2 BEQZC V0, 0xBFD08432
+BFD083FC 0020145E LBU V0, 32(S8)\r
+BFD08400 0C82 MOVE A0, V0\r
+BFD08402 4D2277E8 JALS btmr_valid\r
+BFD08404 4D22 ADDIU T1, T1, 1\r
+BFD08406 0C00 NOP\r
+BFD08408 001340E2 BEQZC V0, 0xBFD08432\r
372: rc = (MEC14XX_FALSE);\r
-BFD0840C 0010181E SB ZERO, 16(S8)
+BFD0840C 0010181E SB ZERO, 16(S8)\r
373: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);\r
-BFD08410 0020145E LBU V0, 32(S8)
-BFD08414 0C82 MOVE A0, V0
-BFD08416 4D3877E8 JALS btmr_get_hw_addr
-BFD08418 4D38 ADDIU T1, T1, -4
-BFD0841A 0C00 NOP
-BFD0841C 0014F85E SW V0, 20(S8)
+BFD08410 0020145E LBU V0, 32(S8)\r
+BFD08414 0C82 MOVE A0, V0\r
+BFD08416 4D3877E8 JALS btmr_get_hw_addr\r
+BFD08418 4D38 ADDIU T1, T1, -4\r
+BFD0841A 0C00 NOP\r
+BFD0841C 0014F85E SW V0, 20(S8)\r
374: if ((p->CONTROL & BTMR_CNTL_START) == 0) {\r
-BFD08420 0014FC5E LW V0, 20(S8)
-BFD08424 6924 LW V0, 16(V0)
-BFD08426 2D2A ANDI V0, V0, 0x20
-BFD08428 000340A2 BNEZC V0, 0xBFD08432
+BFD08420 0014FC5E LW V0, 20(S8)\r
+BFD08424 6924 LW V0, 16(V0)\r
+BFD08426 2D2A ANDI V0, V0, 0x20\r
+BFD08428 000340A2 BNEZC V0, 0xBFD08432\r
375: rc = (MEC14XX_TRUE);\r
-BFD0842C ED01 LI V0, 1
-BFD0842E 0010185E SB V0, 16(S8)
+BFD0842C ED01 LI V0, 1\r
+BFD0842E 0010185E SB V0, 16(S8)\r
376: }\r
377: }\r
378: return rc;\r
-BFD08432 0010145E LBU V0, 16(S8)
+BFD08432 0010145E LBU V0, 16(S8)\r
379: }\r
-BFD08436 0FBE MOVE SP, S8
-BFD08438 4BE7 LW RA, 28(SP)
-BFD0843A 4BC6 LW S8, 24(SP)
-BFD0843C 4C11 ADDIU SP, SP, 32
-BFD0843E 459F JR16 RA
-BFD08440 0C00 NOP
+BFD08436 0FBE MOVE SP, S8\r
+BFD08438 4BE7 LW RA, 28(SP)\r
+BFD0843A 4BC6 LW S8, 24(SP)\r
+BFD0843C 4C11 ADDIU SP, SP, 32\r
+BFD0843E 459F JR16 RA\r
+BFD08440 0C00 NOP\r
380: \r
381: \r
382: /**\r
391: */\r
392: void btmr_halt(uint8_t tmr_id)\r
393: {\r
-BFD08E24 4FF1 ADDIU SP, SP, -32
-BFD08E26 CBE7 SW RA, 28(SP)
-BFD08E28 CBC6 SW S8, 24(SP)
-BFD08E2A 0FDD MOVE S8, SP
-BFD08E2C 0C44 MOVE V0, A0
-BFD08E2E 0020185E SB V0, 32(S8)
+BFD08E24 4FF1 ADDIU SP, SP, -32\r
+BFD08E26 CBE7 SW RA, 28(SP)\r
+BFD08E28 CBC6 SW S8, 24(SP)\r
+BFD08E2A 0FDD MOVE S8, SP\r
+BFD08E2C 0C44 MOVE V0, A0\r
+BFD08E2E 0020185E SB V0, 32(S8)\r
394: BTMR_TypeDef * p;\r
395: \r
396: if ( btmr_valid(tmr_id) ) {\r
-BFD08E32 0020145E LBU V0, 32(S8)
-BFD08E36 0C82 MOVE A0, V0
-BFD08E38 4D2277E8 JALS btmr_valid
-BFD08E3A 4D22 ADDIU T1, T1, 1
-BFD08E3C 0C00 NOP
-BFD08E3E 001040E2 BEQZC V0, 0xBFD08E62
+BFD08E32 0020145E LBU V0, 32(S8)\r
+BFD08E36 0C82 MOVE A0, V0\r
+BFD08E38 4D2277E8 JALS btmr_valid\r
+BFD08E3A 4D22 ADDIU T1, T1, 1\r
+BFD08E3C 0C00 NOP\r
+BFD08E3E 001040E2 BEQZC V0, 0xBFD08E62\r
397: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);\r
-BFD08E42 0020145E LBU V0, 32(S8)
-BFD08E46 0C82 MOVE A0, V0
-BFD08E48 4D3877E8 JALS btmr_get_hw_addr
-BFD08E4A 4D38 ADDIU T1, T1, -4
-BFD08E4C 0C00 NOP
-BFD08E4E 0010F85E SW V0, 16(S8)
+BFD08E42 0020145E LBU V0, 32(S8)\r
+BFD08E46 0C82 MOVE A0, V0\r
+BFD08E48 4D3877E8 JALS btmr_get_hw_addr\r
+BFD08E4A 4D38 ADDIU T1, T1, -4\r
+BFD08E4C 0C00 NOP\r
+BFD08E4E 0010F85E SW V0, 16(S8)\r
398: p->CONTROL |= (BTMR_CNTL_HALT);\r
-BFD08E52 0010FC5E LW V0, 16(S8)
-BFD08E56 6924 LW V0, 16(V0)
-BFD08E58 00805062 ORI V1, V0, 128
-BFD08E5C 0010FC5E LW V0, 16(S8)
-BFD08E60 E9A4 SW V1, 16(V0)
+BFD08E52 0010FC5E LW V0, 16(S8)\r
+BFD08E56 6924 LW V0, 16(V0)\r
+BFD08E58 00805062 ORI V1, V0, 128\r
+BFD08E5C 0010FC5E LW V0, 16(S8)\r
+BFD08E60 E9A4 SW V1, 16(V0)\r
399: }\r
400: }\r
-BFD08E62 0FBE MOVE SP, S8
-BFD08E64 4BE7 LW RA, 28(SP)
-BFD08E66 4BC6 LW S8, 24(SP)
-BFD08E68 4C11 ADDIU SP, SP, 32
-BFD08E6A 459F JR16 RA
-BFD08E6C 0C00 NOP
+BFD08E62 0FBE MOVE SP, S8\r
+BFD08E64 4BE7 LW RA, 28(SP)\r
+BFD08E66 4BC6 LW S8, 24(SP)\r
+BFD08E68 4C11 ADDIU SP, SP, 32\r
+BFD08E6A 459F JR16 RA\r
+BFD08E6C 0C00 NOP\r
401: \r
402: \r
403: /**\r
409: */\r
410: void btmr_unhalt(uint8_t tmr_id)\r
411: {\r
-BFD08E70 4FF1 ADDIU SP, SP, -32
-BFD08E72 CBE7 SW RA, 28(SP)
-BFD08E74 CBC6 SW S8, 24(SP)
-BFD08E76 0FDD MOVE S8, SP
-BFD08E78 0C44 MOVE V0, A0
-BFD08E7A 0020185E SB V0, 32(S8)
+BFD08E70 4FF1 ADDIU SP, SP, -32\r
+BFD08E72 CBE7 SW RA, 28(SP)\r
+BFD08E74 CBC6 SW S8, 24(SP)\r
+BFD08E76 0FDD MOVE S8, SP\r
+BFD08E78 0C44 MOVE V0, A0\r
+BFD08E7A 0020185E SB V0, 32(S8)\r
412: BTMR_TypeDef * p;\r
413: \r
414: if ( btmr_valid(tmr_id) ) {\r
-BFD08E7E 0020145E LBU V0, 32(S8)
-BFD08E82 0C82 MOVE A0, V0
-BFD08E84 4D2277E8 JALS btmr_valid
-BFD08E86 4D22 ADDIU T1, T1, 1
-BFD08E88 0C00 NOP
-BFD08E8A 001140E2 BEQZC V0, 0xBFD08EB0
+BFD08E7E 0020145E LBU V0, 32(S8)\r
+BFD08E82 0C82 MOVE A0, V0\r
+BFD08E84 4D2277E8 JALS btmr_valid\r
+BFD08E86 4D22 ADDIU T1, T1, 1\r
+BFD08E88 0C00 NOP\r
+BFD08E8A 001140E2 BEQZC V0, 0xBFD08EB0\r
415: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);\r
-BFD08E8E 0020145E LBU V0, 32(S8)
-BFD08E92 0C82 MOVE A0, V0
-BFD08E94 4D3877E8 JALS btmr_get_hw_addr
-BFD08E96 4D38 ADDIU T1, T1, -4
-BFD08E98 0C00 NOP
-BFD08E9A 0010F85E SW V0, 16(S8)
+BFD08E8E 0020145E LBU V0, 32(S8)\r
+BFD08E92 0C82 MOVE A0, V0\r
+BFD08E94 4D3877E8 JALS btmr_get_hw_addr\r
+BFD08E96 4D38 ADDIU T1, T1, -4\r
+BFD08E98 0C00 NOP\r
+BFD08E9A 0010F85E SW V0, 16(S8)\r
416: p->CONTROL &= ~(BTMR_CNTL_HALT);\r
-BFD08E9E 0010FC5E LW V0, 16(S8)
-BFD08EA2 69A4 LW V1, 16(V0)
-BFD08EA4 FF7F3040 ADDIU V0, ZERO, -129
-BFD08EA6 449AFF7F LW K1, 17562(RA)
-BFD08EA8 449A AND16 V1, V0
-BFD08EAA 0010FC5E LW V0, 16(S8)
-BFD08EAE E9A4 SW V1, 16(V0)
+BFD08E9E 0010FC5E LW V0, 16(S8)\r
+BFD08EA2 69A4 LW V1, 16(V0)\r
+BFD08EA4 FF7F3040 ADDIU V0, ZERO, -129\r
+BFD08EA6 449AFF7F LW K1, 17562(RA)\r
+BFD08EA8 449A AND16 V1, V0\r
+BFD08EAA 0010FC5E LW V0, 16(S8)\r
+BFD08EAE E9A4 SW V1, 16(V0)\r
417: }\r
418: }\r
-BFD08EB0 0FBE MOVE SP, S8
-BFD08EB2 4BE7 LW RA, 28(SP)
-BFD08EB4 4BC6 LW S8, 24(SP)
-BFD08EB6 4C11 ADDIU SP, SP, 32
-BFD08EB8 459F JR16 RA
-BFD08EBA 0C00 NOP
+BFD08EB0 0FBE MOVE SP, S8\r
+BFD08EB2 4BE7 LW RA, 28(SP)\r
+BFD08EB4 4BC6 LW S8, 24(SP)\r
+BFD08EB6 4C11 ADDIU SP, SP, 32\r
+BFD08EB8 459F JR16 RA\r
+BFD08EBA 0C00 NOP\r
419: \r
420: \r
421: /* end mec14xx_timers.c */\r
422: /** @}\r
423: */\r
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/mec14xx_tfdp.c ---------
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/mec14xx_tfdp.c ---------\r
1: /*****************************************************************************\r
2: * © 2014 Microchip Technology Inc. and its subsidiaries.\r
3: * You may use this software and any derivatives exclusively with\r
46: \r
47: static void tfdp_xmit_header(uint16_t nbr)\r
48: {\r
-BFD0906C 4FB0 ADDIU SP, SP, -8
-BFD0906E CBC1 SW S8, 4(SP)
-BFD09070 0FDD MOVE S8, SP
-BFD09072 0C44 MOVE V0, A0
-BFD09074 0008385E SH V0, 8(S8)
+BFD0906C 4FB0 ADDIU SP, SP, -8\r
+BFD0906E CBC1 SW S8, 4(SP)\r
+BFD09070 0FDD MOVE S8, SP\r
+BFD09072 0C44 MOVE V0, A0\r
+BFD09074 0008385E SH V0, 8(S8)\r
49: TFDP->DATA = TFDP_FRAME_START;\r
-BFD09078 A00041A2 LUI V0, 0xA000
-BFD0907C 8C005042 ORI V0, V0, -29696
-BFD0907E 8C00 BEQZ S0, 0xBFD09080
-BFD09080 FFFD3060 ADDIU V1, ZERO, -3
-BFD09082 89A0FFFD LW RA, -30304(SP)
-BFD09084 89A0 SB V1, 0(V0)
+BFD09078 A00041A2 LUI V0, 0xA000\r
+BFD0907C 8C005042 ORI V0, V0, -29696\r
+BFD0907E 8C00 BEQZ S0, 0xBFD09080\r
+BFD09080 FFFD3060 ADDIU V1, ZERO, -3\r
+BFD09082 89A0FFFD LW RA, -30304(SP)\r
+BFD09084 89A0 SB V1, 0(V0)\r
50: TFDP_DELAY();\r
51: \r
52: TFDP->DATA = (uint8_t)nbr;\r
-BFD09086 A00041A2 LUI V0, 0xA000
-BFD0908A 8C005042 ORI V0, V0, -29696
-BFD0908C 8C00 BEQZ S0, 0xBFD0908E
-BFD0908E 0008347E LHU V1, 8(S8)
-BFD09092 2DBD ANDI V1, V1, 0xFF
-BFD09094 89A0 SB V1, 0(V0)
+BFD09086 A00041A2 LUI V0, 0xA000\r
+BFD0908A 8C005042 ORI V0, V0, -29696\r
+BFD0908C 8C00 BEQZ S0, 0xBFD0908E\r
+BFD0908E 0008347E LHU V1, 8(S8)\r
+BFD09092 2DBD ANDI V1, V1, 0xFF\r
+BFD09094 89A0 SB V1, 0(V0)\r
53: TFDP_DELAY();\r
54: TFDP->DATA = (uint8_t)(nbr >> 8);\r
-BFD09096 A00041A2 LUI V0, 0xA000
-BFD0909A 8C005042 ORI V0, V0, -29696
-BFD0909C 8C00 BEQZ S0, 0xBFD0909E
-BFD0909E 0008347E LHU V1, 8(S8)
-BFD090A2 25B1 SRL V1, V1, 8
-BFD090A4 2DBF ANDI V1, V1, 0xFFFF
-BFD090A6 2DBD ANDI V1, V1, 0xFF
-BFD090A8 89A0 SB V1, 0(V0)
+BFD09096 A00041A2 LUI V0, 0xA000\r
+BFD0909A 8C005042 ORI V0, V0, -29696\r
+BFD0909C 8C00 BEQZ S0, 0xBFD0909E\r
+BFD0909E 0008347E LHU V1, 8(S8)\r
+BFD090A2 25B1 SRL V1, V1, 8\r
+BFD090A4 2DBF ANDI V1, V1, 0xFFFF\r
+BFD090A6 2DBD ANDI V1, V1, 0xFF\r
+BFD090A8 89A0 SB V1, 0(V0)\r
55: TFDP_DELAY();\r
56: }\r
-BFD090AA 0FBE MOVE SP, S8
-BFD090AC 4BC1 LW S8, 4(SP)
-BFD090AE 4C05 ADDIU SP, SP, 8
-BFD090B0 459F JR16 RA
-BFD090B2 0C00 NOP
+BFD090AA 0FBE MOVE SP, S8\r
+BFD090AC 4BC1 LW S8, 4(SP)\r
+BFD090AE 4C05 ADDIU SP, SP, 8\r
+BFD090B0 459F JR16 RA\r
+BFD090B2 0C00 NOP\r
57: \r
58: \r
59: static void tfdp_xmit_hword(uint16_t hword)\r
60: {\r
-BFD09648 4FB0 ADDIU SP, SP, -8
-BFD0964A CBC1 SW S8, 4(SP)
-BFD0964C 0FDD MOVE S8, SP
-BFD0964E 0C44 MOVE V0, A0
-BFD09650 0008385E SH V0, 8(S8)
+BFD09648 4FB0 ADDIU SP, SP, -8\r
+BFD0964A CBC1 SW S8, 4(SP)\r
+BFD0964C 0FDD MOVE S8, SP\r
+BFD0964E 0C44 MOVE V0, A0\r
+BFD09650 0008385E SH V0, 8(S8)\r
61: TFDP->DATA = (uint8_t)hword;\r
-BFD09654 A00041A2 LUI V0, 0xA000
-BFD09658 8C005042 ORI V0, V0, -29696
-BFD0965A 8C00 BEQZ S0, 0xBFD0965C
-BFD0965C 0008347E LHU V1, 8(S8)
-BFD09660 2DBD ANDI V1, V1, 0xFF
-BFD09662 89A0 SB V1, 0(V0)
+BFD09654 A00041A2 LUI V0, 0xA000\r
+BFD09658 8C005042 ORI V0, V0, -29696\r
+BFD0965A 8C00 BEQZ S0, 0xBFD0965C\r
+BFD0965C 0008347E LHU V1, 8(S8)\r
+BFD09660 2DBD ANDI V1, V1, 0xFF\r
+BFD09662 89A0 SB V1, 0(V0)\r
62: TFDP_DELAY();\r
63: TFDP->DATA = (uint8_t)(hword >> 8);\r
-BFD09664 A00041A2 LUI V0, 0xA000
-BFD09668 8C005042 ORI V0, V0, -29696
-BFD0966A 8C00 BEQZ S0, 0xBFD0966C
-BFD0966C 0008347E LHU V1, 8(S8)
-BFD09670 25B1 SRL V1, V1, 8
-BFD09672 2DBF ANDI V1, V1, 0xFFFF
-BFD09674 2DBD ANDI V1, V1, 0xFF
-BFD09676 89A0 SB V1, 0(V0)
+BFD09664 A00041A2 LUI V0, 0xA000\r
+BFD09668 8C005042 ORI V0, V0, -29696\r
+BFD0966A 8C00 BEQZ S0, 0xBFD0966C\r
+BFD0966C 0008347E LHU V1, 8(S8)\r
+BFD09670 25B1 SRL V1, V1, 8\r
+BFD09672 2DBF ANDI V1, V1, 0xFFFF\r
+BFD09674 2DBD ANDI V1, V1, 0xFF\r
+BFD09676 89A0 SB V1, 0(V0)\r
64: TFDP_DELAY();\r
65: }\r
-BFD09678 0FBE MOVE SP, S8
-BFD0967A 4BC1 LW S8, 4(SP)
-BFD0967C 4C05 ADDIU SP, SP, 8
-BFD0967E 459F JR16 RA
-BFD09680 0C00 NOP
+BFD09678 0FBE MOVE SP, S8\r
+BFD0967A 4BC1 LW S8, 4(SP)\r
+BFD0967C 4C05 ADDIU SP, SP, 8\r
+BFD0967E 459F JR16 RA\r
+BFD09680 0C00 NOP\r
66: \r
67: \r
68: static void tfdp_xmit_word(uint32_t word)\r
69: {\r
-BFD08CF4 4FF9 ADDIU SP, SP, -16
-BFD08CF6 CBC3 SW S8, 12(SP)
-BFD08CF8 0FDD MOVE S8, SP
-BFD08CFA 0010F89E SW A0, 16(S8)
+BFD08CF4 4FF9 ADDIU SP, SP, -16\r
+BFD08CF6 CBC3 SW S8, 12(SP)\r
+BFD08CF8 0FDD MOVE S8, SP\r
+BFD08CFA 0010F89E SW A0, 16(S8)\r
70: uint8_t i;\r
71: \r
72: for (i = 0u; i < 4; i++) {\r
-BFD08CFE 0000181E SB ZERO, 0(S8)
-BFD08D02 CC13 B 0xBFD08D2A
-BFD08D04 0C00 NOP
-BFD08D20 0000145E LBU V0, 0(S8)
-BFD08D24 6D20 ADDIU V0, V0, 1
-BFD08D26 0000185E SB V0, 0(S8)
-BFD08D2A 0000145E LBU V0, 0(S8)
-BFD08D2E 0004B042 SLTIU V0, V0, 4
-BFD08D32 FFE840A2 BNEZC V0, 0xBFD08D06
-BFD08D34 0FBEFFE8 LW RA, 4030(T0)
+BFD08CFE 0000181E SB ZERO, 0(S8)\r
+BFD08D02 CC13 B 0xBFD08D2A\r
+BFD08D04 0C00 NOP\r
+BFD08D20 0000145E LBU V0, 0(S8)\r
+BFD08D24 6D20 ADDIU V0, V0, 1\r
+BFD08D26 0000185E SB V0, 0(S8)\r
+BFD08D2A 0000145E LBU V0, 0(S8)\r
+BFD08D2E 0004B042 SLTIU V0, V0, 4\r
+BFD08D32 FFE840A2 BNEZC V0, 0xBFD08D06\r
+BFD08D34 0FBEFFE8 LW RA, 4030(T0)\r
73: TFDP->DATA = (uint8_t)word;\r
-BFD08D06 A00041A2 LUI V0, 0xA000
-BFD08D0A 8C005042 ORI V0, V0, -29696
-BFD08D0C 8C00 BEQZ S0, 0xBFD08D0E
-BFD08D0E 0010FC7E LW V1, 16(S8)
-BFD08D12 2DBD ANDI V1, V1, 0xFF
-BFD08D14 89A0 SB V1, 0(V0)
+BFD08D06 A00041A2 LUI V0, 0xA000\r
+BFD08D0A 8C005042 ORI V0, V0, -29696\r
+BFD08D0C 8C00 BEQZ S0, 0xBFD08D0E\r
+BFD08D0E 0010FC7E LW V1, 16(S8)\r
+BFD08D12 2DBD ANDI V1, V1, 0xFF\r
+BFD08D14 89A0 SB V1, 0(V0)\r
74: word >>= 8; \r
-BFD08D16 0010FC5E LW V0, 16(S8)
-BFD08D1A 2521 SRL V0, V0, 8
-BFD08D1C 0010F85E SW V0, 16(S8)
+BFD08D16 0010FC5E LW V0, 16(S8)\r
+BFD08D1A 2521 SRL V0, V0, 8\r
+BFD08D1C 0010F85E SW V0, 16(S8)\r
75: TFDP_DELAY();\r
76: }\r
77: }\r
-BFD08D36 0FBE MOVE SP, S8
-BFD08D38 4BC3 LW S8, 12(SP)
-BFD08D3A 4C09 ADDIU SP, SP, 16
-BFD08D3C 459F JR16 RA
-BFD08D3E 0C00 NOP
+BFD08D36 0FBE MOVE SP, S8\r
+BFD08D38 4BC3 LW S8, 12(SP)\r
+BFD08D3A 4C09 ADDIU SP, SP, 16\r
+BFD08D3C 459F JR16 RA\r
+BFD08D3E 0C00 NOP\r
78: \r
79: \r
80: /**\r
87: */\r
88: void tfdp_sleep_en(uint8_t sleep_en)\r
89: {\r
-BFD088AC 4FB0 ADDIU SP, SP, -8
-BFD088AE CBC1 SW S8, 4(SP)
-BFD088B0 0FDD MOVE S8, SP
-BFD088B2 0C44 MOVE V0, A0
-BFD088B4 0008185E SB V0, 8(S8)
+BFD088AC 4FB0 ADDIU SP, SP, -8\r
+BFD088AE CBC1 SW S8, 4(SP)\r
+BFD088B0 0FDD MOVE S8, SP\r
+BFD088B2 0C44 MOVE V0, A0\r
+BFD088B4 0008185E SB V0, 8(S8)\r
90: if ( sleep_en ) {\r
-BFD088B8 0008145E LBU V0, 8(S8)
-BFD088BC 000E40E2 BEQZC V0, 0xBFD088DC
+BFD088B8 0008145E LBU V0, 8(S8)\r
+BFD088BC 000E40E2 BEQZC V0, 0xBFD088DC\r
91: PCR->EC_SLEEP_EN |= (PCR_EC_TFDP_SLP_CLK);\r
-BFD088C0 A00841A2 LUI V0, 0xA008
-BFD088C4 01005042 ORI V0, V0, 256
-BFD088C8 A00841A3 LUI V1, 0xA008
-BFD088CC 01005063 ORI V1, V1, 256
-BFD088D0 69B2 LW V1, 8(V1)
-BFD088D2 00805063 ORI V1, V1, 128
-BFD088D6 E9A2 SW V1, 8(V0)
-BFD088D8 CC0E B 0xBFD088F6
-BFD088DA 0C00 NOP
+BFD088C0 A00841A2 LUI V0, 0xA008\r
+BFD088C4 01005042 ORI V0, V0, 256\r
+BFD088C8 A00841A3 LUI V1, 0xA008\r
+BFD088CC 01005063 ORI V1, V1, 256\r
+BFD088D0 69B2 LW V1, 8(V1)\r
+BFD088D2 00805063 ORI V1, V1, 128\r
+BFD088D6 E9A2 SW V1, 8(V0)\r
+BFD088D8 CC0E B 0xBFD088F6\r
+BFD088DA 0C00 NOP\r
92: } else {\r
93: PCR->EC_SLEEP_EN &= ~(PCR_EC_TFDP_SLP_CLK);\r
-BFD088DC A00841A2 LUI V0, 0xA008
-BFD088E0 01005042 ORI V0, V0, 256
-BFD088E4 A00841A3 LUI V1, 0xA008
-BFD088E8 01005063 ORI V1, V1, 256
-BFD088EC 6A32 LW A0, 8(V1)
-BFD088EE FF7F3060 ADDIU V1, ZERO, -129
-BFD088F0 449CFF7F LW K1, 17564(RA)
-BFD088F2 449C AND16 V1, A0
-BFD088F4 E9A2 SW V1, 8(V0)
+BFD088DC A00841A2 LUI V0, 0xA008\r
+BFD088E0 01005042 ORI V0, V0, 256\r
+BFD088E4 A00841A3 LUI V1, 0xA008\r
+BFD088E8 01005063 ORI V1, V1, 256\r
+BFD088EC 6A32 LW A0, 8(V1)\r
+BFD088EE FF7F3060 ADDIU V1, ZERO, -129\r
+BFD088F0 449CFF7F LW K1, 17564(RA)\r
+BFD088F2 449C AND16 V1, A0\r
+BFD088F4 E9A2 SW V1, 8(V0)\r
94: }\r
95: }\r
-BFD088F6 0FBE MOVE SP, S8
-BFD088F8 4BC1 LW S8, 4(SP)
-BFD088FA 4C05 ADDIU SP, SP, 8
-BFD088FC 459F JR16 RA
-BFD088FE 0C00 NOP
+BFD088F6 0FBE MOVE SP, S8\r
+BFD088F8 4BC1 LW S8, 4(SP)\r
+BFD088FA 4C05 ADDIU SP, SP, 8\r
+BFD088FC 459F JR16 RA\r
+BFD088FE 0C00 NOP\r
96: \r
97: \r
98: /**\r
105: */\r
106: void tfdp_enable(uint8_t en, uint8_t pin_cfg)\r
107: {\r
-BFD032C4 4FF9 ADDIU SP, SP, -16
-BFD032C6 CBC3 SW S8, 12(SP)
-BFD032C8 0FDD MOVE S8, SP
-BFD032CA 0C64 MOVE V1, A0
-BFD032CC 0C45 MOVE V0, A1
-BFD032CE 0010187E SB V1, 16(S8)
-BFD032D2 0014185E SB V0, 20(S8)
+BFD032C4 4FF9 ADDIU SP, SP, -16\r
+BFD032C6 CBC3 SW S8, 12(SP)\r
+BFD032C8 0FDD MOVE S8, SP\r
+BFD032CA 0C64 MOVE V1, A0\r
+BFD032CC 0C45 MOVE V0, A1\r
+BFD032CE 0010187E SB V1, 16(S8)\r
+BFD032D2 0014185E SB V0, 20(S8)\r
108: uint32_t delay;\r
109: \r
110: if (en) {\r
-BFD032D6 0010145E LBU V0, 16(S8)
-BFD032DA 007240E2 BEQZC V0, 0xBFD033C2
+BFD032D6 0010145E LBU V0, 16(S8)\r
+BFD032DA 007240E2 BEQZC V0, 0xBFD033C2\r
111: \r
112: if (pin_cfg) {\r
-BFD032DE 0014145E LBU V0, 20(S8)
-BFD032E2 006740E2 BEQZC V0, 0xBFD033B4
+BFD032DE 0014145E LBU V0, 20(S8)\r
+BFD032E2 006740E2 BEQZC V0, 0xBFD033B4\r
113: // Input with AltOut=1 to drive high when switched to output\r
114: GPIO_CTRL->REG[TFDP_PIN_1].w = (1ul << 16);\r
-BFD032E6 A00841A2 LUI V0, 0xA008
-BFD032EA 10005042 ORI V0, V0, 4096
-BFD032EC 41A31000 ADDI ZERO, ZERO, 16803
-BFD032EE 000141A3 LUI V1, 0x1
-BFD032F2 0138F862 SW V1, 312(V0)
+BFD032E6 A00841A2 LUI V0, 0xA008\r
+BFD032EA 10005042 ORI V0, V0, 4096\r
+BFD032EC 41A31000 ADDI ZERO, ZERO, 16803\r
+BFD032EE 000141A3 LUI V1, 0x1\r
+BFD032F2 0138F862 SW V1, 312(V0)\r
115: GPIO_CTRL->REG[TFDP_PIN_2].w = (1ul << 16);\r
-BFD032F6 A00841A2 LUI V0, 0xA008
-BFD032FA 10005042 ORI V0, V0, 4096
-BFD032FC 41A31000 ADDI ZERO, ZERO, 16803
-BFD032FE 000141A3 LUI V1, 0x1
-BFD03302 013CF862 SW V1, 316(V0)
-BFD03304 3040013C SRL T1, GP, 6
+BFD032F6 A00841A2 LUI V0, 0xA008\r
+BFD032FA 10005042 ORI V0, V0, 4096\r
+BFD032FC 41A31000 ADDI ZERO, ZERO, 16803\r
+BFD032FE 000141A3 LUI V1, 0x1\r
+BFD03302 013CF862 SW V1, 316(V0)\r
+BFD03304 3040013C SRL T1, GP, 6\r
116: \r
117: delay = 128;\r
-BFD03306 00803040 ADDIU V0, ZERO, 128
-BFD0330A 0000F85E SW V0, 0(S8)
+BFD03306 00803040 ADDIU V0, ZERO, 128\r
+BFD0330A 0000F85E SW V0, 0(S8)\r
118: while ( delay-- )\r
-BFD0330E CC03 B 0xBFD03316
-BFD03310 0C00 NOP
-BFD03316 0000FC5E LW V0, 0(S8)
-BFD03318 00400000 SRL ZERO, ZERO, 0
-BFD0331A 13900040 SLTU V0, ZERO, V0
-BFD0331C 2D2D1390 ADDI GP, S0, 11565
-BFD0331E 2D2D ANDI V0, V0, 0xFF
-BFD03320 0000FC7E LW V1, 0(S8)
-BFD03324 6DBE ADDIU V1, V1, -1
-BFD03326 0000F87E SW V1, 0(S8)
-BFD0332A FFF240A2 BNEZC V0, 0xBFD03312
-BFD0332C 41A2FFF2 LW RA, 16802(S2)
+BFD0330E CC03 B 0xBFD03316\r
+BFD03310 0C00 NOP\r
+BFD03316 0000FC5E LW V0, 0(S8)\r
+BFD03318 00400000 SRL ZERO, ZERO, 0\r
+BFD0331A 13900040 SLTU V0, ZERO, V0\r
+BFD0331C 2D2D1390 ADDI GP, S0, 11565\r
+BFD0331E 2D2D ANDI V0, V0, 0xFF\r
+BFD03320 0000FC7E LW V1, 0(S8)\r
+BFD03324 6DBE ADDIU V1, V1, -1\r
+BFD03326 0000F87E SW V1, 0(S8)\r
+BFD0332A FFF240A2 BNEZC V0, 0xBFD03312\r
+BFD0332C 41A2FFF2 LW RA, 16802(S2)\r
119: {\r
120: CPU_NOP();\r
-BFD03312 08000000 SSNOP
-BFD03314 0800 LBU S0, 0(S0)
+BFD03312 08000000 SSNOP\r
+BFD03314 0800 LBU S0, 0(S0)\r
121: }\r
122: \r
123: // GPIO Output enabled (drive based on above settings)\r
124: GPIO_CTRL->REG[TFDP_PIN_1].w |= (1ul << 9);\r
-BFD0332E A00841A2 LUI V0, 0xA008
-BFD03332 10005042 ORI V0, V0, 4096
-BFD03334 41A31000 ADDI ZERO, ZERO, 16803
-BFD03336 A00841A3 LUI V1, 0xA008
-BFD0333A 10005063 ORI V1, V1, 4096
-BFD0333C FC631000 ADDI ZERO, ZERO, -925
-BFD0333E 0138FC63 LW V1, 312(V1)
-BFD03342 02005063 ORI V1, V1, 512
-BFD03346 0138F862 SW V1, 312(V0)
+BFD0332E A00841A2 LUI V0, 0xA008\r
+BFD03332 10005042 ORI V0, V0, 4096\r
+BFD03334 41A31000 ADDI ZERO, ZERO, 16803\r
+BFD03336 A00841A3 LUI V1, 0xA008\r
+BFD0333A 10005063 ORI V1, V1, 4096\r
+BFD0333C FC631000 ADDI ZERO, ZERO, -925\r
+BFD0333E 0138FC63 LW V1, 312(V1)\r
+BFD03342 02005063 ORI V1, V1, 512\r
+BFD03346 0138F862 SW V1, 312(V0)\r
125: GPIO_CTRL->REG[TFDP_PIN_2].w |= (1ul << 9);\r
-BFD0334A A00841A2 LUI V0, 0xA008
-BFD0334E 10005042 ORI V0, V0, 4096
-BFD03350 41A31000 ADDI ZERO, ZERO, 16803
-BFD03352 A00841A3 LUI V1, 0xA008
-BFD03356 10005063 ORI V1, V1, 4096
-BFD03358 FC631000 ADDI ZERO, ZERO, -925
-BFD0335A 013CFC63 LW V1, 316(V1)
-BFD0335E 02005063 ORI V1, V1, 512
-BFD03362 013CF862 SW V1, 316(V0)
-BFD03364 3040013C SRL T1, GP, 6
+BFD0334A A00841A2 LUI V0, 0xA008\r
+BFD0334E 10005042 ORI V0, V0, 4096\r
+BFD03350 41A31000 ADDI ZERO, ZERO, 16803\r
+BFD03352 A00841A3 LUI V1, 0xA008\r
+BFD03356 10005063 ORI V1, V1, 4096\r
+BFD03358 FC631000 ADDI ZERO, ZERO, -925\r
+BFD0335A 013CFC63 LW V1, 316(V1)\r
+BFD0335E 02005063 ORI V1, V1, 512\r
+BFD03362 013CF862 SW V1, 316(V0)\r
+BFD03364 3040013C SRL T1, GP, 6\r
126: \r
127: delay = 128;\r
-BFD03366 00803040 ADDIU V0, ZERO, 128
+BFD03366 00803040 ADDIU V0, ZERO, 128\r
128: while ( delay-- )\r
-BFD0336A CC04 B 0xBFD03374
-BFD0336C 0000F85E SW V0, 0(S8)
-BFD0336E 00000000 NOP
-BFD03374 0000FC5E LW V0, 0(S8)
-BFD03376 00400000 SRL ZERO, ZERO, 0
-BFD03378 13900040 SLTU V0, ZERO, V0
-BFD0337A 2D2D1390 ADDI GP, S0, 11565
-BFD0337C 2D2D ANDI V0, V0, 0xFF
-BFD0337E 0000FC7E LW V1, 0(S8)
-BFD03382 6DBE ADDIU V1, V1, -1
-BFD03384 0000F87E SW V1, 0(S8)
-BFD03388 FFF240A2 BNEZC V0, 0xBFD03370
-BFD0338A 41A2FFF2 LW RA, 16802(S2)
+BFD0336A CC04 B 0xBFD03374\r
+BFD0336C 0000F85E SW V0, 0(S8)\r
+BFD0336E 00000000 NOP\r
+BFD03374 0000FC5E LW V0, 0(S8)\r
+BFD03376 00400000 SRL ZERO, ZERO, 0\r
+BFD03378 13900040 SLTU V0, ZERO, V0\r
+BFD0337A 2D2D1390 ADDI GP, S0, 11565\r
+BFD0337C 2D2D ANDI V0, V0, 0xFF\r
+BFD0337E 0000FC7E LW V1, 0(S8)\r
+BFD03382 6DBE ADDIU V1, V1, -1\r
+BFD03384 0000F87E SW V1, 0(S8)\r
+BFD03388 FFF240A2 BNEZC V0, 0xBFD03370\r
+BFD0338A 41A2FFF2 LW RA, 16802(S2)\r
129: {\r
130: CPU_NOP();\r
-BFD03370 08000000 SSNOP
-BFD03372 0800 LBU S0, 0(S0)
+BFD03370 08000000 SSNOP\r
+BFD03372 0800 LBU S0, 0(S0)\r
131: }\r
132: \r
133: // Switch to Function 1 (TFDP mode b[13:12]=01b)\r
134: GPIO_CTRL->REG[TFDP_PIN_1].w = (1ul << 16) + (1ul << 12);\r
-BFD0338C A00841A2 LUI V0, 0xA008
-BFD03390 10005042 ORI V0, V0, 4096
-BFD03392 41A31000 ADDI ZERO, ZERO, 16803
-BFD03394 000141A3 LUI V1, 0x1
-BFD03398 10005063 ORI V1, V1, 4096
-BFD0339A F8621000 ADDI ZERO, ZERO, -1950
-BFD0339C 0138F862 SW V1, 312(V0)
+BFD0338C A00841A2 LUI V0, 0xA008\r
+BFD03390 10005042 ORI V0, V0, 4096\r
+BFD03392 41A31000 ADDI ZERO, ZERO, 16803\r
+BFD03394 000141A3 LUI V1, 0x1\r
+BFD03398 10005063 ORI V1, V1, 4096\r
+BFD0339A F8621000 ADDI ZERO, ZERO, -1950\r
+BFD0339C 0138F862 SW V1, 312(V0)\r
135: GPIO_CTRL->REG[TFDP_PIN_2].w = (1ul << 16) + (1ul << 12);\r
-BFD033A0 A00841A2 LUI V0, 0xA008
-BFD033A4 10005042 ORI V0, V0, 4096
-BFD033A6 41A31000 ADDI ZERO, ZERO, 16803
-BFD033A8 000141A3 LUI V1, 0x1
-BFD033AC 10005063 ORI V1, V1, 4096
-BFD033AE F8621000 ADDI ZERO, ZERO, -1950
-BFD033B0 013CF862 SW V1, 316(V0)
+BFD033A0 A00841A2 LUI V0, 0xA008\r
+BFD033A4 10005042 ORI V0, V0, 4096\r
+BFD033A6 41A31000 ADDI ZERO, ZERO, 16803\r
+BFD033A8 000141A3 LUI V1, 0x1\r
+BFD033AC 10005063 ORI V1, V1, 4096\r
+BFD033AE F8621000 ADDI ZERO, ZERO, -1950\r
+BFD033B0 013CF862 SW V1, 316(V0)\r
136: \r
137: }\r
138: /* b[0]=1(Enable)\r
141: * b[6:4]=000b 1 clock inter-packet delay\r
142: */\r
143: TFDP->CONTROL = 0x01u;\r
-BFD033B4 A00041A2 LUI V0, 0xA000
-BFD033B8 8C005042 ORI V0, V0, -29696
-BFD033BA 8C00 BEQZ S0, 0xBFD033BC
-BFD033BC ED81 LI V1, 1
-BFD033BE CC16 B 0xBFD033EC
-BFD033C0 89A4 SB V1, 4(V0)
+BFD033B4 A00041A2 LUI V0, 0xA000\r
+BFD033B8 8C005042 ORI V0, V0, -29696\r
+BFD033BA 8C00 BEQZ S0, 0xBFD033BC\r
+BFD033BC ED81 LI V1, 1\r
+BFD033BE CC16 B 0xBFD033EC\r
+BFD033C0 89A4 SB V1, 4(V0)\r
144: \r
145: } \r
146: else\r
147: {\r
148: TFDP->CONTROL = 0x00u;\r
-BFD033C2 A00041A2 LUI V0, 0xA000
-BFD033C6 8C005042 ORI V0, V0, -29696
-BFD033C8 8C00 BEQZ S0, 0xBFD033CA
-BFD033CA 8824 SB S0, 4(V0)
+BFD033C2 A00041A2 LUI V0, 0xA000\r
+BFD033C6 8C005042 ORI V0, V0, -29696\r
+BFD033C8 8C00 BEQZ S0, 0xBFD033CA\r
+BFD033CA 8824 SB S0, 4(V0)\r
149: if (pin_cfg) \r
-BFD033CC 0014145E LBU V0, 20(S8)
-BFD033D0 000C40E2 BEQZC V0, 0xBFD033EC
+BFD033CC 0014145E LBU V0, 20(S8)\r
+BFD033D0 000C40E2 BEQZC V0, 0xBFD033EC\r
150: { /* Set to POR value (tri-stated input) */\r
151: GPIO_CTRL->REG[TFDP_PIN_1].w = 0;\r
-BFD033D4 A00841A2 LUI V0, 0xA008
-BFD033D8 10005042 ORI V0, V0, 4096
-BFD033DA F8021000 ADDI ZERO, ZERO, -2046
-BFD033DC 0138F802 SW ZERO, 312(V0)
+BFD033D4 A00841A2 LUI V0, 0xA008\r
+BFD033D8 10005042 ORI V0, V0, 4096\r
+BFD033DA F8021000 ADDI ZERO, ZERO, -2046\r
+BFD033DC 0138F802 SW ZERO, 312(V0)\r
152: GPIO_CTRL->REG[TFDP_PIN_2].w = 0;\r
-BFD033E0 A00841A2 LUI V0, 0xA008
-BFD033E4 10005042 ORI V0, V0, 4096
-BFD033E6 F8021000 ADDI ZERO, ZERO, -2046
-BFD033E8 013CF802 SW ZERO, 316(V0)
+BFD033E0 A00841A2 LUI V0, 0xA008\r
+BFD033E4 10005042 ORI V0, V0, 4096\r
+BFD033E6 F8021000 ADDI ZERO, ZERO, -2046\r
+BFD033E8 013CF802 SW ZERO, 316(V0)\r
153: }\r
154: }\r
155: } // end tfdp_enable()\r
-BFD033EC 0FBE MOVE SP, S8
-BFD033EE 4BC3 LW S8, 12(SP)
-BFD033F0 459F JR16 RA
-BFD033F2 4C09 ADDIU SP, SP, 16
+BFD033EC 0FBE MOVE SP, S8\r
+BFD033EE 4BC3 LW S8, 12(SP)\r
+BFD033F0 459F JR16 RA\r
+BFD033F2 4C09 ADDIU SP, SP, 16\r
156: \r
157: \r
158: /**\r
171: */\r
172: void TFDPTrace0 ( uint16_t nbr, uint8_t b )\r
173: {\r
-BFD09A18 4FF5 ADDIU SP, SP, -24
-BFD09A1A CBE5 SW RA, 20(SP)
-BFD09A1C CBC4 SW S8, 16(SP)
-BFD09A1E 0FDD MOVE S8, SP
-BFD09A20 0C64 MOVE V1, A0
-BFD09A22 0C45 MOVE V0, A1
-BFD09A24 0018387E SH V1, 24(S8)
-BFD09A28 001C185E SB V0, 28(S8)
+BFD09A18 4FF5 ADDIU SP, SP, -24\r
+BFD09A1A CBE5 SW RA, 20(SP)\r
+BFD09A1C CBC4 SW S8, 16(SP)\r
+BFD09A1E 0FDD MOVE S8, SP\r
+BFD09A20 0C64 MOVE V1, A0\r
+BFD09A22 0C45 MOVE V0, A1\r
+BFD09A24 0018387E SH V1, 24(S8)\r
+BFD09A28 001C185E SB V0, 28(S8)\r
174: #ifdef ENABLE_TRACE_MASK_IRQ\r
175: uint32_t isave;\r
176: \r
179: \r
180: (void)b;\r
181: tfdp_xmit_header(nbr);\r
-BFD09A2C 0018345E LHU V0, 24(S8)
-BFD09A30 0C82 MOVE A0, V0
-BFD09A32 483677E8 JALS tfdp_xmit_header
-BFD09A34 4836 LW AT, 88(SP)
-BFD09A36 0C00 NOP
+BFD09A2C 0018345E LHU V0, 24(S8)\r
+BFD09A30 0C82 MOVE A0, V0\r
+BFD09A32 483677E8 JALS tfdp_xmit_header\r
+BFD09A34 4836 LW AT, 88(SP)\r
+BFD09A36 0C00 NOP\r
182: \r
183: #ifdef ENABLE_TRACE_MASK_IRQ\r
184: mips32r2_restore_intr(isave);\r
185: #endif\r
186: }\r
-BFD09A38 0FBE MOVE SP, S8
-BFD09A3A 4BE5 LW RA, 20(SP)
-BFD09A3C 4BC4 LW S8, 16(SP)
-BFD09A3E 4C0D ADDIU SP, SP, 24
-BFD09A40 459F JR16 RA
-BFD09A42 0C00 NOP
+BFD09A38 0FBE MOVE SP, S8\r
+BFD09A3A 4BE5 LW RA, 20(SP)\r
+BFD09A3C 4BC4 LW S8, 16(SP)\r
+BFD09A3E 4C0D ADDIU SP, SP, 24\r
+BFD09A40 459F JR16 RA\r
+BFD09A42 0C00 NOP\r
187: \r
188: \r
189: /**\r
203: */\r
204: void TFDPTrace1 ( uint16_t nbr, uint8_t b, uint32_t p1 )\r
205: {\r
-BFD094A0 4FF5 ADDIU SP, SP, -24
-BFD094A2 CBE5 SW RA, 20(SP)
-BFD094A4 CBC4 SW S8, 16(SP)
-BFD094A6 0FDD MOVE S8, SP
-BFD094A8 0C64 MOVE V1, A0
-BFD094AA 0C45 MOVE V0, A1
-BFD094AC 0020F8DE SW A2, 32(S8)
-BFD094B0 0018387E SH V1, 24(S8)
-BFD094B4 001C185E SB V0, 28(S8)
+BFD094A0 4FF5 ADDIU SP, SP, -24\r
+BFD094A2 CBE5 SW RA, 20(SP)\r
+BFD094A4 CBC4 SW S8, 16(SP)\r
+BFD094A6 0FDD MOVE S8, SP\r
+BFD094A8 0C64 MOVE V1, A0\r
+BFD094AA 0C45 MOVE V0, A1\r
+BFD094AC 0020F8DE SW A2, 32(S8)\r
+BFD094B0 0018387E SH V1, 24(S8)\r
+BFD094B4 001C185E SB V0, 28(S8)\r
206: #ifdef ENABLE_TRACE_MASK_IRQ\r
207: uint32_t isave;\r
208: \r
210: #endif\r
211: (void)b;\r
212: tfdp_xmit_header(nbr);\r
-BFD094B8 0018345E LHU V0, 24(S8)
-BFD094BC 0C82 MOVE A0, V0
-BFD094BE 483677E8 JALS tfdp_xmit_header
-BFD094C0 4836 LW AT, 88(SP)
-BFD094C2 0C00 NOP
+BFD094B8 0018345E LHU V0, 24(S8)\r
+BFD094BC 0C82 MOVE A0, V0\r
+BFD094BE 483677E8 JALS tfdp_xmit_header\r
+BFD094C0 4836 LW AT, 88(SP)\r
+BFD094C2 0C00 NOP\r
213: tfdp_xmit_hword(p1);\r
-BFD094C4 0020FC5E LW V0, 32(S8)
-BFD094C8 2D2F ANDI V0, V0, 0xFFFF
-BFD094CA 0C82 MOVE A0, V0
-BFD094CC 4B2477E8 JALS tfdp_xmit_hword
-BFD094CE 4B24 LW T9, 16(SP)
-BFD094D0 0C00 NOP
+BFD094C4 0020FC5E LW V0, 32(S8)\r
+BFD094C8 2D2F ANDI V0, V0, 0xFFFF\r
+BFD094CA 0C82 MOVE A0, V0\r
+BFD094CC 4B2477E8 JALS tfdp_xmit_hword\r
+BFD094CE 4B24 LW T9, 16(SP)\r
+BFD094D0 0C00 NOP\r
214: \r
215: #ifdef ENABLE_TRACE_MASK_IRQ\r
216: mips32r2_restore_intr(isave);\r
217: #endif\r
218: }\r
-BFD094D2 0FBE MOVE SP, S8
-BFD094D4 4BE5 LW RA, 20(SP)
-BFD094D6 4BC4 LW S8, 16(SP)
-BFD094D8 4C0D ADDIU SP, SP, 24
-BFD094DA 459F JR16 RA
-BFD094DC 0C00 NOP
+BFD094D2 0FBE MOVE SP, S8\r
+BFD094D4 4BE5 LW RA, 20(SP)\r
+BFD094D6 4BC4 LW S8, 16(SP)\r
+BFD094D8 4C0D ADDIU SP, SP, 24\r
+BFD094DA 459F JR16 RA\r
+BFD094DC 0C00 NOP\r
219: \r
220: \r
221: /**\r
236: */\r
237: void TFDPTrace2 ( uint16_t nbr, uint8_t b, uint32_t p1, uint32_t p2 )\r
238: {\r
-BFD08A44 4FF5 ADDIU SP, SP, -24
-BFD08A46 CBE5 SW RA, 20(SP)
-BFD08A48 CBC4 SW S8, 16(SP)
-BFD08A4A 0FDD MOVE S8, SP
-BFD08A4C 0C64 MOVE V1, A0
-BFD08A4E 0C45 MOVE V0, A1
-BFD08A50 0020F8DE SW A2, 32(S8)
-BFD08A54 0024F8FE SW A3, 36(S8)
-BFD08A58 0018387E SH V1, 24(S8)
-BFD08A5C 001C185E SB V0, 28(S8)
+BFD08A44 4FF5 ADDIU SP, SP, -24\r
+BFD08A46 CBE5 SW RA, 20(SP)\r
+BFD08A48 CBC4 SW S8, 16(SP)\r
+BFD08A4A 0FDD MOVE S8, SP\r
+BFD08A4C 0C64 MOVE V1, A0\r
+BFD08A4E 0C45 MOVE V0, A1\r
+BFD08A50 0020F8DE SW A2, 32(S8)\r
+BFD08A54 0024F8FE SW A3, 36(S8)\r
+BFD08A58 0018387E SH V1, 24(S8)\r
+BFD08A5C 001C185E SB V0, 28(S8)\r
239: #ifdef ENABLE_TRACE_MASK_IRQ\r
240: uint32_t isave;\r
241: \r
243: #endif\r
244: (void)b;\r
245: tfdp_xmit_header(nbr);\r
-BFD08A60 0018345E LHU V0, 24(S8)
-BFD08A64 0C82 MOVE A0, V0
-BFD08A66 483677E8 JALS tfdp_xmit_header
-BFD08A68 4836 LW AT, 88(SP)
-BFD08A6A 0C00 NOP
+BFD08A60 0018345E LHU V0, 24(S8)\r
+BFD08A64 0C82 MOVE A0, V0\r
+BFD08A66 483677E8 JALS tfdp_xmit_header\r
+BFD08A68 4836 LW AT, 88(SP)\r
+BFD08A6A 0C00 NOP\r
246: tfdp_xmit_hword(p1);\r
-BFD08A6C 0020FC5E LW V0, 32(S8)
-BFD08A70 2D2F ANDI V0, V0, 0xFFFF
-BFD08A72 0C82 MOVE A0, V0
-BFD08A74 4B2477E8 JALS tfdp_xmit_hword
-BFD08A76 4B24 LW T9, 16(SP)
-BFD08A78 0C00 NOP
+BFD08A6C 0020FC5E LW V0, 32(S8)\r
+BFD08A70 2D2F ANDI V0, V0, 0xFFFF\r
+BFD08A72 0C82 MOVE A0, V0\r
+BFD08A74 4B2477E8 JALS tfdp_xmit_hword\r
+BFD08A76 4B24 LW T9, 16(SP)\r
+BFD08A78 0C00 NOP\r
247: tfdp_xmit_hword(p2);\r
-BFD08A7A 0024FC5E LW V0, 36(S8)
-BFD08A7E 2D2F ANDI V0, V0, 0xFFFF
-BFD08A80 0C82 MOVE A0, V0
-BFD08A82 4B2477E8 JALS tfdp_xmit_hword
-BFD08A84 4B24 LW T9, 16(SP)
-BFD08A86 0C00 NOP
+BFD08A7A 0024FC5E LW V0, 36(S8)\r
+BFD08A7E 2D2F ANDI V0, V0, 0xFFFF\r
+BFD08A80 0C82 MOVE A0, V0\r
+BFD08A82 4B2477E8 JALS tfdp_xmit_hword\r
+BFD08A84 4B24 LW T9, 16(SP)\r
+BFD08A86 0C00 NOP\r
248: \r
249: #ifdef ENABLE_TRACE_MASK_IRQ\r
250: mips32r2_restore_intr(isave);\r
251: #endif\r
252: }\r
-BFD08A88 0FBE MOVE SP, S8
-BFD08A8A 4BE5 LW RA, 20(SP)
-BFD08A8C 4BC4 LW S8, 16(SP)
-BFD08A8E 4C0D ADDIU SP, SP, 24
-BFD08A90 459F JR16 RA
-BFD08A92 0C00 NOP
+BFD08A88 0FBE MOVE SP, S8\r
+BFD08A8A 4BE5 LW RA, 20(SP)\r
+BFD08A8C 4BC4 LW S8, 16(SP)\r
+BFD08A8E 4C0D ADDIU SP, SP, 24\r
+BFD08A90 459F JR16 RA\r
+BFD08A92 0C00 NOP\r
253: \r
254: \r
255: /**\r
271: */\r
272: void TFDPTrace3 ( uint16_t nbr, uint8_t b, uint32_t p1, uint32_t p2, uint32_t p3)\r
273: {\r
-BFD08274 4FF5 ADDIU SP, SP, -24
-BFD08276 CBE5 SW RA, 20(SP)
-BFD08278 CBC4 SW S8, 16(SP)
-BFD0827A 0FDD MOVE S8, SP
-BFD0827C 0C64 MOVE V1, A0
-BFD0827E 0C45 MOVE V0, A1
-BFD08280 0020F8DE SW A2, 32(S8)
-BFD08284 0024F8FE SW A3, 36(S8)
-BFD08288 0018387E SH V1, 24(S8)
-BFD0828C 001C185E SB V0, 28(S8)
+BFD08274 4FF5 ADDIU SP, SP, -24\r
+BFD08276 CBE5 SW RA, 20(SP)\r
+BFD08278 CBC4 SW S8, 16(SP)\r
+BFD0827A 0FDD MOVE S8, SP\r
+BFD0827C 0C64 MOVE V1, A0\r
+BFD0827E 0C45 MOVE V0, A1\r
+BFD08280 0020F8DE SW A2, 32(S8)\r
+BFD08284 0024F8FE SW A3, 36(S8)\r
+BFD08288 0018387E SH V1, 24(S8)\r
+BFD0828C 001C185E SB V0, 28(S8)\r
274: #ifdef ENABLE_TRACE_MASK_IRQ\r
275: uint32_t isave;\r
276: \r
278: #endif \r
279: (void)b;\r
280: tfdp_xmit_header(nbr);\r
-BFD08290 0018345E LHU V0, 24(S8)
-BFD08294 0C82 MOVE A0, V0
-BFD08296 483677E8 JALS tfdp_xmit_header
-BFD08298 4836 LW AT, 88(SP)
-BFD0829A 0C00 NOP
+BFD08290 0018345E LHU V0, 24(S8)\r
+BFD08294 0C82 MOVE A0, V0\r
+BFD08296 483677E8 JALS tfdp_xmit_header\r
+BFD08298 4836 LW AT, 88(SP)\r
+BFD0829A 0C00 NOP\r
281: tfdp_xmit_hword(p1);\r
-BFD0829C 0020FC5E LW V0, 32(S8)
-BFD082A0 2D2F ANDI V0, V0, 0xFFFF
-BFD082A2 0C82 MOVE A0, V0
-BFD082A4 4B2477E8 JALS tfdp_xmit_hword
-BFD082A6 4B24 LW T9, 16(SP)
-BFD082A8 0C00 NOP
+BFD0829C 0020FC5E LW V0, 32(S8)\r
+BFD082A0 2D2F ANDI V0, V0, 0xFFFF\r
+BFD082A2 0C82 MOVE A0, V0\r
+BFD082A4 4B2477E8 JALS tfdp_xmit_hword\r
+BFD082A6 4B24 LW T9, 16(SP)\r
+BFD082A8 0C00 NOP\r
282: tfdp_xmit_hword(p2);\r
-BFD082AA 0024FC5E LW V0, 36(S8)
-BFD082AE 2D2F ANDI V0, V0, 0xFFFF
-BFD082B0 0C82 MOVE A0, V0
-BFD082B2 4B2477E8 JALS tfdp_xmit_hword
-BFD082B4 4B24 LW T9, 16(SP)
-BFD082B6 0C00 NOP
+BFD082AA 0024FC5E LW V0, 36(S8)\r
+BFD082AE 2D2F ANDI V0, V0, 0xFFFF\r
+BFD082B0 0C82 MOVE A0, V0\r
+BFD082B2 4B2477E8 JALS tfdp_xmit_hword\r
+BFD082B4 4B24 LW T9, 16(SP)\r
+BFD082B6 0C00 NOP\r
283: tfdp_xmit_hword(p3);\r
-BFD082B8 0028FC5E LW V0, 40(S8)
-BFD082BC 2D2F ANDI V0, V0, 0xFFFF
-BFD082BE 0C82 MOVE A0, V0
-BFD082C0 4B2477E8 JALS tfdp_xmit_hword
-BFD082C2 4B24 LW T9, 16(SP)
-BFD082C4 0C00 NOP
+BFD082B8 0028FC5E LW V0, 40(S8)\r
+BFD082BC 2D2F ANDI V0, V0, 0xFFFF\r
+BFD082BE 0C82 MOVE A0, V0\r
+BFD082C0 4B2477E8 JALS tfdp_xmit_hword\r
+BFD082C2 4B24 LW T9, 16(SP)\r
+BFD082C4 0C00 NOP\r
284: \r
285: #ifdef ENABLE_TRACE_MASK_IRQ\r
286: if ( isave & (1ul<<0) )\r
289: }\r
290: #endif\r
291: }\r
-BFD082C6 0FBE MOVE SP, S8
-BFD082C8 4BE5 LW RA, 20(SP)
-BFD082CA 4BC4 LW S8, 16(SP)
-BFD082CC 4C0D ADDIU SP, SP, 24
-BFD082CE 459F JR16 RA
-BFD082D0 0C00 NOP
+BFD082C6 0FBE MOVE SP, S8\r
+BFD082C8 4BE5 LW RA, 20(SP)\r
+BFD082CA 4BC4 LW S8, 16(SP)\r
+BFD082CC 4C0D ADDIU SP, SP, 24\r
+BFD082CE 459F JR16 RA\r
+BFD082D0 0C00 NOP\r
292: \r
293: \r
294: /**\r
311: */\r
312: void TFDPTrace4 ( uint16_t nbr, uint8_t b, uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4)\r
313: {\r
-BFD07C28 4FF5 ADDIU SP, SP, -24
-BFD07C2A CBE5 SW RA, 20(SP)
-BFD07C2C CBC4 SW S8, 16(SP)
-BFD07C2E 0FDD MOVE S8, SP
-BFD07C30 0C64 MOVE V1, A0
-BFD07C32 0C45 MOVE V0, A1
-BFD07C34 0020F8DE SW A2, 32(S8)
-BFD07C38 0024F8FE SW A3, 36(S8)
-BFD07C3C 0018387E SH V1, 24(S8)
-BFD07C40 001C185E SB V0, 28(S8)
+BFD07C28 4FF5 ADDIU SP, SP, -24\r
+BFD07C2A CBE5 SW RA, 20(SP)\r
+BFD07C2C CBC4 SW S8, 16(SP)\r
+BFD07C2E 0FDD MOVE S8, SP\r
+BFD07C30 0C64 MOVE V1, A0\r
+BFD07C32 0C45 MOVE V0, A1\r
+BFD07C34 0020F8DE SW A2, 32(S8)\r
+BFD07C38 0024F8FE SW A3, 36(S8)\r
+BFD07C3C 0018387E SH V1, 24(S8)\r
+BFD07C40 001C185E SB V0, 28(S8)\r
314: #ifdef ENABLE_TRACE_MASK_IRQ\r
315: uint32_t isave;\r
316: \r
318: #endif\r
319: (void)b;\r
320: tfdp_xmit_header(nbr);\r
-BFD07C44 0018345E LHU V0, 24(S8)
-BFD07C48 0C82 MOVE A0, V0
-BFD07C4A 483677E8 JALS tfdp_xmit_header
-BFD07C4C 4836 LW AT, 88(SP)
-BFD07C4E 0C00 NOP
+BFD07C44 0018345E LHU V0, 24(S8)\r
+BFD07C48 0C82 MOVE A0, V0\r
+BFD07C4A 483677E8 JALS tfdp_xmit_header\r
+BFD07C4C 4836 LW AT, 88(SP)\r
+BFD07C4E 0C00 NOP\r
321: tfdp_xmit_hword(p1);\r
-BFD07C50 0020FC5E LW V0, 32(S8)
-BFD07C54 2D2F ANDI V0, V0, 0xFFFF
-BFD07C56 0C82 MOVE A0, V0
-BFD07C58 4B2477E8 JALS tfdp_xmit_hword
-BFD07C5A 4B24 LW T9, 16(SP)
-BFD07C5C 0C00 NOP
+BFD07C50 0020FC5E LW V0, 32(S8)\r
+BFD07C54 2D2F ANDI V0, V0, 0xFFFF\r
+BFD07C56 0C82 MOVE A0, V0\r
+BFD07C58 4B2477E8 JALS tfdp_xmit_hword\r
+BFD07C5A 4B24 LW T9, 16(SP)\r
+BFD07C5C 0C00 NOP\r
322: tfdp_xmit_hword(p2);\r
-BFD07C5E 0024FC5E LW V0, 36(S8)
-BFD07C62 2D2F ANDI V0, V0, 0xFFFF
-BFD07C64 0C82 MOVE A0, V0
-BFD07C66 4B2477E8 JALS tfdp_xmit_hword
-BFD07C68 4B24 LW T9, 16(SP)
-BFD07C6A 0C00 NOP
+BFD07C5E 0024FC5E LW V0, 36(S8)\r
+BFD07C62 2D2F ANDI V0, V0, 0xFFFF\r
+BFD07C64 0C82 MOVE A0, V0\r
+BFD07C66 4B2477E8 JALS tfdp_xmit_hword\r
+BFD07C68 4B24 LW T9, 16(SP)\r
+BFD07C6A 0C00 NOP\r
323: tfdp_xmit_hword(p3);\r
-BFD07C6C 0028FC5E LW V0, 40(S8)
-BFD07C70 2D2F ANDI V0, V0, 0xFFFF
-BFD07C72 0C82 MOVE A0, V0
-BFD07C74 4B2477E8 JALS tfdp_xmit_hword
-BFD07C76 4B24 LW T9, 16(SP)
-BFD07C78 0C00 NOP
+BFD07C6C 0028FC5E LW V0, 40(S8)\r
+BFD07C70 2D2F ANDI V0, V0, 0xFFFF\r
+BFD07C72 0C82 MOVE A0, V0\r
+BFD07C74 4B2477E8 JALS tfdp_xmit_hword\r
+BFD07C76 4B24 LW T9, 16(SP)\r
+BFD07C78 0C00 NOP\r
324: tfdp_xmit_hword(p4);\r
-BFD07C7A 002CFC5E LW V0, 44(S8)
-BFD07C7E 2D2F ANDI V0, V0, 0xFFFF
-BFD07C80 0C82 MOVE A0, V0
-BFD07C82 4B2477E8 JALS tfdp_xmit_hword
-BFD07C84 4B24 LW T9, 16(SP)
-BFD07C86 0C00 NOP
+BFD07C7A 002CFC5E LW V0, 44(S8)\r
+BFD07C7E 2D2F ANDI V0, V0, 0xFFFF\r
+BFD07C80 0C82 MOVE A0, V0\r
+BFD07C82 4B2477E8 JALS tfdp_xmit_hword\r
+BFD07C84 4B24 LW T9, 16(SP)\r
+BFD07C86 0C00 NOP\r
325: \r
326: #ifdef ENABLE_TRACE_MASK_IRQ\r
327: if ( isave & (1ul<<0) )\r
330: }\r
331: #endif\r
332: }\r
-BFD07C88 0FBE MOVE SP, S8
-BFD07C8A 4BE5 LW RA, 20(SP)
-BFD07C8C 4BC4 LW S8, 16(SP)
-BFD07C8E 4C0D ADDIU SP, SP, 24
-BFD07C90 459F JR16 RA
-BFD07C92 0C00 NOP
+BFD07C88 0FBE MOVE SP, S8\r
+BFD07C8A 4BE5 LW RA, 20(SP)\r
+BFD07C8C 4BC4 LW S8, 16(SP)\r
+BFD07C8E 4C0D ADDIU SP, SP, 24\r
+BFD07C90 459F JR16 RA\r
+BFD07C92 0C00 NOP\r
333: \r
334: \r
335: /** \r
342: */\r
343: void TFDPTrace11( uint16_t nbr, uint8_t b, uint32_t p1)\r
344: {\r
-BFD09684 4FF5 ADDIU SP, SP, -24
-BFD09686 CBE5 SW RA, 20(SP)
-BFD09688 CBC4 SW S8, 16(SP)
-BFD0968A 0FDD MOVE S8, SP
-BFD0968C 0C64 MOVE V1, A0
-BFD0968E 0C45 MOVE V0, A1
-BFD09690 0020F8DE SW A2, 32(S8)
-BFD09694 0018387E SH V1, 24(S8)
-BFD09698 001C185E SB V0, 28(S8)
+BFD09684 4FF5 ADDIU SP, SP, -24\r
+BFD09686 CBE5 SW RA, 20(SP)\r
+BFD09688 CBC4 SW S8, 16(SP)\r
+BFD0968A 0FDD MOVE S8, SP\r
+BFD0968C 0C64 MOVE V1, A0\r
+BFD0968E 0C45 MOVE V0, A1\r
+BFD09690 0020F8DE SW A2, 32(S8)\r
+BFD09694 0018387E SH V1, 24(S8)\r
+BFD09698 001C185E SB V0, 28(S8)\r
345: #ifdef ENABLE_TRACE_MASK_IRQ\r
346: uint32_t isave;\r
347: \r
349: #endif \r
350: (void)b;\r
351: tfdp_xmit_header(nbr);\r
-BFD0969C 0018345E LHU V0, 24(S8)
-BFD096A0 0C82 MOVE A0, V0
-BFD096A2 483677E8 JALS tfdp_xmit_header
-BFD096A4 4836 LW AT, 88(SP)
-BFD096A6 0C00 NOP
+BFD0969C 0018345E LHU V0, 24(S8)\r
+BFD096A0 0C82 MOVE A0, V0\r
+BFD096A2 483677E8 JALS tfdp_xmit_header\r
+BFD096A4 4836 LW AT, 88(SP)\r
+BFD096A6 0C00 NOP\r
352: tfdp_xmit_word(p1);\r
-BFD096A8 0020FC9E LW A0, 32(S8)
-BFD096AC 467A77E8 JALS tfdp_xmit_word
-BFD096B0 0C00 NOP
+BFD096A8 0020FC9E LW A0, 32(S8)\r
+BFD096AC 467A77E8 JALS tfdp_xmit_word\r
+BFD096B0 0C00 NOP\r
353: \r
354: #ifdef ENABLE_TRACE_MASK_IRQ\r
355: if ( isave & (1ul<<0) )\r
358: }\r
359: #endif\r
360: }\r
-BFD096B2 0FBE MOVE SP, S8
-BFD096B4 4BE5 LW RA, 20(SP)
-BFD096B6 4BC4 LW S8, 16(SP)
-BFD096B8 4C0D ADDIU SP, SP, 24
-BFD096BA 459F JR16 RA
-BFD096BC 0C00 NOP
+BFD096B2 0FBE MOVE SP, S8\r
+BFD096B4 4BE5 LW RA, 20(SP)\r
+BFD096B6 4BC4 LW S8, 16(SP)\r
+BFD096B8 4C0D ADDIU SP, SP, 24\r
+BFD096BA 459F JR16 RA\r
+BFD096BC 0C00 NOP\r
361: \r
362: \r
363: /** \r
371: */\r
372: void TFDPTrace12( uint16_t nbr, uint8_t b, uint32_t p1, uint32_t p2 )\r
373: {\r
-BFD090B4 4FF5 ADDIU SP, SP, -24
-BFD090B6 CBE5 SW RA, 20(SP)
-BFD090B8 CBC4 SW S8, 16(SP)
-BFD090BA 0FDD MOVE S8, SP
-BFD090BC 0C64 MOVE V1, A0
-BFD090BE 0C45 MOVE V0, A1
-BFD090C0 0020F8DE SW A2, 32(S8)
-BFD090C4 0024F8FE SW A3, 36(S8)
-BFD090C8 0018387E SH V1, 24(S8)
-BFD090CC 001C185E SB V0, 28(S8)
+BFD090B4 4FF5 ADDIU SP, SP, -24\r
+BFD090B6 CBE5 SW RA, 20(SP)\r
+BFD090B8 CBC4 SW S8, 16(SP)\r
+BFD090BA 0FDD MOVE S8, SP\r
+BFD090BC 0C64 MOVE V1, A0\r
+BFD090BE 0C45 MOVE V0, A1\r
+BFD090C0 0020F8DE SW A2, 32(S8)\r
+BFD090C4 0024F8FE SW A3, 36(S8)\r
+BFD090C8 0018387E SH V1, 24(S8)\r
+BFD090CC 001C185E SB V0, 28(S8)\r
374: #ifdef ENABLE_TRACE_MASK_IRQ\r
375: uint32_t isave;\r
376: \r
378: #endif \r
379: (void)b;\r
380: tfdp_xmit_header(nbr);\r
-BFD090D0 0018345E LHU V0, 24(S8)
-BFD090D4 0C82 MOVE A0, V0
-BFD090D6 483677E8 JALS tfdp_xmit_header
-BFD090D8 4836 LW AT, 88(SP)
-BFD090DA 0C00 NOP
+BFD090D0 0018345E LHU V0, 24(S8)\r
+BFD090D4 0C82 MOVE A0, V0\r
+BFD090D6 483677E8 JALS tfdp_xmit_header\r
+BFD090D8 4836 LW AT, 88(SP)\r
+BFD090DA 0C00 NOP\r
381: tfdp_xmit_word(p1);\r
-BFD090DC 0020FC9E LW A0, 32(S8)
-BFD090E0 467A77E8 JALS tfdp_xmit_word
-BFD090E4 0C00 NOP
+BFD090DC 0020FC9E LW A0, 32(S8)\r
+BFD090E0 467A77E8 JALS tfdp_xmit_word\r
+BFD090E4 0C00 NOP\r
382: tfdp_xmit_word(p2);\r
-BFD090E6 0024FC9E LW A0, 36(S8)
-BFD090EA 467A77E8 JALS tfdp_xmit_word
-BFD090EE 0C00 NOP
+BFD090E6 0024FC9E LW A0, 36(S8)\r
+BFD090EA 467A77E8 JALS tfdp_xmit_word\r
+BFD090EE 0C00 NOP\r
383: \r
384: #ifdef ENABLE_TRACE_MASK_IRQ\r
385: if ( isave & (1ul<<0) )\r
388: }\r
389: #endif\r
390: }\r
-BFD090F0 0FBE MOVE SP, S8
-BFD090F2 4BE5 LW RA, 20(SP)
-BFD090F4 4BC4 LW S8, 16(SP)
-BFD090F6 4C0D ADDIU SP, SP, 24
-BFD090F8 459F JR16 RA
-BFD090FA 0C00 NOP
+BFD090F0 0FBE MOVE SP, S8\r
+BFD090F2 4BE5 LW RA, 20(SP)\r
+BFD090F4 4BC4 LW S8, 16(SP)\r
+BFD090F6 4C0D ADDIU SP, SP, 24\r
+BFD090F8 459F JR16 RA\r
+BFD090FA 0C00 NOP\r
391: \r
392: #endif // #ifdef ENABLE_TFDP_TRACE\r
393: \r
395: /* end mec14xx_tfdp.c */\r
396: /** @}\r
397: */\r
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/mec14xx_system.c -------
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/mec14xx_system.c -------\r
1: /*****************************************************************************\r
2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
3: * You may use this software and any derivatives exclusively with\r
47: */\r
48: void SystemInit (void)\r
49: {\r
-BFD09E20 4FB0 ADDIU SP, SP, -8
-BFD09E22 CBC1 SW S8, 4(SP)
-BFD09E24 0FDD MOVE S8, SP
+BFD09E20 4FB0 ADDIU SP, SP, -8\r
+BFD09E22 CBC1 SW S8, 4(SP)\r
+BFD09E24 0FDD MOVE S8, SP\r
50: \r
51: PCR->PROC_CLOCK_CNTRL = (PCR_CLOCK_DIVIDER);\r
-BFD09E26 A00841A2 LUI V0, 0xA008
-BFD09E2A 01005042 ORI V0, V0, 256
-BFD09E2E ED81 LI V1, 1
-BFD09E30 E9A8 SW V1, 32(V0)
+BFD09E26 A00841A2 LUI V0, 0xA008\r
+BFD09E2A 01005042 ORI V0, V0, 256\r
+BFD09E2E ED81 LI V1, 1\r
+BFD09E30 E9A8 SW V1, 32(V0)\r
52: \r
53: }\r
-BFD09E32 0FBE MOVE SP, S8
-BFD09E34 4BC1 LW S8, 4(SP)
-BFD09E36 4C05 ADDIU SP, SP, 8
-BFD09E38 459F JR16 RA
-BFD09E3A 0C00 NOP
+BFD09E32 0FBE MOVE SP, S8\r
+BFD09E34 4BC1 LW S8, 4(SP)\r
+BFD09E36 4C05 ADDIU SP, SP, 8\r
+BFD09E38 459F JR16 RA\r
+BFD09E3A 0C00 NOP\r
54: /*---------------------------------------------------------------------------*/\r
55: \r
56: uint32_t sys_code_sram_base(void)\r
57: {\r
-BFD09EAC 4FB0 ADDIU SP, SP, -8
-BFD09EAE CBC1 SW S8, 4(SP)
-BFD09EB0 0FDD MOVE S8, SP
+BFD09EAC 4FB0 ADDIU SP, SP, -8\r
+BFD09EAE CBC1 SW S8, 4(SP)\r
+BFD09EB0 0FDD MOVE S8, SP\r
58: #if MEC14XX_DEVID == MEC1418_DEVID\r
59: return (uint32_t)(MEC1418_ICODE_PSRAM_BASE);\r
60: #else\r
61: return (uint32_t)(MEC1404_ICODE_PSRAM_BASE);\r
-BFD09EB2 1FD041A2 LUI V0, 0x1FD0
-BFD09EB4 0FBE1FD0 LB S8, 4030(S0)
+BFD09EB2 1FD041A2 LUI V0, 0x1FD0\r
+BFD09EB4 0FBE1FD0 LB S8, 4030(S0)\r
62: #endif\r
63: }\r
-BFD09EB6 0FBE MOVE SP, S8
-BFD09EB8 4BC1 LW S8, 4(SP)
-BFD09EBA 4C05 ADDIU SP, SP, 8
-BFD09EBC 459F JR16 RA
-BFD09EBE 0C00 NOP
+BFD09EB6 0FBE MOVE SP, S8\r
+BFD09EB8 4BC1 LW S8, 4(SP)\r
+BFD09EBA 4C05 ADDIU SP, SP, 8\r
+BFD09EBC 459F JR16 RA\r
+BFD09EBE 0C00 NOP\r
64: /*---------------------------------------------------------------------------*/\r
65: \r
66: uint8_t sys_valid_sram_addr(void * const p)\r
67: {\r
-BFD08CA8 4FF1 ADDIU SP, SP, -32
-BFD08CAA CBE7 SW RA, 28(SP)
-BFD08CAC CBC6 SW S8, 24(SP)
-BFD08CAE 0FDD MOVE S8, SP
-BFD08CB0 0020F89E SW A0, 32(S8)
+BFD08CA8 4FF1 ADDIU SP, SP, -32\r
+BFD08CAA CBE7 SW RA, 28(SP)\r
+BFD08CAC CBC6 SW S8, 24(SP)\r
+BFD08CAE 0FDD MOVE S8, SP\r
+BFD08CB0 0020F89E SW A0, 32(S8)\r
68: uint32_t base;\r
69: \r
70: base = sys_code_sram_base();\r
-BFD08CB4 4F5677E8 JALS sys_code_sram_base
-BFD08CB6 4F56 ADDIU K0, K0, -5
-BFD08CB8 0C00 NOP
-BFD08CBA 0010F85E SW V0, 16(S8)
+BFD08CB4 4F5677E8 JALS sys_code_sram_base\r
+BFD08CB6 4F56 ADDIU K0, K0, -5\r
+BFD08CB8 0C00 NOP\r
+BFD08CBA 0010F85E SW V0, 16(S8)\r
71: \r
72: if ((uint32_t)p >= base) {\r
-BFD08CBE 0020FC7E LW V1, 32(S8)
-BFD08CC2 0010FC5E LW V0, 16(S8)
-BFD08CC6 13900043 SLTU V0, V1, V0
-BFD08CC8 40A21390 ADDI GP, S0, 16546
-BFD08CCA 000B40A2 BNEZC V0, 0xBFD08CE4
+BFD08CBE 0020FC7E LW V1, 32(S8)\r
+BFD08CC2 0010FC5E LW V0, 16(S8)\r
+BFD08CC6 13900043 SLTU V0, V1, V0\r
+BFD08CC8 40A21390 ADDI GP, S0, 16546\r
+BFD08CCA 000B40A2 BNEZC V0, 0xBFD08CE4\r
73: if ((uint32_t)p < (MEC14XX_DCODE_VSRAM_LIMIT)) {\r
-BFD08CCE 0020FC7E LW V1, 32(S8)
-BFD08CD2 BFD241A2 LUI V0, 0xBFD2
-BFD08CD4 0043BFD2 LDC1 F30, 67(S2)
-BFD08CD6 13900043 SLTU V0, V1, V0
-BFD08CD8 40E21390 ADDI GP, S0, 16610
-BFD08CDA 000340E2 BEQZC V0, 0xBFD08CE4
+BFD08CCE 0020FC7E LW V1, 32(S8)\r
+BFD08CD2 BFD241A2 LUI V0, 0xBFD2\r
+BFD08CD4 0043BFD2 LDC1 F30, 67(S2)\r
+BFD08CD6 13900043 SLTU V0, V1, V0\r
+BFD08CD8 40E21390 ADDI GP, S0, 16610\r
+BFD08CDA 000340E2 BEQZC V0, 0xBFD08CE4\r
74: return 1u;\r
-BFD08CDE ED01 LI V0, 1
-BFD08CE0 CC02 B 0xBFD08CE6
-BFD08CE2 0C00 NOP
+BFD08CDE ED01 LI V0, 1\r
+BFD08CE0 CC02 B 0xBFD08CE6\r
+BFD08CE2 0C00 NOP\r
75: }\r
76: }\r
77: return 0u;\r
-BFD08CE4 0C40 MOVE V0, ZERO
+BFD08CE4 0C40 MOVE V0, ZERO\r
78: }\r
-BFD08CE6 0FBE MOVE SP, S8
-BFD08CE8 4BE7 LW RA, 28(SP)
-BFD08CEA 4BC6 LW S8, 24(SP)
-BFD08CEC 4C11 ADDIU SP, SP, 32
-BFD08CEE 459F JR16 RA
-BFD08CF0 0C00 NOP
+BFD08CE6 0FBE MOVE SP, S8\r
+BFD08CE8 4BE7 LW RA, 28(SP)\r
+BFD08CEA 4BC6 LW S8, 24(SP)\r
+BFD08CEC 4C11 ADDIU SP, SP, 32\r
+BFD08CEE 459F JR16 RA\r
+BFD08CF0 0C00 NOP\r
79: /*---------------------------------------------------------------------------*/\r
80: \r
81: uint8_t sys_valid_sram_range(void * const p, const uint32_t byte_len)\r
82: {\r
-BFD08858 4FF1 ADDIU SP, SP, -32
-BFD0885A CBE7 SW RA, 28(SP)
-BFD0885C CBC6 SW S8, 24(SP)
-BFD0885E 0FDD MOVE S8, SP
-BFD08860 0020F89E SW A0, 32(S8)
-BFD08864 0024F8BE SW A1, 36(S8)
+BFD08858 4FF1 ADDIU SP, SP, -32\r
+BFD0885A CBE7 SW RA, 28(SP)\r
+BFD0885C CBC6 SW S8, 24(SP)\r
+BFD0885E 0FDD MOVE S8, SP\r
+BFD08860 0020F89E SW A0, 32(S8)\r
+BFD08864 0024F8BE SW A1, 36(S8)\r
83: uint32_t base;\r
84: \r
85: base = sys_code_sram_base();\r
-BFD08868 4F5677E8 JALS sys_code_sram_base
-BFD0886A 4F56 ADDIU K0, K0, -5
-BFD0886C 0C00 NOP
-BFD0886E 0010F85E SW V0, 16(S8)
+BFD08868 4F5677E8 JALS sys_code_sram_base\r
+BFD0886A 4F56 ADDIU K0, K0, -5\r
+BFD0886C 0C00 NOP\r
+BFD0886E 0010F85E SW V0, 16(S8)\r
86: \r
87: if ((uint32_t)p >= base) {\r
-BFD08872 0020FC7E LW V1, 32(S8)
-BFD08876 0010FC5E LW V0, 16(S8)
-BFD0887A 13900043 SLTU V0, V1, V0
-BFD0887C 40A21390 ADDI GP, S0, 16546
-BFD0887E 000E40A2 BNEZC V0, 0xBFD0889E
+BFD08872 0020FC7E LW V1, 32(S8)\r
+BFD08876 0010FC5E LW V0, 16(S8)\r
+BFD0887A 13900043 SLTU V0, V1, V0\r
+BFD0887C 40A21390 ADDI GP, S0, 16546\r
+BFD0887E 000E40A2 BNEZC V0, 0xBFD0889E\r
88: if (((uint32_t)p + byte_len) < (MEC14XX_DCODE_VSRAM_LIMIT)) {\r
-BFD08882 0020FC7E LW V1, 32(S8)
-BFD08886 0024FC5E LW V0, 36(S8)
-BFD0888A 05A6 ADDU V1, V1, V0
-BFD0888C BFD241A2 LUI V0, 0xBFD2
-BFD0888E 0043BFD2 LDC1 F30, 67(S2)
-BFD08890 13900043 SLTU V0, V1, V0
-BFD08892 40E21390 ADDI GP, S0, 16610
-BFD08894 000340E2 BEQZC V0, 0xBFD0889E
+BFD08882 0020FC7E LW V1, 32(S8)\r
+BFD08886 0024FC5E LW V0, 36(S8)\r
+BFD0888A 05A6 ADDU V1, V1, V0\r
+BFD0888C BFD241A2 LUI V0, 0xBFD2\r
+BFD0888E 0043BFD2 LDC1 F30, 67(S2)\r
+BFD08890 13900043 SLTU V0, V1, V0\r
+BFD08892 40E21390 ADDI GP, S0, 16610\r
+BFD08894 000340E2 BEQZC V0, 0xBFD0889E\r
89: return 1u;\r
-BFD08898 ED01 LI V0, 1
-BFD0889A CC02 B 0xBFD088A0
-BFD0889C 0C00 NOP
+BFD08898 ED01 LI V0, 1\r
+BFD0889A CC02 B 0xBFD088A0\r
+BFD0889C 0C00 NOP\r
90: }\r
91: }\r
92: return 0u;\r
-BFD0889E 0C40 MOVE V0, ZERO
+BFD0889E 0C40 MOVE V0, ZERO\r
93: }\r
-BFD088A0 0FBE MOVE SP, S8
-BFD088A2 4BE7 LW RA, 28(SP)
-BFD088A4 4BC6 LW S8, 24(SP)
-BFD088A6 4C11 ADDIU SP, SP, 32
-BFD088A8 459F JR16 RA
-BFD088AA 0C00 NOP
+BFD088A0 0FBE MOVE SP, S8\r
+BFD088A2 4BE7 LW RA, 28(SP)\r
+BFD088A4 4BC6 LW S8, 24(SP)\r
+BFD088A6 4C11 ADDIU SP, SP, 32\r
+BFD088A8 459F JR16 RA\r
+BFD088AA 0C00 NOP\r
94: /*---------------------------------------------------------------------------*/\r
95: \r
96: void sys_cpu_en_timer(uint32_t counts, uint8_t ien)\r
97: {\r
-BFD07570 4FF5 ADDIU SP, SP, -24
-BFD07572 CBE5 SW RA, 20(SP)
-BFD07574 CBC4 SW S8, 16(SP)
-BFD07576 0FDD MOVE S8, SP
-BFD07578 0018F89E SW A0, 24(S8)
-BFD0757A 0C450018 CMP.LT.PH ZERO, T8
-BFD0757C 0C45 MOVE V0, A1
-BFD0757E 001C185E SB V0, 28(S8)
+BFD07570 4FF5 ADDIU SP, SP, -24\r
+BFD07572 CBE5 SW RA, 20(SP)\r
+BFD07574 CBC4 SW S8, 16(SP)\r
+BFD07576 0FDD MOVE S8, SP\r
+BFD07578 0018F89E SW A0, 24(S8)\r
+BFD0757A 0C450018 CMP.LT.PH ZERO, T8\r
+BFD0757C 0C45 MOVE V0, A1\r
+BFD0757E 001C185E SB V0, 28(S8)\r
98: /* Disable Counter by setting DC bit to 1 in CP0.Cause */\r
99: _CP0_BIS_CAUSE(_CP0_CAUSE_DC_MASK);\r
-BFD07582 080041A2 LUI V0, 0x800
-BFD07584 0800 LBU S0, 0(S0)
-BFD07586 00FC006D MFC0 V1, Cause
-BFD07588 0C0000FC SLL A3, GP, 1
-BFD0758A 0C00 NOP
-BFD0758C 44D3 OR16 V0, V1
-BFD0758E 02FC004D MTC0 V0, Cause
-BFD07590 000002FC SLL S7, GP, 0
-BFD07592 18000000 SLL ZERO, ZERO, 3
-BFD07594 FC5E1800 SB ZERO, -930(ZERO)
+BFD07582 080041A2 LUI V0, 0x800\r
+BFD07584 0800 LBU S0, 0(S0)\r
+BFD07586 00FC006D MFC0 V1, Cause\r
+BFD07588 0C0000FC SLL A3, GP, 1\r
+BFD0758A 0C00 NOP\r
+BFD0758C 44D3 OR16 V0, V1\r
+BFD0758E 02FC004D MTC0 V0, Cause\r
+BFD07590 000002FC SLL S7, GP, 0\r
+BFD07592 18000000 SLL ZERO, ZERO, 3\r
+BFD07594 FC5E1800 SB ZERO, -930(ZERO)\r
100: \r
101: _CP0_SET_COUNT(counts);\r
-BFD07596 0018FC5E LW V0, 24(S8)
-BFD0759A 02FC0049 MTC0 V0, Count
-BFD0759C 000002FC SLL S7, GP, 0
-BFD0759E 18000000 SLL ZERO, ZERO, 3
-BFD075A0 145E1800 SB ZERO, 5214(ZERO)
+BFD07596 0018FC5E LW V0, 24(S8)\r
+BFD0759A 02FC0049 MTC0 V0, Count\r
+BFD0759C 000002FC SLL S7, GP, 0\r
+BFD0759E 18000000 SLL ZERO, ZERO, 3\r
+BFD075A0 145E1800 SB ZERO, 5214(ZERO)\r
102: if (ien) {\r
-BFD075A2 001C145E LBU V0, 28(S8)
-BFD075A6 000840E2 BEQZC V0, 0xBFD075BA
-BFD075A8 EE100008 MUL SP, T0, ZERO
+BFD075A2 001C145E LBU V0, 28(S8)\r
+BFD075A6 000840E2 BEQZC V0, 0xBFD075BA\r
+BFD075A8 EE100008 MUL SP, T0, ZERO\r
103: jtvic_en_source(MEC14xx_GIRQ24_ID, 0, 0);\r
-BFD075AA EE10 LI A0, 16
-BFD075AC 0CA0 MOVE A1, ZERO
-BFD075AE 0CC0 MOVE A2, ZERO
-BFD075B0 3A7C77E8 JALS jtvic_en_source
-BFD075B2 0C003A7C SH S3, 3072(GP)
-BFD075B4 0C00 NOP
-BFD075B6 CC07 B 0xBFD075C6
-BFD075B8 0C00 NOP
+BFD075AA EE10 LI A0, 16\r
+BFD075AC 0CA0 MOVE A1, ZERO\r
+BFD075AE 0CC0 MOVE A2, ZERO\r
+BFD075B0 3A7C77E8 JALS jtvic_en_source\r
+BFD075B2 0C003A7C SH S3, 3072(GP)\r
+BFD075B4 0C00 NOP\r
+BFD075B6 CC07 B 0xBFD075C6\r
+BFD075B8 0C00 NOP\r
104: } else {\r
105: jtvic_dis_clr_source(MEC14xx_GIRQ24_ID, 0, 1);\r
-BFD075BA EE10 LI A0, 16
-BFD075BC 0CA0 MOVE A1, ZERO
-BFD075BE EF01 LI A2, 1
-BFD075C0 3A4077E8 JALS jtvic_dis_clr_source
-BFD075C2 0C003A40 SH S2, 3072(ZERO)
-BFD075C4 0C00 NOP
+BFD075BA EE10 LI A0, 16\r
+BFD075BC 0CA0 MOVE A1, ZERO\r
+BFD075BE EF01 LI A2, 1\r
+BFD075C0 3A4077E8 JALS jtvic_dis_clr_source\r
+BFD075C2 0C003A40 SH S2, 3072(ZERO)\r
+BFD075C4 0C00 NOP\r
106: }\r
107: \r
108: /* Enable Counter */\r
109: _CP0_BIC_CAUSE(_CP0_CAUSE_DC_MASK);\r
-BFD075C6 080041A2 LUI V0, 0x800
-BFD075C8 0800 LBU S0, 0(S0)
-BFD075CA 00FC006D MFC0 V1, Cause
-BFD075CC 0C0000FC SLL A3, GP, 1
-BFD075CE 0C00 NOP
-BFD075D0 4412 NOT16 V0, V0
-BFD075D2 4493 AND16 V0, V1
-BFD075D4 02FC004D MTC0 V0, Cause
-BFD075D6 000002FC SLL S7, GP, 0
-BFD075D8 18000000 SLL ZERO, ZERO, 3
-BFD075DA 0FBE1800 SB ZERO, 4030(ZERO)
+BFD075C6 080041A2 LUI V0, 0x800\r
+BFD075C8 0800 LBU S0, 0(S0)\r
+BFD075CA 00FC006D MFC0 V1, Cause\r
+BFD075CC 0C0000FC SLL A3, GP, 1\r
+BFD075CE 0C00 NOP\r
+BFD075D0 4412 NOT16 V0, V0\r
+BFD075D2 4493 AND16 V0, V1\r
+BFD075D4 02FC004D MTC0 V0, Cause\r
+BFD075D6 000002FC SLL S7, GP, 0\r
+BFD075D8 18000000 SLL ZERO, ZERO, 3\r
+BFD075DA 0FBE1800 SB ZERO, 4030(ZERO)\r
110: \r
111: }\r
-BFD075DC 0FBE MOVE SP, S8
-BFD075DE 4BE5 LW RA, 20(SP)
-BFD075E0 4BC4 LW S8, 16(SP)
-BFD075E2 4C0D ADDIU SP, SP, 24
-BFD075E4 459F JR16 RA
-BFD075E6 0C00 NOP
+BFD075DC 0FBE MOVE SP, S8\r
+BFD075DE 4BE5 LW RA, 20(SP)\r
+BFD075E0 4BC4 LW S8, 16(SP)\r
+BFD075E2 4C0D ADDIU SP, SP, 24\r
+BFD075E4 459F JR16 RA\r
+BFD075E6 0C00 NOP\r
112: /*---------------------------------------------------------------------------*/\r
113: \r
114: uint32_t cpu_microsecond_count(void)\r
115: {\r
-BFD09EC0 4FB0 ADDIU SP, SP, -8
-BFD09EC2 CBC1 SW S8, 4(SP)
-BFD09EC4 0FDD MOVE S8, SP
+BFD09EC0 4FB0 ADDIU SP, SP, -8\r
+BFD09EC2 CBC1 SW S8, 4(SP)\r
+BFD09EC4 0FDD MOVE S8, SP\r
116: return _CP0_GET_COUNT();\r
-BFD09EC6 00FC0049 MFC0 V0, Count
+BFD09EC6 00FC0049 MFC0 V0, Count\r
117: }\r
-BFD09ECA 0FBE MOVE SP, S8
-BFD09ECC 4BC1 LW S8, 4(SP)
-BFD09ECE 4C05 ADDIU SP, SP, 8
-BFD09ED0 459F JR16 RA
-BFD09ED2 0C00 NOP
+BFD09ECA 0FBE MOVE SP, S8\r
+BFD09ECC 4BC1 LW S8, 4(SP)\r
+BFD09ECE 4C05 ADDIU SP, SP, 8\r
+BFD09ED0 459F JR16 RA\r
+BFD09ED2 0C00 NOP\r
118: /*---------------------------------------------------------------------------*/\r
119: \r
120: /*\r
125: */\r
126: uint32_t cpu_microsecond_interval(uint32_t start_count)\r
127: {\r
-BFD07DCC 4FF9 ADDIU SP, SP, -16
-BFD07DCE CBC3 SW S8, 12(SP)
-BFD07DD0 0FDD MOVE S8, SP
-BFD07DD2 0010F89E SW A0, 16(S8)
+BFD07DCC 4FF9 ADDIU SP, SP, -16\r
+BFD07DCE CBC3 SW S8, 12(SP)\r
+BFD07DD0 0FDD MOVE S8, SP\r
+BFD07DD2 0010F89E SW A0, 16(S8)\r
128: uint32_t curr_count;\r
129: \r
130: curr_count = _CP0_GET_COUNT();\r
-BFD07DD6 00FC0049 MFC0 V0, Count
-BFD07DDA 0000F85E SW V0, 0(S8)
+BFD07DD6 00FC0049 MFC0 V0, Count\r
+BFD07DDA 0000F85E SW V0, 0(S8)\r
131: if (curr_count >= start_count) {\r
-BFD07DDE 0000FC7E LW V1, 0(S8)
-BFD07DE2 0010FC5E LW V0, 16(S8)
-BFD07DE6 13900043 SLTU V0, V1, V0
-BFD07DE8 40A21390 ADDI GP, S0, 16546
-BFD07DEA 000F40A2 BNEZC V0, 0xBFD07E0C
+BFD07DDE 0000FC7E LW V1, 0(S8)\r
+BFD07DE2 0010FC5E LW V0, 16(S8)\r
+BFD07DE6 13900043 SLTU V0, V1, V0\r
+BFD07DE8 40A21390 ADDI GP, S0, 16546\r
+BFD07DEA 000F40A2 BNEZC V0, 0xBFD07E0C\r
132: return ((curr_count - start_count) >> 4)/ 3ul;\r
-BFD07DEE 0000FC7E LW V1, 0(S8)
-BFD07DF2 0010FC5E LW V0, 16(S8)
-BFD07DF6 0527 SUBU V0, V1, V0
-BFD07DF8 25A9 SRL V1, V0, 4
-BFD07DFA ED03 LI V0, 3
-BFD07DFC BB3C0043 DIVU V0, V1
-BFD07DFE 0002BB3C SDC1 F25, 2(GP)
-BFD07E00 703C0002 TEQ V0, ZERO
-BFD07E02 4603703C XORI AT, GP, 17923
-BFD07E04 4603 MFHI V1
-BFD07E06 4642 MFLO V0
-BFD07E08 CC0F B 0xBFD07E28
-BFD07E0A 0C00 NOP
+BFD07DEE 0000FC7E LW V1, 0(S8)\r
+BFD07DF2 0010FC5E LW V0, 16(S8)\r
+BFD07DF6 0527 SUBU V0, V1, V0\r
+BFD07DF8 25A9 SRL V1, V0, 4\r
+BFD07DFA ED03 LI V0, 3\r
+BFD07DFC BB3C0043 DIVU V0, V1\r
+BFD07DFE 0002BB3C SDC1 F25, 2(GP)\r
+BFD07E00 703C0002 TEQ V0, ZERO\r
+BFD07E02 4603703C XORI AT, GP, 17923\r
+BFD07E04 4603 MFHI V1\r
+BFD07E06 4642 MFLO V0\r
+BFD07E08 CC0F B 0xBFD07E28\r
+BFD07E0A 0C00 NOP\r
133: } else {\r
134: return (((0xFFFFFFFFul - start_count) + curr_count) >> 4) / 3ul;\r
-BFD07E0C 0010FC5E LW V0, 16(S8)
-BFD07E10 441A NOT16 V1, V0
-BFD07E12 0000FC5E LW V0, 0(S8)
-BFD07E16 0526 ADDU V0, V1, V0
-BFD07E18 25A9 SRL V1, V0, 4
-BFD07E1A ED03 LI V0, 3
-BFD07E1C BB3C0043 DIVU V0, V1
-BFD07E1E 0002BB3C SDC1 F25, 2(GP)
-BFD07E20 703C0002 TEQ V0, ZERO
-BFD07E22 4603703C XORI AT, GP, 17923
-BFD07E24 4603 MFHI V1
-BFD07E26 4642 MFLO V0
+BFD07E0C 0010FC5E LW V0, 16(S8)\r
+BFD07E10 441A NOT16 V1, V0\r
+BFD07E12 0000FC5E LW V0, 0(S8)\r
+BFD07E16 0526 ADDU V0, V1, V0\r
+BFD07E18 25A9 SRL V1, V0, 4\r
+BFD07E1A ED03 LI V0, 3\r
+BFD07E1C BB3C0043 DIVU V0, V1\r
+BFD07E1E 0002BB3C SDC1 F25, 2(GP)\r
+BFD07E20 703C0002 TEQ V0, ZERO\r
+BFD07E22 4603703C XORI AT, GP, 17923\r
+BFD07E24 4603 MFHI V1\r
+BFD07E26 4642 MFLO V0\r
135: }\r
136: }\r
-BFD07E28 0FBE MOVE SP, S8
-BFD07E2A 4BC3 LW S8, 12(SP)
-BFD07E2C 4C09 ADDIU SP, SP, 16
-BFD07E2E 459F JR16 RA
-BFD07E30 0C00 NOP
+BFD07E28 0FBE MOVE SP, S8\r
+BFD07E2A 4BC3 LW S8, 12(SP)\r
+BFD07E2C 4C09 ADDIU SP, SP, 16\r
+BFD07E2E 459F JR16 RA\r
+BFD07E30 0C00 NOP\r
137: /*---------------------------------------------------------------------------*/\r
138: \r
139: /* end mec14xx_system.c */\r
140: /** @}\r
141: */\r
142: \r
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/mec14xx_jtvic.c --------
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/mec14xx_jtvic.c --------\r
1: /*****************************************************************************\r
2: * © 2014 Microchip Technology Inc. and its subsidiaries.\r
3: * You may use this software and any derivatives exclusively with\r
34: \r
35: void jtvic_init(const JTVIC_CFG *ih_table, uint32_t disagg_bitmap, uint32_t cflags)\r
36: {\r
-BFD03644 4FF9 ADDIU SP, SP, -16
-BFD03646 CBC3 SW S8, 12(SP)
-BFD03648 0FDD MOVE S8, SP
-BFD0364A 0010F89E SW A0, 16(S8)
-BFD0364E 0014F8BE SW A1, 20(S8)
-BFD03652 0018F8DE SW A2, 24(S8)
+BFD03644 4FF9 ADDIU SP, SP, -16\r
+BFD03646 CBC3 SW S8, 12(SP)\r
+BFD03648 0FDD MOVE S8, SP\r
+BFD0364A 0010F89E SW A0, 16(S8)\r
+BFD0364E 0014F8BE SW A1, 20(S8)\r
+BFD03652 0018F8DE SW A2, 24(S8)\r
37: uint32_t d;\r
38: uint8_t i, j, pidx;\r
39: \r
40: JTVIC_CTRL->w = (1ul << 0); // Soft-Reset\r
-BFD03656 BFFF41A2 LUI V0, 0xBFFF
-BFD03658 5042BFFF LDC1 F31, 20546(RA)
-BFD0365A C5005042 ORI V0, V0, -15104
-BFD0365E ED81 LI V1, 1
-BFD03660 E9A0 SW V1, 0(V0)
+BFD03656 BFFF41A2 LUI V0, 0xBFFF\r
+BFD03658 5042BFFF LDC1 F31, 20546(RA)\r
+BFD0365A C5005042 ORI V0, V0, -15104\r
+BFD0365E ED81 LI V1, 1\r
+BFD03660 E9A0 SW V1, 0(V0)\r
41: d = 0ul;\r
-BFD03662 0000F81E SW ZERO, 0(S8)
+BFD03662 0000F81E SW ZERO, 0(S8)\r
42: if ( cflags & (1ul << 0) ) \r
-BFD03666 0018FC5E LW V0, 24(S8)
-BFD0366A 2D21 ANDI V0, V0, 0x1
-BFD0366C 2D2D ANDI V0, V0, 0xFF
-BFD0366E 000440E2 BEQZC V0, 0xBFD0367A
-BFD03670 30400004 SRL ZERO, A0, 6
+BFD03666 0018FC5E LW V0, 24(S8)\r
+BFD0366A 2D21 ANDI V0, V0, 0x1\r
+BFD0366C 2D2D ANDI V0, V0, 0xFF\r
+BFD0366E 000440E2 BEQZC V0, 0xBFD0367A\r
+BFD03670 30400004 SRL ZERO, A0, 6\r
43: {\r
44: d = (1ul << 8);\r
-BFD03672 01003040 ADDIU V0, ZERO, 256
-BFD03676 0000F85E SW V0, 0(S8)
+BFD03672 01003040 ADDIU V0, ZERO, 256\r
+BFD03676 0000F85E SW V0, 0(S8)\r
45: }\r
46: JTVIC_CTRL->w = d; // HW does not automatically clear Soft-Reset\r
-BFD0367A BFFF41A2 LUI V0, 0xBFFF
-BFD0367C 5042BFFF LDC1 F31, 20546(RA)
-BFD0367E C5005042 ORI V0, V0, -15104
-BFD03682 0000FC7E LW V1, 0(S8)
-BFD03686 E9A0 SW V1, 0(V0)
+BFD0367A BFFF41A2 LUI V0, 0xBFFF\r
+BFD0367C 5042BFFF LDC1 F31, 20546(RA)\r
+BFD0367E C5005042 ORI V0, V0, -15104\r
+BFD03682 0000FC7E LW V1, 0(S8)\r
+BFD03686 E9A0 SW V1, 0(V0)\r
47: \r
48: for (i = 0u; i < (MEC14xx_NUM_JTVIC_INTS); i++) {\r
-BFD03688 0004181E SB ZERO, 4(S8)
-BFD0368C CC5C B 0xBFD03746
-BFD0368E 0C00 NOP
-BFD0373C 0004145E LBU V0, 4(S8)
-BFD03740 6D20 ADDIU V0, V0, 1
-BFD03742 0004185E SB V0, 4(S8)
-BFD03746 0004145E LBU V0, 4(S8)
-BFD0374A 0013B042 SLTIU V0, V0, 19
-BFD0374E FF9F40A2 BNEZC V0, 0xBFD03690
-BFD03750 41A2FF9F LW GP, 16802(RA)
+BFD03688 0004181E SB ZERO, 4(S8)\r
+BFD0368C CC5C B 0xBFD03746\r
+BFD0368E 0C00 NOP\r
+BFD0373C 0004145E LBU V0, 4(S8)\r
+BFD03740 6D20 ADDIU V0, V0, 1\r
+BFD03742 0004185E SB V0, 4(S8)\r
+BFD03746 0004145E LBU V0, 4(S8)\r
+BFD0374A 0013B042 SLTIU V0, V0, 19\r
+BFD0374E FF9F40A2 BNEZC V0, 0xBFD03690\r
+BFD03750 41A2FF9F LW GP, 16802(RA)\r
49: pidx = i << 2;\r
-BFD03690 0004145E LBU V0, 4(S8)
-BFD03694 2524 SLL V0, V0, 2
-BFD03696 0006185E SB V0, 6(S8)
+BFD03690 0004145E LBU V0, 4(S8)\r
+BFD03694 2524 SLL V0, V0, 2\r
+BFD03696 0006185E SB V0, 6(S8)\r
50: for (j = 0u; j < 4u; j++) {\r
-BFD0369A 0005181E SB ZERO, 5(S8)
-BFD0369E CC1F B 0xBFD036DE
-BFD036A0 0C00 NOP
-BFD036D4 0005145E LBU V0, 5(S8)
-BFD036D8 6D20 ADDIU V0, V0, 1
-BFD036DA 0005185E SB V0, 5(S8)
-BFD036DE 0005145E LBU V0, 5(S8)
-BFD036E2 0004B042 SLTIU V0, V0, 4
-BFD036E6 FFDC40A2 BNEZC V0, 0xBFD036A2
-BFD036E8 145EFFDC LW S8, 5214(GP)
+BFD0369A 0005181E SB ZERO, 5(S8)\r
+BFD0369E CC1F B 0xBFD036DE\r
+BFD036A0 0C00 NOP\r
+BFD036D4 0005145E LBU V0, 5(S8)\r
+BFD036D8 6D20 ADDIU V0, V0, 1\r
+BFD036DA 0005185E SB V0, 5(S8)\r
+BFD036DE 0005145E LBU V0, 5(S8)\r
+BFD036E2 0004B042 SLTIU V0, V0, 4\r
+BFD036E6 FFDC40A2 BNEZC V0, 0xBFD036A2\r
+BFD036E8 145EFFDC LW S8, 5214(GP)\r
51: JTVIC_PRI->REG32[pidx+j] = (uint32_t)(ih_table[i].pri[j]);\r
-BFD036A2 BFFF41A2 LUI V0, 0xBFFF
-BFD036A4 5082BFFF LDC1 F31, 20610(RA)
-BFD036A6 C3005082 ORI A0, V0, -15616
-BFD036AA 0006147E LBU V1, 6(S8)
-BFD036AE 0005145E LBU V0, 5(S8)
-BFD036B2 06A6 ADDU A1, V1, V0
-BFD036B4 0004145E LBU V0, 4(S8)
-BFD036B8 2524 SLL V0, V0, 2
-BFD036BA 25A4 SLL V1, V0, 2
-BFD036BC 0534 ADDU V0, V0, V1
-BFD036BE 0010FC7E LW V1, 16(S8)
-BFD036C2 05A6 ADDU V1, V1, V0
-BFD036C4 0005145E LBU V0, 5(S8)
-BFD036C8 2524 SLL V0, V0, 2
-BFD036CA 0526 ADDU V0, V1, V0
-BFD036CC 69A1 LW V1, 4(V0)
-BFD036CE 2554 SLL V0, A1, 2
-BFD036D0 0528 ADDU V0, A0, V0
-BFD036D2 E9A0 SW V1, 0(V0)
+BFD036A2 BFFF41A2 LUI V0, 0xBFFF\r
+BFD036A4 5082BFFF LDC1 F31, 20610(RA)\r
+BFD036A6 C3005082 ORI A0, V0, -15616\r
+BFD036AA 0006147E LBU V1, 6(S8)\r
+BFD036AE 0005145E LBU V0, 5(S8)\r
+BFD036B2 06A6 ADDU A1, V1, V0\r
+BFD036B4 0004145E LBU V0, 4(S8)\r
+BFD036B8 2524 SLL V0, V0, 2\r
+BFD036BA 25A4 SLL V1, V0, 2\r
+BFD036BC 0534 ADDU V0, V0, V1\r
+BFD036BE 0010FC7E LW V1, 16(S8)\r
+BFD036C2 05A6 ADDU V1, V1, V0\r
+BFD036C4 0005145E LBU V0, 5(S8)\r
+BFD036C8 2524 SLL V0, V0, 2\r
+BFD036CA 0526 ADDU V0, V1, V0\r
+BFD036CC 69A1 LW V1, 4(V0)\r
+BFD036CE 2554 SLL V0, A1, 2\r
+BFD036D0 0528 ADDU V0, A0, V0\r
+BFD036D2 E9A0 SW V1, 0(V0)\r
52: }\r
53: d = ih_table[i].isr_addr & ~(1ul << 0);\r
-BFD036EA 0004145E LBU V0, 4(S8)
-BFD036EE 2524 SLL V0, V0, 2
-BFD036F0 25A4 SLL V1, V0, 2
-BFD036F2 0534 ADDU V0, V0, V1
-BFD036F4 0010FC7E LW V1, 16(S8)
-BFD036F8 0526 ADDU V0, V1, V0
-BFD036FA 69A0 LW V1, 0(V0)
-BFD036FC FFFE3040 ADDIU V0, ZERO, -2
-BFD036FE 4493FFFE LW RA, 17555(S8)
-BFD03700 4493 AND16 V0, V1
-BFD03702 0000F85E SW V0, 0(S8)
+BFD036EA 0004145E LBU V0, 4(S8)\r
+BFD036EE 2524 SLL V0, V0, 2\r
+BFD036F0 25A4 SLL V1, V0, 2\r
+BFD036F2 0534 ADDU V0, V0, V1\r
+BFD036F4 0010FC7E LW V1, 16(S8)\r
+BFD036F8 0526 ADDU V0, V1, V0\r
+BFD036FA 69A0 LW V1, 0(V0)\r
+BFD036FC FFFE3040 ADDIU V0, ZERO, -2\r
+BFD036FE 4493FFFE LW RA, 17555(S8)\r
+BFD03700 4493 AND16 V0, V1\r
+BFD03702 0000F85E SW V0, 0(S8)\r
54: if (disagg_bitmap & (1ul << i)) {\r
-BFD03706 0004145E LBU V0, 4(S8)
-BFD0370A 0014FC7E LW V1, 20(S8)
-BFD0370E 10500062 SRLV V0, V0, V1
-BFD03710 2D211050 ADDI V0, S0, 11553
-BFD03712 2D21 ANDI V0, V0, 0x1
-BFD03714 2D2D ANDI V0, V0, 0xFF
-BFD03716 000640E2 BEQZC V0, 0xBFD03726
+BFD03706 0004145E LBU V0, 4(S8)\r
+BFD0370A 0014FC7E LW V1, 20(S8)\r
+BFD0370E 10500062 SRLV V0, V0, V1\r
+BFD03710 2D211050 ADDI V0, S0, 11553\r
+BFD03712 2D21 ANDI V0, V0, 0x1\r
+BFD03714 2D2D ANDI V0, V0, 0xFF\r
+BFD03716 000640E2 BEQZC V0, 0xBFD03726\r
55: d |= (1ul << 0); // dis-aggregate this GIRQ\r
-BFD0371A 0000FC5E LW V0, 0(S8)
-BFD0371E 00015042 ORI V0, V0, 1
-BFD03722 0000F85E SW V0, 0(S8)
+BFD0371A 0000FC5E LW V0, 0(S8)\r
+BFD0371E 00015042 ORI V0, V0, 1\r
+BFD03722 0000F85E SW V0, 0(S8)\r
56: }\r
57: JTVIC_ACTRL->REG32[i] = d;\r
-BFD03726 BFFF41A2 LUI V0, 0xBFFF
-BFD03728 5062BFFF LDC1 F31, 20578(RA)
-BFD0372A C2005062 ORI V1, V0, -15872
-BFD0372E 0004145E LBU V0, 4(S8)
-BFD03732 2524 SLL V0, V0, 2
-BFD03734 0526 ADDU V0, V1, V0
-BFD03736 0000FC7E LW V1, 0(S8)
-BFD0373A E9A0 SW V1, 0(V0)
+BFD03726 BFFF41A2 LUI V0, 0xBFFF\r
+BFD03728 5062BFFF LDC1 F31, 20578(RA)\r
+BFD0372A C2005062 ORI V1, V0, -15872\r
+BFD0372E 0004145E LBU V0, 4(S8)\r
+BFD03732 2524 SLL V0, V0, 2\r
+BFD03734 0526 ADDU V0, V1, V0\r
+BFD03736 0000FC7E LW V1, 0(S8)\r
+BFD0373A E9A0 SW V1, 0(V0)\r
58: }\r
59: \r
60: JTVIC_GROUP_EN_SET->w = 0xFFFFFFFFul; // Enable GIRQ08 - GIRQ18 (all)\r
-BFD03752 BFFF41A2 LUI V0, 0xBFFF
-BFD03754 5042BFFF LDC1 F31, 20546(RA)
-BFD03756 C5085042 ORI V0, V0, -15096
-BFD0375A EDFF LI V1, -1
-BFD0375C E9A0 SW V1, 0(V0)
+BFD03752 BFFF41A2 LUI V0, 0xBFFF\r
+BFD03754 5042BFFF LDC1 F31, 20546(RA)\r
+BFD03756 C5085042 ORI V0, V0, -15096\r
+BFD0375A EDFF LI V1, -1\r
+BFD0375C E9A0 SW V1, 0(V0)\r
61: \r
62: }\r
-BFD0375E 0FBE MOVE SP, S8
-BFD03760 4BC3 LW S8, 12(SP)
-BFD03762 4C09 ADDIU SP, SP, 16
-BFD03764 459F JR16 RA
-BFD03766 0C00 NOP
+BFD0375E 0FBE MOVE SP, S8\r
+BFD03760 4BC3 LW S8, 12(SP)\r
+BFD03762 4C09 ADDIU SP, SP, 16\r
+BFD03764 459F JR16 RA\r
+BFD03766 0C00 NOP\r
63: \r
64: /* Clear JTVIC GIRQn source bit\r
65: *\r
66: */\r
67: void jtvic_clr_source(uint8_t girq_num, uint8_t bit_num)\r
68: {\r
-BFD089F4 4FB0 ADDIU SP, SP, -8
-BFD089F6 CBC1 SW S8, 4(SP)
-BFD089F8 0FDD MOVE S8, SP
-BFD089FA 0C64 MOVE V1, A0
-BFD089FC 0C45 MOVE V0, A1
-BFD089FE 0008187E SB V1, 8(S8)
-BFD08A02 000C185E SB V0, 12(S8)
+BFD089F4 4FB0 ADDIU SP, SP, -8\r
+BFD089F6 CBC1 SW S8, 4(SP)\r
+BFD089F8 0FDD MOVE S8, SP\r
+BFD089FA 0C64 MOVE V1, A0\r
+BFD089FC 0C45 MOVE V0, A1\r
+BFD089FE 0008187E SB V1, 8(S8)\r
+BFD08A02 000C185E SB V0, 12(S8)\r
69: if (girq_num < (MEC14xx_NUM_JTVIC_INTS))\r
-BFD08A06 0008145E LBU V0, 8(S8)
-BFD08A0A 0013B042 SLTIU V0, V0, 19
-BFD08A0E 001340E2 BEQZC V0, 0xBFD08A38
+BFD08A06 0008145E LBU V0, 8(S8)\r
+BFD08A0A 0013B042 SLTIU V0, V0, 19\r
+BFD08A0E 001340E2 BEQZC V0, 0xBFD08A38\r
70: {\r
71: bit_num &= 0x1Fu;\r
-BFD08A12 000C145E LBU V0, 12(S8)
-BFD08A16 2D29 ANDI V0, V0, 0x1F
-BFD08A18 000C185E SB V0, 12(S8)
+BFD08A12 000C145E LBU V0, 12(S8)\r
+BFD08A16 2D29 ANDI V0, V0, 0x1F\r
+BFD08A18 000C185E SB V0, 12(S8)\r
72: JTVIC_GIRQ->REGS[girq_num].SOURCE = (1ul << bit_num);\r
-BFD08A1C BFFF41A2 LUI V0, 0xBFFF
-BFD08A1E 5082BFFF LDC1 F31, 20610(RA)
-BFD08A20 C0005082 ORI A0, V0, -16384
-BFD08A24 0008145E LBU V0, 8(S8)
-BFD08A28 000C147E LBU V1, 12(S8)
-BFD08A2C EE81 LI A1, 1
-BFD08A2E 181000A3 SLLV V1, V1, A1
-BFD08A30 25281810 SB ZERO, 9512(S0)
-BFD08A32 2528 SLL V0, V0, 4
-BFD08A34 0528 ADDU V0, A0, V0
-BFD08A36 E9A0 SW V1, 0(V0)
+BFD08A1C BFFF41A2 LUI V0, 0xBFFF\r
+BFD08A1E 5082BFFF LDC1 F31, 20610(RA)\r
+BFD08A20 C0005082 ORI A0, V0, -16384\r
+BFD08A24 0008145E LBU V0, 8(S8)\r
+BFD08A28 000C147E LBU V1, 12(S8)\r
+BFD08A2C EE81 LI A1, 1\r
+BFD08A2E 181000A3 SLLV V1, V1, A1\r
+BFD08A30 25281810 SB ZERO, 9512(S0)\r
+BFD08A32 2528 SLL V0, V0, 4\r
+BFD08A34 0528 ADDU V0, A0, V0\r
+BFD08A36 E9A0 SW V1, 0(V0)\r
73: }\r
74: }\r
-BFD08A38 0FBE MOVE SP, S8
-BFD08A3A 4BC1 LW S8, 4(SP)
-BFD08A3C 4C05 ADDIU SP, SP, 8
-BFD08A3E 459F JR16 RA
-BFD08A40 0C00 NOP
+BFD08A38 0FBE MOVE SP, S8\r
+BFD08A3A 4BC1 LW S8, 4(SP)\r
+BFD08A3C 4C05 ADDIU SP, SP, 8\r
+BFD08A3E 459F JR16 RA\r
+BFD08A40 0C00 NOP\r
75: \r
76: \r
77: /* Disable GIRQn source with optional clearing of source.\r
80: */\r
81: void jtvic_dis_clr_source(uint8_t girq_num, uint8_t bit_num, uint8_t clr_src)\r
82: {\r
-BFD07480 4FB0 ADDIU SP, SP, -8
-BFD07482 CBC1 SW S8, 4(SP)
-BFD07484 0FDD MOVE S8, SP
-BFD07486 0C65 MOVE V1, A1
-BFD07488 0C46 MOVE V0, A2
-BFD0748A 0008189E SB A0, 8(S8)
-BFD0748E 000C187E SB V1, 12(S8)
-BFD07492 0010185E SB V0, 16(S8)
+BFD07480 4FB0 ADDIU SP, SP, -8\r
+BFD07482 CBC1 SW S8, 4(SP)\r
+BFD07484 0FDD MOVE S8, SP\r
+BFD07486 0C65 MOVE V1, A1\r
+BFD07488 0C46 MOVE V0, A2\r
+BFD0748A 0008189E SB A0, 8(S8)\r
+BFD0748E 000C187E SB V1, 12(S8)\r
+BFD07492 0010185E SB V0, 16(S8)\r
83: if (girq_num < (MEC14xx_NUM_JTVIC_INTS))\r
-BFD07496 0008145E LBU V0, 8(S8)
-BFD0749A 0013B042 SLTIU V0, V0, 19
-BFD0749E 002540E2 BEQZC V0, 0xBFD074EC
+BFD07496 0008145E LBU V0, 8(S8)\r
+BFD0749A 0013B042 SLTIU V0, V0, 19\r
+BFD0749E 002540E2 BEQZC V0, 0xBFD074EC\r
84: {\r
85: bit_num &= 0x1Fu;\r
-BFD074A2 000C145E LBU V0, 12(S8)
-BFD074A6 2D29 ANDI V0, V0, 0x1F
-BFD074A8 000C185E SB V0, 12(S8)
+BFD074A2 000C145E LBU V0, 12(S8)\r
+BFD074A6 2D29 ANDI V0, V0, 0x1F\r
+BFD074A8 000C185E SB V0, 12(S8)\r
86: JTVIC_GIRQ->REGS[girq_num].EN_CLR = (1ul << bit_num);\r
-BFD074AC BFFF41A2 LUI V0, 0xBFFF
-BFD074AE 5082BFFF LDC1 F31, 20610(RA)
-BFD074B0 C0005082 ORI A0, V0, -16384
-BFD074B4 0008145E LBU V0, 8(S8)
-BFD074B8 000C147E LBU V1, 12(S8)
-BFD074BC EE81 LI A1, 1
-BFD074BE 181000A3 SLLV V1, V1, A1
-BFD074C0 25281810 SB ZERO, 9512(S0)
-BFD074C2 2528 SLL V0, V0, 4
-BFD074C4 0528 ADDU V0, A0, V0
-BFD074C6 E9A2 SW V1, 8(V0)
+BFD074AC BFFF41A2 LUI V0, 0xBFFF\r
+BFD074AE 5082BFFF LDC1 F31, 20610(RA)\r
+BFD074B0 C0005082 ORI A0, V0, -16384\r
+BFD074B4 0008145E LBU V0, 8(S8)\r
+BFD074B8 000C147E LBU V1, 12(S8)\r
+BFD074BC EE81 LI A1, 1\r
+BFD074BE 181000A3 SLLV V1, V1, A1\r
+BFD074C0 25281810 SB ZERO, 9512(S0)\r
+BFD074C2 2528 SLL V0, V0, 4\r
+BFD074C4 0528 ADDU V0, A0, V0\r
+BFD074C6 E9A2 SW V1, 8(V0)\r
87: if ( 0 != clr_src )\r
-BFD074C8 0010145E LBU V0, 16(S8)
-BFD074CC 000E40E2 BEQZC V0, 0xBFD074EC
+BFD074C8 0010145E LBU V0, 16(S8)\r
+BFD074CC 000E40E2 BEQZC V0, 0xBFD074EC\r
88: {\r
89: JTVIC_GIRQ->REGS[girq_num].SOURCE = (1ul << bit_num);\r
-BFD074D0 BFFF41A2 LUI V0, 0xBFFF
-BFD074D2 5082BFFF LDC1 F31, 20610(RA)
-BFD074D4 C0005082 ORI A0, V0, -16384
-BFD074D8 0008145E LBU V0, 8(S8)
-BFD074DC 000C147E LBU V1, 12(S8)
-BFD074E0 EE81 LI A1, 1
-BFD074E2 181000A3 SLLV V1, V1, A1
-BFD074E4 25281810 SB ZERO, 9512(S0)
-BFD074E6 2528 SLL V0, V0, 4
-BFD074E8 0528 ADDU V0, A0, V0
-BFD074EA E9A0 SW V1, 0(V0)
+BFD074D0 BFFF41A2 LUI V0, 0xBFFF\r
+BFD074D2 5082BFFF LDC1 F31, 20610(RA)\r
+BFD074D4 C0005082 ORI A0, V0, -16384\r
+BFD074D8 0008145E LBU V0, 8(S8)\r
+BFD074DC 000C147E LBU V1, 12(S8)\r
+BFD074E0 EE81 LI A1, 1\r
+BFD074E2 181000A3 SLLV V1, V1, A1\r
+BFD074E4 25281810 SB ZERO, 9512(S0)\r
+BFD074E6 2528 SLL V0, V0, 4\r
+BFD074E8 0528 ADDU V0, A0, V0\r
+BFD074EA E9A0 SW V1, 0(V0)\r
90: }\r
91: }\r
92: }\r
-BFD074EC 0FBE MOVE SP, S8
-BFD074EE 4BC1 LW S8, 4(SP)
-BFD074F0 4C05 ADDIU SP, SP, 8
-BFD074F2 459F JR16 RA
-BFD074F4 0C00 NOP
+BFD074EC 0FBE MOVE SP, S8\r
+BFD074EE 4BC1 LW S8, 4(SP)\r
+BFD074F0 4C05 ADDIU SP, SP, 8\r
+BFD074F2 459F JR16 RA\r
+BFD074F4 0C00 NOP\r
93: \r
94: \r
95: /* Enable with optional source clear before enable.\r
98: */\r
99: void jtvic_en_source(uint8_t girq_num, uint8_t bit_num, uint8_t clr_src)\r
100: {\r
-BFD074F8 4FB0 ADDIU SP, SP, -8
-BFD074FA CBC1 SW S8, 4(SP)
-BFD074FC 0FDD MOVE S8, SP
-BFD074FE 0C65 MOVE V1, A1
-BFD07500 0C46 MOVE V0, A2
-BFD07502 0008189E SB A0, 8(S8)
-BFD07506 000C187E SB V1, 12(S8)
-BFD0750A 0010185E SB V0, 16(S8)
+BFD074F8 4FB0 ADDIU SP, SP, -8\r
+BFD074FA CBC1 SW S8, 4(SP)\r
+BFD074FC 0FDD MOVE S8, SP\r
+BFD074FE 0C65 MOVE V1, A1\r
+BFD07500 0C46 MOVE V0, A2\r
+BFD07502 0008189E SB A0, 8(S8)\r
+BFD07506 000C187E SB V1, 12(S8)\r
+BFD0750A 0010185E SB V0, 16(S8)\r
101: if (girq_num < (MEC14xx_NUM_JTVIC_INTS))\r
-BFD0750E 0008145E LBU V0, 8(S8)
-BFD07512 0013B042 SLTIU V0, V0, 19
-BFD07516 002540E2 BEQZC V0, 0xBFD07564
+BFD0750E 0008145E LBU V0, 8(S8)\r
+BFD07512 0013B042 SLTIU V0, V0, 19\r
+BFD07516 002540E2 BEQZC V0, 0xBFD07564\r
102: {\r
103: bit_num &= 0x1Fu;\r
-BFD0751A 000C145E LBU V0, 12(S8)
-BFD0751E 2D29 ANDI V0, V0, 0x1F
-BFD07520 000C185E SB V0, 12(S8)
+BFD0751A 000C145E LBU V0, 12(S8)\r
+BFD0751E 2D29 ANDI V0, V0, 0x1F\r
+BFD07520 000C185E SB V0, 12(S8)\r
104: if ( 0 != clr_src )\r
-BFD07524 0010145E LBU V0, 16(S8)
-BFD07528 000E40E2 BEQZC V0, 0xBFD07548
+BFD07524 0010145E LBU V0, 16(S8)\r
+BFD07528 000E40E2 BEQZC V0, 0xBFD07548\r
105: {\r
106: JTVIC_GIRQ->REGS[girq_num].SOURCE = (1ul << bit_num);\r
-BFD0752C BFFF41A2 LUI V0, 0xBFFF
-BFD0752E 5082BFFF LDC1 F31, 20610(RA)
-BFD07530 C0005082 ORI A0, V0, -16384
-BFD07534 0008145E LBU V0, 8(S8)
-BFD07538 000C147E LBU V1, 12(S8)
-BFD0753C EE81 LI A1, 1
-BFD0753E 181000A3 SLLV V1, V1, A1
-BFD07540 25281810 SB ZERO, 9512(S0)
-BFD07542 2528 SLL V0, V0, 4
-BFD07544 0528 ADDU V0, A0, V0
-BFD07546 E9A0 SW V1, 0(V0)
+BFD0752C BFFF41A2 LUI V0, 0xBFFF\r
+BFD0752E 5082BFFF LDC1 F31, 20610(RA)\r
+BFD07530 C0005082 ORI A0, V0, -16384\r
+BFD07534 0008145E LBU V0, 8(S8)\r
+BFD07538 000C147E LBU V1, 12(S8)\r
+BFD0753C EE81 LI A1, 1\r
+BFD0753E 181000A3 SLLV V1, V1, A1\r
+BFD07540 25281810 SB ZERO, 9512(S0)\r
+BFD07542 2528 SLL V0, V0, 4\r
+BFD07544 0528 ADDU V0, A0, V0\r
+BFD07546 E9A0 SW V1, 0(V0)\r
107: }\r
108: JTVIC_GIRQ->REGS[girq_num].EN_SET = (1ul << bit_num);\r
-BFD07548 BFFF41A2 LUI V0, 0xBFFF
-BFD0754A 5082BFFF LDC1 F31, 20610(RA)
-BFD0754C C0005082 ORI A0, V0, -16384
-BFD07550 0008145E LBU V0, 8(S8)
-BFD07554 000C147E LBU V1, 12(S8)
-BFD07558 EE81 LI A1, 1
-BFD0755A 181000A3 SLLV V1, V1, A1
-BFD0755C 25281810 SB ZERO, 9512(S0)
-BFD0755E 2528 SLL V0, V0, 4
-BFD07560 0528 ADDU V0, A0, V0
-BFD07562 E9A1 SW V1, 4(V0)
+BFD07548 BFFF41A2 LUI V0, 0xBFFF\r
+BFD0754A 5082BFFF LDC1 F31, 20610(RA)\r
+BFD0754C C0005082 ORI A0, V0, -16384\r
+BFD07550 0008145E LBU V0, 8(S8)\r
+BFD07554 000C147E LBU V1, 12(S8)\r
+BFD07558 EE81 LI A1, 1\r
+BFD0755A 181000A3 SLLV V1, V1, A1\r
+BFD0755C 25281810 SB ZERO, 9512(S0)\r
+BFD0755E 2528 SLL V0, V0, 4\r
+BFD07560 0528 ADDU V0, A0, V0\r
+BFD07562 E9A1 SW V1, 4(V0)\r
109: }\r
110: }\r
-BFD07564 0FBE MOVE SP, S8
-BFD07566 4BC1 LW S8, 4(SP)
-BFD07568 4C05 ADDIU SP, SP, 8
-BFD0756A 459F JR16 RA
-BFD0756C 0C00 NOP
+BFD07564 0FBE MOVE SP, S8\r
+BFD07566 4BC1 LW S8, 4(SP)\r
+BFD07568 4C05 ADDIU SP, SP, 8\r
+BFD0756A 459F JR16 RA\r
+BFD0756C 0C00 NOP\r
111: \r
112: \r
113: /* end mec14xx_jtvic.c */\r
114: /** @}\r
115: */\r
116: \r
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/mec14xx_gpio.c ---------
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/mec14xx_gpio.c ---------\r
1: /*****************************************************************************\r
2: * © 2014 Microchip Technology Inc. and its subsidiaries.\r
3: * You may use this software and any derivatives exclusively with\r
82: \r
83: static uint32_t gpio_pin_ctrl_addr(enum gpio_id_t gpio_id)\r
84: {\r
-BFD09B28 4FB0 ADDIU SP, SP, -8
-BFD09B2A CBC1 SW S8, 4(SP)
-BFD09B2C 0FDD MOVE S8, SP
-BFD09B2E 0008F89E SW A0, 8(S8)
+BFD09B28 4FB0 ADDIU SP, SP, -8\r
+BFD09B2A CBC1 SW S8, 4(SP)\r
+BFD09B2C 0FDD MOVE S8, SP\r
+BFD09B2E 0008F89E SW A0, 8(S8)\r
85: return ((uint32_t)(GPIO_BASE) + (uint32_t)(gpio_id << 2));\r
-BFD09B32 0008FC5E LW V0, 8(S8)
-BFD09B36 25A4 SLL V1, V0, 2
-BFD09B38 A00841A2 LUI V0, 0xA008
-BFD09B3C 10005042 ORI V0, V0, 4096
-BFD09B3E 05261000 ADDI ZERO, ZERO, 1318
-BFD09B40 0526 ADDU V0, V1, V0
+BFD09B32 0008FC5E LW V0, 8(S8)\r
+BFD09B36 25A4 SLL V1, V0, 2\r
+BFD09B38 A00841A2 LUI V0, 0xA008\r
+BFD09B3C 10005042 ORI V0, V0, 4096\r
+BFD09B3E 05261000 ADDI ZERO, ZERO, 1318\r
+BFD09B40 0526 ADDU V0, V1, V0\r
86: }\r
-BFD09B42 0FBE MOVE SP, S8
-BFD09B44 4BC1 LW S8, 4(SP)
-BFD09B46 4C05 ADDIU SP, SP, 8
-BFD09B48 459F JR16 RA
-BFD09B4A 0C00 NOP
+BFD09B42 0FBE MOVE SP, S8\r
+BFD09B44 4BC1 LW S8, 4(SP)\r
+BFD09B46 4C05 ADDIU SP, SP, 8\r
+BFD09B48 459F JR16 RA\r
+BFD09B4A 0C00 NOP\r
87: \r
88: #ifdef ENABLE_GPIO_PIN_VALIDATION\r
89: \r
100: */\r
101: static uint8_t gpio_is_valid ( enum gpio_id_t gpio_id )\r
102: {\r
-BFD081B4 4FF9 ADDIU SP, SP, -16
-BFD081B6 CBC3 SW S8, 12(SP)
-BFD081B8 0FDD MOVE S8, SP
-BFD081BA 0010F89E SW A0, 16(S8)
+BFD081B4 4FF9 ADDIU SP, SP, -16\r
+BFD081B6 CBC3 SW S8, 12(SP)\r
+BFD081B8 0FDD MOVE S8, SP\r
+BFD081BA 0010F89E SW A0, 16(S8)\r
103: uint16_t gp_bank;\r
104: \r
105: gp_bank = 0;\r
-BFD081BE 0000381E SH ZERO, 0(S8)
+BFD081BE 0000381E SH ZERO, 0(S8)\r
106: \r
107: if ( (uint16_t)gpio_id < (uint16_t)(MAX_GPIO_ID) )\r
-BFD081C2 0010FC5E LW V0, 16(S8)
-BFD081C6 2D2F ANDI V0, V0, 0xFFFF
-BFD081C8 0078B042 SLTIU V0, V0, 120
-BFD081CC 001B40E2 BEQZC V0, 0xBFD08206
+BFD081C2 0010FC5E LW V0, 16(S8)\r
+BFD081C6 2D2F ANDI V0, V0, 0xFFFF\r
+BFD081C8 0078B042 SLTIU V0, V0, 120\r
+BFD081CC 001B40E2 BEQZC V0, 0xBFD08206\r
108: {\r
109: gp_bank = (uint16_t)gpio_id >> 5;\r
-BFD081D0 0010FC5E LW V0, 16(S8)
-BFD081D4 2D2F ANDI V0, V0, 0xFFFF
-BFD081D6 252B SRL V0, V0, 5
-BFD081D8 0000385E SH V0, 0(S8)
+BFD081D0 0010FC5E LW V0, 16(S8)\r
+BFD081D4 2D2F ANDI V0, V0, 0xFFFF\r
+BFD081D6 252B SRL V0, V0, 5\r
+BFD081D8 0000385E SH V0, 0(S8)\r
110: if ( gpio_port_bitmaps[gp_bank] & (1 << (gpio_id & 0x001Fu)) )\r
-BFD081DC 0000347E LHU V1, 0(S8)
-BFD081E0 BFD141A2 LUI V0, 0xBFD1
-BFD081E2 25B4BFD1 LDC1 F30, 9652(S1)
-BFD081E4 25B4 SLL V1, V1, 2
-BFD081E6 92543042 ADDIU V0, V0, -28076
-BFD081E8 05269254 SLTI S2, S4, 1318
-BFD081EA 0526 ADDU V0, V1, V0
-BFD081EC 69A0 LW V1, 0(V0)
-BFD081EE 0010FC5E LW V0, 16(S8)
-BFD081F2 2D29 ANDI V0, V0, 0x1F
-BFD081F4 EE01 LI A0, 1
-BFD081F6 10100082 SLLV V0, V0, A0
-BFD081F8 44931010 ADDI ZERO, S0, 17555
-BFD081FA 4493 AND16 V0, V1
-BFD081FC 000340E2 BEQZC V0, 0xBFD08206
+BFD081DC 0000347E LHU V1, 0(S8)\r
+BFD081E0 BFD141A2 LUI V0, 0xBFD1\r
+BFD081E2 25B4BFD1 LDC1 F30, 9652(S1)\r
+BFD081E4 25B4 SLL V1, V1, 2\r
+BFD081E6 92543042 ADDIU V0, V0, -28076\r
+BFD081E8 05269254 SLTI S2, S4, 1318\r
+BFD081EA 0526 ADDU V0, V1, V0\r
+BFD081EC 69A0 LW V1, 0(V0)\r
+BFD081EE 0010FC5E LW V0, 16(S8)\r
+BFD081F2 2D29 ANDI V0, V0, 0x1F\r
+BFD081F4 EE01 LI A0, 1\r
+BFD081F6 10100082 SLLV V0, V0, A0\r
+BFD081F8 44931010 ADDI ZERO, S0, 17555\r
+BFD081FA 4493 AND16 V0, V1\r
+BFD081FC 000340E2 BEQZC V0, 0xBFD08206\r
111: { \r
112: return true;\r
-BFD08200 ED01 LI V0, 1
-BFD08202 CC02 B 0xBFD08208
-BFD08204 0C00 NOP
+BFD08200 ED01 LI V0, 1\r
+BFD08202 CC02 B 0xBFD08208\r
+BFD08204 0C00 NOP\r
113: }\r
114: }\r
115: \r
116: return false;\r
-BFD08206 0C40 MOVE V0, ZERO
+BFD08206 0C40 MOVE V0, ZERO\r
117: }\r
-BFD08208 0FBE MOVE SP, S8
-BFD0820A 4BC3 LW S8, 12(SP)
-BFD0820C 4C09 ADDIU SP, SP, 16
-BFD0820E 459F JR16 RA
-BFD08210 0C00 NOP
+BFD08208 0FBE MOVE SP, S8\r
+BFD0820A 4BC3 LW S8, 12(SP)\r
+BFD0820C 4C09 ADDIU SP, SP, 16\r
+BFD0820E 459F JR16 RA\r
+BFD08210 0C00 NOP\r
118: \r
119: #else\r
120: static uint32_t gpio_is_valid(enum gpio_id_t gpio_id) { return true; }\r
123: \r
124: static uint8_t gpio_bank_num(enum gpio_id_t gpio_id)\r
125: {\r
-BFD09D2C 4FB0 ADDIU SP, SP, -8
-BFD09D2E CBC1 SW S8, 4(SP)
-BFD09D30 0FDD MOVE S8, SP
-BFD09D32 0008F89E SW A0, 8(S8)
+BFD09D2C 4FB0 ADDIU SP, SP, -8\r
+BFD09D2E CBC1 SW S8, 4(SP)\r
+BFD09D30 0FDD MOVE S8, SP\r
+BFD09D32 0008F89E SW A0, 8(S8)\r
126: return (uint8_t)(gpio_id) >> 5;\r
-BFD09D36 0008FC5E LW V0, 8(S8)
-BFD09D3A 2D2D ANDI V0, V0, 0xFF
-BFD09D3C 252B SRL V0, V0, 5
-BFD09D3E 2D2D ANDI V0, V0, 0xFF
+BFD09D36 0008FC5E LW V0, 8(S8)\r
+BFD09D3A 2D2D ANDI V0, V0, 0xFF\r
+BFD09D3C 252B SRL V0, V0, 5\r
+BFD09D3E 2D2D ANDI V0, V0, 0xFF\r
127: }\r
-BFD09D40 0FBE MOVE SP, S8
-BFD09D42 4BC1 LW S8, 4(SP)
-BFD09D44 4C05 ADDIU SP, SP, 8
-BFD09D46 459F JR16 RA
-BFD09D48 0C00 NOP
+BFD09D40 0FBE MOVE SP, S8\r
+BFD09D42 4BC1 LW S8, 4(SP)\r
+BFD09D44 4C05 ADDIU SP, SP, 8\r
+BFD09D46 459F JR16 RA\r
+BFD09D48 0C00 NOP\r
128: \r
129: \r
130: static uint8_t gpio_pin_num(enum gpio_id_t gpio_id)\r
131: {\r
-BFD09D4C 4FB0 ADDIU SP, SP, -8
-BFD09D4E CBC1 SW S8, 4(SP)
-BFD09D50 0FDD MOVE S8, SP
-BFD09D52 0008F89E SW A0, 8(S8)
+BFD09D4C 4FB0 ADDIU SP, SP, -8\r
+BFD09D4E CBC1 SW S8, 4(SP)\r
+BFD09D50 0FDD MOVE S8, SP\r
+BFD09D52 0008F89E SW A0, 8(S8)\r
132: return (uint8_t)(gpio_id) & 0x1Fu;\r
-BFD09D56 0008FC5E LW V0, 8(S8)
-BFD09D5A 2D2D ANDI V0, V0, 0xFF
-BFD09D5C 2D29 ANDI V0, V0, 0x1F
-BFD09D5E 2D2D ANDI V0, V0, 0xFF
+BFD09D56 0008FC5E LW V0, 8(S8)\r
+BFD09D5A 2D2D ANDI V0, V0, 0xFF\r
+BFD09D5C 2D29 ANDI V0, V0, 0x1F\r
+BFD09D5E 2D2D ANDI V0, V0, 0xFF\r
133: }\r
-BFD09D60 0FBE MOVE SP, S8
-BFD09D62 4BC1 LW S8, 4(SP)
-BFD09D64 4C05 ADDIU SP, SP, 8
-BFD09D66 459F JR16 RA
-BFD09D68 0C00 NOP
+BFD09D60 0FBE MOVE SP, S8\r
+BFD09D62 4BC1 LW S8, 4(SP)\r
+BFD09D64 4C05 ADDIU SP, SP, 8\r
+BFD09D66 459F JR16 RA\r
+BFD09D68 0C00 NOP\r
134: \r
135: \r
136: /**\r
146: */\r
147: static uint32_t gpio_has_drv_str ( enum gpio_id_t gpio_id )\r
148: {\r
-BFD06644 4FED ADDIU SP, SP, -40
-BFD06646 CBE9 SW RA, 36(SP)
-BFD06648 CBC8 SW S8, 32(SP)
-BFD0664A 0FDD MOVE S8, SP
-BFD0664C 0028F89E SW A0, 40(S8)
+BFD06644 4FED ADDIU SP, SP, -40\r
+BFD06646 CBE9 SW RA, 36(SP)\r
+BFD06648 CBC8 SW S8, 32(SP)\r
+BFD0664A 0FDD MOVE S8, SP\r
+BFD0664C 0028F89E SW A0, 40(S8)\r
149: uint32_t bank, bitpos, addr;\r
150: \r
151: addr = 0ul;\r
-BFD06650 0010F81E SW ZERO, 16(S8)
+BFD06650 0010F81E SW ZERO, 16(S8)\r
152: if ( gpio_id < MAX_GPIO_ID )\r
-BFD06654 0028FC5E LW V0, 40(S8)
-BFD06658 0078B042 SLTIU V0, V0, 120
-BFD0665C 003540E2 BEQZC V0, 0xBFD066CA
+BFD06654 0028FC5E LW V0, 40(S8)\r
+BFD06658 0078B042 SLTIU V0, V0, 120\r
+BFD0665C 003540E2 BEQZC V0, 0xBFD066CA\r
153: {\r
154: bank = gpio_bank_num(gpio_id);\r
-BFD06660 0028FC9E LW A0, 40(S8)
-BFD06664 4E9677E8 JALS gpio_bank_num
-BFD06666 4E96 ADDIU S4, S4, -5
-BFD06668 0C00 NOP
-BFD0666A 0014F85E SW V0, 20(S8)
+BFD06660 0028FC9E LW A0, 40(S8)\r
+BFD06664 4E9677E8 JALS gpio_bank_num\r
+BFD06666 4E96 ADDIU S4, S4, -5\r
+BFD06668 0C00 NOP\r
+BFD0666A 0014F85E SW V0, 20(S8)\r
155: bitpos = gpio_pin_num(gpio_id);\r
-BFD0666E 0028FC9E LW A0, 40(S8)
-BFD06672 4EA677E8 JALS gpio_pin_num
-BFD06674 4EA6 ADDIU S5, S5, 3
-BFD06676 0C00 NOP
-BFD06678 0018F85E SW V0, 24(S8)
+BFD0666E 0028FC9E LW A0, 40(S8)\r
+BFD06672 4EA677E8 JALS gpio_pin_num\r
+BFD06674 4EA6 ADDIU S5, S5, 3\r
+BFD06676 0C00 NOP\r
+BFD06678 0018F85E SW V0, 24(S8)\r
156: if ( gpio_drv_str_bitmap[bank] & (1ul << bitpos) )\r
-BFD0667C BFD141A2 LUI V0, 0xBFD1
-BFD0667E FC7EBFD1 LDC1 F30, -898(S1)
-BFD06680 0014FC7E LW V1, 20(S8)
-BFD06684 25B4 SLL V1, V1, 2
-BFD06686 92643042 ADDIU V0, V0, -28060
-BFD06688 05269264 SLTI S3, A0, 1318
-BFD0668A 0526 ADDU V0, V1, V0
-BFD0668C 69A0 LW V1, 0(V0)
-BFD0668E 0018FC5E LW V0, 24(S8)
-BFD06692 10500062 SRLV V0, V0, V1
-BFD06694 2D211050 ADDI V0, S0, 11553
-BFD06696 2D21 ANDI V0, V0, 0x1
-BFD06698 2D2D ANDI V0, V0, 0xFF
-BFD0669A 001640E2 BEQZC V0, 0xBFD066CA
+BFD0667C BFD141A2 LUI V0, 0xBFD1\r
+BFD0667E FC7EBFD1 LDC1 F30, -898(S1)\r
+BFD06680 0014FC7E LW V1, 20(S8)\r
+BFD06684 25B4 SLL V1, V1, 2\r
+BFD06686 92643042 ADDIU V0, V0, -28060\r
+BFD06688 05269264 SLTI S3, A0, 1318\r
+BFD0668A 0526 ADDU V0, V1, V0\r
+BFD0668C 69A0 LW V1, 0(V0)\r
+BFD0668E 0018FC5E LW V0, 24(S8)\r
+BFD06692 10500062 SRLV V0, V0, V1\r
+BFD06694 2D211050 ADDI V0, S0, 11553\r
+BFD06696 2D21 ANDI V0, V0, 0x1\r
+BFD06698 2D2D ANDI V0, V0, 0xFF\r
+BFD0669A 001640E2 BEQZC V0, 0xBFD066CA\r
157: {\r
158: addr = (GPIO_PCTRL2_BASE) + ((uint32_t)(gpio_id) << 2);\r
-BFD0669E 0028FC5E LW V0, 40(S8)
-BFD066A2 25A4 SLL V1, V0, 2
-BFD066A4 A00841A2 LUI V0, 0xA008
-BFD066A8 15005042 ORI V0, V0, 5376
-BFD066AA 05261500 LBU T0, 1318(ZERO)
-BFD066AC 0526 ADDU V0, V1, V0
-BFD066AE 0010F85E SW V0, 16(S8)
+BFD0669E 0028FC5E LW V0, 40(S8)\r
+BFD066A2 25A4 SLL V1, V0, 2\r
+BFD066A4 A00841A2 LUI V0, 0xA008\r
+BFD066A8 15005042 ORI V0, V0, 5376\r
+BFD066AA 05261500 LBU T0, 1318(ZERO)\r
+BFD066AC 0526 ADDU V0, V1, V0\r
+BFD066AE 0010F85E SW V0, 16(S8)\r
159: if ( gpio_id > GPIO_0077_ID )\r
-BFD066B2 0028FC5E LW V0, 40(S8)
-BFD066B6 0040B042 SLTIU V0, V0, 64
-BFD066BA 000640A2 BNEZC V0, 0xBFD066CA
+BFD066B2 0028FC5E LW V0, 40(S8)\r
+BFD066B6 0040B042 SLTIU V0, V0, 64\r
+BFD066BA 000640A2 BNEZC V0, 0xBFD066CA\r
160: {\r
161: addr -= 0x20ul;\r
-BFD066BE 0010FC5E LW V0, 16(S8)
-BFD066C2 FFE03042 ADDIU V0, V0, -32
-BFD066C4 F85EFFE0 LW RA, -1954(ZERO)
-BFD066C6 0010F85E SW V0, 16(S8)
+BFD066BE 0010FC5E LW V0, 16(S8)\r
+BFD066C2 FFE03042 ADDIU V0, V0, -32\r
+BFD066C4 F85EFFE0 LW RA, -1954(ZERO)\r
+BFD066C6 0010F85E SW V0, 16(S8)\r
162: }\r
163: }\r
164: }\r
165: \r
166: return addr;\r
-BFD066CA 0010FC5E LW V0, 16(S8)
+BFD066CA 0010FC5E LW V0, 16(S8)\r
167: }\r
-BFD066CE 0FBE MOVE SP, S8
-BFD066D0 4BE9 LW RA, 36(SP)
-BFD066D2 4BC8 LW S8, 32(SP)
-BFD066D4 4C15 ADDIU SP, SP, 40
-BFD066D6 459F JR16 RA
-BFD066D8 0C00 NOP
+BFD066CE 0FBE MOVE SP, S8\r
+BFD066D0 4BE9 LW RA, 36(SP)\r
+BFD066D2 4BC8 LW S8, 32(SP)\r
+BFD066D4 4C15 ADDIU SP, SP, 40\r
+BFD066D6 459F JR16 RA\r
+BFD066D8 0C00 NOP\r
168: \r
169: \r
170: uint16_t GPIOGetConfig(enum gpio_id_t gpio_id)\r
171: {\r
-BFD09558 4FF5 ADDIU SP, SP, -24
-BFD0955A CBE5 SW RA, 20(SP)
-BFD0955C CBC4 SW S8, 16(SP)
-BFD0955E 0FDD MOVE S8, SP
-BFD09560 0018F89E SW A0, 24(S8)
+BFD09558 4FF5 ADDIU SP, SP, -24\r
+BFD0955A CBE5 SW RA, 20(SP)\r
+BFD0955C CBC4 SW S8, 16(SP)\r
+BFD0955E 0FDD MOVE S8, SP\r
+BFD09560 0018F89E SW A0, 24(S8)\r
172: if (gpio_is_valid(gpio_id)) {\r
-BFD09564 0018FC9E LW A0, 24(S8)
-BFD09568 40DA77E8 JALS gpio_is_valid
-BFD0956A 0C0040DA BGTZ K0, 0xBFD0AD6E
-BFD0956C 0C00 NOP
-BFD0956E 000940E2 BEQZC V0, 0xBFD09584
+BFD09564 0018FC9E LW A0, 24(S8)\r
+BFD09568 40DA77E8 JALS gpio_is_valid\r
+BFD0956A 0C0040DA BGTZ K0, 0xBFD0AD6E\r
+BFD0956C 0C00 NOP\r
+BFD0956E 000940E2 BEQZC V0, 0xBFD09584\r
173: return *((volatile uint16_t *)gpio_pin_ctrl_addr(gpio_id));\r
-BFD09572 0018FC9E LW A0, 24(S8)
-BFD09576 4D9477E8 JALS gpio_pin_ctrl_addr
-BFD09578 4D94 ADDIU T4, T4, -6
-BFD0957A 0C00 NOP
-BFD0957C 2920 LHU V0, 0(V0)
-BFD0957E 2D2F ANDI V0, V0, 0xFFFF
-BFD09580 CC02 B 0xBFD09586
-BFD09582 0C00 NOP
+BFD09572 0018FC9E LW A0, 24(S8)\r
+BFD09576 4D9477E8 JALS gpio_pin_ctrl_addr\r
+BFD09578 4D94 ADDIU T4, T4, -6\r
+BFD0957A 0C00 NOP\r
+BFD0957C 2920 LHU V0, 0(V0)\r
+BFD0957E 2D2F ANDI V0, V0, 0xFFFF\r
+BFD09580 CC02 B 0xBFD09586\r
+BFD09582 0C00 NOP\r
174: } else {\r
175: return 0u;\r
-BFD09584 0C40 MOVE V0, ZERO
+BFD09584 0C40 MOVE V0, ZERO\r
176: }\r
177: }\r
-BFD09586 0FBE MOVE SP, S8
-BFD09588 4BE5 LW RA, 20(SP)
-BFD0958A 4BC4 LW S8, 16(SP)
-BFD0958C 4C0D ADDIU SP, SP, 24
-BFD0958E 459F JR16 RA
-BFD09590 0C00 NOP
+BFD09586 0FBE MOVE SP, S8\r
+BFD09588 4BE5 LW RA, 20(SP)\r
+BFD0958A 4BC4 LW S8, 16(SP)\r
+BFD0958C 4C0D ADDIU SP, SP, 24\r
+BFD0958E 459F JR16 RA\r
+BFD09590 0C00 NOP\r
178: \r
179: \r
180: void GPIOSetConfig(enum gpio_id_t gpio_id, uint16_t config)\r
181: {\r
-BFD09298 4FF1 ADDIU SP, SP, -32
-BFD0929A CBE7 SW RA, 28(SP)
-BFD0929C CBC6 SW S8, 24(SP)
-BFD0929E 0FDD MOVE S8, SP
-BFD092A0 0020F89E SW A0, 32(S8)
-BFD092A2 0C450020 CMP.LT.PH AT, ZERO
-BFD092A4 0C45 MOVE V0, A1
-BFD092A6 0024385E SH V0, 36(S8)
+BFD09298 4FF1 ADDIU SP, SP, -32\r
+BFD0929A CBE7 SW RA, 28(SP)\r
+BFD0929C CBC6 SW S8, 24(SP)\r
+BFD0929E 0FDD MOVE S8, SP\r
+BFD092A0 0020F89E SW A0, 32(S8)\r
+BFD092A2 0C450020 CMP.LT.PH AT, ZERO\r
+BFD092A4 0C45 MOVE V0, A1\r
+BFD092A6 0024385E SH V0, 36(S8)\r
182: volatile uint16_t * p;\r
183: \r
184: if (gpio_is_valid(gpio_id)) {\r
-BFD092AA 0020FC9E LW A0, 32(S8)
-BFD092AE 40DA77E8 JALS gpio_is_valid
-BFD092B0 0C0040DA BGTZ K0, 0xBFD0AAB4
-BFD092B2 0C00 NOP
-BFD092B4 000C40E2 BEQZC V0, 0xBFD092D0
+BFD092AA 0020FC9E LW A0, 32(S8)\r
+BFD092AE 40DA77E8 JALS gpio_is_valid\r
+BFD092B0 0C0040DA BGTZ K0, 0xBFD0AAB4\r
+BFD092B2 0C00 NOP\r
+BFD092B4 000C40E2 BEQZC V0, 0xBFD092D0\r
185: p = (volatile uint16_t *)gpio_pin_ctrl_addr(gpio_id);\r
-BFD092B8 0020FC9E LW A0, 32(S8)
-BFD092BC 4D9477E8 JALS gpio_pin_ctrl_addr
-BFD092BE 4D94 ADDIU T4, T4, -6
-BFD092C0 0C00 NOP
-BFD092C2 0010F85E SW V0, 16(S8)
+BFD092B8 0020FC9E LW A0, 32(S8)\r
+BFD092BC 4D9477E8 JALS gpio_pin_ctrl_addr\r
+BFD092BE 4D94 ADDIU T4, T4, -6\r
+BFD092C0 0C00 NOP\r
+BFD092C2 0010F85E SW V0, 16(S8)\r
186: *p = config;\r
-BFD092C6 0010FC5E LW V0, 16(S8)
-BFD092CA 0024347E LHU V1, 36(S8)
-BFD092CE A9A0 SH V1, 0(V0)
+BFD092C6 0010FC5E LW V0, 16(S8)\r
+BFD092CA 0024347E LHU V1, 36(S8)\r
+BFD092CE A9A0 SH V1, 0(V0)\r
187: }\r
188: }\r
-BFD092D0 0FBE MOVE SP, S8
-BFD092D2 4BE7 LW RA, 28(SP)
-BFD092D4 4BC6 LW S8, 24(SP)
-BFD092D6 4C11 ADDIU SP, SP, 32
-BFD092D8 459F JR16 RA
-BFD092DA 0C00 NOP
+BFD092D0 0FBE MOVE SP, S8\r
+BFD092D2 4BE7 LW RA, 28(SP)\r
+BFD092D4 4BC6 LW S8, 24(SP)\r
+BFD092D6 4C11 ADDIU SP, SP, 32\r
+BFD092D8 459F JR16 RA\r
+BFD092DA 0C00 NOP\r
189: \r
190: \r
191: void GPIOConfigAndOr(enum gpio_id_t gpio_id, uint16_t and_mask, uint16_t or_mask)\r
192: {\r
-BFD08214 4FF1 ADDIU SP, SP, -32
-BFD08216 CBE7 SW RA, 28(SP)
-BFD08218 CBC6 SW S8, 24(SP)
-BFD0821A 0FDD MOVE S8, SP
-BFD0821C 0020F89E SW A0, 32(S8)
-BFD0821E 0C650020 MULEQ_S.W.PHR AT, ZERO, AT
-BFD08220 0C65 MOVE V1, A1
-BFD08222 0C46 MOVE V0, A2
-BFD08224 0024387E SH V1, 36(S8)
-BFD08228 0028385E SH V0, 40(S8)
+BFD08214 4FF1 ADDIU SP, SP, -32\r
+BFD08216 CBE7 SW RA, 28(SP)\r
+BFD08218 CBC6 SW S8, 24(SP)\r
+BFD0821A 0FDD MOVE S8, SP\r
+BFD0821C 0020F89E SW A0, 32(S8)\r
+BFD0821E 0C650020 MULEQ_S.W.PHR AT, ZERO, AT\r
+BFD08220 0C65 MOVE V1, A1\r
+BFD08222 0C46 MOVE V0, A2\r
+BFD08224 0024387E SH V1, 36(S8)\r
+BFD08228 0028385E SH V0, 40(S8)\r
193: volatile uint16_t * p;\r
194: \r
195: \r
196: if (gpio_is_valid(gpio_id)) {\r
-BFD0822C 0020FC9E LW A0, 32(S8)
-BFD08230 40DA77E8 JALS gpio_is_valid
-BFD08232 0C0040DA BGTZ K0, 0xBFD09A36
-BFD08234 0C00 NOP
-BFD08236 001640E2 BEQZC V0, 0xBFD08266
+BFD0822C 0020FC9E LW A0, 32(S8)\r
+BFD08230 40DA77E8 JALS gpio_is_valid\r
+BFD08232 0C0040DA BGTZ K0, 0xBFD09A36\r
+BFD08234 0C00 NOP\r
+BFD08236 001640E2 BEQZC V0, 0xBFD08266\r
197: p = (volatile uint16_t *)gpio_pin_ctrl_addr(gpio_id);\r
-BFD0823A 0020FC9E LW A0, 32(S8)
-BFD0823E 4D9477E8 JALS gpio_pin_ctrl_addr
-BFD08240 4D94 ADDIU T4, T4, -6
-BFD08242 0C00 NOP
-BFD08244 0010F85E SW V0, 16(S8)
+BFD0823A 0020FC9E LW A0, 32(S8)\r
+BFD0823E 4D9477E8 JALS gpio_pin_ctrl_addr\r
+BFD08240 4D94 ADDIU T4, T4, -6\r
+BFD08242 0C00 NOP\r
+BFD08244 0010F85E SW V0, 16(S8)\r
198: *p = (*p & and_mask) | or_mask;\r
-BFD08248 0010FC5E LW V0, 16(S8)
-BFD0824C 2920 LHU V0, 0(V0)
-BFD0824E 2DAF ANDI V1, V0, 0xFFFF
-BFD08250 0024345E LHU V0, 36(S8)
-BFD08254 4493 AND16 V0, V1
-BFD08256 2DAF ANDI V1, V0, 0xFFFF
-BFD08258 0028345E LHU V0, 40(S8)
-BFD0825C 44D3 OR16 V0, V1
-BFD0825E 2DAF ANDI V1, V0, 0xFFFF
-BFD08260 0010FC5E LW V0, 16(S8)
-BFD08264 A9A0 SH V1, 0(V0)
+BFD08248 0010FC5E LW V0, 16(S8)\r
+BFD0824C 2920 LHU V0, 0(V0)\r
+BFD0824E 2DAF ANDI V1, V0, 0xFFFF\r
+BFD08250 0024345E LHU V0, 36(S8)\r
+BFD08254 4493 AND16 V0, V1\r
+BFD08256 2DAF ANDI V1, V0, 0xFFFF\r
+BFD08258 0028345E LHU V0, 40(S8)\r
+BFD0825C 44D3 OR16 V0, V1\r
+BFD0825E 2DAF ANDI V1, V0, 0xFFFF\r
+BFD08260 0010FC5E LW V0, 16(S8)\r
+BFD08264 A9A0 SH V1, 0(V0)\r
199: }\r
200: }\r
-BFD08266 0FBE MOVE SP, S8
-BFD08268 4BE7 LW RA, 28(SP)
-BFD0826A 4BC6 LW S8, 24(SP)
-BFD0826C 4C11 ADDIU SP, SP, 32
-BFD0826E 459F JR16 RA
-BFD08270 0C00 NOP
+BFD08266 0FBE MOVE SP, S8\r
+BFD08268 4BE7 LW RA, 28(SP)\r
+BFD0826A 4BC6 LW S8, 24(SP)\r
+BFD0826C 4C11 ADDIU SP, SP, 32\r
+BFD0826E 459F JR16 RA\r
+BFD08270 0C00 NOP\r
201: \r
202: \r
203: uint32_t GPIOGetControl(enum gpio_id_t gpio_id)\r
204: {\r
-BFD09770 4FF5 ADDIU SP, SP, -24
-BFD09772 CBE5 SW RA, 20(SP)
-BFD09774 CBC4 SW S8, 16(SP)
-BFD09776 0FDD MOVE S8, SP
-BFD09778 0018F89E SW A0, 24(S8)
+BFD09770 4FF5 ADDIU SP, SP, -24\r
+BFD09772 CBE5 SW RA, 20(SP)\r
+BFD09774 CBC4 SW S8, 16(SP)\r
+BFD09776 0FDD MOVE S8, SP\r
+BFD09778 0018F89E SW A0, 24(S8)\r
205: if (gpio_is_valid(gpio_id)) {\r
-BFD0977C 0018FC9E LW A0, 24(S8)
-BFD09780 40DA77E8 JALS gpio_is_valid
-BFD09782 0C0040DA BGTZ K0, 0xBFD0AF86
-BFD09784 0C00 NOP
-BFD09786 000840E2 BEQZC V0, 0xBFD0979A
+BFD0977C 0018FC9E LW A0, 24(S8)\r
+BFD09780 40DA77E8 JALS gpio_is_valid\r
+BFD09782 0C0040DA BGTZ K0, 0xBFD0AF86\r
+BFD09784 0C00 NOP\r
+BFD09786 000840E2 BEQZC V0, 0xBFD0979A\r
206: return *((volatile uint32_t *)gpio_pin_ctrl_addr(gpio_id));\r
-BFD0978A 0018FC9E LW A0, 24(S8)
-BFD0978E 4D9477E8 JALS gpio_pin_ctrl_addr
-BFD09790 4D94 ADDIU T4, T4, -6
-BFD09792 0C00 NOP
-BFD09794 6920 LW V0, 0(V0)
-BFD09796 CC02 B 0xBFD0979C
-BFD09798 0C00 NOP
+BFD0978A 0018FC9E LW A0, 24(S8)\r
+BFD0978E 4D9477E8 JALS gpio_pin_ctrl_addr\r
+BFD09790 4D94 ADDIU T4, T4, -6\r
+BFD09792 0C00 NOP\r
+BFD09794 6920 LW V0, 0(V0)\r
+BFD09796 CC02 B 0xBFD0979C\r
+BFD09798 0C00 NOP\r
207: } else {\r
208: return 0xFFFFFFFFul;\r
-BFD0979A ED7F LI V0, -1
+BFD0979A ED7F LI V0, -1\r
209: }\r
210: }\r
-BFD0979C 0FBE MOVE SP, S8
-BFD0979E 4BE5 LW RA, 20(SP)
-BFD097A0 4BC4 LW S8, 16(SP)
-BFD097A2 4C0D ADDIU SP, SP, 24
-BFD097A4 459F JR16 RA
-BFD097A6 0C00 NOP
+BFD0979C 0FBE MOVE SP, S8\r
+BFD0979E 4BE5 LW RA, 20(SP)\r
+BFD097A0 4BC4 LW S8, 16(SP)\r
+BFD097A2 4C0D ADDIU SP, SP, 24\r
+BFD097A4 459F JR16 RA\r
+BFD097A6 0C00 NOP\r
211: \r
212: \r
213: void GPIOSetControl(enum gpio_id_t gpio_id, uint32_t ctrl_val)\r
214: {\r
-BFD092DC 4FF1 ADDIU SP, SP, -32
-BFD092DE CBE7 SW RA, 28(SP)
-BFD092E0 CBC6 SW S8, 24(SP)
-BFD092E2 0FDD MOVE S8, SP
-BFD092E4 0020F89E SW A0, 32(S8)
-BFD092E8 0024F8BE SW A1, 36(S8)
+BFD092DC 4FF1 ADDIU SP, SP, -32\r
+BFD092DE CBE7 SW RA, 28(SP)\r
+BFD092E0 CBC6 SW S8, 24(SP)\r
+BFD092E2 0FDD MOVE S8, SP\r
+BFD092E4 0020F89E SW A0, 32(S8)\r
+BFD092E8 0024F8BE SW A1, 36(S8)\r
215: volatile uint32_t * p;\r
216: \r
217: if (gpio_is_valid(gpio_id)) {\r
-BFD092EC 0020FC9E LW A0, 32(S8)
-BFD092F0 40DA77E8 JALS gpio_is_valid
-BFD092F2 0C0040DA BGTZ K0, 0xBFD0AAF6
-BFD092F4 0C00 NOP
-BFD092F6 000C40E2 BEQZC V0, 0xBFD09312
+BFD092EC 0020FC9E LW A0, 32(S8)\r
+BFD092F0 40DA77E8 JALS gpio_is_valid\r
+BFD092F2 0C0040DA BGTZ K0, 0xBFD0AAF6\r
+BFD092F4 0C00 NOP\r
+BFD092F6 000C40E2 BEQZC V0, 0xBFD09312\r
218: p = (volatile uint32_t *)gpio_pin_ctrl_addr(gpio_id);\r
-BFD092FA 0020FC9E LW A0, 32(S8)
-BFD092FE 4D9477E8 JALS gpio_pin_ctrl_addr
-BFD09300 4D94 ADDIU T4, T4, -6
-BFD09302 0C00 NOP
-BFD09304 0010F85E SW V0, 16(S8)
+BFD092FA 0020FC9E LW A0, 32(S8)\r
+BFD092FE 4D9477E8 JALS gpio_pin_ctrl_addr\r
+BFD09300 4D94 ADDIU T4, T4, -6\r
+BFD09302 0C00 NOP\r
+BFD09304 0010F85E SW V0, 16(S8)\r
219: *p = ctrl_val;\r
-BFD09308 0010FC5E LW V0, 16(S8)
-BFD0930C 0024FC7E LW V1, 36(S8)
-BFD09310 E9A0 SW V1, 0(V0)
+BFD09308 0010FC5E LW V0, 16(S8)\r
+BFD0930C 0024FC7E LW V1, 36(S8)\r
+BFD09310 E9A0 SW V1, 0(V0)\r
220: }\r
221: }\r
-BFD09312 0FBE MOVE SP, S8
-BFD09314 4BE7 LW RA, 28(SP)
-BFD09316 4BC6 LW S8, 24(SP)
-BFD09318 4C11 ADDIU SP, SP, 32
-BFD0931A 459F JR16 RA
-BFD0931C 0C00 NOP
+BFD09312 0FBE MOVE SP, S8\r
+BFD09314 4BE7 LW RA, 28(SP)\r
+BFD09316 4BC6 LW S8, 24(SP)\r
+BFD09318 4C11 ADDIU SP, SP, 32\r
+BFD0931A 459F JR16 RA\r
+BFD0931C 0C00 NOP\r
222: \r
223: \r
224: void GPIOControlAndOr(enum gpio_id_t gpio_id, uint32_t and_mask, uint32_t or_mask)\r
225: {\r
-BFD08804 4FF1 ADDIU SP, SP, -32
-BFD08806 CBE7 SW RA, 28(SP)
-BFD08808 CBC6 SW S8, 24(SP)
-BFD0880A 0FDD MOVE S8, SP
-BFD0880C 0020F89E SW A0, 32(S8)
-BFD08810 0024F8BE SW A1, 36(S8)
-BFD08814 0028F8DE SW A2, 40(S8)
+BFD08804 4FF1 ADDIU SP, SP, -32\r
+BFD08806 CBE7 SW RA, 28(SP)\r
+BFD08808 CBC6 SW S8, 24(SP)\r
+BFD0880A 0FDD MOVE S8, SP\r
+BFD0880C 0020F89E SW A0, 32(S8)\r
+BFD08810 0024F8BE SW A1, 36(S8)\r
+BFD08814 0028F8DE SW A2, 40(S8)\r
226: volatile uint32_t * p;\r
227: \r
228: if (gpio_is_valid(gpio_id)) {\r
-BFD08818 0020FC9E LW A0, 32(S8)
-BFD0881C 40DA77E8 JALS gpio_is_valid
-BFD0881E 0C0040DA BGTZ K0, 0xBFD0A022
-BFD08820 0C00 NOP
-BFD08822 001340E2 BEQZC V0, 0xBFD0884C
+BFD08818 0020FC9E LW A0, 32(S8)\r
+BFD0881C 40DA77E8 JALS gpio_is_valid\r
+BFD0881E 0C0040DA BGTZ K0, 0xBFD0A022\r
+BFD08820 0C00 NOP\r
+BFD08822 001340E2 BEQZC V0, 0xBFD0884C\r
229: p = (volatile uint32_t *)gpio_pin_ctrl_addr(gpio_id);\r
-BFD08826 0020FC9E LW A0, 32(S8)
-BFD0882A 4D9477E8 JALS gpio_pin_ctrl_addr
-BFD0882C 4D94 ADDIU T4, T4, -6
-BFD0882E 0C00 NOP
-BFD08830 0010F85E SW V0, 16(S8)
+BFD08826 0020FC9E LW A0, 32(S8)\r
+BFD0882A 4D9477E8 JALS gpio_pin_ctrl_addr\r
+BFD0882C 4D94 ADDIU T4, T4, -6\r
+BFD0882E 0C00 NOP\r
+BFD08830 0010F85E SW V0, 16(S8)\r
230: *p = (*p & and_mask) | or_mask;\r
-BFD08834 0010FC5E LW V0, 16(S8)
-BFD08838 69A0 LW V1, 0(V0)
-BFD0883A 0024FC5E LW V0, 36(S8)
-BFD0883E 449A AND16 V1, V0
-BFD08840 0028FC5E LW V0, 40(S8)
-BFD08844 44DA OR16 V1, V0
-BFD08846 0010FC5E LW V0, 16(S8)
-BFD0884A E9A0 SW V1, 0(V0)
+BFD08834 0010FC5E LW V0, 16(S8)\r
+BFD08838 69A0 LW V1, 0(V0)\r
+BFD0883A 0024FC5E LW V0, 36(S8)\r
+BFD0883E 449A AND16 V1, V0\r
+BFD08840 0028FC5E LW V0, 40(S8)\r
+BFD08844 44DA OR16 V1, V0\r
+BFD08846 0010FC5E LW V0, 16(S8)\r
+BFD0884A E9A0 SW V1, 0(V0)\r
231: }\r
232: }\r
-BFD0884C 0FBE MOVE SP, S8
-BFD0884E 4BE7 LW RA, 28(SP)
-BFD08850 4BC6 LW S8, 24(SP)
-BFD08852 4C11 ADDIU SP, SP, 32
-BFD08854 459F JR16 RA
-BFD08856 0C00 NOP
+BFD0884C 0FBE MOVE SP, S8\r
+BFD0884E 4BE7 LW RA, 28(SP)\r
+BFD08850 4BC6 LW S8, 24(SP)\r
+BFD08852 4C11 ADDIU SP, SP, 32\r
+BFD08854 459F JR16 RA\r
+BFD08856 0C00 NOP\r
233: \r
234: \r
235: /**\r
247: uint16_t prop_val\r
248: )\r
249: {\r
-BFD04B98 4FF1 ADDIU SP, SP, -32
-BFD04B9A CBE7 SW RA, 28(SP)
-BFD04B9C CBC6 SW S8, 24(SP)
-BFD04B9E 0FDD MOVE S8, SP
-BFD04BA0 0020F89E SW A0, 32(S8)
-BFD04BA4 0024F8BE SW A1, 36(S8)
-BFD04BA8 0C46 MOVE V0, A2
-BFD04BAA 0028385E SH V0, 40(S8)
+BFD04B98 4FF1 ADDIU SP, SP, -32\r
+BFD04B9A CBE7 SW RA, 28(SP)\r
+BFD04B9C CBC6 SW S8, 24(SP)\r
+BFD04B9E 0FDD MOVE S8, SP\r
+BFD04BA0 0020F89E SW A0, 32(S8)\r
+BFD04BA4 0024F8BE SW A1, 36(S8)\r
+BFD04BA8 0C46 MOVE V0, A2\r
+BFD04BAA 0028385E SH V0, 40(S8)\r
250: volatile uint16_t * p;\r
251: uint16_t gp_cfg;\r
252: \r
253: gp_cfg = 0u;\r
-BFD04BAE 0010381E SH ZERO, 16(S8)
+BFD04BAE 0010381E SH ZERO, 16(S8)\r
254: \r
255: if ( gpio_is_valid(gpio_id) && ((uint16_t)gpio_prop < (uint16_t)GPIO_PROP_MAX) )\r
-BFD04BB2 0020FC9E LW A0, 32(S8)
-BFD04BB6 40DA77E8 JALS gpio_is_valid
-BFD04BB8 0C0040DA BGTZ K0, 0xBFD063BC
-BFD04BBA 0C00 NOP
-BFD04BBC 005140E2 BEQZC V0, 0xBFD04C62
-BFD04BC0 0024FC5E LW V0, 36(S8)
-BFD04BC4 2D2F ANDI V0, V0, 0xFFFF
-BFD04BC6 0009B042 SLTIU V0, V0, 9
-BFD04BCA 004A40E2 BEQZC V0, 0xBFD04C62
+BFD04BB2 0020FC9E LW A0, 32(S8)\r
+BFD04BB6 40DA77E8 JALS gpio_is_valid\r
+BFD04BB8 0C0040DA BGTZ K0, 0xBFD063BC\r
+BFD04BBA 0C00 NOP\r
+BFD04BBC 005140E2 BEQZC V0, 0xBFD04C62\r
+BFD04BC0 0024FC5E LW V0, 36(S8)\r
+BFD04BC4 2D2F ANDI V0, V0, 0xFFFF\r
+BFD04BC6 0009B042 SLTIU V0, V0, 9\r
+BFD04BCA 004A40E2 BEQZC V0, 0xBFD04C62\r
256: {\r
257: p = (volatile uint16_t *)gpio_pin_ctrl_addr(gpio_id);\r
-BFD04BCE 0020FC9E LW A0, 32(S8)
-BFD04BD2 4D9477E8 JALS gpio_pin_ctrl_addr
-BFD04BD4 4D94 ADDIU T4, T4, -6
-BFD04BD6 0C00 NOP
-BFD04BD8 0014F85E SW V0, 20(S8)
+BFD04BCE 0020FC9E LW A0, 32(S8)\r
+BFD04BD2 4D9477E8 JALS gpio_pin_ctrl_addr\r
+BFD04BD4 4D94 ADDIU T4, T4, -6\r
+BFD04BD6 0C00 NOP\r
+BFD04BD8 0014F85E SW V0, 20(S8)\r
258: gp_cfg = *p;\r
-BFD04BDC 0014FC5E LW V0, 20(S8)
-BFD04BE0 2920 LHU V0, 0(V0)
-BFD04BE2 0010385E SH V0, 16(S8)
+BFD04BDC 0014FC5E LW V0, 20(S8)\r
+BFD04BE0 2920 LHU V0, 0(V0)\r
+BFD04BE2 0010385E SH V0, 16(S8)\r
259: gp_cfg &= ~(gpio_cfg_tbl[gpio_prop].bit_mask);\r
-BFD04BE6 BFD141A2 LUI V0, 0xBFD1
-BFD04BE8 FC7EBFD1 LDC1 F30, -898(S1)
-BFD04BEA 0024FC7E LW V1, 36(S8)
-BFD04BEE 25B4 SLL V1, V1, 2
-BFD04BF0 92743042 ADDIU V0, V0, -28044
-BFD04BF2 05269274 SLTI S3, S4, 1318
-BFD04BF4 0526 ADDU V0, V1, V0
-BFD04BF6 2920 LHU V0, 0(V0)
-BFD04BF8 3B3C0042 SEH V0, V0
-BFD04BFA 44123B3C SH T9, 17426(GP)
-BFD04BFC 4412 NOT16 V0, V0
-BFD04BFE 3B3C0062 SEH V1, V0
-BFD04C00 3C5E3B3C SH T9, 15454(GP)
-BFD04C02 00103C5E LH V0, 16(S8)
-BFD04C06 4493 AND16 V0, V1
-BFD04C08 3B3C0042 SEH V0, V0
-BFD04C0A 385E3B3C SH T9, 14430(GP)
-BFD04C0C 0010385E SH V0, 16(S8)
+BFD04BE6 BFD141A2 LUI V0, 0xBFD1\r
+BFD04BE8 FC7EBFD1 LDC1 F30, -898(S1)\r
+BFD04BEA 0024FC7E LW V1, 36(S8)\r
+BFD04BEE 25B4 SLL V1, V1, 2\r
+BFD04BF0 92743042 ADDIU V0, V0, -28044\r
+BFD04BF2 05269274 SLTI S3, S4, 1318\r
+BFD04BF4 0526 ADDU V0, V1, V0\r
+BFD04BF6 2920 LHU V0, 0(V0)\r
+BFD04BF8 3B3C0042 SEH V0, V0\r
+BFD04BFA 44123B3C SH T9, 17426(GP)\r
+BFD04BFC 4412 NOT16 V0, V0\r
+BFD04BFE 3B3C0062 SEH V1, V0\r
+BFD04C00 3C5E3B3C SH T9, 15454(GP)\r
+BFD04C02 00103C5E LH V0, 16(S8)\r
+BFD04C06 4493 AND16 V0, V1\r
+BFD04C08 3B3C0042 SEH V0, V0\r
+BFD04C0A 385E3B3C SH T9, 14430(GP)\r
+BFD04C0C 0010385E SH V0, 16(S8)\r
260: gp_cfg |= (prop_val << gpio_cfg_tbl[gpio_prop].bit_pos) & \r
-BFD04C10 0028347E LHU V1, 40(S8)
-BFD04C14 BFD141A2 LUI V0, 0xBFD1
-BFD04C16 FC9EBFD1 LDC1 F30, -866(S1)
-BFD04C18 0024FC9E LW A0, 36(S8)
-BFD04C1C 2644 SLL A0, A0, 2
-BFD04C1E 92743042 ADDIU V0, V0, -28044
-BFD04C20 05289274 SLTI S3, S4, 1320
-BFD04C22 0528 ADDU V0, A0, V0
-BFD04C24 0922 LBU V0, 2(V0)
-BFD04C26 10100062 SLLV V0, V0, V1
-BFD04C28 00621010 ADDI ZERO, S0, 98
-BFD04C2A 3B3C0062 SEH V1, V0
-BFD04C2C 41A23B3C SH T9, 16802(GP)
-BFD04C40 3B3C0042 SEH V0, V0
-BFD04C42 44933B3C SH T9, 17555(GP)
-BFD04C44 4493 AND16 V0, V1
-BFD04C46 3B3C0062 SEH V1, V0
-BFD04C48 3C5E3B3C SH T9, 15454(GP)
-BFD04C4A 00103C5E LH V0, 16(S8)
-BFD04C4E 44D3 OR16 V0, V1
-BFD04C50 3B3C0042 SEH V0, V0
-BFD04C52 385E3B3C SH T9, 14430(GP)
-BFD04C54 0010385E SH V0, 16(S8)
+BFD04C10 0028347E LHU V1, 40(S8)\r
+BFD04C14 BFD141A2 LUI V0, 0xBFD1\r
+BFD04C16 FC9EBFD1 LDC1 F30, -866(S1)\r
+BFD04C18 0024FC9E LW A0, 36(S8)\r
+BFD04C1C 2644 SLL A0, A0, 2\r
+BFD04C1E 92743042 ADDIU V0, V0, -28044\r
+BFD04C20 05289274 SLTI S3, S4, 1320\r
+BFD04C22 0528 ADDU V0, A0, V0\r
+BFD04C24 0922 LBU V0, 2(V0)\r
+BFD04C26 10100062 SLLV V0, V0, V1\r
+BFD04C28 00621010 ADDI ZERO, S0, 98\r
+BFD04C2A 3B3C0062 SEH V1, V0\r
+BFD04C2C 41A23B3C SH T9, 16802(GP)\r
+BFD04C40 3B3C0042 SEH V0, V0\r
+BFD04C42 44933B3C SH T9, 17555(GP)\r
+BFD04C44 4493 AND16 V0, V1\r
+BFD04C46 3B3C0062 SEH V1, V0\r
+BFD04C48 3C5E3B3C SH T9, 15454(GP)\r
+BFD04C4A 00103C5E LH V0, 16(S8)\r
+BFD04C4E 44D3 OR16 V0, V1\r
+BFD04C50 3B3C0042 SEH V0, V0\r
+BFD04C52 385E3B3C SH T9, 14430(GP)\r
+BFD04C54 0010385E SH V0, 16(S8)\r
261: gpio_cfg_tbl[gpio_prop].bit_mask; \r
-BFD04C2E BFD141A2 LUI V0, 0xBFD1
-BFD04C30 FC9EBFD1 LDC1 F30, -866(S1)
-BFD04C32 0024FC9E LW A0, 36(S8)
-BFD04C36 2644 SLL A0, A0, 2
-BFD04C38 92743042 ADDIU V0, V0, -28044
-BFD04C3A 05289274 SLTI S3, S4, 1320
-BFD04C3C 0528 ADDU V0, A0, V0
-BFD04C3E 2920 LHU V0, 0(V0)
+BFD04C2E BFD141A2 LUI V0, 0xBFD1\r
+BFD04C30 FC9EBFD1 LDC1 F30, -866(S1)\r
+BFD04C32 0024FC9E LW A0, 36(S8)\r
+BFD04C36 2644 SLL A0, A0, 2\r
+BFD04C38 92743042 ADDIU V0, V0, -28044\r
+BFD04C3A 05289274 SLTI S3, S4, 1320\r
+BFD04C3C 0528 ADDU V0, A0, V0\r
+BFD04C3E 2920 LHU V0, 0(V0)\r
262: *p = gp_cfg;\r
-BFD04C58 0014FC5E LW V0, 20(S8)
-BFD04C5C 0010347E LHU V1, 16(S8)
-BFD04C60 A9A0 SH V1, 0(V0)
+BFD04C58 0014FC5E LW V0, 20(S8)\r
+BFD04C5C 0010347E LHU V1, 16(S8)\r
+BFD04C60 A9A0 SH V1, 0(V0)\r
263: }\r
264: }\r
-BFD04C62 0FBE MOVE SP, S8
-BFD04C64 4BE7 LW RA, 28(SP)
-BFD04C66 4BC6 LW S8, 24(SP)
-BFD04C68 4C11 ADDIU SP, SP, 32
-BFD04C6A 459F JR16 RA
-BFD04C6C 0C00 NOP
+BFD04C62 0FBE MOVE SP, S8\r
+BFD04C64 4BE7 LW RA, 28(SP)\r
+BFD04C66 4BC6 LW S8, 24(SP)\r
+BFD04C68 4C11 ADDIU SP, SP, 32\r
+BFD04C6A 459F JR16 RA\r
+BFD04C6C 0C00 NOP\r
265: \r
266: \r
267: /**\r
275: */\r
276: uint8_t GPIOGetSlewRate( enum gpio_id_t gpio_id )\r
277: {\r
-BFD09024 4FF1 ADDIU SP, SP, -32
-BFD09026 CBE7 SW RA, 28(SP)
-BFD09028 CBC6 SW S8, 24(SP)
-BFD0902A 0FDD MOVE S8, SP
-BFD0902C 0020F89E SW A0, 32(S8)
+BFD09024 4FF1 ADDIU SP, SP, -32\r
+BFD09026 CBE7 SW RA, 28(SP)\r
+BFD09028 CBC6 SW S8, 24(SP)\r
+BFD0902A 0FDD MOVE S8, SP\r
+BFD0902C 0020F89E SW A0, 32(S8)\r
278: uint32_t addr;\r
279: uint8_t slew;\r
280: \r
281: addr = gpio_has_drv_str(gpio_id);\r
-BFD09030 0020FC9E LW A0, 32(S8)
-BFD09034 332277E8 JALS gpio_has_drv_str
-BFD09036 0C003322 ADDIU T9, V0, 3072
-BFD09038 0C00 NOP
-BFD0903A 0014F85E SW V0, 20(S8)
+BFD09030 0020FC9E LW A0, 32(S8)\r
+BFD09034 332277E8 JALS gpio_has_drv_str\r
+BFD09036 0C003322 ADDIU T9, V0, 3072\r
+BFD09038 0C00 NOP\r
+BFD0903A 0014F85E SW V0, 20(S8)\r
282: if ( 0ul != addr )\r
-BFD0903E 0014FC5E LW V0, 20(S8)
-BFD09042 000940E2 BEQZC V0, 0xBFD09058
+BFD0903E 0014FC5E LW V0, 20(S8)\r
+BFD09042 000940E2 BEQZC V0, 0xBFD09058\r
283: {\r
284: slew = ((*(volatile uint8_t *)addr) >> GPIO_DRV_SLEW_BITPOS) & 0x01u;\r
-BFD09046 0014FC5E LW V0, 20(S8)
-BFD0904A 0920 LBU V0, 0(V0)
-BFD0904C 2D2D ANDI V0, V0, 0xFF
-BFD0904E 2D21 ANDI V0, V0, 0x1
-BFD09050 0010185E SB V0, 16(S8)
-BFD09054 CC03 B 0xBFD0905C
-BFD09056 0C00 NOP
+BFD09046 0014FC5E LW V0, 20(S8)\r
+BFD0904A 0920 LBU V0, 0(V0)\r
+BFD0904C 2D2D ANDI V0, V0, 0xFF\r
+BFD0904E 2D21 ANDI V0, V0, 0x1\r
+BFD09050 0010185E SB V0, 16(S8)\r
+BFD09054 CC03 B 0xBFD0905C\r
+BFD09056 0C00 NOP\r
285: }\r
286: else\r
287: {\r
288: slew = 0u;\r
-BFD09058 0010181E SB ZERO, 16(S8)
+BFD09058 0010181E SB ZERO, 16(S8)\r
289: }\r
290: \r
291: return slew;\r
-BFD0905C 0010145E LBU V0, 16(S8)
+BFD0905C 0010145E LBU V0, 16(S8)\r
292: }\r
-BFD09060 0FBE MOVE SP, S8
-BFD09062 4BE7 LW RA, 28(SP)
-BFD09064 4BC6 LW S8, 24(SP)
-BFD09066 4C11 ADDIU SP, SP, 32
-BFD09068 459F JR16 RA
-BFD0906A 0C00 NOP
+BFD09060 0FBE MOVE SP, S8\r
+BFD09062 4BE7 LW RA, 28(SP)\r
+BFD09064 4BC6 LW S8, 24(SP)\r
+BFD09066 4C11 ADDIU SP, SP, 32\r
+BFD09068 459F JR16 RA\r
+BFD0906A 0C00 NOP\r
293: \r
294: \r
295: /**\r
303: void GPIOSetSlewRate ( enum gpio_id_t gpio_id,\r
304: enum gpio_slew_rate_t slew_rate )\r
305: {\r
-BFD08600 4FF1 ADDIU SP, SP, -32
-BFD08602 CBE7 SW RA, 28(SP)
-BFD08604 CBC6 SW S8, 24(SP)
-BFD08606 0FDD MOVE S8, SP
-BFD08608 0020F89E SW A0, 32(S8)
-BFD0860C 0024F8BE SW A1, 36(S8)
+BFD08600 4FF1 ADDIU SP, SP, -32\r
+BFD08602 CBE7 SW RA, 28(SP)\r
+BFD08604 CBC6 SW S8, 24(SP)\r
+BFD08606 0FDD MOVE S8, SP\r
+BFD08608 0020F89E SW A0, 32(S8)\r
+BFD0860C 0024F8BE SW A1, 36(S8)\r
306: uint32_t addr;\r
307: \r
308: addr = gpio_has_drv_str(gpio_id );\r
-BFD08610 0020FC9E LW A0, 32(S8)
-BFD08614 332277E8 JALS gpio_has_drv_str
-BFD08616 0C003322 ADDIU T9, V0, 3072
-BFD08618 0C00 NOP
-BFD0861A 0010F85E SW V0, 16(S8)
+BFD08610 0020FC9E LW A0, 32(S8)\r
+BFD08614 332277E8 JALS gpio_has_drv_str\r
+BFD08616 0C003322 ADDIU T9, V0, 3072\r
+BFD08618 0C00 NOP\r
+BFD0861A 0010F85E SW V0, 16(S8)\r
309: if ( addr )\r
-BFD0861E 0010FC5E LW V0, 16(S8)
-BFD08622 001240E2 BEQZC V0, 0xBFD0864A
+BFD0861E 0010FC5E LW V0, 16(S8)\r
+BFD08622 001240E2 BEQZC V0, 0xBFD0864A\r
310: {\r
311: *(volatile uint8_t *)addr = (*(volatile uint8_t *)addr & \r
-BFD08626 0010FC5E LW V0, 16(S8)
-BFD0862A 0010FC7E LW V1, 16(S8)
-BFD0862E 09B0 LBU V1, 0(V1)
-BFD08630 2E3D ANDI A0, V1, 0xFF
-BFD08632 FFFE3060 ADDIU V1, ZERO, -2
-BFD08634 449CFFFE LW RA, 17564(S8)
-BFD08636 449C AND16 V1, A0
-BFD08638 2E3D ANDI A0, V1, 0xFF
-BFD0863A 0024FC7E LW V1, 36(S8)
-BFD0863E 2DBD ANDI V1, V1, 0xFF
-BFD08640 2DB1 ANDI V1, V1, 0x1
-BFD08642 2DBD ANDI V1, V1, 0xFF
-BFD08644 44DC OR16 V1, A0
-BFD08646 2DBD ANDI V1, V1, 0xFF
-BFD08648 89A0 SB V1, 0(V0)
+BFD08626 0010FC5E LW V0, 16(S8)\r
+BFD0862A 0010FC7E LW V1, 16(S8)\r
+BFD0862E 09B0 LBU V1, 0(V1)\r
+BFD08630 2E3D ANDI A0, V1, 0xFF\r
+BFD08632 FFFE3060 ADDIU V1, ZERO, -2\r
+BFD08634 449CFFFE LW RA, 17564(S8)\r
+BFD08636 449C AND16 V1, A0\r
+BFD08638 2E3D ANDI A0, V1, 0xFF\r
+BFD0863A 0024FC7E LW V1, 36(S8)\r
+BFD0863E 2DBD ANDI V1, V1, 0xFF\r
+BFD08640 2DB1 ANDI V1, V1, 0x1\r
+BFD08642 2DBD ANDI V1, V1, 0xFF\r
+BFD08644 44DC OR16 V1, A0\r
+BFD08646 2DBD ANDI V1, V1, 0xFF\r
+BFD08648 89A0 SB V1, 0(V0)\r
312: ~(GPIO_DRV_SLEW_MASK)) | \r
313: ((slew_rate << (GPIO_DRV_SLEW_BITPOS)) & (GPIO_DRV_SLEW_MASK));\r
314: }\r
315: }\r
-BFD0864A 0FBE MOVE SP, S8
-BFD0864C 4BE7 LW RA, 28(SP)
-BFD0864E 4BC6 LW S8, 24(SP)
-BFD08650 4C11 ADDIU SP, SP, 32
-BFD08652 459F JR16 RA
-BFD08654 0C00 NOP
+BFD0864A 0FBE MOVE SP, S8\r
+BFD0864C 4BE7 LW RA, 28(SP)\r
+BFD0864E 4BC6 LW S8, 24(SP)\r
+BFD08650 4C11 ADDIU SP, SP, 32\r
+BFD08652 459F JR16 RA\r
+BFD08654 0C00 NOP\r
316: \r
317: \r
318: /**\r
327: */\r
328: uint8_t GPIOGetDriveStr ( enum gpio_id_t gpio_id )\r
329: {\r
-BFD09594 4FF1 ADDIU SP, SP, -32
-BFD09596 CBE7 SW RA, 28(SP)
-BFD09598 CBC6 SW S8, 24(SP)
-BFD0959A 0FDD MOVE S8, SP
-BFD0959C 0020F89E SW A0, 32(S8)
+BFD09594 4FF1 ADDIU SP, SP, -32\r
+BFD09596 CBE7 SW RA, 28(SP)\r
+BFD09598 CBC6 SW S8, 24(SP)\r
+BFD0959A 0FDD MOVE S8, SP\r
+BFD0959C 0020F89E SW A0, 32(S8)\r
330: uint32_t addr;\r
331: \r
332: addr = gpio_has_drv_str(gpio_id );\r
-BFD095A0 0020FC9E LW A0, 32(S8)
-BFD095A4 332277E8 JALS gpio_has_drv_str
-BFD095A6 0C003322 ADDIU T9, V0, 3072
-BFD095A8 0C00 NOP
-BFD095AA 0010F85E SW V0, 16(S8)
+BFD095A0 0020FC9E LW A0, 32(S8)\r
+BFD095A4 332277E8 JALS gpio_has_drv_str\r
+BFD095A6 0C003322 ADDIU T9, V0, 3072\r
+BFD095A8 0C00 NOP\r
+BFD095AA 0010F85E SW V0, 16(S8)\r
333: if ( addr )\r
-BFD095AE 0010FC5E LW V0, 16(S8)
-BFD095B2 000640E2 BEQZC V0, 0xBFD095C2
+BFD095AE 0010FC5E LW V0, 16(S8)\r
+BFD095B2 000640E2 BEQZC V0, 0xBFD095C2\r
334: {\r
335: return ((*(volatile uint8_t *)addr) >> GPIO_DRV_STR_BITPOS) & (GPIO_DRV_STR_MASK);\r
-BFD095B6 0010FC5E LW V0, 16(S8)
-BFD095BA 0920 LBU V0, 0(V0)
-BFD095BC 0C40 MOVE V0, ZERO
-BFD095BE CC02 B 0xBFD095C4
-BFD095C0 0C00 NOP
+BFD095B6 0010FC5E LW V0, 16(S8)\r
+BFD095BA 0920 LBU V0, 0(V0)\r
+BFD095BC 0C40 MOVE V0, ZERO\r
+BFD095BE CC02 B 0xBFD095C4\r
+BFD095C0 0C00 NOP\r
336: }\r
337: else\r
338: {\r
339: return 0u;\r
-BFD095C2 0C40 MOVE V0, ZERO
+BFD095C2 0C40 MOVE V0, ZERO\r
340: }\r
341: }\r
-BFD095C4 0FBE MOVE SP, S8
-BFD095C6 4BE7 LW RA, 28(SP)
-BFD095C8 4BC6 LW S8, 24(SP)
-BFD095CA 4C11 ADDIU SP, SP, 32
-BFD095CC 459F JR16 RA
-BFD095CE 0C00 NOP
+BFD095C4 0FBE MOVE SP, S8\r
+BFD095C6 4BE7 LW RA, 28(SP)\r
+BFD095C8 4BC6 LW S8, 24(SP)\r
+BFD095CA 4C11 ADDIU SP, SP, 32\r
+BFD095CC 459F JR16 RA\r
+BFD095CE 0C00 NOP\r
342: \r
343: \r
344: /**\r
353: void GPIOSetDriveStr ( enum gpio_id_t gpio_id,\r
354: enum gpio_drv_str_t drv_str )\r
355: {\r
-BFD07D64 4FF1 ADDIU SP, SP, -32
-BFD07D66 CBE7 SW RA, 28(SP)
-BFD07D68 CBC6 SW S8, 24(SP)
-BFD07D6A 0FDD MOVE S8, SP
-BFD07D6C 0020F89E SW A0, 32(S8)
-BFD07D70 0024F8BE SW A1, 36(S8)
+BFD07D64 4FF1 ADDIU SP, SP, -32\r
+BFD07D66 CBE7 SW RA, 28(SP)\r
+BFD07D68 CBC6 SW S8, 24(SP)\r
+BFD07D6A 0FDD MOVE S8, SP\r
+BFD07D6C 0020F89E SW A0, 32(S8)\r
+BFD07D70 0024F8BE SW A1, 36(S8)\r
356: uint32_t addr;\r
357: uint8_t r8;\r
358: \r
359: addr = gpio_has_drv_str(gpio_id);\r
-BFD07D74 0020FC9E LW A0, 32(S8)
-BFD07D78 332277E8 JALS gpio_has_drv_str
-BFD07D7A 0C003322 ADDIU T9, V0, 3072
-BFD07D7C 0C00 NOP
-BFD07D7E 0010F85E SW V0, 16(S8)
+BFD07D74 0020FC9E LW A0, 32(S8)\r
+BFD07D78 332277E8 JALS gpio_has_drv_str\r
+BFD07D7A 0C003322 ADDIU T9, V0, 3072\r
+BFD07D7C 0C00 NOP\r
+BFD07D7E 0010F85E SW V0, 16(S8)\r
360: if ( addr )\r
-BFD07D82 0010FC5E LW V0, 16(S8)
-BFD07D86 001B40E2 BEQZC V0, 0xBFD07DC0
+BFD07D82 0010FC5E LW V0, 16(S8)\r
+BFD07D86 001B40E2 BEQZC V0, 0xBFD07DC0\r
361: {\r
362: r8 = *(volatile uint8_t *)addr & ~(GPIO_DRV_STR_MASK);\r
-BFD07D8A 0010FC5E LW V0, 16(S8)
-BFD07D8E 0920 LBU V0, 0(V0)
-BFD07D90 2DAD ANDI V1, V0, 0xFF
-BFD07D92 FFCF3040 ADDIU V0, ZERO, -49
-BFD07D94 4493FFCF LW S8, 17555(T7)
-BFD07D96 4493 AND16 V0, V1
-BFD07D98 0014185E SB V0, 20(S8)
+BFD07D8A 0010FC5E LW V0, 16(S8)\r
+BFD07D8E 0920 LBU V0, 0(V0)\r
+BFD07D90 2DAD ANDI V1, V0, 0xFF\r
+BFD07D92 FFCF3040 ADDIU V0, ZERO, -49\r
+BFD07D94 4493FFCF LW S8, 17555(T7)\r
+BFD07D96 4493 AND16 V0, V1\r
+BFD07D98 0014185E SB V0, 20(S8)\r
363: r8 += ((drv_str << GPIO_DRV_STR_BITPOS) & GPIO_DRV_STR_MASK);\r
-BFD07D9C 0024FC5E LW V0, 36(S8)
-BFD07DA0 2D2D ANDI V0, V0, 0xFF
-BFD07DA2 2528 SLL V0, V0, 4
-BFD07DA4 2D2D ANDI V0, V0, 0xFF
-BFD07DA6 0030D042 ANDI V0, V0, 48
-BFD07DAA 2DAD ANDI V1, V0, 0xFF
-BFD07DAC 0014145E LBU V0, 20(S8)
-BFD07DB0 0526 ADDU V0, V1, V0
-BFD07DB2 0014185E SB V0, 20(S8)
+BFD07D9C 0024FC5E LW V0, 36(S8)\r
+BFD07DA0 2D2D ANDI V0, V0, 0xFF\r
+BFD07DA2 2528 SLL V0, V0, 4\r
+BFD07DA4 2D2D ANDI V0, V0, 0xFF\r
+BFD07DA6 0030D042 ANDI V0, V0, 48\r
+BFD07DAA 2DAD ANDI V1, V0, 0xFF\r
+BFD07DAC 0014145E LBU V0, 20(S8)\r
+BFD07DB0 0526 ADDU V0, V1, V0\r
+BFD07DB2 0014185E SB V0, 20(S8)\r
364: *(volatile uint8_t *)addr = r8;\r
-BFD07DB6 0010FC5E LW V0, 16(S8)
-BFD07DBA 0014147E LBU V1, 20(S8)
-BFD07DBE 89A0 SB V1, 0(V0)
+BFD07DB6 0010FC5E LW V0, 16(S8)\r
+BFD07DBA 0014147E LBU V1, 20(S8)\r
+BFD07DBE 89A0 SB V1, 0(V0)\r
365: }\r
366: }\r
-BFD07DC0 0FBE MOVE SP, S8
-BFD07DC2 4BE7 LW RA, 28(SP)
-BFD07DC4 4BC6 LW S8, 24(SP)
-BFD07DC6 4C11 ADDIU SP, SP, 32
-BFD07DC8 459F JR16 RA
-BFD07DCA 0C00 NOP
+BFD07DC0 0FBE MOVE SP, S8\r
+BFD07DC2 4BE7 LW RA, 28(SP)\r
+BFD07DC4 4BC6 LW S8, 24(SP)\r
+BFD07DC6 4C11 ADDIU SP, SP, 32\r
+BFD07DC8 459F JR16 RA\r
+BFD07DCA 0C00 NOP\r
367: \r
368: \r
369: /**\r
379: */\r
380: uint8_t GPIOGetDriveStrAndSlew ( enum gpio_id_t gpio_id )\r
381: {\r
-BFD095D0 4FF1 ADDIU SP, SP, -32
-BFD095D2 CBE7 SW RA, 28(SP)
-BFD095D4 CBC6 SW S8, 24(SP)
-BFD095D6 0FDD MOVE S8, SP
-BFD095D8 0020F89E SW A0, 32(S8)
+BFD095D0 4FF1 ADDIU SP, SP, -32\r
+BFD095D2 CBE7 SW RA, 28(SP)\r
+BFD095D4 CBC6 SW S8, 24(SP)\r
+BFD095D6 0FDD MOVE S8, SP\r
+BFD095D8 0020F89E SW A0, 32(S8)\r
382: uint32_t addr;\r
383: \r
384: addr = gpio_has_drv_str(gpio_id );\r
-BFD095DC 0020FC9E LW A0, 32(S8)
-BFD095E0 332277E8 JALS gpio_has_drv_str
-BFD095E2 0C003322 ADDIU T9, V0, 3072
-BFD095E4 0C00 NOP
-BFD095E6 0010F85E SW V0, 16(S8)
+BFD095DC 0020FC9E LW A0, 32(S8)\r
+BFD095E0 332277E8 JALS gpio_has_drv_str\r
+BFD095E2 0C003322 ADDIU T9, V0, 3072\r
+BFD095E4 0C00 NOP\r
+BFD095E6 0010F85E SW V0, 16(S8)\r
385: if ( addr )\r
-BFD095EA 0010FC5E LW V0, 16(S8)
-BFD095EE 000640E2 BEQZC V0, 0xBFD095FE
+BFD095EA 0010FC5E LW V0, 16(S8)\r
+BFD095EE 000640E2 BEQZC V0, 0xBFD095FE\r
386: {\r
387: return (*(volatile uint8_t *)addr);\r
-BFD095F2 0010FC5E LW V0, 16(S8)
-BFD095F6 0920 LBU V0, 0(V0)
-BFD095F8 2D2D ANDI V0, V0, 0xFF
-BFD095FA CC02 B 0xBFD09600
-BFD095FC 0C00 NOP
+BFD095F2 0010FC5E LW V0, 16(S8)\r
+BFD095F6 0920 LBU V0, 0(V0)\r
+BFD095F8 2D2D ANDI V0, V0, 0xFF\r
+BFD095FA CC02 B 0xBFD09600\r
+BFD095FC 0C00 NOP\r
388: }\r
389: else\r
390: {\r
391: return 0u;\r
-BFD095FE 0C40 MOVE V0, ZERO
+BFD095FE 0C40 MOVE V0, ZERO\r
392: }\r
393: }\r
-BFD09600 0FBE MOVE SP, S8
-BFD09602 4BE7 LW RA, 28(SP)
-BFD09604 4BC6 LW S8, 24(SP)
-BFD09606 4C11 ADDIU SP, SP, 32
-BFD09608 459F JR16 RA
-BFD0960A 0C00 NOP
+BFD09600 0FBE MOVE SP, S8\r
+BFD09602 4BE7 LW RA, 28(SP)\r
+BFD09604 4BC6 LW S8, 24(SP)\r
+BFD09606 4C11 ADDIU SP, SP, 32\r
+BFD09608 459F JR16 RA\r
+BFD0960A 0C00 NOP\r
394: \r
395: \r
396: /**\r
406: void GPIOSetDriveStrAndSlew ( enum gpio_id_t gpio_id,\r
407: uint8_t drv_and_slew )\r
408: {\r
-BFD0802C 4FF1 ADDIU SP, SP, -32
-BFD0802E CBE7 SW RA, 28(SP)
-BFD08030 CBC6 SW S8, 24(SP)
-BFD08032 0FDD MOVE S8, SP
-BFD08034 0020F89E SW A0, 32(S8)
-BFD08036 0C450020 CMP.LT.PH AT, ZERO
-BFD08038 0C45 MOVE V0, A1
-BFD0803A 0024185E SB V0, 36(S8)
+BFD0802C 4FF1 ADDIU SP, SP, -32\r
+BFD0802E CBE7 SW RA, 28(SP)\r
+BFD08030 CBC6 SW S8, 24(SP)\r
+BFD08032 0FDD MOVE S8, SP\r
+BFD08034 0020F89E SW A0, 32(S8)\r
+BFD08036 0C450020 CMP.LT.PH AT, ZERO\r
+BFD08038 0C45 MOVE V0, A1\r
+BFD0803A 0024185E SB V0, 36(S8)\r
409: uint32_t addr;\r
410: uint8_t r8;\r
411: \r
412: addr = gpio_has_drv_str(gpio_id);\r
-BFD0803E 0020FC9E LW A0, 32(S8)
-BFD08042 332277E8 JALS gpio_has_drv_str
-BFD08044 0C003322 ADDIU T9, V0, 3072
-BFD08046 0C00 NOP
-BFD08048 0010F85E SW V0, 16(S8)
+BFD0803E 0020FC9E LW A0, 32(S8)\r
+BFD08042 332277E8 JALS gpio_has_drv_str\r
+BFD08044 0C003322 ADDIU T9, V0, 3072\r
+BFD08046 0C00 NOP\r
+BFD08048 0010F85E SW V0, 16(S8)\r
413: if ( addr )\r
-BFD0804C 0010FC5E LW V0, 16(S8)
-BFD08050 001840E2 BEQZC V0, 0xBFD08084
+BFD0804C 0010FC5E LW V0, 16(S8)\r
+BFD08050 001840E2 BEQZC V0, 0xBFD08084\r
414: {\r
415: r8 = *(volatile uint8_t *)addr & ~(GPIO_DRV_SLEW_MASK + GPIO_DRV_STR_MASK);\r
-BFD08054 0010FC5E LW V0, 16(S8)
-BFD08058 0920 LBU V0, 0(V0)
-BFD0805A 2DAD ANDI V1, V0, 0xFF
-BFD0805C FFCE3040 ADDIU V0, ZERO, -50
-BFD0805E 4493FFCE LW S8, 17555(T6)
-BFD08060 4493 AND16 V0, V1
-BFD08062 0014185E SB V0, 20(S8)
+BFD08054 0010FC5E LW V0, 16(S8)\r
+BFD08058 0920 LBU V0, 0(V0)\r
+BFD0805A 2DAD ANDI V1, V0, 0xFF\r
+BFD0805C FFCE3040 ADDIU V0, ZERO, -50\r
+BFD0805E 4493FFCE LW S8, 17555(T6)\r
+BFD08060 4493 AND16 V0, V1\r
+BFD08062 0014185E SB V0, 20(S8)\r
416: r8 |= (drv_and_slew & (GPIO_DRV_SLEW_MASK + GPIO_DRV_STR_MASK));\r
-BFD08066 0024145E LBU V0, 36(S8)
-BFD0806A 0031D042 ANDI V0, V0, 49
-BFD0806E 2DAD ANDI V1, V0, 0xFF
-BFD08070 0014145E LBU V0, 20(S8)
-BFD08074 44D3 OR16 V0, V1
-BFD08076 0014185E SB V0, 20(S8)
+BFD08066 0024145E LBU V0, 36(S8)\r
+BFD0806A 0031D042 ANDI V0, V0, 49\r
+BFD0806E 2DAD ANDI V1, V0, 0xFF\r
+BFD08070 0014145E LBU V0, 20(S8)\r
+BFD08074 44D3 OR16 V0, V1\r
+BFD08076 0014185E SB V0, 20(S8)\r
417: *(volatile uint8_t *)addr = r8;\r
-BFD0807A 0010FC5E LW V0, 16(S8)
-BFD0807E 0014147E LBU V1, 20(S8)
-BFD08082 89A0 SB V1, 0(V0)
+BFD0807A 0010FC5E LW V0, 16(S8)\r
+BFD0807E 0014147E LBU V1, 20(S8)\r
+BFD08082 89A0 SB V1, 0(V0)\r
418: }\r
419: }\r
-BFD08084 0FBE MOVE SP, S8
-BFD08086 4BE7 LW RA, 28(SP)
-BFD08088 4BC6 LW S8, 24(SP)
-BFD0808A 4C11 ADDIU SP, SP, 32
-BFD0808C 459F JR16 RA
-BFD0808E 0C00 NOP
+BFD08084 0FBE MOVE SP, S8\r
+BFD08086 4BE7 LW RA, 28(SP)\r
+BFD08088 4BC6 LW S8, 24(SP)\r
+BFD0808A 4C11 ADDIU SP, SP, 32\r
+BFD0808C 459F JR16 RA\r
+BFD0808E 0C00 NOP\r
420: \r
421: \r
422: /**\r
437: uint8_t gpio_state\r
438: )\r
439: {\r
-BFD08658 4FF1 ADDIU SP, SP, -32
-BFD0865A CBE7 SW RA, 28(SP)
-BFD0865C CBC6 SW S8, 24(SP)
-BFD0865E 0FDD MOVE S8, SP
-BFD08660 0020F89E SW A0, 32(S8)
-BFD08662 0C450020 CMP.LT.PH AT, ZERO
-BFD08664 0C45 MOVE V0, A1
-BFD08666 0024185E SB V0, 36(S8)
+BFD08658 4FF1 ADDIU SP, SP, -32\r
+BFD0865A CBE7 SW RA, 28(SP)\r
+BFD0865C CBC6 SW S8, 24(SP)\r
+BFD0865E 0FDD MOVE S8, SP\r
+BFD08660 0020F89E SW A0, 32(S8)\r
+BFD08662 0C450020 CMP.LT.PH AT, ZERO\r
+BFD08664 0C45 MOVE V0, A1\r
+BFD08666 0024185E SB V0, 36(S8)\r
440: volatile uint8_t * p;\r
441: \r
442: if ( gpio_is_valid(gpio_id) )\r
-BFD0866A 0020FC9E LW A0, 32(S8)
-BFD0866E 40DA77E8 JALS gpio_is_valid
-BFD08670 0C0040DA BGTZ K0, 0xBFD09E74
-BFD08672 0C00 NOP
-BFD08674 001540E2 BEQZC V0, 0xBFD086A2
+BFD0866A 0020FC9E LW A0, 32(S8)\r
+BFD0866E 40DA77E8 JALS gpio_is_valid\r
+BFD08670 0C0040DA BGTZ K0, 0xBFD09E74\r
+BFD08672 0C00 NOP\r
+BFD08674 001540E2 BEQZC V0, 0xBFD086A2\r
443: {\r
444: p = (volatile uint8_t *)(gpio_pin_ctrl_addr(gpio_id) + 2ul);\r
-BFD08678 0020FC9E LW A0, 32(S8)
-BFD0867C 4D9477E8 JALS gpio_pin_ctrl_addr
-BFD0867E 4D94 ADDIU T4, T4, -6
-BFD08680 0C00 NOP
-BFD08682 4C44 ADDIU V0, V0, 2
-BFD08684 0010F85E SW V0, 16(S8)
+BFD08678 0020FC9E LW A0, 32(S8)\r
+BFD0867C 4D9477E8 JALS gpio_pin_ctrl_addr\r
+BFD0867E 4D94 ADDIU T4, T4, -6\r
+BFD08680 0C00 NOP\r
+BFD08682 4C44 ADDIU V0, V0, 2\r
+BFD08684 0010F85E SW V0, 16(S8)\r
445: if (gpio_state) {\r
-BFD08688 0024145E LBU V0, 36(S8)
-BFD0868C 000640E2 BEQZC V0, 0xBFD0869C
+BFD08688 0024145E LBU V0, 36(S8)\r
+BFD0868C 000640E2 BEQZC V0, 0xBFD0869C\r
446: *p = 0x01u;\r
-BFD08690 0010FC5E LW V0, 16(S8)
-BFD08694 ED81 LI V1, 1
-BFD08696 89A0 SB V1, 0(V0)
-BFD08698 CC04 B 0xBFD086A2
-BFD0869A 0C00 NOP
+BFD08690 0010FC5E LW V0, 16(S8)\r
+BFD08694 ED81 LI V1, 1\r
+BFD08696 89A0 SB V1, 0(V0)\r
+BFD08698 CC04 B 0xBFD086A2\r
+BFD0869A 0C00 NOP\r
447: } else {\r
448: *p = 0u;\r
-BFD0869C 0010FC5E LW V0, 16(S8)
-BFD086A0 8820 SB S0, 0(V0)
+BFD0869C 0010FC5E LW V0, 16(S8)\r
+BFD086A0 8820 SB S0, 0(V0)\r
449: }\r
450: }\r
451: }\r
-BFD086A2 0FBE MOVE SP, S8
-BFD086A4 4BE7 LW RA, 28(SP)
-BFD086A6 4BC6 LW S8, 24(SP)
-BFD086A8 4C11 ADDIU SP, SP, 32
-BFD086AA 459F JR16 RA
-BFD086AC 0C00 NOP
+BFD086A2 0FBE MOVE SP, S8\r
+BFD086A4 4BE7 LW RA, 28(SP)\r
+BFD086A6 4BC6 LW S8, 24(SP)\r
+BFD086A8 4C11 ADDIU SP, SP, 32\r
+BFD086AA 459F JR16 RA\r
+BFD086AC 0C00 NOP\r
452: \r
453: \r
454: void GPIOToggleOutput ( enum gpio_id_t gpio_id )\r
455: {\r
-BFD08C5C 4FF1 ADDIU SP, SP, -32
-BFD08C5E CBE7 SW RA, 28(SP)
-BFD08C60 CBC6 SW S8, 24(SP)
-BFD08C62 0FDD MOVE S8, SP
-BFD08C64 0020F89E SW A0, 32(S8)
+BFD08C5C 4FF1 ADDIU SP, SP, -32\r
+BFD08C5E CBE7 SW RA, 28(SP)\r
+BFD08C60 CBC6 SW S8, 24(SP)\r
+BFD08C62 0FDD MOVE S8, SP\r
+BFD08C64 0020F89E SW A0, 32(S8)\r
456: volatile uint8_t * p;\r
457: \r
458: if ( gpio_is_valid(gpio_id) )\r
-BFD08C68 0020FC9E LW A0, 32(S8)
-BFD08C6C 40DA77E8 JALS gpio_is_valid
-BFD08C6E 0C0040DA BGTZ K0, 0xBFD0A472
-BFD08C70 0C00 NOP
-BFD08C72 001240E2 BEQZC V0, 0xBFD08C9A
+BFD08C68 0020FC9E LW A0, 32(S8)\r
+BFD08C6C 40DA77E8 JALS gpio_is_valid\r
+BFD08C6E 0C0040DA BGTZ K0, 0xBFD0A472\r
+BFD08C70 0C00 NOP\r
+BFD08C72 001240E2 BEQZC V0, 0xBFD08C9A\r
459: {\r
460: p = (volatile uint8_t *)(gpio_pin_ctrl_addr(gpio_id) + 2ul);\r
-BFD08C76 0020FC9E LW A0, 32(S8)
-BFD08C7A 4D9477E8 JALS gpio_pin_ctrl_addr
-BFD08C7C 4D94 ADDIU T4, T4, -6
-BFD08C7E 0C00 NOP
-BFD08C80 4C44 ADDIU V0, V0, 2
-BFD08C82 0010F85E SW V0, 16(S8)
+BFD08C76 0020FC9E LW A0, 32(S8)\r
+BFD08C7A 4D9477E8 JALS gpio_pin_ctrl_addr\r
+BFD08C7C 4D94 ADDIU T4, T4, -6\r
+BFD08C7E 0C00 NOP\r
+BFD08C80 4C44 ADDIU V0, V0, 2\r
+BFD08C82 0010F85E SW V0, 16(S8)\r
461: *p ^= 0x01u;\r
-BFD08C86 0010FC5E LW V0, 16(S8)
-BFD08C8A 0920 LBU V0, 0(V0)
-BFD08C8C 2D2D ANDI V0, V0, 0xFF
-BFD08C8E 00017042 XORI V0, V0, 1
-BFD08C92 2DAD ANDI V1, V0, 0xFF
-BFD08C94 0010FC5E LW V0, 16(S8)
-BFD08C98 89A0 SB V1, 0(V0)
+BFD08C86 0010FC5E LW V0, 16(S8)\r
+BFD08C8A 0920 LBU V0, 0(V0)\r
+BFD08C8C 2D2D ANDI V0, V0, 0xFF\r
+BFD08C8E 00017042 XORI V0, V0, 1\r
+BFD08C92 2DAD ANDI V1, V0, 0xFF\r
+BFD08C94 0010FC5E LW V0, 16(S8)\r
+BFD08C98 89A0 SB V1, 0(V0)\r
462: }\r
463: }\r
-BFD08C9A 0FBE MOVE SP, S8
-BFD08C9C 4BE7 LW RA, 28(SP)
-BFD08C9E 4BC6 LW S8, 24(SP)
-BFD08CA0 4C11 ADDIU SP, SP, 32
-BFD08CA2 459F JR16 RA
-BFD08CA4 0C00 NOP
+BFD08C9A 0FBE MOVE SP, S8\r
+BFD08C9C 4BE7 LW RA, 28(SP)\r
+BFD08C9E 4BC6 LW S8, 24(SP)\r
+BFD08CA0 4C11 ADDIU SP, SP, 32\r
+BFD08CA2 459F JR16 RA\r
+BFD08CA4 0C00 NOP\r
464: \r
465: \r
466: /**\r
478: */\r
479: uint8_t GPIOReadPin( enum gpio_id_t gpio_id )\r
480: {\r
-BFD0960C 4FF5 ADDIU SP, SP, -24
-BFD0960E CBE5 SW RA, 20(SP)
-BFD09610 CBC4 SW S8, 16(SP)
-BFD09612 0FDD MOVE S8, SP
-BFD09614 0018F89E SW A0, 24(S8)
+BFD0960C 4FF5 ADDIU SP, SP, -24\r
+BFD0960E CBE5 SW RA, 20(SP)\r
+BFD09610 CBC4 SW S8, 16(SP)\r
+BFD09612 0FDD MOVE S8, SP\r
+BFD09614 0018F89E SW A0, 24(S8)\r
481: if ( gpio_is_valid(gpio_id) )\r
-BFD09618 0018FC9E LW A0, 24(S8)
-BFD0961C 40DA77E8 JALS gpio_is_valid
-BFD0961E 0C0040DA BGTZ K0, 0xBFD0AE22
-BFD09620 0C00 NOP
-BFD09622 000A40E2 BEQZC V0, 0xBFD0963A
+BFD09618 0018FC9E LW A0, 24(S8)\r
+BFD0961C 40DA77E8 JALS gpio_is_valid\r
+BFD0961E 0C0040DA BGTZ K0, 0xBFD0AE22\r
+BFD09620 0C00 NOP\r
+BFD09622 000A40E2 BEQZC V0, 0xBFD0963A\r
482: {\r
483: return *((volatile uint8_t *)(gpio_pin_ctrl_addr(gpio_id) + 3ul));\r
-BFD09626 0018FC9E LW A0, 24(S8)
-BFD0962A 4D9477E8 JALS gpio_pin_ctrl_addr
-BFD0962C 4D94 ADDIU T4, T4, -6
-BFD0962E 0C00 NOP
-BFD09630 4C46 ADDIU V0, V0, 3
-BFD09632 0920 LBU V0, 0(V0)
-BFD09634 2D2D ANDI V0, V0, 0xFF
-BFD09636 CC02 B 0xBFD0963C
-BFD09638 0C00 NOP
+BFD09626 0018FC9E LW A0, 24(S8)\r
+BFD0962A 4D9477E8 JALS gpio_pin_ctrl_addr\r
+BFD0962C 4D94 ADDIU T4, T4, -6\r
+BFD0962E 0C00 NOP\r
+BFD09630 4C46 ADDIU V0, V0, 3\r
+BFD09632 0920 LBU V0, 0(V0)\r
+BFD09634 2D2D ANDI V0, V0, 0xFF\r
+BFD09636 CC02 B 0xBFD0963C\r
+BFD09638 0C00 NOP\r
484: } \r
485: else \r
486: {\r
487: return 0u;\r
-BFD0963A 0C40 MOVE V0, ZERO
+BFD0963A 0C40 MOVE V0, ZERO\r
488: }\r
489: }\r
-BFD0963C 0FBE MOVE SP, S8
-BFD0963E 4BE5 LW RA, 20(SP)
-BFD09640 4BC4 LW S8, 16(SP)
-BFD09642 4C0D ADDIU SP, SP, 24
-BFD09644 459F JR16 RA
-BFD09646 0C00 NOP
+BFD0963C 0FBE MOVE SP, S8\r
+BFD0963E 4BE5 LW RA, 20(SP)\r
+BFD09640 4BC4 LW S8, 16(SP)\r
+BFD09642 4C0D ADDIU SP, SP, 24\r
+BFD09644 459F JR16 RA\r
+BFD09646 0C00 NOP\r
490: \r
491: \r
492: /** GPIOPinLock - Lock specified GPIO's control register.\r
497: * */ \r
498: void GPIOPinLock(enum gpio_id_t gpio_id)\r
499: {\r
-BFD07ADC 4FF1 ADDIU SP, SP, -32
-BFD07ADE CBE7 SW RA, 28(SP)
-BFD07AE0 CBC6 SW S8, 24(SP)
-BFD07AE2 0FDD MOVE S8, SP
-BFD07AE4 0020F89E SW A0, 32(S8)
+BFD07ADC 4FF1 ADDIU SP, SP, -32\r
+BFD07ADE CBE7 SW RA, 28(SP)\r
+BFD07AE0 CBC6 SW S8, 24(SP)\r
+BFD07AE2 0FDD MOVE S8, SP\r
+BFD07AE4 0020F89E SW A0, 32(S8)\r
500: uint32_t addr;\r
501: uint8_t bank, bitpos;\r
502: \r
503: if (gpio_is_valid(gpio_id)) {\r
-BFD07AE8 0020FC9E LW A0, 32(S8)
-BFD07AEC 40DA77E8 JALS gpio_is_valid
-BFD07AEE 0C0040DA BGTZ K0, 0xBFD092F2
-BFD07AF0 0C00 NOP
-BFD07AF2 002440E2 BEQZC V0, 0xBFD07B3E
+BFD07AE8 0020FC9E LW A0, 32(S8)\r
+BFD07AEC 40DA77E8 JALS gpio_is_valid\r
+BFD07AEE 0C0040DA BGTZ K0, 0xBFD092F2\r
+BFD07AF0 0C00 NOP\r
+BFD07AF2 002440E2 BEQZC V0, 0xBFD07B3E\r
504: bank = gpio_bank_num(gpio_id); // 0 - 4\r
-BFD07AF6 0020FC9E LW A0, 32(S8)
-BFD07AFA 4E9677E8 JALS gpio_bank_num
-BFD07AFC 4E96 ADDIU S4, S4, -5
-BFD07AFE 0C00 NOP
-BFD07B00 0010185E SB V0, 16(S8)
+BFD07AF6 0020FC9E LW A0, 32(S8)\r
+BFD07AFA 4E9677E8 JALS gpio_bank_num\r
+BFD07AFC 4E96 ADDIU S4, S4, -5\r
+BFD07AFE 0C00 NOP\r
+BFD07B00 0010185E SB V0, 16(S8)\r
505: bitpos = gpio_pin_num(gpio_id); // 0 - 31\r
-BFD07B04 0020FC9E LW A0, 32(S8)
-BFD07B08 4EA677E8 JALS gpio_pin_num
-BFD07B0A 4EA6 ADDIU S5, S5, 3
-BFD07B0C 0C00 NOP
-BFD07B0E 0011185E SB V0, 17(S8)
+BFD07B04 0020FC9E LW A0, 32(S8)\r
+BFD07B08 4EA677E8 JALS gpio_pin_num\r
+BFD07B0A 4EA6 ADDIU S5, S5, 3\r
+BFD07B0C 0C00 NOP\r
+BFD07B0E 0011185E SB V0, 17(S8)\r
506: addr = (uint32_t)(GPIO_LOCK_BASE) - (bank << 2);\r
-BFD07B12 0010145E LBU V0, 16(S8)
-BFD07B16 2524 SLL V0, V0, 2
-BFD07B18 A00841A3 LUI V1, 0xA008
-BFD07B1C 13F05063 ORI V1, V1, 5104
-BFD07B1E 052713F0 ADDI RA, S0, 1319
-BFD07B20 0527 SUBU V0, V1, V0
-BFD07B22 0014F85E SW V0, 20(S8)
+BFD07B12 0010145E LBU V0, 16(S8)\r
+BFD07B16 2524 SLL V0, V0, 2\r
+BFD07B18 A00841A3 LUI V1, 0xA008\r
+BFD07B1C 13F05063 ORI V1, V1, 5104\r
+BFD07B1E 052713F0 ADDI RA, S0, 1319\r
+BFD07B20 0527 SUBU V0, V1, V0\r
+BFD07B22 0014F85E SW V0, 20(S8)\r
507: *(volatile uint32_t *)addr |= (1ul << bitpos);\r
-BFD07B26 0014FC5E LW V0, 20(S8)
-BFD07B2A 0014FC7E LW V1, 20(S8)
-BFD07B2E 6A30 LW A0, 0(V1)
-BFD07B30 0011147E LBU V1, 17(S8)
-BFD07B34 EE81 LI A1, 1
-BFD07B36 181000A3 SLLV V1, V1, A1
-BFD07B38 44DC1810 SB ZERO, 17628(S0)
-BFD07B3A 44DC OR16 V1, A0
-BFD07B3C E9A0 SW V1, 0(V0)
+BFD07B26 0014FC5E LW V0, 20(S8)\r
+BFD07B2A 0014FC7E LW V1, 20(S8)\r
+BFD07B2E 6A30 LW A0, 0(V1)\r
+BFD07B30 0011147E LBU V1, 17(S8)\r
+BFD07B34 EE81 LI A1, 1\r
+BFD07B36 181000A3 SLLV V1, V1, A1\r
+BFD07B38 44DC1810 SB ZERO, 17628(S0)\r
+BFD07B3A 44DC OR16 V1, A0\r
+BFD07B3C E9A0 SW V1, 0(V0)\r
508: } \r
509: }\r
-BFD07B3E 0FBE MOVE SP, S8
-BFD07B40 4BE7 LW RA, 28(SP)
-BFD07B42 4BC6 LW S8, 24(SP)
-BFD07B44 4C11 ADDIU SP, SP, 32
-BFD07B46 459F JR16 RA
-BFD07B48 0C00 NOP
+BFD07B3E 0FBE MOVE SP, S8\r
+BFD07B40 4BE7 LW RA, 28(SP)\r
+BFD07B42 4BC6 LW S8, 24(SP)\r
+BFD07B44 4C11 ADDIU SP, SP, 32\r
+BFD07B46 459F JR16 RA\r
+BFD07B48 0C00 NOP\r
510: \r
511: \r
512: /* end mec14xx_gpio.c */\r
513: /** @}\r
514: */\r
515: \r
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/mec14xx_bbled.c --------
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/mec14xx_bbled.c --------\r
1: /*****************************************************************************\r
2: * Copyright 2014 Microchip Technology Inc. and its subsidiaries.\r
3: * You may use this software and any derivatives exclusively with\r
39: \r
40: static uint32_t led_addr(uint8_t led_id) \r
41: {\r
-BFD09420 4FB0 ADDIU SP, SP, -8
-BFD09422 CBC1 SW S8, 4(SP)
-BFD09424 0FDD MOVE S8, SP
-BFD09426 0C44 MOVE V0, A0
-BFD09428 0008185E SB V0, 8(S8)
+BFD09420 4FB0 ADDIU SP, SP, -8\r
+BFD09422 CBC1 SW S8, 4(SP)\r
+BFD09424 0FDD MOVE S8, SP\r
+BFD09426 0C44 MOVE V0, A0\r
+BFD09428 0008185E SB V0, 8(S8)\r
42: if (led_id < (LED_ID_MAX) )\r
-BFD0942C 0008145E LBU V0, 8(S8)
-BFD09430 0003B042 SLTIU V0, V0, 3
-BFD09434 000B40E2 BEQZC V0, 0xBFD0944E
+BFD0942C 0008145E LBU V0, 8(S8)\r
+BFD09430 0003B042 SLTIU V0, V0, 3\r
+BFD09434 000B40E2 BEQZC V0, 0xBFD0944E\r
43: {\r
44: return ((LED0_BASE) + (led_id << 8));\r
-BFD09438 0008145E LBU V0, 8(S8)
-BFD0943C 2520 SLL V0, V0, 8
-BFD0943E 0C62 MOVE V1, V0
-BFD09440 A00041A2 LUI V0, 0xA000
-BFD09444 B8005042 ORI V0, V0, -18432
-BFD09446 0526B800 SDC1 F0, 1318(ZERO)
-BFD09448 0526 ADDU V0, V1, V0
-BFD0944A CC05 B 0xBFD09456
-BFD0944C 0C00 NOP
+BFD09438 0008145E LBU V0, 8(S8)\r
+BFD0943C 2520 SLL V0, V0, 8\r
+BFD0943E 0C62 MOVE V1, V0\r
+BFD09440 A00041A2 LUI V0, 0xA000\r
+BFD09444 B8005042 ORI V0, V0, -18432\r
+BFD09446 0526B800 SDC1 F0, 1318(ZERO)\r
+BFD09448 0526 ADDU V0, V1, V0\r
+BFD0944A CC05 B 0xBFD09456\r
+BFD0944C 0C00 NOP\r
45: }\r
46: else\r
47: {\r
48: return (LED0_BASE);\r
-BFD0944E A00041A2 LUI V0, 0xA000
-BFD09452 B8005042 ORI V0, V0, -18432
-BFD09454 0FBEB800 SDC1 F0, 4030(ZERO)
+BFD0944E A00041A2 LUI V0, 0xA000\r
+BFD09452 B8005042 ORI V0, V0, -18432\r
+BFD09454 0FBEB800 SDC1 F0, 4030(ZERO)\r
49: }\r
50: }\r
-BFD09456 0FBE MOVE SP, S8
-BFD09458 4BC1 LW S8, 4(SP)
-BFD0945A 4C05 ADDIU SP, SP, 8
-BFD0945C 459F JR16 RA
-BFD0945E 0C00 NOP
+BFD09456 0FBE MOVE SP, S8\r
+BFD09458 4BC1 LW S8, 4(SP)\r
+BFD0945A 4C05 ADDIU SP, SP, 8\r
+BFD0945C 459F JR16 RA\r
+BFD0945E 0C00 NOP\r
51: \r
52: #ifdef LED_ENABLE_VALID_CHECK\r
53: \r
62: #else\r
63: \r
64: static uint8_t led_is_valid(uint8_t led_id) { ( void ) led_id; return (MEC14XX_TRUE); }\r
-BFD09E6C 4FB0 ADDIU SP, SP, -8
-BFD09E6E CBC1 SW S8, 4(SP)
-BFD09E70 0FDD MOVE S8, SP
-BFD09E72 0C44 MOVE V0, A0
-BFD09E74 0008185E SB V0, 8(S8)
-BFD09E78 ED01 LI V0, 1
-BFD09E7A 0FBE MOVE SP, S8
-BFD09E7C 4BC1 LW S8, 4(SP)
-BFD09E7E 4C05 ADDIU SP, SP, 8
-BFD09E80 459F JR16 RA
-BFD09E82 0C00 NOP
+BFD09E6C 4FB0 ADDIU SP, SP, -8\r
+BFD09E6E CBC1 SW S8, 4(SP)\r
+BFD09E70 0FDD MOVE S8, SP\r
+BFD09E72 0C44 MOVE V0, A0\r
+BFD09E74 0008185E SB V0, 8(S8)\r
+BFD09E78 ED01 LI V0, 1\r
+BFD09E7A 0FBE MOVE SP, S8\r
+BFD09E7C 4BC1 LW S8, 4(SP)\r
+BFD09E7E 4C05 ADDIU SP, SP, 8\r
+BFD09E80 459F JR16 RA\r
+BFD09E82 0C00 NOP\r
65: \r
66: #endif\r
67: \r
101: */\r
102: void led_sleep_en(uint8_t led_id, uint8_t sleep_en)\r
103: {\r
-BFD05D0C 4FF1 ADDIU SP, SP, -32
-BFD05D0E CBE7 SW RA, 28(SP)
-BFD05D10 CBC6 SW S8, 24(SP)
-BFD05D12 0FDD MOVE S8, SP
-BFD05D14 0C64 MOVE V1, A0
-BFD05D16 0C45 MOVE V0, A1
-BFD05D18 0020187E SB V1, 32(S8)
-BFD05D1C 0024185E SB V0, 36(S8)
+BFD05D0C 4FF1 ADDIU SP, SP, -32\r
+BFD05D0E CBE7 SW RA, 28(SP)\r
+BFD05D10 CBC6 SW S8, 24(SP)\r
+BFD05D12 0FDD MOVE S8, SP\r
+BFD05D14 0C64 MOVE V1, A0\r
+BFD05D16 0C45 MOVE V0, A1\r
+BFD05D18 0020187E SB V1, 32(S8)\r
+BFD05D1C 0024185E SB V0, 36(S8)\r
104: uint32_t slp_mask;\r
105: uint32_t laddr;\r
106: \r
107: slp_mask = 0ul;\r
-BFD05D20 0010F81E SW ZERO, 16(S8)
+BFD05D20 0010F81E SW ZERO, 16(S8)\r
108: if ( led_is_valid(led_id) ) {\r
-BFD05D24 0020145E LBU V0, 32(S8)
-BFD05D28 0C82 MOVE A0, V0
-BFD05D2A 4F3677E8 JALS led_is_valid
-BFD05D2C 4F36 ADDIU T9, T9, -5
-BFD05D2E 0C00 NOP
-BFD05D30 003F40E2 BEQZC V0, 0xBFD05DB2
+BFD05D24 0020145E LBU V0, 32(S8)\r
+BFD05D28 0C82 MOVE A0, V0\r
+BFD05D2A 4F3677E8 JALS led_is_valid\r
+BFD05D2C 4F36 ADDIU T9, T9, -5\r
+BFD05D2E 0C00 NOP\r
+BFD05D30 003F40E2 BEQZC V0, 0xBFD05DB2\r
109: slp_mask = (1ul << led_pcr_slp2_bitpos[led_id]);\r
-BFD05D34 0020147E LBU V1, 32(S8)
-BFD05D38 BFD041A2 LUI V0, 0xBFD0
-BFD05D3A 3042BFD0 LDC1 F30, 12354(S0)
-BFD05D3C 01743042 ADDIU V0, V0, 372
-BFD05D40 0526 ADDU V0, V1, V0
-BFD05D42 0920 LBU V0, 0(V0)
-BFD05D44 ED81 LI V1, 1
-BFD05D46 10100062 SLLV V0, V0, V1
-BFD05D48 F85E1010 ADDI ZERO, S0, -1954
-BFD05D4A 0010F85E SW V0, 16(S8)
+BFD05D34 0020147E LBU V1, 32(S8)\r
+BFD05D38 BFD041A2 LUI V0, 0xBFD0\r
+BFD05D3A 3042BFD0 LDC1 F30, 12354(S0)\r
+BFD05D3C 01743042 ADDIU V0, V0, 372\r
+BFD05D40 0526 ADDU V0, V1, V0\r
+BFD05D42 0920 LBU V0, 0(V0)\r
+BFD05D44 ED81 LI V1, 1\r
+BFD05D46 10100062 SLLV V0, V0, V1\r
+BFD05D48 F85E1010 ADDI ZERO, S0, -1954\r
+BFD05D4A 0010F85E SW V0, 16(S8)\r
110: if ( sleep_en ) {\r
-BFD05D4E 0024145E LBU V0, 36(S8)
-BFD05D52 002040E2 BEQZC V0, 0xBFD05D96
+BFD05D4E 0024145E LBU V0, 36(S8)\r
+BFD05D52 002040E2 BEQZC V0, 0xBFD05D96\r
111: PCR->EC_SLEEP_EN2 |= slp_mask;\r
-BFD05D56 A00841A2 LUI V0, 0xA008
-BFD05D5A 01005042 ORI V0, V0, 256
-BFD05D5E A00841A3 LUI V1, 0xA008
-BFD05D62 01005063 ORI V1, V1, 256
-BFD05D66 6A39 LW A0, 36(V1)
-BFD05D68 0010FC7E LW V1, 16(S8)
-BFD05D6C 44DC OR16 V1, A0
-BFD05D6E E9A9 SW V1, 36(V0)
+BFD05D56 A00841A2 LUI V0, 0xA008\r
+BFD05D5A 01005042 ORI V0, V0, 256\r
+BFD05D5E A00841A3 LUI V1, 0xA008\r
+BFD05D62 01005063 ORI V1, V1, 256\r
+BFD05D66 6A39 LW A0, 36(V1)\r
+BFD05D68 0010FC7E LW V1, 16(S8)\r
+BFD05D6C 44DC OR16 V1, A0\r
+BFD05D6E E9A9 SW V1, 36(V0)\r
112: laddr = led_addr(led_id);\r
-BFD05D70 0020145E LBU V0, 32(S8)
-BFD05D74 0C82 MOVE A0, V0
-BFD05D76 4A1077E8 JALS led_addr
-BFD05D78 4A10 LW S0, 64(SP)
-BFD05D7A 0C00 NOP
-BFD05D7C 0014F85E SW V0, 20(S8)
+BFD05D70 0020145E LBU V0, 32(S8)\r
+BFD05D74 0C82 MOVE A0, V0\r
+BFD05D76 4A1077E8 JALS led_addr\r
+BFD05D78 4A10 LW S0, 64(SP)\r
+BFD05D7A 0C00 NOP\r
+BFD05D7C 0014F85E SW V0, 20(S8)\r
113: ((BBLED_TypeDef *)laddr)->CONFIG &= ~(0x03ul);\r
-BFD05D80 0014FC5E LW V0, 20(S8)
-BFD05D84 0014FC7E LW V1, 20(S8)
-BFD05D88 6A30 LW A0, 0(V1)
-BFD05D8A FFFC3060 ADDIU V1, ZERO, -4
-BFD05D8C 449CFFFC LW RA, 17564(GP)
-BFD05D8E 449C AND16 V1, A0
-BFD05D90 E9A0 SW V1, 0(V0)
-BFD05D92 CC0F B 0xBFD05DB2
-BFD05D94 0C00 NOP
+BFD05D80 0014FC5E LW V0, 20(S8)\r
+BFD05D84 0014FC7E LW V1, 20(S8)\r
+BFD05D88 6A30 LW A0, 0(V1)\r
+BFD05D8A FFFC3060 ADDIU V1, ZERO, -4\r
+BFD05D8C 449CFFFC LW RA, 17564(GP)\r
+BFD05D8E 449C AND16 V1, A0\r
+BFD05D90 E9A0 SW V1, 0(V0)\r
+BFD05D92 CC0F B 0xBFD05DB2\r
+BFD05D94 0C00 NOP\r
114: } else {\r
115: PCR->EC_SLEEP_EN2 &= ~(slp_mask);\r
-BFD05D96 A00841A2 LUI V0, 0xA008
-BFD05D9A 01005042 ORI V0, V0, 256
-BFD05D9E A00841A3 LUI V1, 0xA008
-BFD05DA2 01005063 ORI V1, V1, 256
-BFD05DA6 6A39 LW A0, 36(V1)
-BFD05DA8 0010FC7E LW V1, 16(S8)
-BFD05DAC 441B NOT16 V1, V1
-BFD05DAE 449C AND16 V1, A0
-BFD05DB0 E9A9 SW V1, 36(V0)
+BFD05D96 A00841A2 LUI V0, 0xA008\r
+BFD05D9A 01005042 ORI V0, V0, 256\r
+BFD05D9E A00841A3 LUI V1, 0xA008\r
+BFD05DA2 01005063 ORI V1, V1, 256\r
+BFD05DA6 6A39 LW A0, 36(V1)\r
+BFD05DA8 0010FC7E LW V1, 16(S8)\r
+BFD05DAC 441B NOT16 V1, V1\r
+BFD05DAE 449C AND16 V1, A0\r
+BFD05DB0 E9A9 SW V1, 36(V0)\r
116: }\r
117: }\r
118: }\r
-BFD05DB2 0FBE MOVE SP, S8
-BFD05DB4 4BE7 LW RA, 28(SP)
-BFD05DB6 4BC6 LW S8, 24(SP)
-BFD05DB8 4C11 ADDIU SP, SP, 32
-BFD05DBA 459F JR16 RA
-BFD05DBC 0C00 NOP
+BFD05DB2 0FBE MOVE SP, S8\r
+BFD05DB4 4BE7 LW RA, 28(SP)\r
+BFD05DB6 4BC6 LW S8, 24(SP)\r
+BFD05DB8 4C11 ADDIU SP, SP, 32\r
+BFD05DBA 459F JR16 RA\r
+BFD05DBC 0C00 NOP\r
119: \r
120: \r
121: /**\r
129: */\r
130: void led_reset(uint8_t led_id)\r
131: {\r
-BFD07FC8 4FF1 ADDIU SP, SP, -32
-BFD07FCA CBE7 SW RA, 28(SP)
-BFD07FCC CBC6 SW S8, 24(SP)
-BFD07FCE 0FDD MOVE S8, SP
-BFD07FD0 0C44 MOVE V0, A0
-BFD07FD2 0020185E SB V0, 32(S8)
+BFD07FC8 4FF1 ADDIU SP, SP, -32\r
+BFD07FCA CBE7 SW RA, 28(SP)\r
+BFD07FCC CBC6 SW S8, 24(SP)\r
+BFD07FCE 0FDD MOVE S8, SP\r
+BFD07FD0 0C44 MOVE V0, A0\r
+BFD07FD2 0020185E SB V0, 32(S8)\r
132: uint32_t p;\r
133: uint32_t cnt;\r
134: \r
135: p = led_addr(led_id);\r
-BFD07FD6 0020145E LBU V0, 32(S8)
-BFD07FDA 0C82 MOVE A0, V0
-BFD07FDC 4A1077E8 JALS led_addr
-BFD07FDE 4A10 LW S0, 64(SP)
-BFD07FE0 0C00 NOP
-BFD07FE2 0014F85E SW V0, 20(S8)
+BFD07FD6 0020145E LBU V0, 32(S8)\r
+BFD07FDA 0C82 MOVE A0, V0\r
+BFD07FDC 4A1077E8 JALS led_addr\r
+BFD07FDE 4A10 LW S0, 64(SP)\r
+BFD07FE0 0C00 NOP\r
+BFD07FE2 0014F85E SW V0, 20(S8)\r
136: ((BBLED_TypeDef *)p)->CONFIG = (LED_CFG_RESET);\r
-BFD07FE6 0014FC5E LW V0, 20(S8)
-BFD07FEA 00803060 ADDIU V1, ZERO, 128
-BFD07FEE E9A0 SW V1, 0(V0)
+BFD07FE6 0014FC5E LW V0, 20(S8)\r
+BFD07FEA 00803060 ADDIU V1, ZERO, 128\r
+BFD07FEE E9A0 SW V1, 0(V0)\r
137: \r
138: cnt = 0x100000UL;\r
-BFD07FF0 001041A2 LUI V0, 0x10
-BFD07FF4 0010F85E SW V0, 16(S8)
+BFD07FF0 001041A2 LUI V0, 0x10\r
+BFD07FF4 0010F85E SW V0, 16(S8)\r
139: while ( ((BBLED_TypeDef *)p)->CONFIG & (LED_CFG_RESET) ) {\r
-BFD07FF8 CC0A B 0xBFD0800E
-BFD07FFA 0C00 NOP
-BFD0800E 0014FC5E LW V0, 20(S8)
-BFD08012 6920 LW V0, 0(V0)
-BFD08014 2D20 ANDI V0, V0, 0x80
-BFD08016 FFF140A2 BNEZC V0, 0xBFD07FFC
-BFD08018 CC02FFF1 LW RA, -13310(S1)
-BFD0801A CC02 B 0xBFD08020
-BFD0801C 0C00 NOP
+BFD07FF8 CC0A B 0xBFD0800E\r
+BFD07FFA 0C00 NOP\r
+BFD0800E 0014FC5E LW V0, 20(S8)\r
+BFD08012 6920 LW V0, 0(V0)\r
+BFD08014 2D20 ANDI V0, V0, 0x80\r
+BFD08016 FFF140A2 BNEZC V0, 0xBFD07FFC\r
+BFD08018 CC02FFF1 LW RA, -13310(S1)\r
+BFD0801A CC02 B 0xBFD08020\r
+BFD0801C 0C00 NOP\r
140: if ( cnt != 0UL ) {\r
-BFD07FFC 0010FC5E LW V0, 16(S8)
-BFD08000 000D40E2 BEQZC V0, 0xBFD0801E
+BFD07FFC 0010FC5E LW V0, 16(S8)\r
+BFD08000 000D40E2 BEQZC V0, 0xBFD0801E\r
141: cnt--;\r
-BFD08004 0010FC5E LW V0, 16(S8)
-BFD08008 6D2E ADDIU V0, V0, -1
-BFD0800A 0010F85E SW V0, 16(S8)
+BFD08004 0010FC5E LW V0, 16(S8)\r
+BFD08008 6D2E ADDIU V0, V0, -1\r
+BFD0800A 0010F85E SW V0, 16(S8)\r
142: } else {\r
143: break;\r
-BFD0801E 0C00 NOP
+BFD0801E 0C00 NOP\r
144: }\r
145: }\r
146: } \r
-BFD08020 0FBE MOVE SP, S8
-BFD08022 4BE7 LW RA, 28(SP)
-BFD08024 4BC6 LW S8, 24(SP)
-BFD08026 4C11 ADDIU SP, SP, 32
-BFD08028 459F JR16 RA
-BFD0802A 0C00 NOP
+BFD08020 0FBE MOVE SP, S8\r
+BFD08022 4BE7 LW RA, 28(SP)\r
+BFD08024 4BC6 LW S8, 24(SP)\r
+BFD08026 4C11 ADDIU SP, SP, 32\r
+BFD08028 459F JR16 RA\r
+BFD0802A 0C00 NOP\r
147: \r
148: \r
149: uint8_t led_get_gpio_num(uint8_t led_id)\r
150: {\r
-BFD099EC 4FB0 ADDIU SP, SP, -8
-BFD099EE CBC1 SW S8, 4(SP)
-BFD099F0 0FDD MOVE S8, SP
-BFD099F2 0C44 MOVE V0, A0
-BFD099F4 0008185E SB V0, 8(S8)
+BFD099EC 4FB0 ADDIU SP, SP, -8\r
+BFD099EE CBC1 SW S8, 4(SP)\r
+BFD099F0 0FDD MOVE S8, SP\r
+BFD099F2 0C44 MOVE V0, A0\r
+BFD099F4 0008185E SB V0, 8(S8)\r
151: return led_gpio_tbl[(led_id & ((LED_ID_MAX)-1u))];\r
-BFD099F8 0008145E LBU V0, 8(S8)
-BFD099FC 2DA2 ANDI V1, V0, 0x2
-BFD099FE BFD041A2 LUI V0, 0xBFD0
-BFD09A00 25B2BFD0 LDC1 F30, 9650(S0)
-BFD09A02 25B2 SLL V1, V1, 1
-BFD09A04 01783042 ADDIU V0, V0, 376
-BFD09A08 0526 ADDU V0, V1, V0
-BFD09A0A 2920 LHU V0, 0(V0)
-BFD09A0C 2D2D ANDI V0, V0, 0xFF
+BFD099F8 0008145E LBU V0, 8(S8)\r
+BFD099FC 2DA2 ANDI V1, V0, 0x2\r
+BFD099FE BFD041A2 LUI V0, 0xBFD0\r
+BFD09A00 25B2BFD0 LDC1 F30, 9650(S0)\r
+BFD09A02 25B2 SLL V1, V1, 1\r
+BFD09A04 01783042 ADDIU V0, V0, 376\r
+BFD09A08 0526 ADDU V0, V1, V0\r
+BFD09A0A 2920 LHU V0, 0(V0)\r
+BFD09A0C 2D2D ANDI V0, V0, 0xFF\r
152: }\r
-BFD09A0E 0FBE MOVE SP, S8
-BFD09A10 4BC1 LW S8, 4(SP)
-BFD09A12 4C05 ADDIU SP, SP, 8
-BFD09A14 459F JR16 RA
-BFD09A16 0C00 NOP
+BFD09A0E 0FBE MOVE SP, S8\r
+BFD09A10 4BC1 LW S8, 4(SP)\r
+BFD09A12 4C05 ADDIU SP, SP, 8\r
+BFD09A14 459F JR16 RA\r
+BFD09A16 0C00 NOP\r
153: \r
154: \r
155: /**\r
163: */\r
164: void led_init(uint8_t led_id)\r
165: {\r
-BFD07CFC 4FF1 ADDIU SP, SP, -32
-BFD07CFE CBE7 SW RA, 28(SP)
-BFD07D00 CBC6 SW S8, 24(SP)
-BFD07D02 0FDD MOVE S8, SP
-BFD07D04 0C44 MOVE V0, A0
-BFD07D06 0020185E SB V0, 32(S8)
+BFD07CFC 4FF1 ADDIU SP, SP, -32\r
+BFD07CFE CBE7 SW RA, 28(SP)\r
+BFD07D00 CBC6 SW S8, 24(SP)\r
+BFD07D02 0FDD MOVE S8, SP\r
+BFD07D04 0C44 MOVE V0, A0\r
+BFD07D06 0020185E SB V0, 32(S8)\r
166: uint16_t ledi;\r
167: \r
168: if ( led_id < LED_ID_MAX )\r
-BFD07D0A 0020145E LBU V0, 32(S8)
-BFD07D0E 0003B042 SLTIU V0, V0, 3
-BFD07D12 002040E2 BEQZC V0, 0xBFD07D56
+BFD07D0A 0020145E LBU V0, 32(S8)\r
+BFD07D0E 0003B042 SLTIU V0, V0, 3\r
+BFD07D12 002040E2 BEQZC V0, 0xBFD07D56\r
169: {\r
170: /* bits[7:0] = GPIO_ID, bits[15:8] = GPIO Function */\r
171: ledi = led_gpio_tbl[led_id];\r
-BFD07D16 0020147E LBU V1, 32(S8)
-BFD07D1A BFD041A2 LUI V0, 0xBFD0
-BFD07D1C 25B2BFD0 LDC1 F30, 9650(S0)
-BFD07D1E 25B2 SLL V1, V1, 1
-BFD07D20 01783042 ADDIU V0, V0, 376
-BFD07D24 0526 ADDU V0, V1, V0
-BFD07D26 2920 LHU V0, 0(V0)
-BFD07D28 0010385E SH V0, 16(S8)
+BFD07D16 0020147E LBU V1, 32(S8)\r
+BFD07D1A BFD041A2 LUI V0, 0xBFD0\r
+BFD07D1C 25B2BFD0 LDC1 F30, 9650(S0)\r
+BFD07D1E 25B2 SLL V1, V1, 1\r
+BFD07D20 01783042 ADDIU V0, V0, 376\r
+BFD07D24 0526 ADDU V0, V1, V0\r
+BFD07D26 2920 LHU V0, 0(V0)\r
+BFD07D28 0010385E SH V0, 16(S8)\r
172: GPIOPropertySet((ledi & 0xFF), GPIO_PROP_MUX_SEL, (ledi >> 8) & 0xFF);\r
-BFD07D2C 0010345E LHU V0, 16(S8)
-BFD07D30 2D2D ANDI V0, V0, 0xFF
-BFD07D32 0C62 MOVE V1, V0
-BFD07D34 0010345E LHU V0, 16(S8)
-BFD07D38 2521 SRL V0, V0, 8
-BFD07D3A 2D2F ANDI V0, V0, 0xFFFF
-BFD07D3C 0C83 MOVE A0, V1
-BFD07D3E EE87 LI A1, 7
-BFD07D40 0CC2 MOVE A2, V0
-BFD07D42 25CC77E8 JALS GPIOPropertySet
-BFD07D44 25CC SLL V1, A0, 6
-BFD07D46 0C00 NOP
+BFD07D2C 0010345E LHU V0, 16(S8)\r
+BFD07D30 2D2D ANDI V0, V0, 0xFF\r
+BFD07D32 0C62 MOVE V1, V0\r
+BFD07D34 0010345E LHU V0, 16(S8)\r
+BFD07D38 2521 SRL V0, V0, 8\r
+BFD07D3A 2D2F ANDI V0, V0, 0xFFFF\r
+BFD07D3C 0C83 MOVE A0, V1\r
+BFD07D3E EE87 LI A1, 7\r
+BFD07D40 0CC2 MOVE A2, V0\r
+BFD07D42 25CC77E8 JALS GPIOPropertySet\r
+BFD07D44 25CC SLL V1, A0, 6\r
+BFD07D46 0C00 NOP\r
173: led_reset(ledi & 0xFF);\r
-BFD07D48 0010345E LHU V0, 16(S8)
-BFD07D4C 2D2D ANDI V0, V0, 0xFF
-BFD07D4E 0C82 MOVE A0, V0
-BFD07D50 3FE477E8 JALS led_reset
-BFD07D52 0C003FE4 LH RA, 3072(A0)
-BFD07D54 0C00 NOP
+BFD07D48 0010345E LHU V0, 16(S8)\r
+BFD07D4C 2D2D ANDI V0, V0, 0xFF\r
+BFD07D4E 0C82 MOVE A0, V0\r
+BFD07D50 3FE477E8 JALS led_reset\r
+BFD07D52 0C003FE4 LH RA, 3072(A0)\r
+BFD07D54 0C00 NOP\r
174: }\r
175: }\r
-BFD07D56 0FBE MOVE SP, S8
-BFD07D58 4BE7 LW RA, 28(SP)
-BFD07D5A 4BC6 LW S8, 24(SP)
-BFD07D5C 4C11 ADDIU SP, SP, 32
-BFD07D5E 459F JR16 RA
-BFD07D60 0C00 NOP
+BFD07D56 0FBE MOVE SP, S8\r
+BFD07D58 4BE7 LW RA, 28(SP)\r
+BFD07D5A 4BC6 LW S8, 24(SP)\r
+BFD07D5C 4C11 ADDIU SP, SP, 32\r
+BFD07D5E 459F JR16 RA\r
+BFD07D60 0C00 NOP\r
176: \r
177: \r
178: /**\r
189: uint8_t duty_cycle,\r
190: uint16_t prescale)\r
191: {\r
-BFD07914 4FF1 ADDIU SP, SP, -32
-BFD07916 CBE7 SW RA, 28(SP)
-BFD07918 CBC6 SW S8, 24(SP)
-BFD0791A 0FDD MOVE S8, SP
-BFD0791C 0C65 MOVE V1, A1
-BFD0791E 0C46 MOVE V0, A2
-BFD07920 0020189E SB A0, 32(S8)
-BFD07924 0024187E SB V1, 36(S8)
-BFD07928 0028385E SH V0, 40(S8)
+BFD07914 4FF1 ADDIU SP, SP, -32\r
+BFD07916 CBE7 SW RA, 28(SP)\r
+BFD07918 CBC6 SW S8, 24(SP)\r
+BFD0791A 0FDD MOVE S8, SP\r
+BFD0791C 0C65 MOVE V1, A1\r
+BFD0791E 0C46 MOVE V0, A2\r
+BFD07920 0020189E SB A0, 32(S8)\r
+BFD07924 0024187E SB V1, 36(S8)\r
+BFD07928 0028385E SH V0, 40(S8)\r
192: uint32_t pLed;\r
193: \r
194: pLed = 0UL;\r
-BFD0792C 0010F81E SW ZERO, 16(S8)
+BFD0792C 0010F81E SW ZERO, 16(S8)\r
195: \r
196: if (led_is_valid(led_id)) {\r
-BFD07930 0020145E LBU V0, 32(S8)
-BFD07934 0C82 MOVE A0, V0
-BFD07936 4F3677E8 JALS led_is_valid
-BFD07938 4F36 ADDIU T9, T9, -5
-BFD0793A 0C00 NOP
-BFD0793C 001E40E2 BEQZC V0, 0xBFD0797C
+BFD07930 0020145E LBU V0, 32(S8)\r
+BFD07934 0C82 MOVE A0, V0\r
+BFD07936 4F3677E8 JALS led_is_valid\r
+BFD07938 4F36 ADDIU T9, T9, -5\r
+BFD0793A 0C00 NOP\r
+BFD0793C 001E40E2 BEQZC V0, 0xBFD0797C\r
197: pLed = led_addr(led_id);\r
-BFD07940 0020145E LBU V0, 32(S8)
-BFD07944 0C82 MOVE A0, V0
-BFD07946 4A1077E8 JALS led_addr
-BFD07948 4A10 LW S0, 64(SP)
-BFD0794A 0C00 NOP
-BFD0794C 0010F85E SW V0, 16(S8)
+BFD07940 0020145E LBU V0, 32(S8)\r
+BFD07944 0C82 MOVE A0, V0\r
+BFD07946 4A1077E8 JALS led_addr\r
+BFD07948 4A10 LW S0, 64(SP)\r
+BFD0794A 0C00 NOP\r
+BFD0794C 0010F85E SW V0, 16(S8)\r
198: \r
199: ((BBLED_TypeDef *)pLed)->CONFIG = LED_CFG_CNTL_BLINK;\r
-BFD07950 0010FC5E LW V0, 16(S8)
-BFD07954 ED82 LI V1, 2
-BFD07956 E9A0 SW V1, 0(V0)
+BFD07950 0010FC5E LW V0, 16(S8)\r
+BFD07954 ED82 LI V1, 2\r
+BFD07956 E9A0 SW V1, 0(V0)\r
200: ((BBLED_TypeDef *)pLed)->LIMIT = (uint32_t)duty_cycle;\r
-BFD07958 0010FC5E LW V0, 16(S8)
-BFD0795C 0024147E LBU V1, 36(S8)
-BFD07960 E9A1 SW V1, 4(V0)
+BFD07958 0010FC5E LW V0, 16(S8)\r
+BFD0795C 0024147E LBU V1, 36(S8)\r
+BFD07960 E9A1 SW V1, 4(V0)\r
201: ((BBLED_TypeDef *)pLed)->DELAY = (uint32_t)prescale;\r
-BFD07962 0010FC5E LW V0, 16(S8)
-BFD07966 0028347E LHU V1, 40(S8)
-BFD0796A E9A2 SW V1, 8(V0)
+BFD07962 0010FC5E LW V0, 16(S8)\r
+BFD07966 0028347E LHU V1, 40(S8)\r
+BFD0796A E9A2 SW V1, 8(V0)\r
202: ((BBLED_TypeDef *)pLed)->CONFIG |= (LED_CFG_EN_UPDATE);\r
-BFD0796C 0010FC5E LW V0, 16(S8)
-BFD07970 0010FC7E LW V1, 16(S8)
-BFD07974 69B0 LW V1, 0(V1)
-BFD07976 00405063 ORI V1, V1, 64
-BFD0797A E9A0 SW V1, 0(V0)
+BFD0796C 0010FC5E LW V0, 16(S8)\r
+BFD07970 0010FC7E LW V1, 16(S8)\r
+BFD07974 69B0 LW V1, 0(V1)\r
+BFD07976 00405063 ORI V1, V1, 64\r
+BFD0797A E9A0 SW V1, 0(V0)\r
203: }\r
204: }\r
-BFD0797C 0FBE MOVE SP, S8
-BFD0797E 4BE7 LW RA, 28(SP)
-BFD07980 4BC6 LW S8, 24(SP)
-BFD07982 4C11 ADDIU SP, SP, 32
-BFD07984 459F JR16 RA
-BFD07986 0C00 NOP
+BFD0797C 0FBE MOVE SP, S8\r
+BFD0797E 4BE7 LW RA, 28(SP)\r
+BFD07980 4BC6 LW S8, 24(SP)\r
+BFD07982 4C11 ADDIU SP, SP, 32\r
+BFD07984 459F JR16 RA\r
+BFD07986 0C00 NOP\r
205: \r
206: \r
207: /**\r
213: */\r
214: void led_out_toggle(uint8_t led_id)\r
215: {\r
-BFD085A8 4FF1 ADDIU SP, SP, -32
-BFD085AA CBE7 SW RA, 28(SP)
-BFD085AC CBC6 SW S8, 24(SP)
-BFD085AE 0FDD MOVE S8, SP
-BFD085B0 0C44 MOVE V0, A0
-BFD085B2 0020185E SB V0, 32(S8)
+BFD085A8 4FF1 ADDIU SP, SP, -32\r
+BFD085AA CBE7 SW RA, 28(SP)\r
+BFD085AC CBC6 SW S8, 24(SP)\r
+BFD085AE 0FDD MOVE S8, SP\r
+BFD085B0 0C44 MOVE V0, A0\r
+BFD085B2 0020185E SB V0, 32(S8)\r
216: uint32_t p;\r
217: \r
218: if (led_is_valid(led_id)) {\r
-BFD085B6 0020145E LBU V0, 32(S8)
-BFD085BA 0C82 MOVE A0, V0
-BFD085BC 4F3677E8 JALS led_is_valid
-BFD085BE 4F36 ADDIU T9, T9, -5
-BFD085C0 0C00 NOP
-BFD085C2 001740E2 BEQZC V0, 0xBFD085F4
+BFD085B6 0020145E LBU V0, 32(S8)\r
+BFD085BA 0C82 MOVE A0, V0\r
+BFD085BC 4F3677E8 JALS led_is_valid\r
+BFD085BE 4F36 ADDIU T9, T9, -5\r
+BFD085C0 0C00 NOP\r
+BFD085C2 001740E2 BEQZC V0, 0xBFD085F4\r
219: p = led_addr(led_id);\r
-BFD085C6 0020145E LBU V0, 32(S8)
-BFD085CA 0C82 MOVE A0, V0
-BFD085CC 4A1077E8 JALS led_addr
-BFD085CE 4A10 LW S0, 64(SP)
-BFD085D0 0C00 NOP
-BFD085D2 0010F85E SW V0, 16(S8)
+BFD085C6 0020145E LBU V0, 32(S8)\r
+BFD085CA 0C82 MOVE A0, V0\r
+BFD085CC 4A1077E8 JALS led_addr\r
+BFD085CE 4A10 LW S0, 64(SP)\r
+BFD085D0 0C00 NOP\r
+BFD085D2 0010F85E SW V0, 16(S8)\r
220: \r
221: if (((BBLED_TypeDef *)p)->CONFIG & LED_CFG_CNTL_MASK) {\r
-BFD085D6 0010FC5E LW V0, 16(S8)
-BFD085DA 6920 LW V0, 0(V0)
-BFD085DC 2D23 ANDI V0, V0, 0x3
-BFD085DE 000540E2 BEQZC V0, 0xBFD085EC
+BFD085D6 0010FC5E LW V0, 16(S8)\r
+BFD085DA 6920 LW V0, 0(V0)\r
+BFD085DC 2D23 ANDI V0, V0, 0x3\r
+BFD085DE 000540E2 BEQZC V0, 0xBFD085EC\r
222: ((BBLED_TypeDef *)p)->CONFIG = LED_CFG_CNTL_LO;\r
-BFD085E2 0010FC5E LW V0, 16(S8)
-BFD085E6 E820 SW S0, 0(V0)
-BFD085E8 CC05 B 0xBFD085F4
-BFD085EA 0C00 NOP
+BFD085E2 0010FC5E LW V0, 16(S8)\r
+BFD085E6 E820 SW S0, 0(V0)\r
+BFD085E8 CC05 B 0xBFD085F4\r
+BFD085EA 0C00 NOP\r
223: } else {\r
224: ((BBLED_TypeDef *)p)->CONFIG = LED_CFG_CNTL_HI;\r
-BFD085EC 0010FC5E LW V0, 16(S8)
-BFD085F0 ED83 LI V1, 3
-BFD085F2 E9A0 SW V1, 0(V0)
+BFD085EC 0010FC5E LW V0, 16(S8)\r
+BFD085F0 ED83 LI V1, 3\r
+BFD085F2 E9A0 SW V1, 0(V0)\r
225: }\r
226: }\r
227: }\r
-BFD085F4 0FBE MOVE SP, S8
-BFD085F6 4BE7 LW RA, 28(SP)
-BFD085F8 4BC6 LW S8, 24(SP)
-BFD085FA 4C11 ADDIU SP, SP, 32
-BFD085FC 459F JR16 RA
-BFD085FE 0C00 NOP
+BFD085F4 0FBE MOVE SP, S8\r
+BFD085F6 4BE7 LW RA, 28(SP)\r
+BFD085F8 4BC6 LW S8, 24(SP)\r
+BFD085FA 4C11 ADDIU SP, SP, 32\r
+BFD085FC 459F JR16 RA\r
+BFD085FE 0C00 NOP\r
228: \r
229: \r
230: /**\r
239: */\r
240: void led_out_high(uint8_t led_id)\r
241: {\r
-BFD09210 4FF1 ADDIU SP, SP, -32
-BFD09212 CBE7 SW RA, 28(SP)
-BFD09214 CBC6 SW S8, 24(SP)
-BFD09216 0FDD MOVE S8, SP
-BFD09218 0C44 MOVE V0, A0
-BFD0921A 0020185E SB V0, 32(S8)
+BFD09210 4FF1 ADDIU SP, SP, -32\r
+BFD09212 CBE7 SW RA, 28(SP)\r
+BFD09214 CBC6 SW S8, 24(SP)\r
+BFD09216 0FDD MOVE S8, SP\r
+BFD09218 0C44 MOVE V0, A0\r
+BFD0921A 0020185E SB V0, 32(S8)\r
242: uint32_t p;\r
243: \r
244: if (led_is_valid(led_id)) {\r
-BFD0921E 0020145E LBU V0, 32(S8)
-BFD09222 0C82 MOVE A0, V0
-BFD09224 4F3677E8 JALS led_is_valid
-BFD09226 4F36 ADDIU T9, T9, -5
-BFD09228 0C00 NOP
-BFD0922A 000C40E2 BEQZC V0, 0xBFD09246
+BFD0921E 0020145E LBU V0, 32(S8)\r
+BFD09222 0C82 MOVE A0, V0\r
+BFD09224 4F3677E8 JALS led_is_valid\r
+BFD09226 4F36 ADDIU T9, T9, -5\r
+BFD09228 0C00 NOP\r
+BFD0922A 000C40E2 BEQZC V0, 0xBFD09246\r
245: p = led_addr(led_id);\r
-BFD0922E 0020145E LBU V0, 32(S8)
-BFD09232 0C82 MOVE A0, V0
-BFD09234 4A1077E8 JALS led_addr
-BFD09236 4A10 LW S0, 64(SP)
-BFD09238 0C00 NOP
-BFD0923A 0010F85E SW V0, 16(S8)
+BFD0922E 0020145E LBU V0, 32(S8)\r
+BFD09232 0C82 MOVE A0, V0\r
+BFD09234 4A1077E8 JALS led_addr\r
+BFD09236 4A10 LW S0, 64(SP)\r
+BFD09238 0C00 NOP\r
+BFD0923A 0010F85E SW V0, 16(S8)\r
246: ((BBLED_TypeDef *)p)->CONFIG = LED_CFG_CNTL_HI;\r
-BFD0923E 0010FC5E LW V0, 16(S8)
-BFD09242 ED83 LI V1, 3
-BFD09244 E9A0 SW V1, 0(V0)
+BFD0923E 0010FC5E LW V0, 16(S8)\r
+BFD09242 ED83 LI V1, 3\r
+BFD09244 E9A0 SW V1, 0(V0)\r
247: }\r
248: }\r
-BFD09246 0FBE MOVE SP, S8
-BFD09248 4BE7 LW RA, 28(SP)
-BFD0924A 4BC6 LW S8, 24(SP)
-BFD0924C 4C11 ADDIU SP, SP, 32
-BFD0924E 459F JR16 RA
-BFD09250 0C00 NOP
+BFD09246 0FBE MOVE SP, S8\r
+BFD09248 4BE7 LW RA, 28(SP)\r
+BFD0924A 4BC6 LW S8, 24(SP)\r
+BFD0924C 4C11 ADDIU SP, SP, 32\r
+BFD0924E 459F JR16 RA\r
+BFD09250 0C00 NOP\r
249: \r
250: \r
251: /**\r
260: */\r
261: void led_out_low(uint8_t led_id)\r
262: {\r
-BFD09460 4FF1 ADDIU SP, SP, -32
-BFD09462 CBE7 SW RA, 28(SP)
-BFD09464 CBC6 SW S8, 24(SP)
-BFD09466 0FDD MOVE S8, SP
-BFD09468 0C44 MOVE V0, A0
-BFD0946A 0020185E SB V0, 32(S8)
+BFD09460 4FF1 ADDIU SP, SP, -32\r
+BFD09462 CBE7 SW RA, 28(SP)\r
+BFD09464 CBC6 SW S8, 24(SP)\r
+BFD09466 0FDD MOVE S8, SP\r
+BFD09468 0C44 MOVE V0, A0\r
+BFD0946A 0020185E SB V0, 32(S8)\r
263: uint32_t p;\r
264: \r
265: if (led_is_valid(led_id)) {\r
-BFD0946E 0020145E LBU V0, 32(S8)
-BFD09472 0C82 MOVE A0, V0
-BFD09474 4F3677E8 JALS led_is_valid
-BFD09476 4F36 ADDIU T9, T9, -5
-BFD09478 0C00 NOP
-BFD0947A 000B40E2 BEQZC V0, 0xBFD09494
+BFD0946E 0020145E LBU V0, 32(S8)\r
+BFD09472 0C82 MOVE A0, V0\r
+BFD09474 4F3677E8 JALS led_is_valid\r
+BFD09476 4F36 ADDIU T9, T9, -5\r
+BFD09478 0C00 NOP\r
+BFD0947A 000B40E2 BEQZC V0, 0xBFD09494\r
266: p = led_addr(led_id);\r
-BFD0947E 0020145E LBU V0, 32(S8)
-BFD09482 0C82 MOVE A0, V0
-BFD09484 4A1077E8 JALS led_addr
-BFD09486 4A10 LW S0, 64(SP)
-BFD09488 0C00 NOP
-BFD0948A 0010F85E SW V0, 16(S8)
+BFD0947E 0020145E LBU V0, 32(S8)\r
+BFD09482 0C82 MOVE A0, V0\r
+BFD09484 4A1077E8 JALS led_addr\r
+BFD09486 4A10 LW S0, 64(SP)\r
+BFD09488 0C00 NOP\r
+BFD0948A 0010F85E SW V0, 16(S8)\r
267: ((BBLED_TypeDef *)p)->CONFIG = LED_CFG_CNTL_LO;\r
-BFD0948E 0010FC5E LW V0, 16(S8)
-BFD09492 E820 SW S0, 0(V0)
+BFD0948E 0010FC5E LW V0, 16(S8)\r
+BFD09492 E820 SW S0, 0(V0)\r
268: }\r
269: }\r
-BFD09494 0FBE MOVE SP, S8
-BFD09496 4BE7 LW RA, 28(SP)
-BFD09498 4BC6 LW S8, 24(SP)
-BFD0949A 4C11 ADDIU SP, SP, 32
-BFD0949C 459F JR16 RA
-BFD0949E 0C00 NOP
+BFD09494 0FBE MOVE SP, S8\r
+BFD09496 4BE7 LW RA, 28(SP)\r
+BFD09498 4BC6 LW S8, 24(SP)\r
+BFD0949A 4C11 ADDIU SP, SP, 32\r
+BFD0949C 459F JR16 RA\r
+BFD0949E 0C00 NOP\r
270: \r
271: \r
272: #ifdef __cplusplus\r
276: /* end mec14xx_bbled.h */\r
277: /** @}\r
278: */\r
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq26.c ----
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq26.c ----\r
1: /*****************************************************************************\r
2: * (c) 2013 Microchip Technology Inc. and its subsidiaries.\r
3: * You may use this software and any derivatives exclusively with\r
39: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
40: girq26_isr(void)\r
41: {\r
-BFD07408 E17C03BD RDPGPR SP, SP
-BFD0740C 00FC036E MFC0 K1, EPC
-BFD0740E 034C00FC INS A3, GP, 13, -12
-BFD07410 10FC034C MFC0 K0, SRSCtl
-BFD07412 4FF110FC ADDI A3, GP, 20465
-BFD07414 4FF1 ADDIU SP, SP, -32
-BFD07416 CB67 SW K1, 28(SP)
-BFD07418 00FC036C MFC0 K1, Status
-BFD0741C CB46 SW K0, 24(SP)
-BFD0741E 00FC034D MFC0 K0, Cause
-BFD07422 CB65 SW K1, 20(SP)
-BFD07424 5040035A SRL K0, K0, 10
-BFD07426 037A5040 ORI V0, ZERO, 890
-BFD07428 7A8C037A INS K1, K0, 10, 6
-BFD0742A 03607A8C ADDIUPC A1, 787296
-BFD0742C 204C0360 INS K1, ZERO, 1, 4
-BFD0742E 036C204C LWC2 V0, 876(T4)
-BFD07430 02FC036C MTC0 K1, Status
-BFD07434 C862 SW V1, 8(SP)
-BFD07436 C841 SW V0, 4(SP)
-BFD07438 4866 LW V1, 24(SP)
-BFD0743A 2DB7 ANDI V1, V1, 0xF
-BFD0743C CBC3 SW S8, 12(SP)
-BFD0743E 0FDD MOVE S8, SP
+BFD07408 E17C03BD RDPGPR SP, SP\r
+BFD0740C 00FC036E MFC0 K1, EPC\r
+BFD0740E 034C00FC INS A3, GP, 13, -12\r
+BFD07410 10FC034C MFC0 K0, SRSCtl\r
+BFD07412 4FF110FC ADDI A3, GP, 20465\r
+BFD07414 4FF1 ADDIU SP, SP, -32\r
+BFD07416 CB67 SW K1, 28(SP)\r
+BFD07418 00FC036C MFC0 K1, Status\r
+BFD0741C CB46 SW K0, 24(SP)\r
+BFD0741E 00FC034D MFC0 K0, Cause\r
+BFD07422 CB65 SW K1, 20(SP)\r
+BFD07424 5040035A SRL K0, K0, 10\r
+BFD07426 037A5040 ORI V0, ZERO, 890\r
+BFD07428 7A8C037A INS K1, K0, 10, 6\r
+BFD0742A 03607A8C ADDIUPC A1, 787296\r
+BFD0742C 204C0360 INS K1, ZERO, 1, 4\r
+BFD0742E 036C204C LWC2 V0, 876(T4)\r
+BFD07430 02FC036C MTC0 K1, Status\r
+BFD07434 C862 SW V1, 8(SP)\r
+BFD07436 C841 SW V0, 4(SP)\r
+BFD07438 4866 LW V1, 24(SP)\r
+BFD0743A 2DB7 ANDI V1, V1, 0xF\r
+BFD0743C CBC3 SW S8, 12(SP)\r
+BFD0743E 0FDD MOVE S8, SP\r
42: JTVIC_GROUP_EN_CLR->w = (1ul<<16);\r
-BFD07440 BFFF41A2 LUI V0, 0xBFFF
-BFD07442 5042BFFF LDC1 F31, 20546(RA)
-BFD07444 C50C5042 ORI V0, V0, -15092
-BFD07448 000141A3 LUI V1, 0x1
-BFD0744C E9A0 SW V1, 0(V0)
+BFD07440 BFFF41A2 LUI V0, 0xBFFF\r
+BFD07442 5042BFFF LDC1 F31, 20546(RA)\r
+BFD07444 C50C5042 ORI V0, V0, -15092\r
+BFD07448 000141A3 LUI V1, 0x1\r
+BFD0744C E9A0 SW V1, 0(V0)\r
43: }\r
-BFD0744E 0FBE MOVE SP, S8
-BFD07450 4846 LW V0, 24(SP)
-BFD07452 2D27 ANDI V0, V0, 0xF
-BFD07454 4BC3 LW S8, 12(SP)
-BFD07456 4862 LW V1, 8(SP)
-BFD07458 4841 LW V0, 4(SP)
-BFD0745A 477C0000 DI ZERO
-BFD0745E 18000000 SLL ZERO, ZERO, 3
-BFD07460 4B471800 SB ZERO, 19271(ZERO)
-BFD07462 4B47 LW K0, 28(SP)
-BFD07464 4B65 LW K1, 20(SP)
-BFD07466 02FC034E MTC0 K0, EPC
-BFD0746A 4B46 LW K0, 24(SP)
-BFD0746C 4C11 ADDIU SP, SP, 32
-BFD0746E 12FC034C MTC0 K0, SRSCtl
-BFD07470 03BD12FC ADDI S7, GP, 957
-BFD07472 F17C03BD WRPGPR SP, SP
-BFD07474 036CF17C JALX 0xBDF00DB0
-BFD07476 02FC036C MTC0 K1, Status
-BFD07478 000002FC SLL S7, GP, 0
-BFD0747A F37C0000 ERET
-BFD0747C 0C00F37C JALX 0xBDF03000
+BFD0744E 0FBE MOVE SP, S8\r
+BFD07450 4846 LW V0, 24(SP)\r
+BFD07452 2D27 ANDI V0, V0, 0xF\r
+BFD07454 4BC3 LW S8, 12(SP)\r
+BFD07456 4862 LW V1, 8(SP)\r
+BFD07458 4841 LW V0, 4(SP)\r
+BFD0745A 477C0000 DI ZERO\r
+BFD0745E 18000000 SLL ZERO, ZERO, 3\r
+BFD07460 4B471800 SB ZERO, 19271(ZERO)\r
+BFD07462 4B47 LW K0, 28(SP)\r
+BFD07464 4B65 LW K1, 20(SP)\r
+BFD07466 02FC034E MTC0 K0, EPC\r
+BFD0746A 4B46 LW K0, 24(SP)\r
+BFD0746C 4C11 ADDIU SP, SP, 32\r
+BFD0746E 12FC034C MTC0 K0, SRSCtl\r
+BFD07470 03BD12FC ADDI S7, GP, 957\r
+BFD07472 F17C03BD WRPGPR SP, SP\r
+BFD07474 036CF17C JALX 0xBDF00DB0\r
+BFD07476 02FC036C MTC0 K1, Status\r
+BFD07478 000002FC SLL S7, GP, 0\r
+BFD0747A F37C0000 ERET\r
+BFD0747C 0C00F37C JALX 0xBDF03000\r
44: \r
45: #else\r
46: \r
123: /** @}\r
124: */\r
125: \r
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq25.c ----
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq25.c ----\r
1: /*****************************************************************************\r
2: * (c) 2013 Microchip Technology Inc. and its subsidiaries.\r
3: * You may use this software and any derivatives exclusively with\r
38: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
39: girq25_isr(void)\r
40: {\r
-BFD07390 E17C03BD RDPGPR SP, SP
-BFD07394 00FC036E MFC0 K1, EPC
-BFD07396 034C00FC INS A3, GP, 13, -12
-BFD07398 10FC034C MFC0 K0, SRSCtl
-BFD0739A 4FF110FC ADDI A3, GP, 20465
-BFD0739C 4FF1 ADDIU SP, SP, -32
-BFD0739E CB67 SW K1, 28(SP)
-BFD073A0 00FC036C MFC0 K1, Status
-BFD073A4 CB46 SW K0, 24(SP)
-BFD073A6 00FC034D MFC0 K0, Cause
-BFD073AA CB65 SW K1, 20(SP)
-BFD073AC 5040035A SRL K0, K0, 10
-BFD073AE 037A5040 ORI V0, ZERO, 890
-BFD073B0 7A8C037A INS K1, K0, 10, 6
-BFD073B2 03607A8C ADDIUPC A1, 787296
-BFD073B4 204C0360 INS K1, ZERO, 1, 4
-BFD073B6 036C204C LWC2 V0, 876(T4)
-BFD073B8 02FC036C MTC0 K1, Status
-BFD073BC C862 SW V1, 8(SP)
-BFD073BE C841 SW V0, 4(SP)
-BFD073C0 4866 LW V1, 24(SP)
-BFD073C2 2DB7 ANDI V1, V1, 0xF
-BFD073C4 CBC3 SW S8, 12(SP)
-BFD073C6 0FDD MOVE S8, SP
+BFD07390 E17C03BD RDPGPR SP, SP\r
+BFD07394 00FC036E MFC0 K1, EPC\r
+BFD07396 034C00FC INS A3, GP, 13, -12\r
+BFD07398 10FC034C MFC0 K0, SRSCtl\r
+BFD0739A 4FF110FC ADDI A3, GP, 20465\r
+BFD0739C 4FF1 ADDIU SP, SP, -32\r
+BFD0739E CB67 SW K1, 28(SP)\r
+BFD073A0 00FC036C MFC0 K1, Status\r
+BFD073A4 CB46 SW K0, 24(SP)\r
+BFD073A6 00FC034D MFC0 K0, Cause\r
+BFD073AA CB65 SW K1, 20(SP)\r
+BFD073AC 5040035A SRL K0, K0, 10\r
+BFD073AE 037A5040 ORI V0, ZERO, 890\r
+BFD073B0 7A8C037A INS K1, K0, 10, 6\r
+BFD073B2 03607A8C ADDIUPC A1, 787296\r
+BFD073B4 204C0360 INS K1, ZERO, 1, 4\r
+BFD073B6 036C204C LWC2 V0, 876(T4)\r
+BFD073B8 02FC036C MTC0 K1, Status\r
+BFD073BC C862 SW V1, 8(SP)\r
+BFD073BE C841 SW V0, 4(SP)\r
+BFD073C0 4866 LW V1, 24(SP)\r
+BFD073C2 2DB7 ANDI V1, V1, 0xF\r
+BFD073C4 CBC3 SW S8, 12(SP)\r
+BFD073C6 0FDD MOVE S8, SP\r
41: JTVIC_GROUP_EN_CLR->w = (1ul<<15);\r
-BFD073C8 BFFF41A2 LUI V0, 0xBFFF
-BFD073CA 5042BFFF LDC1 F31, 20546(RA)
-BFD073CC C50C5042 ORI V0, V0, -15092
-BFD073D0 80005060 ORI V1, ZERO, -32768
-BFD073D4 E9A0 SW V1, 0(V0)
+BFD073C8 BFFF41A2 LUI V0, 0xBFFF\r
+BFD073CA 5042BFFF LDC1 F31, 20546(RA)\r
+BFD073CC C50C5042 ORI V0, V0, -15092\r
+BFD073D0 80005060 ORI V1, ZERO, -32768\r
+BFD073D4 E9A0 SW V1, 0(V0)\r
42: }\r
-BFD073D6 0FBE MOVE SP, S8
-BFD073D8 4846 LW V0, 24(SP)
-BFD073DA 2D27 ANDI V0, V0, 0xF
-BFD073DC 4BC3 LW S8, 12(SP)
-BFD073DE 4862 LW V1, 8(SP)
-BFD073E0 4841 LW V0, 4(SP)
-BFD073E2 477C0000 DI ZERO
-BFD073E6 18000000 SLL ZERO, ZERO, 3
-BFD073E8 4B471800 SB ZERO, 19271(ZERO)
-BFD073EA 4B47 LW K0, 28(SP)
-BFD073EC 4B65 LW K1, 20(SP)
-BFD073EE 02FC034E MTC0 K0, EPC
-BFD073F2 4B46 LW K0, 24(SP)
-BFD073F4 4C11 ADDIU SP, SP, 32
-BFD073F6 12FC034C MTC0 K0, SRSCtl
-BFD073F8 03BD12FC ADDI S7, GP, 957
-BFD073FA F17C03BD WRPGPR SP, SP
-BFD073FC 036CF17C JALX 0xBDF00DB0
-BFD073FE 02FC036C MTC0 K1, Status
-BFD07400 000002FC SLL S7, GP, 0
-BFD07402 F37C0000 ERET
-BFD07404 0C00F37C JALX 0xBDF03000
+BFD073D6 0FBE MOVE SP, S8\r
+BFD073D8 4846 LW V0, 24(SP)\r
+BFD073DA 2D27 ANDI V0, V0, 0xF\r
+BFD073DC 4BC3 LW S8, 12(SP)\r
+BFD073DE 4862 LW V1, 8(SP)\r
+BFD073E0 4841 LW V0, 4(SP)\r
+BFD073E2 477C0000 DI ZERO\r
+BFD073E6 18000000 SLL ZERO, ZERO, 3\r
+BFD073E8 4B471800 SB ZERO, 19271(ZERO)\r
+BFD073EA 4B47 LW K0, 28(SP)\r
+BFD073EC 4B65 LW K1, 20(SP)\r
+BFD073EE 02FC034E MTC0 K0, EPC\r
+BFD073F2 4B46 LW K0, 24(SP)\r
+BFD073F4 4C11 ADDIU SP, SP, 32\r
+BFD073F6 12FC034C MTC0 K0, SRSCtl\r
+BFD073F8 03BD12FC ADDI S7, GP, 957\r
+BFD073FA F17C03BD WRPGPR SP, SP\r
+BFD073FC 036CF17C JALX 0xBDF00DB0\r
+BFD073FE 02FC036C MTC0 K1, Status\r
+BFD07400 000002FC SLL S7, GP, 0\r
+BFD07402 F37C0000 ERET\r
+BFD07404 0C00F37C JALX 0xBDF03000\r
43: \r
44: #else\r
45: \r
218: /** @}\r
219: */\r
220: \r
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq24.c ----
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq24.c ----\r
1: /*****************************************************************************\r
2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
3: * You may use this software and any derivatives exclusively with\r
137: void __attribute__((weak, interrupt, nomips16))\r
138: girq24_b0(void)\r
139: {\r
-BFD065A8 E17C03BD RDPGPR SP, SP
-BFD065AC 00FC036E MFC0 K1, EPC
-BFD065AE 034C00FC INS A3, GP, 13, -12
-BFD065B0 10FC034C MFC0 K0, SRSCtl
-BFD065B2 4FED10FC ADDI A3, GP, 20461
-BFD065B4 4FED ADDIU SP, SP, -40
-BFD065B6 CB69 SW K1, 36(SP)
-BFD065B8 00FC036C MFC0 K1, Status
-BFD065BC CB48 SW K0, 32(SP)
-BFD065BE 00FC034D MFC0 K0, Cause
-BFD065C2 CB67 SW K1, 28(SP)
-BFD065C4 5040035A SRL K0, K0, 10
-BFD065C6 037A5040 ORI V0, ZERO, 890
-BFD065C8 7A8C037A INS K1, K0, 10, 6
-BFD065CA 03607A8C ADDIUPC A1, 787296
-BFD065CC 204C0360 INS K1, ZERO, 1, 4
-BFD065CE 036C204C LWC2 V0, 876(T4)
-BFD065D0 02FC036C MTC0 K1, Status
-BFD065D4 C864 SW V1, 16(SP)
-BFD065D6 C843 SW V0, 12(SP)
-BFD065D8 4868 LW V1, 32(SP)
-BFD065DA 2DB7 ANDI V1, V1, 0xF
-BFD065DC CBC5 SW S8, 20(SP)
-BFD065DE 0FDD MOVE S8, SP
+BFD065A8 E17C03BD RDPGPR SP, SP\r
+BFD065AC 00FC036E MFC0 K1, EPC\r
+BFD065AE 034C00FC INS A3, GP, 13, -12\r
+BFD065B0 10FC034C MFC0 K0, SRSCtl\r
+BFD065B2 4FED10FC ADDI A3, GP, 20461\r
+BFD065B4 4FED ADDIU SP, SP, -40\r
+BFD065B6 CB69 SW K1, 36(SP)\r
+BFD065B8 00FC036C MFC0 K1, Status\r
+BFD065BC CB48 SW K0, 32(SP)\r
+BFD065BE 00FC034D MFC0 K0, Cause\r
+BFD065C2 CB67 SW K1, 28(SP)\r
+BFD065C4 5040035A SRL K0, K0, 10\r
+BFD065C6 037A5040 ORI V0, ZERO, 890\r
+BFD065C8 7A8C037A INS K1, K0, 10, 6\r
+BFD065CA 03607A8C ADDIUPC A1, 787296\r
+BFD065CC 204C0360 INS K1, ZERO, 1, 4\r
+BFD065CE 036C204C LWC2 V0, 876(T4)\r
+BFD065D0 02FC036C MTC0 K1, Status\r
+BFD065D4 C864 SW V1, 16(SP)\r
+BFD065D6 C843 SW V0, 12(SP)\r
+BFD065D8 4868 LW V1, 32(SP)\r
+BFD065DA 2DB7 ANDI V1, V1, 0xF\r
+BFD065DC CBC5 SW S8, 20(SP)\r
+BFD065DE 0FDD MOVE S8, SP\r
140: uint32_t r;\r
141: \r
142: r = _CP0_GET_COUNT();\r
-BFD065E0 00FC0049 MFC0 V0, Count
-BFD065E4 0000F85E SW V0, 0(S8)
+BFD065E0 00FC0049 MFC0 V0, Count\r
+BFD065E4 0000F85E SW V0, 0(S8)\r
143: r += (M14K_TIMER_COMPARE);\r
-BFD065E8 0000FC7E LW V1, 0(S8)
-BFD065EC 00B741A2 LUI V0, 0xB7
-BFD065F0 1B005042 ORI V0, V0, 6912
-BFD065F2 05261B00 SB T8, 1318(ZERO)
-BFD065F4 0526 ADDU V0, V1, V0
-BFD065F6 0000F85E SW V0, 0(S8)
+BFD065E8 0000FC7E LW V1, 0(S8)\r
+BFD065EC 00B741A2 LUI V0, 0xB7\r
+BFD065F0 1B005042 ORI V0, V0, 6912\r
+BFD065F2 05261B00 SB T8, 1318(ZERO)\r
+BFD065F4 0526 ADDU V0, V1, V0\r
+BFD065F6 0000F85E SW V0, 0(S8)\r
144: _CP0_SET_COUNT(r);\r
-BFD065FA 0000FC5E LW V0, 0(S8)
-BFD065FE 02FC0049 MTC0 V0, Count
-BFD06600 000002FC SLL S7, GP, 0
-BFD06602 18000000 SLL ZERO, ZERO, 3
-BFD06604 41A21800 SB ZERO, 16802(ZERO)
+BFD065FA 0000FC5E LW V0, 0(S8)\r
+BFD065FE 02FC0049 MTC0 V0, Count\r
+BFD06600 000002FC SLL S7, GP, 0\r
+BFD06602 18000000 SLL ZERO, ZERO, 3\r
+BFD06604 41A21800 SB ZERO, 16802(ZERO)\r
145: \r
146: JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << 0); \r
-BFD06606 BFFF41A2 LUI V0, 0xBFFF
-BFD06608 5042BFFF LDC1 F31, 20546(RA)
-BFD0660A C0005042 ORI V0, V0, -16384
-BFD0660E ED81 LI V1, 1
-BFD06610 0100F862 SW V1, 256(V0)
+BFD06606 BFFF41A2 LUI V0, 0xBFFF\r
+BFD06608 5042BFFF LDC1 F31, 20546(RA)\r
+BFD0660A C0005042 ORI V0, V0, -16384\r
+BFD0660E ED81 LI V1, 1\r
+BFD06610 0100F862 SW V1, 256(V0)\r
147: }\r
-BFD06614 0FBE MOVE SP, S8
-BFD06616 4848 LW V0, 32(SP)
-BFD06618 2D27 ANDI V0, V0, 0xF
-BFD0661A 4BC5 LW S8, 20(SP)
-BFD0661C 4864 LW V1, 16(SP)
-BFD0661E 4843 LW V0, 12(SP)
-BFD06620 477C0000 DI ZERO
-BFD06624 18000000 SLL ZERO, ZERO, 3
-BFD06626 4B491800 SB ZERO, 19273(ZERO)
-BFD06628 4B49 LW K0, 36(SP)
-BFD0662A 4B67 LW K1, 28(SP)
-BFD0662C 02FC034E MTC0 K0, EPC
-BFD06630 4B48 LW K0, 32(SP)
-BFD06632 4C15 ADDIU SP, SP, 40
-BFD06634 12FC034C MTC0 K0, SRSCtl
-BFD06636 03BD12FC ADDI S7, GP, 957
-BFD06638 F17C03BD WRPGPR SP, SP
-BFD0663A 036CF17C JALX 0xBDF00DB0
-BFD0663C 02FC036C MTC0 K1, Status
-BFD0663E 000002FC SLL S7, GP, 0
-BFD06640 F37C0000 ERET
-BFD06642 4FEDF37C JALX 0xBDF13FB4
+BFD06614 0FBE MOVE SP, S8\r
+BFD06616 4848 LW V0, 32(SP)\r
+BFD06618 2D27 ANDI V0, V0, 0xF\r
+BFD0661A 4BC5 LW S8, 20(SP)\r
+BFD0661C 4864 LW V1, 16(SP)\r
+BFD0661E 4843 LW V0, 12(SP)\r
+BFD06620 477C0000 DI ZERO\r
+BFD06624 18000000 SLL ZERO, ZERO, 3\r
+BFD06626 4B491800 SB ZERO, 19273(ZERO)\r
+BFD06628 4B49 LW K0, 36(SP)\r
+BFD0662A 4B67 LW K1, 28(SP)\r
+BFD0662C 02FC034E MTC0 K0, EPC\r
+BFD06630 4B48 LW K0, 32(SP)\r
+BFD06632 4C15 ADDIU SP, SP, 40\r
+BFD06634 12FC034C MTC0 K0, SRSCtl\r
+BFD06636 03BD12FC ADDI S7, GP, 957\r
+BFD06638 F17C03BD WRPGPR SP, SP\r
+BFD0663A 036CF17C JALX 0xBDF00DB0\r
+BFD0663C 02FC036C MTC0 K1, Status\r
+BFD0663E 000002FC SLL S7, GP, 0\r
+BFD06640 F37C0000 ERET\r
+BFD06642 4FEDF37C JALX 0xBDF13FB4\r
148: \r
149: void __attribute__((weak, interrupt, nomips16))\r
150: girq24_b1(void)\r
151: {\r
-BFD0465C E17C03BD RDPGPR SP, SP
-BFD04660 00FC036E MFC0 K1, EPC
-BFD04662 034C00FC INS A3, GP, 13, -12
-BFD04664 10FC034C MFC0 K0, SRSCtl
-BFD04666 4FC510FC ADDI A3, GP, 20421
-BFD04668 4FC5 ADDIU SP, SP, -120
-BFD0466A CB7D SW K1, 116(SP)
-BFD0466C 00FC036C MFC0 K1, Status
-BFD04670 CB5C SW K0, 112(SP)
-BFD04672 00FC034D MFC0 K0, Cause
-BFD04676 CB7B SW K1, 108(SP)
-BFD04678 5040035A SRL K0, K0, 10
-BFD0467A 037A5040 ORI V0, ZERO, 890
-BFD0467C 7A8C037A INS K1, K0, 10, 6
-BFD0467E 03607A8C ADDIUPC A1, 787296
-BFD04680 204C0360 INS K1, ZERO, 1, 4
-BFD04682 036C204C LWC2 V0, 876(T4)
-BFD04684 02FC036C MTC0 K1, Status
-BFD04688 C867 SW V1, 28(SP)
-BFD0468A C846 SW V0, 24(SP)
-BFD0468C 487C LW V1, 112(SP)
-BFD0468E 2DB7 ANDI V1, V1, 0xF
-BFD04690 001140A3 BNEZC V1, 0xBFD046B6
-BFD04694 CBF7 SW RA, 92(SP)
-BFD04696 CBD6 SW S8, 88(SP)
-BFD04698 CB35 SW T9, 84(SP)
-BFD0469A CB14 SW T8, 80(SP)
-BFD0469C C9F3 SW T7, 76(SP)
-BFD0469E C9D2 SW T6, 72(SP)
-BFD046A0 C9B1 SW T5, 68(SP)
-BFD046A2 C990 SW T4, 64(SP)
-BFD046A4 C96F SW T3, 60(SP)
-BFD046A6 C94E SW T2, 56(SP)
-BFD046A8 C92D SW T1, 52(SP)
-BFD046AA C90C SW T0, 48(SP)
-BFD046AC C8EB SW A3, 44(SP)
-BFD046AE C8CA SW A2, 40(SP)
-BFD046B0 C8A9 SW A1, 36(SP)
-BFD046B2 C888 SW A0, 32(SP)
-BFD046B4 C825 SW AT, 20(SP)
-BFD046B6 4642 MFLO V0
-BFD046B8 C859 SW V0, 100(SP)
-BFD046BA 4603 MFHI V1
-BFD046BC C878 SW V1, 96(SP)
-BFD046BE 0FDD MOVE S8, SP
+BFD0465C E17C03BD RDPGPR SP, SP\r
+BFD04660 00FC036E MFC0 K1, EPC\r
+BFD04662 034C00FC INS A3, GP, 13, -12\r
+BFD04664 10FC034C MFC0 K0, SRSCtl\r
+BFD04666 4FC510FC ADDI A3, GP, 20421\r
+BFD04668 4FC5 ADDIU SP, SP, -120\r
+BFD0466A CB7D SW K1, 116(SP)\r
+BFD0466C 00FC036C MFC0 K1, Status\r
+BFD04670 CB5C SW K0, 112(SP)\r
+BFD04672 00FC034D MFC0 K0, Cause\r
+BFD04676 CB7B SW K1, 108(SP)\r
+BFD04678 5040035A SRL K0, K0, 10\r
+BFD0467A 037A5040 ORI V0, ZERO, 890\r
+BFD0467C 7A8C037A INS K1, K0, 10, 6\r
+BFD0467E 03607A8C ADDIUPC A1, 787296\r
+BFD04680 204C0360 INS K1, ZERO, 1, 4\r
+BFD04682 036C204C LWC2 V0, 876(T4)\r
+BFD04684 02FC036C MTC0 K1, Status\r
+BFD04688 C867 SW V1, 28(SP)\r
+BFD0468A C846 SW V0, 24(SP)\r
+BFD0468C 487C LW V1, 112(SP)\r
+BFD0468E 2DB7 ANDI V1, V1, 0xF\r
+BFD04690 001140A3 BNEZC V1, 0xBFD046B6\r
+BFD04694 CBF7 SW RA, 92(SP)\r
+BFD04696 CBD6 SW S8, 88(SP)\r
+BFD04698 CB35 SW T9, 84(SP)\r
+BFD0469A CB14 SW T8, 80(SP)\r
+BFD0469C C9F3 SW T7, 76(SP)\r
+BFD0469E C9D2 SW T6, 72(SP)\r
+BFD046A0 C9B1 SW T5, 68(SP)\r
+BFD046A2 C990 SW T4, 64(SP)\r
+BFD046A4 C96F SW T3, 60(SP)\r
+BFD046A6 C94E SW T2, 56(SP)\r
+BFD046A8 C92D SW T1, 52(SP)\r
+BFD046AA C90C SW T0, 48(SP)\r
+BFD046AC C8EB SW A3, 44(SP)\r
+BFD046AE C8CA SW A2, 40(SP)\r
+BFD046B0 C8A9 SW A1, 36(SP)\r
+BFD046B2 C888 SW A0, 32(SP)\r
+BFD046B4 C825 SW AT, 20(SP)\r
+BFD046B6 4642 MFLO V0\r
+BFD046B8 C859 SW V0, 100(SP)\r
+BFD046BA 4603 MFHI V1\r
+BFD046BC C878 SW V1, 96(SP)\r
+BFD046BE 0FDD MOVE S8, SP\r
152: \r
153: _CP0_BIC_CAUSE(0x100ul);\r
-BFD046C0 01003040 ADDIU V0, ZERO, 256
-BFD046C2 006D0100 PRECR.QB.PH ZERO, ZERO, T0
-BFD046C4 00FC006D MFC0 V1, Cause
-BFD046C6 0C0000FC SLL A3, GP, 1
-BFD046C8 0C00 NOP
-BFD046CA 4412 NOT16 V0, V0
-BFD046CC 4493 AND16 V0, V1
-BFD046CE 02FC004D MTC0 V0, Cause
-BFD046D0 000002FC SLL S7, GP, 0
-BFD046D2 18000000 SLL ZERO, ZERO, 3
-BFD046D4 EE101800 SB ZERO, -4592(ZERO)
+BFD046C0 01003040 ADDIU V0, ZERO, 256\r
+BFD046C2 006D0100 PRECR.QB.PH ZERO, ZERO, T0\r
+BFD046C4 00FC006D MFC0 V1, Cause\r
+BFD046C6 0C0000FC SLL A3, GP, 1\r
+BFD046C8 0C00 NOP\r
+BFD046CA 4412 NOT16 V0, V0\r
+BFD046CC 4493 AND16 V0, V1\r
+BFD046CE 02FC004D MTC0 V0, Cause\r
+BFD046D0 000002FC SLL S7, GP, 0\r
+BFD046D2 18000000 SLL ZERO, ZERO, 3\r
+BFD046D4 EE101800 SB ZERO, -4592(ZERO)\r
154: \r
155: jtvic_clr_source(MEC14xx_GIRQ24_ID, 1);\r
-BFD046D6 EE10 LI A0, 16
-BFD046D8 EE81 LI A1, 1
-BFD046DA 44FA77E8 JALS jtvic_clr_source
-BFD046DC 44FA OR16 A3, V0
-BFD046DE 0C00 NOP
+BFD046D6 EE10 LI A0, 16\r
+BFD046D8 EE81 LI A1, 1\r
+BFD046DA 44FA77E8 JALS jtvic_clr_source\r
+BFD046DC 44FA OR16 A3, V0\r
+BFD046DE 0C00 NOP\r
156: }\r
-BFD046E0 0FBE MOVE SP, S8
-BFD046E2 4859 LW V0, 100(SP)
-BFD046E4 3D7C0002 MTLO V0
-BFD046E6 48783D7C LH T3, 18552(GP)
-BFD046E8 4878 LW V1, 96(SP)
-BFD046EA 2D7C0003 MTHI V1
-BFD046EC 2D7C ANDI V0, A3, 0x40
-BFD046EE 485C LW V0, 112(SP)
-BFD046F0 2D27 ANDI V0, V0, 0xF
-BFD046F2 001340A2 BNEZC V0, 0xBFD0471C
-BFD046F6 4BF7 LW RA, 92(SP)
-BFD046F8 4BD6 LW S8, 88(SP)
-BFD046FA 4B35 LW T9, 84(SP)
-BFD046FC 4B14 LW T8, 80(SP)
-BFD046FE 49F3 LW T7, 76(SP)
-BFD04700 49D2 LW T6, 72(SP)
-BFD04702 49B1 LW T5, 68(SP)
-BFD04704 4990 LW T4, 64(SP)
-BFD04706 496F LW T3, 60(SP)
-BFD04708 494E LW T2, 56(SP)
-BFD0470A 492D LW T1, 52(SP)
-BFD0470C 490C LW T0, 48(SP)
-BFD0470E 48EB LW A3, 44(SP)
-BFD04710 48CA LW A2, 40(SP)
-BFD04712 48A9 LW A1, 36(SP)
-BFD04714 4888 LW A0, 32(SP)
-BFD04716 4867 LW V1, 28(SP)
-BFD04718 4846 LW V0, 24(SP)
-BFD0471A 4825 LW AT, 20(SP)
-BFD0471C 477C0000 DI ZERO
-BFD04720 18000000 SLL ZERO, ZERO, 3
-BFD04722 4B5D1800 SB ZERO, 19293(ZERO)
-BFD04724 4B5D LW K0, 116(SP)
-BFD04726 4B7B LW K1, 108(SP)
-BFD04728 02FC034E MTC0 K0, EPC
-BFD0472C 4B5C LW K0, 112(SP)
-BFD0472E 4C3D ADDIU SP, SP, 120
-BFD04730 12FC034C MTC0 K0, SRSCtl
-BFD04732 03BD12FC ADDI S7, GP, 957
-BFD04734 F17C03BD WRPGPR SP, SP
-BFD04736 036CF17C JALX 0xBDF00DB0
-BFD04738 02FC036C MTC0 K1, Status
-BFD0473A 000002FC SLL S7, GP, 0
-BFD0473C F37C0000 ERET
-BFD0473E 03BDF37C JALX 0xBDF00EF4
+BFD046E0 0FBE MOVE SP, S8\r
+BFD046E2 4859 LW V0, 100(SP)\r
+BFD046E4 3D7C0002 MTLO V0\r
+BFD046E6 48783D7C LH T3, 18552(GP)\r
+BFD046E8 4878 LW V1, 96(SP)\r
+BFD046EA 2D7C0003 MTHI V1\r
+BFD046EC 2D7C ANDI V0, A3, 0x40\r
+BFD046EE 485C LW V0, 112(SP)\r
+BFD046F0 2D27 ANDI V0, V0, 0xF\r
+BFD046F2 001340A2 BNEZC V0, 0xBFD0471C\r
+BFD046F6 4BF7 LW RA, 92(SP)\r
+BFD046F8 4BD6 LW S8, 88(SP)\r
+BFD046FA 4B35 LW T9, 84(SP)\r
+BFD046FC 4B14 LW T8, 80(SP)\r
+BFD046FE 49F3 LW T7, 76(SP)\r
+BFD04700 49D2 LW T6, 72(SP)\r
+BFD04702 49B1 LW T5, 68(SP)\r
+BFD04704 4990 LW T4, 64(SP)\r
+BFD04706 496F LW T3, 60(SP)\r
+BFD04708 494E LW T2, 56(SP)\r
+BFD0470A 492D LW T1, 52(SP)\r
+BFD0470C 490C LW T0, 48(SP)\r
+BFD0470E 48EB LW A3, 44(SP)\r
+BFD04710 48CA LW A2, 40(SP)\r
+BFD04712 48A9 LW A1, 36(SP)\r
+BFD04714 4888 LW A0, 32(SP)\r
+BFD04716 4867 LW V1, 28(SP)\r
+BFD04718 4846 LW V0, 24(SP)\r
+BFD0471A 4825 LW AT, 20(SP)\r
+BFD0471C 477C0000 DI ZERO\r
+BFD04720 18000000 SLL ZERO, ZERO, 3\r
+BFD04722 4B5D1800 SB ZERO, 19293(ZERO)\r
+BFD04724 4B5D LW K0, 116(SP)\r
+BFD04726 4B7B LW K1, 108(SP)\r
+BFD04728 02FC034E MTC0 K0, EPC\r
+BFD0472C 4B5C LW K0, 112(SP)\r
+BFD0472E 4C3D ADDIU SP, SP, 120\r
+BFD04730 12FC034C MTC0 K0, SRSCtl\r
+BFD04732 03BD12FC ADDI S7, GP, 957\r
+BFD04734 F17C03BD WRPGPR SP, SP\r
+BFD04736 036CF17C JALX 0xBDF00DB0\r
+BFD04738 02FC036C MTC0 K1, Status\r
+BFD0473A 000002FC SLL S7, GP, 0\r
+BFD0473C F37C0000 ERET\r
+BFD0473E 03BDF37C JALX 0xBDF00EF4\r
157: \r
158: void __attribute__((weak, interrupt, nomips16))\r
159: girq24_b2(void)\r
160: {\r
-BFD04740 E17C03BD RDPGPR SP, SP
-BFD04744 00FC036E MFC0 K1, EPC
-BFD04746 034C00FC INS A3, GP, 13, -12
-BFD04748 10FC034C MFC0 K0, SRSCtl
-BFD0474A 4FC510FC ADDI A3, GP, 20421
-BFD0474C 4FC5 ADDIU SP, SP, -120
-BFD0474E CB7D SW K1, 116(SP)
-BFD04750 00FC036C MFC0 K1, Status
-BFD04754 CB5C SW K0, 112(SP)
-BFD04756 00FC034D MFC0 K0, Cause
-BFD0475A CB7B SW K1, 108(SP)
-BFD0475C 5040035A SRL K0, K0, 10
-BFD0475E 037A5040 ORI V0, ZERO, 890
-BFD04760 7A8C037A INS K1, K0, 10, 6
-BFD04762 03607A8C ADDIUPC A1, 787296
-BFD04764 204C0360 INS K1, ZERO, 1, 4
-BFD04766 036C204C LWC2 V0, 876(T4)
-BFD04768 02FC036C MTC0 K1, Status
-BFD0476C C867 SW V1, 28(SP)
-BFD0476E C846 SW V0, 24(SP)
-BFD04770 487C LW V1, 112(SP)
-BFD04772 2DB7 ANDI V1, V1, 0xF
-BFD04774 001140A3 BNEZC V1, 0xBFD0479A
-BFD04778 CBF7 SW RA, 92(SP)
-BFD0477A CBD6 SW S8, 88(SP)
-BFD0477C CB35 SW T9, 84(SP)
-BFD0477E CB14 SW T8, 80(SP)
-BFD04780 C9F3 SW T7, 76(SP)
-BFD04782 C9D2 SW T6, 72(SP)
-BFD04784 C9B1 SW T5, 68(SP)
-BFD04786 C990 SW T4, 64(SP)
-BFD04788 C96F SW T3, 60(SP)
-BFD0478A C94E SW T2, 56(SP)
-BFD0478C C92D SW T1, 52(SP)
-BFD0478E C90C SW T0, 48(SP)
-BFD04790 C8EB SW A3, 44(SP)
-BFD04792 C8CA SW A2, 40(SP)
-BFD04794 C8A9 SW A1, 36(SP)
-BFD04796 C888 SW A0, 32(SP)
-BFD04798 C825 SW AT, 20(SP)
-BFD0479A 4642 MFLO V0
-BFD0479C C859 SW V0, 100(SP)
-BFD0479E 4603 MFHI V1
-BFD047A0 C878 SW V1, 96(SP)
-BFD047A2 0FDD MOVE S8, SP
+BFD04740 E17C03BD RDPGPR SP, SP\r
+BFD04744 00FC036E MFC0 K1, EPC\r
+BFD04746 034C00FC INS A3, GP, 13, -12\r
+BFD04748 10FC034C MFC0 K0, SRSCtl\r
+BFD0474A 4FC510FC ADDI A3, GP, 20421\r
+BFD0474C 4FC5 ADDIU SP, SP, -120\r
+BFD0474E CB7D SW K1, 116(SP)\r
+BFD04750 00FC036C MFC0 K1, Status\r
+BFD04754 CB5C SW K0, 112(SP)\r
+BFD04756 00FC034D MFC0 K0, Cause\r
+BFD0475A CB7B SW K1, 108(SP)\r
+BFD0475C 5040035A SRL K0, K0, 10\r
+BFD0475E 037A5040 ORI V0, ZERO, 890\r
+BFD04760 7A8C037A INS K1, K0, 10, 6\r
+BFD04762 03607A8C ADDIUPC A1, 787296\r
+BFD04764 204C0360 INS K1, ZERO, 1, 4\r
+BFD04766 036C204C LWC2 V0, 876(T4)\r
+BFD04768 02FC036C MTC0 K1, Status\r
+BFD0476C C867 SW V1, 28(SP)\r
+BFD0476E C846 SW V0, 24(SP)\r
+BFD04770 487C LW V1, 112(SP)\r
+BFD04772 2DB7 ANDI V1, V1, 0xF\r
+BFD04774 001140A3 BNEZC V1, 0xBFD0479A\r
+BFD04778 CBF7 SW RA, 92(SP)\r
+BFD0477A CBD6 SW S8, 88(SP)\r
+BFD0477C CB35 SW T9, 84(SP)\r
+BFD0477E CB14 SW T8, 80(SP)\r
+BFD04780 C9F3 SW T7, 76(SP)\r
+BFD04782 C9D2 SW T6, 72(SP)\r
+BFD04784 C9B1 SW T5, 68(SP)\r
+BFD04786 C990 SW T4, 64(SP)\r
+BFD04788 C96F SW T3, 60(SP)\r
+BFD0478A C94E SW T2, 56(SP)\r
+BFD0478C C92D SW T1, 52(SP)\r
+BFD0478E C90C SW T0, 48(SP)\r
+BFD04790 C8EB SW A3, 44(SP)\r
+BFD04792 C8CA SW A2, 40(SP)\r
+BFD04794 C8A9 SW A1, 36(SP)\r
+BFD04796 C888 SW A0, 32(SP)\r
+BFD04798 C825 SW AT, 20(SP)\r
+BFD0479A 4642 MFLO V0\r
+BFD0479C C859 SW V0, 100(SP)\r
+BFD0479E 4603 MFHI V1\r
+BFD047A0 C878 SW V1, 96(SP)\r
+BFD047A2 0FDD MOVE S8, SP\r
161: \r
162: _CP0_BIC_CAUSE(0x200ul);\r
-BFD047A4 02003040 ADDIU V0, ZERO, 512
-BFD047A6 006D0200 PRECR.QB.PH ZERO, ZERO, S0
-BFD047A8 00FC006D MFC0 V1, Cause
-BFD047AA 0C0000FC SLL A3, GP, 1
-BFD047AC 0C00 NOP
-BFD047AE 4412 NOT16 V0, V0
-BFD047B0 4493 AND16 V0, V1
-BFD047B2 02FC004D MTC0 V0, Cause
-BFD047B4 000002FC SLL S7, GP, 0
-BFD047B6 18000000 SLL ZERO, ZERO, 3
-BFD047B8 EE101800 SB ZERO, -4592(ZERO)
+BFD047A4 02003040 ADDIU V0, ZERO, 512\r
+BFD047A6 006D0200 PRECR.QB.PH ZERO, ZERO, S0\r
+BFD047A8 00FC006D MFC0 V1, Cause\r
+BFD047AA 0C0000FC SLL A3, GP, 1\r
+BFD047AC 0C00 NOP\r
+BFD047AE 4412 NOT16 V0, V0\r
+BFD047B0 4493 AND16 V0, V1\r
+BFD047B2 02FC004D MTC0 V0, Cause\r
+BFD047B4 000002FC SLL S7, GP, 0\r
+BFD047B6 18000000 SLL ZERO, ZERO, 3\r
+BFD047B8 EE101800 SB ZERO, -4592(ZERO)\r
163: \r
164: jtvic_clr_source(MEC14xx_GIRQ24_ID, 2);\r
-BFD047BA EE10 LI A0, 16
-BFD047BC EE82 LI A1, 2
-BFD047BE 44FA77E8 JALS jtvic_clr_source
-BFD047C0 44FA OR16 A3, V0
-BFD047C2 0C00 NOP
+BFD047BA EE10 LI A0, 16\r
+BFD047BC EE82 LI A1, 2\r
+BFD047BE 44FA77E8 JALS jtvic_clr_source\r
+BFD047C0 44FA OR16 A3, V0\r
+BFD047C2 0C00 NOP\r
165: }\r
-BFD047C4 0FBE MOVE SP, S8
-BFD047C6 4859 LW V0, 100(SP)
-BFD047C8 3D7C0002 MTLO V0
-BFD047CA 48783D7C LH T3, 18552(GP)
-BFD047CC 4878 LW V1, 96(SP)
-BFD047CE 2D7C0003 MTHI V1
-BFD047D0 2D7C ANDI V0, A3, 0x40
-BFD047D2 485C LW V0, 112(SP)
-BFD047D4 2D27 ANDI V0, V0, 0xF
-BFD047D6 001340A2 BNEZC V0, 0xBFD04800
-BFD047DA 4BF7 LW RA, 92(SP)
-BFD047DC 4BD6 LW S8, 88(SP)
-BFD047DE 4B35 LW T9, 84(SP)
-BFD047E0 4B14 LW T8, 80(SP)
-BFD047E2 49F3 LW T7, 76(SP)
-BFD047E4 49D2 LW T6, 72(SP)
-BFD047E6 49B1 LW T5, 68(SP)
-BFD047E8 4990 LW T4, 64(SP)
-BFD047EA 496F LW T3, 60(SP)
-BFD047EC 494E LW T2, 56(SP)
-BFD047EE 492D LW T1, 52(SP)
-BFD047F0 490C LW T0, 48(SP)
-BFD047F2 48EB LW A3, 44(SP)
-BFD047F4 48CA LW A2, 40(SP)
-BFD047F6 48A9 LW A1, 36(SP)
-BFD047F8 4888 LW A0, 32(SP)
-BFD047FA 4867 LW V1, 28(SP)
-BFD047FC 4846 LW V0, 24(SP)
-BFD047FE 4825 LW AT, 20(SP)
-BFD04800 477C0000 DI ZERO
-BFD04804 18000000 SLL ZERO, ZERO, 3
-BFD04806 4B5D1800 SB ZERO, 19293(ZERO)
-BFD04808 4B5D LW K0, 116(SP)
-BFD0480A 4B7B LW K1, 108(SP)
-BFD0480C 02FC034E MTC0 K0, EPC
-BFD04810 4B5C LW K0, 112(SP)
-BFD04812 4C3D ADDIU SP, SP, 120
-BFD04814 12FC034C MTC0 K0, SRSCtl
-BFD04816 03BD12FC ADDI S7, GP, 957
-BFD04818 F17C03BD WRPGPR SP, SP
-BFD0481A 036CF17C JALX 0xBDF00DB0
-BFD0481C 02FC036C MTC0 K1, Status
-BFD0481E 000002FC SLL S7, GP, 0
-BFD04820 F37C0000 ERET
-BFD04822 4FEDF37C JALX 0xBDF13FB4
+BFD047C4 0FBE MOVE SP, S8\r
+BFD047C6 4859 LW V0, 100(SP)\r
+BFD047C8 3D7C0002 MTLO V0\r
+BFD047CA 48783D7C LH T3, 18552(GP)\r
+BFD047CC 4878 LW V1, 96(SP)\r
+BFD047CE 2D7C0003 MTHI V1\r
+BFD047D0 2D7C ANDI V0, A3, 0x40\r
+BFD047D2 485C LW V0, 112(SP)\r
+BFD047D4 2D27 ANDI V0, V0, 0xF\r
+BFD047D6 001340A2 BNEZC V0, 0xBFD04800\r
+BFD047DA 4BF7 LW RA, 92(SP)\r
+BFD047DC 4BD6 LW S8, 88(SP)\r
+BFD047DE 4B35 LW T9, 84(SP)\r
+BFD047E0 4B14 LW T8, 80(SP)\r
+BFD047E2 49F3 LW T7, 76(SP)\r
+BFD047E4 49D2 LW T6, 72(SP)\r
+BFD047E6 49B1 LW T5, 68(SP)\r
+BFD047E8 4990 LW T4, 64(SP)\r
+BFD047EA 496F LW T3, 60(SP)\r
+BFD047EC 494E LW T2, 56(SP)\r
+BFD047EE 492D LW T1, 52(SP)\r
+BFD047F0 490C LW T0, 48(SP)\r
+BFD047F2 48EB LW A3, 44(SP)\r
+BFD047F4 48CA LW A2, 40(SP)\r
+BFD047F6 48A9 LW A1, 36(SP)\r
+BFD047F8 4888 LW A0, 32(SP)\r
+BFD047FA 4867 LW V1, 28(SP)\r
+BFD047FC 4846 LW V0, 24(SP)\r
+BFD047FE 4825 LW AT, 20(SP)\r
+BFD04800 477C0000 DI ZERO\r
+BFD04804 18000000 SLL ZERO, ZERO, 3\r
+BFD04806 4B5D1800 SB ZERO, 19293(ZERO)\r
+BFD04808 4B5D LW K0, 116(SP)\r
+BFD0480A 4B7B LW K1, 108(SP)\r
+BFD0480C 02FC034E MTC0 K0, EPC\r
+BFD04810 4B5C LW K0, 112(SP)\r
+BFD04812 4C3D ADDIU SP, SP, 120\r
+BFD04814 12FC034C MTC0 K0, SRSCtl\r
+BFD04816 03BD12FC ADDI S7, GP, 957\r
+BFD04818 F17C03BD WRPGPR SP, SP\r
+BFD0481A 036CF17C JALX 0xBDF00DB0\r
+BFD0481C 02FC036C MTC0 K1, Status\r
+BFD0481E 000002FC SLL S7, GP, 0\r
+BFD04820 F37C0000 ERET\r
+BFD04822 4FEDF37C JALX 0xBDF13FB4\r
166: \r
167: #endif\r
168: \r
170: /** @}\r
171: */\r
172: \r
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq23.c ----
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq23.c ----\r
1: /*****************************************************************************\r
2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
3: * You may use this software and any derivatives exclusively with\r
150: void __attribute__((weak, interrupt, nomips16))\r
151: girq23_b0(void)\r
152: {\r
-BFD072A0 E17C03BD RDPGPR SP, SP
-BFD072A4 00FC036E MFC0 K1, EPC
-BFD072A6 034C00FC INS A3, GP, 13, -12
-BFD072A8 10FC034C MFC0 K0, SRSCtl
-BFD072AA 4FF110FC ADDI A3, GP, 20465
-BFD072AC 4FF1 ADDIU SP, SP, -32
-BFD072AE CB67 SW K1, 28(SP)
-BFD072B0 00FC036C MFC0 K1, Status
-BFD072B4 CB46 SW K0, 24(SP)
-BFD072B6 00FC034D MFC0 K0, Cause
-BFD072BA CB65 SW K1, 20(SP)
-BFD072BC 5040035A SRL K0, K0, 10
-BFD072BE 037A5040 ORI V0, ZERO, 890
-BFD072C0 7A8C037A INS K1, K0, 10, 6
-BFD072C2 03607A8C ADDIUPC A1, 787296
-BFD072C4 204C0360 INS K1, ZERO, 1, 4
-BFD072C6 036C204C LWC2 V0, 876(T4)
-BFD072C8 02FC036C MTC0 K1, Status
-BFD072CC C862 SW V1, 8(SP)
-BFD072CE C841 SW V0, 4(SP)
-BFD072D0 4866 LW V1, 24(SP)
-BFD072D2 2DB7 ANDI V1, V1, 0xF
-BFD072D4 CBC3 SW S8, 12(SP)
-BFD072D6 0FDD MOVE S8, SP
+BFD072A0 E17C03BD RDPGPR SP, SP\r
+BFD072A4 00FC036E MFC0 K1, EPC\r
+BFD072A6 034C00FC INS A3, GP, 13, -12\r
+BFD072A8 10FC034C MFC0 K0, SRSCtl\r
+BFD072AA 4FF110FC ADDI A3, GP, 20465\r
+BFD072AC 4FF1 ADDIU SP, SP, -32\r
+BFD072AE CB67 SW K1, 28(SP)\r
+BFD072B0 00FC036C MFC0 K1, Status\r
+BFD072B4 CB46 SW K0, 24(SP)\r
+BFD072B6 00FC034D MFC0 K0, Cause\r
+BFD072BA CB65 SW K1, 20(SP)\r
+BFD072BC 5040035A SRL K0, K0, 10\r
+BFD072BE 037A5040 ORI V0, ZERO, 890\r
+BFD072C0 7A8C037A INS K1, K0, 10, 6\r
+BFD072C2 03607A8C ADDIUPC A1, 787296\r
+BFD072C4 204C0360 INS K1, ZERO, 1, 4\r
+BFD072C6 036C204C LWC2 V0, 876(T4)\r
+BFD072C8 02FC036C MTC0 K1, Status\r
+BFD072CC C862 SW V1, 8(SP)\r
+BFD072CE C841 SW V0, 4(SP)\r
+BFD072D0 4866 LW V1, 24(SP)\r
+BFD072D2 2DB7 ANDI V1, V1, 0xF\r
+BFD072D4 CBC3 SW S8, 12(SP)\r
+BFD072D6 0FDD MOVE S8, SP\r
153: JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].SOURCE = (1ul << 0); \r
-BFD072D8 BFFF41A2 LUI V0, 0xBFFF
-BFD072DA 5042BFFF LDC1 F31, 20546(RA)
-BFD072DC C0005042 ORI V0, V0, -16384
-BFD072E0 ED81 LI V1, 1
-BFD072E2 00F0F862 SW V1, 240(V0)
+BFD072D8 BFFF41A2 LUI V0, 0xBFFF\r
+BFD072DA 5042BFFF LDC1 F31, 20546(RA)\r
+BFD072DC C0005042 ORI V0, V0, -16384\r
+BFD072E0 ED81 LI V1, 1\r
+BFD072E2 00F0F862 SW V1, 240(V0)\r
154: }\r
-BFD072E6 0FBE MOVE SP, S8
-BFD072E8 4846 LW V0, 24(SP)
-BFD072EA 2D27 ANDI V0, V0, 0xF
-BFD072EC 4BC3 LW S8, 12(SP)
-BFD072EE 4862 LW V1, 8(SP)
-BFD072F0 4841 LW V0, 4(SP)
-BFD072F2 477C0000 DI ZERO
-BFD072F6 18000000 SLL ZERO, ZERO, 3
-BFD072F8 4B471800 SB ZERO, 19271(ZERO)
-BFD072FA 4B47 LW K0, 28(SP)
-BFD072FC 4B65 LW K1, 20(SP)
-BFD072FE 02FC034E MTC0 K0, EPC
-BFD07302 4B46 LW K0, 24(SP)
-BFD07304 4C11 ADDIU SP, SP, 32
-BFD07306 12FC034C MTC0 K0, SRSCtl
-BFD07308 03BD12FC ADDI S7, GP, 957
-BFD0730A F17C03BD WRPGPR SP, SP
-BFD0730C 036CF17C JALX 0xBDF00DB0
-BFD0730E 02FC036C MTC0 K1, Status
-BFD07310 000002FC SLL S7, GP, 0
-BFD07312 F37C0000 ERET
-BFD07314 0C00F37C JALX 0xBDF03000
+BFD072E6 0FBE MOVE SP, S8\r
+BFD072E8 4846 LW V0, 24(SP)\r
+BFD072EA 2D27 ANDI V0, V0, 0xF\r
+BFD072EC 4BC3 LW S8, 12(SP)\r
+BFD072EE 4862 LW V1, 8(SP)\r
+BFD072F0 4841 LW V0, 4(SP)\r
+BFD072F2 477C0000 DI ZERO\r
+BFD072F6 18000000 SLL ZERO, ZERO, 3\r
+BFD072F8 4B471800 SB ZERO, 19271(ZERO)\r
+BFD072FA 4B47 LW K0, 28(SP)\r
+BFD072FC 4B65 LW K1, 20(SP)\r
+BFD072FE 02FC034E MTC0 K0, EPC\r
+BFD07302 4B46 LW K0, 24(SP)\r
+BFD07304 4C11 ADDIU SP, SP, 32\r
+BFD07306 12FC034C MTC0 K0, SRSCtl\r
+BFD07308 03BD12FC ADDI S7, GP, 957\r
+BFD0730A F17C03BD WRPGPR SP, SP\r
+BFD0730C 036CF17C JALX 0xBDF00DB0\r
+BFD0730E 02FC036C MTC0 K1, Status\r
+BFD07310 000002FC SLL S7, GP, 0\r
+BFD07312 F37C0000 ERET\r
+BFD07314 0C00F37C JALX 0xBDF03000\r
155: \r
156: /* 16-bit Basic Timer 1 */\r
157: void __attribute__((weak, interrupt, nomips16))\r
158: girq23_b1(void)\r
159: {\r
-BFD04C70 E17C03BD RDPGPR SP, SP
-BFD04C74 00FC036E MFC0 K1, EPC
-BFD04C76 034C00FC INS A3, GP, 13, -12
-BFD04C78 10FC034C MFC0 K0, SRSCtl
-BFD04C7A 4FC510FC ADDI A3, GP, 20421
-BFD04C7C 4FC5 ADDIU SP, SP, -120
-BFD04C7E CB7D SW K1, 116(SP)
-BFD04C80 00FC036C MFC0 K1, Status
-BFD04C84 CB5C SW K0, 112(SP)
-BFD04C86 00FC034D MFC0 K0, Cause
-BFD04C8A CB7B SW K1, 108(SP)
-BFD04C8C 5040035A SRL K0, K0, 10
-BFD04C8E 037A5040 ORI V0, ZERO, 890
-BFD04C90 7A8C037A INS K1, K0, 10, 6
-BFD04C92 03607A8C ADDIUPC A1, 787296
-BFD04C94 204C0360 INS K1, ZERO, 1, 4
-BFD04C96 036C204C LWC2 V0, 876(T4)
-BFD04C98 02FC036C MTC0 K1, Status
-BFD04C9C C867 SW V1, 28(SP)
-BFD04C9E C846 SW V0, 24(SP)
-BFD04CA0 487C LW V1, 112(SP)
-BFD04CA2 2DB7 ANDI V1, V1, 0xF
-BFD04CA4 001140A3 BNEZC V1, 0xBFD04CCA
-BFD04CA8 CBF7 SW RA, 92(SP)
-BFD04CAA CBD6 SW S8, 88(SP)
-BFD04CAC CB35 SW T9, 84(SP)
-BFD04CAE CB14 SW T8, 80(SP)
-BFD04CB0 C9F3 SW T7, 76(SP)
-BFD04CB2 C9D2 SW T6, 72(SP)
-BFD04CB4 C9B1 SW T5, 68(SP)
-BFD04CB6 C990 SW T4, 64(SP)
-BFD04CB8 C96F SW T3, 60(SP)
-BFD04CBA C94E SW T2, 56(SP)
-BFD04CBC C92D SW T1, 52(SP)
-BFD04CBE C90C SW T0, 48(SP)
-BFD04CC0 C8EB SW A3, 44(SP)
-BFD04CC2 C8CA SW A2, 40(SP)
-BFD04CC4 C8A9 SW A1, 36(SP)
-BFD04CC6 C888 SW A0, 32(SP)
-BFD04CC8 C825 SW AT, 20(SP)
-BFD04CCA 4642 MFLO V0
-BFD04CCC C859 SW V0, 100(SP)
-BFD04CCE 4603 MFHI V1
-BFD04CD0 C878 SW V1, 96(SP)
-BFD04CD2 0FDD MOVE S8, SP
+BFD04C70 E17C03BD RDPGPR SP, SP\r
+BFD04C74 00FC036E MFC0 K1, EPC\r
+BFD04C76 034C00FC INS A3, GP, 13, -12\r
+BFD04C78 10FC034C MFC0 K0, SRSCtl\r
+BFD04C7A 4FC510FC ADDI A3, GP, 20421\r
+BFD04C7C 4FC5 ADDIU SP, SP, -120\r
+BFD04C7E CB7D SW K1, 116(SP)\r
+BFD04C80 00FC036C MFC0 K1, Status\r
+BFD04C84 CB5C SW K0, 112(SP)\r
+BFD04C86 00FC034D MFC0 K0, Cause\r
+BFD04C8A CB7B SW K1, 108(SP)\r
+BFD04C8C 5040035A SRL K0, K0, 10\r
+BFD04C8E 037A5040 ORI V0, ZERO, 890\r
+BFD04C90 7A8C037A INS K1, K0, 10, 6\r
+BFD04C92 03607A8C ADDIUPC A1, 787296\r
+BFD04C94 204C0360 INS K1, ZERO, 1, 4\r
+BFD04C96 036C204C LWC2 V0, 876(T4)\r
+BFD04C98 02FC036C MTC0 K1, Status\r
+BFD04C9C C867 SW V1, 28(SP)\r
+BFD04C9E C846 SW V0, 24(SP)\r
+BFD04CA0 487C LW V1, 112(SP)\r
+BFD04CA2 2DB7 ANDI V1, V1, 0xF\r
+BFD04CA4 001140A3 BNEZC V1, 0xBFD04CCA\r
+BFD04CA8 CBF7 SW RA, 92(SP)\r
+BFD04CAA CBD6 SW S8, 88(SP)\r
+BFD04CAC CB35 SW T9, 84(SP)\r
+BFD04CAE CB14 SW T8, 80(SP)\r
+BFD04CB0 C9F3 SW T7, 76(SP)\r
+BFD04CB2 C9D2 SW T6, 72(SP)\r
+BFD04CB4 C9B1 SW T5, 68(SP)\r
+BFD04CB6 C990 SW T4, 64(SP)\r
+BFD04CB8 C96F SW T3, 60(SP)\r
+BFD04CBA C94E SW T2, 56(SP)\r
+BFD04CBC C92D SW T1, 52(SP)\r
+BFD04CBE C90C SW T0, 48(SP)\r
+BFD04CC0 C8EB SW A3, 44(SP)\r
+BFD04CC2 C8CA SW A2, 40(SP)\r
+BFD04CC4 C8A9 SW A1, 36(SP)\r
+BFD04CC6 C888 SW A0, 32(SP)\r
+BFD04CC8 C825 SW AT, 20(SP)\r
+BFD04CCA 4642 MFLO V0\r
+BFD04CCC C859 SW V0, 100(SP)\r
+BFD04CCE 4603 MFHI V1\r
+BFD04CD0 C878 SW V1, 96(SP)\r
+BFD04CD2 0FDD MOVE S8, SP\r
160: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 1, TRUE);\r
-BFD04CD4 EE0F LI A0, 15
-BFD04CD6 EE81 LI A1, 1
-BFD04CD8 EF01 LI A2, 1
-BFD04CDA 3A4077E8 JALS jtvic_dis_clr_source
-BFD04CDC 0C003A40 SH S2, 3072(ZERO)
-BFD04CDE 0C00 NOP
+BFD04CD4 EE0F LI A0, 15\r
+BFD04CD6 EE81 LI A1, 1\r
+BFD04CD8 EF01 LI A2, 1\r
+BFD04CDA 3A4077E8 JALS jtvic_dis_clr_source\r
+BFD04CDC 0C003A40 SH S2, 3072(ZERO)\r
+BFD04CDE 0C00 NOP\r
161: }\r
-BFD04CE0 0FBE MOVE SP, S8
-BFD04CE2 4859 LW V0, 100(SP)
-BFD04CE4 3D7C0002 MTLO V0
-BFD04CE6 48783D7C LH T3, 18552(GP)
-BFD04CE8 4878 LW V1, 96(SP)
-BFD04CEA 2D7C0003 MTHI V1
-BFD04CEC 2D7C ANDI V0, A3, 0x40
-BFD04CEE 485C LW V0, 112(SP)
-BFD04CF0 2D27 ANDI V0, V0, 0xF
-BFD04CF2 001340A2 BNEZC V0, 0xBFD04D1C
-BFD04CF6 4BF7 LW RA, 92(SP)
-BFD04CF8 4BD6 LW S8, 88(SP)
-BFD04CFA 4B35 LW T9, 84(SP)
-BFD04CFC 4B14 LW T8, 80(SP)
-BFD04CFE 49F3 LW T7, 76(SP)
-BFD04D00 49D2 LW T6, 72(SP)
-BFD04D02 49B1 LW T5, 68(SP)
-BFD04D04 4990 LW T4, 64(SP)
-BFD04D06 496F LW T3, 60(SP)
-BFD04D08 494E LW T2, 56(SP)
-BFD04D0A 492D LW T1, 52(SP)
-BFD04D0C 490C LW T0, 48(SP)
-BFD04D0E 48EB LW A3, 44(SP)
-BFD04D10 48CA LW A2, 40(SP)
-BFD04D12 48A9 LW A1, 36(SP)
-BFD04D14 4888 LW A0, 32(SP)
-BFD04D16 4867 LW V1, 28(SP)
-BFD04D18 4846 LW V0, 24(SP)
-BFD04D1A 4825 LW AT, 20(SP)
-BFD04D1C 477C0000 DI ZERO
-BFD04D20 18000000 SLL ZERO, ZERO, 3
-BFD04D22 4B5D1800 SB ZERO, 19293(ZERO)
-BFD04D24 4B5D LW K0, 116(SP)
-BFD04D26 4B7B LW K1, 108(SP)
-BFD04D28 02FC034E MTC0 K0, EPC
-BFD04D2C 4B5C LW K0, 112(SP)
-BFD04D2E 4C3D ADDIU SP, SP, 120
-BFD04D30 12FC034C MTC0 K0, SRSCtl
-BFD04D32 03BD12FC ADDI S7, GP, 957
-BFD04D34 F17C03BD WRPGPR SP, SP
-BFD04D36 036CF17C JALX 0xBDF00DB0
-BFD04D38 02FC036C MTC0 K1, Status
-BFD04D3A 000002FC SLL S7, GP, 0
-BFD04D3C F37C0000 ERET
-BFD04D3E 03BDF37C JALX 0xBDF00EF4
+BFD04CE0 0FBE MOVE SP, S8\r
+BFD04CE2 4859 LW V0, 100(SP)\r
+BFD04CE4 3D7C0002 MTLO V0\r
+BFD04CE6 48783D7C LH T3, 18552(GP)\r
+BFD04CE8 4878 LW V1, 96(SP)\r
+BFD04CEA 2D7C0003 MTHI V1\r
+BFD04CEC 2D7C ANDI V0, A3, 0x40\r
+BFD04CEE 485C LW V0, 112(SP)\r
+BFD04CF0 2D27 ANDI V0, V0, 0xF\r
+BFD04CF2 001340A2 BNEZC V0, 0xBFD04D1C\r
+BFD04CF6 4BF7 LW RA, 92(SP)\r
+BFD04CF8 4BD6 LW S8, 88(SP)\r
+BFD04CFA 4B35 LW T9, 84(SP)\r
+BFD04CFC 4B14 LW T8, 80(SP)\r
+BFD04CFE 49F3 LW T7, 76(SP)\r
+BFD04D00 49D2 LW T6, 72(SP)\r
+BFD04D02 49B1 LW T5, 68(SP)\r
+BFD04D04 4990 LW T4, 64(SP)\r
+BFD04D06 496F LW T3, 60(SP)\r
+BFD04D08 494E LW T2, 56(SP)\r
+BFD04D0A 492D LW T1, 52(SP)\r
+BFD04D0C 490C LW T0, 48(SP)\r
+BFD04D0E 48EB LW A3, 44(SP)\r
+BFD04D10 48CA LW A2, 40(SP)\r
+BFD04D12 48A9 LW A1, 36(SP)\r
+BFD04D14 4888 LW A0, 32(SP)\r
+BFD04D16 4867 LW V1, 28(SP)\r
+BFD04D18 4846 LW V0, 24(SP)\r
+BFD04D1A 4825 LW AT, 20(SP)\r
+BFD04D1C 477C0000 DI ZERO\r
+BFD04D20 18000000 SLL ZERO, ZERO, 3\r
+BFD04D22 4B5D1800 SB ZERO, 19293(ZERO)\r
+BFD04D24 4B5D LW K0, 116(SP)\r
+BFD04D26 4B7B LW K1, 108(SP)\r
+BFD04D28 02FC034E MTC0 K0, EPC\r
+BFD04D2C 4B5C LW K0, 112(SP)\r
+BFD04D2E 4C3D ADDIU SP, SP, 120\r
+BFD04D30 12FC034C MTC0 K0, SRSCtl\r
+BFD04D32 03BD12FC ADDI S7, GP, 957\r
+BFD04D34 F17C03BD WRPGPR SP, SP\r
+BFD04D36 036CF17C JALX 0xBDF00DB0\r
+BFD04D38 02FC036C MTC0 K1, Status\r
+BFD04D3A 000002FC SLL S7, GP, 0\r
+BFD04D3C F37C0000 ERET\r
+BFD04D3E 03BDF37C JALX 0xBDF00EF4\r
162: \r
163: /* 16-bit Basic Timer 2 */\r
164: void __attribute__((weak, interrupt, nomips16))\r
165: girq23_b2(void)\r
166: {\r
-BFD04D40 E17C03BD RDPGPR SP, SP
-BFD04D44 00FC036E MFC0 K1, EPC
-BFD04D46 034C00FC INS A3, GP, 13, -12
-BFD04D48 10FC034C MFC0 K0, SRSCtl
-BFD04D4A 4FC510FC ADDI A3, GP, 20421
-BFD04D4C 4FC5 ADDIU SP, SP, -120
-BFD04D4E CB7D SW K1, 116(SP)
-BFD04D50 00FC036C MFC0 K1, Status
-BFD04D54 CB5C SW K0, 112(SP)
-BFD04D56 00FC034D MFC0 K0, Cause
-BFD04D5A CB7B SW K1, 108(SP)
-BFD04D5C 5040035A SRL K0, K0, 10
-BFD04D5E 037A5040 ORI V0, ZERO, 890
-BFD04D60 7A8C037A INS K1, K0, 10, 6
-BFD04D62 03607A8C ADDIUPC A1, 787296
-BFD04D64 204C0360 INS K1, ZERO, 1, 4
-BFD04D66 036C204C LWC2 V0, 876(T4)
-BFD04D68 02FC036C MTC0 K1, Status
-BFD04D6C C867 SW V1, 28(SP)
-BFD04D6E C846 SW V0, 24(SP)
-BFD04D70 487C LW V1, 112(SP)
-BFD04D72 2DB7 ANDI V1, V1, 0xF
-BFD04D74 001140A3 BNEZC V1, 0xBFD04D9A
-BFD04D78 CBF7 SW RA, 92(SP)
-BFD04D7A CBD6 SW S8, 88(SP)
-BFD04D7C CB35 SW T9, 84(SP)
-BFD04D7E CB14 SW T8, 80(SP)
-BFD04D80 C9F3 SW T7, 76(SP)
-BFD04D82 C9D2 SW T6, 72(SP)
-BFD04D84 C9B1 SW T5, 68(SP)
-BFD04D86 C990 SW T4, 64(SP)
-BFD04D88 C96F SW T3, 60(SP)
-BFD04D8A C94E SW T2, 56(SP)
-BFD04D8C C92D SW T1, 52(SP)
-BFD04D8E C90C SW T0, 48(SP)
-BFD04D90 C8EB SW A3, 44(SP)
-BFD04D92 C8CA SW A2, 40(SP)
-BFD04D94 C8A9 SW A1, 36(SP)
-BFD04D96 C888 SW A0, 32(SP)
-BFD04D98 C825 SW AT, 20(SP)
-BFD04D9A 4642 MFLO V0
-BFD04D9C C859 SW V0, 100(SP)
-BFD04D9E 4603 MFHI V1
-BFD04DA0 C878 SW V1, 96(SP)
-BFD04DA2 0FDD MOVE S8, SP
+BFD04D40 E17C03BD RDPGPR SP, SP\r
+BFD04D44 00FC036E MFC0 K1, EPC\r
+BFD04D46 034C00FC INS A3, GP, 13, -12\r
+BFD04D48 10FC034C MFC0 K0, SRSCtl\r
+BFD04D4A 4FC510FC ADDI A3, GP, 20421\r
+BFD04D4C 4FC5 ADDIU SP, SP, -120\r
+BFD04D4E CB7D SW K1, 116(SP)\r
+BFD04D50 00FC036C MFC0 K1, Status\r
+BFD04D54 CB5C SW K0, 112(SP)\r
+BFD04D56 00FC034D MFC0 K0, Cause\r
+BFD04D5A CB7B SW K1, 108(SP)\r
+BFD04D5C 5040035A SRL K0, K0, 10\r
+BFD04D5E 037A5040 ORI V0, ZERO, 890\r
+BFD04D60 7A8C037A INS K1, K0, 10, 6\r
+BFD04D62 03607A8C ADDIUPC A1, 787296\r
+BFD04D64 204C0360 INS K1, ZERO, 1, 4\r
+BFD04D66 036C204C LWC2 V0, 876(T4)\r
+BFD04D68 02FC036C MTC0 K1, Status\r
+BFD04D6C C867 SW V1, 28(SP)\r
+BFD04D6E C846 SW V0, 24(SP)\r
+BFD04D70 487C LW V1, 112(SP)\r
+BFD04D72 2DB7 ANDI V1, V1, 0xF\r
+BFD04D74 001140A3 BNEZC V1, 0xBFD04D9A\r
+BFD04D78 CBF7 SW RA, 92(SP)\r
+BFD04D7A CBD6 SW S8, 88(SP)\r
+BFD04D7C CB35 SW T9, 84(SP)\r
+BFD04D7E CB14 SW T8, 80(SP)\r
+BFD04D80 C9F3 SW T7, 76(SP)\r
+BFD04D82 C9D2 SW T6, 72(SP)\r
+BFD04D84 C9B1 SW T5, 68(SP)\r
+BFD04D86 C990 SW T4, 64(SP)\r
+BFD04D88 C96F SW T3, 60(SP)\r
+BFD04D8A C94E SW T2, 56(SP)\r
+BFD04D8C C92D SW T1, 52(SP)\r
+BFD04D8E C90C SW T0, 48(SP)\r
+BFD04D90 C8EB SW A3, 44(SP)\r
+BFD04D92 C8CA SW A2, 40(SP)\r
+BFD04D94 C8A9 SW A1, 36(SP)\r
+BFD04D96 C888 SW A0, 32(SP)\r
+BFD04D98 C825 SW AT, 20(SP)\r
+BFD04D9A 4642 MFLO V0\r
+BFD04D9C C859 SW V0, 100(SP)\r
+BFD04D9E 4603 MFHI V1\r
+BFD04DA0 C878 SW V1, 96(SP)\r
+BFD04DA2 0FDD MOVE S8, SP\r
167: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 2, TRUE);\r
-BFD04DA4 EE0F LI A0, 15
-BFD04DA6 EE82 LI A1, 2
-BFD04DA8 EF01 LI A2, 1
-BFD04DAA 3A4077E8 JALS jtvic_dis_clr_source
-BFD04DAC 0C003A40 SH S2, 3072(ZERO)
-BFD04DAE 0C00 NOP
+BFD04DA4 EE0F LI A0, 15\r
+BFD04DA6 EE82 LI A1, 2\r
+BFD04DA8 EF01 LI A2, 1\r
+BFD04DAA 3A4077E8 JALS jtvic_dis_clr_source\r
+BFD04DAC 0C003A40 SH S2, 3072(ZERO)\r
+BFD04DAE 0C00 NOP\r
168: }\r
-BFD04DB0 0FBE MOVE SP, S8
-BFD04DB2 4859 LW V0, 100(SP)
-BFD04DB4 3D7C0002 MTLO V0
-BFD04DB6 48783D7C LH T3, 18552(GP)
-BFD04DB8 4878 LW V1, 96(SP)
-BFD04DBA 2D7C0003 MTHI V1
-BFD04DBC 2D7C ANDI V0, A3, 0x40
-BFD04DBE 485C LW V0, 112(SP)
-BFD04DC0 2D27 ANDI V0, V0, 0xF
-BFD04DC2 001340A2 BNEZC V0, 0xBFD04DEC
-BFD04DC6 4BF7 LW RA, 92(SP)
-BFD04DC8 4BD6 LW S8, 88(SP)
-BFD04DCA 4B35 LW T9, 84(SP)
-BFD04DCC 4B14 LW T8, 80(SP)
-BFD04DCE 49F3 LW T7, 76(SP)
-BFD04DD0 49D2 LW T6, 72(SP)
-BFD04DD2 49B1 LW T5, 68(SP)
-BFD04DD4 4990 LW T4, 64(SP)
-BFD04DD6 496F LW T3, 60(SP)
-BFD04DD8 494E LW T2, 56(SP)
-BFD04DDA 492D LW T1, 52(SP)
-BFD04DDC 490C LW T0, 48(SP)
-BFD04DDE 48EB LW A3, 44(SP)
-BFD04DE0 48CA LW A2, 40(SP)
-BFD04DE2 48A9 LW A1, 36(SP)
-BFD04DE4 4888 LW A0, 32(SP)
-BFD04DE6 4867 LW V1, 28(SP)
-BFD04DE8 4846 LW V0, 24(SP)
-BFD04DEA 4825 LW AT, 20(SP)
-BFD04DEC 477C0000 DI ZERO
-BFD04DF0 18000000 SLL ZERO, ZERO, 3
-BFD04DF2 4B5D1800 SB ZERO, 19293(ZERO)
-BFD04DF4 4B5D LW K0, 116(SP)
-BFD04DF6 4B7B LW K1, 108(SP)
-BFD04DF8 02FC034E MTC0 K0, EPC
-BFD04DFC 4B5C LW K0, 112(SP)
-BFD04DFE 4C3D ADDIU SP, SP, 120
-BFD04E00 12FC034C MTC0 K0, SRSCtl
-BFD04E02 03BD12FC ADDI S7, GP, 957
-BFD04E04 F17C03BD WRPGPR SP, SP
-BFD04E06 036CF17C JALX 0xBDF00DB0
-BFD04E08 02FC036C MTC0 K1, Status
-BFD04E0A 000002FC SLL S7, GP, 0
-BFD04E0C F37C0000 ERET
-BFD04E0E 03BDF37C JALX 0xBDF00EF4
+BFD04DB0 0FBE MOVE SP, S8\r
+BFD04DB2 4859 LW V0, 100(SP)\r
+BFD04DB4 3D7C0002 MTLO V0\r
+BFD04DB6 48783D7C LH T3, 18552(GP)\r
+BFD04DB8 4878 LW V1, 96(SP)\r
+BFD04DBA 2D7C0003 MTHI V1\r
+BFD04DBC 2D7C ANDI V0, A3, 0x40\r
+BFD04DBE 485C LW V0, 112(SP)\r
+BFD04DC0 2D27 ANDI V0, V0, 0xF\r
+BFD04DC2 001340A2 BNEZC V0, 0xBFD04DEC\r
+BFD04DC6 4BF7 LW RA, 92(SP)\r
+BFD04DC8 4BD6 LW S8, 88(SP)\r
+BFD04DCA 4B35 LW T9, 84(SP)\r
+BFD04DCC 4B14 LW T8, 80(SP)\r
+BFD04DCE 49F3 LW T7, 76(SP)\r
+BFD04DD0 49D2 LW T6, 72(SP)\r
+BFD04DD2 49B1 LW T5, 68(SP)\r
+BFD04DD4 4990 LW T4, 64(SP)\r
+BFD04DD6 496F LW T3, 60(SP)\r
+BFD04DD8 494E LW T2, 56(SP)\r
+BFD04DDA 492D LW T1, 52(SP)\r
+BFD04DDC 490C LW T0, 48(SP)\r
+BFD04DDE 48EB LW A3, 44(SP)\r
+BFD04DE0 48CA LW A2, 40(SP)\r
+BFD04DE2 48A9 LW A1, 36(SP)\r
+BFD04DE4 4888 LW A0, 32(SP)\r
+BFD04DE6 4867 LW V1, 28(SP)\r
+BFD04DE8 4846 LW V0, 24(SP)\r
+BFD04DEA 4825 LW AT, 20(SP)\r
+BFD04DEC 477C0000 DI ZERO\r
+BFD04DF0 18000000 SLL ZERO, ZERO, 3\r
+BFD04DF2 4B5D1800 SB ZERO, 19293(ZERO)\r
+BFD04DF4 4B5D LW K0, 116(SP)\r
+BFD04DF6 4B7B LW K1, 108(SP)\r
+BFD04DF8 02FC034E MTC0 K0, EPC\r
+BFD04DFC 4B5C LW K0, 112(SP)\r
+BFD04DFE 4C3D ADDIU SP, SP, 120\r
+BFD04E00 12FC034C MTC0 K0, SRSCtl\r
+BFD04E02 03BD12FC ADDI S7, GP, 957\r
+BFD04E04 F17C03BD WRPGPR SP, SP\r
+BFD04E06 036CF17C JALX 0xBDF00DB0\r
+BFD04E08 02FC036C MTC0 K1, Status\r
+BFD04E0A 000002FC SLL S7, GP, 0\r
+BFD04E0C F37C0000 ERET\r
+BFD04E0E 03BDF37C JALX 0xBDF00EF4\r
169: \r
170: /* 16-bit Basic Timer 3 */\r
171: void __attribute__((weak, interrupt, nomips16))\r
172: girq23_b3(void)\r
173: {\r
-BFD04E10 E17C03BD RDPGPR SP, SP
-BFD04E14 00FC036E MFC0 K1, EPC
-BFD04E16 034C00FC INS A3, GP, 13, -12
-BFD04E18 10FC034C MFC0 K0, SRSCtl
-BFD04E1A 4FC510FC ADDI A3, GP, 20421
-BFD04E1C 4FC5 ADDIU SP, SP, -120
-BFD04E1E CB7D SW K1, 116(SP)
-BFD04E20 00FC036C MFC0 K1, Status
-BFD04E24 CB5C SW K0, 112(SP)
-BFD04E26 00FC034D MFC0 K0, Cause
-BFD04E2A CB7B SW K1, 108(SP)
-BFD04E2C 5040035A SRL K0, K0, 10
-BFD04E2E 037A5040 ORI V0, ZERO, 890
-BFD04E30 7A8C037A INS K1, K0, 10, 6
-BFD04E32 03607A8C ADDIUPC A1, 787296
-BFD04E34 204C0360 INS K1, ZERO, 1, 4
-BFD04E36 036C204C LWC2 V0, 876(T4)
-BFD04E38 02FC036C MTC0 K1, Status
-BFD04E3C C867 SW V1, 28(SP)
-BFD04E3E C846 SW V0, 24(SP)
-BFD04E40 487C LW V1, 112(SP)
-BFD04E42 2DB7 ANDI V1, V1, 0xF
-BFD04E44 001140A3 BNEZC V1, 0xBFD04E6A
-BFD04E48 CBF7 SW RA, 92(SP)
-BFD04E4A CBD6 SW S8, 88(SP)
-BFD04E4C CB35 SW T9, 84(SP)
-BFD04E4E CB14 SW T8, 80(SP)
-BFD04E50 C9F3 SW T7, 76(SP)
-BFD04E52 C9D2 SW T6, 72(SP)
-BFD04E54 C9B1 SW T5, 68(SP)
-BFD04E56 C990 SW T4, 64(SP)
-BFD04E58 C96F SW T3, 60(SP)
-BFD04E5A C94E SW T2, 56(SP)
-BFD04E5C C92D SW T1, 52(SP)
-BFD04E5E C90C SW T0, 48(SP)
-BFD04E60 C8EB SW A3, 44(SP)
-BFD04E62 C8CA SW A2, 40(SP)
-BFD04E64 C8A9 SW A1, 36(SP)
-BFD04E66 C888 SW A0, 32(SP)
-BFD04E68 C825 SW AT, 20(SP)
-BFD04E6A 4642 MFLO V0
-BFD04E6C C859 SW V0, 100(SP)
-BFD04E6E 4603 MFHI V1
-BFD04E70 C878 SW V1, 96(SP)
-BFD04E72 0FDD MOVE S8, SP
+BFD04E10 E17C03BD RDPGPR SP, SP\r
+BFD04E14 00FC036E MFC0 K1, EPC\r
+BFD04E16 034C00FC INS A3, GP, 13, -12\r
+BFD04E18 10FC034C MFC0 K0, SRSCtl\r
+BFD04E1A 4FC510FC ADDI A3, GP, 20421\r
+BFD04E1C 4FC5 ADDIU SP, SP, -120\r
+BFD04E1E CB7D SW K1, 116(SP)\r
+BFD04E20 00FC036C MFC0 K1, Status\r
+BFD04E24 CB5C SW K0, 112(SP)\r
+BFD04E26 00FC034D MFC0 K0, Cause\r
+BFD04E2A CB7B SW K1, 108(SP)\r
+BFD04E2C 5040035A SRL K0, K0, 10\r
+BFD04E2E 037A5040 ORI V0, ZERO, 890\r
+BFD04E30 7A8C037A INS K1, K0, 10, 6\r
+BFD04E32 03607A8C ADDIUPC A1, 787296\r
+BFD04E34 204C0360 INS K1, ZERO, 1, 4\r
+BFD04E36 036C204C LWC2 V0, 876(T4)\r
+BFD04E38 02FC036C MTC0 K1, Status\r
+BFD04E3C C867 SW V1, 28(SP)\r
+BFD04E3E C846 SW V0, 24(SP)\r
+BFD04E40 487C LW V1, 112(SP)\r
+BFD04E42 2DB7 ANDI V1, V1, 0xF\r
+BFD04E44 001140A3 BNEZC V1, 0xBFD04E6A\r
+BFD04E48 CBF7 SW RA, 92(SP)\r
+BFD04E4A CBD6 SW S8, 88(SP)\r
+BFD04E4C CB35 SW T9, 84(SP)\r
+BFD04E4E CB14 SW T8, 80(SP)\r
+BFD04E50 C9F3 SW T7, 76(SP)\r
+BFD04E52 C9D2 SW T6, 72(SP)\r
+BFD04E54 C9B1 SW T5, 68(SP)\r
+BFD04E56 C990 SW T4, 64(SP)\r
+BFD04E58 C96F SW T3, 60(SP)\r
+BFD04E5A C94E SW T2, 56(SP)\r
+BFD04E5C C92D SW T1, 52(SP)\r
+BFD04E5E C90C SW T0, 48(SP)\r
+BFD04E60 C8EB SW A3, 44(SP)\r
+BFD04E62 C8CA SW A2, 40(SP)\r
+BFD04E64 C8A9 SW A1, 36(SP)\r
+BFD04E66 C888 SW A0, 32(SP)\r
+BFD04E68 C825 SW AT, 20(SP)\r
+BFD04E6A 4642 MFLO V0\r
+BFD04E6C C859 SW V0, 100(SP)\r
+BFD04E6E 4603 MFHI V1\r
+BFD04E70 C878 SW V1, 96(SP)\r
+BFD04E72 0FDD MOVE S8, SP\r
174: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 3, TRUE);\r
-BFD04E74 EE0F LI A0, 15
-BFD04E76 EE83 LI A1, 3
-BFD04E78 EF01 LI A2, 1
-BFD04E7A 3A4077E8 JALS jtvic_dis_clr_source
-BFD04E7C 0C003A40 SH S2, 3072(ZERO)
-BFD04E7E 0C00 NOP
+BFD04E74 EE0F LI A0, 15\r
+BFD04E76 EE83 LI A1, 3\r
+BFD04E78 EF01 LI A2, 1\r
+BFD04E7A 3A4077E8 JALS jtvic_dis_clr_source\r
+BFD04E7C 0C003A40 SH S2, 3072(ZERO)\r
+BFD04E7E 0C00 NOP\r
175: }\r
-BFD04E80 0FBE MOVE SP, S8
-BFD04E82 4859 LW V0, 100(SP)
-BFD04E84 3D7C0002 MTLO V0
-BFD04E86 48783D7C LH T3, 18552(GP)
-BFD04E88 4878 LW V1, 96(SP)
-BFD04E8A 2D7C0003 MTHI V1
-BFD04E8C 2D7C ANDI V0, A3, 0x40
-BFD04E8E 485C LW V0, 112(SP)
-BFD04E90 2D27 ANDI V0, V0, 0xF
-BFD04E92 001340A2 BNEZC V0, 0xBFD04EBC
-BFD04E96 4BF7 LW RA, 92(SP)
-BFD04E98 4BD6 LW S8, 88(SP)
-BFD04E9A 4B35 LW T9, 84(SP)
-BFD04E9C 4B14 LW T8, 80(SP)
-BFD04E9E 49F3 LW T7, 76(SP)
-BFD04EA0 49D2 LW T6, 72(SP)
-BFD04EA2 49B1 LW T5, 68(SP)
-BFD04EA4 4990 LW T4, 64(SP)
-BFD04EA6 496F LW T3, 60(SP)
-BFD04EA8 494E LW T2, 56(SP)
-BFD04EAA 492D LW T1, 52(SP)
-BFD04EAC 490C LW T0, 48(SP)
-BFD04EAE 48EB LW A3, 44(SP)
-BFD04EB0 48CA LW A2, 40(SP)
-BFD04EB2 48A9 LW A1, 36(SP)
-BFD04EB4 4888 LW A0, 32(SP)
-BFD04EB6 4867 LW V1, 28(SP)
-BFD04EB8 4846 LW V0, 24(SP)
-BFD04EBA 4825 LW AT, 20(SP)
-BFD04EBC 477C0000 DI ZERO
-BFD04EC0 18000000 SLL ZERO, ZERO, 3
-BFD04EC2 4B5D1800 SB ZERO, 19293(ZERO)
-BFD04EC4 4B5D LW K0, 116(SP)
-BFD04EC6 4B7B LW K1, 108(SP)
-BFD04EC8 02FC034E MTC0 K0, EPC
-BFD04ECC 4B5C LW K0, 112(SP)
-BFD04ECE 4C3D ADDIU SP, SP, 120
-BFD04ED0 12FC034C MTC0 K0, SRSCtl
-BFD04ED2 03BD12FC ADDI S7, GP, 957
-BFD04ED4 F17C03BD WRPGPR SP, SP
-BFD04ED6 036CF17C JALX 0xBDF00DB0
-BFD04ED8 02FC036C MTC0 K1, Status
-BFD04EDA 000002FC SLL S7, GP, 0
-BFD04EDC F37C0000 ERET
-BFD04EDE 03BDF37C JALX 0xBDF00EF4
+BFD04E80 0FBE MOVE SP, S8\r
+BFD04E82 4859 LW V0, 100(SP)\r
+BFD04E84 3D7C0002 MTLO V0\r
+BFD04E86 48783D7C LH T3, 18552(GP)\r
+BFD04E88 4878 LW V1, 96(SP)\r
+BFD04E8A 2D7C0003 MTHI V1\r
+BFD04E8C 2D7C ANDI V0, A3, 0x40\r
+BFD04E8E 485C LW V0, 112(SP)\r
+BFD04E90 2D27 ANDI V0, V0, 0xF\r
+BFD04E92 001340A2 BNEZC V0, 0xBFD04EBC\r
+BFD04E96 4BF7 LW RA, 92(SP)\r
+BFD04E98 4BD6 LW S8, 88(SP)\r
+BFD04E9A 4B35 LW T9, 84(SP)\r
+BFD04E9C 4B14 LW T8, 80(SP)\r
+BFD04E9E 49F3 LW T7, 76(SP)\r
+BFD04EA0 49D2 LW T6, 72(SP)\r
+BFD04EA2 49B1 LW T5, 68(SP)\r
+BFD04EA4 4990 LW T4, 64(SP)\r
+BFD04EA6 496F LW T3, 60(SP)\r
+BFD04EA8 494E LW T2, 56(SP)\r
+BFD04EAA 492D LW T1, 52(SP)\r
+BFD04EAC 490C LW T0, 48(SP)\r
+BFD04EAE 48EB LW A3, 44(SP)\r
+BFD04EB0 48CA LW A2, 40(SP)\r
+BFD04EB2 48A9 LW A1, 36(SP)\r
+BFD04EB4 4888 LW A0, 32(SP)\r
+BFD04EB6 4867 LW V1, 28(SP)\r
+BFD04EB8 4846 LW V0, 24(SP)\r
+BFD04EBA 4825 LW AT, 20(SP)\r
+BFD04EBC 477C0000 DI ZERO\r
+BFD04EC0 18000000 SLL ZERO, ZERO, 3\r
+BFD04EC2 4B5D1800 SB ZERO, 19293(ZERO)\r
+BFD04EC4 4B5D LW K0, 116(SP)\r
+BFD04EC6 4B7B LW K1, 108(SP)\r
+BFD04EC8 02FC034E MTC0 K0, EPC\r
+BFD04ECC 4B5C LW K0, 112(SP)\r
+BFD04ECE 4C3D ADDIU SP, SP, 120\r
+BFD04ED0 12FC034C MTC0 K0, SRSCtl\r
+BFD04ED2 03BD12FC ADDI S7, GP, 957\r
+BFD04ED4 F17C03BD WRPGPR SP, SP\r
+BFD04ED6 036CF17C JALX 0xBDF00DB0\r
+BFD04ED8 02FC036C MTC0 K1, Status\r
+BFD04EDA 000002FC SLL S7, GP, 0\r
+BFD04EDC F37C0000 ERET\r
+BFD04EDE 03BDF37C JALX 0xBDF00EF4\r
176: \r
177: /* RTOS Timer */\r
178: void __attribute__((weak, interrupt, nomips16))\r
179: girq23_b4(void)\r
180: {\r
-BFD07318 E17C03BD RDPGPR SP, SP
-BFD0731C 00FC036E MFC0 K1, EPC
-BFD0731E 034C00FC INS A3, GP, 13, -12
-BFD07320 10FC034C MFC0 K0, SRSCtl
-BFD07322 4FF110FC ADDI A3, GP, 20465
-BFD07324 4FF1 ADDIU SP, SP, -32
-BFD07326 CB67 SW K1, 28(SP)
-BFD07328 00FC036C MFC0 K1, Status
-BFD0732C CB46 SW K0, 24(SP)
-BFD0732E 00FC034D MFC0 K0, Cause
-BFD07332 CB65 SW K1, 20(SP)
-BFD07334 5040035A SRL K0, K0, 10
-BFD07336 037A5040 ORI V0, ZERO, 890
-BFD07338 7A8C037A INS K1, K0, 10, 6
-BFD0733A 03607A8C ADDIUPC A1, 787296
-BFD0733C 204C0360 INS K1, ZERO, 1, 4
-BFD0733E 036C204C LWC2 V0, 876(T4)
-BFD07340 02FC036C MTC0 K1, Status
-BFD07344 C862 SW V1, 8(SP)
-BFD07346 C841 SW V0, 4(SP)
-BFD07348 4866 LW V1, 24(SP)
-BFD0734A 2DB7 ANDI V1, V1, 0xF
-BFD0734C CBC3 SW S8, 12(SP)
-BFD0734E 0FDD MOVE S8, SP
+BFD07318 E17C03BD RDPGPR SP, SP\r
+BFD0731C 00FC036E MFC0 K1, EPC\r
+BFD0731E 034C00FC INS A3, GP, 13, -12\r
+BFD07320 10FC034C MFC0 K0, SRSCtl\r
+BFD07322 4FF110FC ADDI A3, GP, 20465\r
+BFD07324 4FF1 ADDIU SP, SP, -32\r
+BFD07326 CB67 SW K1, 28(SP)\r
+BFD07328 00FC036C MFC0 K1, Status\r
+BFD0732C CB46 SW K0, 24(SP)\r
+BFD0732E 00FC034D MFC0 K0, Cause\r
+BFD07332 CB65 SW K1, 20(SP)\r
+BFD07334 5040035A SRL K0, K0, 10\r
+BFD07336 037A5040 ORI V0, ZERO, 890\r
+BFD07338 7A8C037A INS K1, K0, 10, 6\r
+BFD0733A 03607A8C ADDIUPC A1, 787296\r
+BFD0733C 204C0360 INS K1, ZERO, 1, 4\r
+BFD0733E 036C204C LWC2 V0, 876(T4)\r
+BFD07340 02FC036C MTC0 K1, Status\r
+BFD07344 C862 SW V1, 8(SP)\r
+BFD07346 C841 SW V0, 4(SP)\r
+BFD07348 4866 LW V1, 24(SP)\r
+BFD0734A 2DB7 ANDI V1, V1, 0xF\r
+BFD0734C CBC3 SW S8, 12(SP)\r
+BFD0734E 0FDD MOVE S8, SP\r
181: JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].SOURCE = (1ul << 4);\r
-BFD07350 BFFF41A2 LUI V0, 0xBFFF
-BFD07352 5042BFFF LDC1 F31, 20546(RA)
-BFD07354 C0005042 ORI V0, V0, -16384
-BFD07358 ED90 LI V1, 16
-BFD0735A 00F0F862 SW V1, 240(V0)
+BFD07350 BFFF41A2 LUI V0, 0xBFFF\r
+BFD07352 5042BFFF LDC1 F31, 20546(RA)\r
+BFD07354 C0005042 ORI V0, V0, -16384\r
+BFD07358 ED90 LI V1, 16\r
+BFD0735A 00F0F862 SW V1, 240(V0)\r
182: \r
183: }\r
-BFD0735E 0FBE MOVE SP, S8
-BFD07360 4846 LW V0, 24(SP)
-BFD07362 2D27 ANDI V0, V0, 0xF
-BFD07364 4BC3 LW S8, 12(SP)
-BFD07366 4862 LW V1, 8(SP)
-BFD07368 4841 LW V0, 4(SP)
-BFD0736A 477C0000 DI ZERO
-BFD0736E 18000000 SLL ZERO, ZERO, 3
-BFD07370 4B471800 SB ZERO, 19271(ZERO)
-BFD07372 4B47 LW K0, 28(SP)
-BFD07374 4B65 LW K1, 20(SP)
-BFD07376 02FC034E MTC0 K0, EPC
-BFD0737A 4B46 LW K0, 24(SP)
-BFD0737C 4C11 ADDIU SP, SP, 32
-BFD0737E 12FC034C MTC0 K0, SRSCtl
-BFD07380 03BD12FC ADDI S7, GP, 957
-BFD07382 F17C03BD WRPGPR SP, SP
-BFD07384 036CF17C JALX 0xBDF00DB0
-BFD07386 02FC036C MTC0 K1, Status
-BFD07388 000002FC SLL S7, GP, 0
-BFD0738A F37C0000 ERET
-BFD0738C 0C00F37C JALX 0xBDF03000
+BFD0735E 0FBE MOVE SP, S8\r
+BFD07360 4846 LW V0, 24(SP)\r
+BFD07362 2D27 ANDI V0, V0, 0xF\r
+BFD07364 4BC3 LW S8, 12(SP)\r
+BFD07366 4862 LW V1, 8(SP)\r
+BFD07368 4841 LW V0, 4(SP)\r
+BFD0736A 477C0000 DI ZERO\r
+BFD0736E 18000000 SLL ZERO, ZERO, 3\r
+BFD07370 4B471800 SB ZERO, 19271(ZERO)\r
+BFD07372 4B47 LW K0, 28(SP)\r
+BFD07374 4B65 LW K1, 20(SP)\r
+BFD07376 02FC034E MTC0 K0, EPC\r
+BFD0737A 4B46 LW K0, 24(SP)\r
+BFD0737C 4C11 ADDIU SP, SP, 32\r
+BFD0737E 12FC034C MTC0 K0, SRSCtl\r
+BFD07380 03BD12FC ADDI S7, GP, 957\r
+BFD07382 F17C03BD WRPGPR SP, SP\r
+BFD07384 036CF17C JALX 0xBDF00DB0\r
+BFD07386 02FC036C MTC0 K1, Status\r
+BFD07388 000002FC SLL S7, GP, 0\r
+BFD0738A F37C0000 ERET\r
+BFD0738C 0C00F37C JALX 0xBDF03000\r
184: \r
185: /* Hibernation Timer */\r
186: void __attribute__((weak, interrupt, nomips16))\r
187: girq23_b5(void)\r
188: {\r
-BFD04EE0 E17C03BD RDPGPR SP, SP
-BFD04EE4 00FC036E MFC0 K1, EPC
-BFD04EE6 034C00FC INS A3, GP, 13, -12
-BFD04EE8 10FC034C MFC0 K0, SRSCtl
-BFD04EEA 4FC510FC ADDI A3, GP, 20421
-BFD04EEC 4FC5 ADDIU SP, SP, -120
-BFD04EEE CB7D SW K1, 116(SP)
-BFD04EF0 00FC036C MFC0 K1, Status
-BFD04EF4 CB5C SW K0, 112(SP)
-BFD04EF6 00FC034D MFC0 K0, Cause
-BFD04EFA CB7B SW K1, 108(SP)
-BFD04EFC 5040035A SRL K0, K0, 10
-BFD04EFE 037A5040 ORI V0, ZERO, 890
-BFD04F00 7A8C037A INS K1, K0, 10, 6
-BFD04F02 03607A8C ADDIUPC A1, 787296
-BFD04F04 204C0360 INS K1, ZERO, 1, 4
-BFD04F06 036C204C LWC2 V0, 876(T4)
-BFD04F08 02FC036C MTC0 K1, Status
-BFD04F0C C867 SW V1, 28(SP)
-BFD04F0E C846 SW V0, 24(SP)
-BFD04F10 487C LW V1, 112(SP)
-BFD04F12 2DB7 ANDI V1, V1, 0xF
-BFD04F14 001140A3 BNEZC V1, 0xBFD04F3A
-BFD04F18 CBF7 SW RA, 92(SP)
-BFD04F1A CBD6 SW S8, 88(SP)
-BFD04F1C CB35 SW T9, 84(SP)
-BFD04F1E CB14 SW T8, 80(SP)
-BFD04F20 C9F3 SW T7, 76(SP)
-BFD04F22 C9D2 SW T6, 72(SP)
-BFD04F24 C9B1 SW T5, 68(SP)
-BFD04F26 C990 SW T4, 64(SP)
-BFD04F28 C96F SW T3, 60(SP)
-BFD04F2A C94E SW T2, 56(SP)
-BFD04F2C C92D SW T1, 52(SP)
-BFD04F2E C90C SW T0, 48(SP)
-BFD04F30 C8EB SW A3, 44(SP)
-BFD04F32 C8CA SW A2, 40(SP)
-BFD04F34 C8A9 SW A1, 36(SP)
-BFD04F36 C888 SW A0, 32(SP)
-BFD04F38 C825 SW AT, 20(SP)
-BFD04F3A 4642 MFLO V0
-BFD04F3C C859 SW V0, 100(SP)
-BFD04F3E 4603 MFHI V1
-BFD04F40 C878 SW V1, 96(SP)
-BFD04F42 0FDD MOVE S8, SP
+BFD04EE0 E17C03BD RDPGPR SP, SP\r
+BFD04EE4 00FC036E MFC0 K1, EPC\r
+BFD04EE6 034C00FC INS A3, GP, 13, -12\r
+BFD04EE8 10FC034C MFC0 K0, SRSCtl\r
+BFD04EEA 4FC510FC ADDI A3, GP, 20421\r
+BFD04EEC 4FC5 ADDIU SP, SP, -120\r
+BFD04EEE CB7D SW K1, 116(SP)\r
+BFD04EF0 00FC036C MFC0 K1, Status\r
+BFD04EF4 CB5C SW K0, 112(SP)\r
+BFD04EF6 00FC034D MFC0 K0, Cause\r
+BFD04EFA CB7B SW K1, 108(SP)\r
+BFD04EFC 5040035A SRL K0, K0, 10\r
+BFD04EFE 037A5040 ORI V0, ZERO, 890\r
+BFD04F00 7A8C037A INS K1, K0, 10, 6\r
+BFD04F02 03607A8C ADDIUPC A1, 787296\r
+BFD04F04 204C0360 INS K1, ZERO, 1, 4\r
+BFD04F06 036C204C LWC2 V0, 876(T4)\r
+BFD04F08 02FC036C MTC0 K1, Status\r
+BFD04F0C C867 SW V1, 28(SP)\r
+BFD04F0E C846 SW V0, 24(SP)\r
+BFD04F10 487C LW V1, 112(SP)\r
+BFD04F12 2DB7 ANDI V1, V1, 0xF\r
+BFD04F14 001140A3 BNEZC V1, 0xBFD04F3A\r
+BFD04F18 CBF7 SW RA, 92(SP)\r
+BFD04F1A CBD6 SW S8, 88(SP)\r
+BFD04F1C CB35 SW T9, 84(SP)\r
+BFD04F1E CB14 SW T8, 80(SP)\r
+BFD04F20 C9F3 SW T7, 76(SP)\r
+BFD04F22 C9D2 SW T6, 72(SP)\r
+BFD04F24 C9B1 SW T5, 68(SP)\r
+BFD04F26 C990 SW T4, 64(SP)\r
+BFD04F28 C96F SW T3, 60(SP)\r
+BFD04F2A C94E SW T2, 56(SP)\r
+BFD04F2C C92D SW T1, 52(SP)\r
+BFD04F2E C90C SW T0, 48(SP)\r
+BFD04F30 C8EB SW A3, 44(SP)\r
+BFD04F32 C8CA SW A2, 40(SP)\r
+BFD04F34 C8A9 SW A1, 36(SP)\r
+BFD04F36 C888 SW A0, 32(SP)\r
+BFD04F38 C825 SW AT, 20(SP)\r
+BFD04F3A 4642 MFLO V0\r
+BFD04F3C C859 SW V0, 100(SP)\r
+BFD04F3E 4603 MFHI V1\r
+BFD04F40 C878 SW V1, 96(SP)\r
+BFD04F42 0FDD MOVE S8, SP\r
189: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 5, TRUE);\r
-BFD04F44 EE0F LI A0, 15
-BFD04F46 EE85 LI A1, 5
-BFD04F48 EF01 LI A2, 1
-BFD04F4A 3A4077E8 JALS jtvic_dis_clr_source
-BFD04F4C 0C003A40 SH S2, 3072(ZERO)
-BFD04F4E 0C00 NOP
+BFD04F44 EE0F LI A0, 15\r
+BFD04F46 EE85 LI A1, 5\r
+BFD04F48 EF01 LI A2, 1\r
+BFD04F4A 3A4077E8 JALS jtvic_dis_clr_source\r
+BFD04F4C 0C003A40 SH S2, 3072(ZERO)\r
+BFD04F4E 0C00 NOP\r
190: }\r
-BFD04F50 0FBE MOVE SP, S8
-BFD04F52 4859 LW V0, 100(SP)
-BFD04F54 3D7C0002 MTLO V0
-BFD04F56 48783D7C LH T3, 18552(GP)
-BFD04F58 4878 LW V1, 96(SP)
-BFD04F5A 2D7C0003 MTHI V1
-BFD04F5C 2D7C ANDI V0, A3, 0x40
-BFD04F5E 485C LW V0, 112(SP)
-BFD04F60 2D27 ANDI V0, V0, 0xF
-BFD04F62 001340A2 BNEZC V0, 0xBFD04F8C
-BFD04F66 4BF7 LW RA, 92(SP)
-BFD04F68 4BD6 LW S8, 88(SP)
-BFD04F6A 4B35 LW T9, 84(SP)
-BFD04F6C 4B14 LW T8, 80(SP)
-BFD04F6E 49F3 LW T7, 76(SP)
-BFD04F70 49D2 LW T6, 72(SP)
-BFD04F72 49B1 LW T5, 68(SP)
-BFD04F74 4990 LW T4, 64(SP)
-BFD04F76 496F LW T3, 60(SP)
-BFD04F78 494E LW T2, 56(SP)
-BFD04F7A 492D LW T1, 52(SP)
-BFD04F7C 490C LW T0, 48(SP)
-BFD04F7E 48EB LW A3, 44(SP)
-BFD04F80 48CA LW A2, 40(SP)
-BFD04F82 48A9 LW A1, 36(SP)
-BFD04F84 4888 LW A0, 32(SP)
-BFD04F86 4867 LW V1, 28(SP)
-BFD04F88 4846 LW V0, 24(SP)
-BFD04F8A 4825 LW AT, 20(SP)
-BFD04F8C 477C0000 DI ZERO
-BFD04F90 18000000 SLL ZERO, ZERO, 3
-BFD04F92 4B5D1800 SB ZERO, 19293(ZERO)
-BFD04F94 4B5D LW K0, 116(SP)
-BFD04F96 4B7B LW K1, 108(SP)
-BFD04F98 02FC034E MTC0 K0, EPC
-BFD04F9C 4B5C LW K0, 112(SP)
-BFD04F9E 4C3D ADDIU SP, SP, 120
-BFD04FA0 12FC034C MTC0 K0, SRSCtl
-BFD04FA2 03BD12FC ADDI S7, GP, 957
-BFD04FA4 F17C03BD WRPGPR SP, SP
-BFD04FA6 036CF17C JALX 0xBDF00DB0
-BFD04FA8 02FC036C MTC0 K1, Status
-BFD04FAA 000002FC SLL S7, GP, 0
-BFD04FAC F37C0000 ERET
-BFD04FAE 03BDF37C JALX 0xBDF00EF4
+BFD04F50 0FBE MOVE SP, S8\r
+BFD04F52 4859 LW V0, 100(SP)\r
+BFD04F54 3D7C0002 MTLO V0\r
+BFD04F56 48783D7C LH T3, 18552(GP)\r
+BFD04F58 4878 LW V1, 96(SP)\r
+BFD04F5A 2D7C0003 MTHI V1\r
+BFD04F5C 2D7C ANDI V0, A3, 0x40\r
+BFD04F5E 485C LW V0, 112(SP)\r
+BFD04F60 2D27 ANDI V0, V0, 0xF\r
+BFD04F62 001340A2 BNEZC V0, 0xBFD04F8C\r
+BFD04F66 4BF7 LW RA, 92(SP)\r
+BFD04F68 4BD6 LW S8, 88(SP)\r
+BFD04F6A 4B35 LW T9, 84(SP)\r
+BFD04F6C 4B14 LW T8, 80(SP)\r
+BFD04F6E 49F3 LW T7, 76(SP)\r
+BFD04F70 49D2 LW T6, 72(SP)\r
+BFD04F72 49B1 LW T5, 68(SP)\r
+BFD04F74 4990 LW T4, 64(SP)\r
+BFD04F76 496F LW T3, 60(SP)\r
+BFD04F78 494E LW T2, 56(SP)\r
+BFD04F7A 492D LW T1, 52(SP)\r
+BFD04F7C 490C LW T0, 48(SP)\r
+BFD04F7E 48EB LW A3, 44(SP)\r
+BFD04F80 48CA LW A2, 40(SP)\r
+BFD04F82 48A9 LW A1, 36(SP)\r
+BFD04F84 4888 LW A0, 32(SP)\r
+BFD04F86 4867 LW V1, 28(SP)\r
+BFD04F88 4846 LW V0, 24(SP)\r
+BFD04F8A 4825 LW AT, 20(SP)\r
+BFD04F8C 477C0000 DI ZERO\r
+BFD04F90 18000000 SLL ZERO, ZERO, 3\r
+BFD04F92 4B5D1800 SB ZERO, 19293(ZERO)\r
+BFD04F94 4B5D LW K0, 116(SP)\r
+BFD04F96 4B7B LW K1, 108(SP)\r
+BFD04F98 02FC034E MTC0 K0, EPC\r
+BFD04F9C 4B5C LW K0, 112(SP)\r
+BFD04F9E 4C3D ADDIU SP, SP, 120\r
+BFD04FA0 12FC034C MTC0 K0, SRSCtl\r
+BFD04FA2 03BD12FC ADDI S7, GP, 957\r
+BFD04FA4 F17C03BD WRPGPR SP, SP\r
+BFD04FA6 036CF17C JALX 0xBDF00DB0\r
+BFD04FA8 02FC036C MTC0 K1, Status\r
+BFD04FAA 000002FC SLL S7, GP, 0\r
+BFD04FAC F37C0000 ERET\r
+BFD04FAE 03BDF37C JALX 0xBDF00EF4\r
191: \r
192: /* Week Alarm */\r
193: void __attribute__((weak, interrupt, nomips16))\r
194: girq23_b6(void)\r
195: {\r
-BFD04FB0 E17C03BD RDPGPR SP, SP
-BFD04FB4 00FC036E MFC0 K1, EPC
-BFD04FB6 034C00FC INS A3, GP, 13, -12
-BFD04FB8 10FC034C MFC0 K0, SRSCtl
-BFD04FBA 4FC510FC ADDI A3, GP, 20421
-BFD04FBC 4FC5 ADDIU SP, SP, -120
-BFD04FBE CB7D SW K1, 116(SP)
-BFD04FC0 00FC036C MFC0 K1, Status
-BFD04FC4 CB5C SW K0, 112(SP)
-BFD04FC6 00FC034D MFC0 K0, Cause
-BFD04FCA CB7B SW K1, 108(SP)
-BFD04FCC 5040035A SRL K0, K0, 10
-BFD04FCE 037A5040 ORI V0, ZERO, 890
-BFD04FD0 7A8C037A INS K1, K0, 10, 6
-BFD04FD2 03607A8C ADDIUPC A1, 787296
-BFD04FD4 204C0360 INS K1, ZERO, 1, 4
-BFD04FD6 036C204C LWC2 V0, 876(T4)
-BFD04FD8 02FC036C MTC0 K1, Status
-BFD04FDC C867 SW V1, 28(SP)
-BFD04FDE C846 SW V0, 24(SP)
-BFD04FE0 487C LW V1, 112(SP)
-BFD04FE2 2DB7 ANDI V1, V1, 0xF
-BFD04FE4 001140A3 BNEZC V1, 0xBFD0500A
-BFD04FE8 CBF7 SW RA, 92(SP)
-BFD04FEA CBD6 SW S8, 88(SP)
-BFD04FEC CB35 SW T9, 84(SP)
-BFD04FEE CB14 SW T8, 80(SP)
-BFD04FF0 C9F3 SW T7, 76(SP)
-BFD04FF2 C9D2 SW T6, 72(SP)
-BFD04FF4 C9B1 SW T5, 68(SP)
-BFD04FF6 C990 SW T4, 64(SP)
-BFD04FF8 C96F SW T3, 60(SP)
-BFD04FFA C94E SW T2, 56(SP)
-BFD04FFC C92D SW T1, 52(SP)
-BFD04FFE C90C SW T0, 48(SP)
-BFD05000 C8EB SW A3, 44(SP)
-BFD05002 C8CA SW A2, 40(SP)
-BFD05004 C8A9 SW A1, 36(SP)
-BFD05006 C888 SW A0, 32(SP)
-BFD05008 C825 SW AT, 20(SP)
-BFD0500A 4642 MFLO V0
-BFD0500C C859 SW V0, 100(SP)
-BFD0500E 4603 MFHI V1
-BFD05010 C878 SW V1, 96(SP)
-BFD05012 0FDD MOVE S8, SP
+BFD04FB0 E17C03BD RDPGPR SP, SP\r
+BFD04FB4 00FC036E MFC0 K1, EPC\r
+BFD04FB6 034C00FC INS A3, GP, 13, -12\r
+BFD04FB8 10FC034C MFC0 K0, SRSCtl\r
+BFD04FBA 4FC510FC ADDI A3, GP, 20421\r
+BFD04FBC 4FC5 ADDIU SP, SP, -120\r
+BFD04FBE CB7D SW K1, 116(SP)\r
+BFD04FC0 00FC036C MFC0 K1, Status\r
+BFD04FC4 CB5C SW K0, 112(SP)\r
+BFD04FC6 00FC034D MFC0 K0, Cause\r
+BFD04FCA CB7B SW K1, 108(SP)\r
+BFD04FCC 5040035A SRL K0, K0, 10\r
+BFD04FCE 037A5040 ORI V0, ZERO, 890\r
+BFD04FD0 7A8C037A INS K1, K0, 10, 6\r
+BFD04FD2 03607A8C ADDIUPC A1, 787296\r
+BFD04FD4 204C0360 INS K1, ZERO, 1, 4\r
+BFD04FD6 036C204C LWC2 V0, 876(T4)\r
+BFD04FD8 02FC036C MTC0 K1, Status\r
+BFD04FDC C867 SW V1, 28(SP)\r
+BFD04FDE C846 SW V0, 24(SP)\r
+BFD04FE0 487C LW V1, 112(SP)\r
+BFD04FE2 2DB7 ANDI V1, V1, 0xF\r
+BFD04FE4 001140A3 BNEZC V1, 0xBFD0500A\r
+BFD04FE8 CBF7 SW RA, 92(SP)\r
+BFD04FEA CBD6 SW S8, 88(SP)\r
+BFD04FEC CB35 SW T9, 84(SP)\r
+BFD04FEE CB14 SW T8, 80(SP)\r
+BFD04FF0 C9F3 SW T7, 76(SP)\r
+BFD04FF2 C9D2 SW T6, 72(SP)\r
+BFD04FF4 C9B1 SW T5, 68(SP)\r
+BFD04FF6 C990 SW T4, 64(SP)\r
+BFD04FF8 C96F SW T3, 60(SP)\r
+BFD04FFA C94E SW T2, 56(SP)\r
+BFD04FFC C92D SW T1, 52(SP)\r
+BFD04FFE C90C SW T0, 48(SP)\r
+BFD05000 C8EB SW A3, 44(SP)\r
+BFD05002 C8CA SW A2, 40(SP)\r
+BFD05004 C8A9 SW A1, 36(SP)\r
+BFD05006 C888 SW A0, 32(SP)\r
+BFD05008 C825 SW AT, 20(SP)\r
+BFD0500A 4642 MFLO V0\r
+BFD0500C C859 SW V0, 100(SP)\r
+BFD0500E 4603 MFHI V1\r
+BFD05010 C878 SW V1, 96(SP)\r
+BFD05012 0FDD MOVE S8, SP\r
196: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 6, TRUE);\r
-BFD05014 EE0F LI A0, 15
-BFD05016 EE86 LI A1, 6
-BFD05018 EF01 LI A2, 1
-BFD0501A 3A4077E8 JALS jtvic_dis_clr_source
-BFD0501C 0C003A40 SH S2, 3072(ZERO)
-BFD0501E 0C00 NOP
+BFD05014 EE0F LI A0, 15\r
+BFD05016 EE86 LI A1, 6\r
+BFD05018 EF01 LI A2, 1\r
+BFD0501A 3A4077E8 JALS jtvic_dis_clr_source\r
+BFD0501C 0C003A40 SH S2, 3072(ZERO)\r
+BFD0501E 0C00 NOP\r
197: }\r
-BFD05020 0FBE MOVE SP, S8
-BFD05022 4859 LW V0, 100(SP)
-BFD05024 3D7C0002 MTLO V0
-BFD05026 48783D7C LH T3, 18552(GP)
-BFD05028 4878 LW V1, 96(SP)
-BFD0502A 2D7C0003 MTHI V1
-BFD0502C 2D7C ANDI V0, A3, 0x40
-BFD0502E 485C LW V0, 112(SP)
-BFD05030 2D27 ANDI V0, V0, 0xF
-BFD05032 001340A2 BNEZC V0, 0xBFD0505C
-BFD05036 4BF7 LW RA, 92(SP)
-BFD05038 4BD6 LW S8, 88(SP)
-BFD0503A 4B35 LW T9, 84(SP)
-BFD0503C 4B14 LW T8, 80(SP)
-BFD0503E 49F3 LW T7, 76(SP)
-BFD05040 49D2 LW T6, 72(SP)
-BFD05042 49B1 LW T5, 68(SP)
-BFD05044 4990 LW T4, 64(SP)
-BFD05046 496F LW T3, 60(SP)
-BFD05048 494E LW T2, 56(SP)
-BFD0504A 492D LW T1, 52(SP)
-BFD0504C 490C LW T0, 48(SP)
-BFD0504E 48EB LW A3, 44(SP)
-BFD05050 48CA LW A2, 40(SP)
-BFD05052 48A9 LW A1, 36(SP)
-BFD05054 4888 LW A0, 32(SP)
-BFD05056 4867 LW V1, 28(SP)
-BFD05058 4846 LW V0, 24(SP)
-BFD0505A 4825 LW AT, 20(SP)
-BFD0505C 477C0000 DI ZERO
-BFD05060 18000000 SLL ZERO, ZERO, 3
-BFD05062 4B5D1800 SB ZERO, 19293(ZERO)
-BFD05064 4B5D LW K0, 116(SP)
-BFD05066 4B7B LW K1, 108(SP)
-BFD05068 02FC034E MTC0 K0, EPC
-BFD0506C 4B5C LW K0, 112(SP)
-BFD0506E 4C3D ADDIU SP, SP, 120
-BFD05070 12FC034C MTC0 K0, SRSCtl
-BFD05072 03BD12FC ADDI S7, GP, 957
-BFD05074 F17C03BD WRPGPR SP, SP
-BFD05076 036CF17C JALX 0xBDF00DB0
-BFD05078 02FC036C MTC0 K1, Status
-BFD0507A 000002FC SLL S7, GP, 0
-BFD0507C F37C0000 ERET
-BFD0507E 03BDF37C JALX 0xBDF00EF4
+BFD05020 0FBE MOVE SP, S8\r
+BFD05022 4859 LW V0, 100(SP)\r
+BFD05024 3D7C0002 MTLO V0\r
+BFD05026 48783D7C LH T3, 18552(GP)\r
+BFD05028 4878 LW V1, 96(SP)\r
+BFD0502A 2D7C0003 MTHI V1\r
+BFD0502C 2D7C ANDI V0, A3, 0x40\r
+BFD0502E 485C LW V0, 112(SP)\r
+BFD05030 2D27 ANDI V0, V0, 0xF\r
+BFD05032 001340A2 BNEZC V0, 0xBFD0505C\r
+BFD05036 4BF7 LW RA, 92(SP)\r
+BFD05038 4BD6 LW S8, 88(SP)\r
+BFD0503A 4B35 LW T9, 84(SP)\r
+BFD0503C 4B14 LW T8, 80(SP)\r
+BFD0503E 49F3 LW T7, 76(SP)\r
+BFD05040 49D2 LW T6, 72(SP)\r
+BFD05042 49B1 LW T5, 68(SP)\r
+BFD05044 4990 LW T4, 64(SP)\r
+BFD05046 496F LW T3, 60(SP)\r
+BFD05048 494E LW T2, 56(SP)\r
+BFD0504A 492D LW T1, 52(SP)\r
+BFD0504C 490C LW T0, 48(SP)\r
+BFD0504E 48EB LW A3, 44(SP)\r
+BFD05050 48CA LW A2, 40(SP)\r
+BFD05052 48A9 LW A1, 36(SP)\r
+BFD05054 4888 LW A0, 32(SP)\r
+BFD05056 4867 LW V1, 28(SP)\r
+BFD05058 4846 LW V0, 24(SP)\r
+BFD0505A 4825 LW AT, 20(SP)\r
+BFD0505C 477C0000 DI ZERO\r
+BFD05060 18000000 SLL ZERO, ZERO, 3\r
+BFD05062 4B5D1800 SB ZERO, 19293(ZERO)\r
+BFD05064 4B5D LW K0, 116(SP)\r
+BFD05066 4B7B LW K1, 108(SP)\r
+BFD05068 02FC034E MTC0 K0, EPC\r
+BFD0506C 4B5C LW K0, 112(SP)\r
+BFD0506E 4C3D ADDIU SP, SP, 120\r
+BFD05070 12FC034C MTC0 K0, SRSCtl\r
+BFD05072 03BD12FC ADDI S7, GP, 957\r
+BFD05074 F17C03BD WRPGPR SP, SP\r
+BFD05076 036CF17C JALX 0xBDF00DB0\r
+BFD05078 02FC036C MTC0 K1, Status\r
+BFD0507A 000002FC SLL S7, GP, 0\r
+BFD0507C F37C0000 ERET\r
+BFD0507E 03BDF37C JALX 0xBDF00EF4\r
198: \r
199: /* Sub-Week Alarm */\r
200: void __attribute__((weak, interrupt, nomips16))\r
201: girq23_b7(void)\r
202: {\r
-BFD05080 E17C03BD RDPGPR SP, SP
-BFD05084 00FC036E MFC0 K1, EPC
-BFD05086 034C00FC INS A3, GP, 13, -12
-BFD05088 10FC034C MFC0 K0, SRSCtl
-BFD0508A 4FC510FC ADDI A3, GP, 20421
-BFD0508C 4FC5 ADDIU SP, SP, -120
-BFD0508E CB7D SW K1, 116(SP)
-BFD05090 00FC036C MFC0 K1, Status
-BFD05094 CB5C SW K0, 112(SP)
-BFD05096 00FC034D MFC0 K0, Cause
-BFD0509A CB7B SW K1, 108(SP)
-BFD0509C 5040035A SRL K0, K0, 10
-BFD0509E 037A5040 ORI V0, ZERO, 890
-BFD050A0 7A8C037A INS K1, K0, 10, 6
-BFD050A2 03607A8C ADDIUPC A1, 787296
-BFD050A4 204C0360 INS K1, ZERO, 1, 4
-BFD050A6 036C204C LWC2 V0, 876(T4)
-BFD050A8 02FC036C MTC0 K1, Status
-BFD050AC C867 SW V1, 28(SP)
-BFD050AE C846 SW V0, 24(SP)
-BFD050B0 487C LW V1, 112(SP)
-BFD050B2 2DB7 ANDI V1, V1, 0xF
-BFD050B4 001140A3 BNEZC V1, 0xBFD050DA
-BFD050B8 CBF7 SW RA, 92(SP)
-BFD050BA CBD6 SW S8, 88(SP)
-BFD050BC CB35 SW T9, 84(SP)
-BFD050BE CB14 SW T8, 80(SP)
-BFD050C0 C9F3 SW T7, 76(SP)
-BFD050C2 C9D2 SW T6, 72(SP)
-BFD050C4 C9B1 SW T5, 68(SP)
-BFD050C6 C990 SW T4, 64(SP)
-BFD050C8 C96F SW T3, 60(SP)
-BFD050CA C94E SW T2, 56(SP)
-BFD050CC C92D SW T1, 52(SP)
-BFD050CE C90C SW T0, 48(SP)
-BFD050D0 C8EB SW A3, 44(SP)
-BFD050D2 C8CA SW A2, 40(SP)
-BFD050D4 C8A9 SW A1, 36(SP)
-BFD050D6 C888 SW A0, 32(SP)
-BFD050D8 C825 SW AT, 20(SP)
-BFD050DA 4642 MFLO V0
-BFD050DC C859 SW V0, 100(SP)
-BFD050DE 4603 MFHI V1
-BFD050E0 C878 SW V1, 96(SP)
-BFD050E2 0FDD MOVE S8, SP
+BFD05080 E17C03BD RDPGPR SP, SP\r
+BFD05084 00FC036E MFC0 K1, EPC\r
+BFD05086 034C00FC INS A3, GP, 13, -12\r
+BFD05088 10FC034C MFC0 K0, SRSCtl\r
+BFD0508A 4FC510FC ADDI A3, GP, 20421\r
+BFD0508C 4FC5 ADDIU SP, SP, -120\r
+BFD0508E CB7D SW K1, 116(SP)\r
+BFD05090 00FC036C MFC0 K1, Status\r
+BFD05094 CB5C SW K0, 112(SP)\r
+BFD05096 00FC034D MFC0 K0, Cause\r
+BFD0509A CB7B SW K1, 108(SP)\r
+BFD0509C 5040035A SRL K0, K0, 10\r
+BFD0509E 037A5040 ORI V0, ZERO, 890\r
+BFD050A0 7A8C037A INS K1, K0, 10, 6\r
+BFD050A2 03607A8C ADDIUPC A1, 787296\r
+BFD050A4 204C0360 INS K1, ZERO, 1, 4\r
+BFD050A6 036C204C LWC2 V0, 876(T4)\r
+BFD050A8 02FC036C MTC0 K1, Status\r
+BFD050AC C867 SW V1, 28(SP)\r
+BFD050AE C846 SW V0, 24(SP)\r
+BFD050B0 487C LW V1, 112(SP)\r
+BFD050B2 2DB7 ANDI V1, V1, 0xF\r
+BFD050B4 001140A3 BNEZC V1, 0xBFD050DA\r
+BFD050B8 CBF7 SW RA, 92(SP)\r
+BFD050BA CBD6 SW S8, 88(SP)\r
+BFD050BC CB35 SW T9, 84(SP)\r
+BFD050BE CB14 SW T8, 80(SP)\r
+BFD050C0 C9F3 SW T7, 76(SP)\r
+BFD050C2 C9D2 SW T6, 72(SP)\r
+BFD050C4 C9B1 SW T5, 68(SP)\r
+BFD050C6 C990 SW T4, 64(SP)\r
+BFD050C8 C96F SW T3, 60(SP)\r
+BFD050CA C94E SW T2, 56(SP)\r
+BFD050CC C92D SW T1, 52(SP)\r
+BFD050CE C90C SW T0, 48(SP)\r
+BFD050D0 C8EB SW A3, 44(SP)\r
+BFD050D2 C8CA SW A2, 40(SP)\r
+BFD050D4 C8A9 SW A1, 36(SP)\r
+BFD050D6 C888 SW A0, 32(SP)\r
+BFD050D8 C825 SW AT, 20(SP)\r
+BFD050DA 4642 MFLO V0\r
+BFD050DC C859 SW V0, 100(SP)\r
+BFD050DE 4603 MFHI V1\r
+BFD050E0 C878 SW V1, 96(SP)\r
+BFD050E2 0FDD MOVE S8, SP\r
203: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 7, TRUE);\r
-BFD050E4 EE0F LI A0, 15
-BFD050E6 EE87 LI A1, 7
-BFD050E8 EF01 LI A2, 1
-BFD050EA 3A4077E8 JALS jtvic_dis_clr_source
-BFD050EC 0C003A40 SH S2, 3072(ZERO)
-BFD050EE 0C00 NOP
+BFD050E4 EE0F LI A0, 15\r
+BFD050E6 EE87 LI A1, 7\r
+BFD050E8 EF01 LI A2, 1\r
+BFD050EA 3A4077E8 JALS jtvic_dis_clr_source\r
+BFD050EC 0C003A40 SH S2, 3072(ZERO)\r
+BFD050EE 0C00 NOP\r
204: }\r
-BFD050F0 0FBE MOVE SP, S8
-BFD050F2 4859 LW V0, 100(SP)
-BFD050F4 3D7C0002 MTLO V0
-BFD050F6 48783D7C LH T3, 18552(GP)
-BFD050F8 4878 LW V1, 96(SP)
-BFD050FA 2D7C0003 MTHI V1
-BFD050FC 2D7C ANDI V0, A3, 0x40
-BFD050FE 485C LW V0, 112(SP)
-BFD05100 2D27 ANDI V0, V0, 0xF
-BFD05102 001340A2 BNEZC V0, 0xBFD0512C
-BFD05106 4BF7 LW RA, 92(SP)
-BFD05108 4BD6 LW S8, 88(SP)
-BFD0510A 4B35 LW T9, 84(SP)
-BFD0510C 4B14 LW T8, 80(SP)
-BFD0510E 49F3 LW T7, 76(SP)
-BFD05110 49D2 LW T6, 72(SP)
-BFD05112 49B1 LW T5, 68(SP)
-BFD05114 4990 LW T4, 64(SP)
-BFD05116 496F LW T3, 60(SP)
-BFD05118 494E LW T2, 56(SP)
-BFD0511A 492D LW T1, 52(SP)
-BFD0511C 490C LW T0, 48(SP)
-BFD0511E 48EB LW A3, 44(SP)
-BFD05120 48CA LW A2, 40(SP)
-BFD05122 48A9 LW A1, 36(SP)
-BFD05124 4888 LW A0, 32(SP)
-BFD05126 4867 LW V1, 28(SP)
-BFD05128 4846 LW V0, 24(SP)
-BFD0512A 4825 LW AT, 20(SP)
-BFD0512C 477C0000 DI ZERO
-BFD05130 18000000 SLL ZERO, ZERO, 3
-BFD05132 4B5D1800 SB ZERO, 19293(ZERO)
-BFD05134 4B5D LW K0, 116(SP)
-BFD05136 4B7B LW K1, 108(SP)
-BFD05138 02FC034E MTC0 K0, EPC
-BFD0513C 4B5C LW K0, 112(SP)
-BFD0513E 4C3D ADDIU SP, SP, 120
-BFD05140 12FC034C MTC0 K0, SRSCtl
-BFD05142 03BD12FC ADDI S7, GP, 957
-BFD05144 F17C03BD WRPGPR SP, SP
-BFD05146 036CF17C JALX 0xBDF00DB0
-BFD05148 02FC036C MTC0 K1, Status
-BFD0514A 000002FC SLL S7, GP, 0
-BFD0514C F37C0000 ERET
-BFD0514E 03BDF37C JALX 0xBDF00EF4
+BFD050F0 0FBE MOVE SP, S8\r
+BFD050F2 4859 LW V0, 100(SP)\r
+BFD050F4 3D7C0002 MTLO V0\r
+BFD050F6 48783D7C LH T3, 18552(GP)\r
+BFD050F8 4878 LW V1, 96(SP)\r
+BFD050FA 2D7C0003 MTHI V1\r
+BFD050FC 2D7C ANDI V0, A3, 0x40\r
+BFD050FE 485C LW V0, 112(SP)\r
+BFD05100 2D27 ANDI V0, V0, 0xF\r
+BFD05102 001340A2 BNEZC V0, 0xBFD0512C\r
+BFD05106 4BF7 LW RA, 92(SP)\r
+BFD05108 4BD6 LW S8, 88(SP)\r
+BFD0510A 4B35 LW T9, 84(SP)\r
+BFD0510C 4B14 LW T8, 80(SP)\r
+BFD0510E 49F3 LW T7, 76(SP)\r
+BFD05110 49D2 LW T6, 72(SP)\r
+BFD05112 49B1 LW T5, 68(SP)\r
+BFD05114 4990 LW T4, 64(SP)\r
+BFD05116 496F LW T3, 60(SP)\r
+BFD05118 494E LW T2, 56(SP)\r
+BFD0511A 492D LW T1, 52(SP)\r
+BFD0511C 490C LW T0, 48(SP)\r
+BFD0511E 48EB LW A3, 44(SP)\r
+BFD05120 48CA LW A2, 40(SP)\r
+BFD05122 48A9 LW A1, 36(SP)\r
+BFD05124 4888 LW A0, 32(SP)\r
+BFD05126 4867 LW V1, 28(SP)\r
+BFD05128 4846 LW V0, 24(SP)\r
+BFD0512A 4825 LW AT, 20(SP)\r
+BFD0512C 477C0000 DI ZERO\r
+BFD05130 18000000 SLL ZERO, ZERO, 3\r
+BFD05132 4B5D1800 SB ZERO, 19293(ZERO)\r
+BFD05134 4B5D LW K0, 116(SP)\r
+BFD05136 4B7B LW K1, 108(SP)\r
+BFD05138 02FC034E MTC0 K0, EPC\r
+BFD0513C 4B5C LW K0, 112(SP)\r
+BFD0513E 4C3D ADDIU SP, SP, 120\r
+BFD05140 12FC034C MTC0 K0, SRSCtl\r
+BFD05142 03BD12FC ADDI S7, GP, 957\r
+BFD05144 F17C03BD WRPGPR SP, SP\r
+BFD05146 036CF17C JALX 0xBDF00DB0\r
+BFD05148 02FC036C MTC0 K1, Status\r
+BFD0514A 000002FC SLL S7, GP, 0\r
+BFD0514C F37C0000 ERET\r
+BFD0514E 03BDF37C JALX 0xBDF00EF4\r
205: \r
206: /* Week Alarm One Second */\r
207: void __attribute__((weak, interrupt, nomips16))\r
208: girq23_b8(void)\r
209: {\r
-BFD05150 E17C03BD RDPGPR SP, SP
-BFD05154 00FC036E MFC0 K1, EPC
-BFD05156 034C00FC INS A3, GP, 13, -12
-BFD05158 10FC034C MFC0 K0, SRSCtl
-BFD0515A 4FC510FC ADDI A3, GP, 20421
-BFD0515C 4FC5 ADDIU SP, SP, -120
-BFD0515E CB7D SW K1, 116(SP)
-BFD05160 00FC036C MFC0 K1, Status
-BFD05164 CB5C SW K0, 112(SP)
-BFD05166 00FC034D MFC0 K0, Cause
-BFD0516A CB7B SW K1, 108(SP)
-BFD0516C 5040035A SRL K0, K0, 10
-BFD0516E 037A5040 ORI V0, ZERO, 890
-BFD05170 7A8C037A INS K1, K0, 10, 6
-BFD05172 03607A8C ADDIUPC A1, 787296
-BFD05174 204C0360 INS K1, ZERO, 1, 4
-BFD05176 036C204C LWC2 V0, 876(T4)
-BFD05178 02FC036C MTC0 K1, Status
-BFD0517C C867 SW V1, 28(SP)
-BFD0517E C846 SW V0, 24(SP)
-BFD05180 487C LW V1, 112(SP)
-BFD05182 2DB7 ANDI V1, V1, 0xF
-BFD05184 001140A3 BNEZC V1, 0xBFD051AA
-BFD05188 CBF7 SW RA, 92(SP)
-BFD0518A CBD6 SW S8, 88(SP)
-BFD0518C CB35 SW T9, 84(SP)
-BFD0518E CB14 SW T8, 80(SP)
-BFD05190 C9F3 SW T7, 76(SP)
-BFD05192 C9D2 SW T6, 72(SP)
-BFD05194 C9B1 SW T5, 68(SP)
-BFD05196 C990 SW T4, 64(SP)
-BFD05198 C96F SW T3, 60(SP)
-BFD0519A C94E SW T2, 56(SP)
-BFD0519C C92D SW T1, 52(SP)
-BFD0519E C90C SW T0, 48(SP)
-BFD051A0 C8EB SW A3, 44(SP)
-BFD051A2 C8CA SW A2, 40(SP)
-BFD051A4 C8A9 SW A1, 36(SP)
-BFD051A6 C888 SW A0, 32(SP)
-BFD051A8 C825 SW AT, 20(SP)
-BFD051AA 4642 MFLO V0
-BFD051AC C859 SW V0, 100(SP)
-BFD051AE 4603 MFHI V1
-BFD051B0 C878 SW V1, 96(SP)
-BFD051B2 0FDD MOVE S8, SP
+BFD05150 E17C03BD RDPGPR SP, SP\r
+BFD05154 00FC036E MFC0 K1, EPC\r
+BFD05156 034C00FC INS A3, GP, 13, -12\r
+BFD05158 10FC034C MFC0 K0, SRSCtl\r
+BFD0515A 4FC510FC ADDI A3, GP, 20421\r
+BFD0515C 4FC5 ADDIU SP, SP, -120\r
+BFD0515E CB7D SW K1, 116(SP)\r
+BFD05160 00FC036C MFC0 K1, Status\r
+BFD05164 CB5C SW K0, 112(SP)\r
+BFD05166 00FC034D MFC0 K0, Cause\r
+BFD0516A CB7B SW K1, 108(SP)\r
+BFD0516C 5040035A SRL K0, K0, 10\r
+BFD0516E 037A5040 ORI V0, ZERO, 890\r
+BFD05170 7A8C037A INS K1, K0, 10, 6\r
+BFD05172 03607A8C ADDIUPC A1, 787296\r
+BFD05174 204C0360 INS K1, ZERO, 1, 4\r
+BFD05176 036C204C LWC2 V0, 876(T4)\r
+BFD05178 02FC036C MTC0 K1, Status\r
+BFD0517C C867 SW V1, 28(SP)\r
+BFD0517E C846 SW V0, 24(SP)\r
+BFD05180 487C LW V1, 112(SP)\r
+BFD05182 2DB7 ANDI V1, V1, 0xF\r
+BFD05184 001140A3 BNEZC V1, 0xBFD051AA\r
+BFD05188 CBF7 SW RA, 92(SP)\r
+BFD0518A CBD6 SW S8, 88(SP)\r
+BFD0518C CB35 SW T9, 84(SP)\r
+BFD0518E CB14 SW T8, 80(SP)\r
+BFD05190 C9F3 SW T7, 76(SP)\r
+BFD05192 C9D2 SW T6, 72(SP)\r
+BFD05194 C9B1 SW T5, 68(SP)\r
+BFD05196 C990 SW T4, 64(SP)\r
+BFD05198 C96F SW T3, 60(SP)\r
+BFD0519A C94E SW T2, 56(SP)\r
+BFD0519C C92D SW T1, 52(SP)\r
+BFD0519E C90C SW T0, 48(SP)\r
+BFD051A0 C8EB SW A3, 44(SP)\r
+BFD051A2 C8CA SW A2, 40(SP)\r
+BFD051A4 C8A9 SW A1, 36(SP)\r
+BFD051A6 C888 SW A0, 32(SP)\r
+BFD051A8 C825 SW AT, 20(SP)\r
+BFD051AA 4642 MFLO V0\r
+BFD051AC C859 SW V0, 100(SP)\r
+BFD051AE 4603 MFHI V1\r
+BFD051B0 C878 SW V1, 96(SP)\r
+BFD051B2 0FDD MOVE S8, SP\r
210: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 8, TRUE);\r
-BFD051B4 EE0F LI A0, 15
-BFD051B6 EE88 LI A1, 8
-BFD051B8 EF01 LI A2, 1
-BFD051BA 3A4077E8 JALS jtvic_dis_clr_source
-BFD051BC 0C003A40 SH S2, 3072(ZERO)
-BFD051BE 0C00 NOP
+BFD051B4 EE0F LI A0, 15\r
+BFD051B6 EE88 LI A1, 8\r
+BFD051B8 EF01 LI A2, 1\r
+BFD051BA 3A4077E8 JALS jtvic_dis_clr_source\r
+BFD051BC 0C003A40 SH S2, 3072(ZERO)\r
+BFD051BE 0C00 NOP\r
211: }\r
-BFD051C0 0FBE MOVE SP, S8
-BFD051C2 4859 LW V0, 100(SP)
-BFD051C4 3D7C0002 MTLO V0
-BFD051C6 48783D7C LH T3, 18552(GP)
-BFD051C8 4878 LW V1, 96(SP)
-BFD051CA 2D7C0003 MTHI V1
-BFD051CC 2D7C ANDI V0, A3, 0x40
-BFD051CE 485C LW V0, 112(SP)
-BFD051D0 2D27 ANDI V0, V0, 0xF
-BFD051D2 001340A2 BNEZC V0, 0xBFD051FC
-BFD051D6 4BF7 LW RA, 92(SP)
-BFD051D8 4BD6 LW S8, 88(SP)
-BFD051DA 4B35 LW T9, 84(SP)
-BFD051DC 4B14 LW T8, 80(SP)
-BFD051DE 49F3 LW T7, 76(SP)
-BFD051E0 49D2 LW T6, 72(SP)
-BFD051E2 49B1 LW T5, 68(SP)
-BFD051E4 4990 LW T4, 64(SP)
-BFD051E6 496F LW T3, 60(SP)
-BFD051E8 494E LW T2, 56(SP)
-BFD051EA 492D LW T1, 52(SP)
-BFD051EC 490C LW T0, 48(SP)
-BFD051EE 48EB LW A3, 44(SP)
-BFD051F0 48CA LW A2, 40(SP)
-BFD051F2 48A9 LW A1, 36(SP)
-BFD051F4 4888 LW A0, 32(SP)
-BFD051F6 4867 LW V1, 28(SP)
-BFD051F8 4846 LW V0, 24(SP)
-BFD051FA 4825 LW AT, 20(SP)
-BFD051FC 477C0000 DI ZERO
-BFD05200 18000000 SLL ZERO, ZERO, 3
-BFD05202 4B5D1800 SB ZERO, 19293(ZERO)
-BFD05204 4B5D LW K0, 116(SP)
-BFD05206 4B7B LW K1, 108(SP)
-BFD05208 02FC034E MTC0 K0, EPC
-BFD0520C 4B5C LW K0, 112(SP)
-BFD0520E 4C3D ADDIU SP, SP, 120
-BFD05210 12FC034C MTC0 K0, SRSCtl
-BFD05212 03BD12FC ADDI S7, GP, 957
-BFD05214 F17C03BD WRPGPR SP, SP
-BFD05216 036CF17C JALX 0xBDF00DB0
-BFD05218 02FC036C MTC0 K1, Status
-BFD0521A 000002FC SLL S7, GP, 0
-BFD0521C F37C0000 ERET
-BFD0521E 03BDF37C JALX 0xBDF00EF4
+BFD051C0 0FBE MOVE SP, S8\r
+BFD051C2 4859 LW V0, 100(SP)\r
+BFD051C4 3D7C0002 MTLO V0\r
+BFD051C6 48783D7C LH T3, 18552(GP)\r
+BFD051C8 4878 LW V1, 96(SP)\r
+BFD051CA 2D7C0003 MTHI V1\r
+BFD051CC 2D7C ANDI V0, A3, 0x40\r
+BFD051CE 485C LW V0, 112(SP)\r
+BFD051D0 2D27 ANDI V0, V0, 0xF\r
+BFD051D2 001340A2 BNEZC V0, 0xBFD051FC\r
+BFD051D6 4BF7 LW RA, 92(SP)\r
+BFD051D8 4BD6 LW S8, 88(SP)\r
+BFD051DA 4B35 LW T9, 84(SP)\r
+BFD051DC 4B14 LW T8, 80(SP)\r
+BFD051DE 49F3 LW T7, 76(SP)\r
+BFD051E0 49D2 LW T6, 72(SP)\r
+BFD051E2 49B1 LW T5, 68(SP)\r
+BFD051E4 4990 LW T4, 64(SP)\r
+BFD051E6 496F LW T3, 60(SP)\r
+BFD051E8 494E LW T2, 56(SP)\r
+BFD051EA 492D LW T1, 52(SP)\r
+BFD051EC 490C LW T0, 48(SP)\r
+BFD051EE 48EB LW A3, 44(SP)\r
+BFD051F0 48CA LW A2, 40(SP)\r
+BFD051F2 48A9 LW A1, 36(SP)\r
+BFD051F4 4888 LW A0, 32(SP)\r
+BFD051F6 4867 LW V1, 28(SP)\r
+BFD051F8 4846 LW V0, 24(SP)\r
+BFD051FA 4825 LW AT, 20(SP)\r
+BFD051FC 477C0000 DI ZERO\r
+BFD05200 18000000 SLL ZERO, ZERO, 3\r
+BFD05202 4B5D1800 SB ZERO, 19293(ZERO)\r
+BFD05204 4B5D LW K0, 116(SP)\r
+BFD05206 4B7B LW K1, 108(SP)\r
+BFD05208 02FC034E MTC0 K0, EPC\r
+BFD0520C 4B5C LW K0, 112(SP)\r
+BFD0520E 4C3D ADDIU SP, SP, 120\r
+BFD05210 12FC034C MTC0 K0, SRSCtl\r
+BFD05212 03BD12FC ADDI S7, GP, 957\r
+BFD05214 F17C03BD WRPGPR SP, SP\r
+BFD05216 036CF17C JALX 0xBDF00DB0\r
+BFD05218 02FC036C MTC0 K1, Status\r
+BFD0521A 000002FC SLL S7, GP, 0\r
+BFD0521C F37C0000 ERET\r
+BFD0521E 03BDF37C JALX 0xBDF00EF4\r
212: \r
213: /* Week Alarm Sub Second */\r
214: void __attribute__((weak, interrupt, nomips16))\r
215: girq23_b9(void)\r
216: {\r
-BFD05220 E17C03BD RDPGPR SP, SP
-BFD05224 00FC036E MFC0 K1, EPC
-BFD05226 034C00FC INS A3, GP, 13, -12
-BFD05228 10FC034C MFC0 K0, SRSCtl
-BFD0522A 4FC510FC ADDI A3, GP, 20421
-BFD0522C 4FC5 ADDIU SP, SP, -120
-BFD0522E CB7D SW K1, 116(SP)
-BFD05230 00FC036C MFC0 K1, Status
-BFD05234 CB5C SW K0, 112(SP)
-BFD05236 00FC034D MFC0 K0, Cause
-BFD0523A CB7B SW K1, 108(SP)
-BFD0523C 5040035A SRL K0, K0, 10
-BFD0523E 037A5040 ORI V0, ZERO, 890
-BFD05240 7A8C037A INS K1, K0, 10, 6
-BFD05242 03607A8C ADDIUPC A1, 787296
-BFD05244 204C0360 INS K1, ZERO, 1, 4
-BFD05246 036C204C LWC2 V0, 876(T4)
-BFD05248 02FC036C MTC0 K1, Status
-BFD0524C C867 SW V1, 28(SP)
-BFD0524E C846 SW V0, 24(SP)
-BFD05250 487C LW V1, 112(SP)
-BFD05252 2DB7 ANDI V1, V1, 0xF
-BFD05254 001140A3 BNEZC V1, 0xBFD0527A
-BFD05258 CBF7 SW RA, 92(SP)
-BFD0525A CBD6 SW S8, 88(SP)
-BFD0525C CB35 SW T9, 84(SP)
-BFD0525E CB14 SW T8, 80(SP)
-BFD05260 C9F3 SW T7, 76(SP)
-BFD05262 C9D2 SW T6, 72(SP)
-BFD05264 C9B1 SW T5, 68(SP)
-BFD05266 C990 SW T4, 64(SP)
-BFD05268 C96F SW T3, 60(SP)
-BFD0526A C94E SW T2, 56(SP)
-BFD0526C C92D SW T1, 52(SP)
-BFD0526E C90C SW T0, 48(SP)
-BFD05270 C8EB SW A3, 44(SP)
-BFD05272 C8CA SW A2, 40(SP)
-BFD05274 C8A9 SW A1, 36(SP)
-BFD05276 C888 SW A0, 32(SP)
-BFD05278 C825 SW AT, 20(SP)
-BFD0527A 4642 MFLO V0
-BFD0527C C859 SW V0, 100(SP)
-BFD0527E 4603 MFHI V1
-BFD05280 C878 SW V1, 96(SP)
-BFD05282 0FDD MOVE S8, SP
+BFD05220 E17C03BD RDPGPR SP, SP\r
+BFD05224 00FC036E MFC0 K1, EPC\r
+BFD05226 034C00FC INS A3, GP, 13, -12\r
+BFD05228 10FC034C MFC0 K0, SRSCtl\r
+BFD0522A 4FC510FC ADDI A3, GP, 20421\r
+BFD0522C 4FC5 ADDIU SP, SP, -120\r
+BFD0522E CB7D SW K1, 116(SP)\r
+BFD05230 00FC036C MFC0 K1, Status\r
+BFD05234 CB5C SW K0, 112(SP)\r
+BFD05236 00FC034D MFC0 K0, Cause\r
+BFD0523A CB7B SW K1, 108(SP)\r
+BFD0523C 5040035A SRL K0, K0, 10\r
+BFD0523E 037A5040 ORI V0, ZERO, 890\r
+BFD05240 7A8C037A INS K1, K0, 10, 6\r
+BFD05242 03607A8C ADDIUPC A1, 787296\r
+BFD05244 204C0360 INS K1, ZERO, 1, 4\r
+BFD05246 036C204C LWC2 V0, 876(T4)\r
+BFD05248 02FC036C MTC0 K1, Status\r
+BFD0524C C867 SW V1, 28(SP)\r
+BFD0524E C846 SW V0, 24(SP)\r
+BFD05250 487C LW V1, 112(SP)\r
+BFD05252 2DB7 ANDI V1, V1, 0xF\r
+BFD05254 001140A3 BNEZC V1, 0xBFD0527A\r
+BFD05258 CBF7 SW RA, 92(SP)\r
+BFD0525A CBD6 SW S8, 88(SP)\r
+BFD0525C CB35 SW T9, 84(SP)\r
+BFD0525E CB14 SW T8, 80(SP)\r
+BFD05260 C9F3 SW T7, 76(SP)\r
+BFD05262 C9D2 SW T6, 72(SP)\r
+BFD05264 C9B1 SW T5, 68(SP)\r
+BFD05266 C990 SW T4, 64(SP)\r
+BFD05268 C96F SW T3, 60(SP)\r
+BFD0526A C94E SW T2, 56(SP)\r
+BFD0526C C92D SW T1, 52(SP)\r
+BFD0526E C90C SW T0, 48(SP)\r
+BFD05270 C8EB SW A3, 44(SP)\r
+BFD05272 C8CA SW A2, 40(SP)\r
+BFD05274 C8A9 SW A1, 36(SP)\r
+BFD05276 C888 SW A0, 32(SP)\r
+BFD05278 C825 SW AT, 20(SP)\r
+BFD0527A 4642 MFLO V0\r
+BFD0527C C859 SW V0, 100(SP)\r
+BFD0527E 4603 MFHI V1\r
+BFD05280 C878 SW V1, 96(SP)\r
+BFD05282 0FDD MOVE S8, SP\r
217: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 9, TRUE);\r
-BFD05284 EE0F LI A0, 15
-BFD05286 EE89 LI A1, 9
-BFD05288 EF01 LI A2, 1
-BFD0528A 3A4077E8 JALS jtvic_dis_clr_source
-BFD0528C 0C003A40 SH S2, 3072(ZERO)
-BFD0528E 0C00 NOP
+BFD05284 EE0F LI A0, 15\r
+BFD05286 EE89 LI A1, 9\r
+BFD05288 EF01 LI A2, 1\r
+BFD0528A 3A4077E8 JALS jtvic_dis_clr_source\r
+BFD0528C 0C003A40 SH S2, 3072(ZERO)\r
+BFD0528E 0C00 NOP\r
218: }\r
-BFD05290 0FBE MOVE SP, S8
-BFD05292 4859 LW V0, 100(SP)
-BFD05294 3D7C0002 MTLO V0
-BFD05296 48783D7C LH T3, 18552(GP)
-BFD05298 4878 LW V1, 96(SP)
-BFD0529A 2D7C0003 MTHI V1
-BFD0529C 2D7C ANDI V0, A3, 0x40
-BFD0529E 485C LW V0, 112(SP)
-BFD052A0 2D27 ANDI V0, V0, 0xF
-BFD052A2 001340A2 BNEZC V0, 0xBFD052CC
-BFD052A6 4BF7 LW RA, 92(SP)
-BFD052A8 4BD6 LW S8, 88(SP)
-BFD052AA 4B35 LW T9, 84(SP)
-BFD052AC 4B14 LW T8, 80(SP)
-BFD052AE 49F3 LW T7, 76(SP)
-BFD052B0 49D2 LW T6, 72(SP)
-BFD052B2 49B1 LW T5, 68(SP)
-BFD052B4 4990 LW T4, 64(SP)
-BFD052B6 496F LW T3, 60(SP)
-BFD052B8 494E LW T2, 56(SP)
-BFD052BA 492D LW T1, 52(SP)
-BFD052BC 490C LW T0, 48(SP)
-BFD052BE 48EB LW A3, 44(SP)
-BFD052C0 48CA LW A2, 40(SP)
-BFD052C2 48A9 LW A1, 36(SP)
-BFD052C4 4888 LW A0, 32(SP)
-BFD052C6 4867 LW V1, 28(SP)
-BFD052C8 4846 LW V0, 24(SP)
-BFD052CA 4825 LW AT, 20(SP)
-BFD052CC 477C0000 DI ZERO
-BFD052D0 18000000 SLL ZERO, ZERO, 3
-BFD052D2 4B5D1800 SB ZERO, 19293(ZERO)
-BFD052D4 4B5D LW K0, 116(SP)
-BFD052D6 4B7B LW K1, 108(SP)
-BFD052D8 02FC034E MTC0 K0, EPC
-BFD052DC 4B5C LW K0, 112(SP)
-BFD052DE 4C3D ADDIU SP, SP, 120
-BFD052E0 12FC034C MTC0 K0, SRSCtl
-BFD052E2 03BD12FC ADDI S7, GP, 957
-BFD052E4 F17C03BD WRPGPR SP, SP
-BFD052E6 036CF17C JALX 0xBDF00DB0
-BFD052E8 02FC036C MTC0 K1, Status
-BFD052EA 000002FC SLL S7, GP, 0
-BFD052EC F37C0000 ERET
-BFD052EE 03BDF37C JALX 0xBDF00EF4
+BFD05290 0FBE MOVE SP, S8\r
+BFD05292 4859 LW V0, 100(SP)\r
+BFD05294 3D7C0002 MTLO V0\r
+BFD05296 48783D7C LH T3, 18552(GP)\r
+BFD05298 4878 LW V1, 96(SP)\r
+BFD0529A 2D7C0003 MTHI V1\r
+BFD0529C 2D7C ANDI V0, A3, 0x40\r
+BFD0529E 485C LW V0, 112(SP)\r
+BFD052A0 2D27 ANDI V0, V0, 0xF\r
+BFD052A2 001340A2 BNEZC V0, 0xBFD052CC\r
+BFD052A6 4BF7 LW RA, 92(SP)\r
+BFD052A8 4BD6 LW S8, 88(SP)\r
+BFD052AA 4B35 LW T9, 84(SP)\r
+BFD052AC 4B14 LW T8, 80(SP)\r
+BFD052AE 49F3 LW T7, 76(SP)\r
+BFD052B0 49D2 LW T6, 72(SP)\r
+BFD052B2 49B1 LW T5, 68(SP)\r
+BFD052B4 4990 LW T4, 64(SP)\r
+BFD052B6 496F LW T3, 60(SP)\r
+BFD052B8 494E LW T2, 56(SP)\r
+BFD052BA 492D LW T1, 52(SP)\r
+BFD052BC 490C LW T0, 48(SP)\r
+BFD052BE 48EB LW A3, 44(SP)\r
+BFD052C0 48CA LW A2, 40(SP)\r
+BFD052C2 48A9 LW A1, 36(SP)\r
+BFD052C4 4888 LW A0, 32(SP)\r
+BFD052C6 4867 LW V1, 28(SP)\r
+BFD052C8 4846 LW V0, 24(SP)\r
+BFD052CA 4825 LW AT, 20(SP)\r
+BFD052CC 477C0000 DI ZERO\r
+BFD052D0 18000000 SLL ZERO, ZERO, 3\r
+BFD052D2 4B5D1800 SB ZERO, 19293(ZERO)\r
+BFD052D4 4B5D LW K0, 116(SP)\r
+BFD052D6 4B7B LW K1, 108(SP)\r
+BFD052D8 02FC034E MTC0 K0, EPC\r
+BFD052DC 4B5C LW K0, 112(SP)\r
+BFD052DE 4C3D ADDIU SP, SP, 120\r
+BFD052E0 12FC034C MTC0 K0, SRSCtl\r
+BFD052E2 03BD12FC ADDI S7, GP, 957\r
+BFD052E4 F17C03BD WRPGPR SP, SP\r
+BFD052E6 036CF17C JALX 0xBDF00DB0\r
+BFD052E8 02FC036C MTC0 K1, Status\r
+BFD052EA 000002FC SLL S7, GP, 0\r
+BFD052EC F37C0000 ERET\r
+BFD052EE 03BDF37C JALX 0xBDF00EF4\r
219: \r
220: /* Week Alarm System Power Present Pin */\r
221: void __attribute__((weak, interrupt, nomips16))\r
222: girq23_b10(void)\r
223: {\r
-BFD052F0 E17C03BD RDPGPR SP, SP
-BFD052F4 00FC036E MFC0 K1, EPC
-BFD052F6 034C00FC INS A3, GP, 13, -12
-BFD052F8 10FC034C MFC0 K0, SRSCtl
-BFD052FA 4FC510FC ADDI A3, GP, 20421
-BFD052FC 4FC5 ADDIU SP, SP, -120
-BFD052FE CB7D SW K1, 116(SP)
-BFD05300 00FC036C MFC0 K1, Status
-BFD05304 CB5C SW K0, 112(SP)
-BFD05306 00FC034D MFC0 K0, Cause
-BFD0530A CB7B SW K1, 108(SP)
-BFD0530C 5040035A SRL K0, K0, 10
-BFD0530E 037A5040 ORI V0, ZERO, 890
-BFD05310 7A8C037A INS K1, K0, 10, 6
-BFD05312 03607A8C ADDIUPC A1, 787296
-BFD05314 204C0360 INS K1, ZERO, 1, 4
-BFD05316 036C204C LWC2 V0, 876(T4)
-BFD05318 02FC036C MTC0 K1, Status
-BFD0531C C867 SW V1, 28(SP)
-BFD0531E C846 SW V0, 24(SP)
-BFD05320 487C LW V1, 112(SP)
-BFD05322 2DB7 ANDI V1, V1, 0xF
-BFD05324 001140A3 BNEZC V1, 0xBFD0534A
-BFD05328 CBF7 SW RA, 92(SP)
-BFD0532A CBD6 SW S8, 88(SP)
-BFD0532C CB35 SW T9, 84(SP)
-BFD0532E CB14 SW T8, 80(SP)
-BFD05330 C9F3 SW T7, 76(SP)
-BFD05332 C9D2 SW T6, 72(SP)
-BFD05334 C9B1 SW T5, 68(SP)
-BFD05336 C990 SW T4, 64(SP)
-BFD05338 C96F SW T3, 60(SP)
-BFD0533A C94E SW T2, 56(SP)
-BFD0533C C92D SW T1, 52(SP)
-BFD0533E C90C SW T0, 48(SP)
-BFD05340 C8EB SW A3, 44(SP)
-BFD05342 C8CA SW A2, 40(SP)
-BFD05344 C8A9 SW A1, 36(SP)
-BFD05346 C888 SW A0, 32(SP)
-BFD05348 C825 SW AT, 20(SP)
-BFD0534A 4642 MFLO V0
-BFD0534C C859 SW V0, 100(SP)
-BFD0534E 4603 MFHI V1
-BFD05350 C878 SW V1, 96(SP)
-BFD05352 0FDD MOVE S8, SP
+BFD052F0 E17C03BD RDPGPR SP, SP\r
+BFD052F4 00FC036E MFC0 K1, EPC\r
+BFD052F6 034C00FC INS A3, GP, 13, -12\r
+BFD052F8 10FC034C MFC0 K0, SRSCtl\r
+BFD052FA 4FC510FC ADDI A3, GP, 20421\r
+BFD052FC 4FC5 ADDIU SP, SP, -120\r
+BFD052FE CB7D SW K1, 116(SP)\r
+BFD05300 00FC036C MFC0 K1, Status\r
+BFD05304 CB5C SW K0, 112(SP)\r
+BFD05306 00FC034D MFC0 K0, Cause\r
+BFD0530A CB7B SW K1, 108(SP)\r
+BFD0530C 5040035A SRL K0, K0, 10\r
+BFD0530E 037A5040 ORI V0, ZERO, 890\r
+BFD05310 7A8C037A INS K1, K0, 10, 6\r
+BFD05312 03607A8C ADDIUPC A1, 787296\r
+BFD05314 204C0360 INS K1, ZERO, 1, 4\r
+BFD05316 036C204C LWC2 V0, 876(T4)\r
+BFD05318 02FC036C MTC0 K1, Status\r
+BFD0531C C867 SW V1, 28(SP)\r
+BFD0531E C846 SW V0, 24(SP)\r
+BFD05320 487C LW V1, 112(SP)\r
+BFD05322 2DB7 ANDI V1, V1, 0xF\r
+BFD05324 001140A3 BNEZC V1, 0xBFD0534A\r
+BFD05328 CBF7 SW RA, 92(SP)\r
+BFD0532A CBD6 SW S8, 88(SP)\r
+BFD0532C CB35 SW T9, 84(SP)\r
+BFD0532E CB14 SW T8, 80(SP)\r
+BFD05330 C9F3 SW T7, 76(SP)\r
+BFD05332 C9D2 SW T6, 72(SP)\r
+BFD05334 C9B1 SW T5, 68(SP)\r
+BFD05336 C990 SW T4, 64(SP)\r
+BFD05338 C96F SW T3, 60(SP)\r
+BFD0533A C94E SW T2, 56(SP)\r
+BFD0533C C92D SW T1, 52(SP)\r
+BFD0533E C90C SW T0, 48(SP)\r
+BFD05340 C8EB SW A3, 44(SP)\r
+BFD05342 C8CA SW A2, 40(SP)\r
+BFD05344 C8A9 SW A1, 36(SP)\r
+BFD05346 C888 SW A0, 32(SP)\r
+BFD05348 C825 SW AT, 20(SP)\r
+BFD0534A 4642 MFLO V0\r
+BFD0534C C859 SW V0, 100(SP)\r
+BFD0534E 4603 MFHI V1\r
+BFD05350 C878 SW V1, 96(SP)\r
+BFD05352 0FDD MOVE S8, SP\r
224: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 10, TRUE);\r
-BFD05354 EE0F LI A0, 15
-BFD05356 EE8A LI A1, 10
-BFD05358 EF01 LI A2, 1
-BFD0535A 3A4077E8 JALS jtvic_dis_clr_source
-BFD0535C 0C003A40 SH S2, 3072(ZERO)
-BFD0535E 0C00 NOP
+BFD05354 EE0F LI A0, 15\r
+BFD05356 EE8A LI A1, 10\r
+BFD05358 EF01 LI A2, 1\r
+BFD0535A 3A4077E8 JALS jtvic_dis_clr_source\r
+BFD0535C 0C003A40 SH S2, 3072(ZERO)\r
+BFD0535E 0C00 NOP\r
225: }\r
-BFD05360 0FBE MOVE SP, S8
-BFD05362 4859 LW V0, 100(SP)
-BFD05364 3D7C0002 MTLO V0
-BFD05366 48783D7C LH T3, 18552(GP)
-BFD05368 4878 LW V1, 96(SP)
-BFD0536A 2D7C0003 MTHI V1
-BFD0536C 2D7C ANDI V0, A3, 0x40
-BFD0536E 485C LW V0, 112(SP)
-BFD05370 2D27 ANDI V0, V0, 0xF
-BFD05372 001340A2 BNEZC V0, 0xBFD0539C
-BFD05376 4BF7 LW RA, 92(SP)
-BFD05378 4BD6 LW S8, 88(SP)
-BFD0537A 4B35 LW T9, 84(SP)
-BFD0537C 4B14 LW T8, 80(SP)
-BFD0537E 49F3 LW T7, 76(SP)
-BFD05380 49D2 LW T6, 72(SP)
-BFD05382 49B1 LW T5, 68(SP)
-BFD05384 4990 LW T4, 64(SP)
-BFD05386 496F LW T3, 60(SP)
-BFD05388 494E LW T2, 56(SP)
-BFD0538A 492D LW T1, 52(SP)
-BFD0538C 490C LW T0, 48(SP)
-BFD0538E 48EB LW A3, 44(SP)
-BFD05390 48CA LW A2, 40(SP)
-BFD05392 48A9 LW A1, 36(SP)
-BFD05394 4888 LW A0, 32(SP)
-BFD05396 4867 LW V1, 28(SP)
-BFD05398 4846 LW V0, 24(SP)
-BFD0539A 4825 LW AT, 20(SP)
-BFD0539C 477C0000 DI ZERO
-BFD053A0 18000000 SLL ZERO, ZERO, 3
-BFD053A2 4B5D1800 SB ZERO, 19293(ZERO)
-BFD053A4 4B5D LW K0, 116(SP)
-BFD053A6 4B7B LW K1, 108(SP)
-BFD053A8 02FC034E MTC0 K0, EPC
-BFD053AC 4B5C LW K0, 112(SP)
-BFD053AE 4C3D ADDIU SP, SP, 120
-BFD053B0 12FC034C MTC0 K0, SRSCtl
-BFD053B2 03BD12FC ADDI S7, GP, 957
-BFD053B4 F17C03BD WRPGPR SP, SP
-BFD053B6 036CF17C JALX 0xBDF00DB0
-BFD053B8 02FC036C MTC0 K1, Status
-BFD053BA 000002FC SLL S7, GP, 0
-BFD053BC F37C0000 ERET
-BFD053BE 03BDF37C JALX 0xBDF00EF4
+BFD05360 0FBE MOVE SP, S8\r
+BFD05362 4859 LW V0, 100(SP)\r
+BFD05364 3D7C0002 MTLO V0\r
+BFD05366 48783D7C LH T3, 18552(GP)\r
+BFD05368 4878 LW V1, 96(SP)\r
+BFD0536A 2D7C0003 MTHI V1\r
+BFD0536C 2D7C ANDI V0, A3, 0x40\r
+BFD0536E 485C LW V0, 112(SP)\r
+BFD05370 2D27 ANDI V0, V0, 0xF\r
+BFD05372 001340A2 BNEZC V0, 0xBFD0539C\r
+BFD05376 4BF7 LW RA, 92(SP)\r
+BFD05378 4BD6 LW S8, 88(SP)\r
+BFD0537A 4B35 LW T9, 84(SP)\r
+BFD0537C 4B14 LW T8, 80(SP)\r
+BFD0537E 49F3 LW T7, 76(SP)\r
+BFD05380 49D2 LW T6, 72(SP)\r
+BFD05382 49B1 LW T5, 68(SP)\r
+BFD05384 4990 LW T4, 64(SP)\r
+BFD05386 496F LW T3, 60(SP)\r
+BFD05388 494E LW T2, 56(SP)\r
+BFD0538A 492D LW T1, 52(SP)\r
+BFD0538C 490C LW T0, 48(SP)\r
+BFD0538E 48EB LW A3, 44(SP)\r
+BFD05390 48CA LW A2, 40(SP)\r
+BFD05392 48A9 LW A1, 36(SP)\r
+BFD05394 4888 LW A0, 32(SP)\r
+BFD05396 4867 LW V1, 28(SP)\r
+BFD05398 4846 LW V0, 24(SP)\r
+BFD0539A 4825 LW AT, 20(SP)\r
+BFD0539C 477C0000 DI ZERO\r
+BFD053A0 18000000 SLL ZERO, ZERO, 3\r
+BFD053A2 4B5D1800 SB ZERO, 19293(ZERO)\r
+BFD053A4 4B5D LW K0, 116(SP)\r
+BFD053A6 4B7B LW K1, 108(SP)\r
+BFD053A8 02FC034E MTC0 K0, EPC\r
+BFD053AC 4B5C LW K0, 112(SP)\r
+BFD053AE 4C3D ADDIU SP, SP, 120\r
+BFD053B0 12FC034C MTC0 K0, SRSCtl\r
+BFD053B2 03BD12FC ADDI S7, GP, 957\r
+BFD053B4 F17C03BD WRPGPR SP, SP\r
+BFD053B6 036CF17C JALX 0xBDF00DB0\r
+BFD053B8 02FC036C MTC0 K1, Status\r
+BFD053BA 000002FC SLL S7, GP, 0\r
+BFD053BC F37C0000 ERET\r
+BFD053BE 03BDF37C JALX 0xBDF00EF4\r
226: \r
227: /* VCI OVRD Input */\r
228: void __attribute__((weak, interrupt, nomips16))\r
229: girq23_b11(void)\r
230: {\r
-BFD053C0 E17C03BD RDPGPR SP, SP
-BFD053C4 00FC036E MFC0 K1, EPC
-BFD053C6 034C00FC INS A3, GP, 13, -12
-BFD053C8 10FC034C MFC0 K0, SRSCtl
-BFD053CA 4FC510FC ADDI A3, GP, 20421
-BFD053CC 4FC5 ADDIU SP, SP, -120
-BFD053CE CB7D SW K1, 116(SP)
-BFD053D0 00FC036C MFC0 K1, Status
-BFD053D4 CB5C SW K0, 112(SP)
-BFD053D6 00FC034D MFC0 K0, Cause
-BFD053DA CB7B SW K1, 108(SP)
-BFD053DC 5040035A SRL K0, K0, 10
-BFD053DE 037A5040 ORI V0, ZERO, 890
-BFD053E0 7A8C037A INS K1, K0, 10, 6
-BFD053E2 03607A8C ADDIUPC A1, 787296
-BFD053E4 204C0360 INS K1, ZERO, 1, 4
-BFD053E6 036C204C LWC2 V0, 876(T4)
-BFD053E8 02FC036C MTC0 K1, Status
-BFD053EC C867 SW V1, 28(SP)
-BFD053EE C846 SW V0, 24(SP)
-BFD053F0 487C LW V1, 112(SP)
-BFD053F2 2DB7 ANDI V1, V1, 0xF
-BFD053F4 001140A3 BNEZC V1, 0xBFD0541A
-BFD053F8 CBF7 SW RA, 92(SP)
-BFD053FA CBD6 SW S8, 88(SP)
-BFD053FC CB35 SW T9, 84(SP)
-BFD053FE CB14 SW T8, 80(SP)
-BFD05400 C9F3 SW T7, 76(SP)
-BFD05402 C9D2 SW T6, 72(SP)
-BFD05404 C9B1 SW T5, 68(SP)
-BFD05406 C990 SW T4, 64(SP)
-BFD05408 C96F SW T3, 60(SP)
-BFD0540A C94E SW T2, 56(SP)
-BFD0540C C92D SW T1, 52(SP)
-BFD0540E C90C SW T0, 48(SP)
-BFD05410 C8EB SW A3, 44(SP)
-BFD05412 C8CA SW A2, 40(SP)
-BFD05414 C8A9 SW A1, 36(SP)
-BFD05416 C888 SW A0, 32(SP)
-BFD05418 C825 SW AT, 20(SP)
-BFD0541A 4642 MFLO V0
-BFD0541C C859 SW V0, 100(SP)
-BFD0541E 4603 MFHI V1
-BFD05420 C878 SW V1, 96(SP)
-BFD05422 0FDD MOVE S8, SP
+BFD053C0 E17C03BD RDPGPR SP, SP\r
+BFD053C4 00FC036E MFC0 K1, EPC\r
+BFD053C6 034C00FC INS A3, GP, 13, -12\r
+BFD053C8 10FC034C MFC0 K0, SRSCtl\r
+BFD053CA 4FC510FC ADDI A3, GP, 20421\r
+BFD053CC 4FC5 ADDIU SP, SP, -120\r
+BFD053CE CB7D SW K1, 116(SP)\r
+BFD053D0 00FC036C MFC0 K1, Status\r
+BFD053D4 CB5C SW K0, 112(SP)\r
+BFD053D6 00FC034D MFC0 K0, Cause\r
+BFD053DA CB7B SW K1, 108(SP)\r
+BFD053DC 5040035A SRL K0, K0, 10\r
+BFD053DE 037A5040 ORI V0, ZERO, 890\r
+BFD053E0 7A8C037A INS K1, K0, 10, 6\r
+BFD053E2 03607A8C ADDIUPC A1, 787296\r
+BFD053E4 204C0360 INS K1, ZERO, 1, 4\r
+BFD053E6 036C204C LWC2 V0, 876(T4)\r
+BFD053E8 02FC036C MTC0 K1, Status\r
+BFD053EC C867 SW V1, 28(SP)\r
+BFD053EE C846 SW V0, 24(SP)\r
+BFD053F0 487C LW V1, 112(SP)\r
+BFD053F2 2DB7 ANDI V1, V1, 0xF\r
+BFD053F4 001140A3 BNEZC V1, 0xBFD0541A\r
+BFD053F8 CBF7 SW RA, 92(SP)\r
+BFD053FA CBD6 SW S8, 88(SP)\r
+BFD053FC CB35 SW T9, 84(SP)\r
+BFD053FE CB14 SW T8, 80(SP)\r
+BFD05400 C9F3 SW T7, 76(SP)\r
+BFD05402 C9D2 SW T6, 72(SP)\r
+BFD05404 C9B1 SW T5, 68(SP)\r
+BFD05406 C990 SW T4, 64(SP)\r
+BFD05408 C96F SW T3, 60(SP)\r
+BFD0540A C94E SW T2, 56(SP)\r
+BFD0540C C92D SW T1, 52(SP)\r
+BFD0540E C90C SW T0, 48(SP)\r
+BFD05410 C8EB SW A3, 44(SP)\r
+BFD05412 C8CA SW A2, 40(SP)\r
+BFD05414 C8A9 SW A1, 36(SP)\r
+BFD05416 C888 SW A0, 32(SP)\r
+BFD05418 C825 SW AT, 20(SP)\r
+BFD0541A 4642 MFLO V0\r
+BFD0541C C859 SW V0, 100(SP)\r
+BFD0541E 4603 MFHI V1\r
+BFD05420 C878 SW V1, 96(SP)\r
+BFD05422 0FDD MOVE S8, SP\r
231: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 11, TRUE);\r
-BFD05424 EE0F LI A0, 15
-BFD05426 EE8B LI A1, 11
-BFD05428 EF01 LI A2, 1
-BFD0542A 3A4077E8 JALS jtvic_dis_clr_source
-BFD0542C 0C003A40 SH S2, 3072(ZERO)
-BFD0542E 0C00 NOP
+BFD05424 EE0F LI A0, 15\r
+BFD05426 EE8B LI A1, 11\r
+BFD05428 EF01 LI A2, 1\r
+BFD0542A 3A4077E8 JALS jtvic_dis_clr_source\r
+BFD0542C 0C003A40 SH S2, 3072(ZERO)\r
+BFD0542E 0C00 NOP\r
232: }\r
-BFD05430 0FBE MOVE SP, S8
-BFD05432 4859 LW V0, 100(SP)
-BFD05434 3D7C0002 MTLO V0
-BFD05436 48783D7C LH T3, 18552(GP)
-BFD05438 4878 LW V1, 96(SP)
-BFD0543A 2D7C0003 MTHI V1
-BFD0543C 2D7C ANDI V0, A3, 0x40
-BFD0543E 485C LW V0, 112(SP)
-BFD05440 2D27 ANDI V0, V0, 0xF
-BFD05442 001340A2 BNEZC V0, 0xBFD0546C
-BFD05446 4BF7 LW RA, 92(SP)
-BFD05448 4BD6 LW S8, 88(SP)
-BFD0544A 4B35 LW T9, 84(SP)
-BFD0544C 4B14 LW T8, 80(SP)
-BFD0544E 49F3 LW T7, 76(SP)
-BFD05450 49D2 LW T6, 72(SP)
-BFD05452 49B1 LW T5, 68(SP)
-BFD05454 4990 LW T4, 64(SP)
-BFD05456 496F LW T3, 60(SP)
-BFD05458 494E LW T2, 56(SP)
-BFD0545A 492D LW T1, 52(SP)
-BFD0545C 490C LW T0, 48(SP)
-BFD0545E 48EB LW A3, 44(SP)
-BFD05460 48CA LW A2, 40(SP)
-BFD05462 48A9 LW A1, 36(SP)
-BFD05464 4888 LW A0, 32(SP)
-BFD05466 4867 LW V1, 28(SP)
-BFD05468 4846 LW V0, 24(SP)
-BFD0546A 4825 LW AT, 20(SP)
-BFD0546C 477C0000 DI ZERO
-BFD05470 18000000 SLL ZERO, ZERO, 3
-BFD05472 4B5D1800 SB ZERO, 19293(ZERO)
-BFD05474 4B5D LW K0, 116(SP)
-BFD05476 4B7B LW K1, 108(SP)
-BFD05478 02FC034E MTC0 K0, EPC
-BFD0547C 4B5C LW K0, 112(SP)
-BFD0547E 4C3D ADDIU SP, SP, 120
-BFD05480 12FC034C MTC0 K0, SRSCtl
-BFD05482 03BD12FC ADDI S7, GP, 957
-BFD05484 F17C03BD WRPGPR SP, SP
-BFD05486 036CF17C JALX 0xBDF00DB0
-BFD05488 02FC036C MTC0 K1, Status
-BFD0548A 000002FC SLL S7, GP, 0
-BFD0548C F37C0000 ERET
-BFD0548E 03BDF37C JALX 0xBDF00EF4
+BFD05430 0FBE MOVE SP, S8\r
+BFD05432 4859 LW V0, 100(SP)\r
+BFD05434 3D7C0002 MTLO V0\r
+BFD05436 48783D7C LH T3, 18552(GP)\r
+BFD05438 4878 LW V1, 96(SP)\r
+BFD0543A 2D7C0003 MTHI V1\r
+BFD0543C 2D7C ANDI V0, A3, 0x40\r
+BFD0543E 485C LW V0, 112(SP)\r
+BFD05440 2D27 ANDI V0, V0, 0xF\r
+BFD05442 001340A2 BNEZC V0, 0xBFD0546C\r
+BFD05446 4BF7 LW RA, 92(SP)\r
+BFD05448 4BD6 LW S8, 88(SP)\r
+BFD0544A 4B35 LW T9, 84(SP)\r
+BFD0544C 4B14 LW T8, 80(SP)\r
+BFD0544E 49F3 LW T7, 76(SP)\r
+BFD05450 49D2 LW T6, 72(SP)\r
+BFD05452 49B1 LW T5, 68(SP)\r
+BFD05454 4990 LW T4, 64(SP)\r
+BFD05456 496F LW T3, 60(SP)\r
+BFD05458 494E LW T2, 56(SP)\r
+BFD0545A 492D LW T1, 52(SP)\r
+BFD0545C 490C LW T0, 48(SP)\r
+BFD0545E 48EB LW A3, 44(SP)\r
+BFD05460 48CA LW A2, 40(SP)\r
+BFD05462 48A9 LW A1, 36(SP)\r
+BFD05464 4888 LW A0, 32(SP)\r
+BFD05466 4867 LW V1, 28(SP)\r
+BFD05468 4846 LW V0, 24(SP)\r
+BFD0546A 4825 LW AT, 20(SP)\r
+BFD0546C 477C0000 DI ZERO\r
+BFD05470 18000000 SLL ZERO, ZERO, 3\r
+BFD05472 4B5D1800 SB ZERO, 19293(ZERO)\r
+BFD05474 4B5D LW K0, 116(SP)\r
+BFD05476 4B7B LW K1, 108(SP)\r
+BFD05478 02FC034E MTC0 K0, EPC\r
+BFD0547C 4B5C LW K0, 112(SP)\r
+BFD0547E 4C3D ADDIU SP, SP, 120\r
+BFD05480 12FC034C MTC0 K0, SRSCtl\r
+BFD05482 03BD12FC ADDI S7, GP, 957\r
+BFD05484 F17C03BD WRPGPR SP, SP\r
+BFD05486 036CF17C JALX 0xBDF00DB0\r
+BFD05488 02FC036C MTC0 K1, Status\r
+BFD0548A 000002FC SLL S7, GP, 0\r
+BFD0548C F37C0000 ERET\r
+BFD0548E 03BDF37C JALX 0xBDF00EF4\r
233: \r
234: /* VCI IN0 */\r
235: void __attribute__((weak, interrupt, nomips16))\r
236: girq23_b12(void)\r
237: {\r
-BFD05490 E17C03BD RDPGPR SP, SP
-BFD05494 00FC036E MFC0 K1, EPC
-BFD05496 034C00FC INS A3, GP, 13, -12
-BFD05498 10FC034C MFC0 K0, SRSCtl
-BFD0549A 4FC510FC ADDI A3, GP, 20421
-BFD0549C 4FC5 ADDIU SP, SP, -120
-BFD0549E CB7D SW K1, 116(SP)
-BFD054A0 00FC036C MFC0 K1, Status
-BFD054A4 CB5C SW K0, 112(SP)
-BFD054A6 00FC034D MFC0 K0, Cause
-BFD054AA CB7B SW K1, 108(SP)
-BFD054AC 5040035A SRL K0, K0, 10
-BFD054AE 037A5040 ORI V0, ZERO, 890
-BFD054B0 7A8C037A INS K1, K0, 10, 6
-BFD054B2 03607A8C ADDIUPC A1, 787296
-BFD054B4 204C0360 INS K1, ZERO, 1, 4
-BFD054B6 036C204C LWC2 V0, 876(T4)
-BFD054B8 02FC036C MTC0 K1, Status
-BFD054BC C867 SW V1, 28(SP)
-BFD054BE C846 SW V0, 24(SP)
-BFD054C0 487C LW V1, 112(SP)
-BFD054C2 2DB7 ANDI V1, V1, 0xF
-BFD054C4 001140A3 BNEZC V1, 0xBFD054EA
-BFD054C8 CBF7 SW RA, 92(SP)
-BFD054CA CBD6 SW S8, 88(SP)
-BFD054CC CB35 SW T9, 84(SP)
-BFD054CE CB14 SW T8, 80(SP)
-BFD054D0 C9F3 SW T7, 76(SP)
-BFD054D2 C9D2 SW T6, 72(SP)
-BFD054D4 C9B1 SW T5, 68(SP)
-BFD054D6 C990 SW T4, 64(SP)
-BFD054D8 C96F SW T3, 60(SP)
-BFD054DA C94E SW T2, 56(SP)
-BFD054DC C92D SW T1, 52(SP)
-BFD054DE C90C SW T0, 48(SP)
-BFD054E0 C8EB SW A3, 44(SP)
-BFD054E2 C8CA SW A2, 40(SP)
-BFD054E4 C8A9 SW A1, 36(SP)
-BFD054E6 C888 SW A0, 32(SP)
-BFD054E8 C825 SW AT, 20(SP)
-BFD054EA 4642 MFLO V0
-BFD054EC C859 SW V0, 100(SP)
-BFD054EE 4603 MFHI V1
-BFD054F0 C878 SW V1, 96(SP)
-BFD054F2 0FDD MOVE S8, SP
+BFD05490 E17C03BD RDPGPR SP, SP\r
+BFD05494 00FC036E MFC0 K1, EPC\r
+BFD05496 034C00FC INS A3, GP, 13, -12\r
+BFD05498 10FC034C MFC0 K0, SRSCtl\r
+BFD0549A 4FC510FC ADDI A3, GP, 20421\r
+BFD0549C 4FC5 ADDIU SP, SP, -120\r
+BFD0549E CB7D SW K1, 116(SP)\r
+BFD054A0 00FC036C MFC0 K1, Status\r
+BFD054A4 CB5C SW K0, 112(SP)\r
+BFD054A6 00FC034D MFC0 K0, Cause\r
+BFD054AA CB7B SW K1, 108(SP)\r
+BFD054AC 5040035A SRL K0, K0, 10\r
+BFD054AE 037A5040 ORI V0, ZERO, 890\r
+BFD054B0 7A8C037A INS K1, K0, 10, 6\r
+BFD054B2 03607A8C ADDIUPC A1, 787296\r
+BFD054B4 204C0360 INS K1, ZERO, 1, 4\r
+BFD054B6 036C204C LWC2 V0, 876(T4)\r
+BFD054B8 02FC036C MTC0 K1, Status\r
+BFD054BC C867 SW V1, 28(SP)\r
+BFD054BE C846 SW V0, 24(SP)\r
+BFD054C0 487C LW V1, 112(SP)\r
+BFD054C2 2DB7 ANDI V1, V1, 0xF\r
+BFD054C4 001140A3 BNEZC V1, 0xBFD054EA\r
+BFD054C8 CBF7 SW RA, 92(SP)\r
+BFD054CA CBD6 SW S8, 88(SP)\r
+BFD054CC CB35 SW T9, 84(SP)\r
+BFD054CE CB14 SW T8, 80(SP)\r
+BFD054D0 C9F3 SW T7, 76(SP)\r
+BFD054D2 C9D2 SW T6, 72(SP)\r
+BFD054D4 C9B1 SW T5, 68(SP)\r
+BFD054D6 C990 SW T4, 64(SP)\r
+BFD054D8 C96F SW T3, 60(SP)\r
+BFD054DA C94E SW T2, 56(SP)\r
+BFD054DC C92D SW T1, 52(SP)\r
+BFD054DE C90C SW T0, 48(SP)\r
+BFD054E0 C8EB SW A3, 44(SP)\r
+BFD054E2 C8CA SW A2, 40(SP)\r
+BFD054E4 C8A9 SW A1, 36(SP)\r
+BFD054E6 C888 SW A0, 32(SP)\r
+BFD054E8 C825 SW AT, 20(SP)\r
+BFD054EA 4642 MFLO V0\r
+BFD054EC C859 SW V0, 100(SP)\r
+BFD054EE 4603 MFHI V1\r
+BFD054F0 C878 SW V1, 96(SP)\r
+BFD054F2 0FDD MOVE S8, SP\r
238: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 12, TRUE);\r
-BFD054F4 EE0F LI A0, 15
-BFD054F6 EE8C LI A1, 12
-BFD054F8 EF01 LI A2, 1
-BFD054FA 3A4077E8 JALS jtvic_dis_clr_source
-BFD054FC 0C003A40 SH S2, 3072(ZERO)
-BFD054FE 0C00 NOP
+BFD054F4 EE0F LI A0, 15\r
+BFD054F6 EE8C LI A1, 12\r
+BFD054F8 EF01 LI A2, 1\r
+BFD054FA 3A4077E8 JALS jtvic_dis_clr_source\r
+BFD054FC 0C003A40 SH S2, 3072(ZERO)\r
+BFD054FE 0C00 NOP\r
239: }\r
-BFD05500 0FBE MOVE SP, S8
-BFD05502 4859 LW V0, 100(SP)
-BFD05504 3D7C0002 MTLO V0
-BFD05506 48783D7C LH T3, 18552(GP)
-BFD05508 4878 LW V1, 96(SP)
-BFD0550A 2D7C0003 MTHI V1
-BFD0550C 2D7C ANDI V0, A3, 0x40
-BFD0550E 485C LW V0, 112(SP)
-BFD05510 2D27 ANDI V0, V0, 0xF
-BFD05512 001340A2 BNEZC V0, 0xBFD0553C
-BFD05516 4BF7 LW RA, 92(SP)
-BFD05518 4BD6 LW S8, 88(SP)
-BFD0551A 4B35 LW T9, 84(SP)
-BFD0551C 4B14 LW T8, 80(SP)
-BFD0551E 49F3 LW T7, 76(SP)
-BFD05520 49D2 LW T6, 72(SP)
-BFD05522 49B1 LW T5, 68(SP)
-BFD05524 4990 LW T4, 64(SP)
-BFD05526 496F LW T3, 60(SP)
-BFD05528 494E LW T2, 56(SP)
-BFD0552A 492D LW T1, 52(SP)
-BFD0552C 490C LW T0, 48(SP)
-BFD0552E 48EB LW A3, 44(SP)
-BFD05530 48CA LW A2, 40(SP)
-BFD05532 48A9 LW A1, 36(SP)
-BFD05534 4888 LW A0, 32(SP)
-BFD05536 4867 LW V1, 28(SP)
-BFD05538 4846 LW V0, 24(SP)
-BFD0553A 4825 LW AT, 20(SP)
-BFD0553C 477C0000 DI ZERO
-BFD05540 18000000 SLL ZERO, ZERO, 3
-BFD05542 4B5D1800 SB ZERO, 19293(ZERO)
-BFD05544 4B5D LW K0, 116(SP)
-BFD05546 4B7B LW K1, 108(SP)
-BFD05548 02FC034E MTC0 K0, EPC
-BFD0554C 4B5C LW K0, 112(SP)
-BFD0554E 4C3D ADDIU SP, SP, 120
-BFD05550 12FC034C MTC0 K0, SRSCtl
-BFD05552 03BD12FC ADDI S7, GP, 957
-BFD05554 F17C03BD WRPGPR SP, SP
-BFD05556 036CF17C JALX 0xBDF00DB0
-BFD05558 02FC036C MTC0 K1, Status
-BFD0555A 000002FC SLL S7, GP, 0
-BFD0555C F37C0000 ERET
-BFD0555E 03BDF37C JALX 0xBDF00EF4
+BFD05500 0FBE MOVE SP, S8\r
+BFD05502 4859 LW V0, 100(SP)\r
+BFD05504 3D7C0002 MTLO V0\r
+BFD05506 48783D7C LH T3, 18552(GP)\r
+BFD05508 4878 LW V1, 96(SP)\r
+BFD0550A 2D7C0003 MTHI V1\r
+BFD0550C 2D7C ANDI V0, A3, 0x40\r
+BFD0550E 485C LW V0, 112(SP)\r
+BFD05510 2D27 ANDI V0, V0, 0xF\r
+BFD05512 001340A2 BNEZC V0, 0xBFD0553C\r
+BFD05516 4BF7 LW RA, 92(SP)\r
+BFD05518 4BD6 LW S8, 88(SP)\r
+BFD0551A 4B35 LW T9, 84(SP)\r
+BFD0551C 4B14 LW T8, 80(SP)\r
+BFD0551E 49F3 LW T7, 76(SP)\r
+BFD05520 49D2 LW T6, 72(SP)\r
+BFD05522 49B1 LW T5, 68(SP)\r
+BFD05524 4990 LW T4, 64(SP)\r
+BFD05526 496F LW T3, 60(SP)\r
+BFD05528 494E LW T2, 56(SP)\r
+BFD0552A 492D LW T1, 52(SP)\r
+BFD0552C 490C LW T0, 48(SP)\r
+BFD0552E 48EB LW A3, 44(SP)\r
+BFD05530 48CA LW A2, 40(SP)\r
+BFD05532 48A9 LW A1, 36(SP)\r
+BFD05534 4888 LW A0, 32(SP)\r
+BFD05536 4867 LW V1, 28(SP)\r
+BFD05538 4846 LW V0, 24(SP)\r
+BFD0553A 4825 LW AT, 20(SP)\r
+BFD0553C 477C0000 DI ZERO\r
+BFD05540 18000000 SLL ZERO, ZERO, 3\r
+BFD05542 4B5D1800 SB ZERO, 19293(ZERO)\r
+BFD05544 4B5D LW K0, 116(SP)\r
+BFD05546 4B7B LW K1, 108(SP)\r
+BFD05548 02FC034E MTC0 K0, EPC\r
+BFD0554C 4B5C LW K0, 112(SP)\r
+BFD0554E 4C3D ADDIU SP, SP, 120\r
+BFD05550 12FC034C MTC0 K0, SRSCtl\r
+BFD05552 03BD12FC ADDI S7, GP, 957\r
+BFD05554 F17C03BD WRPGPR SP, SP\r
+BFD05556 036CF17C JALX 0xBDF00DB0\r
+BFD05558 02FC036C MTC0 K1, Status\r
+BFD0555A 000002FC SLL S7, GP, 0\r
+BFD0555C F37C0000 ERET\r
+BFD0555E 03BDF37C JALX 0xBDF00EF4\r
240: \r
241: /* VCI IN1 */\r
242: void __attribute__((weak, interrupt, nomips16))\r
243: girq23_b13(void)\r
244: {\r
-BFD05560 E17C03BD RDPGPR SP, SP
-BFD05564 00FC036E MFC0 K1, EPC
-BFD05566 034C00FC INS A3, GP, 13, -12
-BFD05568 10FC034C MFC0 K0, SRSCtl
-BFD0556A 4FC510FC ADDI A3, GP, 20421
-BFD0556C 4FC5 ADDIU SP, SP, -120
-BFD0556E CB7D SW K1, 116(SP)
-BFD05570 00FC036C MFC0 K1, Status
-BFD05574 CB5C SW K0, 112(SP)
-BFD05576 00FC034D MFC0 K0, Cause
-BFD0557A CB7B SW K1, 108(SP)
-BFD0557C 5040035A SRL K0, K0, 10
-BFD0557E 037A5040 ORI V0, ZERO, 890
-BFD05580 7A8C037A INS K1, K0, 10, 6
-BFD05582 03607A8C ADDIUPC A1, 787296
-BFD05584 204C0360 INS K1, ZERO, 1, 4
-BFD05586 036C204C LWC2 V0, 876(T4)
-BFD05588 02FC036C MTC0 K1, Status
-BFD0558C C867 SW V1, 28(SP)
-BFD0558E C846 SW V0, 24(SP)
-BFD05590 487C LW V1, 112(SP)
-BFD05592 2DB7 ANDI V1, V1, 0xF
-BFD05594 001140A3 BNEZC V1, 0xBFD055BA
-BFD05598 CBF7 SW RA, 92(SP)
-BFD0559A CBD6 SW S8, 88(SP)
-BFD0559C CB35 SW T9, 84(SP)
-BFD0559E CB14 SW T8, 80(SP)
-BFD055A0 C9F3 SW T7, 76(SP)
-BFD055A2 C9D2 SW T6, 72(SP)
-BFD055A4 C9B1 SW T5, 68(SP)
-BFD055A6 C990 SW T4, 64(SP)
-BFD055A8 C96F SW T3, 60(SP)
-BFD055AA C94E SW T2, 56(SP)
-BFD055AC C92D SW T1, 52(SP)
-BFD055AE C90C SW T0, 48(SP)
-BFD055B0 C8EB SW A3, 44(SP)
-BFD055B2 C8CA SW A2, 40(SP)
-BFD055B4 C8A9 SW A1, 36(SP)
-BFD055B6 C888 SW A0, 32(SP)
-BFD055B8 C825 SW AT, 20(SP)
-BFD055BA 4642 MFLO V0
-BFD055BC C859 SW V0, 100(SP)
-BFD055BE 4603 MFHI V1
-BFD055C0 C878 SW V1, 96(SP)
-BFD055C2 0FDD MOVE S8, SP
+BFD05560 E17C03BD RDPGPR SP, SP\r
+BFD05564 00FC036E MFC0 K1, EPC\r
+BFD05566 034C00FC INS A3, GP, 13, -12\r
+BFD05568 10FC034C MFC0 K0, SRSCtl\r
+BFD0556A 4FC510FC ADDI A3, GP, 20421\r
+BFD0556C 4FC5 ADDIU SP, SP, -120\r
+BFD0556E CB7D SW K1, 116(SP)\r
+BFD05570 00FC036C MFC0 K1, Status\r
+BFD05574 CB5C SW K0, 112(SP)\r
+BFD05576 00FC034D MFC0 K0, Cause\r
+BFD0557A CB7B SW K1, 108(SP)\r
+BFD0557C 5040035A SRL K0, K0, 10\r
+BFD0557E 037A5040 ORI V0, ZERO, 890\r
+BFD05580 7A8C037A INS K1, K0, 10, 6\r
+BFD05582 03607A8C ADDIUPC A1, 787296\r
+BFD05584 204C0360 INS K1, ZERO, 1, 4\r
+BFD05586 036C204C LWC2 V0, 876(T4)\r
+BFD05588 02FC036C MTC0 K1, Status\r
+BFD0558C C867 SW V1, 28(SP)\r
+BFD0558E C846 SW V0, 24(SP)\r
+BFD05590 487C LW V1, 112(SP)\r
+BFD05592 2DB7 ANDI V1, V1, 0xF\r
+BFD05594 001140A3 BNEZC V1, 0xBFD055BA\r
+BFD05598 CBF7 SW RA, 92(SP)\r
+BFD0559A CBD6 SW S8, 88(SP)\r
+BFD0559C CB35 SW T9, 84(SP)\r
+BFD0559E CB14 SW T8, 80(SP)\r
+BFD055A0 C9F3 SW T7, 76(SP)\r
+BFD055A2 C9D2 SW T6, 72(SP)\r
+BFD055A4 C9B1 SW T5, 68(SP)\r
+BFD055A6 C990 SW T4, 64(SP)\r
+BFD055A8 C96F SW T3, 60(SP)\r
+BFD055AA C94E SW T2, 56(SP)\r
+BFD055AC C92D SW T1, 52(SP)\r
+BFD055AE C90C SW T0, 48(SP)\r
+BFD055B0 C8EB SW A3, 44(SP)\r
+BFD055B2 C8CA SW A2, 40(SP)\r
+BFD055B4 C8A9 SW A1, 36(SP)\r
+BFD055B6 C888 SW A0, 32(SP)\r
+BFD055B8 C825 SW AT, 20(SP)\r
+BFD055BA 4642 MFLO V0\r
+BFD055BC C859 SW V0, 100(SP)\r
+BFD055BE 4603 MFHI V1\r
+BFD055C0 C878 SW V1, 96(SP)\r
+BFD055C2 0FDD MOVE S8, SP\r
245: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 13, TRUE);\r
-BFD055C4 EE0F LI A0, 15
-BFD055C6 EE8D LI A1, 13
-BFD055C8 EF01 LI A2, 1
-BFD055CA 3A4077E8 JALS jtvic_dis_clr_source
-BFD055CC 0C003A40 SH S2, 3072(ZERO)
-BFD055CE 0C00 NOP
+BFD055C4 EE0F LI A0, 15\r
+BFD055C6 EE8D LI A1, 13\r
+BFD055C8 EF01 LI A2, 1\r
+BFD055CA 3A4077E8 JALS jtvic_dis_clr_source\r
+BFD055CC 0C003A40 SH S2, 3072(ZERO)\r
+BFD055CE 0C00 NOP\r
246: }\r
-BFD055D0 0FBE MOVE SP, S8
-BFD055D2 4859 LW V0, 100(SP)
-BFD055D4 3D7C0002 MTLO V0
-BFD055D6 48783D7C LH T3, 18552(GP)
-BFD055D8 4878 LW V1, 96(SP)
-BFD055DA 2D7C0003 MTHI V1
-BFD055DC 2D7C ANDI V0, A3, 0x40
-BFD055DE 485C LW V0, 112(SP)
-BFD055E0 2D27 ANDI V0, V0, 0xF
-BFD055E2 001340A2 BNEZC V0, 0xBFD0560C
-BFD055E6 4BF7 LW RA, 92(SP)
-BFD055E8 4BD6 LW S8, 88(SP)
-BFD055EA 4B35 LW T9, 84(SP)
-BFD055EC 4B14 LW T8, 80(SP)
-BFD055EE 49F3 LW T7, 76(SP)
-BFD055F0 49D2 LW T6, 72(SP)
-BFD055F2 49B1 LW T5, 68(SP)
-BFD055F4 4990 LW T4, 64(SP)
-BFD055F6 496F LW T3, 60(SP)
-BFD055F8 494E LW T2, 56(SP)
-BFD055FA 492D LW T1, 52(SP)
-BFD055FC 490C LW T0, 48(SP)
-BFD055FE 48EB LW A3, 44(SP)
-BFD05600 48CA LW A2, 40(SP)
-BFD05602 48A9 LW A1, 36(SP)
-BFD05604 4888 LW A0, 32(SP)
-BFD05606 4867 LW V1, 28(SP)
-BFD05608 4846 LW V0, 24(SP)
-BFD0560A 4825 LW AT, 20(SP)
-BFD0560C 477C0000 DI ZERO
-BFD05610 18000000 SLL ZERO, ZERO, 3
-BFD05612 4B5D1800 SB ZERO, 19293(ZERO)
-BFD05614 4B5D LW K0, 116(SP)
-BFD05616 4B7B LW K1, 108(SP)
-BFD05618 02FC034E MTC0 K0, EPC
-BFD0561C 4B5C LW K0, 112(SP)
-BFD0561E 4C3D ADDIU SP, SP, 120
-BFD05620 12FC034C MTC0 K0, SRSCtl
-BFD05622 03BD12FC ADDI S7, GP, 957
-BFD05624 F17C03BD WRPGPR SP, SP
-BFD05626 036CF17C JALX 0xBDF00DB0
-BFD05628 02FC036C MTC0 K1, Status
-BFD0562A 000002FC SLL S7, GP, 0
-BFD0562C F37C0000 ERET
-BFD0562E 4FF5F37C JALX 0xBDF13FD4
+BFD055D0 0FBE MOVE SP, S8\r
+BFD055D2 4859 LW V0, 100(SP)\r
+BFD055D4 3D7C0002 MTLO V0\r
+BFD055D6 48783D7C LH T3, 18552(GP)\r
+BFD055D8 4878 LW V1, 96(SP)\r
+BFD055DA 2D7C0003 MTHI V1\r
+BFD055DC 2D7C ANDI V0, A3, 0x40\r
+BFD055DE 485C LW V0, 112(SP)\r
+BFD055E0 2D27 ANDI V0, V0, 0xF\r
+BFD055E2 001340A2 BNEZC V0, 0xBFD0560C\r
+BFD055E6 4BF7 LW RA, 92(SP)\r
+BFD055E8 4BD6 LW S8, 88(SP)\r
+BFD055EA 4B35 LW T9, 84(SP)\r
+BFD055EC 4B14 LW T8, 80(SP)\r
+BFD055EE 49F3 LW T7, 76(SP)\r
+BFD055F0 49D2 LW T6, 72(SP)\r
+BFD055F2 49B1 LW T5, 68(SP)\r
+BFD055F4 4990 LW T4, 64(SP)\r
+BFD055F6 496F LW T3, 60(SP)\r
+BFD055F8 494E LW T2, 56(SP)\r
+BFD055FA 492D LW T1, 52(SP)\r
+BFD055FC 490C LW T0, 48(SP)\r
+BFD055FE 48EB LW A3, 44(SP)\r
+BFD05600 48CA LW A2, 40(SP)\r
+BFD05602 48A9 LW A1, 36(SP)\r
+BFD05604 4888 LW A0, 32(SP)\r
+BFD05606 4867 LW V1, 28(SP)\r
+BFD05608 4846 LW V0, 24(SP)\r
+BFD0560A 4825 LW AT, 20(SP)\r
+BFD0560C 477C0000 DI ZERO\r
+BFD05610 18000000 SLL ZERO, ZERO, 3\r
+BFD05612 4B5D1800 SB ZERO, 19293(ZERO)\r
+BFD05614 4B5D LW K0, 116(SP)\r
+BFD05616 4B7B LW K1, 108(SP)\r
+BFD05618 02FC034E MTC0 K0, EPC\r
+BFD0561C 4B5C LW K0, 112(SP)\r
+BFD0561E 4C3D ADDIU SP, SP, 120\r
+BFD05620 12FC034C MTC0 K0, SRSCtl\r
+BFD05622 03BD12FC ADDI S7, GP, 957\r
+BFD05624 F17C03BD WRPGPR SP, SP\r
+BFD05626 036CF17C JALX 0xBDF00DB0\r
+BFD05628 02FC036C MTC0 K1, Status\r
+BFD0562A 000002FC SLL S7, GP, 0\r
+BFD0562C F37C0000 ERET\r
+BFD0562E 4FF5F37C JALX 0xBDF13FD4\r
247: \r
248: \r
249: #endif\r
253: /** @}\r
254: */\r
255: \r
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq22.c ----
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq22.c ----\r
1: /*****************************************************************************\r
2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
3: * You may use this software and any derivatives exclusively with\r
38: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
39: girq22_isr(void)\r
40: {\r
-BFD07228 E17C03BD RDPGPR SP, SP
-BFD0722C 00FC036E MFC0 K1, EPC
-BFD0722E 034C00FC INS A3, GP, 13, -12
-BFD07230 10FC034C MFC0 K0, SRSCtl
-BFD07232 4FF110FC ADDI A3, GP, 20465
-BFD07234 4FF1 ADDIU SP, SP, -32
-BFD07236 CB67 SW K1, 28(SP)
-BFD07238 00FC036C MFC0 K1, Status
-BFD0723C CB46 SW K0, 24(SP)
-BFD0723E 00FC034D MFC0 K0, Cause
-BFD07242 CB65 SW K1, 20(SP)
-BFD07244 5040035A SRL K0, K0, 10
-BFD07246 037A5040 ORI V0, ZERO, 890
-BFD07248 7A8C037A INS K1, K0, 10, 6
-BFD0724A 03607A8C ADDIUPC A1, 787296
-BFD0724C 204C0360 INS K1, ZERO, 1, 4
-BFD0724E 036C204C LWC2 V0, 876(T4)
-BFD07250 02FC036C MTC0 K1, Status
-BFD07254 C862 SW V1, 8(SP)
-BFD07256 C841 SW V0, 4(SP)
-BFD07258 4866 LW V1, 24(SP)
-BFD0725A 2DB7 ANDI V1, V1, 0xF
-BFD0725C CBC3 SW S8, 12(SP)
-BFD0725E 0FDD MOVE S8, SP
+BFD07228 E17C03BD RDPGPR SP, SP\r
+BFD0722C 00FC036E MFC0 K1, EPC\r
+BFD0722E 034C00FC INS A3, GP, 13, -12\r
+BFD07230 10FC034C MFC0 K0, SRSCtl\r
+BFD07232 4FF110FC ADDI A3, GP, 20465\r
+BFD07234 4FF1 ADDIU SP, SP, -32\r
+BFD07236 CB67 SW K1, 28(SP)\r
+BFD07238 00FC036C MFC0 K1, Status\r
+BFD0723C CB46 SW K0, 24(SP)\r
+BFD0723E 00FC034D MFC0 K0, Cause\r
+BFD07242 CB65 SW K1, 20(SP)\r
+BFD07244 5040035A SRL K0, K0, 10\r
+BFD07246 037A5040 ORI V0, ZERO, 890\r
+BFD07248 7A8C037A INS K1, K0, 10, 6\r
+BFD0724A 03607A8C ADDIUPC A1, 787296\r
+BFD0724C 204C0360 INS K1, ZERO, 1, 4\r
+BFD0724E 036C204C LWC2 V0, 876(T4)\r
+BFD07250 02FC036C MTC0 K1, Status\r
+BFD07254 C862 SW V1, 8(SP)\r
+BFD07256 C841 SW V0, 4(SP)\r
+BFD07258 4866 LW V1, 24(SP)\r
+BFD0725A 2DB7 ANDI V1, V1, 0xF\r
+BFD0725C CBC3 SW S8, 12(SP)\r
+BFD0725E 0FDD MOVE S8, SP\r
41: JTVIC_GROUP_EN_CLR->w = (1ul<<14);\r
-BFD07260 BFFF41A2 LUI V0, 0xBFFF
-BFD07262 5042BFFF LDC1 F31, 20546(RA)
-BFD07264 C50C5042 ORI V0, V0, -15092
-BFD07268 40003060 ADDIU V1, ZERO, 16384
-BFD0726A E9A04000 BLTZ ZERO, 0xBFD045AE
-BFD0726C E9A0 SW V1, 0(V0)
+BFD07260 BFFF41A2 LUI V0, 0xBFFF\r
+BFD07262 5042BFFF LDC1 F31, 20546(RA)\r
+BFD07264 C50C5042 ORI V0, V0, -15092\r
+BFD07268 40003060 ADDIU V1, ZERO, 16384\r
+BFD0726A E9A04000 BLTZ ZERO, 0xBFD045AE\r
+BFD0726C E9A0 SW V1, 0(V0)\r
42: }\r
-BFD0726E 0FBE MOVE SP, S8
-BFD07270 4846 LW V0, 24(SP)
-BFD07272 2D27 ANDI V0, V0, 0xF
-BFD07274 4BC3 LW S8, 12(SP)
-BFD07276 4862 LW V1, 8(SP)
-BFD07278 4841 LW V0, 4(SP)
-BFD0727A 477C0000 DI ZERO
-BFD0727E 18000000 SLL ZERO, ZERO, 3
-BFD07280 4B471800 SB ZERO, 19271(ZERO)
-BFD07282 4B47 LW K0, 28(SP)
-BFD07284 4B65 LW K1, 20(SP)
-BFD07286 02FC034E MTC0 K0, EPC
-BFD0728A 4B46 LW K0, 24(SP)
-BFD0728C 4C11 ADDIU SP, SP, 32
-BFD0728E 12FC034C MTC0 K0, SRSCtl
-BFD07290 03BD12FC ADDI S7, GP, 957
-BFD07292 F17C03BD WRPGPR SP, SP
-BFD07294 036CF17C JALX 0xBDF00DB0
-BFD07296 02FC036C MTC0 K1, Status
-BFD07298 000002FC SLL S7, GP, 0
-BFD0729A F37C0000 ERET
-BFD0729C 0C00F37C JALX 0xBDF03000
+BFD0726E 0FBE MOVE SP, S8\r
+BFD07270 4846 LW V0, 24(SP)\r
+BFD07272 2D27 ANDI V0, V0, 0xF\r
+BFD07274 4BC3 LW S8, 12(SP)\r
+BFD07276 4862 LW V1, 8(SP)\r
+BFD07278 4841 LW V0, 4(SP)\r
+BFD0727A 477C0000 DI ZERO\r
+BFD0727E 18000000 SLL ZERO, ZERO, 3\r
+BFD07280 4B471800 SB ZERO, 19271(ZERO)\r
+BFD07282 4B47 LW K0, 28(SP)\r
+BFD07284 4B65 LW K1, 20(SP)\r
+BFD07286 02FC034E MTC0 K0, EPC\r
+BFD0728A 4B46 LW K0, 24(SP)\r
+BFD0728C 4C11 ADDIU SP, SP, 32\r
+BFD0728E 12FC034C MTC0 K0, SRSCtl\r
+BFD07290 03BD12FC ADDI S7, GP, 957\r
+BFD07292 F17C03BD WRPGPR SP, SP\r
+BFD07294 036CF17C JALX 0xBDF00DB0\r
+BFD07296 02FC036C MTC0 K1, Status\r
+BFD07298 000002FC SLL S7, GP, 0\r
+BFD0729A F37C0000 ERET\r
+BFD0729C 0C00F37C JALX 0xBDF03000\r
43: \r
44: #else\r
45: \r
110: /** @}\r
111: */\r
112: \r
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq21.c ----
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq21.c ----\r
1: /*****************************************************************************\r
2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
3: * You may use this software and any derivatives exclusively with\r
45: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
46: girq21_isr(void)\r
47: {\r
-BFD071B0 E17C03BD RDPGPR SP, SP
-BFD071B4 00FC036E MFC0 K1, EPC
-BFD071B6 034C00FC INS A3, GP, 13, -12
-BFD071B8 10FC034C MFC0 K0, SRSCtl
-BFD071BA 4FF110FC ADDI A3, GP, 20465
-BFD071BC 4FF1 ADDIU SP, SP, -32
-BFD071BE CB67 SW K1, 28(SP)
-BFD071C0 00FC036C MFC0 K1, Status
-BFD071C4 CB46 SW K0, 24(SP)
-BFD071C6 00FC034D MFC0 K0, Cause
-BFD071CA CB65 SW K1, 20(SP)
-BFD071CC 5040035A SRL K0, K0, 10
-BFD071CE 037A5040 ORI V0, ZERO, 890
-BFD071D0 7A8C037A INS K1, K0, 10, 6
-BFD071D2 03607A8C ADDIUPC A1, 787296
-BFD071D4 204C0360 INS K1, ZERO, 1, 4
-BFD071D6 036C204C LWC2 V0, 876(T4)
-BFD071D8 02FC036C MTC0 K1, Status
-BFD071DC C862 SW V1, 8(SP)
-BFD071DE C841 SW V0, 4(SP)
-BFD071E0 4866 LW V1, 24(SP)
-BFD071E2 2DB7 ANDI V1, V1, 0xF
-BFD071E4 CBC3 SW S8, 12(SP)
-BFD071E6 0FDD MOVE S8, SP
+BFD071B0 E17C03BD RDPGPR SP, SP\r
+BFD071B4 00FC036E MFC0 K1, EPC\r
+BFD071B6 034C00FC INS A3, GP, 13, -12\r
+BFD071B8 10FC034C MFC0 K0, SRSCtl\r
+BFD071BA 4FF110FC ADDI A3, GP, 20465\r
+BFD071BC 4FF1 ADDIU SP, SP, -32\r
+BFD071BE CB67 SW K1, 28(SP)\r
+BFD071C0 00FC036C MFC0 K1, Status\r
+BFD071C4 CB46 SW K0, 24(SP)\r
+BFD071C6 00FC034D MFC0 K0, Cause\r
+BFD071CA CB65 SW K1, 20(SP)\r
+BFD071CC 5040035A SRL K0, K0, 10\r
+BFD071CE 037A5040 ORI V0, ZERO, 890\r
+BFD071D0 7A8C037A INS K1, K0, 10, 6\r
+BFD071D2 03607A8C ADDIUPC A1, 787296\r
+BFD071D4 204C0360 INS K1, ZERO, 1, 4\r
+BFD071D6 036C204C LWC2 V0, 876(T4)\r
+BFD071D8 02FC036C MTC0 K1, Status\r
+BFD071DC C862 SW V1, 8(SP)\r
+BFD071DE C841 SW V0, 4(SP)\r
+BFD071E0 4866 LW V1, 24(SP)\r
+BFD071E2 2DB7 ANDI V1, V1, 0xF\r
+BFD071E4 CBC3 SW S8, 12(SP)\r
+BFD071E6 0FDD MOVE S8, SP\r
48: JTVIC_GROUP_EN_CLR->w = (1ul<<13);\r
-BFD071E8 BFFF41A2 LUI V0, 0xBFFF
-BFD071EA 5042BFFF LDC1 F31, 20546(RA)
-BFD071EC C50C5042 ORI V0, V0, -15092
-BFD071F0 20003060 ADDIU V1, ZERO, 8192
-BFD071F4 E9A0 SW V1, 0(V0)
+BFD071E8 BFFF41A2 LUI V0, 0xBFFF\r
+BFD071EA 5042BFFF LDC1 F31, 20546(RA)\r
+BFD071EC C50C5042 ORI V0, V0, -15092\r
+BFD071F0 20003060 ADDIU V1, ZERO, 8192\r
+BFD071F4 E9A0 SW V1, 0(V0)\r
49: }\r
-BFD071F6 0FBE MOVE SP, S8
-BFD071F8 4846 LW V0, 24(SP)
-BFD071FA 2D27 ANDI V0, V0, 0xF
-BFD071FC 4BC3 LW S8, 12(SP)
-BFD071FE 4862 LW V1, 8(SP)
-BFD07200 4841 LW V0, 4(SP)
-BFD07202 477C0000 DI ZERO
-BFD07206 18000000 SLL ZERO, ZERO, 3
-BFD07208 4B471800 SB ZERO, 19271(ZERO)
-BFD0720A 4B47 LW K0, 28(SP)
-BFD0720C 4B65 LW K1, 20(SP)
-BFD0720E 02FC034E MTC0 K0, EPC
-BFD07212 4B46 LW K0, 24(SP)
-BFD07214 4C11 ADDIU SP, SP, 32
-BFD07216 12FC034C MTC0 K0, SRSCtl
-BFD07218 03BD12FC ADDI S7, GP, 957
-BFD0721A F17C03BD WRPGPR SP, SP
-BFD0721C 036CF17C JALX 0xBDF00DB0
-BFD0721E 02FC036C MTC0 K1, Status
-BFD07220 000002FC SLL S7, GP, 0
-BFD07222 F37C0000 ERET
-BFD07224 0C00F37C JALX 0xBDF03000
+BFD071F6 0FBE MOVE SP, S8\r
+BFD071F8 4846 LW V0, 24(SP)\r
+BFD071FA 2D27 ANDI V0, V0, 0xF\r
+BFD071FC 4BC3 LW S8, 12(SP)\r
+BFD071FE 4862 LW V1, 8(SP)\r
+BFD07200 4841 LW V0, 4(SP)\r
+BFD07202 477C0000 DI ZERO\r
+BFD07206 18000000 SLL ZERO, ZERO, 3\r
+BFD07208 4B471800 SB ZERO, 19271(ZERO)\r
+BFD0720A 4B47 LW K0, 28(SP)\r
+BFD0720C 4B65 LW K1, 20(SP)\r
+BFD0720E 02FC034E MTC0 K0, EPC\r
+BFD07212 4B46 LW K0, 24(SP)\r
+BFD07214 4C11 ADDIU SP, SP, 32\r
+BFD07216 12FC034C MTC0 K0, SRSCtl\r
+BFD07218 03BD12FC ADDI S7, GP, 957\r
+BFD0721A F17C03BD WRPGPR SP, SP\r
+BFD0721C 036CF17C JALX 0xBDF00DB0\r
+BFD0721E 02FC036C MTC0 K1, Status\r
+BFD07220 000002FC SLL S7, GP, 0\r
+BFD07222 F37C0000 ERET\r
+BFD07224 0C00F37C JALX 0xBDF03000\r
50: \r
51: #else\r
52: \r
62: /** @}\r
63: */\r
64: \r
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq20.c ----
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq20.c ----\r
1: /*****************************************************************************\r
2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
3: * You may use this software and any derivatives exclusively with\r
38: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
39: girq20_isr(void)\r
40: {\r
-BFD07138 E17C03BD RDPGPR SP, SP
-BFD0713C 00FC036E MFC0 K1, EPC
-BFD0713E 034C00FC INS A3, GP, 13, -12
-BFD07140 10FC034C MFC0 K0, SRSCtl
-BFD07142 4FF110FC ADDI A3, GP, 20465
-BFD07144 4FF1 ADDIU SP, SP, -32
-BFD07146 CB67 SW K1, 28(SP)
-BFD07148 00FC036C MFC0 K1, Status
-BFD0714C CB46 SW K0, 24(SP)
-BFD0714E 00FC034D MFC0 K0, Cause
-BFD07152 CB65 SW K1, 20(SP)
-BFD07154 5040035A SRL K0, K0, 10
-BFD07156 037A5040 ORI V0, ZERO, 890
-BFD07158 7A8C037A INS K1, K0, 10, 6
-BFD0715A 03607A8C ADDIUPC A1, 787296
-BFD0715C 204C0360 INS K1, ZERO, 1, 4
-BFD0715E 036C204C LWC2 V0, 876(T4)
-BFD07160 02FC036C MTC0 K1, Status
-BFD07164 C862 SW V1, 8(SP)
-BFD07166 C841 SW V0, 4(SP)
-BFD07168 4866 LW V1, 24(SP)
-BFD0716A 2DB7 ANDI V1, V1, 0xF
-BFD0716C CBC3 SW S8, 12(SP)
-BFD0716E 0FDD MOVE S8, SP
+BFD07138 E17C03BD RDPGPR SP, SP\r
+BFD0713C 00FC036E MFC0 K1, EPC\r
+BFD0713E 034C00FC INS A3, GP, 13, -12\r
+BFD07140 10FC034C MFC0 K0, SRSCtl\r
+BFD07142 4FF110FC ADDI A3, GP, 20465\r
+BFD07144 4FF1 ADDIU SP, SP, -32\r
+BFD07146 CB67 SW K1, 28(SP)\r
+BFD07148 00FC036C MFC0 K1, Status\r
+BFD0714C CB46 SW K0, 24(SP)\r
+BFD0714E 00FC034D MFC0 K0, Cause\r
+BFD07152 CB65 SW K1, 20(SP)\r
+BFD07154 5040035A SRL K0, K0, 10\r
+BFD07156 037A5040 ORI V0, ZERO, 890\r
+BFD07158 7A8C037A INS K1, K0, 10, 6\r
+BFD0715A 03607A8C ADDIUPC A1, 787296\r
+BFD0715C 204C0360 INS K1, ZERO, 1, 4\r
+BFD0715E 036C204C LWC2 V0, 876(T4)\r
+BFD07160 02FC036C MTC0 K1, Status\r
+BFD07164 C862 SW V1, 8(SP)\r
+BFD07166 C841 SW V0, 4(SP)\r
+BFD07168 4866 LW V1, 24(SP)\r
+BFD0716A 2DB7 ANDI V1, V1, 0xF\r
+BFD0716C CBC3 SW S8, 12(SP)\r
+BFD0716E 0FDD MOVE S8, SP\r
41: JTVIC_GROUP_EN_CLR->w = (1ul<<12);\r
-BFD07170 BFFF41A2 LUI V0, 0xBFFF
-BFD07172 5042BFFF LDC1 F31, 20546(RA)
-BFD07174 C50C5042 ORI V0, V0, -15092
-BFD07178 10003060 ADDIU V1, ZERO, 4096
-BFD0717A E9A01000 ADDI ZERO, ZERO, -5728
-BFD0717C E9A0 SW V1, 0(V0)
+BFD07170 BFFF41A2 LUI V0, 0xBFFF\r
+BFD07172 5042BFFF LDC1 F31, 20546(RA)\r
+BFD07174 C50C5042 ORI V0, V0, -15092\r
+BFD07178 10003060 ADDIU V1, ZERO, 4096\r
+BFD0717A E9A01000 ADDI ZERO, ZERO, -5728\r
+BFD0717C E9A0 SW V1, 0(V0)\r
42: }\r
-BFD0717E 0FBE MOVE SP, S8
-BFD07180 4846 LW V0, 24(SP)
-BFD07182 2D27 ANDI V0, V0, 0xF
-BFD07184 4BC3 LW S8, 12(SP)
-BFD07186 4862 LW V1, 8(SP)
-BFD07188 4841 LW V0, 4(SP)
-BFD0718A 477C0000 DI ZERO
-BFD0718E 18000000 SLL ZERO, ZERO, 3
-BFD07190 4B471800 SB ZERO, 19271(ZERO)
-BFD07192 4B47 LW K0, 28(SP)
-BFD07194 4B65 LW K1, 20(SP)
-BFD07196 02FC034E MTC0 K0, EPC
-BFD0719A 4B46 LW K0, 24(SP)
-BFD0719C 4C11 ADDIU SP, SP, 32
-BFD0719E 12FC034C MTC0 K0, SRSCtl
-BFD071A0 03BD12FC ADDI S7, GP, 957
-BFD071A2 F17C03BD WRPGPR SP, SP
-BFD071A4 036CF17C JALX 0xBDF00DB0
-BFD071A6 02FC036C MTC0 K1, Status
-BFD071A8 000002FC SLL S7, GP, 0
-BFD071AA F37C0000 ERET
-BFD071AC 0C00F37C JALX 0xBDF03000
+BFD0717E 0FBE MOVE SP, S8\r
+BFD07180 4846 LW V0, 24(SP)\r
+BFD07182 2D27 ANDI V0, V0, 0xF\r
+BFD07184 4BC3 LW S8, 12(SP)\r
+BFD07186 4862 LW V1, 8(SP)\r
+BFD07188 4841 LW V0, 4(SP)\r
+BFD0718A 477C0000 DI ZERO\r
+BFD0718E 18000000 SLL ZERO, ZERO, 3\r
+BFD07190 4B471800 SB ZERO, 19271(ZERO)\r
+BFD07192 4B47 LW K0, 28(SP)\r
+BFD07194 4B65 LW K1, 20(SP)\r
+BFD07196 02FC034E MTC0 K0, EPC\r
+BFD0719A 4B46 LW K0, 24(SP)\r
+BFD0719C 4C11 ADDIU SP, SP, 32\r
+BFD0719E 12FC034C MTC0 K0, SRSCtl\r
+BFD071A0 03BD12FC ADDI S7, GP, 957\r
+BFD071A2 F17C03BD WRPGPR SP, SP\r
+BFD071A4 036CF17C JALX 0xBDF00DB0\r
+BFD071A6 02FC036C MTC0 K1, Status\r
+BFD071A8 000002FC SLL S7, GP, 0\r
+BFD071AA F37C0000 ERET\r
+BFD071AC 0C00F37C JALX 0xBDF03000\r
43: \r
44: #else\r
45: \r
86: /** @}\r
87: */\r
88: \r
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq19.c ----
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq19.c ----\r
1: /*****************************************************************************\r
2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
3: * You may use this software and any derivatives exclusively with\r
38: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
39: girq19_isr(void)\r
40: {\r
-BFD070C0 E17C03BD RDPGPR SP, SP
-BFD070C4 00FC036E MFC0 K1, EPC
-BFD070C6 034C00FC INS A3, GP, 13, -12
-BFD070C8 10FC034C MFC0 K0, SRSCtl
-BFD070CA 4FF110FC ADDI A3, GP, 20465
-BFD070CC 4FF1 ADDIU SP, SP, -32
-BFD070CE CB67 SW K1, 28(SP)
-BFD070D0 00FC036C MFC0 K1, Status
-BFD070D4 CB46 SW K0, 24(SP)
-BFD070D6 00FC034D MFC0 K0, Cause
-BFD070DA CB65 SW K1, 20(SP)
-BFD070DC 5040035A SRL K0, K0, 10
-BFD070DE 037A5040 ORI V0, ZERO, 890
-BFD070E0 7A8C037A INS K1, K0, 10, 6
-BFD070E2 03607A8C ADDIUPC A1, 787296
-BFD070E4 204C0360 INS K1, ZERO, 1, 4
-BFD070E6 036C204C LWC2 V0, 876(T4)
-BFD070E8 02FC036C MTC0 K1, Status
-BFD070EC C862 SW V1, 8(SP)
-BFD070EE C841 SW V0, 4(SP)
-BFD070F0 4866 LW V1, 24(SP)
-BFD070F2 2DB7 ANDI V1, V1, 0xF
-BFD070F4 CBC3 SW S8, 12(SP)
-BFD070F6 0FDD MOVE S8, SP
+BFD070C0 E17C03BD RDPGPR SP, SP\r
+BFD070C4 00FC036E MFC0 K1, EPC\r
+BFD070C6 034C00FC INS A3, GP, 13, -12\r
+BFD070C8 10FC034C MFC0 K0, SRSCtl\r
+BFD070CA 4FF110FC ADDI A3, GP, 20465\r
+BFD070CC 4FF1 ADDIU SP, SP, -32\r
+BFD070CE CB67 SW K1, 28(SP)\r
+BFD070D0 00FC036C MFC0 K1, Status\r
+BFD070D4 CB46 SW K0, 24(SP)\r
+BFD070D6 00FC034D MFC0 K0, Cause\r
+BFD070DA CB65 SW K1, 20(SP)\r
+BFD070DC 5040035A SRL K0, K0, 10\r
+BFD070DE 037A5040 ORI V0, ZERO, 890\r
+BFD070E0 7A8C037A INS K1, K0, 10, 6\r
+BFD070E2 03607A8C ADDIUPC A1, 787296\r
+BFD070E4 204C0360 INS K1, ZERO, 1, 4\r
+BFD070E6 036C204C LWC2 V0, 876(T4)\r
+BFD070E8 02FC036C MTC0 K1, Status\r
+BFD070EC C862 SW V1, 8(SP)\r
+BFD070EE C841 SW V0, 4(SP)\r
+BFD070F0 4866 LW V1, 24(SP)\r
+BFD070F2 2DB7 ANDI V1, V1, 0xF\r
+BFD070F4 CBC3 SW S8, 12(SP)\r
+BFD070F6 0FDD MOVE S8, SP\r
41: JTVIC_GROUP_EN_CLR->w = (1ul<<11);\r
-BFD070F8 BFFF41A2 LUI V0, 0xBFFF
-BFD070FA 5042BFFF LDC1 F31, 20546(RA)
-BFD070FC C50C5042 ORI V0, V0, -15092
-BFD07100 08003060 ADDIU V1, ZERO, 2048
-BFD07102 0800 LBU S0, 0(S0)
-BFD07104 E9A0 SW V1, 0(V0)
+BFD070F8 BFFF41A2 LUI V0, 0xBFFF\r
+BFD070FA 5042BFFF LDC1 F31, 20546(RA)\r
+BFD070FC C50C5042 ORI V0, V0, -15092\r
+BFD07100 08003060 ADDIU V1, ZERO, 2048\r
+BFD07102 0800 LBU S0, 0(S0)\r
+BFD07104 E9A0 SW V1, 0(V0)\r
42: }\r
-BFD07106 0FBE MOVE SP, S8
-BFD07108 4846 LW V0, 24(SP)
-BFD0710A 2D27 ANDI V0, V0, 0xF
-BFD0710C 4BC3 LW S8, 12(SP)
-BFD0710E 4862 LW V1, 8(SP)
-BFD07110 4841 LW V0, 4(SP)
-BFD07112 477C0000 DI ZERO
-BFD07116 18000000 SLL ZERO, ZERO, 3
-BFD07118 4B471800 SB ZERO, 19271(ZERO)
-BFD0711A 4B47 LW K0, 28(SP)
-BFD0711C 4B65 LW K1, 20(SP)
-BFD0711E 02FC034E MTC0 K0, EPC
-BFD07122 4B46 LW K0, 24(SP)
-BFD07124 4C11 ADDIU SP, SP, 32
-BFD07126 12FC034C MTC0 K0, SRSCtl
-BFD07128 03BD12FC ADDI S7, GP, 957
-BFD0712A F17C03BD WRPGPR SP, SP
-BFD0712C 036CF17C JALX 0xBDF00DB0
-BFD0712E 02FC036C MTC0 K1, Status
-BFD07130 000002FC SLL S7, GP, 0
-BFD07132 F37C0000 ERET
-BFD07134 0C00F37C JALX 0xBDF03000
+BFD07106 0FBE MOVE SP, S8\r
+BFD07108 4846 LW V0, 24(SP)\r
+BFD0710A 2D27 ANDI V0, V0, 0xF\r
+BFD0710C 4BC3 LW S8, 12(SP)\r
+BFD0710E 4862 LW V1, 8(SP)\r
+BFD07110 4841 LW V0, 4(SP)\r
+BFD07112 477C0000 DI ZERO\r
+BFD07116 18000000 SLL ZERO, ZERO, 3\r
+BFD07118 4B471800 SB ZERO, 19271(ZERO)\r
+BFD0711A 4B47 LW K0, 28(SP)\r
+BFD0711C 4B65 LW K1, 20(SP)\r
+BFD0711E 02FC034E MTC0 K0, EPC\r
+BFD07122 4B46 LW K0, 24(SP)\r
+BFD07124 4C11 ADDIU SP, SP, 32\r
+BFD07126 12FC034C MTC0 K0, SRSCtl\r
+BFD07128 03BD12FC ADDI S7, GP, 957\r
+BFD0712A F17C03BD WRPGPR SP, SP\r
+BFD0712C 036CF17C JALX 0xBDF00DB0\r
+BFD0712E 02FC036C MTC0 K1, Status\r
+BFD07130 000002FC SLL S7, GP, 0\r
+BFD07132 F37C0000 ERET\r
+BFD07134 0C00F37C JALX 0xBDF03000\r
43: \r
44: #else\r
45: \r
104: /** @}\r
105: */\r
106: \r
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq18.c ----
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq18.c ----\r
1: /*****************************************************************************\r
2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
3: * You may use this software and any derivatives exclusively with\r
38: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
39: girq18_isr(void)\r
40: {\r
-BFD07048 E17C03BD RDPGPR SP, SP
-BFD0704C 00FC036E MFC0 K1, EPC
-BFD0704E 034C00FC INS A3, GP, 13, -12
-BFD07050 10FC034C MFC0 K0, SRSCtl
-BFD07052 4FF110FC ADDI A3, GP, 20465
-BFD07054 4FF1 ADDIU SP, SP, -32
-BFD07056 CB67 SW K1, 28(SP)
-BFD07058 00FC036C MFC0 K1, Status
-BFD0705C CB46 SW K0, 24(SP)
-BFD0705E 00FC034D MFC0 K0, Cause
-BFD07062 CB65 SW K1, 20(SP)
-BFD07064 5040035A SRL K0, K0, 10
-BFD07066 037A5040 ORI V0, ZERO, 890
-BFD07068 7A8C037A INS K1, K0, 10, 6
-BFD0706A 03607A8C ADDIUPC A1, 787296
-BFD0706C 204C0360 INS K1, ZERO, 1, 4
-BFD0706E 036C204C LWC2 V0, 876(T4)
-BFD07070 02FC036C MTC0 K1, Status
-BFD07074 C862 SW V1, 8(SP)
-BFD07076 C841 SW V0, 4(SP)
-BFD07078 4866 LW V1, 24(SP)
-BFD0707A 2DB7 ANDI V1, V1, 0xF
-BFD0707C CBC3 SW S8, 12(SP)
-BFD0707E 0FDD MOVE S8, SP
+BFD07048 E17C03BD RDPGPR SP, SP\r
+BFD0704C 00FC036E MFC0 K1, EPC\r
+BFD0704E 034C00FC INS A3, GP, 13, -12\r
+BFD07050 10FC034C MFC0 K0, SRSCtl\r
+BFD07052 4FF110FC ADDI A3, GP, 20465\r
+BFD07054 4FF1 ADDIU SP, SP, -32\r
+BFD07056 CB67 SW K1, 28(SP)\r
+BFD07058 00FC036C MFC0 K1, Status\r
+BFD0705C CB46 SW K0, 24(SP)\r
+BFD0705E 00FC034D MFC0 K0, Cause\r
+BFD07062 CB65 SW K1, 20(SP)\r
+BFD07064 5040035A SRL K0, K0, 10\r
+BFD07066 037A5040 ORI V0, ZERO, 890\r
+BFD07068 7A8C037A INS K1, K0, 10, 6\r
+BFD0706A 03607A8C ADDIUPC A1, 787296\r
+BFD0706C 204C0360 INS K1, ZERO, 1, 4\r
+BFD0706E 036C204C LWC2 V0, 876(T4)\r
+BFD07070 02FC036C MTC0 K1, Status\r
+BFD07074 C862 SW V1, 8(SP)\r
+BFD07076 C841 SW V0, 4(SP)\r
+BFD07078 4866 LW V1, 24(SP)\r
+BFD0707A 2DB7 ANDI V1, V1, 0xF\r
+BFD0707C CBC3 SW S8, 12(SP)\r
+BFD0707E 0FDD MOVE S8, SP\r
41: JTVIC_GROUP_EN_CLR->w = (1ul<<10);\r
-BFD07080 BFFF41A2 LUI V0, 0xBFFF
-BFD07082 5042BFFF LDC1 F31, 20546(RA)
-BFD07084 C50C5042 ORI V0, V0, -15092
-BFD07088 04003060 ADDIU V1, ZERO, 1024
-BFD0708A 0400 ADDU S0, S0, S0
-BFD0708C E9A0 SW V1, 0(V0)
+BFD07080 BFFF41A2 LUI V0, 0xBFFF\r
+BFD07082 5042BFFF LDC1 F31, 20546(RA)\r
+BFD07084 C50C5042 ORI V0, V0, -15092\r
+BFD07088 04003060 ADDIU V1, ZERO, 1024\r
+BFD0708A 0400 ADDU S0, S0, S0\r
+BFD0708C E9A0 SW V1, 0(V0)\r
42: }\r
-BFD0708E 0FBE MOVE SP, S8
-BFD07090 4846 LW V0, 24(SP)
-BFD07092 2D27 ANDI V0, V0, 0xF
-BFD07094 4BC3 LW S8, 12(SP)
-BFD07096 4862 LW V1, 8(SP)
-BFD07098 4841 LW V0, 4(SP)
-BFD0709A 477C0000 DI ZERO
-BFD0709E 18000000 SLL ZERO, ZERO, 3
-BFD070A0 4B471800 SB ZERO, 19271(ZERO)
-BFD070A2 4B47 LW K0, 28(SP)
-BFD070A4 4B65 LW K1, 20(SP)
-BFD070A6 02FC034E MTC0 K0, EPC
-BFD070AA 4B46 LW K0, 24(SP)
-BFD070AC 4C11 ADDIU SP, SP, 32
-BFD070AE 12FC034C MTC0 K0, SRSCtl
-BFD070B0 03BD12FC ADDI S7, GP, 957
-BFD070B2 F17C03BD WRPGPR SP, SP
-BFD070B4 036CF17C JALX 0xBDF00DB0
-BFD070B6 02FC036C MTC0 K1, Status
-BFD070B8 000002FC SLL S7, GP, 0
-BFD070BA F37C0000 ERET
-BFD070BC 0C00F37C JALX 0xBDF03000
+BFD0708E 0FBE MOVE SP, S8\r
+BFD07090 4846 LW V0, 24(SP)\r
+BFD07092 2D27 ANDI V0, V0, 0xF\r
+BFD07094 4BC3 LW S8, 12(SP)\r
+BFD07096 4862 LW V1, 8(SP)\r
+BFD07098 4841 LW V0, 4(SP)\r
+BFD0709A 477C0000 DI ZERO\r
+BFD0709E 18000000 SLL ZERO, ZERO, 3\r
+BFD070A0 4B471800 SB ZERO, 19271(ZERO)\r
+BFD070A2 4B47 LW K0, 28(SP)\r
+BFD070A4 4B65 LW K1, 20(SP)\r
+BFD070A6 02FC034E MTC0 K0, EPC\r
+BFD070AA 4B46 LW K0, 24(SP)\r
+BFD070AC 4C11 ADDIU SP, SP, 32\r
+BFD070AE 12FC034C MTC0 K0, SRSCtl\r
+BFD070B0 03BD12FC ADDI S7, GP, 957\r
+BFD070B2 F17C03BD WRPGPR SP, SP\r
+BFD070B4 036CF17C JALX 0xBDF00DB0\r
+BFD070B6 02FC036C MTC0 K1, Status\r
+BFD070B8 000002FC SLL S7, GP, 0\r
+BFD070BA F37C0000 ERET\r
+BFD070BC 0C00F37C JALX 0xBDF03000\r
43: \r
44: #else\r
45: \r
55: /** @}\r
56: */\r
57: \r
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq17.c ----
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq17.c ----\r
1: /*****************************************************************************\r
2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
3: * You may use this software and any derivatives exclusively with\r
38: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
39: girq17_isr(void)\r
40: {\r
-BFD06FD0 E17C03BD RDPGPR SP, SP
-BFD06FD4 00FC036E MFC0 K1, EPC
-BFD06FD6 034C00FC INS A3, GP, 13, -12
-BFD06FD8 10FC034C MFC0 K0, SRSCtl
-BFD06FDA 4FF110FC ADDI A3, GP, 20465
-BFD06FDC 4FF1 ADDIU SP, SP, -32
-BFD06FDE CB67 SW K1, 28(SP)
-BFD06FE0 00FC036C MFC0 K1, Status
-BFD06FE4 CB46 SW K0, 24(SP)
-BFD06FE6 00FC034D MFC0 K0, Cause
-BFD06FEA CB65 SW K1, 20(SP)
-BFD06FEC 5040035A SRL K0, K0, 10
-BFD06FEE 037A5040 ORI V0, ZERO, 890
-BFD06FF0 7A8C037A INS K1, K0, 10, 6
-BFD06FF2 03607A8C ADDIUPC A1, 787296
-BFD06FF4 204C0360 INS K1, ZERO, 1, 4
-BFD06FF6 036C204C LWC2 V0, 876(T4)
-BFD06FF8 02FC036C MTC0 K1, Status
-BFD06FFC C862 SW V1, 8(SP)
-BFD06FFE C841 SW V0, 4(SP)
-BFD07000 4866 LW V1, 24(SP)
-BFD07002 2DB7 ANDI V1, V1, 0xF
-BFD07004 CBC3 SW S8, 12(SP)
-BFD07006 0FDD MOVE S8, SP
+BFD06FD0 E17C03BD RDPGPR SP, SP\r
+BFD06FD4 00FC036E MFC0 K1, EPC\r
+BFD06FD6 034C00FC INS A3, GP, 13, -12\r
+BFD06FD8 10FC034C MFC0 K0, SRSCtl\r
+BFD06FDA 4FF110FC ADDI A3, GP, 20465\r
+BFD06FDC 4FF1 ADDIU SP, SP, -32\r
+BFD06FDE CB67 SW K1, 28(SP)\r
+BFD06FE0 00FC036C MFC0 K1, Status\r
+BFD06FE4 CB46 SW K0, 24(SP)\r
+BFD06FE6 00FC034D MFC0 K0, Cause\r
+BFD06FEA CB65 SW K1, 20(SP)\r
+BFD06FEC 5040035A SRL K0, K0, 10\r
+BFD06FEE 037A5040 ORI V0, ZERO, 890\r
+BFD06FF0 7A8C037A INS K1, K0, 10, 6\r
+BFD06FF2 03607A8C ADDIUPC A1, 787296\r
+BFD06FF4 204C0360 INS K1, ZERO, 1, 4\r
+BFD06FF6 036C204C LWC2 V0, 876(T4)\r
+BFD06FF8 02FC036C MTC0 K1, Status\r
+BFD06FFC C862 SW V1, 8(SP)\r
+BFD06FFE C841 SW V0, 4(SP)\r
+BFD07000 4866 LW V1, 24(SP)\r
+BFD07002 2DB7 ANDI V1, V1, 0xF\r
+BFD07004 CBC3 SW S8, 12(SP)\r
+BFD07006 0FDD MOVE S8, SP\r
41: JTVIC_GROUP_EN_CLR->w = (1ul<<9);\r
-BFD07008 BFFF41A2 LUI V0, 0xBFFF
-BFD0700A 5042BFFF LDC1 F31, 20546(RA)
-BFD0700C C50C5042 ORI V0, V0, -15092
-BFD07010 02003060 ADDIU V1, ZERO, 512
-BFD07014 E9A0 SW V1, 0(V0)
+BFD07008 BFFF41A2 LUI V0, 0xBFFF\r
+BFD0700A 5042BFFF LDC1 F31, 20546(RA)\r
+BFD0700C C50C5042 ORI V0, V0, -15092\r
+BFD07010 02003060 ADDIU V1, ZERO, 512\r
+BFD07014 E9A0 SW V1, 0(V0)\r
42: }\r
-BFD07016 0FBE MOVE SP, S8
-BFD07018 4846 LW V0, 24(SP)
-BFD0701A 2D27 ANDI V0, V0, 0xF
-BFD0701C 4BC3 LW S8, 12(SP)
-BFD0701E 4862 LW V1, 8(SP)
-BFD07020 4841 LW V0, 4(SP)
-BFD07022 477C0000 DI ZERO
-BFD07026 18000000 SLL ZERO, ZERO, 3
-BFD07028 4B471800 SB ZERO, 19271(ZERO)
-BFD0702A 4B47 LW K0, 28(SP)
-BFD0702C 4B65 LW K1, 20(SP)
-BFD0702E 02FC034E MTC0 K0, EPC
-BFD07032 4B46 LW K0, 24(SP)
-BFD07034 4C11 ADDIU SP, SP, 32
-BFD07036 12FC034C MTC0 K0, SRSCtl
-BFD07038 03BD12FC ADDI S7, GP, 957
-BFD0703A F17C03BD WRPGPR SP, SP
-BFD0703C 036CF17C JALX 0xBDF00DB0
-BFD0703E 02FC036C MTC0 K1, Status
-BFD07040 000002FC SLL S7, GP, 0
-BFD07042 F37C0000 ERET
-BFD07044 0C00F37C JALX 0xBDF03000
+BFD07016 0FBE MOVE SP, S8\r
+BFD07018 4846 LW V0, 24(SP)\r
+BFD0701A 2D27 ANDI V0, V0, 0xF\r
+BFD0701C 4BC3 LW S8, 12(SP)\r
+BFD0701E 4862 LW V1, 8(SP)\r
+BFD07020 4841 LW V0, 4(SP)\r
+BFD07022 477C0000 DI ZERO\r
+BFD07026 18000000 SLL ZERO, ZERO, 3\r
+BFD07028 4B471800 SB ZERO, 19271(ZERO)\r
+BFD0702A 4B47 LW K0, 28(SP)\r
+BFD0702C 4B65 LW K1, 20(SP)\r
+BFD0702E 02FC034E MTC0 K0, EPC\r
+BFD07032 4B46 LW K0, 24(SP)\r
+BFD07034 4C11 ADDIU SP, SP, 32\r
+BFD07036 12FC034C MTC0 K0, SRSCtl\r
+BFD07038 03BD12FC ADDI S7, GP, 957\r
+BFD0703A F17C03BD WRPGPR SP, SP\r
+BFD0703C 036CF17C JALX 0xBDF00DB0\r
+BFD0703E 02FC036C MTC0 K1, Status\r
+BFD07040 000002FC SLL S7, GP, 0\r
+BFD07042 F37C0000 ERET\r
+BFD07044 0C00F37C JALX 0xBDF03000\r
43: \r
44: #else\r
45: \r
126: /** @}\r
127: */\r
128: \r
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq16.c ----
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq16.c ----\r
1: /*****************************************************************************\r
2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
3: * You may use this software and any derivatives exclusively with\r
39: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
40: girq16_isr(void)\r
41: {\r
-BFD06F58 E17C03BD RDPGPR SP, SP
-BFD06F5C 00FC036E MFC0 K1, EPC
-BFD06F5E 034C00FC INS A3, GP, 13, -12
-BFD06F60 10FC034C MFC0 K0, SRSCtl
-BFD06F62 4FF110FC ADDI A3, GP, 20465
-BFD06F64 4FF1 ADDIU SP, SP, -32
-BFD06F66 CB67 SW K1, 28(SP)
-BFD06F68 00FC036C MFC0 K1, Status
-BFD06F6C CB46 SW K0, 24(SP)
-BFD06F6E 00FC034D MFC0 K0, Cause
-BFD06F72 CB65 SW K1, 20(SP)
-BFD06F74 5040035A SRL K0, K0, 10
-BFD06F76 037A5040 ORI V0, ZERO, 890
-BFD06F78 7A8C037A INS K1, K0, 10, 6
-BFD06F7A 03607A8C ADDIUPC A1, 787296
-BFD06F7C 204C0360 INS K1, ZERO, 1, 4
-BFD06F7E 036C204C LWC2 V0, 876(T4)
-BFD06F80 02FC036C MTC0 K1, Status
-BFD06F84 C862 SW V1, 8(SP)
-BFD06F86 C841 SW V0, 4(SP)
-BFD06F88 4866 LW V1, 24(SP)
-BFD06F8A 2DB7 ANDI V1, V1, 0xF
-BFD06F8C CBC3 SW S8, 12(SP)
-BFD06F8E 0FDD MOVE S8, SP
+BFD06F58 E17C03BD RDPGPR SP, SP\r
+BFD06F5C 00FC036E MFC0 K1, EPC\r
+BFD06F5E 034C00FC INS A3, GP, 13, -12\r
+BFD06F60 10FC034C MFC0 K0, SRSCtl\r
+BFD06F62 4FF110FC ADDI A3, GP, 20465\r
+BFD06F64 4FF1 ADDIU SP, SP, -32\r
+BFD06F66 CB67 SW K1, 28(SP)\r
+BFD06F68 00FC036C MFC0 K1, Status\r
+BFD06F6C CB46 SW K0, 24(SP)\r
+BFD06F6E 00FC034D MFC0 K0, Cause\r
+BFD06F72 CB65 SW K1, 20(SP)\r
+BFD06F74 5040035A SRL K0, K0, 10\r
+BFD06F76 037A5040 ORI V0, ZERO, 890\r
+BFD06F78 7A8C037A INS K1, K0, 10, 6\r
+BFD06F7A 03607A8C ADDIUPC A1, 787296\r
+BFD06F7C 204C0360 INS K1, ZERO, 1, 4\r
+BFD06F7E 036C204C LWC2 V0, 876(T4)\r
+BFD06F80 02FC036C MTC0 K1, Status\r
+BFD06F84 C862 SW V1, 8(SP)\r
+BFD06F86 C841 SW V0, 4(SP)\r
+BFD06F88 4866 LW V1, 24(SP)\r
+BFD06F8A 2DB7 ANDI V1, V1, 0xF\r
+BFD06F8C CBC3 SW S8, 12(SP)\r
+BFD06F8E 0FDD MOVE S8, SP\r
42: JTVIC_GROUP_EN_CLR->w = (1ul<<8);\r
-BFD06F90 BFFF41A2 LUI V0, 0xBFFF
-BFD06F92 5042BFFF LDC1 F31, 20546(RA)
-BFD06F94 C50C5042 ORI V0, V0, -15092
-BFD06F98 01003060 ADDIU V1, ZERO, 256
-BFD06F9C E9A0 SW V1, 0(V0)
+BFD06F90 BFFF41A2 LUI V0, 0xBFFF\r
+BFD06F92 5042BFFF LDC1 F31, 20546(RA)\r
+BFD06F94 C50C5042 ORI V0, V0, -15092\r
+BFD06F98 01003060 ADDIU V1, ZERO, 256\r
+BFD06F9C E9A0 SW V1, 0(V0)\r
43: }\r
-BFD06F9E 0FBE MOVE SP, S8
-BFD06FA0 4846 LW V0, 24(SP)
-BFD06FA2 2D27 ANDI V0, V0, 0xF
-BFD06FA4 4BC3 LW S8, 12(SP)
-BFD06FA6 4862 LW V1, 8(SP)
-BFD06FA8 4841 LW V0, 4(SP)
-BFD06FAA 477C0000 DI ZERO
-BFD06FAE 18000000 SLL ZERO, ZERO, 3
-BFD06FB0 4B471800 SB ZERO, 19271(ZERO)
-BFD06FB2 4B47 LW K0, 28(SP)
-BFD06FB4 4B65 LW K1, 20(SP)
-BFD06FB6 02FC034E MTC0 K0, EPC
-BFD06FBA 4B46 LW K0, 24(SP)
-BFD06FBC 4C11 ADDIU SP, SP, 32
-BFD06FBE 12FC034C MTC0 K0, SRSCtl
-BFD06FC0 03BD12FC ADDI S7, GP, 957
-BFD06FC2 F17C03BD WRPGPR SP, SP
-BFD06FC4 036CF17C JALX 0xBDF00DB0
-BFD06FC6 02FC036C MTC0 K1, Status
-BFD06FC8 000002FC SLL S7, GP, 0
-BFD06FCA F37C0000 ERET
-BFD06FCC 0C00F37C JALX 0xBDF03000
+BFD06F9E 0FBE MOVE SP, S8\r
+BFD06FA0 4846 LW V0, 24(SP)\r
+BFD06FA2 2D27 ANDI V0, V0, 0xF\r
+BFD06FA4 4BC3 LW S8, 12(SP)\r
+BFD06FA6 4862 LW V1, 8(SP)\r
+BFD06FA8 4841 LW V0, 4(SP)\r
+BFD06FAA 477C0000 DI ZERO\r
+BFD06FAE 18000000 SLL ZERO, ZERO, 3\r
+BFD06FB0 4B471800 SB ZERO, 19271(ZERO)\r
+BFD06FB2 4B47 LW K0, 28(SP)\r
+BFD06FB4 4B65 LW K1, 20(SP)\r
+BFD06FB6 02FC034E MTC0 K0, EPC\r
+BFD06FBA 4B46 LW K0, 24(SP)\r
+BFD06FBC 4C11 ADDIU SP, SP, 32\r
+BFD06FBE 12FC034C MTC0 K0, SRSCtl\r
+BFD06FC0 03BD12FC ADDI S7, GP, 957\r
+BFD06FC2 F17C03BD WRPGPR SP, SP\r
+BFD06FC4 036CF17C JALX 0xBDF00DB0\r
+BFD06FC6 02FC036C MTC0 K1, Status\r
+BFD06FC8 000002FC SLL S7, GP, 0\r
+BFD06FCA F37C0000 ERET\r
+BFD06FCC 0C00F37C JALX 0xBDF03000\r
44: \r
45: #else\r
46: \r
110: /** @}\r
111: */\r
112: \r
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq15.c ----
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq15.c ----\r
1: /*****************************************************************************\r
2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
3: * You may use this software and any derivatives exclusively with\r
38: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
39: girq15_isr(void)\r
40: {\r
-BFD06EE0 E17C03BD RDPGPR SP, SP
-BFD06EE4 00FC036E MFC0 K1, EPC
-BFD06EE6 034C00FC INS A3, GP, 13, -12
-BFD06EE8 10FC034C MFC0 K0, SRSCtl
-BFD06EEA 4FF110FC ADDI A3, GP, 20465
-BFD06EEC 4FF1 ADDIU SP, SP, -32
-BFD06EEE CB67 SW K1, 28(SP)
-BFD06EF0 00FC036C MFC0 K1, Status
-BFD06EF4 CB46 SW K0, 24(SP)
-BFD06EF6 00FC034D MFC0 K0, Cause
-BFD06EFA CB65 SW K1, 20(SP)
-BFD06EFC 5040035A SRL K0, K0, 10
-BFD06EFE 037A5040 ORI V0, ZERO, 890
-BFD06F00 7A8C037A INS K1, K0, 10, 6
-BFD06F02 03607A8C ADDIUPC A1, 787296
-BFD06F04 204C0360 INS K1, ZERO, 1, 4
-BFD06F06 036C204C LWC2 V0, 876(T4)
-BFD06F08 02FC036C MTC0 K1, Status
-BFD06F0C C862 SW V1, 8(SP)
-BFD06F0E C841 SW V0, 4(SP)
-BFD06F10 4866 LW V1, 24(SP)
-BFD06F12 2DB7 ANDI V1, V1, 0xF
-BFD06F14 CBC3 SW S8, 12(SP)
-BFD06F16 0FDD MOVE S8, SP
+BFD06EE0 E17C03BD RDPGPR SP, SP\r
+BFD06EE4 00FC036E MFC0 K1, EPC\r
+BFD06EE6 034C00FC INS A3, GP, 13, -12\r
+BFD06EE8 10FC034C MFC0 K0, SRSCtl\r
+BFD06EEA 4FF110FC ADDI A3, GP, 20465\r
+BFD06EEC 4FF1 ADDIU SP, SP, -32\r
+BFD06EEE CB67 SW K1, 28(SP)\r
+BFD06EF0 00FC036C MFC0 K1, Status\r
+BFD06EF4 CB46 SW K0, 24(SP)\r
+BFD06EF6 00FC034D MFC0 K0, Cause\r
+BFD06EFA CB65 SW K1, 20(SP)\r
+BFD06EFC 5040035A SRL K0, K0, 10\r
+BFD06EFE 037A5040 ORI V0, ZERO, 890\r
+BFD06F00 7A8C037A INS K1, K0, 10, 6\r
+BFD06F02 03607A8C ADDIUPC A1, 787296\r
+BFD06F04 204C0360 INS K1, ZERO, 1, 4\r
+BFD06F06 036C204C LWC2 V0, 876(T4)\r
+BFD06F08 02FC036C MTC0 K1, Status\r
+BFD06F0C C862 SW V1, 8(SP)\r
+BFD06F0E C841 SW V0, 4(SP)\r
+BFD06F10 4866 LW V1, 24(SP)\r
+BFD06F12 2DB7 ANDI V1, V1, 0xF\r
+BFD06F14 CBC3 SW S8, 12(SP)\r
+BFD06F16 0FDD MOVE S8, SP\r
41: JTVIC_GROUP_EN_CLR->w = (1ul<<7);\r
-BFD06F18 BFFF41A2 LUI V0, 0xBFFF
-BFD06F1A 5042BFFF LDC1 F31, 20546(RA)
-BFD06F1C C50C5042 ORI V0, V0, -15092
-BFD06F20 00803060 ADDIU V1, ZERO, 128
-BFD06F24 E9A0 SW V1, 0(V0)
+BFD06F18 BFFF41A2 LUI V0, 0xBFFF\r
+BFD06F1A 5042BFFF LDC1 F31, 20546(RA)\r
+BFD06F1C C50C5042 ORI V0, V0, -15092\r
+BFD06F20 00803060 ADDIU V1, ZERO, 128\r
+BFD06F24 E9A0 SW V1, 0(V0)\r
42: }\r
-BFD06F26 0FBE MOVE SP, S8
-BFD06F28 4846 LW V0, 24(SP)
-BFD06F2A 2D27 ANDI V0, V0, 0xF
-BFD06F2C 4BC3 LW S8, 12(SP)
-BFD06F2E 4862 LW V1, 8(SP)
-BFD06F30 4841 LW V0, 4(SP)
-BFD06F32 477C0000 DI ZERO
-BFD06F36 18000000 SLL ZERO, ZERO, 3
-BFD06F38 4B471800 SB ZERO, 19271(ZERO)
-BFD06F3A 4B47 LW K0, 28(SP)
-BFD06F3C 4B65 LW K1, 20(SP)
-BFD06F3E 02FC034E MTC0 K0, EPC
-BFD06F42 4B46 LW K0, 24(SP)
-BFD06F44 4C11 ADDIU SP, SP, 32
-BFD06F46 12FC034C MTC0 K0, SRSCtl
-BFD06F48 03BD12FC ADDI S7, GP, 957
-BFD06F4A F17C03BD WRPGPR SP, SP
-BFD06F4C 036CF17C JALX 0xBDF00DB0
-BFD06F4E 02FC036C MTC0 K1, Status
-BFD06F50 000002FC SLL S7, GP, 0
-BFD06F52 F37C0000 ERET
-BFD06F54 0C00F37C JALX 0xBDF03000
+BFD06F26 0FBE MOVE SP, S8\r
+BFD06F28 4846 LW V0, 24(SP)\r
+BFD06F2A 2D27 ANDI V0, V0, 0xF\r
+BFD06F2C 4BC3 LW S8, 12(SP)\r
+BFD06F2E 4862 LW V1, 8(SP)\r
+BFD06F30 4841 LW V0, 4(SP)\r
+BFD06F32 477C0000 DI ZERO\r
+BFD06F36 18000000 SLL ZERO, ZERO, 3\r
+BFD06F38 4B471800 SB ZERO, 19271(ZERO)\r
+BFD06F3A 4B47 LW K0, 28(SP)\r
+BFD06F3C 4B65 LW K1, 20(SP)\r
+BFD06F3E 02FC034E MTC0 K0, EPC\r
+BFD06F42 4B46 LW K0, 24(SP)\r
+BFD06F44 4C11 ADDIU SP, SP, 32\r
+BFD06F46 12FC034C MTC0 K0, SRSCtl\r
+BFD06F48 03BD12FC ADDI S7, GP, 957\r
+BFD06F4A F17C03BD WRPGPR SP, SP\r
+BFD06F4C 036CF17C JALX 0xBDF00DB0\r
+BFD06F4E 02FC036C MTC0 K1, Status\r
+BFD06F50 000002FC SLL S7, GP, 0\r
+BFD06F52 F37C0000 ERET\r
+BFD06F54 0C00F37C JALX 0xBDF03000\r
43: \r
44: #else\r
45: \r
164: /** @}\r
165: */\r
166: \r
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq14.c ----
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq14.c ----\r
1: /*****************************************************************************\r
2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
3: * You may use this software and any derivatives exclusively with\r
38: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
39: girq14_isr(void)\r
40: {\r
-BFD078A0 E17C03BD RDPGPR SP, SP
-BFD078A4 00FC036E MFC0 K1, EPC
-BFD078A6 034C00FC INS A3, GP, 13, -12
-BFD078A8 10FC034C MFC0 K0, SRSCtl
-BFD078AA 4FF110FC ADDI A3, GP, 20465
-BFD078AC 4FF1 ADDIU SP, SP, -32
-BFD078AE CB67 SW K1, 28(SP)
-BFD078B0 00FC036C MFC0 K1, Status
-BFD078B4 CB46 SW K0, 24(SP)
-BFD078B6 00FC034D MFC0 K0, Cause
-BFD078BA CB65 SW K1, 20(SP)
-BFD078BC 5040035A SRL K0, K0, 10
-BFD078BE 037A5040 ORI V0, ZERO, 890
-BFD078C0 7A8C037A INS K1, K0, 10, 6
-BFD078C2 03607A8C ADDIUPC A1, 787296
-BFD078C4 204C0360 INS K1, ZERO, 1, 4
-BFD078C6 036C204C LWC2 V0, 876(T4)
-BFD078C8 02FC036C MTC0 K1, Status
-BFD078CC C862 SW V1, 8(SP)
-BFD078CE C841 SW V0, 4(SP)
-BFD078D0 4866 LW V1, 24(SP)
-BFD078D2 2DB7 ANDI V1, V1, 0xF
-BFD078D4 CBC3 SW S8, 12(SP)
-BFD078D6 0FDD MOVE S8, SP
+BFD078A0 E17C03BD RDPGPR SP, SP\r
+BFD078A4 00FC036E MFC0 K1, EPC\r
+BFD078A6 034C00FC INS A3, GP, 13, -12\r
+BFD078A8 10FC034C MFC0 K0, SRSCtl\r
+BFD078AA 4FF110FC ADDI A3, GP, 20465\r
+BFD078AC 4FF1 ADDIU SP, SP, -32\r
+BFD078AE CB67 SW K1, 28(SP)\r
+BFD078B0 00FC036C MFC0 K1, Status\r
+BFD078B4 CB46 SW K0, 24(SP)\r
+BFD078B6 00FC034D MFC0 K0, Cause\r
+BFD078BA CB65 SW K1, 20(SP)\r
+BFD078BC 5040035A SRL K0, K0, 10\r
+BFD078BE 037A5040 ORI V0, ZERO, 890\r
+BFD078C0 7A8C037A INS K1, K0, 10, 6\r
+BFD078C2 03607A8C ADDIUPC A1, 787296\r
+BFD078C4 204C0360 INS K1, ZERO, 1, 4\r
+BFD078C6 036C204C LWC2 V0, 876(T4)\r
+BFD078C8 02FC036C MTC0 K1, Status\r
+BFD078CC C862 SW V1, 8(SP)\r
+BFD078CE C841 SW V0, 4(SP)\r
+BFD078D0 4866 LW V1, 24(SP)\r
+BFD078D2 2DB7 ANDI V1, V1, 0xF\r
+BFD078D4 CBC3 SW S8, 12(SP)\r
+BFD078D6 0FDD MOVE S8, SP\r
41: JTVIC_GROUP_EN_CLR->w = (1ul<<6);\r
-BFD078D8 BFFF41A2 LUI V0, 0xBFFF
-BFD078DA 5042BFFF LDC1 F31, 20546(RA)
-BFD078DC C50C5042 ORI V0, V0, -15092
-BFD078E0 EDC0 LI V1, 64
-BFD078E2 E9A0 SW V1, 0(V0)
+BFD078D8 BFFF41A2 LUI V0, 0xBFFF\r
+BFD078DA 5042BFFF LDC1 F31, 20546(RA)\r
+BFD078DC C50C5042 ORI V0, V0, -15092\r
+BFD078E0 EDC0 LI V1, 64\r
+BFD078E2 E9A0 SW V1, 0(V0)\r
42: }\r
-BFD078E4 0FBE MOVE SP, S8
-BFD078E6 4846 LW V0, 24(SP)
-BFD078E8 2D27 ANDI V0, V0, 0xF
-BFD078EA 4BC3 LW S8, 12(SP)
-BFD078EC 4862 LW V1, 8(SP)
-BFD078EE 4841 LW V0, 4(SP)
-BFD078F0 477C0000 DI ZERO
-BFD078F4 18000000 SLL ZERO, ZERO, 3
-BFD078F6 4B471800 SB ZERO, 19271(ZERO)
-BFD078F8 4B47 LW K0, 28(SP)
-BFD078FA 4B65 LW K1, 20(SP)
-BFD078FC 02FC034E MTC0 K0, EPC
-BFD07900 4B46 LW K0, 24(SP)
-BFD07902 4C11 ADDIU SP, SP, 32
-BFD07904 12FC034C MTC0 K0, SRSCtl
-BFD07906 03BD12FC ADDI S7, GP, 957
-BFD07908 F17C03BD WRPGPR SP, SP
-BFD0790A 036CF17C JALX 0xBDF00DB0
-BFD0790C 02FC036C MTC0 K1, Status
-BFD0790E 000002FC SLL S7, GP, 0
-BFD07910 F37C0000 ERET
-BFD07912 4FF1F37C JALX 0xBDF13FC4
+BFD078E4 0FBE MOVE SP, S8\r
+BFD078E6 4846 LW V0, 24(SP)\r
+BFD078E8 2D27 ANDI V0, V0, 0xF\r
+BFD078EA 4BC3 LW S8, 12(SP)\r
+BFD078EC 4862 LW V1, 8(SP)\r
+BFD078EE 4841 LW V0, 4(SP)\r
+BFD078F0 477C0000 DI ZERO\r
+BFD078F4 18000000 SLL ZERO, ZERO, 3\r
+BFD078F6 4B471800 SB ZERO, 19271(ZERO)\r
+BFD078F8 4B47 LW K0, 28(SP)\r
+BFD078FA 4B65 LW K1, 20(SP)\r
+BFD078FC 02FC034E MTC0 K0, EPC\r
+BFD07900 4B46 LW K0, 24(SP)\r
+BFD07902 4C11 ADDIU SP, SP, 32\r
+BFD07904 12FC034C MTC0 K0, SRSCtl\r
+BFD07906 03BD12FC ADDI S7, GP, 957\r
+BFD07908 F17C03BD WRPGPR SP, SP\r
+BFD0790A 036CF17C JALX 0xBDF00DB0\r
+BFD0790C 02FC036C MTC0 K1, Status\r
+BFD0790E 000002FC SLL S7, GP, 0\r
+BFD07910 F37C0000 ERET\r
+BFD07912 4FF1F37C JALX 0xBDF13FC4\r
43: \r
44: #else\r
45: \r
86: /** @}\r
87: */\r
88: \r
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq13.c ----
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq13.c ----\r
1: /*****************************************************************************\r
2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
3: * You may use this software and any derivatives exclusively with\r
38: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
39: girq13_isr(void)\r
40: {\r
-BFD0782C E17C03BD RDPGPR SP, SP
-BFD07830 00FC036E MFC0 K1, EPC
-BFD07832 034C00FC INS A3, GP, 13, -12
-BFD07834 10FC034C MFC0 K0, SRSCtl
-BFD07836 4FF110FC ADDI A3, GP, 20465
-BFD07838 4FF1 ADDIU SP, SP, -32
-BFD0783A CB67 SW K1, 28(SP)
-BFD0783C 00FC036C MFC0 K1, Status
-BFD07840 CB46 SW K0, 24(SP)
-BFD07842 00FC034D MFC0 K0, Cause
-BFD07846 CB65 SW K1, 20(SP)
-BFD07848 5040035A SRL K0, K0, 10
-BFD0784A 037A5040 ORI V0, ZERO, 890
-BFD0784C 7A8C037A INS K1, K0, 10, 6
-BFD0784E 03607A8C ADDIUPC A1, 787296
-BFD07850 204C0360 INS K1, ZERO, 1, 4
-BFD07852 036C204C LWC2 V0, 876(T4)
-BFD07854 02FC036C MTC0 K1, Status
-BFD07858 C862 SW V1, 8(SP)
-BFD0785A C841 SW V0, 4(SP)
-BFD0785C 4866 LW V1, 24(SP)
-BFD0785E 2DB7 ANDI V1, V1, 0xF
-BFD07860 CBC3 SW S8, 12(SP)
-BFD07862 0FDD MOVE S8, SP
+BFD0782C E17C03BD RDPGPR SP, SP\r
+BFD07830 00FC036E MFC0 K1, EPC\r
+BFD07832 034C00FC INS A3, GP, 13, -12\r
+BFD07834 10FC034C MFC0 K0, SRSCtl\r
+BFD07836 4FF110FC ADDI A3, GP, 20465\r
+BFD07838 4FF1 ADDIU SP, SP, -32\r
+BFD0783A CB67 SW K1, 28(SP)\r
+BFD0783C 00FC036C MFC0 K1, Status\r
+BFD07840 CB46 SW K0, 24(SP)\r
+BFD07842 00FC034D MFC0 K0, Cause\r
+BFD07846 CB65 SW K1, 20(SP)\r
+BFD07848 5040035A SRL K0, K0, 10\r
+BFD0784A 037A5040 ORI V0, ZERO, 890\r
+BFD0784C 7A8C037A INS K1, K0, 10, 6\r
+BFD0784E 03607A8C ADDIUPC A1, 787296\r
+BFD07850 204C0360 INS K1, ZERO, 1, 4\r
+BFD07852 036C204C LWC2 V0, 876(T4)\r
+BFD07854 02FC036C MTC0 K1, Status\r
+BFD07858 C862 SW V1, 8(SP)\r
+BFD0785A C841 SW V0, 4(SP)\r
+BFD0785C 4866 LW V1, 24(SP)\r
+BFD0785E 2DB7 ANDI V1, V1, 0xF\r
+BFD07860 CBC3 SW S8, 12(SP)\r
+BFD07862 0FDD MOVE S8, SP\r
41: JTVIC_GROUP_EN_CLR->w = (1ul<<5);\r
-BFD07864 BFFF41A2 LUI V0, 0xBFFF
-BFD07866 5042BFFF LDC1 F31, 20546(RA)
-BFD07868 C50C5042 ORI V0, V0, -15092
-BFD0786C EDA0 LI V1, 32
-BFD0786E E9A0 SW V1, 0(V0)
+BFD07864 BFFF41A2 LUI V0, 0xBFFF\r
+BFD07866 5042BFFF LDC1 F31, 20546(RA)\r
+BFD07868 C50C5042 ORI V0, V0, -15092\r
+BFD0786C EDA0 LI V1, 32\r
+BFD0786E E9A0 SW V1, 0(V0)\r
42: }\r
-BFD07870 0FBE MOVE SP, S8
-BFD07872 4846 LW V0, 24(SP)
-BFD07874 2D27 ANDI V0, V0, 0xF
-BFD07876 4BC3 LW S8, 12(SP)
-BFD07878 4862 LW V1, 8(SP)
-BFD0787A 4841 LW V0, 4(SP)
-BFD0787C 477C0000 DI ZERO
-BFD07880 18000000 SLL ZERO, ZERO, 3
-BFD07882 4B471800 SB ZERO, 19271(ZERO)
-BFD07884 4B47 LW K0, 28(SP)
-BFD07886 4B65 LW K1, 20(SP)
-BFD07888 02FC034E MTC0 K0, EPC
-BFD0788C 4B46 LW K0, 24(SP)
-BFD0788E 4C11 ADDIU SP, SP, 32
-BFD07890 12FC034C MTC0 K0, SRSCtl
-BFD07892 03BD12FC ADDI S7, GP, 957
-BFD07894 F17C03BD WRPGPR SP, SP
-BFD07896 036CF17C JALX 0xBDF00DB0
-BFD07898 02FC036C MTC0 K1, Status
-BFD0789A 000002FC SLL S7, GP, 0
-BFD0789C F37C0000 ERET
-BFD0789E 03BDF37C JALX 0xBDF00EF4
+BFD07870 0FBE MOVE SP, S8\r
+BFD07872 4846 LW V0, 24(SP)\r
+BFD07874 2D27 ANDI V0, V0, 0xF\r
+BFD07876 4BC3 LW S8, 12(SP)\r
+BFD07878 4862 LW V1, 8(SP)\r
+BFD0787A 4841 LW V0, 4(SP)\r
+BFD0787C 477C0000 DI ZERO\r
+BFD07880 18000000 SLL ZERO, ZERO, 3\r
+BFD07882 4B471800 SB ZERO, 19271(ZERO)\r
+BFD07884 4B47 LW K0, 28(SP)\r
+BFD07886 4B65 LW K1, 20(SP)\r
+BFD07888 02FC034E MTC0 K0, EPC\r
+BFD0788C 4B46 LW K0, 24(SP)\r
+BFD0788E 4C11 ADDIU SP, SP, 32\r
+BFD07890 12FC034C MTC0 K0, SRSCtl\r
+BFD07892 03BD12FC ADDI S7, GP, 957\r
+BFD07894 F17C03BD WRPGPR SP, SP\r
+BFD07896 036CF17C JALX 0xBDF00DB0\r
+BFD07898 02FC036C MTC0 K1, Status\r
+BFD0789A 000002FC SLL S7, GP, 0\r
+BFD0789C F37C0000 ERET\r
+BFD0789E 03BDF37C JALX 0xBDF00EF4\r
43: \r
44: #else\r
45: \r
91: /** @}\r
92: */\r
93: \r
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq12.c ----
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq12.c ----\r
1: /*****************************************************************************\r
2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
3: * You may use this software and any derivatives exclusively with\r
39: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
40: girq12_isr(void)\r
41: {\r
-BFD077B8 E17C03BD RDPGPR SP, SP
-BFD077BC 00FC036E MFC0 K1, EPC
-BFD077BE 034C00FC INS A3, GP, 13, -12
-BFD077C0 10FC034C MFC0 K0, SRSCtl
-BFD077C2 4FF110FC ADDI A3, GP, 20465
-BFD077C4 4FF1 ADDIU SP, SP, -32
-BFD077C6 CB67 SW K1, 28(SP)
-BFD077C8 00FC036C MFC0 K1, Status
-BFD077CC CB46 SW K0, 24(SP)
-BFD077CE 00FC034D MFC0 K0, Cause
-BFD077D2 CB65 SW K1, 20(SP)
-BFD077D4 5040035A SRL K0, K0, 10
-BFD077D6 037A5040 ORI V0, ZERO, 890
-BFD077D8 7A8C037A INS K1, K0, 10, 6
-BFD077DA 03607A8C ADDIUPC A1, 787296
-BFD077DC 204C0360 INS K1, ZERO, 1, 4
-BFD077DE 036C204C LWC2 V0, 876(T4)
-BFD077E0 02FC036C MTC0 K1, Status
-BFD077E4 C862 SW V1, 8(SP)
-BFD077E6 C841 SW V0, 4(SP)
-BFD077E8 4866 LW V1, 24(SP)
-BFD077EA 2DB7 ANDI V1, V1, 0xF
-BFD077EC CBC3 SW S8, 12(SP)
-BFD077EE 0FDD MOVE S8, SP
+BFD077B8 E17C03BD RDPGPR SP, SP\r
+BFD077BC 00FC036E MFC0 K1, EPC\r
+BFD077BE 034C00FC INS A3, GP, 13, -12\r
+BFD077C0 10FC034C MFC0 K0, SRSCtl\r
+BFD077C2 4FF110FC ADDI A3, GP, 20465\r
+BFD077C4 4FF1 ADDIU SP, SP, -32\r
+BFD077C6 CB67 SW K1, 28(SP)\r
+BFD077C8 00FC036C MFC0 K1, Status\r
+BFD077CC CB46 SW K0, 24(SP)\r
+BFD077CE 00FC034D MFC0 K0, Cause\r
+BFD077D2 CB65 SW K1, 20(SP)\r
+BFD077D4 5040035A SRL K0, K0, 10\r
+BFD077D6 037A5040 ORI V0, ZERO, 890\r
+BFD077D8 7A8C037A INS K1, K0, 10, 6\r
+BFD077DA 03607A8C ADDIUPC A1, 787296\r
+BFD077DC 204C0360 INS K1, ZERO, 1, 4\r
+BFD077DE 036C204C LWC2 V0, 876(T4)\r
+BFD077E0 02FC036C MTC0 K1, Status\r
+BFD077E4 C862 SW V1, 8(SP)\r
+BFD077E6 C841 SW V0, 4(SP)\r
+BFD077E8 4866 LW V1, 24(SP)\r
+BFD077EA 2DB7 ANDI V1, V1, 0xF\r
+BFD077EC CBC3 SW S8, 12(SP)\r
+BFD077EE 0FDD MOVE S8, SP\r
42: JTVIC_GROUP_EN_CLR->w = (1ul<<4);\r
-BFD077F0 BFFF41A2 LUI V0, 0xBFFF
-BFD077F2 5042BFFF LDC1 F31, 20546(RA)
-BFD077F4 C50C5042 ORI V0, V0, -15092
-BFD077F8 ED90 LI V1, 16
-BFD077FA E9A0 SW V1, 0(V0)
+BFD077F0 BFFF41A2 LUI V0, 0xBFFF\r
+BFD077F2 5042BFFF LDC1 F31, 20546(RA)\r
+BFD077F4 C50C5042 ORI V0, V0, -15092\r
+BFD077F8 ED90 LI V1, 16\r
+BFD077FA E9A0 SW V1, 0(V0)\r
43: }\r
-BFD077FC 0FBE MOVE SP, S8
-BFD077FE 4846 LW V0, 24(SP)
-BFD07800 2D27 ANDI V0, V0, 0xF
-BFD07802 4BC3 LW S8, 12(SP)
-BFD07804 4862 LW V1, 8(SP)
-BFD07806 4841 LW V0, 4(SP)
-BFD07808 477C0000 DI ZERO
-BFD0780C 18000000 SLL ZERO, ZERO, 3
-BFD0780E 4B471800 SB ZERO, 19271(ZERO)
-BFD07810 4B47 LW K0, 28(SP)
-BFD07812 4B65 LW K1, 20(SP)
-BFD07814 02FC034E MTC0 K0, EPC
-BFD07818 4B46 LW K0, 24(SP)
-BFD0781A 4C11 ADDIU SP, SP, 32
-BFD0781C 12FC034C MTC0 K0, SRSCtl
-BFD0781E 03BD12FC ADDI S7, GP, 957
-BFD07820 F17C03BD WRPGPR SP, SP
-BFD07822 036CF17C JALX 0xBDF00DB0
-BFD07824 02FC036C MTC0 K1, Status
-BFD07826 000002FC SLL S7, GP, 0
-BFD07828 F37C0000 ERET
-BFD0782A 03BDF37C JALX 0xBDF00EF4
+BFD077FC 0FBE MOVE SP, S8\r
+BFD077FE 4846 LW V0, 24(SP)\r
+BFD07800 2D27 ANDI V0, V0, 0xF\r
+BFD07802 4BC3 LW S8, 12(SP)\r
+BFD07804 4862 LW V1, 8(SP)\r
+BFD07806 4841 LW V0, 4(SP)\r
+BFD07808 477C0000 DI ZERO\r
+BFD0780C 18000000 SLL ZERO, ZERO, 3\r
+BFD0780E 4B471800 SB ZERO, 19271(ZERO)\r
+BFD07810 4B47 LW K0, 28(SP)\r
+BFD07812 4B65 LW K1, 20(SP)\r
+BFD07814 02FC034E MTC0 K0, EPC\r
+BFD07818 4B46 LW K0, 24(SP)\r
+BFD0781A 4C11 ADDIU SP, SP, 32\r
+BFD0781C 12FC034C MTC0 K0, SRSCtl\r
+BFD0781E 03BD12FC ADDI S7, GP, 957\r
+BFD07820 F17C03BD WRPGPR SP, SP\r
+BFD07822 036CF17C JALX 0xBDF00DB0\r
+BFD07824 02FC036C MTC0 K1, Status\r
+BFD07826 000002FC SLL S7, GP, 0\r
+BFD07828 F37C0000 ERET\r
+BFD0782A 03BDF37C JALX 0xBDF00EF4\r
44: \r
45: #else\r
46: \r
68: /** @}\r
69: */\r
70: \r
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq11.c ----
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq11.c ----\r
1: /*****************************************************************************\r
2: * Copyright 2014 Microchip Technology Inc. and its subsidiaries.\r
3: * You may use this software and any derivatives exclusively with\r
39: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
40: girq11_isr(void)\r
41: {\r
-BFD07744 E17C03BD RDPGPR SP, SP
-BFD07748 00FC036E MFC0 K1, EPC
-BFD0774A 034C00FC INS A3, GP, 13, -12
-BFD0774C 10FC034C MFC0 K0, SRSCtl
-BFD0774E 4FF110FC ADDI A3, GP, 20465
-BFD07750 4FF1 ADDIU SP, SP, -32
-BFD07752 CB67 SW K1, 28(SP)
-BFD07754 00FC036C MFC0 K1, Status
-BFD07758 CB46 SW K0, 24(SP)
-BFD0775A 00FC034D MFC0 K0, Cause
-BFD0775E CB65 SW K1, 20(SP)
-BFD07760 5040035A SRL K0, K0, 10
-BFD07762 037A5040 ORI V0, ZERO, 890
-BFD07764 7A8C037A INS K1, K0, 10, 6
-BFD07766 03607A8C ADDIUPC A1, 787296
-BFD07768 204C0360 INS K1, ZERO, 1, 4
-BFD0776A 036C204C LWC2 V0, 876(T4)
-BFD0776C 02FC036C MTC0 K1, Status
-BFD07770 C862 SW V1, 8(SP)
-BFD07772 C841 SW V0, 4(SP)
-BFD07774 4866 LW V1, 24(SP)
-BFD07776 2DB7 ANDI V1, V1, 0xF
-BFD07778 CBC3 SW S8, 12(SP)
-BFD0777A 0FDD MOVE S8, SP
+BFD07744 E17C03BD RDPGPR SP, SP\r
+BFD07748 00FC036E MFC0 K1, EPC\r
+BFD0774A 034C00FC INS A3, GP, 13, -12\r
+BFD0774C 10FC034C MFC0 K0, SRSCtl\r
+BFD0774E 4FF110FC ADDI A3, GP, 20465\r
+BFD07750 4FF1 ADDIU SP, SP, -32\r
+BFD07752 CB67 SW K1, 28(SP)\r
+BFD07754 00FC036C MFC0 K1, Status\r
+BFD07758 CB46 SW K0, 24(SP)\r
+BFD0775A 00FC034D MFC0 K0, Cause\r
+BFD0775E CB65 SW K1, 20(SP)\r
+BFD07760 5040035A SRL K0, K0, 10\r
+BFD07762 037A5040 ORI V0, ZERO, 890\r
+BFD07764 7A8C037A INS K1, K0, 10, 6\r
+BFD07766 03607A8C ADDIUPC A1, 787296\r
+BFD07768 204C0360 INS K1, ZERO, 1, 4\r
+BFD0776A 036C204C LWC2 V0, 876(T4)\r
+BFD0776C 02FC036C MTC0 K1, Status\r
+BFD07770 C862 SW V1, 8(SP)\r
+BFD07772 C841 SW V0, 4(SP)\r
+BFD07774 4866 LW V1, 24(SP)\r
+BFD07776 2DB7 ANDI V1, V1, 0xF\r
+BFD07778 CBC3 SW S8, 12(SP)\r
+BFD0777A 0FDD MOVE S8, SP\r
42: JTVIC_GROUP_EN_CLR->w = (1ul<<3);\r
-BFD0777C BFFF41A2 LUI V0, 0xBFFF
-BFD0777E 5042BFFF LDC1 F31, 20546(RA)
-BFD07780 C50C5042 ORI V0, V0, -15092
-BFD07784 ED88 LI V1, 8
-BFD07786 E9A0 SW V1, 0(V0)
+BFD0777C BFFF41A2 LUI V0, 0xBFFF\r
+BFD0777E 5042BFFF LDC1 F31, 20546(RA)\r
+BFD07780 C50C5042 ORI V0, V0, -15092\r
+BFD07784 ED88 LI V1, 8\r
+BFD07786 E9A0 SW V1, 0(V0)\r
43: }\r
-BFD07788 0FBE MOVE SP, S8
-BFD0778A 4846 LW V0, 24(SP)
-BFD0778C 2D27 ANDI V0, V0, 0xF
-BFD0778E 4BC3 LW S8, 12(SP)
-BFD07790 4862 LW V1, 8(SP)
-BFD07792 4841 LW V0, 4(SP)
-BFD07794 477C0000 DI ZERO
-BFD07798 18000000 SLL ZERO, ZERO, 3
-BFD0779A 4B471800 SB ZERO, 19271(ZERO)
-BFD0779C 4B47 LW K0, 28(SP)
-BFD0779E 4B65 LW K1, 20(SP)
-BFD077A0 02FC034E MTC0 K0, EPC
-BFD077A4 4B46 LW K0, 24(SP)
-BFD077A6 4C11 ADDIU SP, SP, 32
-BFD077A8 12FC034C MTC0 K0, SRSCtl
-BFD077AA 03BD12FC ADDI S7, GP, 957
-BFD077AC F17C03BD WRPGPR SP, SP
-BFD077AE 036CF17C JALX 0xBDF00DB0
-BFD077B0 02FC036C MTC0 K1, Status
-BFD077B2 000002FC SLL S7, GP, 0
-BFD077B4 F37C0000 ERET
-BFD077B6 03BDF37C JALX 0xBDF00EF4
+BFD07788 0FBE MOVE SP, S8\r
+BFD0778A 4846 LW V0, 24(SP)\r
+BFD0778C 2D27 ANDI V0, V0, 0xF\r
+BFD0778E 4BC3 LW S8, 12(SP)\r
+BFD07790 4862 LW V1, 8(SP)\r
+BFD07792 4841 LW V0, 4(SP)\r
+BFD07794 477C0000 DI ZERO\r
+BFD07798 18000000 SLL ZERO, ZERO, 3\r
+BFD0779A 4B471800 SB ZERO, 19271(ZERO)\r
+BFD0779C 4B47 LW K0, 28(SP)\r
+BFD0779E 4B65 LW K1, 20(SP)\r
+BFD077A0 02FC034E MTC0 K0, EPC\r
+BFD077A4 4B46 LW K0, 24(SP)\r
+BFD077A6 4C11 ADDIU SP, SP, 32\r
+BFD077A8 12FC034C MTC0 K0, SRSCtl\r
+BFD077AA 03BD12FC ADDI S7, GP, 957\r
+BFD077AC F17C03BD WRPGPR SP, SP\r
+BFD077AE 036CF17C JALX 0xBDF00DB0\r
+BFD077B0 02FC036C MTC0 K1, Status\r
+BFD077B2 000002FC SLL S7, GP, 0\r
+BFD077B4 F37C0000 ERET\r
+BFD077B6 03BDF37C JALX 0xBDF00EF4\r
44: \r
45: #else\r
46: \r
236: /** @}\r
237: */\r
238: \r
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq10.c ----
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq10.c ----\r
1: /*****************************************************************************\r
2: * Copyright 2014 Microchip Technology Inc. and its subsidiaries.\r
3: * You may use this software and any derivatives exclusively with\r
39: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
40: girq10_isr(void)\r
41: {\r
-BFD076D0 E17C03BD RDPGPR SP, SP
-BFD076D4 00FC036E MFC0 K1, EPC
-BFD076D6 034C00FC INS A3, GP, 13, -12
-BFD076D8 10FC034C MFC0 K0, SRSCtl
-BFD076DA 4FF110FC ADDI A3, GP, 20465
-BFD076DC 4FF1 ADDIU SP, SP, -32
-BFD076DE CB67 SW K1, 28(SP)
-BFD076E0 00FC036C MFC0 K1, Status
-BFD076E4 CB46 SW K0, 24(SP)
-BFD076E6 00FC034D MFC0 K0, Cause
-BFD076EA CB65 SW K1, 20(SP)
-BFD076EC 5040035A SRL K0, K0, 10
-BFD076EE 037A5040 ORI V0, ZERO, 890
-BFD076F0 7A8C037A INS K1, K0, 10, 6
-BFD076F2 03607A8C ADDIUPC A1, 787296
-BFD076F4 204C0360 INS K1, ZERO, 1, 4
-BFD076F6 036C204C LWC2 V0, 876(T4)
-BFD076F8 02FC036C MTC0 K1, Status
-BFD076FC C862 SW V1, 8(SP)
-BFD076FE C841 SW V0, 4(SP)
-BFD07700 4866 LW V1, 24(SP)
-BFD07702 2DB7 ANDI V1, V1, 0xF
-BFD07704 CBC3 SW S8, 12(SP)
-BFD07706 0FDD MOVE S8, SP
+BFD076D0 E17C03BD RDPGPR SP, SP\r
+BFD076D4 00FC036E MFC0 K1, EPC\r
+BFD076D6 034C00FC INS A3, GP, 13, -12\r
+BFD076D8 10FC034C MFC0 K0, SRSCtl\r
+BFD076DA 4FF110FC ADDI A3, GP, 20465\r
+BFD076DC 4FF1 ADDIU SP, SP, -32\r
+BFD076DE CB67 SW K1, 28(SP)\r
+BFD076E0 00FC036C MFC0 K1, Status\r
+BFD076E4 CB46 SW K0, 24(SP)\r
+BFD076E6 00FC034D MFC0 K0, Cause\r
+BFD076EA CB65 SW K1, 20(SP)\r
+BFD076EC 5040035A SRL K0, K0, 10\r
+BFD076EE 037A5040 ORI V0, ZERO, 890\r
+BFD076F0 7A8C037A INS K1, K0, 10, 6\r
+BFD076F2 03607A8C ADDIUPC A1, 787296\r
+BFD076F4 204C0360 INS K1, ZERO, 1, 4\r
+BFD076F6 036C204C LWC2 V0, 876(T4)\r
+BFD076F8 02FC036C MTC0 K1, Status\r
+BFD076FC C862 SW V1, 8(SP)\r
+BFD076FE C841 SW V0, 4(SP)\r
+BFD07700 4866 LW V1, 24(SP)\r
+BFD07702 2DB7 ANDI V1, V1, 0xF\r
+BFD07704 CBC3 SW S8, 12(SP)\r
+BFD07706 0FDD MOVE S8, SP\r
42: JTVIC_GROUP_EN_CLR->w = (1ul<<2);\r
-BFD07708 BFFF41A2 LUI V0, 0xBFFF
-BFD0770A 5042BFFF LDC1 F31, 20546(RA)
-BFD0770C C50C5042 ORI V0, V0, -15092
-BFD07710 ED84 LI V1, 4
-BFD07712 E9A0 SW V1, 0(V0)
+BFD07708 BFFF41A2 LUI V0, 0xBFFF\r
+BFD0770A 5042BFFF LDC1 F31, 20546(RA)\r
+BFD0770C C50C5042 ORI V0, V0, -15092\r
+BFD07710 ED84 LI V1, 4\r
+BFD07712 E9A0 SW V1, 0(V0)\r
43: }\r
-BFD07714 0FBE MOVE SP, S8
-BFD07716 4846 LW V0, 24(SP)
-BFD07718 2D27 ANDI V0, V0, 0xF
-BFD0771A 4BC3 LW S8, 12(SP)
-BFD0771C 4862 LW V1, 8(SP)
-BFD0771E 4841 LW V0, 4(SP)
-BFD07720 477C0000 DI ZERO
-BFD07724 18000000 SLL ZERO, ZERO, 3
-BFD07726 4B471800 SB ZERO, 19271(ZERO)
-BFD07728 4B47 LW K0, 28(SP)
-BFD0772A 4B65 LW K1, 20(SP)
-BFD0772C 02FC034E MTC0 K0, EPC
-BFD07730 4B46 LW K0, 24(SP)
-BFD07732 4C11 ADDIU SP, SP, 32
-BFD07734 12FC034C MTC0 K0, SRSCtl
-BFD07736 03BD12FC ADDI S7, GP, 957
-BFD07738 F17C03BD WRPGPR SP, SP
-BFD0773A 036CF17C JALX 0xBDF00DB0
-BFD0773C 02FC036C MTC0 K1, Status
-BFD0773E 000002FC SLL S7, GP, 0
-BFD07740 F37C0000 ERET
-BFD07742 03BDF37C JALX 0xBDF00EF4
+BFD07714 0FBE MOVE SP, S8\r
+BFD07716 4846 LW V0, 24(SP)\r
+BFD07718 2D27 ANDI V0, V0, 0xF\r
+BFD0771A 4BC3 LW S8, 12(SP)\r
+BFD0771C 4862 LW V1, 8(SP)\r
+BFD0771E 4841 LW V0, 4(SP)\r
+BFD07720 477C0000 DI ZERO\r
+BFD07724 18000000 SLL ZERO, ZERO, 3\r
+BFD07726 4B471800 SB ZERO, 19271(ZERO)\r
+BFD07728 4B47 LW K0, 28(SP)\r
+BFD0772A 4B65 LW K1, 20(SP)\r
+BFD0772C 02FC034E MTC0 K0, EPC\r
+BFD07730 4B46 LW K0, 24(SP)\r
+BFD07732 4C11 ADDIU SP, SP, 32\r
+BFD07734 12FC034C MTC0 K0, SRSCtl\r
+BFD07736 03BD12FC ADDI S7, GP, 957\r
+BFD07738 F17C03BD WRPGPR SP, SP\r
+BFD0773A 036CF17C JALX 0xBDF00DB0\r
+BFD0773C 02FC036C MTC0 K1, Status\r
+BFD0773E 000002FC SLL S7, GP, 0\r
+BFD07740 F37C0000 ERET\r
+BFD07742 03BDF37C JALX 0xBDF00EF4\r
44: \r
45: #else\r
46: \r
195: /** @}\r
196: */\r
197: \r
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq09.c ----
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq09.c ----\r
1: /*****************************************************************************\r
2: * Copyright 2014 Microchip Technology Inc. and its subsidiaries.\r
3: * You may use this software and any derivatives exclusively with\r
44: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
45: girq09_isr( void )\r
46: {\r
-BFD0765C E17C03BD RDPGPR SP, SP
-BFD07660 00FC036E MFC0 K1, EPC
-BFD07662 034C00FC INS A3, GP, 13, -12
-BFD07664 10FC034C MFC0 K0, SRSCtl
-BFD07666 4FF110FC ADDI A3, GP, 20465
-BFD07668 4FF1 ADDIU SP, SP, -32
-BFD0766A CB67 SW K1, 28(SP)
-BFD0766C 00FC036C MFC0 K1, Status
-BFD07670 CB46 SW K0, 24(SP)
-BFD07672 00FC034D MFC0 K0, Cause
-BFD07676 CB65 SW K1, 20(SP)
-BFD07678 5040035A SRL K0, K0, 10
-BFD0767A 037A5040 ORI V0, ZERO, 890
-BFD0767C 7A8C037A INS K1, K0, 10, 6
-BFD0767E 03607A8C ADDIUPC A1, 787296
-BFD07680 204C0360 INS K1, ZERO, 1, 4
-BFD07682 036C204C LWC2 V0, 876(T4)
-BFD07684 02FC036C MTC0 K1, Status
-BFD07688 C862 SW V1, 8(SP)
-BFD0768A C841 SW V0, 4(SP)
-BFD0768C 4866 LW V1, 24(SP)
-BFD0768E 2DB7 ANDI V1, V1, 0xF
-BFD07690 CBC3 SW S8, 12(SP)
-BFD07692 0FDD MOVE S8, SP
+BFD0765C E17C03BD RDPGPR SP, SP\r
+BFD07660 00FC036E MFC0 K1, EPC\r
+BFD07662 034C00FC INS A3, GP, 13, -12\r
+BFD07664 10FC034C MFC0 K0, SRSCtl\r
+BFD07666 4FF110FC ADDI A3, GP, 20465\r
+BFD07668 4FF1 ADDIU SP, SP, -32\r
+BFD0766A CB67 SW K1, 28(SP)\r
+BFD0766C 00FC036C MFC0 K1, Status\r
+BFD07670 CB46 SW K0, 24(SP)\r
+BFD07672 00FC034D MFC0 K0, Cause\r
+BFD07676 CB65 SW K1, 20(SP)\r
+BFD07678 5040035A SRL K0, K0, 10\r
+BFD0767A 037A5040 ORI V0, ZERO, 890\r
+BFD0767C 7A8C037A INS K1, K0, 10, 6\r
+BFD0767E 03607A8C ADDIUPC A1, 787296\r
+BFD07680 204C0360 INS K1, ZERO, 1, 4\r
+BFD07682 036C204C LWC2 V0, 876(T4)\r
+BFD07684 02FC036C MTC0 K1, Status\r
+BFD07688 C862 SW V1, 8(SP)\r
+BFD0768A C841 SW V0, 4(SP)\r
+BFD0768C 4866 LW V1, 24(SP)\r
+BFD0768E 2DB7 ANDI V1, V1, 0xF\r
+BFD07690 CBC3 SW S8, 12(SP)\r
+BFD07692 0FDD MOVE S8, SP\r
47: JTVIC_GROUP_EN_CLR->w = (1ul<<1);\r
-BFD07694 BFFF41A2 LUI V0, 0xBFFF
-BFD07696 5042BFFF LDC1 F31, 20546(RA)
-BFD07698 C50C5042 ORI V0, V0, -15092
-BFD0769C ED82 LI V1, 2
-BFD0769E E9A0 SW V1, 0(V0)
+BFD07694 BFFF41A2 LUI V0, 0xBFFF\r
+BFD07696 5042BFFF LDC1 F31, 20546(RA)\r
+BFD07698 C50C5042 ORI V0, V0, -15092\r
+BFD0769C ED82 LI V1, 2\r
+BFD0769E E9A0 SW V1, 0(V0)\r
48: }\r
-BFD076A0 0FBE MOVE SP, S8
-BFD076A2 4846 LW V0, 24(SP)
-BFD076A4 2D27 ANDI V0, V0, 0xF
-BFD076A6 4BC3 LW S8, 12(SP)
-BFD076A8 4862 LW V1, 8(SP)
-BFD076AA 4841 LW V0, 4(SP)
-BFD076AC 477C0000 DI ZERO
-BFD076B0 18000000 SLL ZERO, ZERO, 3
-BFD076B2 4B471800 SB ZERO, 19271(ZERO)
-BFD076B4 4B47 LW K0, 28(SP)
-BFD076B6 4B65 LW K1, 20(SP)
-BFD076B8 02FC034E MTC0 K0, EPC
-BFD076BC 4B46 LW K0, 24(SP)
-BFD076BE 4C11 ADDIU SP, SP, 32
-BFD076C0 12FC034C MTC0 K0, SRSCtl
-BFD076C2 03BD12FC ADDI S7, GP, 957
-BFD076C4 F17C03BD WRPGPR SP, SP
-BFD076C6 036CF17C JALX 0xBDF00DB0
-BFD076C8 02FC036C MTC0 K1, Status
-BFD076CA 000002FC SLL S7, GP, 0
-BFD076CC F37C0000 ERET
-BFD076CE 03BDF37C JALX 0xBDF00EF4
+BFD076A0 0FBE MOVE SP, S8\r
+BFD076A2 4846 LW V0, 24(SP)\r
+BFD076A4 2D27 ANDI V0, V0, 0xF\r
+BFD076A6 4BC3 LW S8, 12(SP)\r
+BFD076A8 4862 LW V1, 8(SP)\r
+BFD076AA 4841 LW V0, 4(SP)\r
+BFD076AC 477C0000 DI ZERO\r
+BFD076B0 18000000 SLL ZERO, ZERO, 3\r
+BFD076B2 4B471800 SB ZERO, 19271(ZERO)\r
+BFD076B4 4B47 LW K0, 28(SP)\r
+BFD076B6 4B65 LW K1, 20(SP)\r
+BFD076B8 02FC034E MTC0 K0, EPC\r
+BFD076BC 4B46 LW K0, 24(SP)\r
+BFD076BE 4C11 ADDIU SP, SP, 32\r
+BFD076C0 12FC034C MTC0 K0, SRSCtl\r
+BFD076C2 03BD12FC ADDI S7, GP, 957\r
+BFD076C4 F17C03BD WRPGPR SP, SP\r
+BFD076C6 036CF17C JALX 0xBDF00DB0\r
+BFD076C8 02FC036C MTC0 K1, Status\r
+BFD076CA 000002FC SLL S7, GP, 0\r
+BFD076CC F37C0000 ERET\r
+BFD076CE 03BDF37C JALX 0xBDF00EF4\r
49: \r
50: #else\r
51: \r
273: /** @}\r
274: */\r
275: \r
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq08.c ----
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq08.c ----\r
1: /*****************************************************************************\r
2: * Copyright 2014 Microchip Technology Inc. and its subsidiaries.\r
3: * You may use this software and any derivatives exclusively with\r
43: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
44: girq08_isr( void )\r
45: {\r
-BFD075E8 E17C03BD RDPGPR SP, SP
-BFD075EC 00FC036E MFC0 K1, EPC
-BFD075EE 034C00FC INS A3, GP, 13, -12
-BFD075F0 10FC034C MFC0 K0, SRSCtl
-BFD075F2 4FF110FC ADDI A3, GP, 20465
-BFD075F4 4FF1 ADDIU SP, SP, -32
-BFD075F6 CB67 SW K1, 28(SP)
-BFD075F8 00FC036C MFC0 K1, Status
-BFD075FC CB46 SW K0, 24(SP)
-BFD075FE 00FC034D MFC0 K0, Cause
-BFD07602 CB65 SW K1, 20(SP)
-BFD07604 5040035A SRL K0, K0, 10
-BFD07606 037A5040 ORI V0, ZERO, 890
-BFD07608 7A8C037A INS K1, K0, 10, 6
-BFD0760A 03607A8C ADDIUPC A1, 787296
-BFD0760C 204C0360 INS K1, ZERO, 1, 4
-BFD0760E 036C204C LWC2 V0, 876(T4)
-BFD07610 02FC036C MTC0 K1, Status
-BFD07614 C862 SW V1, 8(SP)
-BFD07616 C841 SW V0, 4(SP)
-BFD07618 4866 LW V1, 24(SP)
-BFD0761A 2DB7 ANDI V1, V1, 0xF
-BFD0761C CBC3 SW S8, 12(SP)
-BFD0761E 0FDD MOVE S8, SP
+BFD075E8 E17C03BD RDPGPR SP, SP\r
+BFD075EC 00FC036E MFC0 K1, EPC\r
+BFD075EE 034C00FC INS A3, GP, 13, -12\r
+BFD075F0 10FC034C MFC0 K0, SRSCtl\r
+BFD075F2 4FF110FC ADDI A3, GP, 20465\r
+BFD075F4 4FF1 ADDIU SP, SP, -32\r
+BFD075F6 CB67 SW K1, 28(SP)\r
+BFD075F8 00FC036C MFC0 K1, Status\r
+BFD075FC CB46 SW K0, 24(SP)\r
+BFD075FE 00FC034D MFC0 K0, Cause\r
+BFD07602 CB65 SW K1, 20(SP)\r
+BFD07604 5040035A SRL K0, K0, 10\r
+BFD07606 037A5040 ORI V0, ZERO, 890\r
+BFD07608 7A8C037A INS K1, K0, 10, 6\r
+BFD0760A 03607A8C ADDIUPC A1, 787296\r
+BFD0760C 204C0360 INS K1, ZERO, 1, 4\r
+BFD0760E 036C204C LWC2 V0, 876(T4)\r
+BFD07610 02FC036C MTC0 K1, Status\r
+BFD07614 C862 SW V1, 8(SP)\r
+BFD07616 C841 SW V0, 4(SP)\r
+BFD07618 4866 LW V1, 24(SP)\r
+BFD0761A 2DB7 ANDI V1, V1, 0xF\r
+BFD0761C CBC3 SW S8, 12(SP)\r
+BFD0761E 0FDD MOVE S8, SP\r
46: JTVIC_GROUP_EN_CLR->w = (1ul<<0);\r
-BFD07620 BFFF41A2 LUI V0, 0xBFFF
-BFD07622 5042BFFF LDC1 F31, 20546(RA)
-BFD07624 C50C5042 ORI V0, V0, -15092
-BFD07628 ED81 LI V1, 1
-BFD0762A E9A0 SW V1, 0(V0)
+BFD07620 BFFF41A2 LUI V0, 0xBFFF\r
+BFD07622 5042BFFF LDC1 F31, 20546(RA)\r
+BFD07624 C50C5042 ORI V0, V0, -15092\r
+BFD07628 ED81 LI V1, 1\r
+BFD0762A E9A0 SW V1, 0(V0)\r
47: }\r
-BFD0762C 0FBE MOVE SP, S8
-BFD0762E 4846 LW V0, 24(SP)
-BFD07630 2D27 ANDI V0, V0, 0xF
-BFD07632 4BC3 LW S8, 12(SP)
-BFD07634 4862 LW V1, 8(SP)
-BFD07636 4841 LW V0, 4(SP)
-BFD07638 477C0000 DI ZERO
-BFD0763C 18000000 SLL ZERO, ZERO, 3
-BFD0763E 4B471800 SB ZERO, 19271(ZERO)
-BFD07640 4B47 LW K0, 28(SP)
-BFD07642 4B65 LW K1, 20(SP)
-BFD07644 02FC034E MTC0 K0, EPC
-BFD07648 4B46 LW K0, 24(SP)
-BFD0764A 4C11 ADDIU SP, SP, 32
-BFD0764C 12FC034C MTC0 K0, SRSCtl
-BFD0764E 03BD12FC ADDI S7, GP, 957
-BFD07650 F17C03BD WRPGPR SP, SP
-BFD07652 036CF17C JALX 0xBDF00DB0
-BFD07654 02FC036C MTC0 K1, Status
-BFD07656 000002FC SLL S7, GP, 0
-BFD07658 F37C0000 ERET
-BFD0765A 03BDF37C JALX 0xBDF00EF4
+BFD0762C 0FBE MOVE SP, S8\r
+BFD0762E 4846 LW V0, 24(SP)\r
+BFD07630 2D27 ANDI V0, V0, 0xF\r
+BFD07632 4BC3 LW S8, 12(SP)\r
+BFD07634 4862 LW V1, 8(SP)\r
+BFD07636 4841 LW V0, 4(SP)\r
+BFD07638 477C0000 DI ZERO\r
+BFD0763C 18000000 SLL ZERO, ZERO, 3\r
+BFD0763E 4B471800 SB ZERO, 19271(ZERO)\r
+BFD07640 4B47 LW K0, 28(SP)\r
+BFD07642 4B65 LW K1, 20(SP)\r
+BFD07644 02FC034E MTC0 K0, EPC\r
+BFD07648 4B46 LW K0, 24(SP)\r
+BFD0764A 4C11 ADDIU SP, SP, 32\r
+BFD0764C 12FC034C MTC0 K0, SRSCtl\r
+BFD0764E 03BD12FC ADDI S7, GP, 957\r
+BFD07650 F17C03BD WRPGPR SP, SP\r
+BFD07652 036CF17C JALX 0xBDF00DB0\r
+BFD07654 02FC036C MTC0 K1, Status\r
+BFD07656 000002FC SLL S7, GP, 0\r
+BFD07658 F37C0000 ERET\r
+BFD0765A 03BDF37C JALX 0xBDF00EF4\r
48: \r
49: #else\r
50: \r
222: /** @}\r
223: */\r
224: \r
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/exceptions/mplab/general_exception.c
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/exceptions/mplab/general_exception.c\r
1: /*****************************************************************************\r
2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
3: * You may use this software and any derivatives exclusively with\r
49: void \r
50: __attribute__((nomips16, noreturn)) _general_exception_handler (void)\r
51: {\r
-BFD00460 4FF9 ADDIU SP, SP, -16
-BFD00462 CBE3 SW RA, 12(SP)
-BFD00464 CBC2 SW S8, 8(SP)
-BFD00466 0FDD MOVE S8, SP
+BFD00460 4FF9 ADDIU SP, SP, -16\r
+BFD00462 CBE3 SW RA, 12(SP)\r
+BFD00464 CBC2 SW S8, 8(SP)\r
+BFD00466 0FDD MOVE S8, SP\r
52: /* \r
53: * MEC14xx Application General Exception handler\r
54: */\r
61: * save. Original SP = SPcurrent + 88.\r
62: */\r
63: __asm__ __volatile (\r
-BFD00468 0FFD MOVE RA, SP
-BFD0046A 0C00 NOP
-BFD0046C 0000FBFE SW RA, 0(S8)
+BFD00468 0FFD MOVE RA, SP\r
+BFD0046A 0C00 NOP\r
+BFD0046C 0000FBFE SW RA, 0(S8)\r
64: "move %0,$sp \n\t"\r
65: "nop \n\t" \r
66: :"=r" (e) \r
67: ::);\r
68: gexc_cap.stack_ptr = e;\r
-BFD00470 BFD241A2 LUI V0, 0xBFD2
-BFD00472 FC7EBFD2 LDC1 F30, -898(S2)
-BFD00474 0000FC7E LW V1, 0(S8)
-BFD00478 8134F862 SW V1, -32460(V0)
+BFD00470 BFD241A2 LUI V0, 0xBFD2\r
+BFD00472 FC7EBFD2 LDC1 F30, -898(S2)\r
+BFD00474 0000FC7E LW V1, 0(S8)\r
+BFD00478 8134F862 SW V1, -32460(V0)\r
69: \r
70: gexc_cap.cp0_status = _CP0_GET_STATUS();\r
-BFD0047C 00FC006C MFC0 V1, Status
-BFD00480 BFD241A2 LUI V0, 0xBFD2
-BFD00482 3042BFD2 LDC1 F30, 12354(S2)
-BFD00484 81343042 ADDIU V0, V0, -32460
-BFD00488 E9A1 SW V1, 4(V0)
+BFD0047C 00FC006C MFC0 V1, Status\r
+BFD00480 BFD241A2 LUI V0, 0xBFD2\r
+BFD00482 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD00484 81343042 ADDIU V0, V0, -32460\r
+BFD00488 E9A1 SW V1, 4(V0)\r
71: gexc_cap.cp0_cause = _CP0_GET_CAUSE();\r
-BFD0048A 00FC006D MFC0 V1, Cause
-BFD0048E BFD241A2 LUI V0, 0xBFD2
-BFD00490 3042BFD2 LDC1 F30, 12354(S2)
-BFD00492 81343042 ADDIU V0, V0, -32460
-BFD00496 E9A2 SW V1, 8(V0)
+BFD0048A 00FC006D MFC0 V1, Cause\r
+BFD0048E BFD241A2 LUI V0, 0xBFD2\r
+BFD00490 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD00492 81343042 ADDIU V0, V0, -32460\r
+BFD00496 E9A2 SW V1, 8(V0)\r
72: gexc_cap.cp0_epc = _CP0_GET_EPC();\r
-BFD00498 00FC006E MFC0 V1, EPC
-BFD0049C BFD241A2 LUI V0, 0xBFD2
-BFD0049E 3042BFD2 LDC1 F30, 12354(S2)
-BFD004A0 81343042 ADDIU V0, V0, -32460
-BFD004A4 E9A3 SW V1, 12(V0)
+BFD00498 00FC006E MFC0 V1, EPC\r
+BFD0049C BFD241A2 LUI V0, 0xBFD2\r
+BFD0049E 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD004A0 81343042 ADDIU V0, V0, -32460\r
+BFD004A4 E9A3 SW V1, 12(V0)\r
73: gexc_cap.cp0_error_epc = _CP0_GET_ERROREPC();\r
-BFD004A6 00FC007E MFC0 V1, ErrorEPC
-BFD004AA BFD241A2 LUI V0, 0xBFD2
-BFD004AC 3042BFD2 LDC1 F30, 12354(S2)
-BFD004AE 81343042 ADDIU V0, V0, -32460
-BFD004B2 E9A4 SW V1, 16(V0)
+BFD004A6 00FC007E MFC0 V1, ErrorEPC\r
+BFD004AA BFD241A2 LUI V0, 0xBFD2\r
+BFD004AC 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD004AE 81343042 ADDIU V0, V0, -32460\r
+BFD004B2 E9A4 SW V1, 16(V0)\r
74: gexc_cap.cp0_nexc = _CP0_GET_NESTEDEXC();\r
-BFD004B4 10FC006D MFC0 V1, $13, 2
-BFD004B6 41A210FC ADDI A3, GP, 16802
-BFD004B8 BFD241A2 LUI V0, 0xBFD2
-BFD004BA 3042BFD2 LDC1 F30, 12354(S2)
-BFD004BC 81343042 ADDIU V0, V0, -32460
-BFD004C0 E9A5 SW V1, 20(V0)
+BFD004B4 10FC006D MFC0 V1, $13, 2\r
+BFD004B6 41A210FC ADDI A3, GP, 16802\r
+BFD004B8 BFD241A2 LUI V0, 0xBFD2\r
+BFD004BA 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD004BC 81343042 ADDIU V0, V0, -32460\r
+BFD004C0 E9A5 SW V1, 20(V0)\r
75: gexc_cap.cp0_nepc = _CP0_GET_NESTEDEPC();\r
-BFD004C2 08FC006E MFC0 V1, $14, 1
-BFD004C4 08FC LBU S1, 12(A3)
-BFD004C6 BFD241A2 LUI V0, 0xBFD2
-BFD004C8 3042BFD2 LDC1 F30, 12354(S2)
-BFD004CA 81343042 ADDIU V0, V0, -32460
-BFD004CE E9A6 SW V1, 24(V0)
+BFD004C2 08FC006E MFC0 V1, $14, 1\r
+BFD004C4 08FC LBU S1, 12(A3)\r
+BFD004C6 BFD241A2 LUI V0, 0xBFD2\r
+BFD004C8 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD004CA 81343042 ADDIU V0, V0, -32460\r
+BFD004CE E9A6 SW V1, 24(V0)\r
76: gexc_cap.cp0_badvaddr = _CP0_GET_BADVADDR();\r
-BFD004D0 00FC0068 MFC0 V1, BadVAddr
-BFD004D4 BFD241A2 LUI V0, 0xBFD2
-BFD004D6 3042BFD2 LDC1 F30, 12354(S2)
-BFD004D8 81343042 ADDIU V0, V0, -32460
-BFD004DC E9A7 SW V1, 28(V0)
+BFD004D0 00FC0068 MFC0 V1, BadVAddr\r
+BFD004D4 BFD241A2 LUI V0, 0xBFD2\r
+BFD004D6 3042BFD2 LDC1 F30, 12354(S2)\r
+BFD004D8 81343042 ADDIU V0, V0, -32460\r
+BFD004DC E9A7 SW V1, 28(V0)\r
77: \r
78: trace0(0, AP3GENEXCEPT, 0, "Application General Exception Handler (BEV=0)");\r
79: TRACE11(601, AP3GENEXCEPT, 0, "Current SP = 0x%08x",gexc_cap.stack_ptr);\r
-BFD004DE A00041A2 LUI V0, 0xA000
-BFD004E2 8C005042 ORI V0, V0, -29696
-BFD004E4 8C00 BEQZ S0, 0xBFD004E6
-BFD004E6 FFFD3060 ADDIU V1, ZERO, -3
-BFD004E8 89A0FFFD LW RA, -30304(SP)
-BFD004EA 89A0 SB V1, 0(V0)
-BFD004EC A00041A2 LUI V0, 0xA000
-BFD004F0 8C005042 ORI V0, V0, -29696
-BFD004F2 8C00 BEQZ S0, 0xBFD004F4
-BFD004F4 EDD9 LI V1, 89
-BFD004F6 89A0 SB V1, 0(V0)
-BFD004F8 A00041A2 LUI V0, 0xA000
-BFD004FC 8C005042 ORI V0, V0, -29696
-BFD004FE 8C00 BEQZ S0, 0xBFD00500
-BFD00500 ED82 LI V1, 2
-BFD00502 89A0 SB V1, 0(V0)
-BFD00504 A00041A2 LUI V0, 0xA000
-BFD00508 8C005042 ORI V0, V0, -29696
-BFD0050A 8C00 BEQZ S0, 0xBFD0050C
-BFD0050C BFD241A3 LUI V1, 0xBFD2
-BFD0050E FC63BFD2 LDC1 F30, -925(S2)
-BFD00510 8134FC63 LW V1, -32460(V1)
-BFD00514 2DBD ANDI V1, V1, 0xFF
-BFD00516 89A0 SB V1, 0(V0)
-BFD00518 A00041A2 LUI V0, 0xA000
-BFD0051C 8C005042 ORI V0, V0, -29696
-BFD0051E 8C00 BEQZ S0, 0xBFD00520
-BFD00520 BFD241A3 LUI V1, 0xBFD2
-BFD00522 FC63BFD2 LDC1 F30, -925(S2)
-BFD00524 8134FC63 LW V1, -32460(V1)
-BFD00528 25B1 SRL V1, V1, 8
-BFD0052A 2DBD ANDI V1, V1, 0xFF
-BFD0052C 89A0 SB V1, 0(V0)
-BFD0052E A00041A2 LUI V0, 0xA000
-BFD00532 8C005042 ORI V0, V0, -29696
-BFD00534 8C00 BEQZ S0, 0xBFD00536
-BFD00536 BFD241A3 LUI V1, 0xBFD2
-BFD00538 FC63BFD2 LDC1 F30, -925(S2)
-BFD0053A 8134FC63 LW V1, -32460(V1)
-BFD0053E 80400063 SRL V1, V1, 16
-BFD00542 2DBD ANDI V1, V1, 0xFF
-BFD00544 89A0 SB V1, 0(V0)
-BFD00546 A00041A2 LUI V0, 0xA000
-BFD0054A 8C005042 ORI V0, V0, -29696
-BFD0054C 8C00 BEQZ S0, 0xBFD0054E
-BFD0054E BFD241A3 LUI V1, 0xBFD2
-BFD00550 FC63BFD2 LDC1 F30, -925(S2)
-BFD00552 8134FC63 LW V1, -32460(V1)
-BFD00556 C0400063 SRL V1, V1, 24
-BFD0055A 2DBD ANDI V1, V1, 0xFF
-BFD0055C 89A0 SB V1, 0(V0)
+BFD004DE A00041A2 LUI V0, 0xA000\r
+BFD004E2 8C005042 ORI V0, V0, -29696\r
+BFD004E4 8C00 BEQZ S0, 0xBFD004E6\r
+BFD004E6 FFFD3060 ADDIU V1, ZERO, -3\r
+BFD004E8 89A0FFFD LW RA, -30304(SP)\r
+BFD004EA 89A0 SB V1, 0(V0)\r
+BFD004EC A00041A2 LUI V0, 0xA000\r
+BFD004F0 8C005042 ORI V0, V0, -29696\r
+BFD004F2 8C00 BEQZ S0, 0xBFD004F4\r
+BFD004F4 EDD9 LI V1, 89\r
+BFD004F6 89A0 SB V1, 0(V0)\r
+BFD004F8 A00041A2 LUI V0, 0xA000\r
+BFD004FC 8C005042 ORI V0, V0, -29696\r
+BFD004FE 8C00 BEQZ S0, 0xBFD00500\r
+BFD00500 ED82 LI V1, 2\r
+BFD00502 89A0 SB V1, 0(V0)\r
+BFD00504 A00041A2 LUI V0, 0xA000\r
+BFD00508 8C005042 ORI V0, V0, -29696\r
+BFD0050A 8C00 BEQZ S0, 0xBFD0050C\r
+BFD0050C BFD241A3 LUI V1, 0xBFD2\r
+BFD0050E FC63BFD2 LDC1 F30, -925(S2)\r
+BFD00510 8134FC63 LW V1, -32460(V1)\r
+BFD00514 2DBD ANDI V1, V1, 0xFF\r
+BFD00516 89A0 SB V1, 0(V0)\r
+BFD00518 A00041A2 LUI V0, 0xA000\r
+BFD0051C 8C005042 ORI V0, V0, -29696\r
+BFD0051E 8C00 BEQZ S0, 0xBFD00520\r
+BFD00520 BFD241A3 LUI V1, 0xBFD2\r
+BFD00522 FC63BFD2 LDC1 F30, -925(S2)\r
+BFD00524 8134FC63 LW V1, -32460(V1)\r
+BFD00528 25B1 SRL V1, V1, 8\r
+BFD0052A 2DBD ANDI V1, V1, 0xFF\r
+BFD0052C 89A0 SB V1, 0(V0)\r
+BFD0052E A00041A2 LUI V0, 0xA000\r
+BFD00532 8C005042 ORI V0, V0, -29696\r
+BFD00534 8C00 BEQZ S0, 0xBFD00536\r
+BFD00536 BFD241A3 LUI V1, 0xBFD2\r
+BFD00538 FC63BFD2 LDC1 F30, -925(S2)\r
+BFD0053A 8134FC63 LW V1, -32460(V1)\r
+BFD0053E 80400063 SRL V1, V1, 16\r
+BFD00542 2DBD ANDI V1, V1, 0xFF\r
+BFD00544 89A0 SB V1, 0(V0)\r
+BFD00546 A00041A2 LUI V0, 0xA000\r
+BFD0054A 8C005042 ORI V0, V0, -29696\r
+BFD0054C 8C00 BEQZ S0, 0xBFD0054E\r
+BFD0054E BFD241A3 LUI V1, 0xBFD2\r
+BFD00550 FC63BFD2 LDC1 F30, -925(S2)\r
+BFD00552 8134FC63 LW V1, -32460(V1)\r
+BFD00556 C0400063 SRL V1, V1, 24\r
+BFD0055A 2DBD ANDI V1, V1, 0xFF\r
+BFD0055C 89A0 SB V1, 0(V0)\r
80: TRACE11(602, AP3GENEXCEPT, 0, "CP0 STATUS = 0x%08x",gexc_cap.cp0_status);\r
-BFD0055E A00041A2 LUI V0, 0xA000
-BFD00562 8C005042 ORI V0, V0, -29696
-BFD00564 8C00 BEQZ S0, 0xBFD00566
-BFD00566 FFFD3060 ADDIU V1, ZERO, -3
-BFD00568 89A0FFFD LW RA, -30304(SP)
-BFD0056A 89A0 SB V1, 0(V0)
-BFD0056C A00041A2 LUI V0, 0xA000
-BFD00570 8C005042 ORI V0, V0, -29696
-BFD00572 8C00 BEQZ S0, 0xBFD00574
-BFD00574 EDDA LI V1, 90
-BFD00576 89A0 SB V1, 0(V0)
-BFD00578 A00041A2 LUI V0, 0xA000
-BFD0057C 8C005042 ORI V0, V0, -29696
-BFD0057E 8C00 BEQZ S0, 0xBFD00580
-BFD00580 ED82 LI V1, 2
-BFD00582 89A0 SB V1, 0(V0)
-BFD00584 A00041A2 LUI V0, 0xA000
-BFD00588 8C005042 ORI V0, V0, -29696
-BFD0058A 8C00 BEQZ S0, 0xBFD0058C
-BFD0058C BFD241A3 LUI V1, 0xBFD2
-BFD0058E 3063BFD2 LDC1 F30, 12387(S2)
-BFD00590 81343063 ADDIU V1, V1, -32460
-BFD00594 69B1 LW V1, 4(V1)
-BFD00596 2DBD ANDI V1, V1, 0xFF
-BFD00598 89A0 SB V1, 0(V0)
-BFD0059A A00041A2 LUI V0, 0xA000
-BFD0059E 8C005042 ORI V0, V0, -29696
-BFD005A0 8C00 BEQZ S0, 0xBFD005A2
-BFD005A2 BFD241A3 LUI V1, 0xBFD2
-BFD005A4 3063BFD2 LDC1 F30, 12387(S2)
-BFD005A6 81343063 ADDIU V1, V1, -32460
-BFD005AA 69B1 LW V1, 4(V1)
-BFD005AC 25B1 SRL V1, V1, 8
-BFD005AE 2DBD ANDI V1, V1, 0xFF
-BFD005B0 89A0 SB V1, 0(V0)
-BFD005B2 A00041A2 LUI V0, 0xA000
-BFD005B6 8C005042 ORI V0, V0, -29696
-BFD005B8 8C00 BEQZ S0, 0xBFD005BA
-BFD005BA BFD241A3 LUI V1, 0xBFD2
-BFD005BC 3063BFD2 LDC1 F30, 12387(S2)
-BFD005BE 81343063 ADDIU V1, V1, -32460
-BFD005C2 69B1 LW V1, 4(V1)
-BFD005C4 80400063 SRL V1, V1, 16
-BFD005C8 2DBD ANDI V1, V1, 0xFF
-BFD005CA 89A0 SB V1, 0(V0)
-BFD005CC A00041A2 LUI V0, 0xA000
-BFD005D0 8C005042 ORI V0, V0, -29696
-BFD005D2 8C00 BEQZ S0, 0xBFD005D4
-BFD005D4 BFD241A3 LUI V1, 0xBFD2
-BFD005D6 3063BFD2 LDC1 F30, 12387(S2)
-BFD005D8 81343063 ADDIU V1, V1, -32460
-BFD005DC 69B1 LW V1, 4(V1)
-BFD005DE C0400063 SRL V1, V1, 24
-BFD005E2 2DBD ANDI V1, V1, 0xFF
-BFD005E4 89A0 SB V1, 0(V0)
+BFD0055E A00041A2 LUI V0, 0xA000\r
+BFD00562 8C005042 ORI V0, V0, -29696\r
+BFD00564 8C00 BEQZ S0, 0xBFD00566\r
+BFD00566 FFFD3060 ADDIU V1, ZERO, -3\r
+BFD00568 89A0FFFD LW RA, -30304(SP)\r
+BFD0056A 89A0 SB V1, 0(V0)\r
+BFD0056C A00041A2 LUI V0, 0xA000\r
+BFD00570 8C005042 ORI V0, V0, -29696\r
+BFD00572 8C00 BEQZ S0, 0xBFD00574\r
+BFD00574 EDDA LI V1, 90\r
+BFD00576 89A0 SB V1, 0(V0)\r
+BFD00578 A00041A2 LUI V0, 0xA000\r
+BFD0057C 8C005042 ORI V0, V0, -29696\r
+BFD0057E 8C00 BEQZ S0, 0xBFD00580\r
+BFD00580 ED82 LI V1, 2\r
+BFD00582 89A0 SB V1, 0(V0)\r
+BFD00584 A00041A2 LUI V0, 0xA000\r
+BFD00588 8C005042 ORI V0, V0, -29696\r
+BFD0058A 8C00 BEQZ S0, 0xBFD0058C\r
+BFD0058C BFD241A3 LUI V1, 0xBFD2\r
+BFD0058E 3063BFD2 LDC1 F30, 12387(S2)\r
+BFD00590 81343063 ADDIU V1, V1, -32460\r
+BFD00594 69B1 LW V1, 4(V1)\r
+BFD00596 2DBD ANDI V1, V1, 0xFF\r
+BFD00598 89A0 SB V1, 0(V0)\r
+BFD0059A A00041A2 LUI V0, 0xA000\r
+BFD0059E 8C005042 ORI V0, V0, -29696\r
+BFD005A0 8C00 BEQZ S0, 0xBFD005A2\r
+BFD005A2 BFD241A3 LUI V1, 0xBFD2\r
+BFD005A4 3063BFD2 LDC1 F30, 12387(S2)\r
+BFD005A6 81343063 ADDIU V1, V1, -32460\r
+BFD005AA 69B1 LW V1, 4(V1)\r
+BFD005AC 25B1 SRL V1, V1, 8\r
+BFD005AE 2DBD ANDI V1, V1, 0xFF\r
+BFD005B0 89A0 SB V1, 0(V0)\r
+BFD005B2 A00041A2 LUI V0, 0xA000\r
+BFD005B6 8C005042 ORI V0, V0, -29696\r
+BFD005B8 8C00 BEQZ S0, 0xBFD005BA\r
+BFD005BA BFD241A3 LUI V1, 0xBFD2\r
+BFD005BC 3063BFD2 LDC1 F30, 12387(S2)\r
+BFD005BE 81343063 ADDIU V1, V1, -32460\r
+BFD005C2 69B1 LW V1, 4(V1)\r
+BFD005C4 80400063 SRL V1, V1, 16\r
+BFD005C8 2DBD ANDI V1, V1, 0xFF\r
+BFD005CA 89A0 SB V1, 0(V0)\r
+BFD005CC A00041A2 LUI V0, 0xA000\r
+BFD005D0 8C005042 ORI V0, V0, -29696\r
+BFD005D2 8C00 BEQZ S0, 0xBFD005D4\r
+BFD005D4 BFD241A3 LUI V1, 0xBFD2\r
+BFD005D6 3063BFD2 LDC1 F30, 12387(S2)\r
+BFD005D8 81343063 ADDIU V1, V1, -32460\r
+BFD005DC 69B1 LW V1, 4(V1)\r
+BFD005DE C0400063 SRL V1, V1, 24\r
+BFD005E2 2DBD ANDI V1, V1, 0xFF\r
+BFD005E4 89A0 SB V1, 0(V0)\r
81: TRACE11(603, AP3GENEXCEPT, 0, "CP0 CAUSE = 0x%08x",gexc_cap.cp0_cause);\r
-BFD005E6 A00041A2 LUI V0, 0xA000
-BFD005EA 8C005042 ORI V0, V0, -29696
-BFD005EC 8C00 BEQZ S0, 0xBFD005EE
-BFD005EE FFFD3060 ADDIU V1, ZERO, -3
-BFD005F0 89A0FFFD LW RA, -30304(SP)
-BFD005F2 89A0 SB V1, 0(V0)
-BFD005F4 A00041A2 LUI V0, 0xA000
-BFD005F8 8C005042 ORI V0, V0, -29696
-BFD005FA 8C00 BEQZ S0, 0xBFD005FC
-BFD005FC EDDB LI V1, 91
-BFD005FE 89A0 SB V1, 0(V0)
-BFD00600 A00041A2 LUI V0, 0xA000
-BFD00604 8C005042 ORI V0, V0, -29696
-BFD00606 8C00 BEQZ S0, 0xBFD00608
-BFD00608 ED82 LI V1, 2
-BFD0060A 89A0 SB V1, 0(V0)
-BFD0060C A00041A2 LUI V0, 0xA000
-BFD00610 8C005042 ORI V0, V0, -29696
-BFD00612 8C00 BEQZ S0, 0xBFD00614
-BFD00614 BFD241A3 LUI V1, 0xBFD2
-BFD00616 3063BFD2 LDC1 F30, 12387(S2)
-BFD00618 81343063 ADDIU V1, V1, -32460
-BFD0061C 69B2 LW V1, 8(V1)
-BFD0061E 2DBD ANDI V1, V1, 0xFF
-BFD00620 89A0 SB V1, 0(V0)
-BFD00622 A00041A2 LUI V0, 0xA000
-BFD00626 8C005042 ORI V0, V0, -29696
-BFD00628 8C00 BEQZ S0, 0xBFD0062A
-BFD0062A BFD241A3 LUI V1, 0xBFD2
-BFD0062C 3063BFD2 LDC1 F30, 12387(S2)
-BFD0062E 81343063 ADDIU V1, V1, -32460
-BFD00632 69B2 LW V1, 8(V1)
-BFD00634 25B1 SRL V1, V1, 8
-BFD00636 2DBD ANDI V1, V1, 0xFF
-BFD00638 89A0 SB V1, 0(V0)
-BFD0063A A00041A2 LUI V0, 0xA000
-BFD0063E 8C005042 ORI V0, V0, -29696
-BFD00640 8C00 BEQZ S0, 0xBFD00642
-BFD00642 BFD241A3 LUI V1, 0xBFD2
-BFD00644 3063BFD2 LDC1 F30, 12387(S2)
-BFD00646 81343063 ADDIU V1, V1, -32460
-BFD0064A 69B2 LW V1, 8(V1)
-BFD0064C 80400063 SRL V1, V1, 16
-BFD00650 2DBD ANDI V1, V1, 0xFF
-BFD00652 89A0 SB V1, 0(V0)
-BFD00654 A00041A2 LUI V0, 0xA000
-BFD00658 8C005042 ORI V0, V0, -29696
-BFD0065A 8C00 BEQZ S0, 0xBFD0065C
-BFD0065C BFD241A3 LUI V1, 0xBFD2
-BFD0065E 3063BFD2 LDC1 F30, 12387(S2)
-BFD00660 81343063 ADDIU V1, V1, -32460
-BFD00664 69B2 LW V1, 8(V1)
-BFD00666 C0400063 SRL V1, V1, 24
-BFD0066A 2DBD ANDI V1, V1, 0xFF
-BFD0066C 89A0 SB V1, 0(V0)
+BFD005E6 A00041A2 LUI V0, 0xA000\r
+BFD005EA 8C005042 ORI V0, V0, -29696\r
+BFD005EC 8C00 BEQZ S0, 0xBFD005EE\r
+BFD005EE FFFD3060 ADDIU V1, ZERO, -3\r
+BFD005F0 89A0FFFD LW RA, -30304(SP)\r
+BFD005F2 89A0 SB V1, 0(V0)\r
+BFD005F4 A00041A2 LUI V0, 0xA000\r
+BFD005F8 8C005042 ORI V0, V0, -29696\r
+BFD005FA 8C00 BEQZ S0, 0xBFD005FC\r
+BFD005FC EDDB LI V1, 91\r
+BFD005FE 89A0 SB V1, 0(V0)\r
+BFD00600 A00041A2 LUI V0, 0xA000\r
+BFD00604 8C005042 ORI V0, V0, -29696\r
+BFD00606 8C00 BEQZ S0, 0xBFD00608\r
+BFD00608 ED82 LI V1, 2\r
+BFD0060A 89A0 SB V1, 0(V0)\r
+BFD0060C A00041A2 LUI V0, 0xA000\r
+BFD00610 8C005042 ORI V0, V0, -29696\r
+BFD00612 8C00 BEQZ S0, 0xBFD00614\r
+BFD00614 BFD241A3 LUI V1, 0xBFD2\r
+BFD00616 3063BFD2 LDC1 F30, 12387(S2)\r
+BFD00618 81343063 ADDIU V1, V1, -32460\r
+BFD0061C 69B2 LW V1, 8(V1)\r
+BFD0061E 2DBD ANDI V1, V1, 0xFF\r
+BFD00620 89A0 SB V1, 0(V0)\r
+BFD00622 A00041A2 LUI V0, 0xA000\r
+BFD00626 8C005042 ORI V0, V0, -29696\r
+BFD00628 8C00 BEQZ S0, 0xBFD0062A\r
+BFD0062A BFD241A3 LUI V1, 0xBFD2\r
+BFD0062C 3063BFD2 LDC1 F30, 12387(S2)\r
+BFD0062E 81343063 ADDIU V1, V1, -32460\r
+BFD00632 69B2 LW V1, 8(V1)\r
+BFD00634 25B1 SRL V1, V1, 8\r
+BFD00636 2DBD ANDI V1, V1, 0xFF\r
+BFD00638 89A0 SB V1, 0(V0)\r
+BFD0063A A00041A2 LUI V0, 0xA000\r
+BFD0063E 8C005042 ORI V0, V0, -29696\r
+BFD00640 8C00 BEQZ S0, 0xBFD00642\r
+BFD00642 BFD241A3 LUI V1, 0xBFD2\r
+BFD00644 3063BFD2 LDC1 F30, 12387(S2)\r
+BFD00646 81343063 ADDIU V1, V1, -32460\r
+BFD0064A 69B2 LW V1, 8(V1)\r
+BFD0064C 80400063 SRL V1, V1, 16\r
+BFD00650 2DBD ANDI V1, V1, 0xFF\r
+BFD00652 89A0 SB V1, 0(V0)\r
+BFD00654 A00041A2 LUI V0, 0xA000\r
+BFD00658 8C005042 ORI V0, V0, -29696\r
+BFD0065A 8C00 BEQZ S0, 0xBFD0065C\r
+BFD0065C BFD241A3 LUI V1, 0xBFD2\r
+BFD0065E 3063BFD2 LDC1 F30, 12387(S2)\r
+BFD00660 81343063 ADDIU V1, V1, -32460\r
+BFD00664 69B2 LW V1, 8(V1)\r
+BFD00666 C0400063 SRL V1, V1, 24\r
+BFD0066A 2DBD ANDI V1, V1, 0xFF\r
+BFD0066C 89A0 SB V1, 0(V0)\r
82: TRACE11(604, AP3GENEXCEPT, 0, "CP0 EPC = 0x%08x",gexc_cap.cp0_epc);\r
-BFD0066E A00041A2 LUI V0, 0xA000
-BFD00672 8C005042 ORI V0, V0, -29696
-BFD00674 8C00 BEQZ S0, 0xBFD00676
-BFD00676 FFFD3060 ADDIU V1, ZERO, -3
-BFD00678 89A0FFFD LW RA, -30304(SP)
-BFD0067A 89A0 SB V1, 0(V0)
-BFD0067C A00041A2 LUI V0, 0xA000
-BFD00680 8C005042 ORI V0, V0, -29696
-BFD00682 8C00 BEQZ S0, 0xBFD00684
-BFD00684 EDDC LI V1, 92
-BFD00686 89A0 SB V1, 0(V0)
-BFD00688 A00041A2 LUI V0, 0xA000
-BFD0068C 8C005042 ORI V0, V0, -29696
-BFD0068E 8C00 BEQZ S0, 0xBFD00690
-BFD00690 ED82 LI V1, 2
-BFD00692 89A0 SB V1, 0(V0)
-BFD00694 A00041A2 LUI V0, 0xA000
-BFD00698 8C005042 ORI V0, V0, -29696
-BFD0069A 8C00 BEQZ S0, 0xBFD0069C
-BFD0069C BFD241A3 LUI V1, 0xBFD2
-BFD0069E 3063BFD2 LDC1 F30, 12387(S2)
-BFD006A0 81343063 ADDIU V1, V1, -32460
-BFD006A4 69B3 LW V1, 12(V1)
-BFD006A6 2DBD ANDI V1, V1, 0xFF
-BFD006A8 89A0 SB V1, 0(V0)
-BFD006AA A00041A2 LUI V0, 0xA000
-BFD006AE 8C005042 ORI V0, V0, -29696
-BFD006B0 8C00 BEQZ S0, 0xBFD006B2
-BFD006B2 BFD241A3 LUI V1, 0xBFD2
-BFD006B4 3063BFD2 LDC1 F30, 12387(S2)
-BFD006B6 81343063 ADDIU V1, V1, -32460
-BFD006BA 69B3 LW V1, 12(V1)
-BFD006BC 25B1 SRL V1, V1, 8
-BFD006BE 2DBD ANDI V1, V1, 0xFF
-BFD006C0 89A0 SB V1, 0(V0)
-BFD006C2 A00041A2 LUI V0, 0xA000
-BFD006C6 8C005042 ORI V0, V0, -29696
-BFD006C8 8C00 BEQZ S0, 0xBFD006CA
-BFD006CA BFD241A3 LUI V1, 0xBFD2
-BFD006CC 3063BFD2 LDC1 F30, 12387(S2)
-BFD006CE 81343063 ADDIU V1, V1, -32460
-BFD006D2 69B3 LW V1, 12(V1)
-BFD006D4 80400063 SRL V1, V1, 16
-BFD006D8 2DBD ANDI V1, V1, 0xFF
-BFD006DA 89A0 SB V1, 0(V0)
-BFD006DC A00041A2 LUI V0, 0xA000
-BFD006E0 8C005042 ORI V0, V0, -29696
-BFD006E2 8C00 BEQZ S0, 0xBFD006E4
-BFD006E4 BFD241A3 LUI V1, 0xBFD2
-BFD006E6 3063BFD2 LDC1 F30, 12387(S2)
-BFD006E8 81343063 ADDIU V1, V1, -32460
-BFD006EC 69B3 LW V1, 12(V1)
-BFD006EE C0400063 SRL V1, V1, 24
-BFD006F2 2DBD ANDI V1, V1, 0xFF
-BFD006F4 89A0 SB V1, 0(V0)
+BFD0066E A00041A2 LUI V0, 0xA000\r
+BFD00672 8C005042 ORI V0, V0, -29696\r
+BFD00674 8C00 BEQZ S0, 0xBFD00676\r
+BFD00676 FFFD3060 ADDIU V1, ZERO, -3\r
+BFD00678 89A0FFFD LW RA, -30304(SP)\r
+BFD0067A 89A0 SB V1, 0(V0)\r
+BFD0067C A00041A2 LUI V0, 0xA000\r
+BFD00680 8C005042 ORI V0, V0, -29696\r
+BFD00682 8C00 BEQZ S0, 0xBFD00684\r
+BFD00684 EDDC LI V1, 92\r
+BFD00686 89A0 SB V1, 0(V0)\r
+BFD00688 A00041A2 LUI V0, 0xA000\r
+BFD0068C 8C005042 ORI V0, V0, -29696\r
+BFD0068E 8C00 BEQZ S0, 0xBFD00690\r
+BFD00690 ED82 LI V1, 2\r
+BFD00692 89A0 SB V1, 0(V0)\r
+BFD00694 A00041A2 LUI V0, 0xA000\r
+BFD00698 8C005042 ORI V0, V0, -29696\r
+BFD0069A 8C00 BEQZ S0, 0xBFD0069C\r
+BFD0069C BFD241A3 LUI V1, 0xBFD2\r
+BFD0069E 3063BFD2 LDC1 F30, 12387(S2)\r
+BFD006A0 81343063 ADDIU V1, V1, -32460\r
+BFD006A4 69B3 LW V1, 12(V1)\r
+BFD006A6 2DBD ANDI V1, V1, 0xFF\r
+BFD006A8 89A0 SB V1, 0(V0)\r
+BFD006AA A00041A2 LUI V0, 0xA000\r
+BFD006AE 8C005042 ORI V0, V0, -29696\r
+BFD006B0 8C00 BEQZ S0, 0xBFD006B2\r
+BFD006B2 BFD241A3 LUI V1, 0xBFD2\r
+BFD006B4 3063BFD2 LDC1 F30, 12387(S2)\r
+BFD006B6 81343063 ADDIU V1, V1, -32460\r
+BFD006BA 69B3 LW V1, 12(V1)\r
+BFD006BC 25B1 SRL V1, V1, 8\r
+BFD006BE 2DBD ANDI V1, V1, 0xFF\r
+BFD006C0 89A0 SB V1, 0(V0)\r
+BFD006C2 A00041A2 LUI V0, 0xA000\r
+BFD006C6 8C005042 ORI V0, V0, -29696\r
+BFD006C8 8C00 BEQZ S0, 0xBFD006CA\r
+BFD006CA BFD241A3 LUI V1, 0xBFD2\r
+BFD006CC 3063BFD2 LDC1 F30, 12387(S2)\r
+BFD006CE 81343063 ADDIU V1, V1, -32460\r
+BFD006D2 69B3 LW V1, 12(V1)\r
+BFD006D4 80400063 SRL V1, V1, 16\r
+BFD006D8 2DBD ANDI V1, V1, 0xFF\r
+BFD006DA 89A0 SB V1, 0(V0)\r
+BFD006DC A00041A2 LUI V0, 0xA000\r
+BFD006E0 8C005042 ORI V0, V0, -29696\r
+BFD006E2 8C00 BEQZ S0, 0xBFD006E4\r
+BFD006E4 BFD241A3 LUI V1, 0xBFD2\r
+BFD006E6 3063BFD2 LDC1 F30, 12387(S2)\r
+BFD006E8 81343063 ADDIU V1, V1, -32460\r
+BFD006EC 69B3 LW V1, 12(V1)\r
+BFD006EE C0400063 SRL V1, V1, 24\r
+BFD006F2 2DBD ANDI V1, V1, 0xFF\r
+BFD006F4 89A0 SB V1, 0(V0)\r
83: TRACE11(605, AP3GENEXCEPT, 0, "CP0 ERROREPC = 0x%08x",gexc_cap.cp0_error_epc);\r
-BFD006F6 A00041A2 LUI V0, 0xA000
-BFD006FA 8C005042 ORI V0, V0, -29696
-BFD006FC 8C00 BEQZ S0, 0xBFD006FE
-BFD006FE FFFD3060 ADDIU V1, ZERO, -3
-BFD00700 89A0FFFD LW RA, -30304(SP)
-BFD00702 89A0 SB V1, 0(V0)
-BFD00704 A00041A2 LUI V0, 0xA000
-BFD00708 8C005042 ORI V0, V0, -29696
-BFD0070A 8C00 BEQZ S0, 0xBFD0070C
-BFD0070C EDDD LI V1, 93
-BFD0070E 89A0 SB V1, 0(V0)
-BFD00710 A00041A2 LUI V0, 0xA000
-BFD00714 8C005042 ORI V0, V0, -29696
-BFD00716 8C00 BEQZ S0, 0xBFD00718
-BFD00718 ED82 LI V1, 2
-BFD0071A 89A0 SB V1, 0(V0)
-BFD0071C A00041A2 LUI V0, 0xA000
-BFD00720 8C005042 ORI V0, V0, -29696
-BFD00722 8C00 BEQZ S0, 0xBFD00724
-BFD00724 BFD241A3 LUI V1, 0xBFD2
-BFD00726 3063BFD2 LDC1 F30, 12387(S2)
-BFD00728 81343063 ADDIU V1, V1, -32460
-BFD0072C 69B4 LW V1, 16(V1)
-BFD0072E 2DBD ANDI V1, V1, 0xFF
-BFD00730 89A0 SB V1, 0(V0)
-BFD00732 A00041A2 LUI V0, 0xA000
-BFD00736 8C005042 ORI V0, V0, -29696
-BFD00738 8C00 BEQZ S0, 0xBFD0073A
-BFD0073A BFD241A3 LUI V1, 0xBFD2
-BFD0073C 3063BFD2 LDC1 F30, 12387(S2)
-BFD0073E 81343063 ADDIU V1, V1, -32460
-BFD00742 69B4 LW V1, 16(V1)
-BFD00744 25B1 SRL V1, V1, 8
-BFD00746 2DBD ANDI V1, V1, 0xFF
-BFD00748 89A0 SB V1, 0(V0)
-BFD0074A A00041A2 LUI V0, 0xA000
-BFD0074E 8C005042 ORI V0, V0, -29696
-BFD00750 8C00 BEQZ S0, 0xBFD00752
-BFD00752 BFD241A3 LUI V1, 0xBFD2
-BFD00754 3063BFD2 LDC1 F30, 12387(S2)
-BFD00756 81343063 ADDIU V1, V1, -32460
-BFD0075A 69B4 LW V1, 16(V1)
-BFD0075C 80400063 SRL V1, V1, 16
-BFD00760 2DBD ANDI V1, V1, 0xFF
-BFD00762 89A0 SB V1, 0(V0)
-BFD00764 A00041A2 LUI V0, 0xA000
-BFD00768 8C005042 ORI V0, V0, -29696
-BFD0076A 8C00 BEQZ S0, 0xBFD0076C
-BFD0076C BFD241A3 LUI V1, 0xBFD2
-BFD0076E 3063BFD2 LDC1 F30, 12387(S2)
-BFD00770 81343063 ADDIU V1, V1, -32460
-BFD00774 69B4 LW V1, 16(V1)
-BFD00776 C0400063 SRL V1, V1, 24
-BFD0077A 2DBD ANDI V1, V1, 0xFF
-BFD0077C 89A0 SB V1, 0(V0)
+BFD006F6 A00041A2 LUI V0, 0xA000\r
+BFD006FA 8C005042 ORI V0, V0, -29696\r
+BFD006FC 8C00 BEQZ S0, 0xBFD006FE\r
+BFD006FE FFFD3060 ADDIU V1, ZERO, -3\r
+BFD00700 89A0FFFD LW RA, -30304(SP)\r
+BFD00702 89A0 SB V1, 0(V0)\r
+BFD00704 A00041A2 LUI V0, 0xA000\r
+BFD00708 8C005042 ORI V0, V0, -29696\r
+BFD0070A 8C00 BEQZ S0, 0xBFD0070C\r
+BFD0070C EDDD LI V1, 93\r
+BFD0070E 89A0 SB V1, 0(V0)\r
+BFD00710 A00041A2 LUI V0, 0xA000\r
+BFD00714 8C005042 ORI V0, V0, -29696\r
+BFD00716 8C00 BEQZ S0, 0xBFD00718\r
+BFD00718 ED82 LI V1, 2\r
+BFD0071A 89A0 SB V1, 0(V0)\r
+BFD0071C A00041A2 LUI V0, 0xA000\r
+BFD00720 8C005042 ORI V0, V0, -29696\r
+BFD00722 8C00 BEQZ S0, 0xBFD00724\r
+BFD00724 BFD241A3 LUI V1, 0xBFD2\r
+BFD00726 3063BFD2 LDC1 F30, 12387(S2)\r
+BFD00728 81343063 ADDIU V1, V1, -32460\r
+BFD0072C 69B4 LW V1, 16(V1)\r
+BFD0072E 2DBD ANDI V1, V1, 0xFF\r
+BFD00730 89A0 SB V1, 0(V0)\r
+BFD00732 A00041A2 LUI V0, 0xA000\r
+BFD00736 8C005042 ORI V0, V0, -29696\r
+BFD00738 8C00 BEQZ S0, 0xBFD0073A\r
+BFD0073A BFD241A3 LUI V1, 0xBFD2\r
+BFD0073C 3063BFD2 LDC1 F30, 12387(S2)\r
+BFD0073E 81343063 ADDIU V1, V1, -32460\r
+BFD00742 69B4 LW V1, 16(V1)\r
+BFD00744 25B1 SRL V1, V1, 8\r
+BFD00746 2DBD ANDI V1, V1, 0xFF\r
+BFD00748 89A0 SB V1, 0(V0)\r
+BFD0074A A00041A2 LUI V0, 0xA000\r
+BFD0074E 8C005042 ORI V0, V0, -29696\r
+BFD00750 8C00 BEQZ S0, 0xBFD00752\r
+BFD00752 BFD241A3 LUI V1, 0xBFD2\r
+BFD00754 3063BFD2 LDC1 F30, 12387(S2)\r
+BFD00756 81343063 ADDIU V1, V1, -32460\r
+BFD0075A 69B4 LW V1, 16(V1)\r
+BFD0075C 80400063 SRL V1, V1, 16\r
+BFD00760 2DBD ANDI V1, V1, 0xFF\r
+BFD00762 89A0 SB V1, 0(V0)\r
+BFD00764 A00041A2 LUI V0, 0xA000\r
+BFD00768 8C005042 ORI V0, V0, -29696\r
+BFD0076A 8C00 BEQZ S0, 0xBFD0076C\r
+BFD0076C BFD241A3 LUI V1, 0xBFD2\r
+BFD0076E 3063BFD2 LDC1 F30, 12387(S2)\r
+BFD00770 81343063 ADDIU V1, V1, -32460\r
+BFD00774 69B4 LW V1, 16(V1)\r
+BFD00776 C0400063 SRL V1, V1, 24\r
+BFD0077A 2DBD ANDI V1, V1, 0xFF\r
+BFD0077C 89A0 SB V1, 0(V0)\r
84: TRACE11(606, AP3GENEXCEPT, 0, "CP0 NEXC = 0x%08x",gexc_cap.cp0_nexc);\r
-BFD0077E A00041A2 LUI V0, 0xA000
-BFD00782 8C005042 ORI V0, V0, -29696
-BFD00784 8C00 BEQZ S0, 0xBFD00786
-BFD00786 FFFD3060 ADDIU V1, ZERO, -3
-BFD00788 89A0FFFD LW RA, -30304(SP)
-BFD0078A 89A0 SB V1, 0(V0)
-BFD0078C A00041A2 LUI V0, 0xA000
-BFD00790 8C005042 ORI V0, V0, -29696
-BFD00792 8C00 BEQZ S0, 0xBFD00794
-BFD00794 EDDE LI V1, 94
-BFD00796 89A0 SB V1, 0(V0)
-BFD00798 A00041A2 LUI V0, 0xA000
-BFD0079C 8C005042 ORI V0, V0, -29696
-BFD0079E 8C00 BEQZ S0, 0xBFD007A0
-BFD007A0 ED82 LI V1, 2
-BFD007A2 89A0 SB V1, 0(V0)
-BFD007A4 A00041A2 LUI V0, 0xA000
-BFD007A8 8C005042 ORI V0, V0, -29696
-BFD007AA 8C00 BEQZ S0, 0xBFD007AC
-BFD007AC BFD241A3 LUI V1, 0xBFD2
-BFD007AE 3063BFD2 LDC1 F30, 12387(S2)
-BFD007B0 81343063 ADDIU V1, V1, -32460
-BFD007B4 69B5 LW V1, 20(V1)
-BFD007B6 2DBD ANDI V1, V1, 0xFF
-BFD007B8 89A0 SB V1, 0(V0)
-BFD007BA A00041A2 LUI V0, 0xA000
-BFD007BE 8C005042 ORI V0, V0, -29696
-BFD007C0 8C00 BEQZ S0, 0xBFD007C2
-BFD007C2 BFD241A3 LUI V1, 0xBFD2
-BFD007C4 3063BFD2 LDC1 F30, 12387(S2)
-BFD007C6 81343063 ADDIU V1, V1, -32460
-BFD007CA 69B5 LW V1, 20(V1)
-BFD007CC 25B1 SRL V1, V1, 8
-BFD007CE 2DBD ANDI V1, V1, 0xFF
-BFD007D0 89A0 SB V1, 0(V0)
-BFD007D2 A00041A2 LUI V0, 0xA000
-BFD007D6 8C005042 ORI V0, V0, -29696
-BFD007D8 8C00 BEQZ S0, 0xBFD007DA
-BFD007DA BFD241A3 LUI V1, 0xBFD2
-BFD007DC 3063BFD2 LDC1 F30, 12387(S2)
-BFD007DE 81343063 ADDIU V1, V1, -32460
-BFD007E2 69B5 LW V1, 20(V1)
-BFD007E4 80400063 SRL V1, V1, 16
-BFD007E8 2DBD ANDI V1, V1, 0xFF
-BFD007EA 89A0 SB V1, 0(V0)
-BFD007EC A00041A2 LUI V0, 0xA000
-BFD007F0 8C005042 ORI V0, V0, -29696
-BFD007F2 8C00 BEQZ S0, 0xBFD007F4
-BFD007F4 BFD241A3 LUI V1, 0xBFD2
-BFD007F6 3063BFD2 LDC1 F30, 12387(S2)
-BFD007F8 81343063 ADDIU V1, V1, -32460
-BFD007FC 69B5 LW V1, 20(V1)
-BFD007FE C0400063 SRL V1, V1, 24
-BFD00802 2DBD ANDI V1, V1, 0xFF
-BFD00804 89A0 SB V1, 0(V0)
+BFD0077E A00041A2 LUI V0, 0xA000\r
+BFD00782 8C005042 ORI V0, V0, -29696\r
+BFD00784 8C00 BEQZ S0, 0xBFD00786\r
+BFD00786 FFFD3060 ADDIU V1, ZERO, -3\r
+BFD00788 89A0FFFD LW RA, -30304(SP)\r
+BFD0078A 89A0 SB V1, 0(V0)\r
+BFD0078C A00041A2 LUI V0, 0xA000\r
+BFD00790 8C005042 ORI V0, V0, -29696\r
+BFD00792 8C00 BEQZ S0, 0xBFD00794\r
+BFD00794 EDDE LI V1, 94\r
+BFD00796 89A0 SB V1, 0(V0)\r
+BFD00798 A00041A2 LUI V0, 0xA000\r
+BFD0079C 8C005042 ORI V0, V0, -29696\r
+BFD0079E 8C00 BEQZ S0, 0xBFD007A0\r
+BFD007A0 ED82 LI V1, 2\r
+BFD007A2 89A0 SB V1, 0(V0)\r
+BFD007A4 A00041A2 LUI V0, 0xA000\r
+BFD007A8 8C005042 ORI V0, V0, -29696\r
+BFD007AA 8C00 BEQZ S0, 0xBFD007AC\r
+BFD007AC BFD241A3 LUI V1, 0xBFD2\r
+BFD007AE 3063BFD2 LDC1 F30, 12387(S2)\r
+BFD007B0 81343063 ADDIU V1, V1, -32460\r
+BFD007B4 69B5 LW V1, 20(V1)\r
+BFD007B6 2DBD ANDI V1, V1, 0xFF\r
+BFD007B8 89A0 SB V1, 0(V0)\r
+BFD007BA A00041A2 LUI V0, 0xA000\r
+BFD007BE 8C005042 ORI V0, V0, -29696\r
+BFD007C0 8C00 BEQZ S0, 0xBFD007C2\r
+BFD007C2 BFD241A3 LUI V1, 0xBFD2\r
+BFD007C4 3063BFD2 LDC1 F30, 12387(S2)\r
+BFD007C6 81343063 ADDIU V1, V1, -32460\r
+BFD007CA 69B5 LW V1, 20(V1)\r
+BFD007CC 25B1 SRL V1, V1, 8\r
+BFD007CE 2DBD ANDI V1, V1, 0xFF\r
+BFD007D0 89A0 SB V1, 0(V0)\r
+BFD007D2 A00041A2 LUI V0, 0xA000\r
+BFD007D6 8C005042 ORI V0, V0, -29696\r
+BFD007D8 8C00 BEQZ S0, 0xBFD007DA\r
+BFD007DA BFD241A3 LUI V1, 0xBFD2\r
+BFD007DC 3063BFD2 LDC1 F30, 12387(S2)\r
+BFD007DE 81343063 ADDIU V1, V1, -32460\r
+BFD007E2 69B5 LW V1, 20(V1)\r
+BFD007E4 80400063 SRL V1, V1, 16\r
+BFD007E8 2DBD ANDI V1, V1, 0xFF\r
+BFD007EA 89A0 SB V1, 0(V0)\r
+BFD007EC A00041A2 LUI V0, 0xA000\r
+BFD007F0 8C005042 ORI V0, V0, -29696\r
+BFD007F2 8C00 BEQZ S0, 0xBFD007F4\r
+BFD007F4 BFD241A3 LUI V1, 0xBFD2\r
+BFD007F6 3063BFD2 LDC1 F30, 12387(S2)\r
+BFD007F8 81343063 ADDIU V1, V1, -32460\r
+BFD007FC 69B5 LW V1, 20(V1)\r
+BFD007FE C0400063 SRL V1, V1, 24\r
+BFD00802 2DBD ANDI V1, V1, 0xFF\r
+BFD00804 89A0 SB V1, 0(V0)\r
85: TRACE11(607, AP3GENEXCEPT, 0, "CP0 NEPC = 0x%08x",gexc_cap.cp0_nepc);\r
-BFD00806 A00041A2 LUI V0, 0xA000
-BFD0080A 8C005042 ORI V0, V0, -29696
-BFD0080C 8C00 BEQZ S0, 0xBFD0080E
-BFD0080E FFFD3060 ADDIU V1, ZERO, -3
-BFD00810 89A0FFFD LW RA, -30304(SP)
-BFD00812 89A0 SB V1, 0(V0)
-BFD00814 A00041A2 LUI V0, 0xA000
-BFD00818 8C005042 ORI V0, V0, -29696
-BFD0081A 8C00 BEQZ S0, 0xBFD0081C
-BFD0081C EDDF LI V1, 95
-BFD0081E 89A0 SB V1, 0(V0)
-BFD00820 A00041A2 LUI V0, 0xA000
-BFD00824 8C005042 ORI V0, V0, -29696
-BFD00826 8C00 BEQZ S0, 0xBFD00828
-BFD00828 ED82 LI V1, 2
-BFD0082A 89A0 SB V1, 0(V0)
-BFD0082C A00041A2 LUI V0, 0xA000
-BFD00830 8C005042 ORI V0, V0, -29696
-BFD00832 8C00 BEQZ S0, 0xBFD00834
-BFD00834 BFD241A3 LUI V1, 0xBFD2
-BFD00836 3063BFD2 LDC1 F30, 12387(S2)
-BFD00838 81343063 ADDIU V1, V1, -32460
-BFD0083C 69B6 LW V1, 24(V1)
-BFD0083E 2DBD ANDI V1, V1, 0xFF
-BFD00840 89A0 SB V1, 0(V0)
-BFD00842 A00041A2 LUI V0, 0xA000
-BFD00846 8C005042 ORI V0, V0, -29696
-BFD00848 8C00 BEQZ S0, 0xBFD0084A
-BFD0084A BFD241A3 LUI V1, 0xBFD2
-BFD0084C 3063BFD2 LDC1 F30, 12387(S2)
-BFD0084E 81343063 ADDIU V1, V1, -32460
-BFD00852 69B6 LW V1, 24(V1)
-BFD00854 25B1 SRL V1, V1, 8
-BFD00856 2DBD ANDI V1, V1, 0xFF
-BFD00858 89A0 SB V1, 0(V0)
-BFD0085A A00041A2 LUI V0, 0xA000
-BFD0085E 8C005042 ORI V0, V0, -29696
-BFD00860 8C00 BEQZ S0, 0xBFD00862
-BFD00862 BFD241A3 LUI V1, 0xBFD2
-BFD00864 3063BFD2 LDC1 F30, 12387(S2)
-BFD00866 81343063 ADDIU V1, V1, -32460
-BFD0086A 69B6 LW V1, 24(V1)
-BFD0086C 80400063 SRL V1, V1, 16
-BFD00870 2DBD ANDI V1, V1, 0xFF
-BFD00872 89A0 SB V1, 0(V0)
-BFD00874 A00041A2 LUI V0, 0xA000
-BFD00878 8C005042 ORI V0, V0, -29696
-BFD0087A 8C00 BEQZ S0, 0xBFD0087C
-BFD0087C BFD241A3 LUI V1, 0xBFD2
-BFD0087E 3063BFD2 LDC1 F30, 12387(S2)
-BFD00880 81343063 ADDIU V1, V1, -32460
-BFD00884 69B6 LW V1, 24(V1)
-BFD00886 C0400063 SRL V1, V1, 24
-BFD0088A 2DBD ANDI V1, V1, 0xFF
-BFD0088C 89A0 SB V1, 0(V0)
+BFD00806 A00041A2 LUI V0, 0xA000\r
+BFD0080A 8C005042 ORI V0, V0, -29696\r
+BFD0080C 8C00 BEQZ S0, 0xBFD0080E\r
+BFD0080E FFFD3060 ADDIU V1, ZERO, -3\r
+BFD00810 89A0FFFD LW RA, -30304(SP)\r
+BFD00812 89A0 SB V1, 0(V0)\r
+BFD00814 A00041A2 LUI V0, 0xA000\r
+BFD00818 8C005042 ORI V0, V0, -29696\r
+BFD0081A 8C00 BEQZ S0, 0xBFD0081C\r
+BFD0081C EDDF LI V1, 95\r
+BFD0081E 89A0 SB V1, 0(V0)\r
+BFD00820 A00041A2 LUI V0, 0xA000\r
+BFD00824 8C005042 ORI V0, V0, -29696\r
+BFD00826 8C00 BEQZ S0, 0xBFD00828\r
+BFD00828 ED82 LI V1, 2\r
+BFD0082A 89A0 SB V1, 0(V0)\r
+BFD0082C A00041A2 LUI V0, 0xA000\r
+BFD00830 8C005042 ORI V0, V0, -29696\r
+BFD00832 8C00 BEQZ S0, 0xBFD00834\r
+BFD00834 BFD241A3 LUI V1, 0xBFD2\r
+BFD00836 3063BFD2 LDC1 F30, 12387(S2)\r
+BFD00838 81343063 ADDIU V1, V1, -32460\r
+BFD0083C 69B6 LW V1, 24(V1)\r
+BFD0083E 2DBD ANDI V1, V1, 0xFF\r
+BFD00840 89A0 SB V1, 0(V0)\r
+BFD00842 A00041A2 LUI V0, 0xA000\r
+BFD00846 8C005042 ORI V0, V0, -29696\r
+BFD00848 8C00 BEQZ S0, 0xBFD0084A\r
+BFD0084A BFD241A3 LUI V1, 0xBFD2\r
+BFD0084C 3063BFD2 LDC1 F30, 12387(S2)\r
+BFD0084E 81343063 ADDIU V1, V1, -32460\r
+BFD00852 69B6 LW V1, 24(V1)\r
+BFD00854 25B1 SRL V1, V1, 8\r
+BFD00856 2DBD ANDI V1, V1, 0xFF\r
+BFD00858 89A0 SB V1, 0(V0)\r
+BFD0085A A00041A2 LUI V0, 0xA000\r
+BFD0085E 8C005042 ORI V0, V0, -29696\r
+BFD00860 8C00 BEQZ S0, 0xBFD00862\r
+BFD00862 BFD241A3 LUI V1, 0xBFD2\r
+BFD00864 3063BFD2 LDC1 F30, 12387(S2)\r
+BFD00866 81343063 ADDIU V1, V1, -32460\r
+BFD0086A 69B6 LW V1, 24(V1)\r
+BFD0086C 80400063 SRL V1, V1, 16\r
+BFD00870 2DBD ANDI V1, V1, 0xFF\r
+BFD00872 89A0 SB V1, 0(V0)\r
+BFD00874 A00041A2 LUI V0, 0xA000\r
+BFD00878 8C005042 ORI V0, V0, -29696\r
+BFD0087A 8C00 BEQZ S0, 0xBFD0087C\r
+BFD0087C BFD241A3 LUI V1, 0xBFD2\r
+BFD0087E 3063BFD2 LDC1 F30, 12387(S2)\r
+BFD00880 81343063 ADDIU V1, V1, -32460\r
+BFD00884 69B6 LW V1, 24(V1)\r
+BFD00886 C0400063 SRL V1, V1, 24\r
+BFD0088A 2DBD ANDI V1, V1, 0xFF\r
+BFD0088C 89A0 SB V1, 0(V0)\r
86: TRACE11(608, AP3GENEXCEPT, 0, "CP0 BADVADDR = 0x%08x",gexc_cap.cp0_badvaddr);\r
-BFD0088E A00041A2 LUI V0, 0xA000
-BFD00892 8C005042 ORI V0, V0, -29696
-BFD00894 8C00 BEQZ S0, 0xBFD00896
-BFD00896 FFFD3060 ADDIU V1, ZERO, -3
-BFD00898 89A0FFFD LW RA, -30304(SP)
-BFD0089A 89A0 SB V1, 0(V0)
-BFD0089C A00041A2 LUI V0, 0xA000
-BFD008A0 8C005042 ORI V0, V0, -29696
-BFD008A2 8C00 BEQZ S0, 0xBFD008A4
-BFD008A4 EDE0 LI V1, 96
-BFD008A6 89A0 SB V1, 0(V0)
-BFD008A8 A00041A2 LUI V0, 0xA000
-BFD008AC 8C005042 ORI V0, V0, -29696
-BFD008AE 8C00 BEQZ S0, 0xBFD008B0
-BFD008B0 ED82 LI V1, 2
-BFD008B2 89A0 SB V1, 0(V0)
-BFD008B4 A00041A2 LUI V0, 0xA000
-BFD008B8 8C005042 ORI V0, V0, -29696
-BFD008BA 8C00 BEQZ S0, 0xBFD008BC
-BFD008BC BFD241A3 LUI V1, 0xBFD2
-BFD008BE 3063BFD2 LDC1 F30, 12387(S2)
-BFD008C0 81343063 ADDIU V1, V1, -32460
-BFD008C4 69B7 LW V1, 28(V1)
-BFD008C6 2DBD ANDI V1, V1, 0xFF
-BFD008C8 89A0 SB V1, 0(V0)
-BFD008CA A00041A2 LUI V0, 0xA000
-BFD008CE 8C005042 ORI V0, V0, -29696
-BFD008D0 8C00 BEQZ S0, 0xBFD008D2
-BFD008D2 BFD241A3 LUI V1, 0xBFD2
-BFD008D4 3063BFD2 LDC1 F30, 12387(S2)
-BFD008D6 81343063 ADDIU V1, V1, -32460
-BFD008DA 69B7 LW V1, 28(V1)
-BFD008DC 25B1 SRL V1, V1, 8
-BFD008DE 2DBD ANDI V1, V1, 0xFF
-BFD008E0 89A0 SB V1, 0(V0)
-BFD008E2 A00041A2 LUI V0, 0xA000
-BFD008E6 8C005042 ORI V0, V0, -29696
-BFD008E8 8C00 BEQZ S0, 0xBFD008EA
-BFD008EA BFD241A3 LUI V1, 0xBFD2
-BFD008EC 3063BFD2 LDC1 F30, 12387(S2)
-BFD008EE 81343063 ADDIU V1, V1, -32460
-BFD008F2 69B7 LW V1, 28(V1)
-BFD008F4 80400063 SRL V1, V1, 16
-BFD008F8 2DBD ANDI V1, V1, 0xFF
-BFD008FA 89A0 SB V1, 0(V0)
-BFD008FC A00041A2 LUI V0, 0xA000
-BFD00900 8C005042 ORI V0, V0, -29696
-BFD00902 8C00 BEQZ S0, 0xBFD00904
-BFD00904 BFD241A3 LUI V1, 0xBFD2
-BFD00906 3063BFD2 LDC1 F30, 12387(S2)
-BFD00908 81343063 ADDIU V1, V1, -32460
-BFD0090C 69B7 LW V1, 28(V1)
-BFD0090E C0400063 SRL V1, V1, 24
-BFD00912 2DBD ANDI V1, V1, 0xFF
-BFD00914 89A0 SB V1, 0(V0)
+BFD0088E A00041A2 LUI V0, 0xA000\r
+BFD00892 8C005042 ORI V0, V0, -29696\r
+BFD00894 8C00 BEQZ S0, 0xBFD00896\r
+BFD00896 FFFD3060 ADDIU V1, ZERO, -3\r
+BFD00898 89A0FFFD LW RA, -30304(SP)\r
+BFD0089A 89A0 SB V1, 0(V0)\r
+BFD0089C A00041A2 LUI V0, 0xA000\r
+BFD008A0 8C005042 ORI V0, V0, -29696\r
+BFD008A2 8C00 BEQZ S0, 0xBFD008A4\r
+BFD008A4 EDE0 LI V1, 96\r
+BFD008A6 89A0 SB V1, 0(V0)\r
+BFD008A8 A00041A2 LUI V0, 0xA000\r
+BFD008AC 8C005042 ORI V0, V0, -29696\r
+BFD008AE 8C00 BEQZ S0, 0xBFD008B0\r
+BFD008B0 ED82 LI V1, 2\r
+BFD008B2 89A0 SB V1, 0(V0)\r
+BFD008B4 A00041A2 LUI V0, 0xA000\r
+BFD008B8 8C005042 ORI V0, V0, -29696\r
+BFD008BA 8C00 BEQZ S0, 0xBFD008BC\r
+BFD008BC BFD241A3 LUI V1, 0xBFD2\r
+BFD008BE 3063BFD2 LDC1 F30, 12387(S2)\r
+BFD008C0 81343063 ADDIU V1, V1, -32460\r
+BFD008C4 69B7 LW V1, 28(V1)\r
+BFD008C6 2DBD ANDI V1, V1, 0xFF\r
+BFD008C8 89A0 SB V1, 0(V0)\r
+BFD008CA A00041A2 LUI V0, 0xA000\r
+BFD008CE 8C005042 ORI V0, V0, -29696\r
+BFD008D0 8C00 BEQZ S0, 0xBFD008D2\r
+BFD008D2 BFD241A3 LUI V1, 0xBFD2\r
+BFD008D4 3063BFD2 LDC1 F30, 12387(S2)\r
+BFD008D6 81343063 ADDIU V1, V1, -32460\r
+BFD008DA 69B7 LW V1, 28(V1)\r
+BFD008DC 25B1 SRL V1, V1, 8\r
+BFD008DE 2DBD ANDI V1, V1, 0xFF\r
+BFD008E0 89A0 SB V1, 0(V0)\r
+BFD008E2 A00041A2 LUI V0, 0xA000\r
+BFD008E6 8C005042 ORI V0, V0, -29696\r
+BFD008E8 8C00 BEQZ S0, 0xBFD008EA\r
+BFD008EA BFD241A3 LUI V1, 0xBFD2\r
+BFD008EC 3063BFD2 LDC1 F30, 12387(S2)\r
+BFD008EE 81343063 ADDIU V1, V1, -32460\r
+BFD008F2 69B7 LW V1, 28(V1)\r
+BFD008F4 80400063 SRL V1, V1, 16\r
+BFD008F8 2DBD ANDI V1, V1, 0xFF\r
+BFD008FA 89A0 SB V1, 0(V0)\r
+BFD008FC A00041A2 LUI V0, 0xA000\r
+BFD00900 8C005042 ORI V0, V0, -29696\r
+BFD00902 8C00 BEQZ S0, 0xBFD00904\r
+BFD00904 BFD241A3 LUI V1, 0xBFD2\r
+BFD00906 3063BFD2 LDC1 F30, 12387(S2)\r
+BFD00908 81343063 ADDIU V1, V1, -32460\r
+BFD0090C 69B7 LW V1, 28(V1)\r
+BFD0090E C0400063 SRL V1, V1, 24\r
+BFD00912 2DBD ANDI V1, V1, 0xFF\r
+BFD00914 89A0 SB V1, 0(V0)\r
87: \r
88: for (;;) {\r
89: __asm__ __volatile ("%(ssnop%)" : :);\r
-BFD00916 08000000 SSNOP
-BFD00918 0800 LBU S0, 0(S0)
+BFD00916 08000000 SSNOP\r
+BFD00918 0800 LBU S0, 0(S0)\r
90: } \r
-BFD0091A CFFD B 0xBFD00916
-BFD0091C 0C00 NOP
+BFD0091A CFFD B 0xBFD00916\r
+BFD0091C 0C00 NOP\r
91: }\r
92: \r
93: \r
95: /** @}\r
96: */\r
97: \r
---- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/main.c -------------------------
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/main.c -------------------------\r
1: #warning configTIMERS_DISAGGREGATED_ISRS and configCPU_DISAGGREGATED_ISRS need documenting.\r
2: \r
3: /*\r
10: \r
11: FreeRTOS is free software; you can redistribute it and/or modify it under\r
12: the terms of the GNU General Public License (version 2) as published by the\r
-13: Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+13: Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
14: \r
15: ***************************************************************************\r
16: >>! NOTE: The modification to the GPL is included to allow you to !<<\r
167: \r
168: int main( void )\r
169: {\r
-BFD096C0 4FF1 ADDIU SP, SP, -32
-BFD096C2 CBE7 SW RA, 28(SP)
-BFD096C4 CBC6 SW S8, 24(SP)
-BFD096C6 0FDD MOVE S8, SP
+BFD096C0 4FF1 ADDIU SP, SP, -32\r
+BFD096C2 CBE7 SW RA, 28(SP)\r
+BFD096C4 CBC6 SW S8, 24(SP)\r
+BFD096C6 0FDD MOVE S8, SP\r
170: TimerHandle_t xTimer;\r
171: \r
172: /* Perform any hardware initialisation necessary. */\r
173: //prvSetupHardware();\r
174: \r
175: __asm volatile( "di" );\r
-BFD096C8 477C0000 DI ZERO
+BFD096C8 477C0000 DI ZERO\r
176: \r
177: \r
178: {\r
179: volatile uint32_t ulx = 0;\r
-BFD096CC 0010F81E SW ZERO, 16(S8)
+BFD096CC 0010F81E SW ZERO, 16(S8)\r
180: \r
181: for( ;; )\r
182: {\r
183: for( ulx = 0; ulx < 0x1fff; ulx++ )\r
-BFD096D0 CC0A B 0xBFD096E6
-BFD096D2 0010F81E SW ZERO, 16(S8)
-BFD096D4 0C000010 SLL ZERO, S0, 1
-BFD096DC 0010FC5E LW V0, 16(S8)
-BFD096E0 6D20 ADDIU V0, V0, 1
-BFD096E2 0010F85E SW V0, 16(S8)
-BFD096E6 0010FC5E LW V0, 16(S8)
-BFD096EA 1FFFB042 SLTIU V0, V0, 8191
-BFD096EC 40A21FFF LB RA, 16546(RA)
-BFD096EE FFF240A2 BNEZC V0, 0xBFD096D6
-BFD096F0 77E8FFF2 LW RA, 30696(S2)
+BFD096D0 CC0A B 0xBFD096E6\r
+BFD096D2 0010F81E SW ZERO, 16(S8)\r
+BFD096D4 0C000010 SLL ZERO, S0, 1\r
+BFD096DC 0010FC5E LW V0, 16(S8)\r
+BFD096E0 6D20 ADDIU V0, V0, 1\r
+BFD096E2 0010F85E SW V0, 16(S8)\r
+BFD096E6 0010FC5E LW V0, 16(S8)\r
+BFD096EA 1FFFB042 SLTIU V0, V0, 8191\r
+BFD096EC 40A21FFF LB RA, 16546(RA)\r
+BFD096EE FFF240A2 BNEZC V0, 0xBFD096D6\r
+BFD096F0 77E8FFF2 LW RA, 30696(S2)\r
184: {\r
185: __asm volatile( "NOP" );\r
-BFD096D6 0C00 NOP
+BFD096D6 0C00 NOP\r
186: __asm volatile( "NOP" );\r
-BFD096D8 0C00 NOP
+BFD096D8 0C00 NOP\r
187: __asm volatile( "NOP" ); \r
-BFD096DA 0C00 NOP
+BFD096DA 0C00 NOP\r
188: }\r
189: \r
190: led_out_toggle( 0 );\r
-BFD096F2 42D477E8 JALS led_out_toggle
-BFD096F6 0C80 MOVE A0, ZERO
+BFD096F2 42D477E8 JALS led_out_toggle\r
+BFD096F6 0C80 MOVE A0, ZERO\r
191: }\r
-BFD096F8 CFEB B 0xBFD096D0
-BFD096FA 0C00 NOP
+BFD096F8 CFEB B 0xBFD096D0\r
+BFD096FA 0C00 NOP\r
192: }\r
193: \r
194: \r
239: \r
240: static void prvQueueSendTask( void *pvParameters )\r
241: {\r
-BFD07E34 4FF1 ADDIU SP, SP, -32
-BFD07E36 CBE7 SW RA, 28(SP)
-BFD07E38 CBC6 SW S8, 24(SP)
-BFD07E3A 0FDD MOVE S8, SP
-BFD07E3C 0020F89E SW A0, 32(S8)
+BFD07E34 4FF1 ADDIU SP, SP, -32\r
+BFD07E36 CBE7 SW RA, 28(SP)\r
+BFD07E38 CBC6 SW S8, 24(SP)\r
+BFD07E3A 0FDD MOVE S8, SP\r
+BFD07E3C 0020F89E SW A0, 32(S8)\r
242: TickType_t xNextWakeTime;\r
243: const unsigned long ulValueToSend = 100UL;\r
-BFD07E40 ED64 LI V0, 100
-BFD07E42 0014F85E SW V0, 20(S8)
+BFD07E40 ED64 LI V0, 100\r
+BFD07E42 0014F85E SW V0, 20(S8)\r
244: \r
245: /* Remove compiler warnigns in the case that configASSERT() is not dfined. */\r
246: ( void ) pvParameters;\r
247: \r
248: /* Check the task parameter is as expected. */\r
249: configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER );\r
-BFD07E46 0020FC7E LW V1, 32(S8)
-BFD07E48 30400020 SRL AT, ZERO, 6
-BFD07E4A 11113040 ADDIU V0, ZERO, 4369
-BFD07E4C 94431111 ADDI T0, S1, -27581
-BFD07E4E 000A9443 BEQ V1, V0, 0xBFD07E66
-BFD07E50 0C00000A SLL ZERO, T2, 1
-BFD07E52 0C00 NOP
-BFD07E54 BFD141A2 LUI V0, 0xBFD1
-BFD07E56 3082BFD1 LDC1 F30, 12418(S1)
-BFD07E58 9EF43082 ADDIU A0, V0, -24844
-BFD07E5A 30A09EF4 LWC1 F23, 12448(S4)
-BFD07E5C 00F930A0 ADDIU A1, ZERO, 249
-BFD07E60 4B7E77E8 JALS vAssertCalled
-BFD07E62 4B7E LW K1, 120(SP)
-BFD07E64 0C00 NOP
+BFD07E46 0020FC7E LW V1, 32(S8)\r
+BFD07E48 30400020 SRL AT, ZERO, 6\r
+BFD07E4A 11113040 ADDIU V0, ZERO, 4369\r
+BFD07E4C 94431111 ADDI T0, S1, -27581\r
+BFD07E4E 000A9443 BEQ V1, V0, 0xBFD07E66\r
+BFD07E50 0C00000A SLL ZERO, T2, 1\r
+BFD07E52 0C00 NOP\r
+BFD07E54 BFD141A2 LUI V0, 0xBFD1\r
+BFD07E56 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD07E58 9EF43082 ADDIU A0, V0, -24844\r
+BFD07E5A 30A09EF4 LWC1 F23, 12448(S4)\r
+BFD07E5C 00F930A0 ADDIU A1, ZERO, 249\r
+BFD07E60 4B7E77E8 JALS vAssertCalled\r
+BFD07E62 4B7E LW K1, 120(SP)\r
+BFD07E64 0C00 NOP\r
250: \r
251: /* Initialise xNextWakeTime - this only needs to be done once. */\r
252: xNextWakeTime = xTaskGetTickCount();\r
-BFD07E66 4CCA77E8 JALS xTaskGetTickCount
-BFD07E68 4CCA ADDIU A2, A2, 5
-BFD07E6A 0C00 NOP
-BFD07E6C 0010F85E SW V0, 16(S8)
+BFD07E66 4CCA77E8 JALS xTaskGetTickCount\r
+BFD07E68 4CCA ADDIU A2, A2, 5\r
+BFD07E6A 0C00 NOP\r
+BFD07E6C 0010F85E SW V0, 16(S8)\r
253: \r
254: for( ;; )\r
255: {\r
258: to ms. While in the Blocked state this task will not consume any CPU\r
259: time. */\r
260: vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
-BFD07E70 0010305E ADDIU V0, S8, 16
-BFD07E74 0C82 MOVE A0, V0
-BFD07E76 00C830A0 ADDIU A1, ZERO, 200
-BFD07E7A 000477E8 JALS vTaskDelayUntil
-BFD07E7C 0C000004 SLL ZERO, A0, 1
-BFD07E7E 0C00 NOP
+BFD07E70 0010305E ADDIU V0, S8, 16\r
+BFD07E74 0C82 MOVE A0, V0\r
+BFD07E76 00C830A0 ADDIU A1, ZERO, 200\r
+BFD07E7A 000477E8 JALS vTaskDelayUntil\r
+BFD07E7C 0C000004 SLL ZERO, A0, 1\r
+BFD07E7E 0C00 NOP\r
261: \r
262: /* Send to the queue - causing the queue receive task to unblock and\r
263: toggle the LED. 0 is used as the block time so the sending operation\r
264: will not block - it shouldn't need to block as the queue should always\r
265: be empty at this point in the code. */\r
266: xQueueSend( xQueue, &ulValueToSend, 0U );\r
-BFD07E80 8070FC7C LW V1, -32656(GP)
-BFD07E84 0014305E ADDIU V0, S8, 20
-BFD07E88 0C83 MOVE A0, V1
-BFD07E8A 0CA2 MOVE A1, V0
-BFD07E8C 0CC0 MOVE A2, ZERO
-BFD07E8E 0CE0 MOVE A3, ZERO
-BFD07E90 06A277E8 JALS xQueueGenericSend
-BFD07E92 06A2 ADDU A1, S1, V0
-BFD07E94 0C00 NOP
+BFD07E80 8070FC7C LW V1, -32656(GP)\r
+BFD07E84 0014305E ADDIU V0, S8, 20\r
+BFD07E88 0C83 MOVE A0, V1\r
+BFD07E8A 0CA2 MOVE A1, V0\r
+BFD07E8C 0CC0 MOVE A2, ZERO\r
+BFD07E8E 0CE0 MOVE A3, ZERO\r
+BFD07E90 06A277E8 JALS xQueueGenericSend\r
+BFD07E92 06A2 ADDU A1, S1, V0\r
+BFD07E94 0C00 NOP\r
267: }\r
-BFD07E96 CFEC B 0xBFD07E70
-BFD07E98 0C00 NOP
+BFD07E96 CFEC B 0xBFD07E70\r
+BFD07E98 0C00 NOP\r
268: }\r
269: /*-----------------------------------------------------------*/\r
270: \r
271: static void prvQueueReceiveTask( void *pvParameters )\r
272: {\r
-BFD08090 4FF1 ADDIU SP, SP, -32
-BFD08092 CBE7 SW RA, 28(SP)
-BFD08094 CBC6 SW S8, 24(SP)
-BFD08096 0FDD MOVE S8, SP
-BFD08098 0020F89E SW A0, 32(S8)
+BFD08090 4FF1 ADDIU SP, SP, -32\r
+BFD08092 CBE7 SW RA, 28(SP)\r
+BFD08094 CBC6 SW S8, 24(SP)\r
+BFD08096 0FDD MOVE S8, SP\r
+BFD08098 0020F89E SW A0, 32(S8)\r
273: unsigned long ulReceivedValue;\r
274: \r
275: /* Remove compiler warnings in the case where configASSERT() is not defined. */\r
277: \r
278: /* Check the task parameter is as expected. */\r
279: configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER );\r
-BFD0809C 0020FC7E LW V1, 32(S8)
-BFD080A0 ED22 LI V0, 34
-BFD080A2 000D9443 BEQ V1, V0, 0xBFD080C0
-BFD080A4 0C00000D SLL ZERO, T5, 1
-BFD080A6 0C00 NOP
-BFD080A8 BFD141A2 LUI V0, 0xBFD1
-BFD080AA 3082BFD1 LDC1 F30, 12418(S1)
-BFD080AC 9EF43082 ADDIU A0, V0, -24844
-BFD080AE 30A09EF4 LWC1 F23, 12448(S4)
-BFD080B0 011730A0 ADDIU A1, ZERO, 279
-BFD080B4 4B7E77E8 JALS vAssertCalled
-BFD080B6 4B7E LW K1, 120(SP)
-BFD080B8 0C00 NOP
-BFD080BA CC02 B 0xBFD080C0
-BFD080BC 0C00 NOP
+BFD0809C 0020FC7E LW V1, 32(S8)\r
+BFD080A0 ED22 LI V0, 34\r
+BFD080A2 000D9443 BEQ V1, V0, 0xBFD080C0\r
+BFD080A4 0C00000D SLL ZERO, T5, 1\r
+BFD080A6 0C00 NOP\r
+BFD080A8 BFD141A2 LUI V0, 0xBFD1\r
+BFD080AA 3082BFD1 LDC1 F30, 12418(S1)\r
+BFD080AC 9EF43082 ADDIU A0, V0, -24844\r
+BFD080AE 30A09EF4 LWC1 F23, 12448(S4)\r
+BFD080B0 011730A0 ADDIU A1, ZERO, 279\r
+BFD080B4 4B7E77E8 JALS vAssertCalled\r
+BFD080B6 4B7E LW K1, 120(SP)\r
+BFD080B8 0C00 NOP\r
+BFD080BA CC02 B 0xBFD080C0\r
+BFD080BC 0C00 NOP\r
280: \r
281: for( ;; )\r
282: {\r
284: indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
285: FreeRTOSConfig.h. */\r
286: xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
-BFD080C0 8070FC5C LW V0, -32656(GP)
-BFD080C4 0C82 MOVE A0, V0
-BFD080C6 0010305E ADDIU V0, S8, 16
-BFD080CA 0CA2 MOVE A1, V0
-BFD080CC EF7F LI A2, -1
-BFD080CE 0CE0 MOVE A3, ZERO
-BFD080D0 081E77E8 JALS xQueueGenericReceive
-BFD080D2 081E LBU S0, 14(S1)
-BFD080D4 0C00 NOP
+BFD080C0 8070FC5C LW V0, -32656(GP)\r
+BFD080C4 0C82 MOVE A0, V0\r
+BFD080C6 0010305E ADDIU V0, S8, 16\r
+BFD080CA 0CA2 MOVE A1, V0\r
+BFD080CC EF7F LI A2, -1\r
+BFD080CE 0CE0 MOVE A3, ZERO\r
+BFD080D0 081E77E8 JALS xQueueGenericReceive\r
+BFD080D2 081E LBU S0, 14(S1)\r
+BFD080D4 0C00 NOP\r
287: \r
288: /* To get here something must have been received from the queue, but\r
289: is it the expected value? If it is, toggle the LED. */\r
290: if( ulReceivedValue == 100UL )\r
-BFD080D6 0010FC7E LW V1, 16(S8)
-BFD080DA ED64 LI V0, 100
-BFD080DC FFEFB443 BNE V1, V0, 0xBFD080BE
-BFD080DE 0C00FFEF LW RA, 3072(T7)
-BFD080E0 0C00 NOP
+BFD080D6 0010FC7E LW V1, 16(S8)\r
+BFD080DA ED64 LI V0, 100\r
+BFD080DC FFEFB443 BNE V1, V0, 0xBFD080BE\r
+BFD080DE 0C00FFEF LW RA, 3072(T7)\r
+BFD080E0 0C00 NOP\r
291: {\r
292: prvToggleLED( mainTASKS_LED );\r
-BFD080E2 0C80 MOVE A0, ZERO
-BFD080E4 4C3C77E8 JALS prvToggleLED
-BFD080E6 4C3C ADDIU AT, AT, -2
-BFD080E8 0C00 NOP
+BFD080E2 0C80 MOVE A0, ZERO\r
+BFD080E4 4C3C77E8 JALS prvToggleLED\r
+BFD080E6 4C3C ADDIU AT, AT, -2\r
+BFD080E8 0C00 NOP\r
293: ulReceivedValue = 0U;\r
-BFD080EA 0010F81E SW ZERO, 16(S8)
+BFD080EA 0010F81E SW ZERO, 16(S8)\r
294: }\r
295: }\r
-BFD080BE 0C00 NOP
-BFD080EE CFE8 B 0xBFD080C0
-BFD080F0 0C00 NOP
+BFD080BE 0C00 NOP\r
+BFD080EE CFE8 B 0xBFD080C0\r
+BFD080F0 0C00 NOP\r
296: }\r
297: /*-----------------------------------------------------------*/\r
298: \r
299: static void prvBlinkyTimerCallback( TimerHandle_t xTimer )\r
300: {\r
-BFD09DAC 4FF5 ADDIU SP, SP, -24
-BFD09DAE CBE5 SW RA, 20(SP)
-BFD09DB0 CBC4 SW S8, 16(SP)
-BFD09DB2 0FDD MOVE S8, SP
-BFD09DB4 0018F89E SW A0, 24(S8)
+BFD09DAC 4FF5 ADDIU SP, SP, -24\r
+BFD09DAE CBE5 SW RA, 20(SP)\r
+BFD09DB0 CBC4 SW S8, 16(SP)\r
+BFD09DB2 0FDD MOVE S8, SP\r
+BFD09DB4 0018F89E SW A0, 24(S8)\r
301: /* Avoid compiler warnings. */\r
302: ( void ) xTimer;\r
303: \r
305: function does is toggle the LED. LED mainTIMER_LED should therefore toggle\r
306: with the period set by mainBLINKY_TIMER_PERIOD. */\r
307: prvToggleLED( mainTIMER_LED );\r
-BFD09DB8 EE01 LI A0, 1
-BFD09DBA 4C3C77E8 JALS prvToggleLED
-BFD09DBC 4C3C ADDIU AT, AT, -2
-BFD09DBE 0C00 NOP
+BFD09DB8 EE01 LI A0, 1\r
+BFD09DBA 4C3C77E8 JALS prvToggleLED\r
+BFD09DBC 4C3C ADDIU AT, AT, -2\r
+BFD09DBE 0C00 NOP\r
308: }\r
-BFD09DC0 0FBE MOVE SP, S8
-BFD09DC2 4BE5 LW RA, 20(SP)
-BFD09DC4 4BC4 LW S8, 16(SP)
-BFD09DC6 4C0D ADDIU SP, SP, 24
-BFD09DC8 459F JR16 RA
-BFD09DCA 0C00 NOP
+BFD09DC0 0FBE MOVE SP, S8\r
+BFD09DC2 4BE5 LW RA, 20(SP)\r
+BFD09DC4 4BC4 LW S8, 16(SP)\r
+BFD09DC6 4C0D ADDIU SP, SP, 24\r
+BFD09DC8 459F JR16 RA\r
+BFD09DCA 0C00 NOP\r
309: /*-----------------------------------------------------------*/\r
310: \r
311: static void prvToggleLED( uint8_t ucLED )\r
312: {\r
-BFD09878 4FF5 ADDIU SP, SP, -24
-BFD0987A CBE5 SW RA, 20(SP)
-BFD0987C CBC4 SW S8, 16(SP)
-BFD0987E 0FDD MOVE S8, SP
-BFD09880 0C44 MOVE V0, A0
-BFD09882 0018185E SB V0, 24(S8)
+BFD09878 4FF5 ADDIU SP, SP, -24\r
+BFD0987A CBE5 SW RA, 20(SP)\r
+BFD0987C CBC4 SW S8, 16(SP)\r
+BFD0987E 0FDD MOVE S8, SP\r
+BFD09880 0C44 MOVE V0, A0\r
+BFD09882 0018185E SB V0, 24(S8)\r
313: taskENTER_CRITICAL();\r
-BFD09886 33B877E8 JALS vTaskEnterCritical
-BFD09888 0C0033B8 ADDIU SP, T8, 3072
-BFD0988A 0C00 NOP
+BFD09886 33B877E8 JALS vTaskEnterCritical\r
+BFD09888 0C0033B8 ADDIU SP, T8, 3072\r
+BFD0988A 0C00 NOP\r
314: {\r
315: led_out_toggle( ucLED );\r
-BFD0988C 0018145E LBU V0, 24(S8)
-BFD09890 0C82 MOVE A0, V0
-BFD09892 42D477E8 JALS led_out_toggle
-BFD09896 0C00 NOP
+BFD0988C 0018145E LBU V0, 24(S8)\r
+BFD09890 0C82 MOVE A0, V0\r
+BFD09892 42D477E8 JALS led_out_toggle\r
+BFD09896 0C00 NOP\r
316: }\r
317: taskEXIT_CRITICAL();\r
-BFD09898 40AA77E8 JALS vTaskExitCritical
-BFD0989A 0C0040AA BNEZC T2, 0xBFD0B09E
-BFD0989C 0C00 NOP
+BFD09898 40AA77E8 JALS vTaskExitCritical\r
+BFD0989A 0C0040AA BNEZC T2, 0xBFD0B09E\r
+BFD0989C 0C00 NOP\r
318: }\r
-BFD0989E 0FBE MOVE SP, S8
-BFD098A0 4BE5 LW RA, 20(SP)
-BFD098A2 4BC4 LW S8, 16(SP)
-BFD098A4 4C0D ADDIU SP, SP, 24
-BFD098A6 459F JR16 RA
-BFD098A8 0C00 NOP
+BFD0989E 0FBE MOVE SP, S8\r
+BFD098A0 4BE5 LW RA, 20(SP)\r
+BFD098A2 4BC4 LW S8, 16(SP)\r
+BFD098A4 4C0D ADDIU SP, SP, 24\r
+BFD098A6 459F JR16 RA\r
+BFD098A8 0C00 NOP\r
319: /*-----------------------------------------------------------*/\r
320: \r
321: static void prvSetupHardware( void )\r
322: {\r
-BFD05890 4FF1 ADDIU SP, SP, -32
-BFD05892 CBE7 SW RA, 28(SP)
-BFD05894 CBC6 SW S8, 24(SP)
-BFD05896 0FDD MOVE S8, SP
+BFD05890 4FF1 ADDIU SP, SP, -32\r
+BFD05892 CBE7 SW RA, 28(SP)\r
+BFD05894 CBC6 SW S8, 24(SP)\r
+BFD05896 0FDD MOVE S8, SP\r
323: volatile uint32_t ulTemp;\r
324: \r
325: /* Interrupts are automatically re-enabled when the scheduler is started. */\r
326: __asm volatile( "di" );\r
-BFD05898 477C0000 DI ZERO
+BFD05898 477C0000 DI ZERO\r
327: \r
328: /* Enable M14K Vector Pre-fetch: CP0.IntCtl b[22]=1\r
329: IRET (interrupt chaining): b[21]=1\r
330: Enable Auto-Prolog: b[14]=1 */\r
331: ulTemp = _CP0_GET_INTCTL();\r
-BFD0589C 08FC004C MFC0 V0, IntCtl
-BFD0589E 08FC LBU S1, 12(A3)
-BFD058A0 0010F85E SW V0, 16(S8)
+BFD0589C 08FC004C MFC0 V0, IntCtl\r
+BFD0589E 08FC LBU S1, 12(A3)\r
+BFD058A0 0010F85E SW V0, 16(S8)\r
332: ulTemp |= ( 1ul << 22 ) + ( 1ul << 21 ) + ( 1ul << 14 );\r
-BFD058A4 0010FC7E LW V1, 16(S8)
-BFD058A8 006041A2 LUI V0, 0x60
-BFD058AC 40005042 ORI V0, V0, 16384
-BFD058AE 44D34000 BLTZ ZERO, 0xBFD0E258
-BFD058B0 44D3 OR16 V0, V1
-BFD058B2 0010F85E SW V0, 16(S8)
+BFD058A4 0010FC7E LW V1, 16(S8)\r
+BFD058A8 006041A2 LUI V0, 0x60\r
+BFD058AC 40005042 ORI V0, V0, 16384\r
+BFD058AE 44D34000 BLTZ ZERO, 0xBFD0E258\r
+BFD058B0 44D3 OR16 V0, V1\r
+BFD058B2 0010F85E SW V0, 16(S8)\r
333: _CP0_SET_INTCTL( ulTemp );\r
-BFD058B6 0010FC5E LW V0, 16(S8)
-BFD058B8 004C0010 INS ZERO, S0, 1, 0
-BFD058BA 0AFC004C MTC0 V0, IntCtl
-BFD058BC 0AFC LBU A1, 12(A3)
-BFD058BE 18000000 SLL ZERO, ZERO, 3
-BFD058C0 41A21800 SB ZERO, 16802(ZERO)
+BFD058B6 0010FC5E LW V0, 16(S8)\r
+BFD058B8 004C0010 INS ZERO, S0, 1, 0\r
+BFD058BA 0AFC004C MTC0 V0, IntCtl\r
+BFD058BC 0AFC LBU A1, 12(A3)\r
+BFD058BE 18000000 SLL ZERO, ZERO, 3\r
+BFD058C0 41A21800 SB ZERO, 16802(ZERO)\r
334: \r
335: /* Configure 32KHz for Switched Clock Source always ON\r
336: b[ 0 ] = XOSEL = 1\r
339: b[ 3 ] = INT_32K_VTR_PWR_WELL_EMUL = 0\r
340: b[ 4 ] = 32K_SWITCHER_CTRL = 0 */\r
341: VBAT_REGS->CLOCK_ENABLE = 0x07;\r
-BFD058C2 A00041A2 LUI V0, 0xA000
-BFD058C6 A4005042 ORI V0, V0, -23552
-BFD058CA ED87 LI V1, 7
-BFD058CC E9A2 SW V1, 8(V0)
+BFD058C2 A00041A2 LUI V0, 0xA000\r
+BFD058C6 A4005042 ORI V0, V0, -23552\r
+BFD058CA ED87 LI V1, 7\r
+BFD058CC E9A2 SW V1, 8(V0)\r
342: \r
343: ulTemp = 256;\r
-BFD058CE 01003040 ADDIU V0, ZERO, 256
+BFD058CE 01003040 ADDIU V0, ZERO, 256\r
344: while (ulTemp--)\r
-BFD058D2 CC06 B 0xBFD058E0
-BFD058D4 0010F85E SW V0, 16(S8)
-BFD058D6 0C000010 SLL ZERO, S0, 1
-BFD058E0 0010FC5E LW V0, 16(S8)
-BFD058E2 00400010 SRL ZERO, S0, 0
-BFD058E4 1B900040 SLTU V1, ZERO, V0
-BFD058E6 2DBD1B90 SB GP, 11709(S0)
-BFD058E8 2DBD ANDI V1, V1, 0xFF
-BFD058EA 6D2E ADDIU V0, V0, -1
-BFD058EC 0010F85E SW V0, 16(S8)
-BFD058F0 FFF240A3 BNEZC V1, 0xBFD058D8
-BFD058F2 41A2FFF2 LW RA, 16802(S2)
+BFD058D2 CC06 B 0xBFD058E0\r
+BFD058D4 0010F85E SW V0, 16(S8)\r
+BFD058D6 0C000010 SLL ZERO, S0, 1\r
+BFD058E0 0010FC5E LW V0, 16(S8)\r
+BFD058E2 00400010 SRL ZERO, S0, 0\r
+BFD058E4 1B900040 SLTU V1, ZERO, V0\r
+BFD058E6 2DBD1B90 SB GP, 11709(S0)\r
+BFD058E8 2DBD ANDI V1, V1, 0xFF\r
+BFD058EA 6D2E ADDIU V0, V0, -1\r
+BFD058EC 0010F85E SW V0, 16(S8)\r
+BFD058F0 FFF240A3 BNEZC V1, 0xBFD058D8\r
+BFD058F2 41A2FFF2 LW RA, 16802(S2)\r
345: {\r
346: __asm volatile( "NOP" );\r
-BFD058D8 0C00 NOP
+BFD058D8 0C00 NOP\r
347: __asm volatile( "NOP" );\r
-BFD058DA 0C00 NOP
+BFD058DA 0C00 NOP\r
348: __asm volatile( "NOP" );\r
-BFD058DC 0C00 NOP
+BFD058DC 0C00 NOP\r
349: __asm volatile( "NOP" );\r
-BFD058DE 0C00 NOP
+BFD058DE 0C00 NOP\r
350: }\r
351: \r
352: /* Disaggregate GIRQ23 & GIRQ24 for FreeRTOS. Second parameter is a bit-map\r
360: Each disaggregated interrupt handler is spaced 8-bytes apart starting at\r
361: base address for that GIRQ. */\r
362: jtvic_init( dflt_ih_table, ( JTVIC_DISAGR_BITMAP ), ( JTVIC_FLAG_DISAGR_SPACING_8 ) );\r
-BFD058F4 BFD041A2 LUI V0, 0xBFD0
-BFD058F6 3082BFD0 LDC1 F30, 12418(S0)
-BFD058F8 26F03082 ADDIU A0, V0, 9968
-BFD058FA 26F0 SLL A1, A3, 8
-BFD058FC 000141A2 LUI V0, 0x1
-BFD05900 800050A2 ORI A1, V0, -32768
-BFD05904 1B2277E8 JALS jtvic_init
-BFD05906 0CC01B22 SB T9, 3264(V0)
-BFD05908 0CC0 MOVE A2, ZERO
+BFD058F4 BFD041A2 LUI V0, 0xBFD0\r
+BFD058F6 3082BFD0 LDC1 F30, 12418(S0)\r
+BFD058F8 26F03082 ADDIU A0, V0, 9968\r
+BFD058FA 26F0 SLL A1, A3, 8\r
+BFD058FC 000141A2 LUI V0, 0x1\r
+BFD05900 800050A2 ORI A1, V0, -32768\r
+BFD05904 1B2277E8 JALS jtvic_init\r
+BFD05906 0CC01B22 SB T9, 3264(V0)\r
+BFD05908 0CC0 MOVE A2, ZERO\r
363: \r
364: /* Initialise the LEDs. */\r
365: for( ulTemp = 0; ulTemp < LED_ID_MAX; ulTemp++ )\r
-BFD0590A CC1A B 0xBFD05940
-BFD0590C 0010F81E SW ZERO, 16(S8)
-BFD05936 0010FC5E LW V0, 16(S8)
-BFD0593A 6D20 ADDIU V0, V0, 1
-BFD0593C 0010F85E SW V0, 16(S8)
-BFD05940 0010FC5E LW V0, 16(S8)
-BFD05944 0003B042 SLTIU V0, V0, 3
-BFD05948 FFE240A2 BNEZC V0, 0xBFD05910
-BFD0594A 0FBEFFE2 LW RA, 4030(V0)
+BFD0590A CC1A B 0xBFD05940\r
+BFD0590C 0010F81E SW ZERO, 16(S8)\r
+BFD05936 0010FC5E LW V0, 16(S8)\r
+BFD0593A 6D20 ADDIU V0, V0, 1\r
+BFD0593C 0010F85E SW V0, 16(S8)\r
+BFD05940 0010FC5E LW V0, 16(S8)\r
+BFD05944 0003B042 SLTIU V0, V0, 3\r
+BFD05948 FFE240A2 BNEZC V0, 0xBFD05910\r
+BFD0594A 0FBEFFE2 LW RA, 4030(V0)\r
366: {\r
367: led_sleep_en( ulTemp, ADISABLE );\r
-BFD05910 0010FC5E LW V0, 16(S8)
-BFD05914 2D2D ANDI V0, V0, 0xFF
-BFD05916 0C82 MOVE A0, V0
-BFD05918 2E8677E8 JALS led_sleep_en
-BFD0591A 2E86 ANDI A1, S0, 0x8
-BFD0591C 0CA0 MOVE A1, ZERO
+BFD05910 0010FC5E LW V0, 16(S8)\r
+BFD05914 2D2D ANDI V0, V0, 0xFF\r
+BFD05916 0C82 MOVE A0, V0\r
+BFD05918 2E8677E8 JALS led_sleep_en\r
+BFD0591A 2E86 ANDI A1, S0, 0x8\r
+BFD0591C 0CA0 MOVE A1, ZERO\r
368: led_init( ulTemp );\r
-BFD0591E 0010FC5E LW V0, 16(S8)
-BFD05922 2D2D ANDI V0, V0, 0xFF
-BFD05924 3E7E77E8 JALS led_init
-BFD05926 0C823E7E LH S3, 3202(S8)
-BFD05928 0C82 MOVE A0, V0
+BFD0591E 0010FC5E LW V0, 16(S8)\r
+BFD05922 2D2D ANDI V0, V0, 0xFF\r
+BFD05924 3E7E77E8 JALS led_init\r
+BFD05926 0C823E7E LH S3, 3202(S8)\r
+BFD05928 0C82 MOVE A0, V0\r
369: led_out_low( ulTemp );\r
-BFD0592A 0010FC5E LW V0, 16(S8)
-BFD0592E 2D2D ANDI V0, V0, 0xFF
-BFD05930 4A3077E8 JALS led_out_low
-BFD05932 4A30 LW S1, 64(SP)
-BFD05934 0C82 MOVE A0, V0
+BFD0592A 0010FC5E LW V0, 16(S8)\r
+BFD0592E 2D2D ANDI V0, V0, 0xFF\r
+BFD05930 4A3077E8 JALS led_out_low\r
+BFD05932 4A30 LW S1, 64(SP)\r
+BFD05934 0C82 MOVE A0, V0\r
370: }\r
371: }\r
-BFD0594C 0FBE MOVE SP, S8
-BFD0594E 4BE7 LW RA, 28(SP)
-BFD05950 4BC6 LW S8, 24(SP)
-BFD05952 459F JR16 RA
-BFD05954 4C11 ADDIU SP, SP, 32
+BFD0594C 0FBE MOVE SP, S8\r
+BFD0594E 4BE7 LW RA, 28(SP)\r
+BFD05950 4BC6 LW S8, 24(SP)\r
+BFD05952 459F JR16 RA\r
+BFD05954 4C11 ADDIU SP, SP, 32\r
372: /*-----------------------------------------------------------*/\r
373: \r
374: void vApplicationMallocFailedHook( void )\r
375: {\r
-BFD08900 4FF1 ADDIU SP, SP, -32
-BFD08902 CBE7 SW RA, 28(SP)
-BFD08904 CBC6 SW S8, 24(SP)
-BFD08906 0FDD MOVE S8, SP
+BFD08900 4FF1 ADDIU SP, SP, -32\r
+BFD08902 CBE7 SW RA, 28(SP)\r
+BFD08904 CBC6 SW S8, 24(SP)\r
+BFD08906 0FDD MOVE S8, SP\r
376: /* vApplicationMallocFailedHook() will only be called if\r
377: configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook\r
378: function that will get called if a call to pvPortMalloc() fails.\r
384: to query the size of free heap space that remains (although it does not\r
385: provide information on how the remaining heap might be fragmented). */\r
386: taskDISABLE_INTERRUPTS();\r
-BFD08908 4EB677E8 JALS ulPortGetCP0Status
-BFD0890A 4EB6 ADDIU S5, S5, -5
-BFD0890C 0C00 NOP
-BFD0890E 0010F85E SW V0, 16(S8)
-BFD08912 0010FC7E LW V1, 16(S8)
-BFD08916 000141A2 LUI V0, 0x1
-BFD0891A FC005042 ORI V0, V0, -1024
-BFD0891C 4493FC00 LW ZERO, 17555(ZERO)
-BFD0891E 4493 AND16 V0, V1
-BFD08920 50400042 SRL V0, V0, 10
-BFD08922 B0425040 ORI V0, ZERO, -20414
-BFD08924 0003B042 SLTIU V0, V0, 3
-BFD08928 001140E2 BEQZC V0, 0xBFD0894E
-BFD0892C 0010FC7E LW V1, 16(S8)
-BFD08930 FFFE41A2 LUI V0, 0xFFFE
-BFD08932 5042FFFE LW RA, 20546(S8)
-BFD08934 03FF5042 ORI V0, V0, 1023
-BFD08938 4493 AND16 V0, V1
-BFD0893A 0010F85E SW V0, 16(S8)
-BFD0893E 0010FC5E LW V0, 16(S8)
-BFD08942 0C005042 ORI V0, V0, 3072
-BFD08944 0C00 NOP
-BFD08946 0C82 MOVE A0, V0
-BFD08948 4EC677E8 JALS vPortSetCP0Status
-BFD0894A 4EC6 ADDIU S6, S6, 3
-BFD0894C 0C00 NOP
+BFD08908 4EB677E8 JALS ulPortGetCP0Status\r
+BFD0890A 4EB6 ADDIU S5, S5, -5\r
+BFD0890C 0C00 NOP\r
+BFD0890E 0010F85E SW V0, 16(S8)\r
+BFD08912 0010FC7E LW V1, 16(S8)\r
+BFD08916 000141A2 LUI V0, 0x1\r
+BFD0891A FC005042 ORI V0, V0, -1024\r
+BFD0891C 4493FC00 LW ZERO, 17555(ZERO)\r
+BFD0891E 4493 AND16 V0, V1\r
+BFD08920 50400042 SRL V0, V0, 10\r
+BFD08922 B0425040 ORI V0, ZERO, -20414\r
+BFD08924 0003B042 SLTIU V0, V0, 3\r
+BFD08928 001140E2 BEQZC V0, 0xBFD0894E\r
+BFD0892C 0010FC7E LW V1, 16(S8)\r
+BFD08930 FFFE41A2 LUI V0, 0xFFFE\r
+BFD08932 5042FFFE LW RA, 20546(S8)\r
+BFD08934 03FF5042 ORI V0, V0, 1023\r
+BFD08938 4493 AND16 V0, V1\r
+BFD0893A 0010F85E SW V0, 16(S8)\r
+BFD0893E 0010FC5E LW V0, 16(S8)\r
+BFD08942 0C005042 ORI V0, V0, 3072\r
+BFD08944 0C00 NOP\r
+BFD08946 0C82 MOVE A0, V0\r
+BFD08948 4EC677E8 JALS vPortSetCP0Status\r
+BFD0894A 4EC6 ADDIU S6, S6, 3\r
+BFD0894C 0C00 NOP\r
387: for( ;; );\r
-BFD0894E CFFF B 0xBFD0894E
-BFD08950 0C00 NOP
+BFD0894E CFFF B 0xBFD0894E\r
+BFD08950 0C00 NOP\r
388: }\r
389: /*-----------------------------------------------------------*/\r
390: \r
391: void vApplicationIdleHook( void )\r
392: {\r
-BFD09F04 4FB0 ADDIU SP, SP, -8
-BFD09F06 CBC1 SW S8, 4(SP)
-BFD09F08 0FDD MOVE S8, SP
+BFD09F04 4FB0 ADDIU SP, SP, -8\r
+BFD09F06 CBC1 SW S8, 4(SP)\r
+BFD09F08 0FDD MOVE S8, SP\r
393: /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set\r
394: to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle\r
395: task. It is essential that code added to this hook function never attempts\r
400: function, because it is the responsibility of the idle task to clean up\r
401: memory allocated by the kernel to any task that has since been deleted. */\r
402: }\r
-BFD09F0A 0FBE MOVE SP, S8
-BFD09F0C 4BC1 LW S8, 4(SP)
-BFD09F0E 4C05 ADDIU SP, SP, 8
-BFD09F10 459F JR16 RA
-BFD09F12 0C00 NOP
+BFD09F0A 0FBE MOVE SP, S8\r
+BFD09F0C 4BC1 LW S8, 4(SP)\r
+BFD09F0E 4C05 ADDIU SP, SP, 8\r
+BFD09F10 459F JR16 RA\r
+BFD09F12 0C00 NOP\r
403: /*-----------------------------------------------------------*/\r
404: \r
405: void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )\r
406: {\r
-BFD08444 4FF1 ADDIU SP, SP, -32
-BFD08446 CBE7 SW RA, 28(SP)
-BFD08448 CBC6 SW S8, 24(SP)
-BFD0844A 0FDD MOVE S8, SP
-BFD0844C 0020F89E SW A0, 32(S8)
-BFD08450 0024F8BE SW A1, 36(S8)
+BFD08444 4FF1 ADDIU SP, SP, -32\r
+BFD08446 CBE7 SW RA, 28(SP)\r
+BFD08448 CBC6 SW S8, 24(SP)\r
+BFD0844A 0FDD MOVE S8, SP\r
+BFD0844C 0020F89E SW A0, 32(S8)\r
+BFD08450 0024F8BE SW A1, 36(S8)\r
407: ( void ) pcTaskName;\r
408: ( void ) pxTask;\r
409: \r
412: called if a task stack overflow is detected. Note the system/interrupt\r
413: stack is not checked. */\r
414: taskDISABLE_INTERRUPTS();\r
-BFD08454 4EB677E8 JALS ulPortGetCP0Status
-BFD08456 4EB6 ADDIU S5, S5, -5
-BFD08458 0C00 NOP
-BFD0845A 0010F85E SW V0, 16(S8)
-BFD0845E 0010FC7E LW V1, 16(S8)
-BFD08462 000141A2 LUI V0, 0x1
-BFD08466 FC005042 ORI V0, V0, -1024
-BFD08468 4493FC00 LW ZERO, 17555(ZERO)
-BFD0846A 4493 AND16 V0, V1
-BFD0846C 50400042 SRL V0, V0, 10
-BFD0846E B0425040 ORI V0, ZERO, -20414
-BFD08470 0003B042 SLTIU V0, V0, 3
-BFD08474 001140E2 BEQZC V0, 0xBFD0849A
-BFD08478 0010FC7E LW V1, 16(S8)
-BFD0847C FFFE41A2 LUI V0, 0xFFFE
-BFD0847E 5042FFFE LW RA, 20546(S8)
-BFD08480 03FF5042 ORI V0, V0, 1023
-BFD08484 4493 AND16 V0, V1
-BFD08486 0010F85E SW V0, 16(S8)
-BFD0848A 0010FC5E LW V0, 16(S8)
-BFD0848E 0C005042 ORI V0, V0, 3072
-BFD08490 0C00 NOP
-BFD08492 0C82 MOVE A0, V0
-BFD08494 4EC677E8 JALS vPortSetCP0Status
-BFD08496 4EC6 ADDIU S6, S6, 3
-BFD08498 0C00 NOP
+BFD08454 4EB677E8 JALS ulPortGetCP0Status\r
+BFD08456 4EB6 ADDIU S5, S5, -5\r
+BFD08458 0C00 NOP\r
+BFD0845A 0010F85E SW V0, 16(S8)\r
+BFD0845E 0010FC7E LW V1, 16(S8)\r
+BFD08462 000141A2 LUI V0, 0x1\r
+BFD08466 FC005042 ORI V0, V0, -1024\r
+BFD08468 4493FC00 LW ZERO, 17555(ZERO)\r
+BFD0846A 4493 AND16 V0, V1\r
+BFD0846C 50400042 SRL V0, V0, 10\r
+BFD0846E B0425040 ORI V0, ZERO, -20414\r
+BFD08470 0003B042 SLTIU V0, V0, 3\r
+BFD08474 001140E2 BEQZC V0, 0xBFD0849A\r
+BFD08478 0010FC7E LW V1, 16(S8)\r
+BFD0847C FFFE41A2 LUI V0, 0xFFFE\r
+BFD0847E 5042FFFE LW RA, 20546(S8)\r
+BFD08480 03FF5042 ORI V0, V0, 1023\r
+BFD08484 4493 AND16 V0, V1\r
+BFD08486 0010F85E SW V0, 16(S8)\r
+BFD0848A 0010FC5E LW V0, 16(S8)\r
+BFD0848E 0C005042 ORI V0, V0, 3072\r
+BFD08490 0C00 NOP\r
+BFD08492 0C82 MOVE A0, V0\r
+BFD08494 4EC677E8 JALS vPortSetCP0Status\r
+BFD08496 4EC6 ADDIU S6, S6, 3\r
+BFD08498 0C00 NOP\r
415: for( ;; );\r
-BFD0849A CFFF B 0xBFD0849A
-BFD0849C 0C00 NOP
+BFD0849A CFFF B 0xBFD0849A\r
+BFD0849C 0C00 NOP\r
416: }\r
417: /*-----------------------------------------------------------*/\r
418: \r
419: void vApplicationTickHook( void )\r
420: {\r
-BFD09F14 4FB0 ADDIU SP, SP, -8
-BFD09F16 CBC1 SW S8, 4(SP)
-BFD09F18 0FDD MOVE S8, SP
+BFD09F14 4FB0 ADDIU SP, SP, -8\r
+BFD09F16 CBC1 SW S8, 4(SP)\r
+BFD09F18 0FDD MOVE S8, SP\r
421: /* This function will be called by each tick interrupt if\r
422: configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be\r
423: added here, but the tick hook is called from an interrupt context, so\r
424: code must not attempt to block, and only the interrupt safe FreeRTOS API\r
425: functions can be used (those that end in FromISR()). */\r
426: }\r
-BFD09F1A 0FBE MOVE SP, S8
-BFD09F1C 4BC1 LW S8, 4(SP)
-BFD09F1E 4C05 ADDIU SP, SP, 8
-BFD09F20 459F JR16 RA
-BFD09F22 0C00 NOP
+BFD09F1A 0FBE MOVE SP, S8\r
+BFD09F1C 4BC1 LW S8, 4(SP)\r
+BFD09F1E 4C05 ADDIU SP, SP, 8\r
+BFD09F20 459F JR16 RA\r
+BFD09F22 0C00 NOP\r
427: /*-----------------------------------------------------------*/\r
428: \r
429: void vAssertCalled( const char * pcFile, unsigned long ulLine )\r
430: {\r
-BFD096FC 4FF9 ADDIU SP, SP, -16
-BFD096FE CBC3 SW S8, 12(SP)
-BFD09700 0FDD MOVE S8, SP
-BFD09702 0010F89E SW A0, 16(S8)
-BFD09706 0014F8BE SW A1, 20(S8)
+BFD096FC 4FF9 ADDIU SP, SP, -16\r
+BFD096FE CBC3 SW S8, 12(SP)\r
+BFD09700 0FDD MOVE S8, SP\r
+BFD09702 0010F89E SW A0, 16(S8)\r
+BFD09706 0014F8BE SW A1, 20(S8)\r
431: volatile char *pcFileName;\r
432: volatile unsigned long ulLineNumber;\r
433: \r
434: /* Prevent things that are useful to view in the debugger from being\r
435: optimised away. */\r
436: pcFileName = ( char * ) pcFile;\r
-BFD0970A 0010FC5E LW V0, 16(S8)
-BFD0970E 0000F85E SW V0, 0(S8)
+BFD0970A 0010FC5E LW V0, 16(S8)\r
+BFD0970E 0000F85E SW V0, 0(S8)\r
437: ( void ) pcFileName;\r
438: ulLineNumber = ulLine;\r
-BFD09712 0014FC5E LW V0, 20(S8)
-BFD09716 0004F85E SW V0, 4(S8)
+BFD09712 0014FC5E LW V0, 20(S8)\r
+BFD09716 0004F85E SW V0, 4(S8)\r
439: \r
440: /* Set ulLineNumber to 0 in the debugger to break out of this loop and\r
441: return to the line that triggered the assert. */\r
442: while( ulLineNumber != 0 )\r
-BFD0971A CC06 B 0xBFD09728
-BFD0971C 0C00 NOP
-BFD09728 0004FC5E LW V0, 4(S8)
-BFD0972C FFF740A2 BNEZC V0, 0xBFD0971E
-BFD0972E 0FBEFFF7 LW RA, 4030(S7)
+BFD0971A CC06 B 0xBFD09728\r
+BFD0971C 0C00 NOP\r
+BFD09728 0004FC5E LW V0, 4(S8)\r
+BFD0972C FFF740A2 BNEZC V0, 0xBFD0971E\r
+BFD0972E 0FBEFFF7 LW RA, 4030(S7)\r
443: {\r
444: __asm volatile( "NOP" );\r
-BFD0971E 0C00 NOP
+BFD0971E 0C00 NOP\r
445: __asm volatile( "NOP" );\r
-BFD09720 0C00 NOP
+BFD09720 0C00 NOP\r
446: __asm volatile( "NOP" );\r
-BFD09722 0C00 NOP
+BFD09722 0C00 NOP\r
447: __asm volatile( "NOP" );\r
-BFD09724 0C00 NOP
+BFD09724 0C00 NOP\r
448: __asm volatile( "NOP" );\r
-BFD09726 0C00 NOP
+BFD09726 0C00 NOP\r
449: }\r
450: }\r
-BFD09730 0FBE MOVE SP, S8
-BFD09732 4BC3 LW S8, 12(SP)
-BFD09734 459F JR16 RA
-BFD09736 4C09 ADDIU SP, SP, 16
+BFD09730 0FBE MOVE SP, S8\r
+BFD09732 4BC3 LW S8, 12(SP)\r
+BFD09734 459F JR16 RA\r
+BFD09736 4C09 ADDIU SP, SP, 16\r
451: \r
---- C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/port_asm.S --------------
+--- C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/port_asm.S --------------\r
1: /*\r
2: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
3: All rights reserved\r
8: \r
9: FreeRTOS is free software; you can redistribute it and/or modify it under\r
10: the terms of the GNU General Public License (version 2) as published by the\r
- 11: Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+ 11: Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
12: \r
13: ***************************************************************************\r
14: >>! NOTE: The modification to the GPL is included to allow you to !<<\r
387: \r
388: \r
389: \r
---- C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/crtn.S ---
+--- C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/crtn.S ---\r
1: /*********************************************************************\r
2: *\r
3: * C Runtime Startup\r
60: addu $sp,$sp,32\r
BFD00458 03E00008 JR RA 61: j $31\r
62: \r
---- C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/crti.S ---
+--- C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/crti.S ---\r
1: /*********************************************************************\r
2: *\r
3: * C Runtime Startup\r
66: _fini:\r
BFD0044C 27BDFFE0 ADDIU SP, SP, -32 67: addu $sp,$sp,-32\r
BFD00450 AFBF0014 SW RA, 20(SP) 68: sw $31,20($sp)\r
---- C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/crt0.S ---
+--- C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/crt0.S ---\r
1: /*********************************************************************\r
2: *\r
3: * C Runtime Startup\r
613: \r
614: .end rom_launch_fw\r
615: .size rom_launch_fw, .-rom_launch_fw\r
- 616:
---- C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq24d.S ---
+ 616: \r
+--- C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq24d.S ---\r
1: /*\r
2: Copyright (C) 2014 Microchip Inc.\r
3: All rights reserved\r
82: /******************************************************************/\r
83: \r
84: \r
---- C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq23d.S ---
+--- C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq23d.S ---\r
1: /*\r
2: Copyright (C) 2014 Microchip Inc.\r
3: All rights reserved\r
161: \r
162: \r
163: \r
---- C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/exceptions/MPLAB/general_exception_ctx.S
+--- C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/exceptions/MPLAB/general_exception_ctx.S\r
1: /*********************************************************************\r
2: *\r
3: * General Exception\r
projects / freertos / commitdiff